Wafer-level chip test probe card and carrier board thereof

Abstract

A wafer-level chip test probe card and a carrier board (4) thereof. The carrier board (4) comprises: a core layer (43), a top surface layer (41) and a wrapping layer (42), wherein three sides of the core layer (43) are wrapped by the wrapping layer (42) and the remaining top surface is covered by the top surface layer (41); the core layer (43) is an alloy layer having a preset structural strength and serves as a support structure layer of the carrier board (4); the top surface layer (41) is a heat-conducting layer having a preset heat conduction property, so as to conduct heat from the outside of the probe card to the core layer (43); and the wrapping layer (42) is a heat-insulating layer having a preset heat insulation property, so as to prevent the heat from being conducted to the core layer (43) from the outside of the probe card and prevent the heat of the core layer (43) from being conducted to the outside of the probe card. The carrier board (4) is composed of multiple layers and the stacking structure is improved, so that the carrier board (4) has a good temperature adaptability range, thereby improving the temperature adaptability of the probe card, and satisfying the requirements of wafer tests at different temperatures.

Description

A wafer-level chip test probe card and its carrier board Technical Field

[0001] This application relates to the field of semiconductor testing technology, specifically to a wafer-level chip test probe card and its carrier board. Background Technology

[0002] Currently, the communications and consumer electronics industries are developing rapidly, and the market is placing higher demands on product performance, which has greatly promoted the miniaturization and integration of semiconductor devices.

[0003] Correspondingly, the testing technology for semiconductor devices has also been subject to higher requirements. The overall trend is that the density of test contacts is getting higher and higher, the test temperature is more and higher, and the probe card is required to quickly adapt to different temperatures to complete the test.

[0004] Therefore, traditional wafer test probe cards can no longer meet the above-mentioned new testing requirements, and a new probe card structure solution is needed. Summary of the Invention

[0005] In view of this, embodiments of this specification provide a wafer-level chip test probe card and its carrier board for wafer-level large-size chip testing. Compared with traditional probe cards, the carrier board can adapt to temperature changes and has a better temperature adaptation range, thus meeting the testing requirements for temperature changes in wafer testing.

[0006] The embodiments in this specification provide the following technical solutions:

[0007] This specification provides a wafer-level chip test probe card carrier board. The bottom surface of the carrier board faces the wafer under test, and the top surface of the carrier board faces the PCB board of the probe card. The bottom surface of the carrier board is used to mount the measurement head module of the probe card. The carrier board includes a core layer, a top surface layer, and a wrapping layer. The core layer is wrapped on three sides by the wrapping layer, and the remaining top surface is covered by the top surface layer. The core layer is an alloy layer with a preset structural strength to serve as the support structure layer of the carrier board. The top surface layer is a thermally conductive layer with preset thermal conductivity to conduct heat from outside the probe card to the core layer. The wrapping layer is a thermally insulating layer with preset thermal resistance to prevent heat from outside the probe card from conducting to the core layer and to prevent heat from the core layer from conducting to outside the probe card.

[0008] Preferably, the alloy material of the core layer includes any one of the following alloy materials: iron-nickel alloy, nickel-chromium alloy.

[0009] Preferably, the thickness of the kernel layer includes 1-5 mm.

[0010] Preferably, the heat-insulating material of the wrapping layer includes any one of the following heat-insulating materials: glass fiber, asbestos, rock wool, silicate, aerogel felt, and vacuum plate.

[0011] Preferably, the thickness of the wrapping layer includes 1-3 mm.

[0012] Preferably, the thermally conductive material of the top layer includes any one of the following: copper, aluminum, graphite, graphene, thermally conductive silicone, and aluminum nitride.

[0013] Preferably, the thickness of the top layer includes 0.5-1.5 mm.

[0014] This specification also provides a wafer-level chip test probe card, including: a support frame, a PCB board, a carrier board, and a test head module; wherein, the carrier board is a wafer-level chip test probe card carrier board as described in any one of this application; the test head module is mounted on the bottom surface of the carrier board; the top surface of the carrier board faces the PCB board, and the carrier board is fixedly connected to the PCB board; the PCB board is fixedly mounted on the support frame and electrically connected to the test machine to realize electrical signal transmission.

[0015] Preferably, the PCB board is a multilayer epoxy resin circuit board.

[0016] Preferably, the wafer-level chip test probe card further includes several ZIF connectors, wherein the ZIF connectors are electrically connected to the PCB board for electrical connection with the test machine to achieve electrical signal transmission.

[0017] Compared with the prior art, the beneficial effects that at least one technical solution adopted in the embodiments of this specification can achieve include at least:

[0018] By optimizing the carrier board's structure—specifically, using an alloy layer with excellent structural hardness and low thermal expansion as the core layer, surrounding the core layer with a thermally insulating layer, and covering the top surface with a thermally conductive top layer—the top layer can effectively conduct external heat to the core layer, while the outer layer effectively isolates the core layer from the outside environment. This significantly improves the carrier board's temperature adaptability and enables it to handle multi-temperature field testing requirements in a single test. Therefore, while meeting the overall rigidity requirements of the probe card, the new carrier board structure can respond and adjust promptly to the overall deformation of the probe card as it changes with temperature, resulting in higher stability of the test results from the probe card's measuring head (i.e., the probe) on the wafer-level chip.

[0019] In addition, since the carrier plate has a multi-layer structure, the deformation force adjustment needs of different probe cards can be flexibly met by changing the material stacking and layer ratio of the carrier plate, making the probe card structure more adaptable. Attached Figure Description

[0020] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 is a schematic diagram of the multi-layered stacked structure of the wafer-level chip test probe card carrier in this application;

[0022] Figure 2 is a schematic diagram of the wafer-level chip test probe card in this application. Detailed Implementation

[0023] The embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0024] The following specific examples illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. This application can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this application. It should be noted that, in the absence of conflict, the following embodiments and features in the embodiments can be combined with each other. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0025] It should be noted that various aspects of embodiments within the scope of the appended claims are described below. It will be apparent that the aspects described herein can be embodied in a wide variety of forms, and any particular structure and / or function described herein is merely illustrative. Based on this application, those skilled in the art will understand that one aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number and aspects set forth herein can be used to implement the device and / or practice the method. Additionally, this device and / or method can be implemented using structures and / or functionalities other than one or more of the aspects set forth herein.

[0026] It should also be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of this application. The drawings only show the components related to this application and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0027] Additionally, specific details are provided in the following description to facilitate a thorough understanding of the examples. However, those skilled in the art will understand that practice can be carried out without these specific details.

[0028] With technological advancements, chip performance requirements and circuit complexity are increasing, while chip size is decreasing, placing higher demands on testing tools.

[0029] In wafer-level chip testing, there is a need to test at temperatures other than room temperature (25°C). In actual semiconductor chip production, the main problem encountered in application scenarios where testing is performed at different temperatures is that due to temperature differences, the expansion / contraction rates of the wafer and the probe card are different, which can easily lead to deviations in the positions of the test contacts and probes, thus causing test failures.

[0030] In addition, probe cards typically have multiple components, such as a PCB board, a carrier board, a probe card measuring head, probes, and a fixing structure. The probes are mounted on the measuring head, the measuring head is mounted on the carrier board, the carrier board is then mounted on the PCB board, and finally, the PCB board is electrically connected to the testing machine through structural components. The probes, measuring heads, and carrier boards are components relatively close to the wafer under test. Although the temperature characteristics of these components are not entirely the same, and the overall heating conditions of the probe card are complex, they can be estimated based on a Gaussian temperature distribution. Furthermore, the probes can be made to have temperature deformation characteristics close to those of the wafer through material selection. Currently, the most difficult aspect to approximate is the matching problem between the probes and the wafer caused by the temperature change characteristics of the carrier board.

[0031] Furthermore, while the temperature of the test wafer is relatively uniform, the temperature difference at the edge of the wafer is significant in the testing of large-size wafers, which can further deteriorate the compatibility between the probe card and the wafer.

[0032] Therefore, there is an urgent need for a new probe card structure to improve the matching performance between the probe tip of the probe card and the test contacts on the wafer-level chip during large-size testing.

[0033] Based on this, the embodiments of this specification propose a carrier board structure scheme: as shown in Figure 1, the carrier board adopts a multi-layer structure: a top surface layer, a core layer, and a wrapping layer. The wrapping layer covers the core layer on three sides to provide internal and external temperature isolation, and conducts heat between the core layer and the top surface layer. Therefore, the core layer can only transfer heat to the outside through the top surface layer. Thus, when the core layer serves as the supporting structure of the overall carrier board structure, its temperature change can only be achieved through the top surface layer to exchange heat with the external environment. Therefore, the temperature change of the core layer as a supporting structure will not be too drastic, resulting in a small overall displacement change of the measuring head mounted on the carrier board. As a result, the probe on the measuring head can be well matched with the measurement points of the wafer-level chip, which is beneficial for wafer testing at different temperatures.

[0034] The technical solutions provided by the various embodiments of this application are described below with reference to the accompanying drawings.

[0035] A probe card is typically a printed circuit board with probes. The printed circuit board is connected to the test machine to form a complete test environment, enabling the testing of electrical parameters and performance of integrated circuits at the wafer level. The probes make physical and electrical contact with the wafer under test to achieve electrical performance testing.

[0036] As shown in Figure 2, a probe card is installed in a measuring head module 5. The measuring head module 5 is installed on a carrier board 4. The carrier board 4 is connected to a PCB board 3. The PCB board 3 is finally electrically connected to the testing machine, for example, through a cable, connector 1, etc., to achieve electrical signal connection and communication with the testing machine.

[0037] In wafer testing, the wafer is subjected to a test temperature through the wafer stage, and the probe card is placed in the corresponding temperature environment. The ambient temperature is conducted to the probe to stabilize the probe temperature. If the deformation of the carrier board 4, the measuring head module 5, etc., in response to the external temperature change is too large, it can easily cause mismatch between the probe and the wafer, thus affecting the test.

[0038] Referring to Figure 1, this application provides a wafer-level chip test probe card carrier board. The bottom surface of the carrier board 4 faces the wafer to be tested (not shown in the figure), the top surface of the carrier board 4 faces the PCB board 3 of the probe card, and the bottom surface of the carrier board 4 is used to mount the measurement head module 5 of the probe card.

[0039] In practice, to improve the temperature adaptability range of the carrier plate, the carrier plate 4 adopts a multi-layered stacked structure, which includes: a top layer 41, a core layer 43, and a wrapping layer 42; wherein, three sides of the core layer 43 are wrapped by the wrapping layer 42, and the remaining top surface is covered by the top layer 41. In this case, the core layer 43 is preferably an alloy layer with a preset structural strength, so as to serve as a structural layer for overall support of the carrier plate 4; the top layer 41 is a thermally conductive layer with preset thermal conductivity characteristics, so as to quickly, timely and accurately conduct the external heat of the probe card to the core layer 43, and / or conduct the heat of the core layer 43 to the outside, realize the heat exchange between the core layer 43 and the external environment, and ensure that the core layer 43 can follow the temperature change; the wrapping layer 42 is a thermally insulating layer with preset thermal insulation characteristics, so as to block the heat of the external environment of the probe card from conducting to the core layer 43 and the heat of the core layer 43 from conducting to the outside of the probe card.

[0040] Therefore, by wrapping the core layer 43 with the encapsulation layer 42 and covering the top surface of the core layer 43 with the top surface layer 41, and ensuring that the core layer 43 can meet the overall rigidity requirements of the probe card, the carrier plate 4 can have good temperature adaptability characteristics, which can adjust for the overall deformation of the probe card, thereby ensuring that the test results of the probe card on the wafer have higher stability.

[0041] In addition, with the carrier plate adopting a multi-layered structure, the deformation force requirements of the probe card can be flexibly met by changing the material stacking and material ratio of the carrier plate (such as material selection, thickness optimization, etc.), so that the probe card structure has a wider range of temperature adaptability.

[0042] In some embodiments, since the core layer 43 is the core inner layer of the carrier plate 4 and needs to have good structural support to provide good support performance to the carrier plate 4, the alloy material of the core layer 43 can be optimized to not only ensure the structural support performance of the carrier plate 4, but also improve the temperature characteristics of the carrier plate 4, better meet the temperature adaptability of the carrier plate 4, and make the carrier plate 4 have better temperature adaptability characteristics.

[0043] In practice, the alloy layer material of the core layer 43 can preferably be any of the following alloy materials: iron-nickel alloy, nickel-chromium alloy, etc.

[0044] Among them, iron-nickel alloy is an alloy material with excellent performance. Its chemical composition is mainly composed of iron and nickel. This alloy has a low coefficient of thermal expansion and good thermal conductivity. For example, the coefficient of thermal expansion is 1.1×10-6 / K (in the range of 20-100℃) and the thermal conductivity is 12.8W / (m•K) (at 20℃), which is very suitable as the inner support structure of the carrier plate 4.

[0045] It should be noted that both iron-nickel alloys and nickel-chromium alloys have multiple models. Therefore, when selecting, you can choose the specific model based on the application cost, environment, etc. There are no specific restrictions here.

[0046] In addition, nickel-chromium alloys can be high-resistance heating alloys (high-nickel and iron-chromium-aluminum), high-temperature alloys, precision alloys, heat-resistant alloys, special alloys, stainless steel, etc., without specific limitations.

[0047] In some embodiments, for the multi-layered structure of the carrier plate 4, the thickness of the core layer is preferably selected in the range of 1-5mm, so that the core layer 43 has a certain supporting strength and the thickness is also moderate, which is beneficial to the strength design of the overall structure of the probe card. In some examples, the thickness can be preferably 2.5mm.

[0048] In some embodiments, since the wrapping layer 42 is used to block heat conduction between the core layer 43 and the outside, the temperature adaptability of the carrier plate 4 can also be improved by selecting a better material for the wrapping layer 42. In practice, the heat-insulating material of the wrapping layer 42 includes any one of the following heat-insulating materials: glass fiber, asbestos, rock wool, silicate, aerogel felt, and vacuum plate.

[0049] It should be noted that different insulation materials have different shapes and insulation performance, so the appropriate material can be selected according to different application scenarios. No specific restrictions are made here.

[0050] In some embodiments, the temperature range adaptability of the carrier plate 4 can also be improved by optimizing the thickness parameters of the wrapping layer 42 to enhance its barrier function. In practice, the thickness of the wrapping layer 42 is preferably selected in the range of 1-3 mm, so that the wrapping layer 42 can not only effectively wrap the core layer 43, but also meet the barrier performance requirements, and the thickness is also moderate. In some examples, the thickness can be preferably 1.5 mm.

[0051] In some embodiments, the top layer 41 is a thermally conductive layer, and the material of the top layer 41 is preferably a sheet material with thermal conductivity. In practice, the thermally conductive material of the top layer 41 includes any one of the following thermally conductive materials: copper, aluminum, graphite, graphene, thermally conductive silicone, and aluminum nitride.

[0052] It should be noted that the appropriate thermal conductive material can be selected according to different application scenarios. For example, for applications with high thermal conductivity requirements, materials with better thermal conductivity such as graphene can be selected. For applications with lower application costs, materials such as aluminum and copper can be selected. No specific restrictions are made here.

[0053] In some embodiments, the thermal conductivity of the top layer 41 can also be improved by optimizing its thickness parameters to enhance the temperature range adaptability of the carrier plate 4. In practice, the preferred thickness range of the top layer is 0.5-1.5 mm, so that the top layer 41 can not only conduct heat well to the core layer 43, but also has a moderate thickness. In some examples, a thickness of 1.0 mm is preferred.

[0054] In summary, targeted improvements were made to each layer of the carrier plate 4, enabling it to have a better temperature range. This allows the carrier plate 4 to provide better temperature adaptability for the probe card, ensuring that the probes of the probe card and the wafer under test can still be well matched at different temperatures. This guarantees the test results and avoids problems such as test failures caused by mismatch due to temperature deformation during testing.

[0055] Based on the same inventive concept, this application can provide a wafer-level chip test probe card.

[0056] Referring to Figure 2, a wafer-level chip test probe card may include: a support frame 2, a PCB board 3, a carrier board 4, and a test head module 5; wherein, the carrier board 4 is the wafer-level chip test probe card carrier board as described in any of the foregoing examples of this application.

[0057] As shown in Figure 2, in this probe card, the test head module 5 is installed on the bottom surface of the carrier board 4; the top surface of the carrier board 4 faces the PCB board 3, and the carrier board 4 is fixedly connected to the PCB board 3, and the PCB board 3 is fixedly installed on the support frame 2, thereby electrically connecting the probe card and the test machine (not shown in the figure) through the support frame 2, thereby realizing the electrical signal connection and transmission between the probe card and the test machine.

[0058] In the probe card structure shown in Figure 2, the support frame 2 is the basic rigid structure of the probe card; the PCB board 3 is used to carry various electronic components and contains transmission lines for signal and power interaction, serving as the concentration point for electrical signals in the probe card; the carrier board 4 is the basic supporting structure for mounting the test head module 5, providing overall deformation and adjustment capabilities for the test head module 5; the test head module 5 (with probes installed) is mounted on the probe card and used to contact the chip under test, and is a key structure for acquiring test data. It should be noted that the PCB board can perform simple electrical signal conversion processing (such as weak signal amplification, simple filtering, etc.), while complex signal processing can be performed by the testing machine to simplify the probe card design.

[0059] By adopting the new structure of carrier plate 4, the probe card has better temperature adaptability. When the probe card performs different temperature tests on the wafer, the probe can adapt to temperature changes and accurately match the wafer, thus successfully completing the test and ensuring the stability of the probe card's test results.

[0060] In some implementations, for PCBs where electrical signals are concentrated, a multilayer epoxy resin circuit board can be preferred as the core of the PCB, thereby enabling the exchange and processing of electrical signals acquired by tens of thousands of probe cards through the multilayer epoxy resin circuit board.

[0061] In some implementations, electrical connectors can be used for the electrical signal connection and transmission between the probe card and the tester. Considering the plug-in connection between the probe card and the tester, ZIF connectors, which are small in size and require zero insertion force, are preferred.

[0062] Referring to Figure 2, the wafer-level chip test probe card also includes several ZIF connectors 1, which are electrically connected to the PCB board for electrical connection with the test equipment to achieve electrical signal transmission. The ZIF (Zero Insertion Force) connector is a connector with zero insertion force. By using ZIF connectors, the electrical connection between the probe card and the test equipment can be achieved through connector insertion and removal, and the ZIF connectors do not require excessive additional force, which is beneficial for the connection between the probe card and the test equipment. Furthermore, the probe card can adapt to different temperatures for ZIF connector connection and port operation.

[0063] In this specification, the same or similar parts between the various embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the descriptions of the embodiments described later are relatively simple, and relevant parts can be referred to the descriptions of the foregoing embodiments.

[0064] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A wafer-level chip test probe card carrier board, characterized in that, The bottom surface of the carrier plate faces the wafer to be tested, and the top surface of the carrier plate faces the PCB board of the probe card. The bottom surface of the carrier plate is used to mount the measurement head module of the probe card. The carrier plate includes a core layer, a top surface layer, and a wrapping layer. The core layer is wrapped on three sides by the wrapping layer and the remaining top surface layer is covered by the top surface layer. The core layer is an alloy layer with a preset structural strength to serve as the supporting structural layer of the carrier plate. The top surface layer is a thermally conductive layer with preset thermal conductivity to conduct heat from outside the probe card to the core layer. The wrapping layer is a thermally insulating layer with preset thermal resistance to block heat from outside the probe card from conducting to the core layer and to block heat from the core layer from conducting to outside the probe card.

2. The wafer-level chip test probe carrier board according to claim 1, characterized in that, The alloy material of the core layer includes any one of the following alloy materials: iron-nickel alloy, nickel-chromium alloy.

3. The wafer-level chip test probe carrier board according to claim 2, characterized in that, The thickness of the core layer ranges from 1 to 5 mm.

4. The wafer-level chip test probe carrier board according to claim 1, characterized in that, The heat-insulating material of the wrapping layer includes any one of the following: glass fiber, asbestos, rock wool, silicate, aerogel felt, and vacuum board.

5. The wafer-level chip test probe carrier board according to claim 4, characterized in that, The thickness of the wrapping layer includes 1-3 mm.

6. The wafer-level chip test probe carrier board according to claim 1, characterized in that, The thermally conductive material of the top layer includes any one of the following: copper, aluminum, graphite, graphene, thermally conductive silicone, and aluminum nitride.

7. The wafer-level chip test probe carrier board according to claim 6, characterized in that, The thickness of the top layer includes 0.5-1.5 mm.

8. A wafer-level chip test probe card, characterized in that, include: The device comprises a support frame, a PCB board, a carrier board, and a test head module; wherein the carrier board is a wafer-level chip test probe card carrier board as described in any one of claims 1-7; the test head module is mounted on the bottom surface of the carrier board; the top surface of the carrier board faces the PCB board, and the carrier board is fixedly connected to the PCB board; the PCB board is fixedly mounted on the support frame and electrically connected to the test machine to achieve electrical signal transmission.

9. The wafer-level chip test probe card according to claim 8, characterized in that, The PCB board is a multilayer epoxy resin circuit board.

10. The wafer-level chip test probe card according to claim 8, characterized in that, The wafer-level chip test probe card also includes several ZIF connectors, wherein the ZIF connectors are electrically connected to the PCB board for electrical connection with the test machine to achieve electrical signal transmission.

Images