Transistor device and preparation method therefor, and display substrate

Abstract

A transistor device and a preparation method therefor, and a display substrate. The transistor device is arranged on a base (100). The transistor device comprises a gate electrode (201), a gate insulating layer (300), an active layer (202), a first electrode (203) and a second electrode (204), wherein the first electrode (203) and the second electrode (204) are arranged on the side of the active layer (202) and the gate electrode (201) away from the base (100), and the gate insulating layer (300) is arranged between the active layer (202) and the gate electrode (201). The gate insulating layer (300) comprises a first insulating layer (301) and a second insulating layer (302) that are stacked on the base, wherein one of the first insulating layer (301) and the second insulating layer (302) is provided with a via hole (VV), and the orthographic projection of the via hole (VV) on the base (100) at least partially overlaps with the orthographic projection of the active layer (202) on the base (100).

Description

Transistor device and preparation method thereof, display substrate

[0001] The present application claims priority to PCT International Application No. PCT / CN2024 / 108632, filed on July 30, 2024, entitled “Display substrate and preparation method thereof”, and to Chinese Invention Patent Application No. 202511038242.4, filed on July 25, 2025, entitled “Transistor device and preparation method thereof, display substrate”, the contents of which are understood to be incorporated herein by reference. TECHNICAL FIELD

[0002] The present disclosure relates to, but is not limited to, the technical field of display, in particular to a transistor device and preparation method thereof, display substrate. BACKGROUND

[0003] In recent years, thin film transistor flat panel displays have been widely used in watches, mobile phones, tablets, desktop computers, vehicle displays, industrial Internet of Things displays, televisions and other fields of social production and life. With the expansion of the application field of flat panel displays, display technologies with excellent image quality, high smoothness, high touch performance, high refresh rate and high touch frequency have become the highest point of display industry. SUMMARY

[0004] The following is a summary of the subject matter of the detailed description of the present disclosure. This summary is not intended to limit the scope of protection of the claims.

[0005] The present disclosure provides a transistor device and preparation method thereof, display substrate.

[0006] In a first aspect, the present disclosure provides a transistor device, disposed on a substrate, comprising: a gate electrode, a gate insulating layer, an active layer, a first electrode and a second electrode, the first electrode and the second electrode are disposed on the side of the active layer and the gate electrode away from the substrate, the gate insulating layer is disposed between the active layer and the gate electrode;

[0007] The gate insulating layer comprises: a first insulating layer and a second insulating layer which are stacked on the substrate, one of the first insulating layer and the second insulating layer is provided with a via hole;

[0008] The orthographic projection of the via hole on the substrate at least partially overlaps the orthographic projection of the active layer on the substrate.

[0009] In a second aspect, the present disclosure further provides a display substrate, comprising: a plurality of the above transistor devices.

[0010] In a third aspect, the present disclosure also provides a method for manufacturing a transistor device, configured to manufacture the transistor device as described above, the method comprising:

[0011] forming a gate electrode of the transistor device on the substrate;

[0012] forming a gate insulating layer and an active layer of the transistor device on the gate electrode, the gate insulating layer comprising: a first insulating layer and a second insulating layer which are stacked on the substrate, one of the first insulating layer and the second insulating layer being provided with a via hole; a normal projection of the via hole on the substrate at least partially overlapping a normal projection of the active layer on the substrate;

[0013] forming a first electrode and a second electrode on the active layer;

[0014] the forming of the gate insulating layer and the active layer of the transistor device on the gate electrode comprises:

[0015] forming a first insulating layer on the gate electrode, the first insulating layer being provided with a via hole;

[0016] forming a second insulating layer on the first insulating layer;

[0017] forming a raw semiconductor layer on the second insulating layer, the raw semiconductor layer comprising: a first active layer and a third active layer;

[0018] forming a first electrode, a second electrode and an active layer on the raw semiconductor layer, the active layer comprising: a first active layer and a second active layer.

[0019] Other aspects can become apparent from a review of the drawings and detailed description.

[0020] SUMMARY

[0021] The accompanying drawings are included to provide a further understanding of the present application, and constitute a part of this specification. The drawings illustrate embodiments of the present application and, together with the description, serve to explain the principles of the present application. The present application should not be limited to the embodiments of the drawings.

[0022] FIG. 1 is a schematic structural diagram of a display substrate according to an embodiment of the present disclosure;

[0023] FIG. 2 is a schematic structural diagram of part of the film layers according to FIG. 1;

[0024] FIG. 3 is a schematic structural diagram of a display substrate according to another embodiment of the present disclosure;

[0025] FIG. 4 is a schematic structural diagram of part of the film layers according to FIG. 3;

[0026] FIG. 5 is a top view of a transistor device according to FIG. 1 and FIG. 3;

[0027] FIG. 6 is a graph of gate insulating layer thickness versus Ion normalization factor;

[0028] FIG. 7 is a graph of voltage Vg of the gate electrode versus current Id flowing through the source electrode for different gate insulating layer thicknesses;

[0029] FIG. 8 is a top view of a transistor device;

[0030] FIG. 9 is a cross-sectional view of FIG. 8 along A-A;

[0031] FIG. 10 is a cross-sectional view of FIG. 8 along B-B;

[0032] FIG. 11 is a schematic view of a structure of a display substrate;

[0033] FIG. 12 is a schematic view of another structure of a display substrate;

[0034] FIG. 13 is a schematic view of FIG. 11 after forming a gate electrode;

[0035] FIG. 14 is a schematic view of FIG. 11 after forming a gate insulating layer;

[0036] FIG. 15 is a schematic view of FIG. 11 after forming an original semiconductor layer;

[0037] FIG. 16 is a schematic view of FIG. 11 after forming a first electrode and a second electrode;

[0038] FIG. 17 is a schematic view of FIG. 11 after forming a passivation layer;

[0039] FIG. 18 is a schematic view of FIG. 12 after forming a gate insulating layer;

[0040] FIG. 19 is a schematic view of FIG. 12 after forming an original semiconductor layer;

[0041] FIG. 20 is a schematic view of FIG. 12 after forming a first electrode and a second electrode;

[0042] FIG. 21 is a schematic view of FIG. 12 after forming a passivation layer;

[0043] FIG. 22A is a cross-sectional schematic view of a transistor device according to an embodiment of the present disclosure;

[0044] FIG. 22B is a partial cross-sectional view of FIG. 22A;

[0045] FIGS. 23a to 23e are schematic views of forming the transistor device according to FIG. 22A;

[0046] FIG. 24 is a top view of a transistor device;

[0047] FIG. 25 is a top view of a transistor device;

[0048] FIG. 26 is a top view of a transistor device;

[0049] Figure 27 is a top view four of a transistor device;

[0050] Figure 28 is a top view five of a transistor device;

[0051] Figure 29 is a top view six of a transistor device,

[0052] Figure 30 is a top view seven of a transistor device;

[0053] Figure 31 is a top view eight of a transistor device;

[0054] Figure 32 is a top view nine of a transistor device;

[0055] Figure 33 is a top view ten of a transistor device;

[0056] Figure 34 is a top view eleven of a transistor device;

[0057] Figure 35 is a top view twelve of a transistor device;

[0058] Figure 36 is a top view thirteen of a transistor device;

[0059] Figure 37 is a top view fourteen of a transistor device;

[0060] Figure 38 is a top view fifteen of a transistor device;

[0061] Figure 39 is a top view sixteen of a transistor device;

[0062] Figure 40 is a top view seventeen of a transistor device;

[0063] Figure 41 is a top view eighteen of a transistor device;

[0064] Figure 42 is a top view nineteen of a transistor device;

[0065] Figure 43 is a top view twenty of a transistor device;

[0066] Figure 44 is a top view twenty-one of a transistor device;

[0067] Figure 45 is a top view twenty-two of a transistor device;

[0068] Figure 46 is a top view twenty-three of a transistor device;

[0069] Figure 47 is a top view twenty-four of a transistor device;

[0070] Figure 48 is a top view twenty-five of a transistor device;

[0071] Figure 49 is a top view twenty-six of a transistor device;

[0072] Figure 50 is a top view twenty-seven of a transistor device;

[0073] Fig. 51 is a plan view of a transistor device twenty-eight;

[0074] Fig. 52 is a plan view of a transistor device twenty-nine;

[0075] Fig. 53 is a plan view of a transistor device thirty;

[0076] Fig. 54 is a plan view of a transistor device thirty-one;

[0077] Fig. 55 is a plan view of another transistor device;

[0078] Fig. 56 is a structural schematic diagram of a display substrate provided by an embodiment of the present disclosure;

[0079] Fig. 57 is a partial connection schematic diagram of the display substrate provided by Fig. 56;

[0080] Fig. 58 is an equivalent circuit diagram of at least one stage of a shift register;

[0081] Fig. 59 is a structural schematic diagram of a shift register provided by an embodiment of the present disclosure;

[0082] Fig. 60 is a plan view of a light-sensing switch device one;

[0083] Fig. 61 is a plan view of a light-sensing switch device two;

[0084] Fig. 62 is a structural schematic diagram of a partial switch device located on a data side;

[0085] Fig. 63 is a structural schematic diagram of a partial switch device located on a non-data side;

[0086] Fig. 64 is a structural schematic diagram of a partial switch device of an electrostatic discharge circuit;

[0087] Fig. 65 is a flow schematic diagram of a preparation method of a transistor device provided by an embodiment of the present disclosure.

[0088] Detailed description

[0089] In order to make the objects, technical solutions and advantages of the present disclosure clearer, the following will be used to specifically describe the embodiments of the present disclosure with reference to the drawings. It should be noted that the embodiments can be implemented in a variety of different forms. Those skilled in the art can easily understand that the manners and contents can be changed into various forms without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. The embodiments in the present disclosure and the features in the embodiments can be combined with each other in any manner without conflict. In order to keep the following description of the embodiments of the present disclosure clear and brief, the detailed description of some known functions and known components is omitted. The drawings of the embodiments of the present disclosure only involve the structures related to the embodiments of the present disclosure, and other structures can be referred to the general design.

[0090] The proportions of the drawings in the present disclosure can be used as a reference in the actual process, but are not limited thereto. For example, the width-length ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are also not limited to the number shown in the drawings. The drawings described in the present disclosure are only schematic structural diagrams, and one embodiment of the present disclosure is not limited to the shapes or values shown in the drawings.

[0091] In the present specification, ordinal numbers such as "first", "second", "third", and the like are provided to avoid confusion of components, and are not intended to be limiting in terms of number.

[0092] In the present specification, for the convenience of description, words indicating the orientation or positional relationship such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like are used to describe the positional relationship of the components with reference to the drawings, and are only for the convenience of description of the present specification and simplification of the description, and are not intended to indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present disclosure. The positional relationship of the components is appropriately changed according to the direction of describing each component. Therefore, it is not limited to the words described in the specification, and can be appropriately changed according to the situation.

[0093] In the present specification, unless specifically defined and limited otherwise, the terms "mount", "connected", "connection" should be interpreted broadly. For example, it can be fixedly connected, or detachably connected, or integrally connected; it can be mechanically connected, or electrically connected; it can be directly connected, or indirectly connected through an intermediate piece, or the communication inside two elements. Those skilled in the art can understand the specific meaning of the above terms in the present disclosure according to the specific circumstances.

[0094] In this specification, a transistor means an element including at least three terminals of a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between the drain electrode (a drain electrode terminal, a drain region, or a drain electrode) and the source electrode (a source electrode terminal, a source region, or a source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that, in this specification, the channel region means a region where current flows mainly.

[0095] In this specification, the first electrode can be a drain electrode and the second electrode can be a source electrode, or the first electrode can be a source electrode and the second electrode can be a drain electrode. In the case of using a transistor having opposite polarity or in the case of changing the direction of current in circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Thus, in this specification, the "source electrode" and the "drain electrode" can be interchanged with each other.

[0096] In this specification, "electrically connected" includes the case where components are connected through an element having some function of electricity. The element having some function of electricity is not particularly limited as long as electric signals can be transmitted and received between components to be connected. Examples of the element having some function of electricity include not only an electrode and a wiring but also a switching element such as a transistor, a resistor, an inductor, a capacitor, and another element having some function.

[0097] In this specification, "parallel" means a state where an angle formed between two straight lines is greater than or equal to -10° and less than or equal to 10°, and thus includes a state where the angle is greater than or equal to -5° and less than or equal to 5°. In addition, "perpendicular" means a state where an angle formed between two straight lines is greater than or equal to 80° and less than or equal to 100°, and thus includes a state where the angle is greater than or equal to 85° and less than or equal to 95°.

[0098] In this specification, a "film" and a "layer" can be interchanged with each other. For example, a "conductive layer" can be replaced with a "conductive film". Similarly, an "insulating film" can be replaced with an "insulating layer".

[0099] In this specification, "formation in the same layer" means that two (or more) structures are formed by patterning in the same process, and the materials thereof can be the same or different. For example, the materials of precursors used for forming the two (or more) structures in the same layer are the same, and the materials of the formed structures can be the same or different.

[0100] In this specification, a triangle, a rectangle, a trapezoid, a pentagon, or a hexagon is not necessarily a strict one, and can be an approximate triangle, rectangle, trapezoid, pentagon, or hexagon. There can be some small deformation due to a tolerance, a rounded corner, a rounded side, or deformation.

[0101] The transistor is limited by its own semiconductor characteristics, i.e. the limitation of carrier mobility, so that the on-current of the transistor is difficult to be further improved, thereby limiting the improvement of the refresh frequency of the display product.

[0102] To this end, the present disclosure provides a transistor device.

[0103] FIG. 1 is a structural schematic diagram of a display substrate according to an embodiment of the present disclosure, FIG. 2 is a structural schematic diagram of part of a film layer according to FIG. 1, FIG. 3 is a structural schematic diagram of a display substrate according to an embodiment of the present disclosure, and FIG. 4 is a structural schematic diagram of part of a film layer according to FIG. 3. As shown in FIGS. 1 to 4, the display substrate provided by the embodiment of the present disclosure can include a substrate and a transistor device disposed on the substrate, and the transistor device can include a gate electrode 11, a gate insulating layer 21 and an active layer 12 which are sequentially stacked on the substrate 10. The second direction Y in FIGS. 1 to 4 is the direction in which the gate electrode, the gate insulating layer and the active layer are stacked, and the first direction X can be the extension direction of the active layer, and the first direction X intersects the second direction Y.

[0104] As shown in FIGS. 1 to 4, the gate insulating layer 21 is provided with a groove structure 1 on the side away from the substrate 10, at least part of the active layer 12 is disposed in the groove structure 1, and at least two boundaries of the active layer 12 have a preset interval with the corresponding boundaries of the groove structure. That is, the orthographic projection of the active layer 12 on the substrate 10 is located in the orthographic projection range of the groove structure 1 on the substrate 10, and the width of the longitudinal section of the active layer 12 falls entirely into the groove structure 1.

[0105] In the exemplary embodiment, the substrate 10 can be a rigid substrate or a flexible substrate, wherein the rigid substrate can be, but is not limited to, one or more of glass, conductive foil; the flexible substrate can be, but is not limited to, one or more of polyethylene terephthalate, ethylene terephthalate, polyether ether ketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, textile fibers.

[0106] In the exemplary embodiment, the transistor device in the present disclosure is a bottom gate structure.

[0107] In the exemplary embodiment, the gate electrode 11 can adopt a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or an alloy material of the above-mentioned metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), which can be a single-layer structure or a multi-layer composite structure, such as Mo / Cu / Mo, etc. For example, the gate electrode can adopt Al / Mo or MoNb / Cu.

[0108] In an exemplary embodiment, the gate insulating layer 21 can be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and can be a single layer, multiple layers, or a composite layer.

[0109] In an exemplary embodiment, the material of the active layer can include one or more of amorphous silicon (a-Si), low temperature polysilicon (LTPS), and metal oxide. Among them, the metal oxide layer can be made of an oxide containing indium and tin, an oxide containing tungsten and indium, an oxide containing tungsten, indium and zinc, an oxide containing titanium and indium, an oxide containing titanium, indium and tin, an oxide containing indium and zinc, an oxide containing silicon, indium and tin, or an oxide containing indium or gallium and zinc.

[0110] In some embodiments, the material of the active layer can be M1OaNb, where M1 is a single metal or a combination of multiple metals, a > 0, and b ≥ 0, O represents an oxygen element, and N represents a nitrogen element, that is, the material of the active layer is a metal oxide material or a metal oxynitride material. Suitable metal oxide materials include, but are not limited to, one or more of indium gallium zinc oxide (IGZO), indium gallium tin oxide (IGTO), indium tin zinc oxide (ITZO), indium gallium oxide (IGO), indium gallium zinc tin oxide (IGZTO), indium zinc oxide (IZO), zinc tin oxide (ZTO), In-free OS, rare earth doped oxide (Ln-OS, such as rare earth element doped IGZO / IZO), zinc oxide (ZnO), gallium oxide (GaO), indium oxide (InO), HfInZnO (HIZO), ZnO:F, In2O3:Sn, In2O3:Mo, Cd2SnO4, ZnO:Al, TiO2:Nb, and Cd-Sn-O.

[0111] Suitable metal oxynitride materials include, but are not limited to, zinc oxynitride, indium oxynitride, gallium oxynitride, tin oxynitride, cadmium oxynitride, aluminum oxynitride, germanium oxynitride, titanium oxynitride, silicon oxynitride, or a combination thereof. In one example, the material of the channel region CH1 / CH2 / CH3 includes indium gallium zinc oxide (IGZO). The material of the active layer can be in an amorphous, partially crystalline, single crystalline, or polycrystalline state, and can be a single layer or a multi-layer structure.

[0112] In an exemplary embodiment, the transistor device further includes a first electrode 13 and a second electrode 14 located on the side of the active layer 12 away from the substrate 10, and the first electrode 13 and the second electrode 14 are respectively connected to the active layer 12. In an exemplary embodiment, the first electrode 13 can be one of a source electrode and a drain electrode, and the second electrode 14 can be the other of the source electrode and the drain electrode.

[0113] In the example embodiments, the first electrode 13 and the second electrode 14 can adopt a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), niobium (Nb), neodymium (Nd), nickel (Ni), and molybdenum (Mo), or an alloy material composed of at least two of the above-mentioned metals, such as an aluminum neodymium alloy (AlNd), a titanium aluminum alloy (TiAl), a molybdenum nickel titanium alloy (Mo-Ni-Ti, MTD), or a molybdenum niobium alloy (MoNb), and can also be a single-layer structure or a multi-layer composite structure, such as Mo / Cu / Mo, etc. For example, the first electrode 13 and the second electrode 14 can adopt Mo / Al / Mo, MoNb / Cu, MTD / Cu / MTD, Cu / MTD.

[0114] In the example embodiments, the on-current Ion of the transistor satisfies the following formula,

[0115] Ion = (W / L) * C * [(Vgs-Vth) * Vds-0.5 * (Vds)2]

[0116] wherein W is the width of the channel region of the active layer, L is the length of the channel region of the active layer, C is the parasitic capacitance between the channel region of the active layer and the gate electrode, Vgs is the voltage difference between the gate electrode and the source electrode of the transistor, Vds is the voltage difference between the drain electrode and the source electrode of the transistor, and Vth is the threshold voltage of the transistor. As can be seen from the above formula, the on-current Ion of the transistor depends on the parameters C, W, L, Vgs, Vth, and Vds.

[0117] The present disclosure reduces the thickness of the gate insulating layer that overlaps with the active layer by providing a recess structure on the side of the gate insulating layer away from the substrate, arranging at least part of the active layer in the recess structure, and arranging at least two boundaries of the active layer to have a preset spacing with the corresponding boundaries of the recess structure, increases the capacitance value of the parasitic capacitance between the channel region of the active layer and the gate electrode, increases the on-current of the transistor device, and thus can improve the refresh frequency of the display product.

[0118] In the example embodiments, as shown in FIGS. 2 and 4, the gate insulating layer 21 includes a first region R1 and a second region R2, and the second region R2 is all regions except the first region R1, and the second region R2 is arranged around at least one side of the first region R1.

[0119] In the example embodiments, as shown in FIGS. 2 and 4, the recess structure 1 is located in the first region R1, and the thickness H1 of the gate insulating layer 21 located in the first region R1 is less than the thickness H2 of the gate insulating layer 21 located in the second region R2.

[0120] In an example embodiment, FIG. 5 is a top view of the transistor device provided in FIGS. 1 and 3. As shown in FIG. 5, the orthogonal projection of the recess structure 1 on the substrate 10 is within the orthogonal projection of the gate electrode 11 on the substrate 10.

[0121] In an example embodiment, the shape of the cross section of the recess structure in the direction parallel to the substrate can be circular, square, rectangular, or other shapes, and the present disclosure does not make any limitation in this regard. FIG. 5 is an example in which the shape of the cross section of the recess structure in the direction parallel to the substrate is square.

[0122] In an example embodiment, as shown in FIGS. 1, 3, and 5, the active layer 12 can include a first active layer 121 and a second active layer 122. The second active layer 122 is disposed on the side of the first active layer 121 away from the substrate 10.

[0123] In an example embodiment, as shown in FIG. 5, the orthogonal projection of the second active layer 122 on the substrate 10 can be within the orthogonal projection of the first active layer 121 on the substrate 10.

[0124] In an example embodiment, the thickness of the first active layer 121 is greater than the thickness of the second active layer 122.

[0125] In an example embodiment, the electrical conductivity of the second active layer 122 is greater than the electrical conductivity of the first active layer 121.

[0126] In an example embodiment, the first active layer 121 can be an amorphous silicon layer, or a metal oxide layer.

[0127] In an example embodiment, the second active layer 122 is an N-type semiconductor layer. For example, the second active layer 122 is an N-type doped amorphous silicon layer, or a metal oxide layer.

[0128] In an example embodiment, as shown in FIGS. 1 and 3, the distance L1 between the surface of the first active layer 121 away from the substrate 10 and the surface of the gate electrode 11 away from the substrate 10 is less than or equal to the distance L2 between the surface of the gate insulating layer 21 in the second region away from the substrate 10 and the surface of the gate electrode 11 away from the substrate 10. FIGS. 1 and 3 are examples in which the distance L1 between the surface of the first active layer 121 away from the substrate 10 and the surface of the gate electrode 11 away from the substrate 10 is equal to the distance L2 between the surface of the gate insulating layer 21 in the second region away from the substrate 10 and the surface of the gate electrode 11 away from the substrate 10.

[0129] In an example embodiment, as shown in FIG. 1 and FIG. 3, the distance L3 between the surface of the second active layer 122 away from the substrate 10 and the surface of the gate electrode 11 away from the substrate 10 is greater than the distance L2 between the surface of the gate insulating layer 21 in the second region away from the substrate 10 and the surface of the gate electrode 11 away from the substrate 10.

[0130] In an example embodiment, as shown in FIG. 1 and FIG. 3, the orthographic projection of at least part of the second active layer 122 on the substrate 10 is within the orthographic projection of the first electrode 13 on the substrate 10, i.e. the first electrode 13 covers at least part of the second active layer.

[0131] In an example embodiment, as shown in FIG. 1 and FIG. 3, the orthographic projection of at least part of the second active layer 122 on the substrate 10 is within the orthographic projection of the second electrode 14 on the substrate 10, i.e. the second electrode 14 covers at least part of the second active layer.

[0132] In an example embodiment, as shown in FIG. 1, FIG. 3 and FIG. 5, at least one of the first electrode 13 and the second electrode 14 fills part of the groove structure 1 and covers the sidewall of the active layer 12.

[0133] In an example embodiment, as shown in FIG. 1, FIG. 3 and FIG. 5, the orthographic projection of at least one of the first electrode 13 and the second electrode 14 on the substrate 10 at least partially overlaps the orthographic projection of the gate insulating layer 21 in the second region on the substrate 10. The at least partial overlap between the orthographic projection of at least one of the first electrode 13 and the second electrode 14 on the substrate 10 and the orthographic projection of the gate insulating layer 21 in the second region on the substrate 10 can ensure that the first electrode and the second electrode can sufficiently contact the active layer 12.

[0134] In an example embodiment, as shown in FIG. 1 and FIG. 2, the gate insulating layer 21 can be a single layer structure.

[0135] In an example embodiment, as shown in FIG. 2, the thickness H1 of the gate insulating layer 21 in the first region R1 is in the range of 2000 angstroms to 3500 angstroms. Exemplarily, the thickness H1 of the gate insulating layer 21 in the first region R1 can be 2000 angstroms.

[0136] In an example embodiment, when the gate insulating layer 21 is a single layer structure, the material of the gate insulating layer 21 can include silicon oxide or silicon nitride.

[0137] In an example embodiment, as shown in FIG. 2, the distance H between the surface of the gate insulating layer 21 in the second region R2 and the surface of the gate electrode 11 away from the substrate 10 is in the range of 3800-4200 angstroms. Exemplarily, the distance H between the surface of the gate insulating layer 21 in the second region R2 and the surface of the gate electrode 11 away from the substrate 10 can be 4000 angstroms.

[0138] In an example embodiment, when the gate insulating layer is a single layer structure, the thickness of the gate insulating layer is the thickness of the gate insulating layer in the second region. The thickness of the gate insulating layer is in the range of 3800-4200 angstroms.

[0139] In an example embodiment, the distance H between the surface of the gate insulating layer 21 in the second region R2 and the surface of the gate electrode 11 away from the substrate 10 can be controlled by the etching time of the gate insulating layer.

[0140] In an example embodiment, as shown in FIG. 3 and FIG. 4, the gate insulating layer 21 can include a first gate insulating layer 22 and a second gate insulating layer 23 which are sequentially stacked on the substrate 10.

[0141] In an example embodiment, as shown in FIG. 4, the second gate insulating layer 23 is provided with a via V which exposes the first gate insulating layer 22, and the via V of the second gate insulating layer 23 and the first gate insulating layer 22 form a groove structure 1.

[0142] In an example embodiment, as shown in FIG. 4, the orthographic projection of the active layer 12 on the substrate 10 is within the orthographic projection of the via V on the substrate 10.

[0143] In an example embodiment, as shown in FIG. 4, the thickness H2 of the first gate insulating layer 22 is in the range of 2000-3500 angstroms. Exemplarily, the thickness H3 of the first gate insulating layer 22 can be 2000 angstroms. In an example embodiment, the thinner the thickness of the first gate insulating layer, the more obvious the effect of improving the on-state current of the transistor device.

[0144] In an example embodiment, as shown in FIG. 3, the distance H between the surface of the second gate insulating layer 23 away from the substrate 10 and the surface of the gate electrode 11 away from the substrate 10 is in the range of 3800-4200 angstroms.

[0145] In an example embodiment, when the gate insulating layer is a double layer structure, the thickness of the gate insulating layer is equal to the sum of the thickness of the first gate insulating layer and the thickness of the second gate insulating layer. The thickness of the gate insulating layer is in the range of 3800-4200 angstroms.

[0146] In the example embodiment, the first gate insulating layer 22 and the second gate insulating layer 23 can be made of different materials. The first gate insulating layer 22 can be made of one of silicon oxide and silicon nitride, and the second gate insulating layer 23 can be made of the other of silicon oxide and silicon nitride.

[0147] In the example embodiment, the first gate insulating layer 22 and the second gate insulating layer 23 are made of different materials, and the first gate insulating layer 22 and the second gate insulating layer 23 require different dry etching gases. When forming the gate insulating layer, only the etching gas for the second gate insulating layer is used, and the etching gas for the first gate insulating layer is not used. In this way, the second gate insulating layer can be etched, and the first gate insulating layer is completely retained, thereby avoiding changes in transistor characteristics caused by etching amount fluctuations.

[0148] In the example embodiment, the active layer 12 is made of a metal oxide. The first gate insulating layer 22 is made of silicon oxide, and the second gate insulating layer 23 is made of silicon nitride.

[0149] In the example embodiment, the active layer 12 is made of amorphous silicon. The first gate insulating layer 22 is made of silicon nitride, and the second gate insulating layer 23 is made of silicon oxide.

[0150] FIG. 6 is a graph of the gate insulating layer thickness and the Ion normalization coefficient. As shown in FIG. 6, the smaller the gate insulating layer thickness, the greater the increase in the on-current Ion of the transistor.

[0151] FIG. 7 is a graph of the voltage Vg of the gate electrode and the current Id flowing through the source electrode under different gate insulating layer thicknesses. As shown in FIG. 7, S1 is a graph of the voltage of the gate electrode and the current flowing through the source electrode when the gate insulating layer thickness is 3500 angstroms, and S2 is a graph of the voltage of the gate electrode and the current flowing through the source electrode when the gate insulating layer thickness is 4000 angstroms. As shown in FIG. 7, the smaller the gate insulating layer thickness, the greater the increase in the on-current Ion of the transistor.

[0152] The smaller the gate insulating layer thickness, the greater the increase in the on-current Ion of the transistor, and the greater the increase in the failure rate of the load of the display product and the short circuit between the data line and the gate line.

[0153] The present disclosure can increase the on-current of the transistor while reducing the failure rate of the load of the display product and the short circuit between the data line and the gate line when the thickness of the gate insulating layer is in the range of 3800 angstroms to 4200 angstroms.

[0154] In the example embodiment, the thickness of the gate electrode 11 is in the range of 2000 angstroms to 5000 angstroms. The thickness of the gate electrode 11 depends on the resolution and refresh frequency of the display product, and the present disclosure does not make any limitation thereon.

[0155] In an exemplary embodiment, the thickness of at least one of the first electrode 13 and the second electrode 14 is in the range of 2000 angstroms to 5000 angstroms. The thickness of at least one of the first electrode 13 and the second electrode 14 depends on the resolution and refresh frequency of the display product, and the present disclosure does not make any limitation in this regard.

[0156] In an exemplary embodiment, the thickness of the active layer 12 is in the range of 1700 angstroms to 2200 angstroms.

[0157] The subsequent process flow is shown in FIG. 2. Thus, the overall Ion value of the TFT can be adjusted by adjusting the thickness of the GI1 deposition. As can be seen from the above formula, the Ion value ratio is proportional to the GI thinning value and the initial GI value ratio, i.e., Ion / Ionref=GIref / GI. FIG. 4 shows the relationship between the Ion normalization coefficient and GI using a-Si as an example. In theory, the thinner the GI, the greater the Ion improvement, but GI thinning will cause an increase in the gate parasitic capacitance and source / drain parasitic capacitance of the TFT, and the DGS defect rate will also increase, so in general industrial production, the commonly used value of the thickness of GI1 is 2000 angstroms to 3500 angstroms.

[0158] In an exemplary embodiment, the thickness of the gate electrode of the transistor is determined by the product characteristics of the product, wherein the product characteristics include: resolution and refresh frequency.

[0159] In an exemplary embodiment, the thickness of the first electrode and the second electrode of the transistor is determined by the product characteristics of the product.

[0160] In an exemplary embodiment, the thickness of the gate insulating layer can be 4000 angstroms.

[0161] In an exemplary embodiment, the thickness of the first gate insulating layer can be between 2000 angstroms and 3500 angstroms. The thinner the thickness of the first gate insulating layer, the more obvious the improvement effect on the on-current of the transistor device.

[0162] FIG. 8 is a top view of a transistor device, FIG. 9 is a sectional view of FIG. 8 along the A-A direction, and FIG. 10 is a sectional view of FIG. 8 along the B-B direction. As shown in FIGS. 8 to 10, the first electrode 13 can surround at least one side of the second electrode 14, and the orthographic projection of the first electrode 13 on the substrate 10 covers the sidewall of the active layer 12, and the orthographic projection of the second electrode 14 on the substrate 10 at least partially overlaps with the orthographic projection of the middle part of the active layer 12 on the substrate 10. That is, the first electrode 13 in FIG. 8 at least partially surrounds the second electrode 14. FIG. 5 is described by taking the first electrode and the second electrode as strips as an example, and FIG. 8 is described by taking the first electrode 13 at least partially surrounding the second electrode 14 as an example.

[0163] In the example embodiment, as shown in FIGS. 5 and 8, the minimum width W of at least one of the first electrode 13 and the second electrode 14 along the arrangement direction of the first electrode 13 and the second electrode 14 is in the range of 2.5 microns to 3.5 microns.

[0164] In the example embodiment, as shown in FIGS. 5 and 8, the distance W2 between the orthographic projection of the boundary of the recess structure 1 on the substrate 10 and the orthographic projection of the boundary of the active layer 12 on the substrate 10 is less than the distance W3 between the orthographic projection of the boundary of the first electrode 13 close to the second electrode 14 on the substrate 10 and the orthographic projection of the boundary of the active layer 12 on the substrate 10.

[0165] In the example embodiment, as shown in FIGS. 5 and 8, the distance W3 between the orthographic projection of the boundary of the first electrode 13 close to the second electrode 14 on the substrate 10 and the orthographic projection of the boundary of the active layer 12 on the substrate 10 is greater than the distance W1 between the orthographic projection of the boundary of the first electrode 13 away from the second electrode 14 on the substrate 10 and the orthographic projection of the boundary of the gate electrode 11 on the substrate 10.

[0166] In the example embodiment, the distance W1 between the orthographic projection of the boundary of the first electrode 13 away from the second electrode 14 on the substrate 10 and the orthographic projection of the boundary of the gate electrode 11 on the substrate 10 satisfies the overlap error between the film layer where the gate electrode is located and the film layer where the first electrode 13 and the second electrode 14 are located, i.e., the distance W1 between the orthographic projection of the boundary of the first electrode 13 away from the second electrode 14 on the substrate 10 and the orthographic projection of the boundary of the gate electrode 11 on the substrate 10 is greater than or equal to the overlap error between the film layer where the gate electrode 11 is located and the film layer where the first electrode 13 and the second electrode 14 are located.

[0167] In the example embodiment, the distance W2 between the orthographic projection of the boundary of the recess structure 1 on the substrate 10 and the orthographic projection of the boundary of the active layer 12 on the substrate 10 satisfies the overlap error between the film layer where the active layer is located and the film layer where the gate insulating layer is located, i.e., the distance W1 between the orthographic projection of the boundary of the recess structure 1 on the substrate 10 and the orthographic projection of the boundary of the active layer 12 on the substrate 10 is greater than or equal to the overlap error between the film layer where the active layer is located and the film layer where the gate insulating layer is located.

[0168] In the example embodiment, the distance W3 between the orthographic projection of the boundary of the first electrode 13 close to the second electrode 14 on the substrate 10 and the orthographic projection of the boundary of the active layer 12 on the substrate 10 is greater than or equal to the overlap error between the film layer where the active layer is located and the film layer where the first electrode and the second electrode are located plus 1 micron, so as to ensure the overlap area between one of the first electrode and the second electrode and the active layer, which can improve the reliability of the transistor device.

[0169] In the example embodiment, the distance W4 between the first electrode 13 and the second electrode 14 along the first electrode and second electrode arrangement direction is determined by the resolution of the exposure machine used in the process of forming the first electrode and the second electrode, the process type, and the product model, and the present disclosure does not make any limitation thereto.

[0170] In the example embodiment, FIG. 11 is a schematic structural diagram of a display substrate, and FIG. 12 is another schematic structural diagram of a display substrate. As shown in FIGS. 11 and 12, the transistor device further comprises a passivation layer 31. The passivation layer 31 is located on the side of the first electrode 13 and the second electrode 14 of the transistor away from the substrate 10. In the example embodiment, the passivation layer can protect the metal film layer where the first electrode and the second electrode of the transistor are located, can avoid the metal film layer where the first electrode and the second electrode of the transistor are located from being corroded, and can improve the reliability of the transistor device.

[0171] In the example embodiment, the passivation layer 31 can be any one or more of silicon oxide compound (SiOx), silicon nitride compound (SiNx), and silicon oxynitride compound (SiON), and can be a single layer, multiple layers, or a composite layer.

[0172] The “patterning process” in the present disclosure includes coating photoresist, mask exposure, development, etching, stripping photoresist, and the like for metal materials, inorganic materials, or transparent conductive materials, and includes coating organic materials, mask exposure, development, and the like for organic materials. The deposition can use any one or more of sputtering, evaporation, and chemical vapor deposition, the coating can use any one or more of spraying, spin coating, and inkjet printing, and the etching can use any one or more of dry etching and wet etching, and the present disclosure does not make any limitation. The “thin film” refers to a thin film of a certain material made on a substrate by deposition, coating, or other processes. If the “thin film” does not need to be patterned during the entire manufacturing process, the “thin film” can also be referred to as a “layer”. If the “thin film” needs to be patterned during the entire manufacturing process, it is referred to as a “thin film” before the patterning process and a “layer” after the patterning process. The “layer” after the patterning process contains at least one “pattern”. The “A and B are arranged in the same layer” in the present disclosure means that A and B are formed at the same time by the same patterning process. The “thickness” of the film layer is the size of the film layer in the direction perpendicular to the display substrate. In the example embodiment of the present disclosure, “the orthographic projection of B is within the orthographic projection of A” or “the orthographic projection of A contains the orthographic projection of B” means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0173] The preparation process of the transistor device provided in FIG. 11 is exemplarily described below.

[0174] (1) Forming the gate electrode. In an exemplary embodiment, forming the gate electrode comprises: depositing a first metal thin film on the substrate, patterning the first metal thin film by a patterning process, and forming the gate electrode 11. As shown in FIG. 13, FIG. 13 is a schematic diagram of the structure after forming the gate electrode of FIG. 11.

[0175] (2) Forming the gate insulating layer. In an exemplary embodiment, forming the gate insulating layer comprises: depositing a gate insulating thin film on the substrate with the gate electrode formed thereon, patterning the gate insulating thin film by a patterning process, and forming the gate insulating layer 21 with the groove structure 1 arranged thereon. As shown in FIG. 14, FIG. 14 is a schematic diagram of the structure after forming the gate insulating layer of FIG. 11.

[0176] In an exemplary embodiment, the gate insulating thin film is deposited on the substrate with the gate electrode formed thereon by a chemical vapor deposition process.

[0177] (3) Forming the original semiconductor layer. In an exemplary embodiment, forming the original semiconductor layer comprises: depositing a semiconductor thin film on the substrate with the gate insulating layer formed thereon, doping the surface of the semiconductor thin film by a hydrogenation process, and patterning the doped semiconductor thin film by a patterning process, thereby forming the original semiconductor layer comprising the first active layer 121 and the third active layer 123. As shown in FIG. 15, FIG. 15 is a schematic diagram of the structure after forming the original semiconductor layer of FIG. 11.

[0178] In an exemplary embodiment, the third active layer 123 is an N-type semiconductor layer.

[0179] In an exemplary embodiment, the third active layer 123 has a normal projection on the substrate that coincides with a normal projection on the substrate of a surface of the first active layer 121 away from the substrate.

[0180] (4) Forming the first electrode and the second electrode. In an exemplary embodiment, forming the first electrode and the second electrode comprises: depositing a second metal thin film on the substrate with the original semiconductor layer formed thereon, and patterning the second metal thin film and the third active layer by a patterning process, respectively, thereby forming the first electrode 13, the fourth electrode 14, and the second active layer 122. As shown in FIG. 16, FIG. 16 is a schematic diagram of the structure after forming the first electrode and the second electrode of FIG. 11.

[0181] In an exemplary embodiment, the active layer comprises the first active layer 121 and the second active layer 122.

[0182] (5) Forming the passivation layer. In an exemplary embodiment, forming the passivation layer comprises: depositing the passivation layer on the substrate with the first electrode and the second electrode formed thereon. As shown in FIG. 17, FIG. 17 is a schematic diagram of the structure after forming the passivation layer of FIG. 11.

[0183] The preparation process of the transistor device provided in FIG. 12 is described below by way of example.

[0184] (1) Forming a gate electrode. In an example embodiment, forming the gate electrode includes depositing a first metal thin film on the substrate, patterning the first metal thin film by a patterning process, and forming the gate electrode. The schematic diagram after forming the gate electrode in FIG. 12 is the same as that in FIG. 9.

[0185] (2) Forming a gate insulating layer. In an example embodiment, forming the gate insulating layer includes sequentially depositing a first gate insulating thin film and a second gate insulating thin film on the substrate on which the gate electrode is formed, patterning the second gate insulating thin film by a patterning process, and forming the gate insulating layer 21 including the first gate insulating layer 22 and the second gate insulating layer 23. As shown in FIG. 18, the schematic diagram after forming the gate insulating layer in FIG. 12 is the same as that in FIG. 18.

[0186] In an example embodiment, the second gate insulating layer 23 is provided with a via V exposing the first gate insulating layer 22. The via V and the first gate insulating layer 22 constitute a groove structure.

[0187] In an example embodiment, the first gate insulating thin film and the second gate insulating thin film are sequentially deposited on the substrate on which the gate electrode is formed by a chemical vapor deposition process.

[0188] (3) Forming a raw semiconductor layer. In an example embodiment, forming the raw semiconductor layer includes depositing a semiconductor thin film on the substrate on which the gate insulating layer is formed, N-type doping the surface of the semiconductor thin film by a hydrogenation process, and patterning the doped semiconductor thin film by a patterning process to form the raw semiconductor layer including the first active layer 121 and the third active layer 123. As shown in FIG. 19, the schematic diagram after forming the raw semiconductor layer in FIG. 12 is the same as that in FIG. 19.

[0189] In an example embodiment, the third active layer 123 is an N-type semiconductor layer.

[0190] In an example embodiment, the third active layer 123 is an N-type semiconductor layer.

[0191] (4) Forming a first electrode and a second electrode. In an example embodiment, forming the first electrode and the second electrode includes depositing a second metal thin film on the substrate on which the raw semiconductor layer is formed, and patterning the second metal thin film and the third active layer by a patterning process, respectively, to form the first electrode 13, the fourth electrode 14, and the second active layer 122. As shown in FIG. 20, the schematic diagram after forming the first electrode and the second electrode in FIG. 12 is the same as that in FIG. 20.

[0192] In an example embodiment, the active layer includes the first active layer 121 and the second active layer 122.

[0193] (5) forming a passivation layer. In an example embodiment, forming the passivation layer comprises depositing the passivation layer on the substrate on which the first electrode and the second electrode are formed. As shown in FIG. 21, which is a schematic diagram of the transistor device after the passivation layer is formed in FIG. 12.

[0194] The embodiments of the present disclosure also provide a method for manufacturing a transistor device, configured to manufacture the transistor device provided by any one of the preceding embodiments. The method for manufacturing the transistor device comprises:

[0195] Step 100, forming a gate electrode of the transistor device on a substrate.

[0196] Step 200, forming a gate insulating layer of the transistor device on the gate electrode, the gate insulating layer being provided with a groove structure, and the groove structure being located on a side of the gate insulating layer away from the substrate.

[0197] Step 300, forming an active layer of the transistor device in the groove structure of the gate insulating layer.

[0198] wherein at least two boundaries of the active layer have a preset interval with corresponding boundaries of the groove structure.

[0199] In an example embodiment, step 200 can comprise coating a gate insulating film on the gate electrode, and opening a groove on the gate insulating film through a patterning process to form the gate insulating layer of the transistor device.

[0200] In an example embodiment, step 200 can comprise coating a first gate insulating film and a second gate insulating film on the gate electrode in sequence, opening a via on the second gate insulating film through a patterning process to form the gate insulating layer provided with the groove structure composed of the via and the first gate insulating film.

[0201] In an example embodiment, the active layer comprises a first active layer and a second active layer. Step 300 comprises depositing a semiconductor film on the gate insulating layer; treating the semiconductor film through a hydrogenation process to form the first active layer and a third active layer;

[0202] depositing a source-drain metal film on the third active layer, and treating the source-drain metal film and the third active layer through a patterning process to form the second active layer, the first electrode and the second electrode.

[0203] In an example embodiment, the method for manufacturing the transistor device further comprises:

[0204] Step 400, forming a passivation layer on the first electrode and the second electrode.

[0205] FIG. 22A is a schematic cross-sectional view of a transistor device according to an embodiment of the present disclosure, and FIG. 22B is a partial cross-sectional view of FIG. 22A. As shown in FIG. 22A and FIG. 22B, the transistor device according to an embodiment of the present disclosure is disposed on a substrate 100, and includes a gate electrode 201, an active layer 202, a first electrode 203, a second electrode 204, and a gate insulating layer 300. The first electrode 203 and the second electrode 204 are disposed on a side of the active layer 202 and the gate electrode 201 away from the substrate 100, and the gate insulating layer 300 is disposed between the active layer 202 and the gate electrode 201.

[0206] In an exemplary embodiment, the gate electrode 201 can be disposed on a side of the gate insulating layer 300 close to the substrate 100, and the active layer 20 can be disposed on a side of the gate insulating layer 300 away from the substrate 100, that is, the transistor device can be a bottom-gate structure. Alternatively, the gate electrode 201 can be disposed on a side of the gate insulating layer 300 away from the substrate 100, and the active layer 20 can be disposed on a side of the gate insulating layer 300 close to the substrate 100, that is, the transistor device can be a top-gate structure. FIG. 22A and FIG. 22B are described by taking the transistor device as a bottom-gate structure as an example.

[0207] As shown in FIG. 22A and FIG. 22B, the gate insulating layer 300 can include a first insulating layer 301 and a second insulating layer 302 disposed on the substrate 100 in a stacked manner, and one of the first insulating layer 301 and the second insulating layer 302 is provided with a via hole VV. FIG. 22B is described by taking the first insulating layer 301 provided with the via hole VV as an example.

[0208] As shown in FIG. 22A and FIG. 22B, a normal projection of the via hole VV on the substrate 100 at least partially overlaps a normal projection of the active layer 202 on the substrate 100. The at least partial overlap between the normal projection of the via hole VV on the substrate 100 and the normal projection of the active layer 202 on the substrate 100 in the present disclosure can reduce the thickness of the gate insulating layer disposed between the channel region of the active layer and the gate electrode, increase the capacitance value of the parasitic capacitance between the channel region of the active layer and the gate electrode, increase the on-current Ion of the transistor device, and thus improve the refresh rate of the display product.

[0209] The present disclosure can ensure the etching precision of the gate insulating layer, improve the process stability of the transistor device, and reduce the fluctuation of the on-current of the transistor device by disposing the gate insulating layer including the first insulating layer and the second insulating layer, and providing the via hole in one of the first insulating layer and the second insulating layer.

[0210] In an exemplary embodiment, as shown in FIG. 22A, a normal projection of at least one of the first electrode 203 and the second electrode 204 on the substrate at least partially overlaps a normal projection of the active layer 202 on the substrate.

[0211] In an example embodiment, as shown in FIGS. 22A and 22B, the active layer 202 includes a first active layer 2021 and a second active layer 2022, the second active layer 2022 is disposed on a side of the first active layer 2021 away from the substrate 100, and the second active layer 2022 includes a first active structure 2021 and a second active structure 2022.

[0212] In an example embodiment, as shown in FIGS. 22A and 22B, the orthographic projection of the second active layer 202 on the substrate 100 is within the orthographic projection of the first active layer 201 on the substrate 100.

[0213] In an example embodiment, as shown in FIGS. 22A and 22B, the orthographic projection of the first active structure 2021 on the substrate 100 is within the orthographic projection of the first electrode 203 on the substrate 100.

[0214] In an example embodiment, as shown in FIGS. 22A and 22B, the orthographic projection of the second active structure 3222 on the substrate 100 is within the orthographic projection of the second electrode 204 on the substrate 100.

[0215] In an example embodiment, the second active layer 202 can be prepared with the same mask as the first electrode 203 and the second electrode 204, and the present disclosure does not make any limitation in this regard.

[0216] In an example embodiment, the thickness of the first active layer 201 is greater than the thickness of the second active layer 202.

[0217] In an example embodiment, the second active layer 202 has a greater electrical conductivity than the first active layer 201. In an example embodiment, the second active layer can be an N-type semiconductor layer.

[0218] In an example embodiment, the maximum distance H between the surface of the gate insulating layer 300 away from the substrate 100 and the surface of the gate electrode 31 away from the substrate 100 is in the range of 3800 angstroms to 4200 angstroms. For example, the maximum distance H between the surface of the gate insulating layer 300 away from the substrate 100 and the surface of the gate electrode 31 away from the substrate 100 can be 4000 angstroms.

[0219] In an example embodiment, the thickness H0 of the via VV in the direction perpendicular to the substrate is in the range of 1500 angstroms to 3500 angstroms.

[0220] In the example embodiment, the material for forming the first insulating layer 301 includes one of silicon oxide and silicon nitride, and the material for forming the second insulating layer 302 includes the other of silicon oxide and silicon nitride. For example, when the material for forming the first insulating layer 301 is silicon oxide, the material for forming the second insulating layer 302 can be silicon nitride, or when the material for forming the first insulating layer 301 is silicon nitride, the material for forming the second insulating layer 302 can be silicon oxide, and the present disclosure does not make any limitation in this regard.

[0221] In the example embodiment, the semiconductor layer can be an amorphous silicon layer, or can be a metal oxide layer. The metal oxide layer can include an oxide containing indium and tin, an oxide containing tungsten and indium, an oxide containing tungsten, indium and zinc, an oxide containing titanium and indium, an oxide containing titanium, indium and tin, an oxide containing indium and zinc, an oxide containing silicon, indium and tin, or an oxide containing indium or gallium and zinc. The metal oxide layer can be a single layer, or can be a double layer, or can be a multi-layer.

[0222] In the example embodiment, the gate electrode can be made of a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or an alloy material of the above-mentioned metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), and can be a single layer structure, or a multi-layer composite structure, such as Mo / Cu / Mo, etc., and the present disclosure does not make any limitation in this regard.

[0223] In the example embodiment, the first electrode and the second electrode can be made of a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or an alloy material of the above-mentioned metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), and can be a single layer structure, or a multi-layer composite structure, such as Mo / Al / Mo or MoNb / Cu, etc., and the present disclosure does not make any limitation in this regard.

[0224] The transistor device provided by the example embodiment of the present disclosure is exemplarily described below through the preparation process of the transistor device provided by FIG. 22A.

[0225] (1) Forming the gate electrode. In the example embodiment, forming the gate electrode includes depositing a first metal thin film on the substrate, and patterning the first metal thin film through a patterning process to form the gate electrode 201, as shown in FIG. 23a.

[0226] (2) Forming the first insulating layer. In the example embodiment, forming the first insulating layer includes depositing a first insulating thin film on the substrate on which the gate electrode is formed to form the first insulating layer 301, as shown in FIG. 23b.

[0227] In an example embodiment, a first insulating thin film is deposited on the substrate on which the gate electrode is formed by a chemical vapor deposition process.

[0228] In an example embodiment, the first insulating layer 301 is provided with a via hole VV.

[0229] (3) Forming a second insulating layer. In an example embodiment, forming the second insulating layer comprises forming a second insulating layer 302 on the substrate on which the first insulating layer is formed, as shown in FIG. 23c.

[0230] (4) Forming a raw semiconductor layer. In an example embodiment, forming the raw semiconductor layer comprises depositing a semiconductor thin film on the substrate on which the second insulating layer is formed, N-type doping the surface of the semiconductor thin film by a hydrogenation process, patterning the doped semiconductor thin film by a patterning process, and forming a raw semiconductor layer comprising a first active layer 2021 and a third active layer 2025, as shown in FIG. 23d.

[0231] In an example embodiment, the third active layer 2025 has a front projection on the substrate that coincides with the front projection on the substrate of the surface of the first active layer 2021 away from the substrate.

[0232] (5) Forming a first electrode and a second electrode. In an example embodiment, forming the first electrode and the second electrode comprises depositing a second metal thin film on the substrate on which the second insulating layer is formed, and patterning the second metal thin film and the third active layer respectively by a patterning process, to form a first electrode 203, a fourth electrode 204, and a second active layer 2022, as shown in FIG. 23e.

[0233] (6) Forming a passivation layer. In an example embodiment, forming the passivation layer comprises forming a passivation layer on the substrate on which the first electrode and the second electrode are formed.

[0234] In an example embodiment, the first electrode can be in the shape of a "U", an "I", or an "L". The second electrode can be in the shape of an "I". When the first electrode is in the shape of a "U", the transistor device can be referred to as a U-shaped transistor device, when the first electrode is in the shape of an "I", the transistor device can be referred to as an "I"-shaped transistor device, and when the first electrode is in the shape of an "L", the transistor device can be referred to as an L-shaped transistor device.

[0235] In an exemplary embodiment, FIG. 24 is a top view I of a transistor device, FIG. 25 is a top view II of a transistor device, FIG. 26 is a top view III of a transistor device, FIG. 27 is a top view IV of a transistor device, and FIG. 28 is a top view V of a transistor device. As shown in FIGS. 24-28, the orthogonal projection of the active layer 42 on the substrate is located within the orthogonal projection of the gate electrode 41 on the substrate, the orthogonal projection of the via VV on the substrate is located within the orthogonal projection of the active layer 42 on the substrate, the orthogonal projection of the first electrode 43 on the substrate is located within the orthogonal projection of the active layer 42 on the substrate, and the orthogonal projection of a portion of the second electrode 44 on the substrate does not overlap the orthogonal projection of the gate electrode 41 on the substrate.

[0236] As shown in FIGS. 24-28, the via VV includes a plurality of boundaries, which includes a first boundary L11, a second boundary L12, a third boundary L13, and a fourth boundary L14. The first boundary L11 and the second boundary L12 extend along a first direction D1, and the third boundary L13 and the fourth boundary L14 extend along a second direction D2. The first boundary L11, the fourth boundary L14, the second boundary L12, and the third boundary L13 are connected in sequence.

[0237] In an exemplary embodiment, as shown in FIGS. 24-28, the first electrode 43 includes an electrode connecting segment 434, a first branch segment 431, a second branch segment 432, and a third branch segment 433. The electrode connecting segment 434 extends at least partially along the first direction D1, the first branch segment 431, the second branch segment 432, and the third branch segment 433 are arranged along the first direction D1, and at least one branch segment extends along the second direction D2. The electrode connecting segment 434 is connected to the first branch segment 431, the second branch segment 432, and the third branch segment 433, respectively. The first direction D1 intersects the second direction D2.

[0238] In an exemplary embodiment, as shown in FIGS. 24-28, the second electrode 44 includes a first sub-electrode 441 and a second sub-electrode 442. The first sub-electrode 441 and the second sub-electrode 442 extend along the second direction D2. The orthogonal projection of the first sub-electrode 441 on the substrate is located between the orthogonal projection of the first branch segment 431 on the substrate and the orthogonal projection of the second branch segment 432 on the substrate. The orthogonal projection of the second sub-electrode 442 on the substrate is located between the orthogonal projection of the second branch segment 432 on the substrate and the orthogonal projection of the third branch segment 433 on the substrate.

[0239] In an exemplary embodiment, as shown in FIGS. 24-28, the orthogonal projection of the second boundary L12 on the substrate is located on the side of the first boundary L11 close to the orthogonal projection of the electrode connecting segment 434 on the substrate.

[0240] In the example embodiment, as shown in FIG. 24, the first boundary L11, the second boundary L12, the third boundary L13, and the fourth boundary L14 are in a straight line shape.

[0241] In the example embodiment, as shown in FIG. 24, the orthographic projection of the electrode connecting segment 434 on the substrate does not overlap with the orthographic projections of the plurality of boundaries on the substrate, the orthographic projections of the first branch segment 431 on the substrate overlap with the orthographic projections of the first boundary L11, the second boundary L12, and the third boundary L13 on the substrate respectively, the orthographic projections of the second branch segment 432 on the substrate overlap with the orthographic projections of the first boundary L11 and the second boundary L12 on the substrate respectively, the orthographic projections of the third branch segment 433 on the substrate overlap with the orthographic projections of the first boundary L11, the second boundary L12, and the fourth boundary L14 on the substrate respectively, and the orthographic projections of the first sub-electrode 441 and the second sub-electrode 442 on the substrate overlap with the orthographic projections of the first boundary L11 and the second boundary L12 on the substrate respectively.

[0242] In the example embodiment, as shown in FIG. 24, the distance a1 between the orthographic projection of the boundary of the first branch segment 431 close to the first sub-electrode 441 on the substrate and the orthographic projection of the third boundary L13 on the substrate along the first direction D1 is in the range of 1 micrometer to 1.5 micrometers.

[0243] In the example embodiment, as shown in FIG. 24, the distance b1 between the orthographic projection of the boundary of at least one of the first sub-electrode 441 and the second sub-electrode 442 close to the electrode connecting segment 434 on the substrate and the orthographic projection of the second boundary L12 on the substrate along the second direction D2 is in the range of 1 micrometer to 1.5 micrometers.

[0244] In the example embodiment, as shown in FIG. 24, the distance c1 between the orthographic projection of the boundary of the third branch segment 433 close to the second sub-electrode 442 on the substrate and the orthographic projection of the fourth boundary L14 on the substrate along the first direction D1 is in the range of 1 micrometer to 1.5 micrometers.

[0245] In the example embodiment, in the transistor device provided in FIG. 24, since the orthographic projection of the first electrode of the transistor device on the substrate overlaps with the orthographic projections of the third boundary and the fourth boundary on the substrate respectively, and the orthographic projection of the second electrode of the transistor device on the substrate overlaps with the orthographic projections of the first boundary and the second boundary on the substrate, when the first electrode and the second electrode are misaligned in the first direction relative to the gate insulating layer, the parasitic capacitance between the gate electrode and the first electrode and the parasitic capacitance between the gate electrode and the second electrode do not fluctuate. However, since the thickness of the part of the channel region of the active layer between the first electrode and the second electrode is not thinned, the transistor device provided in FIG. 24 has limited effect on the improvement of the on-current of the transistor device.

[0246] In the example embodiment, as shown in FIGS. 25 and 26, the first boundary L11, the third boundary L13, and the fourth boundary L14 are linear, and the second boundary L12 is shaped to match the shape of the electrode connecting segment 434. In the example embodiment, the electrode connecting segment 434 can have an M shape.

[0247] In the example embodiment, as shown in FIGS. 25 and 26, the orthogonal projection of the electrode connecting segment 434 on the substrate overlaps the orthogonal projection of the second boundary L12 on the substrate, the orthogonal projection of the first branch segment 431 on the substrate overlaps the orthogonal projection of the third boundary L13 on the substrate and does not overlap the orthogonal projection of the first boundary L11 on the substrate, the orthogonal projection of the second branch segment 432 on the substrate does not overlap the orthogonal projection of each of the plurality of boundaries on the substrate, the orthogonal projection of the third branch segment 433 on the substrate overlaps the orthogonal projection of the fourth boundary L14 on the substrate and does not overlap the orthogonal projection of the first boundary L11 on the substrate, and the orthogonal projection of the first sub-electrode 441 and the second sub-electrode 442 on the substrate partially overlaps the orthogonal projection of the first boundary L11 on the substrate.

[0248] In the example embodiment, as shown in FIGS. 25 and 26, the distance a2 between the orthogonal projection of the boundary of the first branch segment 431 near the first sub-electrode 441 on the substrate and the orthogonal projection of the third boundary L13 on the substrate along the first direction D1 is in the range of 1 to 1.5 micrometers.

[0249] In the example embodiment, as shown in FIGS. 25 and 26, the distance b2 between the orthogonal projection of the boundary of the electrode connecting segment 434 near the second electrode 44 on the substrate and the orthogonal projection of the second boundary L12 on the substrate along the second direction D2 is in the range of 1 to 1.5 micrometers.

[0250] In the example embodiment, as shown in FIGS. 25 and 26, the distance c2 between the orthogonal projection of the boundary of the third branch segment 433 near the second sub-electrode 442 on the substrate and the orthogonal projection of the fourth boundary L14 on the substrate along the first direction D1 is in the range of 1 to 1.5 micrometers.

[0251] In the example embodiment, as shown in FIG. 26, the plurality of boundaries further include a first convex boundary L21, a second convex boundary L22, a third convex boundary L23, a fourth convex boundary L24, a fifth convex boundary L25, a sixth convex boundary L26, a seventh boundary, and an eighth convex boundary L28, the first convex boundary L21, the third convex boundary L23, the fifth convex boundary L25, and the seventh convex boundary L27 extend along the first direction D1, and the second convex boundary L22, the fourth convex boundary L24, the sixth convex boundary L26, and the eighth convex boundary L28 extend along the second direction D2.

[0252] In an exemplary embodiment, as shown in FIG. 26, the third boundary L13 is connected with the first boundary L11 through the first protruding boundary L21, the second protruding boundary L22, the third protruding boundary L23 and the fourth protruding boundary L24 in sequence, and the fourth boundary L14 is connected with the first boundary L11 through the fifth protruding boundary L25, the sixth protruding boundary L26, the seventh protruding boundary L27 and the eighth protruding boundary L28 in sequence.

[0253] In an exemplary embodiment, as shown in FIG. 26, the orthographic projection of the first electrode 43 and the second electrode 44 on the substrate does not overlap with the orthographic projection of at least one of the first protruding boundary L21, the second protruding boundary L22, the third protruding boundary L23, the fourth protruding boundary L24, the fifth protruding boundary L25, the sixth protruding boundary L26, the seventh protruding boundary L27 and the eighth protruding boundary L28 on the substrate.

[0254] In an exemplary embodiment, as shown in FIG. 26, the distance d1 between the second protruding boundary L22 and the fourth protruding boundary L24 along the second direction D2 is in the range of 1 micrometer to 4 micrometers.

[0255] In an exemplary embodiment, as shown in FIG. 26, the distance d2 between the sixth protruding boundary L26 and the eighth protruding boundary L28 along the second direction D2 is in the range of 1 micrometer to 4 micrometers.

[0256] In an exemplary embodiment, in the transistor device provided in FIG. 25 and FIG. 26, since the orthographic projection of the first electrode of the transistor device on the substrate overlaps with the orthographic projection of the second boundary, the third boundary and the fourth boundary on the substrate respectively, and the orthographic projection of the second electrode of the transistor device on the substrate overlaps with the orthographic projection of the first boundary on the substrate, when the first electrode and the second electrode exist alignment deviation in the first direction or the second direction relative to the gate insulating layer, the parasitic capacitance between the gate electrode and the first electrode and the parasitic capacitance between the gate electrode and the second electrode will not fluctuate. And since the thickness of the partial channel region of the active layer between the first electrode and the second electrode is thinned in total, the transistor device provided in FIG. 25 and FIG. 26 is better for improving the on-current of the transistor device.

[0257] Fig. 26 provides a transistor device with more first to eighth protruding branch segments to the via VV than the transistor device provided in Fig. 25. The first to eighth protruding branch segments can be referred to as optical compensation structures. The structures of the via in the transistor device provided in Fig. 26 after exposure approach right angles at the first and third boundaries and approach right angles at the first and fourth boundaries, which can avoid the loss of on-current caused by the structures of the via in the transistor device provided in Fig. 25 after exposure approach arcs at the first and third boundaries and approach arcs at the first and fourth boundaries, and can improve the performance of the transistor device.

[0258] In an example embodiment, as shown in Fig. 27, the via includes a first via V1, a second via V2, a third via V3, and a fourth via V4, which are arranged along a first direction D1.

[0259] In an example embodiment, as shown in Fig. 27, the orthographic projection of the first via V1 on the substrate is between the orthographic projection of the first branch segment 431 on the substrate and the orthographic projection of the first sub-electrode 441 on the substrate, the orthographic projection of the second via V2 on the substrate is between the orthographic projection of the first sub-electrode 441 on the substrate and the orthographic projection of the second branch segment 432 on the substrate, the orthographic projection of the third via V3 on the substrate is between the orthographic projection of the second branch segment 432 on the substrate and the orthographic projection of the second sub-electrode 442 on the substrate, and the orthographic projection of the fourth via V4 on the substrate is between the orthographic projection of the second sub-electrode 442 on the substrate and the orthographic projection of the third branch segment 433 on the substrate.

[0260] In an example embodiment, the distance between the orthographic projection of the third boundary L13 of the first via V1 on the substrate and the orthographic projection of the boundary of the first branch segment 431 close to the first via V1 on the substrate along the first direction D1 is greater than or equal to 0, and the distance between the orthographic projection of the fourth boundary L14 of the first via V1 on the substrate and the orthographic projection of the boundary of the first sub-electrode 441 close to the first via V1 on the substrate along the first direction D1 is greater than or equal to 0. Fig. 27 is an example in which the distance between the orthographic projection of the third boundary L13 of the first via V1 on the substrate and the orthographic projection of the boundary of the first branch segment 431 close to the first via V1 on the substrate along the first direction D1 is equal to 0, and the distance between the orthographic projection of the fourth boundary L14 of the first via V1 on the substrate and the orthographic projection of the boundary of the first sub-electrode 441 close to the first via V1 on the substrate along the first direction D1 is equal to 0.

[0261] In the example embodiment, the distance between the orthogonal projection on the substrate of the third boundary L13 of the second via V2 and the orthogonal projection on the substrate of the boundary of the first sub-electrode 441 close to the second via V2 along the first direction D1 is greater than or equal to 0, and the distance between the orthogonal projection on the substrate of the fourth boundary L14 of the second via V2 and the orthogonal projection on the substrate of the boundary of the second branch segment 432 close to the second via V2 along the first direction D1 is greater than or equal to 0. FIG. 27 is an example in which the distance between the orthogonal projection on the substrate of the third boundary L13 of the second via V2 and the orthogonal projection on the substrate of the boundary of the first sub-electrode 441 close to the second via V2 along the first direction D1 is equal to 0, and the distance between the orthogonal projection on the substrate of the fourth boundary L14 of the second via V2 and the orthogonal projection on the substrate of the boundary of the second branch segment 432 close to the second via V2 along the first direction D1 is equal to 0.

[0262] In the example embodiment, the distance between the orthogonal projection on the substrate of the third boundary L13 of the third via V3 and the orthogonal projection on the substrate of the boundary of the second branch segment 432 close to the third via V3 along the first direction D1 is greater than or equal to 0, and the distance between the orthogonal projection on the substrate of the fourth boundary L14 of the third via V3 and the orthogonal projection on the substrate of the boundary of the second sub-electrode 442 close to the third via V3 along the first direction D1 is greater than or equal to 0. FIG. 27 is an example in which the distance between the orthogonal projection on the substrate of the third boundary L13 of the third via V3 and the orthogonal projection on the substrate of the boundary of the second branch segment 432 close to the third via V3 along the first direction D1 is equal to 0, and the distance between the orthogonal projection on the substrate of the fourth boundary L14 of the third via V3 and the orthogonal projection on the substrate of the boundary of the second sub-electrode 442 close to the third via V3 along the first direction D1 is equal to 0.

[0263] In the example embodiment, the distance between the orthogonal projection on the substrate of the third boundary L13 of the fourth via V4 and the orthogonal projection on the substrate of the boundary of the second sub-electrode 442 close to the fourth via V4 along the first direction D1 is greater than or equal to 0, and the distance between the orthogonal projection on the substrate of the fourth boundary L14 of the fourth via V4 and the orthogonal projection on the substrate of the boundary of the third branch segment 433 close to the fourth via V4 along the first direction D1 is greater than or equal to 0. FIG. 27 is an example in which the distance between the orthogonal projection on the substrate of the third boundary L13 of the fourth via V4 and the orthogonal projection on the substrate of the boundary of the second sub-electrode 442 close to the fourth via V4 along the first direction D1 is equal to 0, and the distance between the orthogonal projection on the substrate of the fourth boundary L14 of the fourth via V4 and the orthogonal projection on the substrate of the boundary of the third branch segment 433 close to the fourth via V4 along the first direction D1 is equal to 0.

[0264] As shown in FIG. 27, the first electrode and the second electrode in the transistor device do not overlap with the projection of the via on the substrate, which can reduce the load of the transistor device. However, when the first electrode and the second electrode are misaligned in the first direction relative to the gate insulating layer, the parasitic capacitance between the gate electrode and the first electrode and the parasitic capacitance between the gate electrode and the second electrode will fluctuate.

[0265] In an example embodiment, as shown in FIG. 28, the via includes a first via V1, a second via V2, and a third via V3, which are arranged along the first direction D1.

[0266] In an example embodiment, as shown in FIG. 28, the projection of the first via V1 on the substrate partially overlaps with the projection of the first branch segment 431 on the substrate and does not overlap with the projection of the first sub-electrode 441 on the substrate, the projection of the second via V2 on the substrate partially overlaps with the projection of the second branch segment 432 on the substrate and does not overlap with the projection of the first sub-electrode 441 and the second sub-electrode 442 on the substrate, respectively, and the projection of the third via V3 on the substrate partially overlaps with the projection of the third branch segment 433 on the substrate and does not overlap with the projection of the second sub-electrode 442 on the substrate.

[0267] In an example embodiment, as shown in FIG. 28, the projection of the first branch segment 431 on the substrate at least partially overlaps with the projection of the first boundary L11, the second boundary L12, and the third boundary L13 of the first via V1 on the substrate, respectively, the projection of the second branch segment 432 on the substrate at least partially overlaps with the projection of the first boundary L11 and the second boundary L12 of the second via V2 on the substrate, respectively, and the projection of the third branch segment 433 on the substrate at least partially overlaps with the projection of the first boundary L11, the second boundary L12, and the fourth boundary L14 of the third via V3 on the substrate, respectively.

[0268] In an example embodiment, as shown in FIG. 28, the distance a4 between the projection of the boundary of the first sub-electrode 441 on the substrate and the projection of the third boundary L13 of the first via V1 on the substrate is in the range of 1 micrometer to 1.5 micrometers, and the distance c4 between the projection of the boundary of the second sub-electrode 442 on the substrate and the projection of the fourth boundary L14 of the third via V3 on the substrate is in the range of 1 micrometer to 1.5 micrometers.

[0269] In an example embodiment, as shown in FIGS. 27 and 28, the distance between the normal projection of the boundary of the electrode connecting segment 434 on the substrate and the first boundary L11 of at least one of the first via V1, the second via V2 and the third via V3 along the second direction D2 is greater than the distance between the first boundary L11 and the second boundary L12 of at least one of the first via V1, the second via V2 and the third via V3 along the second direction D2, and the distance between the normal projection of the boundary of the first branch segment 431 on the substrate and the second boundary L12 of at least one of the first via V1, the second via V2 and the third via V3 along the second direction D2 is greater than the distance between the first boundary L11 and the second boundary L12 of at least one of the first via V1, the second via V2 and the third via V3 along the second direction D2.

[0270] In an example embodiment, as shown in FIGS. 27 and 28, the distance b4 between the normal projection of the boundary of at least one of the first sub-electrode 441 and the second sub-electrode 442 on the substrate and the normal projection of the second boundary L12 of at least one of the first via V1, the second via V2 and the third via V3 on the substrate along the second direction D2 is in the range of 1 micrometer to 1.5 micrometers.

[0271] In an example embodiment, as shown in FIG. 28, when the first electrode of the transistor device overlaps the normal projection of the plurality of vias on the substrate and the second electrode of the transistor device does not overlap the normal projection of the plurality of vias on the substrate, and the first electrode and the second electrode are misaligned with respect to the gate insulating layer in the first direction, the parasitic capacitance between the gate electrode and the first electrode and the parasitic capacitance between the gate electrode and the second electrode do not fluctuate. However, since the overlapping area of the via and the active layer is small, the transistor device provided in FIG. 28 has limited effect on improving the on-current of the transistor device.

[0272] In exemplary embodiments, FIG. 29 is a top view of a transistor device six, FIG. 30 is a top view of a transistor device seven, FIG. 31 is a top view of a transistor device eight, FIG. 32 is a top view of a transistor device nine, and FIG. 33 is a top view of a transistor device ten. As shown in FIGS. 29-33, the first electrode 53 includes an electrode connecting segment 533, a first branch segment 531, and a second branch segment 532, the electrode connecting segment 533 extends at least partially along a first direction D1, the first branch segment 531 and the second branch segment 532 are arranged along the first direction D1, and at least one branch segment extends along a second direction D2, the electrode connecting segment 533 is connected to the first branch segment 531 and the second branch segment 532, respectively; the first direction D1 intersects the second direction D2. The second electrode 54 extends along the second direction D2, and a projection of the second electrode 54 on the substrate is located between a projection of the first branch segment 531 on the substrate and a projection of the second branch segment 532 on the substrate; a projection of the second boundary L12 on the substrate is located on a side of the projection of the first boundary L11 on the substrate close to the projection of the electrode connecting segment 533 on the substrate.

[0273] In exemplary embodiments, as shown in FIG. 29, the first boundary L11, the second boundary L12, the third boundary L13, and the fourth boundary L14 are linear. The projection of the electrode connecting segment 533 on the substrate does not overlap the projections of the plurality of boundaries on the substrate, the projection of the first branch segment 531 on the substrate overlaps the projections of the first boundary L11, the second boundary L12, and the third boundary L13 on the substrate, respectively, the projection of the second branch segment 532 on the substrate overlaps the projections of the first boundary L11, the second boundary L12, and the fourth boundary on the substrate, respectively, and the projection of the second electrode 54 on the substrate overlaps the projections of the first boundary L11 and the second boundary L12 on the substrate, respectively.

[0274] In exemplary embodiments, as shown in FIG. 29, a distance x1 between the projection of the boundary of the first branch segment 531 on the substrate close to the second electrode 54 and the projection of the third boundary L13 on the substrate along the first direction D1 is in a range of 1-1.5 microns, a distance y1 between the projection of the boundary of the second electrode 54 on the substrate close to the electrode connecting segment 533 and the projection of the second boundary L12 on the substrate along the second direction D2 is in a range of 1-1.5 microns, and a distance z1 between the projection of the boundary of the third branch segment on the substrate close to the second electrode 54 and the projection of the fourth boundary on the substrate along the first direction D1 is in a range of 1-1.5 microns.

[0275] In the exemplary embodiment, in the transistor device provided in FIG. 29, since the orthogonal projection of the first electrode of the transistor device on the substrate overlaps with the orthogonal projection of the third boundary and the fourth boundary on the substrate, respectively, and the orthogonal projection of the second electrode of the transistor device on the substrate overlaps with the orthogonal projection of the first boundary and the second boundary on the substrate, the parasitic capacitance between the gate electrode and the first electrode and the parasitic capacitance between the gate electrode and the second electrode do not fluctuate when the first electrode and the second electrode are misaligned in the first direction with respect to the gate insulating layer. However, since the thickness of the channel region of the active layer between the first electrode and the second electrode is not thinned, the transistor device provided in FIG. 29 has limited effect on the improvement of the on-current of the transistor device.

[0276] In the exemplary embodiment, as shown in FIGS. 30 and 31, the first boundary L11, the third boundary L13, and the fourth boundary L14 are linear, and the shape of the second boundary L12 is adapted to the shape of the electrode connecting segment 533. The shape of the electrode connecting segment 533 can be an inverted "U" shape.

[0277] In the exemplary embodiment, as shown in FIGS. 30 and 31, the orthogonal projection of the electrode connecting segment 533 on the substrate overlaps with the orthogonal projection of the second boundary L12 on the substrate, the orthogonal projection of the first branch segment 531 on the substrate overlaps with the orthogonal projection of the third boundary L13 on the substrate and does not overlap with the orthogonal projection of the first boundary L11 on the substrate, the orthogonal projection of the second branch segment 532 on the substrate at least partially overlaps with the orthogonal projection of the fourth boundary L14 on the substrate and does not overlap with the orthogonal projection of the first boundary L11 on the substrate, and the orthogonal projection of the second electrode 54 on the substrate at least partially overlaps with the orthogonal projection of the first boundary L11 on the substrate.

[0278] In the exemplary embodiment, as shown in FIGS. 30 and 31, the distance x2 between the orthogonal projection of the first branch segment 531 on the substrate near the boundary of the first sub-electrode and the orthogonal projection of the third boundary L13 on the substrate in the first direction D1 is in the range of 1 to 1.5 microns, the distance y2 between the orthogonal projection of the electrode connecting segment 533 on the substrate near the boundary of the second electrode 54 and the orthogonal projection of the second boundary L12 on the substrate near the boundary of the second electrode 54 in the second direction D2 is in the range of 1 to 1.5 microns, and the distance z2 between the orthogonal projection of the third branch segment on the substrate near the boundary of the second electrode 54 and the orthogonal projection of the fourth boundary L14 on the substrate in the first direction D1 is in the range of 1 to 1.5 microns.

[0279] In the exemplary embodiment, the shape of the via in FIG. 30 is rectangular.

[0280] In an exemplary embodiment, as shown in FIG. 31, the plurality of boundaries of the via VV further comprises: a first protruding boundary L21, a second protruding boundary L22, a third protruding boundary L23, a fourth protruding boundary L24, a fifth protruding boundary L25, a sixth protruding boundary L26, a seventh protruding boundary L27, and an eighth protruding boundary L28, the first protruding boundary L21, the third protruding boundary L23, the fifth protruding boundary L25, and the seventh protruding boundary L27 extend along the first direction D1, and the second protruding boundary L22, the fourth protruding boundary L24, the sixth protruding boundary L26, and the eighth protruding boundary L28 extend along the second direction D2.

[0281] In an exemplary embodiment, as shown in FIG. 31, the third boundary L13 is connected with the first boundary L11 through the first protruding boundary L21, the second protruding boundary L22, the third protruding boundary L23, and the fourth protruding boundary L24 in sequence, and the fourth boundary L14 is connected with the first boundary L11 through the fifth protruding boundary L25, the sixth protruding boundary L26, the seventh protruding boundary L27, and the eighth protruding boundary L28 in sequence.

[0282] In an exemplary embodiment, as shown in FIG. 31, the orthographic projection of the first electrode 53 and the second electrode 54 on the substrate does not overlap with the orthographic projection of at least one of the first protruding boundary L21, the second protruding boundary L22, the third protruding boundary L23, the fourth protruding boundary L24, the fifth protruding boundary L25, the sixth protruding boundary L26, the seventh protruding boundary L27, and the eighth protruding boundary L28 on the substrate.

[0283] In an exemplary embodiment, as shown in FIG. 31, the distance d1 between the second protruding boundary L22 and the fourth protruding boundary L24 along the second direction D2 is in the range of 1 micrometer to 4 micrometers.

[0284] In an exemplary embodiment, as shown in FIG. 31, the distance d2 between the sixth protruding boundary L26 and the eighth protruding boundary L28 along the second direction D2 is in the range of 1 micrometer to 4 micrometers.

[0285] In an exemplary embodiment, in the transistor device provided in FIG. 30 and FIG. 31, since the orthographic projection of the first electrode of the transistor device on the substrate overlaps with the orthographic projection of the second boundary, the third boundary, and the fourth boundary on the substrate respectively, and the orthographic projection of the second electrode of the transistor device on the substrate overlaps with the orthographic projection of the first boundary on the substrate, when the first electrode and the second electrode exist a misalignment in the first direction or the second direction relative to the gate insulating layer, the parasitic capacitance between the gate electrode and the first electrode and the parasitic capacitance between the gate electrode and the second electrode will not fluctuate. And since the thickness of the partial channel region of the active layer between the first electrode and the second electrode is thinned, the transistor device provided in FIG. 30 and FIG. 31 is better for improving the on-state current of the transistor device.

[0286] Fig. 31 provides the transistor device with the via VV with the first protruding branch segment to the eighth protruding branch segment compared to the transistor device provided in Fig. 30. The first protruding branch segment to the eighth protruding branch segment can be referred to as an optical compensation structure. The structure of the via in the transistor device provided in Fig. 31 after exposure approaches a right angle at the first boundary and the third boundary, and approaches a right angle at the first boundary and the fourth boundary, which can avoid the loss of the on-current caused by the structure of the via in the transistor device provided in Fig. 30 after exposure approaches an arc at the first boundary and the third boundary, and approaches an arc at the first boundary and the fourth boundary, and can improve the performance of the transistor device.

[0287] In an example embodiment, as shown in Fig. 32, the via VV includes a first via V1 and a second via V2, and the first via V1 and the second via V2 are arranged along the first direction D1.

[0288] In an example embodiment, as shown in Fig. 32, the first via V1 has a projection on the substrate between the projection on the substrate of the first branch segment 531 and the projection on the substrate of the second electrode 54, and the second via V2 has a projection on the substrate between the projection on the substrate of the second electrode 54 and the projection on the substrate of the second branch segment 532.

[0289] In an example embodiment, as shown in Fig. 32, the projection on the substrate of the third boundary L13 of the first via V1 and the projection on the substrate of the boundary of the first branch segment 531 close to the first via V1 along the first direction D1 are equal to or greater than 0, and the projection on the substrate of the fourth boundary L14 of the first via V1 and the projection on the substrate of the boundary of the second electrode 54 close to the first via V1 along the first direction D1 are equal to or greater than 0. Fig. 32 is an example in which the projection on the substrate of the third boundary L13 of the first via V1 and the projection on the substrate of the boundary of the first branch segment 531 close to the first via V1 along the first direction D1 are equal to 0, and the projection on the substrate of the fourth boundary L14 of the first via V1 and the projection on the substrate of the boundary of the second electrode 54 close to the first via V1 along the first direction D1 are equal to 0.

[0290] In an example embodiment, as shown in FIG. 32, the distance between the orthogonal projection of the third boundary L13 of the second via V2 on the substrate and the orthogonal projection of the boundary of the second electrode 54 close to the second via V2 on the substrate along the first direction D1 is greater than or equal to 0, and the distance between the orthogonal projection of the fourth boundary L14 of the second via V2 on the substrate and the orthogonal projection of the boundary of the second branch segment 532 close to the second via V2 on the substrate along the first direction D1 is greater than or equal to 0. FIG. 32 is an example in which the distance between the orthogonal projection of the third boundary L13 of the second via V2 on the substrate and the orthogonal projection of the boundary of the second electrode 54 close to the second via V2 on the substrate along the first direction D1 is equal to 0, and the distance between the orthogonal projection of the fourth boundary L14 of the second via V2 on the substrate and the orthogonal projection of the boundary of the second branch segment 532 close to the second via V2 on the substrate along the first direction D1 is equal to 0.

[0291] As shown in FIG. 32, the distance y3 between the orthogonal projection of the boundary of the second electrode 54 close to the electrode connection segment 533 on the substrate and the orthogonal projection of the second boundary L12 of at least one of the plurality of vias on the substrate along the second direction D2 is in the range of 1 micrometer to 1.5 micrometers.

[0292] The non-overlapping of the orthogonal projection of the first electrode and the second electrode on the substrate and the orthogonal projection of the via on the substrate in the transistor device provided in FIG. 32 can reduce the load of the transistor device, but when the first electrode and the second electrode exist a misalignment deviation in the first direction relative to the gate insulating layer, the parasitic capacitance between the gate electrode and the first electrode and the parasitic capacitance between the gate electrode and the second electrode will fluctuate.

[0293] In an example embodiment, as shown in FIG. 33, the via includes: a first via V1 and a second via V2, and the first via V1 and the second via V2 are arranged along the first direction D1.

[0294] In an example embodiment, as shown in FIG. 33, the orthogonal projection of the first via V1 on the substrate at least partially overlaps the orthogonal projection of the first branch segment 531 on the substrate, and does not overlap the orthogonal projection of the second electrode 54 on the substrate, and the orthogonal projection of the second via V2 on the substrate at least partially overlaps the orthogonal projection of the second branch segment 532 on the substrate, and does not overlap the orthogonal projection of the second electrode 54 on the substrate. The orthogonal projection of the first branch segment 531 on the substrate at least partially overlaps the orthogonal projection of the first boundary L11, the second boundary L12 and the third boundary L13 of the first via V1 on the substrate, and the orthogonal projection of the second branch segment 532 on the substrate at least partially overlaps the orthogonal projection of the first boundary L11, the second boundary L12 and the fourth boundary L14 of the third via V3 on the substrate.

[0295] In an example embodiment, as shown in FIG. 33, the distance x4 between the normal projection on the substrate of the boundary of the first branch segment 531 close to the second electrode 54 and the normal projection on the substrate of the third boundary L13 of the first via V1 is in the range of 1 to 1.5 microns, the distance y4 between the normal projection on the substrate of the boundary of the second electrode 54 close to the electrode connecting segment 533 and the normal projection on the substrate of the second boundary L12 of at least one of the plurality of vias along the second direction D2 is in the range of 1 to 1.5 microns, and the distance z4 between the normal projection on the substrate of the boundary of the second branch segment 532 close to the second electrode 54 and the normal projection on the substrate of the fourth boundary L14 of the second via V2 is in the range of 1 to 1.5 microns.

[0296] In an example embodiment, as shown in FIGS. 32 and 33, the distance between the normal projection on the substrate of the boundary of the second electrode 54 close to the electrode connecting segment 533 and the first boundary L11 of the plurality of vias along the second direction D2 is greater than the distance between the first boundary L11 and the second boundary L12 of the plurality of vias along the second direction D2, and the distance between the normal projection on the substrate of the boundary of the first branch segment 531 away from the electrode connecting segment 533 and the second boundary L12 of at least one of the first via and the second via V2 along the second direction D2 is greater than the distance between the first boundary L11 and the second boundary L12 of at least one of the first via and the second via V2 along the second direction D2.

[0297] In an example embodiment, in the transistor device provided in FIG. 33, due to the normal projection on the substrate of the first electrode of the transistor device overlapping with the normal projection on the substrate of the plurality of vias respectively, and the normal projection on the substrate of the second electrode of the transistor device not overlapping with the normal projection on the substrate of the vias, when the first electrode and the second electrode have a misalignment in the first direction relative to the gate insulating layer, the parasitic capacitance between the gate electrode and the first electrode and the parasitic capacitance between the gate electrode and the second electrode do not fluctuate. However, due to the small overlapping area between the vias and the active layer, the transistor device provided in FIG. 33 has limited effect on improving the on-current of the transistor device.

[0298] The transistor devices provided in FIGS. 24 to 28 are equivalent to the parallel connection of the two transistor devices provided in FIGS. 29 to 33. The shape of the first electrode in the transistor devices in FIGS. 24 to 33 is in the shape of a “U” letter.

[0299] In an exemplary embodiment, FIG. 34 is a plan view XI I of a transistor device, FIG. 35 is a plan view XII of a transistor device, FIG. 36 is a plan view XIII of a transistor device, and FIG. 37 is a plan view XIV of a transistor device. As shown in FIGS. 34 to 37, the transistor device includes a gate electrode 61, an active layer 62, a first electrode 63, and a second electrode 64. Among them, the first electrode 63 and the second electrode 64 extend along a second direction D2. The orthogonal projection of the active layer 62 on the substrate is within the range of the orthogonal projection of the gate electrode 61 on the substrate, and the orthogonal projection of the via VV on the substrate is within the range of the orthogonal projection of the active layer 62 on the substrate. The orthogonal projection of a part of at least one of the first electrode 63 and the second electrode 64 on the substrate does not overlap with the orthogonal projection of the gate electrode 61 on the substrate.

[0300] In an exemplary embodiment, as shown in FIGS. 34 to 37, the via includes a plurality of boundaries including a first boundary L11, a second boundary L12, a third boundary L13, and a fourth boundary L14, the first boundary L11 and the second boundary L12 extend along the first direction D1, the third boundary L13 and the fourth boundary L14 extend along the second direction D2, the first boundary L11, the fourth boundary L14, the second boundary L12, and the third boundary L13 are sequentially connected, and the first boundary L11, the second boundary L12, the third boundary L13, and the fourth boundary L14 are linear. The distance between the orthogonal projection of the first target boundary GL1 on the substrate and the orthogonal projection of the first boundary L11 on the substrate along the second direction D2 is less than the distance between the orthogonal projection of the first target boundary on the substrate and the orthogonal projection of the second boundary L12 on the substrate along the second direction D2, the distance between the orthogonal projection of the second target boundary GL2 on the substrate and the orthogonal projection of the second boundary L12 on the substrate along the second direction D2 is less than the distance between the orthogonal projection of the second target boundary on the substrate and the orthogonal projection of the first boundary L11 on the substrate along the second direction D2, the first target boundary is a boundary extending along the first direction D1, and the first electrode 63 and the active layer 62 overlap, and the second target boundary is a boundary extending along the first direction D1, and the second electrode 64 and the active layer 62 overlap.

[0301] In an exemplary embodiment, as shown in FIG. 34, the orthogonal projection of at least one of the first electrode 63 and the second electrode 64 on the substrate at least partially overlaps with the orthogonal projection of the first boundary L11 and the second boundary L12 on the substrate, respectively, and does not overlap with the orthogonal projection of the third boundary L13 and the fourth boundary L14 on the substrate.

[0302] In an exemplary embodiment, as shown in FIG. 34, the maximum distance r1 between the boundary on the substrate of the first electrode 63 close to the third boundary L13 and the orthogonal projection on the substrate of the third boundary L13 along the first direction D1 is in the range of 1 to 1.5 microns, the distance t1 between the orthogonal projection on the substrate of the first target boundary GL1 and the orthogonal projection on the substrate of the first boundary L11 along the second direction D2 is in the range of 1 to 1.5 microns, the distance t2 between the orthogonal projection on the substrate of the second target boundary GL2 and the orthogonal projection on the substrate of the second boundary L12 along the second direction D2 is in the range of 1 to 1.5 microns, and the maximum distance s1 between the boundary on the substrate of the second electrode 64 close to the fourth boundary L14 and the orthogonal projection on the substrate of the fourth boundary L14 along the first direction D1 is in the range of 1 to 1.5 microns.

[0303] In an exemplary embodiment, in the transistor device provided in FIG. 34, due to the orthogonal projection on the substrate of the first electrode and the second electrode of the transistor device respectively overlapping with the orthogonal projection on the substrate of the first boundary and the second boundary, when the first electrode and the second electrode are misaligned with respect to the gate insulating layer in the first direction and the second direction, the parasitic capacitance between the gate electrode and the first electrode and the parasitic capacitance between the gate electrode and the second electrode do not fluctuate. However, the active layer has a large channel area, and thus the transistor device provided in FIG. 34 has a relatively obvious effect on improving the on-current of the transistor device.

[0304] In an exemplary embodiment, as shown in FIGS. 35 and 36, the orthogonal projection on the substrate of the via VV does not overlap with the orthogonal projection on the substrate of the first electrode 63 and the second electrode 64.

[0305] In an exemplary embodiment, as shown in FIGS. 35 and 36, the distance between the boundary on the substrate of the first electrode 63 close to the via VV and the orthogonal projection on the substrate of the third boundary L13 of the via VV along the first direction D1 is greater than or equal to 0, and the distance between the boundary on the substrate of the second electrode 64 close to the via VV and the orthogonal projection on the substrate of the fourth boundary L14 of the via VV along the first direction D1 is greater than or equal to 0. FIGS. 35 and 36 are illustrative examples in which the distance between the boundary on the substrate of the first electrode 63 close to the via VV and the orthogonal projection on the substrate of the third boundary L13 of the via VV along the first direction D1 is equal to 0, and the distance between the boundary on the substrate of the second electrode 64 close to the via VV and the orthogonal projection on the substrate of the fourth boundary L14 of the via VV along the first direction D1 is equal to 0.

[0306] In an example embodiment, as shown in FIG. 35, the shape of the active layer 62 is adapted to the shape of the gate electrode 61, the distance between the normal projection of the boundary of the active layer 62 close to the first boundary L11 on the substrate and the normal projection of the first boundary L11 on the substrate along the second direction D2 is greater than the distance between the normal projection of the boundary of the active layer 62 close to the first boundary L11 on the substrate and the normal projection of the first target boundary GL1 on the substrate along the second direction D2; the distance between the normal projection of the boundary of the active layer 62 close to the second boundary L12 on the substrate and the normal projection of the second boundary L12 on the substrate along the second direction D2 is greater than the distance between the normal projection of the boundary of the active layer 62 close to the second boundary L12 on the substrate and the normal projection of the second target boundary GL2 on the substrate along the second direction D2.

[0307] In an example embodiment, as shown in FIG. 36, the distance between the normal projection of the boundary of the active layer 62 close to the first boundary L11 on the substrate and the normal projection of the first boundary L11 on the substrate along the second direction D2 is less than the distance between the normal projection of the boundary of the active layer 62 close to the first boundary L11 on the substrate and the normal projection of the first target boundary GL1 on the substrate along the second direction D2; the distance between the normal projection of the boundary of the active layer 62 close to the second boundary L12 on the substrate and the normal projection of the second boundary L12 on the substrate along the second direction D2 is less than the distance between the normal projection of the boundary of the active layer 62 close to the second boundary L12 on the substrate and the normal projection of the second target boundary GL2 on the substrate along the second direction D2.

[0308] In an example embodiment, the normal projection of the first electrode and the second electrode on the substrate in the transistor device provided in FIG. 35 and FIG. 36 does not overlap with the normal projection of the via on the substrate, which can reduce the load of the transistor device, but when the first electrode and the second electrode exist a misalignment deviation relative to the gate insulating layer in the first direction, the parasitic capacitance between the gate electrode and the first electrode and the parasitic capacitance between the gate electrode and the second electrode will fluctuate.

[0309] In an example embodiment, as shown in FIG. 37, the normal projection of the via VV on the substrate partially overlaps with the normal projection of the first electrode 63 on the substrate, and does not overlap with the normal projection of the second electrode 64 on the substrate. The normal projection of the first electrode 63 on the substrate overlaps with the normal projection of the first boundary L11 and the second boundary L12 on the substrate respectively.

[0310] In an example embodiment, as shown in FIG. 37, the distance t1 between the orthographic projection on the substrate of the boundary of the second electrode 64 close to the third boundary L13 and the orthographic projection on the substrate of the third boundary L13 along the first direction D1 is in the range of 1 to 1.5 microns, the maximum distance s2 between the orthographic projection on the substrate of the boundary of the first electrode 63 close to the fourth boundary L14 and the orthographic projection on the substrate of the fourth boundary L14 along the first direction D1 is in the range of 1 to 1.5 microns, the distance t1 between the orthographic projection on the substrate of the first target boundary GL1 and the orthographic projection on the substrate of the first boundary L11 along the second direction D2 is in the range of 1 to 1.5 microns, and the distance t2 between the orthographic projection on the substrate of the second target boundary GL2 and the orthographic projection on the substrate of the second boundary L12 along the second direction D2 is in the range of 1 to 1.5 microns.

[0311] In an example embodiment, as shown in FIG. 37, the active layer 62 is shaped to fit the gate electrode 61, the distance between the orthographic projection on the substrate of the boundary of the active layer 62 close to the first boundary L11 and the orthographic projection on the substrate of the first boundary L11 along the second direction D2 is greater than the distance between the orthographic projection on the substrate of the boundary of the active layer 62 close to the first boundary L11 and the orthographic projection on the substrate of the first target boundary GL1 along the second direction D2, and the distance between the orthographic projection on the substrate of the boundary of the active layer 62 close to the second boundary L12 and the orthographic projection on the substrate of the second boundary L12 along the second direction D2 is greater than the distance between the orthographic projection on the substrate of the boundary of the active layer 62 close to the second boundary L12 and the orthographic projection on the substrate of the second target boundary GL2 along the second direction D2.

[0312] In an example embodiment, in the transistor device provided in FIG. 37, due to the orthographic projection on the substrate of the first electrode of the transistor device respectively overlapping the orthographic projection on the substrate of the via, and the orthographic projection on the substrate of the second electrode of the transistor device not overlapping the orthographic projection on the substrate of the via, when the first electrode and the second electrode are misaligned relative to the gate insulating layer in the first direction, the parasitic capacitance between the gate electrode and the first electrode and the parasitic capacitance between the gate electrode and the second electrode do not fluctuate. However, due to the small overlapping area between the via and the active layer, the transistor device provided in FIG. 37 has limited effect on improving the on-current of the transistor device.

[0313] In an example embodiment, FIG. 38 is a fifteenth top view of a transistor device, FIG. 39 is a sixteenth top view of a transistor device, FIG. 40 is a seventeenth top view of a transistor device, FIG. 41 is an eighteenth top view of a transistor device, and FIG. 42 is a nineteenth top view of a transistor device. As shown in FIGS. 38 to 42, the transistor device includes a gate electrode 71, an active layer 72, a first electrode 73, and a second electrode 74.

[0314] In the example embodiment, as shown in FIGS. 38 to 42, the first electrode 73 includes: a first electrode connecting portion 731 and a second electrode connecting portion 732 connected to each other, the first electrode connecting portion 731 extends along the first direction D1, and the second electrode connecting portion 732 extends along the second direction D2; a part of the first electrode connecting portion 731 has a projection on the substrate that partially overlaps with a projection on the substrate of the active layer 72, another part of the first electrode connecting portion 731 has a projection on the substrate that does not overlap with a projection on the substrate of the gate electrode, and a projection on the substrate of the second electrode connecting portion 732 is within a range of a projection on the substrate of the active layer 72. The projection on the substrate of the active layer 72 is within a range of a projection on the substrate of the gate electrode 71, the projection on the substrate of the via hole VV is within a range of a projection on the substrate of the active layer 72, a part of the second electrode 74 has a projection on the substrate that partially overlaps with a projection on the substrate of the active layer 72, and another part of the second electrode 74 has a projection on the substrate that does not overlap with a projection on the substrate of the gate electrode.

[0315] In the example embodiment, as shown in FIGS. 38 to 42, the via hole VV includes: a plurality of boundaries, the plurality of boundaries includes: a first boundary L11, a second boundary L12, a third boundary L13, and a fourth boundary L14, the first boundary L11 and the second boundary L12 extend along the first direction D1, the third boundary L13 and the fourth boundary L14 extend along the second direction D2, the first boundary L11, the fourth boundary L14, the second boundary L12, and the third boundary L13 are connected in sequence, and the first boundary L11, the second boundary L12, the third boundary L13, and the fourth boundary L14 are in a linear shape. A distance between a projection on the substrate of the first target boundary GL1 and a projection on the substrate of the first boundary L11 along the second direction D2 is less than a distance between the projection on the substrate of the first target boundary GL1 and a projection on the substrate of the second boundary L12 along the second direction D2, a distance between a projection on the substrate of the second target boundary GL2 and the projection on the substrate of the second boundary L12 along the second direction D2 is less than a distance between the projection on the substrate of the second target boundary GL2 and the projection on the substrate of the first boundary L11 along the second direction D2, the first target boundary GL1 is a boundary close to the first boundary L11 and extending along the first direction D1 of the second electrode connecting portion 732, and the second target boundary GL2 is a boundary close to the first boundary L11 and extending along the first direction D1 of the second electrode connecting portion 732.

[0316] In an exemplary embodiment, as shown in FIG. 38, the orthogonal projection of the first electrode connecting portion 731 on the substrate at least partially overlaps with the orthogonal projection of the third boundary L13 on the substrate, the orthogonal projection of the second electrode connecting portion 732 on the substrate does not overlap with the orthogonal projections of the plurality of boundaries on the substrate, the orthogonal projection of the second electrode 74 on the substrate partially overlaps with the orthogonal projections of the first boundary L11 and the second boundary L12 on the substrate, and the orthogonal projection of the fourth boundary L14 on the substrate does not overlap.

[0317] In an exemplary embodiment, in the transistor device provided in FIG. 38, since the orthogonal projection of the first electrode of the transistor device on the substrate overlaps with the orthogonal projections of the first boundary and the second boundary on the substrate, and the orthogonal projection of the second electrode of the transistor device on the substrate overlaps with the orthogonal projections of the first boundary and the second boundary on the substrate, when the first electrode and the second electrode exist alignment deviation in the first direction and the second direction relative to the gate insulating layer, the parasitic capacitance between the gate electrode and the first electrode and the parasitic capacitance between the gate electrode and the second electrode do not fluctuate. However, the thinning area of the channel region of the active layer is large, and thus the transistor device provided in FIG. 38 has a relatively obvious effect on the improvement of the on-current of the transistor device.

[0318] In an exemplary embodiment, as shown in FIG. 39, the orthogonal projection of the first electrode connecting portion 731 on the substrate at least partially overlaps with the orthogonal projection of the third boundary L13 on the substrate, the orthogonal projection of the second electrode connecting portion 732 on the substrate partially overlaps with the orthogonal projections of the first boundary L11 and the second boundary L12 on the substrate, the orthogonal projection of the second electrode 74 on the substrate partially overlaps with the orthogonal projections of the first boundary L11 and the second boundary L12 on the substrate, and the orthogonal projection of the fourth boundary L14 on the substrate does not overlap.

[0319] In an exemplary embodiment, in the transistor device provided in FIG. 39, since the orthogonal projection of the first electrode of the transistor device on the substrate overlaps with the orthogonal projections of the first boundary, the second boundary and the third boundary on the substrate, and the orthogonal projection of the second electrode of the transistor device on the substrate overlaps with the orthogonal projections of the first boundary and the second boundary on the substrate, when the first electrode and the second electrode exist alignment deviation in the first direction and the second direction relative to the gate insulating layer, the parasitic capacitance between the gate electrode and the first electrode and the parasitic capacitance between the gate electrode and the second electrode do not fluctuate. However, the thinning area of the channel region of the active layer is not large, and thus the transistor device provided in FIG. 39 has an effective effect on the improvement of the on-current of the transistor device.

[0320] In an exemplary embodiment, as shown in FIGS. 40 and 41, the orthogonal projection of the via VV on the substrate does not overlap with the orthogonal projections of the first electrode 73 and the second electrode 74 on the substrate, and is located between the orthogonal projection of the second electrode connecting portion 732 on the substrate and the orthogonal projection of the second electrode 74 on the substrate.

[0321] In the example embodiment, as shown in FIGS. 40 and 41, the distance tl between the orthogonal projection on the substrate of the first target boundary GL1 close to the boundary of the via VV and the orthogonal projection on the substrate of the third boundary L13 of the via VV along the first direction Dl is greater than or equal to 0, and the distance t2 between the orthogonal projection on the substrate of the second target boundary GL2 close to the boundary of the via VV and the orthogonal projection on the substrate of the fourth boundary L14 of the via along the first direction Dl is greater than or equal to 0. FIGS. 40 and 41 are described by way of example with the distance tl between the orthogonal projection on the substrate of the first target boundary GL1 close to the boundary of the via VV and the orthogonal projection on the substrate of the third boundary L13 of the via VV along the first direction Dl being equal to 0, and the distance t2 between the orthogonal projection on the substrate of the second target boundary GL2 close to the boundary of the via VV and the orthogonal projection on the substrate of the fourth boundary L14 of the via along the first direction Dl being equal to 0.

[0322] In the example embodiment, as shown in FIGS. 40 and 41, the distance tl between the orthogonal projection on the substrate of the first target boundary GL1 close to the boundary of the via VV and the orthogonal projection on the substrate of the third boundary L13 of the via VV along the first direction Dl is greater than or equal to 0, and the distance t2 between the orthogonal projection on the substrate of the second target boundary GL2 close to the boundary of the via VV and the orthogonal projection on the substrate of the fourth boundary L14 of the via along the first direction Dl is greater than or equal to 0. FIGS. 40 and 41 are described by way of example with the distance tl between the orthogonal projection on the substrate of the first target boundary GL1 close to the boundary of the via VV and the orthogonal projection on the substrate of the third boundary L13 of the via VV along the first direction Dl being equal to 0, and the distance t2 between the orthogonal projection on the substrate of the second target boundary GL2 close to the boundary of the via VV and the orthogonal projection on the substrate of the fourth boundary L14 of the via along the first direction Dl being equal to 0.

[0323] In the example embodiment, as shown in FIG. 40, the shape of the active layer 72 is adapted to the shape of the gate electrode 71, the distance between the orthogonal projection on the substrate of the boundary of the active layer 72 close to the first boundary L11 and the orthogonal projection on the substrate of the first boundary L11 along the second direction D2 is greater than the distance between the orthogonal projection on the substrate of the boundary of the active layer 72 close to the first boundary L11 and the orthogonal projection on the substrate of the first target boundary GL1 along the second direction D2, and the distance between the orthogonal projection on the substrate of the boundary of the active layer 72 close to the second boundary L12 and the orthogonal projection on the substrate of the second boundary L12 along the second direction D2 is greater than the distance between the orthogonal projection on the substrate of the boundary of the active layer 72 close to the second boundary L12 and the orthogonal projection on the substrate of the second target boundary GL2 along the second direction D2.

[0324] In an example embodiment, as shown in FIG. 41, the distance between the orthogonal projection on the substrate of the boundary of the active layer 72 close to the first boundary L11 and the orthogonal projection on the substrate of the first boundary L11 along the second direction D2 is smaller than the distance between the orthogonal projection on the substrate of the boundary of the active layer 72 close to the first boundary L11 and the orthogonal projection on the substrate of the first target boundary GL1 along the second direction D2; the distance between the orthogonal projection on the substrate of the boundary of the active layer 72 close to the second boundary L12 and the orthogonal projection on the substrate of the second boundary L12 along the second direction D2 is smaller than the distance between the orthogonal projection on the substrate of the boundary of the active layer 72 close to the second boundary L12 and the orthogonal projection on the substrate of the second target boundary GL2 along the second direction D2.

[0325] The non-overlapping of the orthogonal projection on the substrate of the first electrode and the second electrode in the transistor device provided in FIG. 40 and FIG. 41 and the orthogonal projection on the substrate of the via can reduce the load of the transistor device, but when the first electrode and the second electrode exist alignment deviation in the first direction relative to the gate insulating layer, the parasitic capacitance between the gate electrode and the first electrode and the parasitic capacitance between the gate electrode and the second electrode will fluctuate.

[0326] In an example embodiment, as shown in FIG. 42, the orthogonal projection on the substrate of the via VV partially overlaps with the orthogonal projection on the substrate of the first electrode 73 and does not overlap with the orthogonal projection on the substrate of the second electrode 74, and the orthogonal projection on the substrate of the first electrode connecting part 731 partially overlaps with the orthogonal projection on the substrate of the third boundary L13, and the orthogonal projection on the substrate of the second electrode connecting part 732 partially overlaps with the orthogonal projection on the substrate of the first boundary L11 and the second boundary L12 respectively.

[0327] In an example embodiment, as shown in FIG. 42, the active layer 72 and the gate electrode 71 are shaped to fit, the distance between the orthogonal projection on the substrate of the boundary of the active layer 72 close to the first boundary L11 and the orthogonal projection on the substrate of the first boundary L11 along the second direction D2 is greater than the distance between the orthogonal projection on the substrate of the boundary of the active layer 72 close to the first boundary L11 and the orthogonal projection on the substrate of the first target boundary GL1 along the second direction D2, and the distance between the orthogonal projection on the substrate of the boundary of the active layer 72 close to the second boundary L12 and the orthogonal projection on the substrate of the second boundary L12 along the second direction D2 is greater than the distance between the orthogonal projection on the substrate of the boundary of the active layer 72 close to the second boundary L12 and the orthogonal projection on the substrate of the second target boundary GL2 along the second direction D2.

[0328] In the exemplary embodiments, in the transistor device provided in FIG. 42, due to the fact that the orthogonal projection of the first electrode of the transistor device on the substrate overlaps with the orthogonal projection of the via on the substrate, and the orthogonal projection of the second electrode of the transistor device on the substrate does not overlap with the orthogonal projection of the via on the substrate, the parasitic capacitance between the gate electrode and the first electrode and the parasitic capacitance between the gate electrode and the second electrode will not fluctuate when the first electrode and the second electrode are misaligned in the first direction relative to the gate insulating layer. However, due to the fact that the overlapping area between the via and the active layer is small, the transistor device provided in FIG. 42 has limited effect on the improvement of the on-current of the transistor device.

[0329] In the exemplary embodiments, FIG. 43 is a top view XX of a transistor device, FIG. 44 is a top view XXI of a transistor device, FIG. 45 is a top view XXII of a transistor device, FIG. 46 is a top view XXIII of a transistor device, and FIG. 47 is a top view XXIV of a transistor device. As shown in FIGS. 43-47, the transistor device includes a gate electrode 81, an active layer 82, a first electrode 83, and a second electrode 84.

[0330] In the exemplary embodiments, as shown in FIGS. 43-47, the active layer 82 includes a first active connection portion 821 and a second active connection portion 822 connected to each other, the first active connection portion 821 extends at least partially along the first direction D1, and the second active connection portion 822 extends at least partially along the second direction D2; the first electrode 83 includes a first electrode connection portion 831 and a second electrode connection portion 832 connected to each other, the first electrode connection portion 831 extends along the first direction D1, and the second electrode connection portion 832 extends along the second direction D2. Among them, the orthogonal projection of a part of the first active connection portion 821 on the substrate overlaps with the orthogonal projection of the gate electrode 81 on the substrate, the orthogonal projection of another part of the first electrode connection portion 831 on the substrate does not overlap with the orthogonal projection of the gate electrode 81 on the substrate, the orthogonal projection of a part of the second active connection portion 822 on the substrate overlaps with the orthogonal projection of the gate electrode 81 on the substrate, the orthogonal projection of another part of the second electrode connection portion 832 on the substrate does not overlap with the orthogonal projection of the gate electrode 81 on the substrate, the orthogonal projection of the first electrode 83 on the substrate is within the range of the orthogonal projection of the first active connection portion 821 on the substrate, and the orthogonal projection of the second electrode 84 on the substrate is within the range of the orthogonal projection of the second active connection portion 822 on the substrate.

[0331] In the exemplary embodiments, as shown in FIGS. 43-47, the orthogonal projection of the via VV on the substrate is within the range of the orthogonal projection of the active layer 82 on the substrate and overlaps with the orthogonal projection of the first active connection portion 821 and the second active connection portion 822 on the substrate.

[0332] In an example embodiment, as shown in FIGS. 43-47, the via hole includes a plurality of boundaries, the plurality of boundaries includes a first boundary L11, a second boundary L12, a third boundary L13, and a fourth boundary L14, the first boundary L11 and the second boundary L12 extend along a first direction D1, the third boundary L13 and the fourth boundary L14 extend along a second direction D2, the first boundary L11, the fourth boundary L14, the second boundary L12, and the third boundary L13 are sequentially connected, the first boundary L11, the second boundary L12, the third boundary L13, and the fourth boundary L14 are in a straight line shape; a distance between a projection of the first target boundary GL1 on the substrate and a projection of the first boundary L11 on the substrate along the second direction D2 is less than a distance between a projection of the first target boundary GL1 on the substrate and a projection of the second boundary L12 on the substrate along the second direction D2, a distance between a projection of the second target boundary GL2 on the substrate and a projection of the second boundary L12 on the substrate along the second direction D2 is less than a distance between a projection of the second target boundary GL2 on the substrate and a projection of the first boundary L11 on the substrate along the second direction D2, the first target boundary GL1 is a boundary close to the first boundary L11 and extending along the first direction D1 of the second electrode connecting portion, and the second target boundary GL2 is a boundary close to the first boundary L11 and extending along the first direction D1 of the second electrode connecting portion.

[0333] In an example embodiment, as shown in FIG. 43, the first electrode connecting portion 831 at least partially overlaps with a projection of the third boundary L13 on the substrate, a projection of the second electrode connecting portion 832 on the substrate does not overlap with a projection of the plurality of boundaries on the substrate, a projection of the second electrode 84 on the substrate partially overlaps with a projection of the first boundary L11 and the second boundary L12 on the substrate, and a projection of the fourth boundary L14 on the substrate does not overlap.

[0334] In an example embodiment, in the transistor device provided in FIG. 43, because the projection of the first electrode of the transistor device on the substrate overlaps with the projection of the third boundary on the substrate, and the projection of the second electrode on the substrate overlaps with the projection of the first boundary and the second boundary on the substrate respectively, when the first electrode and the second electrode have a misalignment deviation in the first direction and the second direction relative to the gate insulating layer, the parasitic capacitance between the gate electrode and the first electrode and the parasitic capacitance between the gate electrode and the second electrode will not fluctuate. However, the channel region thinning area of the active layer is relatively large, and therefore, the transistor device provided in FIG. 43 has a relatively obvious effect on improving the on-current of the transistor device.

[0335] In the exemplary embodiment, as shown in FIG. 44, the orthogonal projection of the first electrode connecting portion 831 on the substrate at least partially overlaps the orthogonal projection of the third boundary L13 on the substrate, the orthogonal projection of the second electrode connecting portion 832 on the substrate partially overlaps the orthogonal projection of the first boundary L11 and the second boundary L12 on the substrate, respectively, the orthogonal projection of the second electrode 74 on the substrate partially overlaps the orthogonal projection of the first boundary L11 and the second boundary L12 on the substrate, and the orthogonal projection of the fourth boundary L14 on the substrate does not overlap.

[0336] In the exemplary embodiment, in the transistor device provided in FIG. 44, because the orthogonal projection of the first electrode of the transistor device on the substrate overlaps the orthogonal projection of the first boundary, the second boundary and the third boundary on the substrate, and the orthogonal projection of the second electrode of the transistor device on the substrate overlaps the orthogonal projection of the first boundary and the second boundary on the substrate, when the first electrode and the second electrode have alignment deviation in the first direction and the second direction relative to the gate insulating layer, the parasitic capacitance between the gate electrode and the first electrode and the parasitic capacitance between the gate electrode and the second electrode do not fluctuate. However, the active layer channel region thinning area is not large, and thus the transistor device provided in FIG. 44 is effective for improving the on-state current of the transistor device.

[0337] In the exemplary embodiment, as shown in FIG. 45 and FIG. 46, the orthogonal projection of the via VV on the substrate does not overlap the orthogonal projection of the first electrode 83 and the second electrode 84 on the substrate, respectively, and is located between the orthogonal projection of the second electrode connecting portion 832 on the substrate and the orthogonal projection of the second electrode 84 on the substrate.

[0338] In the exemplary embodiment, as shown in FIG. 45 and FIG. 46, the distance between the orthogonal projection of the first electrode 83 close to the boundary of the via VV on the substrate and the orthogonal projection of the third boundary L13 of the via VV on the substrate along the first direction D1 is greater than or equal to 0, and the distance between the orthogonal projection of the second electrode 84 close to the boundary of the via VV on the substrate and the orthogonal projection of the fourth boundary L14 of the via on the substrate along the first direction D1 is greater than or equal to 0. FIG. 45 and FIG. 46 are described by taking an example in which the distance between the orthogonal projection of the first electrode 83 close to the boundary of the via VV on the substrate and the orthogonal projection of the third boundary L13 of the via VV on the substrate along the first direction D1 is equal to 0, and the distance between the orthogonal projection of the second electrode 84 close to the boundary of the via VV on the substrate and the orthogonal projection of the fourth boundary L14 of the via on the substrate along the first direction D1 is equal to 0.

[0339] In an example embodiment, as shown in FIG. 45, the distance between the normal projection of the boundary of the active layer 82 close to the first boundary L11 on the substrate and the normal projection of the first boundary L11 on the substrate along the second direction D2 is greater than the distance between the normal projection of the boundary of the active layer 82 close to the first boundary L11 on the substrate and the normal projection of the first target boundary GL1 on the substrate along the second direction D2; the distance between the normal projection of the boundary of the active layer 82 close to the second boundary L12 on the substrate and the normal projection of the second boundary L12 on the substrate along the second direction D2 is greater than the distance between the normal projection of the boundary of the active layer 82 close to the second boundary L12 on the substrate and the normal projection of the second target boundary GL2 on the substrate along the second direction D2.

[0340] In an example embodiment, as shown in FIG. 46, the distance between the normal projection of the boundary of the active layer 82 close to the first boundary L11 on the substrate and the normal projection of the first boundary L11 on the substrate along the second direction D2 is less than the distance between the normal projection of the boundary of the active layer 82 close to the first boundary L11 on the substrate and the normal projection of the first target boundary GL1 on the substrate along the second direction D2; the distance between the normal projection of the boundary of the active layer 82 close to the second boundary L12 on the substrate and the normal projection of the second boundary L12 on the substrate along the second direction D2 is less than the distance between the normal projection of the boundary of the active layer 82 close to the second boundary L12 on the substrate and the normal projection of the second target boundary GL2 on the substrate along the second direction D2.

[0341] In an example embodiment, as shown in FIGS. 45 and 46, the distance t1 between the normal projection of the first target boundary GL1 on the substrate and the normal projection of the first boundary L11 on the substrate along the second direction D2 is in the range of 1 micrometer to 1.5 micrometers, and the distance t2 between the normal projection of the second target boundary GL2 on the substrate and the normal projection of the second boundary L12 on the substrate along the second direction D2 is in the range of 1 micrometer to 1.5 micrometers.

[0342] The normal projection of the first electrode and the second electrode on the substrate in the transistor device provided by FIGS. 45 and 46 does not overlap with the normal projection of the via on the substrate, which can reduce the load of the transistor device, but when the first electrode and the second electrode exist in the alignment deviation relative to the gate insulating layer in the first direction, the parasitic capacitance between the gate electrode and the first electrode and the parasitic capacitance between the gate electrode and the second electrode will fluctuate.

[0343] In an example embodiment, as shown in FIG. 47, the orthogonal projection of the via VV on the substrate partially overlaps with the orthogonal projection of the first electrode 83 on the substrate, and does not overlap with the orthogonal projection of the second electrode 84 on the substrate, and the orthogonal projection of the first electrode connecting portion 831 on the substrate partially overlaps with the orthogonal projection of the third boundary L13 on the substrate, and the orthogonal projection of the second electrode connecting portion 832 on the substrate partially overlaps with the orthogonal projection of the first boundary L11 and the second boundary L12 on the substrate respectively.

[0344] In an example embodiment, as shown in FIG. 47, the distance between the orthogonal projection of the boundary of the active layer 82 close to the first boundary L11 on the substrate and the orthogonal projection of the first boundary L11 on the substrate along the second direction D2 is greater than the distance between the orthogonal projection of the boundary of the active layer 82 close to the first boundary L11 on the substrate and the orthogonal projection of the first target boundary GL1 on the substrate along the second direction D2, and the distance between the orthogonal projection of the boundary of the active layer 82 close to the second boundary L12 on the substrate and the orthogonal projection of the second boundary L12 on the substrate along the second direction D2 is greater than the distance between the orthogonal projection of the boundary of the active layer 82 close to the second boundary L12 on the substrate and the orthogonal projection of the second target boundary GL2 on the substrate along the second direction D2.

[0345] In an example embodiment, in the transistor device provided in FIG. 43, when the first electrode and the second electrode of the transistor device exist a misalignment in the first direction relative to the gate insulating layer, the parasitic capacitance between the gate electrode and the first electrode and the parasitic capacitance between the gate electrode and the second electrode will not fluctuate due to the orthogonal projection of the first electrode of the transistor device on the substrate respectively overlapping with the orthogonal projection of the via on the substrate, and the orthogonal projection of the second electrode of the transistor device on the substrate not overlapping with the orthogonal projection of the via on the substrate. However, since the overlapping area between the via and the active layer is small, the transistor device provided in FIG. 43 has limited effect on improving the on-current of the transistor device.

[0346] FIG. 48 is a top view of a transistor device twenty-five, FIG. 49 is a top view of a transistor device twenty-six, FIG. 50 is a top view of a transistor device twenty-seven, FIG. 51 is a top view of a transistor device twenty-eight, FIG. 52 is a top view of a transistor device twenty-nine, FIG. 53 is a top view of a transistor device thirty, and FIG. 54 is a top view of a transistor device thirty-one. As shown in FIGS. 48-54, the transistor device includes a gate electrode 91, an active layer 92, a first electrode 93, and a second electrode 94.

[0347] In an example embodiment, as shown in FIGS. 48-54, the first electrode 93 includes a first electrode connecting portion 931, a second electrode connecting portion 932, a third electrode connecting portion 933, and a fourth electrode connecting portion 934. The first electrode connecting portion 931 and the fourth electrode connecting portion 934 extend along the first direction D1, the third electrode connecting portion 933 extends along the second direction D2, the second electrode connecting portion 932 is connected with the first electrode connecting portion 931 and the third electrode connecting portion 933 respectively, the first electrode connecting portion 931 is arranged at an obtuse angle with the second electrode connecting portion 932, the second electrode connecting portion 932 is arranged at an obtuse angle with the third electrode connecting portion 933, the fourth electrode connecting portion 934 is arranged at a right angle with the third electrode connecting portion 933, and the second electrode 94 extends along the second direction D2. The orthographic projection of at least one of the first electrode 93 and the second electrode 94 on the substrate does not overlap with the orthographic projection of the gate electrode 91 on the substrate.

[0348] In an example embodiment, as shown in FIGS. 48-54, the orthographic projection of the active layer 92 on the substrate is located within the range of the orthographic projection of the gate electrode 91 on the substrate.

[0349] In an example embodiment, as shown in FIG. 48, the orthographic projection of the active layer 92 on the substrate is located within the range of the orthographic projection of the via on the substrate, or the orthographic projection of the via on the substrate is located within the range of the orthographic projection of the active layer 92 on the substrate. The via includes a first boundary L11, a second boundary L12, a third boundary L13, and a fourth boundary L14. The first boundary L11 and the second boundary L12 extend along the first direction D1, the third boundary L13 and the fourth boundary L14 extend along the second direction D2, the first boundary L11, the fourth boundary L14, the second boundary L12, and the third boundary L13 are connected in sequence, and the first boundary L11, the second boundary L12, the third boundary L13, and the fourth boundary L14 are linear.

[0350] In an example embodiment, as shown in FIG. 48, the orthographic projection of the second electrode 94 on the substrate overlaps with the orthographic projection of the second boundary L12 on the substrate, the orthographic projection of the first electrode connecting portion 931 on the substrate overlaps with the orthographic projection of the third boundary L13 on the substrate, the orthographic projection of the second electrode connecting portion 932 and the third electrode connecting portion 933 on the substrate does not overlap with the orthographic projection of the plurality of boundaries on the substrate, and the orthographic projection of the fourth electrode connecting portion 934 on the substrate overlaps with the orthographic projection of the fourth boundary L14 on the substrate.

[0351] In the exemplary embodiment, in the transistor device provided in FIG. 48, the normal projection of the first electrode of the transistor device on the substrate overlaps the normal projection of the third boundary and the fourth boundary on the substrate, respectively, and the normal projection of the second electrode of the transistor device on the substrate overlaps the normal projection of the second boundary on the substrate, so that the parasitic capacitance between the gate electrode and the first electrode and the parasitic capacitance between the gate electrode and the second electrode do not fluctuate when the first electrode and the second electrode are misaligned in the first direction with respect to the gate insulating layer. However, the thickness of the channel region of the active layer between the first electrode and the second electrode is thinned overall, so that the transistor device provided in FIG. 48 has a relatively obvious effect on improving the on-current of the transistor device.

[0352] In the exemplary embodiment, as shown in FIG. 49, the normal projection of the via VV on the substrate is located within the range of the normal projection of the active layer 92 on the substrate, the via VV includes a first boundary L21, a second boundary L22, a third boundary L23, a fourth boundary L24, and a fifth boundary L25; the first boundary L21 and the second boundary L22 extend along the first direction D1, the third boundary L23 and the fourth boundary L24 extend along the second direction D2, the first boundary L21, the fifth boundary L25, the fourth boundary L24, the second boundary L22, and the third boundary L23 are sequentially connected, the first boundary L21, the second boundary L22, the third boundary L23, the fourth boundary L24, and the fifth boundary L25 are linear in shape, the fifth boundary L25 is arranged at an obtuse angle with the first boundary L21, and the fourth boundary L24 is arranged at an obtuse angle with the fifth boundary L25.

[0353] In the exemplary embodiment, as shown in FIG. 49, the normal projection of the first electrode connection part 931 on the substrate overlaps the normal projection of the first boundary L21 and the third boundary L23 on the substrate, respectively, the normal projection of the second electrode connection part 932 on the substrate overlaps the normal projection of the fifth boundary on the substrate, the normal projection of the third electrode connection part 933 on the substrate overlaps the normal projection of the fourth boundary L24 on the substrate, and the normal projection of the fourth electrode connection part 934 on the substrate does not overlap the normal projection of the plurality of boundaries on the substrate.

[0354] In the exemplary embodiment, as shown in FIG. 49, the first electrode of the transistor device is overlapped with the first boundary, the third boundary, the fourth boundary and the fifth boundary on the substrate, respectively, and the second electrode of the transistor device is overlapped with the second boundary on the substrate, so that the parasitic capacitance between the gate electrode and the first electrode and the parasitic capacitance between the gate electrode and the second electrode do not fluctuate when the first electrode and the second electrode are misaligned in the first direction relative to the gate insulating layer. The thickness of the channel region of the active layer between the first electrode and the second electrode is reduced, so that the transistor device shown in FIG. 49 has a more obvious effect on the improvement of the on-current of the transistor device.

[0355] In the exemplary embodiment, as shown in FIG. 54, the via V1 is located within the projection of the active layer 92 on the substrate, and the via V1 includes a first boundary L41, a second boundary L42, a third boundary L43, a fourth boundary L44 and a fifth boundary L45. The first boundary L41 and the second boundary L42 extend along the first direction D1, the third boundary L43 and the fourth boundary L44 extend along the second direction D2, the first boundary L41, the fifth boundary L45, the fourth boundary L44, the second boundary L42 and the third boundary L43 are sequentially connected, the first boundary L41, the second boundary L42, the third boundary L43, the fourth boundary L44 and the fifth boundary L45 are linear, the fifth boundary L45 is arranged at an obtuse angle with the first boundary L41, and the fourth boundary L44 is arranged at an obtuse angle with the fifth boundary L45.

[0356] In the exemplary embodiment, as shown in FIG. 54, the projection of the first electrode 93 on the substrate does not overlap with the projections of the plurality of boundaries on the substrate, the projection of the second electrode 93 on the substrate overlaps with the projection of the second boundary L42 on the substrate, and the distance between the boundary of the second boundary L42 on the substrate and the boundary of the active layer 92 close to the second boundary L42 along the second direction D2 is less than the distance between the projection of the second boundary L42 on the substrate and the boundary of the active layer 92 close to the second boundary L42 along the second direction D2.

[0357] In the example embodiment, as shown in FIG. 54, the distance between the orthographic projection on the substrate of the boundary of the first electrode connecting portion 931 near the boundary of the first boundary L31 of the via and the orthographic projection on the substrate of the first boundary L31 along the second direction is greater than or equal to 0, the distance between the orthographic projection on the substrate of the boundary of the second electrode connecting portion near the boundary of the second boundary of the via and the orthographic projection on the substrate of the second boundary is greater than or equal to 0, and the distance between the orthographic projection on the substrate of the boundary of the third electrode connecting portion near the boundary of the third boundary of the via and the orthographic projection on the substrate of the third boundary along the second direction is greater than or equal to 0. FIG. 54 is an example in which the distance between the orthographic projection on the substrate of the boundary of the first electrode connecting portion 931 near the boundary of the first boundary L31 of the via and the orthographic projection on the substrate of the first boundary L31 along the second direction is equal to 0, the distance between the orthographic projection on the substrate of the boundary of the second electrode connecting portion near the boundary of the second boundary of the via and the orthographic projection on the substrate of the second boundary is equal to 0, and the distance between the orthographic projection on the substrate of the boundary of the third electrode connecting portion near the boundary of the third boundary of the via and the orthographic projection on the substrate of the third boundary along the second direction is equal to 0.

[0358] In the example embodiment, in the transistor device provided in FIG. 54, because the orthographic projection on the substrate of the first electrode of the transistor device does not overlap the orthographic projections on the substrate of the multiple boundaries, and the orthographic projection on the substrate of the second electrode of the transistor device overlaps the orthographic projection on the substrate of the second boundary, when the first electrode and the second electrode have a misalignment in the first direction relative to the gate insulating layer, the parasitic capacitance between the gate electrode and the first electrode and the parasitic capacitance between the gate electrode and the second electrode fluctuate. However, because the overlapping area of the via and the active layer is small, the transistor device provided in FIG. 54 has a relatively obvious effect on the improvement of the on-current of the transistor device.

[0359] In the example embodiment, as shown in FIGS. 50 to 53, the orthographic projection on the substrate of the via VV is located in the range of the orthographic projection on the substrate of the active layer 92.

[0360] In an exemplary embodiment, as shown in FIGS. 50 to 53, the via hole VV includes a first boundary L31, a second boundary L32, a third boundary L33, a fourth boundary L34, a fifth boundary L35, a sixth boundary L36, and a seventh boundary L37, the first boundary L31, the fourth boundary L34, and the sixth boundary L36 extend along the second direction D2, the third boundary L33, the fifth boundary L35, and the seventh boundary L37 extend along the first direction D1, the first boundary L31 to the seventh boundary L37 are sequentially connected, and at least one of the first boundary L31 to the seventh boundary L37 is in a straight line shape. The second boundary L32 is disposed at an obtuse angle with respect to the first boundary L31 and the third boundary L33, the third boundary L33 and the fourth boundary L34 are disposed at a right angle, the fourth boundary L34 and the fifth boundary L35 are disposed at a right angle, the fifth boundary L35 and the sixth boundary L36 are disposed at a right angle, the sixth boundary L36 and the seventh boundary L37 are disposed at a right angle, the seventh boundary L37 and the first boundary L31 are disposed at a right angle, and a distance between the sixth boundary L36 and the first boundary L31 is less than a distance between the fourth boundary L34 and the first boundary L31.

[0361] In an exemplary embodiment, as shown in FIGS. 50 and 51, a projection of the first electrode connection portion 931 on the substrate overlaps a projection of the first boundary L31 and the seventh boundary L37 on the substrate, a projection of the second electrode connection portion 932 on the substrate overlaps a projection of the second boundary L32 on the substrate, a projection of the third electrode connection portion 933 on the substrate overlaps a projection of the third boundary L33 on the substrate, a projection of the fourth electrode connection portion 934 on the substrate does not overlap any of the plurality of boundaries, and a projection of the second electrode 94 on the substrate overlaps a projection of the fourth boundary L34, the fifth boundary L35, and the sixth boundary L36 on the substrate.

[0362] In an exemplary embodiment, FIG. 50 is an example of one transistor device. FIG. 51 is an example of two transistor devices. In FIG. 51, a target transistor device that is at least partially symmetrical to a first transistor device with respect to a straight line extending along the second direction is a second transistor device that is at least partially symmetrical to the first transistor device with respect to a straight line extending along the first direction; wherein the second electrode of the first transistor device and the second electrode of the second transistor device are the same electrode.

[0363] In the exemplary embodiments, in the transistor device provided in FIGS. 50 and 51, since the orthogonal projection of the first electrode of the transistor device on the substrate overlaps with the orthogonal projection of the first boundary, the second boundary, the third boundary and the seventh boundary on the substrate respectively, and the orthogonal projection of the second electrode of the transistor device on the substrate overlaps with the orthogonal projection of the fifth boundary and the sixth boundary on the substrate, when the first electrode and the second electrode are misaligned in the first direction relative to the gate insulating layer, the parasitic capacitance between the gate electrode and the first electrode and the parasitic capacitance between the gate electrode and the second electrode do not fluctuate. However, since the thickness of the channel region of the active layer between the first electrode and the second electrode is partially thinned, the transistor device provided in FIGS. 50 and 51 has limited effect on improving the on-current of the transistor device.

[0364] In the exemplary embodiments, as shown in FIGS. 52 and 53, the orthogonal projection of the first electrode 93 and the second electrode 94 on the substrate does not overlap with the orthogonal projection of the plurality of boundaries on the substrate.

[0365] In the exemplary embodiments, as shown in FIGS. 52 and 53, the distance between the orthogonal projection of the boundary of the via VV close to the first electrode connection part 931 on the substrate and the orthogonal projection of the first boundary L31 on the substrate is greater than or equal to 0, the distance between the orthogonal projection of the boundary of the via VV close to the second electrode connection part 932 on the substrate and the orthogonal projection of the second boundary L32 on the substrate is greater than or equal to 0, the distance between the orthogonal projection of the boundary of the via VV close to the third electrode connection part 933 on the substrate and the orthogonal projection of the third boundary L33 on the substrate is greater than or equal to 0, the distance between the orthogonal projection of the boundary of the via VV close to the second electrode on the substrate and extending in the second direction D2 and the orthogonal projection of the fifth boundary L35 on the substrate is greater than or equal to 0, and the distance between the orthogonal projection of the boundary of the via VV close to the second electrode on the substrate and extending in the first direction D1 and the orthogonal projection of the sixth boundary L36 on the substrate is greater than or equal to 0. FIGS. 52 and 53 are described by taking an example in which the distance between the orthogonal projection of the boundary of the via VV close to the first electrode connection part 931 on the substrate and the orthogonal projection of the first boundary L31 on the substrate is equal to 0, the distance between the orthogonal projection of the boundary of the via VV close to the second electrode connection part 932 on the substrate and the orthogonal projection of the second boundary L32 on the substrate is equal to 0, the distance between the orthogonal projection of the boundary of the via VV close to the third electrode connection part 933 on the substrate and the orthogonal projection of the third boundary L33 on the substrate is equal to 0, the distance between the orthogonal projection of the boundary of the via VV close to the second electrode on the substrate and extending in the second direction D2 and the orthogonal projection of the fifth boundary L35 on the substrate is equal to 0, and the distance between the orthogonal projection of the boundary of the via VV close to the second electrode on the substrate and extending in the first direction D1 and the orthogonal projection of the sixth boundary L36 on the substrate is equal to 0.

[0366] As shown in FIG. 52, the distance between the orthogonal projection of the boundary of the active layer 92 close to the fourth boundary L34 on the substrate and the orthogonal projection of the fourth boundary L34 on the substrate along the second direction D2 is smaller than the distance between the boundary of the third electrode connection portion 933 close to the fourth boundary L34 and the orthogonal projection of the fourth boundary L34 on the substrate along the second direction D2, and the distance between the orthogonal projection of the boundary of the active layer 92 close to the seventh boundary L37 on the substrate and the orthogonal projection of the seventh boundary on the substrate along the second direction D2 is smaller than the maximum distance between the boundary of the second electrode 94 close to the seventh boundary L37 and the orthogonal projection of the seventh boundary L37 on the substrate along the second direction D2.

[0367] As shown in FIG. 53, the distance between the orthogonal projection of the boundary of the active layer 92 close to the fourth boundary L34 on the substrate and the orthogonal projection of the fourth boundary L34 on the substrate along the second direction D2 is greater than the distance between the boundary of the third electrode connection portion 933 close to the fourth boundary L34 and the orthogonal projection of the fourth boundary L34 on the substrate along the second direction D2, and the distance between the orthogonal projection of the boundary of the active layer 92 close to the seventh boundary L37 on the substrate and the orthogonal projection of the seventh boundary on the substrate along the second direction D2 is greater than the maximum distance between the boundary of the second electrode 94 close to the seventh boundary L37 and the orthogonal projection of the seventh boundary L37 on the substrate along the second direction D2.

[0368] As shown in FIG. 52 and FIG. 53, the maximum distance m between the boundary of the second electrode 94 close to the seventh boundary L37 and the orthogonal projection of the seventh boundary L37 on the substrate along the second direction D2 is in the range of 1 micrometer to 1.5 micrometers, and the distance n between the boundary of the third electrode connection portion 933 close to the fourth boundary L34 and the orthogonal projection of the fourth boundary L34 on the substrate along the second direction D2 is in the range of 1 micrometer to 1.5 micrometers.

[0369] The orthogonal projection of the first electrode and the second electrode on the substrate and the orthogonal projection of the via in the transistor device provided in FIG. 52 and FIG. 53 do not overlap, which can reduce the load of the transistor device, but when the first electrode and the second electrode are misaligned relative to the gate insulating layer in the first direction, the parasitic capacitance between the gate electrode and the first electrode and the parasitic capacitance between the gate electrode and the second electrode will fluctuate.

[0370] In an exemplary embodiment, the transistor device provided in FIG. 24 to FIG. 54 is a single-gate structure.

[0371] FIG. 55 is a top view of another transistor device. As shown in FIG. 55, the gate electrode 201 includes a first gate electrode 2011 and a second gate electrode 2012 connected to each other, and the transistor device further includes a connecting electrode 205 located on the side of the first electrode 203 and the second electrode 204 away from the substrate. The orthogonal projection of the active layer 202 on the substrate at least partially overlaps the orthogonal projection of the first gate electrode 2011 on the substrate, and does not overlap the orthogonal projection of the second gate electrode 2012 on the substrate, and the connecting electrode 205 is electrically connected to the second gate electrode 2022.

[0372] In an example embodiment, the connecting electrode 205 is a transparent electrode.

[0373] In an example embodiment, the connecting electrode is connected to the gate electrode, and can serve as two gate electrodes of the transistor device, so that the transistor device is a dual-gate structure.

[0374] In an example embodiment, the transistor device structure including a plurality of transistor devices in FIGS. 24-28 and 51 can be applied to products with high requirements for parasitic capacitance fluctuation between the gate electrode and the source electrode.

[0375] In an example embodiment, the transistor device provided by the present disclosure is formed using the following masks: a first mask for forming the first insulating layer, a second mask for forming the gate electrode, a third mask for forming the original semiconductor layer, a fourth mask for forming the second active layer, and a fifth mask for forming the first electrode and the second electrode.

[0376] In an example embodiment, the transistor device provided by FIGS. 38-42 is formed using different fourth and fifth masks, and five masks are required to form the transistor device provided by FIGS. 38 and 42.

[0377] In an example embodiment, the transistor device provided by FIGS. 24-37 and 42-54 is formed using the same fourth and fifth masks, and four masks are required to form the transistor device provided by FIGS. 24-37 and 42-54.

[0378] The present disclosure also provides a display substrate including a plurality of transistor devices provided by any one of the preceding embodiments.

[0379] FIG. 56 is a structural schematic diagram of a display substrate provided by an embodiment of the present disclosure, and FIG. 57 is a partial connection schematic diagram of the display substrate provided by FIG. 56. As shown in FIG. 56 and FIG. 57, the display substrate provided by an embodiment of the present disclosure has a display area AA and a non-display area BB, the display area AA is provided with a plurality of first circuits Px, and the non-display area AA is provided with a plurality of second circuits. At least one circuit of the first electrode Px and the second circuit includes: at least one switching device; and at least one switching device in at least one circuit of the first circuit and the second circuit is a transistor device.

[0380] In an example embodiment, the second circuit includes at least one circuit of a gate driving circuit, a source driving circuit, a multiplexing circuit, an electrostatic discharge circuit, an array test circuit, and a light-on test circuit.

[0381] In an example embodiment, the second circuit can be located on at least one of a first side, a second side, a third side, and a fourth side of the display area. The first side and the second side are oppositely arranged, and the third side and the fourth side are oppositely arranged. For example, the gate driving circuit can be located on at least one of the first side and the second side of the display area. The source driving circuit, the multiplexing circuit, and the light-on test circuit can be located on the fourth side of the display area. The array test circuit can be located on at least one of the third side and the fourth side of the display area, and the electrostatic discharge circuit can be located on at least one of the third side and the fourth side of the display area.

[0382] The fourth side of the display area can be referred to as a data side, and the third side of the display area can be referred to as a non-data side.

[0383] In an example embodiment, the transistor device provided by FIG. 38 to FIG. 54 is applicable to the first circuit.

[0384] In an example embodiment, the transistor device provided by FIG. 24 to FIG. 37 is applicable to the first circuit and the gate driving circuit.

[0385] The gate driving circuit includes a plurality of cascaded shift registers, and at least one level of the shift registers includes: an input transistor and an output transistor, which are the transistor device provided by any of the foregoing embodiments. In an example embodiment, at least one level of the shift registers can include: an input sub-circuit, an output sub-circuit, a blanking reset sub-circuit, a display reset sub-circuit, a pull-down control sub-circuit, and a noise reduction sub-circuit.

[0386] Figure 58 is an equivalent circuit diagram of at least one level shift register. As shown in Figure 58, the input sub-circuit includes: a first transistor T1, the output sub-circuit includes: a third transistor T3 and a capacitor C, the display reset sub-circuit includes: a second transistor T2, the blanking reset sub-circuit includes: an eighteenth transistor T18 and a nineteenth transistor T19, the pull-down control sub-circuit includes: a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, an eleventh transistor T11, a twelfth transistor T12 and a thirteenth transistor T13, the noise reduction sub-circuit includes: a fourteenth transistor T14, a fifteenth transistor T15, a sixteenth transistor T16 and a seventeenth transistor T17.

[0387] As shown in FIG. 58, the control electrode and the first electrode of the first transistor T1 are electrically connected with the signal input end IN respectively, the second electrode of the first transistor T1 is electrically connected with the pull-up node PU; the control electrode of the second transistor T2 is electrically connected with the reset signal end RST, the first electrode of the second transistor T2 is electrically connected with the pull-up node PU, and the second electrode of the second transistor T2 is electrically connected with the third power supply end VGL; the control electrode of the third transistor T3 is electrically connected with the pull-up node PU, the first electrode of the third transistor T3 is electrically connected with the clock signal end CLK, and the second electrode of the third transistor T3 is electrically connected with the signal output end OUT; the control electrode and the first electrode of the fourth transistor T4 are electrically connected with the first power supply end VDD1 respectively, the second electrode of the fourth transistor T4 is electrically connected with the control electrode of the fifth transistor T5 and the first electrode of the sixth transistor T6 respectively; the first electrode of the fifth transistor T5 is electrically connected with the first power supply end VDD1, the second electrode of the fifth transistor T5 is electrically connected with the first pull-down node PD1, the control electrode of the sixth transistor T6 is electrically connected with the pull-up node PU, and the second electrode of the sixth transistor T6 is electrically connected with the third power supply end VGL; the control electrode of the seventh transistor T7 is electrically connected with the pull-up node PU, the first electrode of the seventh transistor T7 is electrically connected with the first pull-down node PD1, the second electrode of the seventh transistor T7 is electrically connected with the third power supply end VGL, the control electrode of the eighth transistor T8 is electrically connected with the signal input end IN, the first electrode of the eighth transistor T8 is electrically connected with the first pull-down node PD1, and the second electrode of the eighth transistor T8 is electrically connected with the third power supply end VGL; the control electrode and the first electrode of the ninth transistor T9 are electrically connected with the second power supply end VDD2 respectively, the second electrode of the ninth transistor T9 is electrically connected with the control electrode of the tenth transistor T10 and the first electrode of the eleventh transistor T11 respectively; the first electrode of the tenth transistor T10 is electrically connected with the second power supply end VDD2, the second electrode of the tenth transistor T10 is electrically connected with the second pull-down node PD2, the control electrode of the eleventh transistor T11 is electrically connected with the pull-up node PU, and the second electrode of the eleventh transistor T11 is electrically connected with the third power supply end VGL; the control electrode of the twelfth transistor T12 is electrically connected with the pull-up node PU, the first electrode of the twelfth transistor T12 is electrically connected with the second pull-down node PD2, the second electrode of the twelfth transistor T12 is electrically connected with the third power supply end VGL, the control electrode of the thirteenth transistor T13 is electrically connected with the signal input end IN, the first electrode of the thirteenth transistor T13 is electrically connected with the second pull-down node PD2, and the second electrode of the thirteenth transistor T13 is electrically connected with the third power supply end VGL; the control electrode of the fourteenth transistor T14 is electrically connected with the first pull-down node PD1, the first electrode of the fourteenth transistor T14 is electrically connected with the pull-up node PU, and the second electrode of the fourteenth transistor T14 is electrically connected with the third power supply end VGL; the control electrode of the fifteenth transistor T15 is electrically connected with the second pull-down node PD2, the first electrode of the fifteenth transistor T15 is electrically connected with the pull-up node PU, and the second electrode of the fifteenth transistor T15 is electrically connected with the third power supply end VGL.A control electrode of the sixteenth transistor T16 is electrically connected with the first pull-down node PD1, a first electrode of the sixteenth transistor T16 is electrically connected with the signal output terminal OUT, and a second electrode of the sixteenth transistor T16 is electrically connected with the third power terminal VGL; a control electrode of the seventeenth transistor T17 is electrically connected with the second pull-down node PD2, a first electrode of the seventeenth transistor T17 is electrically connected with the signal output terminal OUT, and a second electrode of the seventeenth transistor T17 is electrically connected with the third power terminal VGL; a control electrode of the eighteenth transistor T18 is electrically connected with the blanking reset signal terminal TRST, a first electrode of the eighteenth transistor T18 is electrically connected with the pull-up node PU, and a second electrode of the eighteenth transistor T18 is electrically connected with the third power terminal VGL; a control electrode of the nineteenth transistor T19 is electrically connected with the blanking reset signal terminal TRST, a first electrode of the nineteenth transistor T19 is electrically connected with the signal output terminal OUT, and a second electrode of the nineteenth transistor T19 is electrically connected with the third power terminal VGL; a first plate C1 of the capacitor C is electrically connected with the pull-up node PU, and a second plate C2 of the capacitor C is electrically connected with the signal output terminal OUT.

[0388] In an example embodiment, the first transistor T1 can be referred to as an input transistor. The third transistor T3 can be referred to as an output transistor.

[0389] In an example embodiment, the signal output terminal of the at least one stage of shift register is electrically connected with the reset signal terminal of the at least one stage of shift register, and is electrically connected with the signal input terminal of the at least one stage of shift register. For example, the cascade signal output terminal of the at least one stage of shift register is electrically connected with the reset signal terminal of the previous stage of shift register and the signal input terminal of the next stage of shift register, respectively.

[0390] In an example embodiment, the working process of the display substrate includes a display stage and a shutdown stage. The display substrate has an Xon function in the shutdown stage to timely release the charges of the pixel units in the display substrate.

[0391] In an example embodiment, the display stage includes a plurality of display frames, and a mute period is arranged between adjacent display frames.

[0392] In an example embodiment, in at least one display frame, the signal received by the signal input terminal IN is a single pulse signal.

[0393] In an example embodiment, in at least one display frame, the signal output terminal OUT of the at least one stage of shift register is configured to provide an output cascade signal to the signal input terminal of the at least one stage of shift register and the reset signal terminal of the at least one stage of shift register, and to provide a driving signal to the scan signal line connected with the pixel driving circuit located in the display area.

[0394] In an example embodiment, in the display stage, the signal of the third power supply end VGL is a low level signal.

[0395] In an example embodiment, in the power-off stage, the signal of the third power supply end VGL is a high level signal to pull up the signal of the driving signal output end OUT of the at least one stage of shift register, thereby discharging the pixel unit, and the signal of the third power supply end VGL is a low level signal to pull down the signal of the pull-up node PU, thereby preventing the pull-up node PU of the at least one stage of shift register from accumulating charges, so as to ensure that the at least one stage of shift register can normally work in the display stage.

[0396] In an example embodiment, in the display stage, the signal of at least one of the first power supply end VDD1 and the second power supply end VDD2 is a periodic signal.

[0397] In an example embodiment, in the display stage, the signals of the first power supply end VDD1 and the second power supply end VDD2 are at least partially complementary signals. When the signal of the first power supply end VDD1 is a high level signal, the signal of the second power supply end VDD2 is a low level signal, and when the signal of the second power supply end VDD2 is a high level signal, the signal of the first power supply end VDD1 is a low level signal.

[0398] In an example embodiment, the display frame includes a first display frame and a second display frame. In at least one first display frame, the signal of the first power supply end VDD1 is a high level signal and the signal of the second power supply end VDD2 is a low level signal, and in at least one second display frame, the signal of the second power supply end VDD2 is a high level signal and the signal of the first power supply end VDD1 is a low level signal.

[0399] In an example embodiment, the signal of the blanking reset signal end TRST is an effective level signal in the blanking period and is an ineffective level signal in the display stage. Wherein the signal of the signal end being an effective level signal means that the signal end is electrically connected to the control electrode of a transistor and makes the transistor connected to the signal end conductive, and the signal of the signal end being an ineffective level signal means that the signal end is electrically connected to the control electrode of a transistor and makes the transistor connected to the signal end non-conductive.

[0400] In an example embodiment, the signal of the reset signal end RST is an effective level signal in part of at least one display frame.

[0401] In an example embodiment, the present disclosure reduces the stress of at least one transistor in the shift register by alternately changing the first power supply end VDD1 and the second power supply end VDD2 to a high level signal to reduce noise of the shift register, thereby prolonging the service life of the shift register.

[0402] In an example embodiment, FIG. 59 is a structural schematic diagram of a shift register provided by an embodiment of the present disclosure. The display substrate provided by FIG. 59 includes a first shift register as provided by FIG. 58. The at least one shift register includes a plurality of transistors. The plurality of transistors includes a first transistor T1 to a nineteenth transistor T19. At least one transistor of the plurality of transistors is the transistor device provided by any one of the foregoing embodiments.

[0403] As shown in FIG. 59, the at least one transistor includes an input transistor (the first transistor T1), and the input transistor (the first transistor T1) is electrically connected to a signal input end and an upper pull node respectively. The at least one transistor further includes an output transistor (the third transistor T3), and the output transistor (the third transistor T3) is electrically connected to the upper pull node, a signal output end and a clock signal end respectively.

[0404] In an example embodiment, the display substrate includes a substrate and a gate insulating layer disposed on the substrate, and the gate insulating layer includes a first insulating layer and a second insulating layer which are disposed in layers on the substrate.

[0405] In an example embodiment, as shown in FIG. 59, one of the first insulating layer and the second insulating layer is provided with a first device via hole VV1. The active layer of the input transistor (the first transistor T1) has an orthographic projection on the substrate that at least partially overlaps the orthographic projection of the first device via hole VV1 on the substrate.

[0406] In an example embodiment, as shown in FIG. 59, one of the first insulating layer and the second insulating layer is further provided with a second device via hole VV2. The active layer 3-2 of the output transistor (the third transistor T3) has an orthographic projection on the substrate that at least partially overlaps the orthographic projection of the second device via hole VV2 on the substrate.

[0407] In an example embodiment, the first device via hole VV1 and the second device via hole VV2 can be disposed on the same insulating layer. For example, the first device via hole VV1 and the second device via hole VV2 can be disposed on the first insulating layer, or the first device via hole VV1 and the second device via hole VV2 can be disposed on the second insulating layer.

[0408] In the example embodiment, the input transistor of the at least one stage of shift register drives the signal of the pull-up node, and the output transistor drives the signal of the signal output terminal. Therefore, the display substrate has a large demand for the increase of the on-current of the input transistor and the output transistor. The disclosure sets the input transistor as the transistor device provided in the foregoing embodiment, so as to improve the charging capability of the pull-up node, thereby improving the voltage of the signal of the pull-up node. The disclosure sets the output transistor as the transistor device provided in the foregoing embodiment, so as to increase the driving circuit of the shift register, thereby improving the overall driving capability of the shift register, and further improving the reliability of the gate driving circuit.

[0409] In the example embodiment, the transistor of the at least one stage of shift register other than the input transistor and the output transistor is not sensitive to the on-current of the transistor device. Therefore, the active layer of the transistor of the at least one stage of shift register other than the input transistor and the output transistor can not be provided with a via hole in the presence of the overlapping gate insulating layer on the substrate.

[0410] In the example embodiment, the display substrate comprises a substrate and a circuit structure layer provided on the substrate. The circuit structure layer comprises a first conductive layer, a semiconductor layer and a second conductive layer which are sequentially stacked on the substrate.

[0411] In the example embodiment, the first conductive layer comprises gate electrodes of a plurality of transistors in the at least one stage of shift register.

[0412] In the example embodiment, the semiconductor layer comprises active layers of a plurality of transistors in the at least one stage of shift register.

[0413] In the example embodiment, the second conductive layer comprises first electrodes and second electrodes of a plurality of transistors in the at least one stage of shift register.

[0414] In the example embodiment, as shown in FIG. 59, the display substrate further comprises a plurality of clock signal lines, a first power supply line VDDL1, a second power supply line VDDL2, a third power supply line VGLL and a total reset signal line TRL provided on the substrate. FIG. 59 is an example of a plurality of clock signal lines comprising a first clock signal line CLKL1, a second clock signal line CLKL2, a third clock signal line CLKL3 and a fourth clock signal line CLKL4.

[0415] In the example embodiment, at least one of the first electrode and the second electrode of at least one transistor (the fourth transistor T4 and the fifth transistor T5) in the at least one stage shift register is electrically connected with the first power supply end. At least one of the first electrode and the second electrode of at least one transistor (the ninth transistor T9 and the tenth transistor T10) in the at least one stage shift register is electrically connected with the second power supply end, the second electrode of at least one transistor (the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the eleventh transistor T11, the twelfth transistor T12, the thirteenth transistor T13, the fourteenth transistor T14, the fifteenth transistor T15, the sixteenth transistor T16, the seventeenth transistor T17, the eighteenth transistor T18 and the nineteenth transistor T19) in the at least one stage shift register is electrically connected with the third power supply end, and the control electrode of at least one transistor (the eighteenth transistor T18 and the nineteenth transistor T19) in the at least one stage shift register is electrically connected with the total reset signal line TRL.

[0416] In the example embodiment, at least one of the plurality of clock signal lines, the first power supply line VDDL1, the second power supply line VDDL2, the third power supply line VGLL and the total reset signal line TRL extends at least partially along the third direction D3 and is located in the first conductive layer.

[0417] In the example embodiment, as shown in FIG. 59, the orthographic projection of at least one of the plurality of clock signal lines, the first power supply line VDDL1, the second power supply line VDDL2 and the third power supply line VGLL on the substrate is located on the side away from the display area of the orthographic projection of the plurality of transistors in the at least one stage shift register on the substrate.

[0418] In the example embodiment, as shown in FIG. 59, the orthographic projection of the total reset signal line TRL on the substrate is located between the orthographic projections of the plurality of transistors on the substrate and between the orthographic projection of the output transistor on the substrate and the orthographic projection of the input transistor on the substrate. For example, the orthographic projection of the total reset signal line TRL on the substrate can be located between the orthographic projection of at least one of the first transistor T1 to the seventeenth transistor T17 on the substrate and the orthographic projection of the third transistor T3 on the substrate and at least partially overlaps with the orthographic projection of at least one of the eighteenth transistor T18 and the nineteenth transistor T19 on the substrate.

[0419] In the example embodiment, as shown in FIG. 59, the display substrate can further include a plurality of cascade signal lines OUTL, which can be electrically connected with the signal input end of the at least one stage shift register and can be electrically connected with the reset signal end of the at least one stage shift register.

[0420] In an exemplary embodiment, as shown in FIG. 59, the plurality of cascaded signal lines OUTL are located in the first conductive layer.

[0421] In an exemplary embodiment, as shown in FIG. 59, the orthographic projection of the plurality of cascaded signal lines OUTL on the base is between the orthographic projection of at least one of the first transistor T1 to the seventeenth transistor T17 on the base and the orthographic projection of at least one of the eighteenth transistor T18 and the nineteenth transistor T19 on the base.

[0422] In an exemplary embodiment, the display substrate further includes a light sensing structure configured to convert a light signal into an electrical signal. The light sensing structure includes at least one light sensing switching device, the at least one light sensing switching device being the transistor device.

[0423] In an exemplary embodiment, the light sensing structure can be located in the display area.

[0424] FIG. 60 is a top view of a light sensing switching device I. As shown in FIG. 60, the light sensing switching device includes a gate electrode 301, an active layer 302, a first electrode 303, and a second electrode 304. The light sensing switching device further includes a gate insulating layer.

[0425] In an exemplary embodiment, as shown in FIG. 60, the orthographic projection of the active layer 302 on the base is within the range of the orthographic projection of the gate electrode 301 on the base. The gate insulating layer is provided with a via hole VV4, the number of the via hole VV4 is one, and the orthographic projection of the via hole VV4 on the base is within the range of the orthographic projection of the active layer 302 on the base.

[0426] In an exemplary embodiment, as shown in FIG. 60, the first electrode 303 includes a first connecting portion 3031 and a plurality of first branch portions 3032. The first connecting portion 3031 is connected with the plurality of first branch portions 3032 respectively. Wherein, the first connecting portion 3031 extends along the first direction D1, the plurality of first branch portions 3032 are arranged along the first direction D1, and at least one of the branch portions 3032 extends along the second direction D2.

[0427] In an exemplary embodiment, as shown in FIG. 60, the orthographic projection of the first connecting portion 3031 on the base does not overlap with the orthographic projection of the gate electrode 301 on the base, and the orthographic projection of at least one of the plurality of first branch portions 3032 on the base at least partially overlaps with the orthographic projection of the via hole VV3 on the base.

[0428] In an exemplary embodiment, as shown in FIG. 60, the second electrode 304 includes a second connecting portion 3041, a third connecting portion 3043, a plurality of second branch portions 3042, and a plurality of third branch portions 3044. The second connecting portion 3041 and the third connecting portion 3043 extend along the first direction D1, and the plurality of second branch portions 3042 and the plurality of third branch portions 3044 extend along the second direction D2. The plurality of second branch portions 3042 are connected to the second connecting portion 3041 and the third connecting portion 3043, respectively, and the plurality of third branch portions 3044 are connected to the third connecting portion 3043.

[0429] In an exemplary embodiment, as shown in FIG. 60, the second connecting portion 3041 does not overlap with the orthogonal projection of the gate electrode 301 on the substrate, at least one of the plurality of second branch portions 3042 at least partially overlaps with the orthogonal projection of the via VV3 on the substrate, and the third connecting portion 3043 and the plurality of third branch portions 3044 are located within the range of the orthogonal projection of the via VV3 on the substrate.

[0430] In an exemplary embodiment, as shown in FIG. 60, the plurality of second branch portions 3042 and the plurality of third branch portions 3044 are staggered. The plurality of second branch portions 3042 correspond to the plurality of first branch portions 3032 one-to-one, and the second branch portion 3042 and the corresponding first branch portion 3032 are arranged along the second direction D2.

[0431] In an exemplary embodiment, the light sensing switch device provided in FIG. 60 includes a plurality of transistor devices, the first electrodes of the plurality of transistor devices are the same electrode, the second electrodes of the plurality of transistor devices are the same electrode, the gate electrodes of the plurality of transistor devices are the same electrode, the active layers of the plurality of transistor devices are the same active layer, and the vias of each transistor device are the same via.

[0432] In an exemplary embodiment, the light sensing switch device provided in FIG. 60 can be referred to as a merged light sensing switch device.

[0433] In an exemplary embodiment, FIG. 61 is a top view II of a light sensing switch device. As shown in FIG. 61, the light sensing switch device includes a gate electrode 401, an active layer 402, a first electrode 403, and a second electrode 404. The light sensing switch device further includes a gate insulating layer.

[0434] In an exemplary embodiment, as shown in FIG. 61, the orthogonal projection of the active layer 402 on the substrate is located within the range of the orthogonal projection of the gate electrode 401 on the substrate. The gate insulating layer is provided with a plurality of vias VV4, the plurality of vias VV4 are arranged along the first direction D1, and the orthogonal projection of the plurality of vias VV4 on the substrate is located within the range of the orthogonal projection of the active layer 402 on the substrate.

[0435] In an exemplary embodiment, as shown in FIG. 61, the first electrode 403 includes a first connecting portion 4031 and a plurality of first branch portions 4032. The first connecting portion 4031 is connected with the plurality of first branch portions 4032 respectively. Among them, the first connecting portion 4031 extends along the first direction D1, the plurality of first branch portions 4032 are arranged along the first direction D1, and at least one branch portion 4032 extends along the second direction D2.

[0436] In an exemplary embodiment, as shown in FIG. 61, the orthographic projection of the first connecting portion 4031 on the substrate does not overlap with the orthographic projection of the gate electrode 401 on the substrate, and the orthographic projection of at least one branch portion of the plurality of first branch portions 4032 on the substrate at least partially overlaps with the orthographic projection of the via hole VV3 on the substrate.

[0437] In an exemplary embodiment, as shown in FIG. 61, the second electrode 404 includes a second connecting portion 4041, a plurality of second branch portions 4042 and a plurality of third branch portions 4043. The second connecting portion 4041 extends along the first direction D1, the plurality of second branch portions 4042 and the plurality of third branch portions 4043 extend along the second direction D2, the plurality of second branch portions and the plurality of third branch portions correspond one-to-one, and the plurality of second branch portions 4042 are connected with the second connecting portion 4041 and the plurality of third branch portions 4043 respectively.

[0438] In an exemplary embodiment, as shown in FIG. 61, the plurality of second branch portions 4042 and the plurality of third branch portions 4043 correspond one-to-one, and the second branch portion 4042 is connected with the corresponding third branch portion 4043. The plurality of second branch portions 4042 and the plurality of first branch portions 4032 correspond one-to-one, and the second branch portion 4042 and the corresponding first branch portion 4032 are arranged along the second direction D2.

[0439] In an exemplary embodiment, the third branch portion 4043 includes a first sub-branch 4051, a second sub-branch 4052 and a third sub-branch 4053. The first sub-branch 4051 and the second sub-branch 4052 extend along the second direction D2, and the third sub-branch 4053 extends along the first direction D1. The third sub-branch 4053 is connected with the first sub-branch 4051 and the second sub-branch 4052 respectively.

[0440] In an exemplary embodiment, the second branch portion 4042 is connected with the middle segment of the third sub-branch 4053 of the corresponding third branch portion 4043.

[0441] In an exemplary embodiment, as shown in FIG. 61, the orthogonal projection of the second connection portion 4041 on the substrate does not overlap with the orthogonal projection of the gate electrode 401 on the substrate, the orthogonal projection of at least one branch portion in the plurality of second branch portions 4042 on the substrate at least partially overlaps with the orthogonal projection of the via VV3 on the substrate, and the orthogonal projection of the plurality of third branch portions 4043 on the substrate is within the range of the orthogonal projection of the via VV4 on the substrate. The plurality of third branch portions 4043 correspond to the plurality of vias VV4 one-to-one. The orthogonal projection of the third branch portion 4043 on the substrate is within the range of the orthogonal projection of the corresponding via VV4 on the substrate.

[0442] In an exemplary embodiment, the light sensing switch device provided in FIG. 61 includes a plurality of transistor devices, the first electrodes of the plurality of transistor devices are the same electrode, the second electrodes of the plurality of transistor devices are the same electrode, the gate electrodes of the plurality of transistor devices are the same electrode, the active layers of the plurality of transistor devices are the same active layer, and the vias of each transistor device are different vias.

[0443] The light sensing switch device provided in FIG. 61 can be referred to as a separate light sensing switch device.

[0444] In an exemplary embodiment, the light sensing switch device provided by the present disclosure can increase the leakage current of the light sensing switch device, thereby enhancing the detection capability of the light sensing switch device to light changes.

[0445] FIG. 62 is a structural schematic diagram of a part of the switch device on the data side. The gate insulating layer of the switch device STFT1 on the data side in FIG. 62 is provided with a via VV5.

[0446] FIG. 63 is a structural schematic diagram of a part of the switch device on the non-data side. The gate insulating layer of the switch device STFT2 on the non-data side in FIG. 63 is provided with a via VV6.

[0447] In an exemplary embodiment, the switch device on the data side and the switch device on the non-data side are the transistor device provided in any one of the preceding embodiments, which can reduce the channel width of the switch device, thereby reducing the area occupied by the switch device on the data side and the non-data side.

[0448] FIG. 64 is a structural schematic diagram of a part of the switch device in the electrostatic discharge circuit. The gate insulating layer of the switch device STFT3 in the electrostatic discharge circuit provided in FIG. 64 is provided with a via VV7.

[0449] In an exemplary embodiment, the switch device in the electrostatic discharge circuit adopts the transistor device provided in any one of the preceding embodiments, which can further enhance the transient on capability of the electrostatic discharge circuit, thereby improving the charge discharge capability of the electrostatic discharge circuit.

[0450] FIG. 65 is a flowchart of a method for manufacturing a transistor device according to an embodiment of the present disclosure. As shown in FIG. 65, the method for manufacturing a transistor device according to an embodiment of the present disclosure can include the following steps:

[0451] In step S101, a gate electrode of a transistor device is formed on a substrate.

[0452] In step S102, a gate insulating layer and an active layer of the transistor device are formed on the gate electrode.

[0453] The gate insulating layer includes a first insulating layer and a second insulating layer which are stacked on the substrate, and one of the first insulating layer and the second insulating layer is provided with a via hole; a normal projection of the via hole on the substrate at least partially overlaps a normal projection of the active layer on the substrate.

[0454] In step S103, a first electrode and a second electrode are formed on the active layer.

[0455] In an exemplary embodiment, step S102 includes:

[0456] The first insulating layer is formed on the gate electrode, and the first insulating layer is provided with a via hole;

[0457] The second insulating layer is formed on the first insulating layer;

[0458] The original semiconductor layer is formed on the second insulating layer, and the original semiconductor layer includes a first active layer and a third active layer;

[0459] The first electrode, the second electrode, and the active layer are formed on the original semiconductor layer, and the active layer includes a first active layer and a second active layer.

[0460] For clarity, the thickness and size of layers or microstructures are exaggerated in the drawings used to describe embodiments of the present disclosure. It can be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "under" another element, it can be "directly" on or under the other element, or there can be an intervening element.

[0461] Although the embodiments disclosed by the present disclosure are as described above, the content described is only the embodiments adopted for the purpose of facilitating the understanding of the present disclosure, and is not intended to limit the present disclosure. Any person skilled in the art of the present disclosure can make any modification and change in the form and details without departing from the spirit and scope of the present disclosure, but the patent protection scope of the present disclosure shall be subject to the scope defined by the appended claims.

Claims

1. A transistor device, wherein, The transistor device disposed on a substrate includes a gate electrode, a gate insulating layer, an active layer, a first electrode and a second electrode, the first electrode and the second electrode are disposed on the active layer and the gate electrode away from the substrate side, the gate insulating layer is disposed between the active layer and the gate electrode; The gate insulating layer includes a first insulating layer and a second insulating layer stacked on the substrate, one of the first insulating layer and the second insulating layer is provided with a via hole; The orthographic projection of the via hole on the substrate at least partially overlaps the orthographic projection of the active layer on the substrate.

2. The transistor device of claim 1, wherein, The orthographic projection of the active layer on the substrate is within the range of the orthographic projection of the gate electrode on the substrate, and the orthographic projection of at least one of the first electrode and the second electrode on the substrate at least partially overlaps the orthographic projection of the active layer on the substrate; The orthographic projection of the via hole on the substrate is within the range of the orthographic projection of the active layer on the substrate.

3. The transistor device of claim 2, wherein, The orthographic projection of the first electrode on the substrate is within the range of the orthographic projection of the active layer on the substrate, and the orthographic projection of part of the second electrode on the substrate does not overlap the orthographic projection of the gate electrode on the substrate; The via hole includes a plurality of boundaries, the plurality of boundaries include a first boundary, a second boundary, a third boundary and a fourth boundary, the first boundary and the second boundary extend along a first direction, the third boundary and the fourth boundary extend along a second direction, and the first boundary, the fourth boundary, the second boundary and the third boundary are connected in turn.

4. The transistor device of claim 3, wherein, The first electrode includes an electrode connecting segment, a first branch segment, a second branch segment and a third branch segment, the electrode connecting segment at least partially extends along a first direction, the first branch segment, the second branch segment and the third branch segment are arranged along the first direction, and at least one branch segment extends along a second direction, and the electrode connecting segment is connected with the first branch segment, the second branch segment and the third branch segment respectively; the first direction intersects with the second direction; The second electrode includes a first sub-electrode and a second sub-electrode; the first sub-electrode and the second sub-electrode extend along a second direction, the orthographic projection of the first sub-electrode on the substrate is located between the orthographic projection of the first branch segment on the substrate and the orthographic projection of the second branch segment on the substrate, and the orthographic projection of the second sub-electrode on the substrate is located between the orthographic projection of the second branch segment on the substrate and the orthographic projection of the third branch segment on the substrate; The orthographic projection of the second boundary on the substrate is located on one side of the first boundary close to the orthographic projection of the electrode connecting segment on the substrate.

5. The transistor device of claim 4, wherein, The first boundary, the second boundary, the third boundary and the fourth boundary are linear in shape; The first branch section is adjacent to the first sub-electrode, the distance between the projection of the boundary of the first sub-electrode on the substrate and the projection of the third boundary on the substrate along the first direction is in the range of 1-1.5 microns, at least one of the first sub-electrode and the second sub-electrode is adjacent to the electrode connecting section, the distance between the projection of the boundary of the electrode connecting section on the substrate and the projection of the second boundary on the substrate along the second direction is in the range of 1-1.5 microns, and the third branch section is adjacent to the second sub-electrode, the distance between the projection of the boundary of the second sub-electrode on the substrate and the projection of the fourth boundary on the substrate along the first direction is in the range of 1-1.5 microns. The first boundary, the third boundary and the fourth boundary are in a linear shape, and the shape of the second boundary is matched with the shape of the electrode connecting section; 6. The transistor device of claim 4, wherein, The first branch section is adjacent to the first sub-electrode, the distance between the projection of the boundary of the first sub-electrode on the substrate and the projection of the third boundary on the substrate along the first direction is in the range of 1-1.5 microns, at least one of the first sub-electrode and the second sub-electrode is adjacent to the electrode connecting section, the distance between the projection of the boundary of the electrode connecting section on the substrate and the projection of the second boundary on the substrate along the second direction is in the range of 1-1.5 microns, and the third branch section is adjacent to the second sub-electrode, the distance between the projection of the boundary of the second sub-electrode on the substrate and the projection of the fourth boundary on the substrate along the first direction is in the range of 1-1.5 microns. The first branch section is adjacent to the first sub-electrode, the distance between the projection of the boundary of the first sub-electrode on the substrate and the projection of the third boundary on the substrate along the first direction is in the range of 1-1.5 microns, at least one of the first sub-electrode and the second sub-electrode is adjacent to the electrode connecting section, the distance between the projection of the boundary of the electrode connecting section on the substrate and the projection of the second boundary on the substrate along the second direction is in the range of 1-1.5 microns, and the third branch section is adjacent to the second sub-electrode, the distance between the projection of the boundary of the second sub-electrode on the substrate and the projection of the fourth boundary on the substrate along the first direction is in the range of 1-1.5 microns. The via hole comprises: a first via hole, a second via hole, a third via hole and a fourth via hole, the first via hole, the second via hole, the third via hole and the fourth via hole are arranged along the first direction; 7. The transistor device of claim 4, wherein, ​ a third boundary of the first via and a boundary of the first branch segment close to the first via partially overlap on the substrate, and a fourth boundary of the first via and a boundary of the first sub-electrode close to the first via partially overlap on the substrate, a third boundary of the second via and a boundary of the first sub-electrode close to the second via partially overlap on the substrate, and a fourth boundary of the second via and a boundary of the second branch segment close to the second via partially overlap on the substrate, a third boundary of the third via and a boundary of the second branch segment close to the third via partially overlap on the substrate, and a fourth boundary of the third via and a boundary of the second sub-electrode close to the third via partially overlap on the substrate, and a third boundary of the fourth via and a boundary of the second sub-electrode close to the fourth via partially overlap on the substrate, and a fourth boundary of the fourth via and a boundary of the third branch segment close to the fourth via partially overlap on the substrate. a third boundary of the first via and a boundary of the first branch segment close to the first via partially overlap on the substrate, and a fourth boundary of the first via and a boundary of the first sub-electrode close to the first via partially overlap on the substrate, a third boundary of the second via and a boundary of the first sub-electrode close to the second via partially overlap on the substrate, and a fourth boundary of the second via and a boundary of the second branch segment close to the second via partially overlap on the substrate, a third boundary of the third via and a boundary of the second branch segment close to the third via partially overlap on the substrate, and a fourth boundary of the third via and a boundary of the second sub-electrode close to the third via partially overlap on the substrate, and a third boundary of the fourth via and a boundary of the second sub-electrode close to the fourth via partially overlap on the substrate, and a fourth boundary of the fourth via and a boundary of the third branch segment close to the fourth via partially overlap on the substrate.

8. The transistor device of claim 4, wherein, the vias include a first via, a second via and a third via, the first via, the second via and the third via are arranged along a first direction; a third boundary of the first via and a boundary of the first branch segment close to the first via partially overlap on the substrate, and a fourth boundary of the first via and a boundary of the first sub-electrode close to the first via partially overlap on the substrate, a third boundary of the second via and a boundary of the first sub-electrode close to the second via partially overlap on the substrate, and a fourth boundary of the second via and a boundary of the second branch segment close to the second via partially overlap on the substrate, a third boundary of the third via and a boundary of the second branch segment close to the third via partially overlap on the substrate, and a fourth boundary of the third via and a boundary of the second sub-electrode close to the third via partially overlap on the substrate, and a third boundary of the fourth via and a boundary of the second sub-electrode close to the fourth via partially overlap on the substrate, and a fourth boundary of the fourth via and a boundary of the third branch segment close to the fourth via partially overlap on the substrate. the vias include a first via, a second via and a third via, the first via, the second via and the third via are arranged along a first direction; a third boundary of the first via and a boundary of the first branch segment close to the first via partially overlap on the substrate, and a fourth boundary of the first via and a boundary of the first sub-electrode close to the first via partially overlap on the substrate, a third boundary of the second via and a boundary of the first sub-electrode close to the second via partially overlap on the substrate, and a fourth boundary of the second via and a boundary of the second branch segment close to the second via partially overlap on the substrate, a third boundary of the third via and a boundary of the second branch segment close to the third via partially overlap on the substrate, and a fourth boundary of the third via and a boundary of the second sub-electrode close to the third via partially overlap on the substrate, and a third boundary of the fourth via and a boundary of the second sub-electrode close to the fourth via partially overlap on the substrate, and a fourth boundary of the fourth via and a boundary of the third branch segment close to the fourth via partially overlap on the substrate. The first branch segment is at least partially overlapped with the first boundary, the second boundary and the third boundary of the first via hole in the projection on the substrate, the second branch segment is at least partially overlapped with the first boundary and the second boundary of the second via hole in the projection on the substrate, and the third branch segment is at least partially overlapped with the first boundary, the second boundary and the fourth boundary of the third via hole in the projection on the substrate; The distance between the projection on the substrate of the boundary of the first branch segment close to the first sub-electrode and the projection on the substrate of the third boundary of the first via hole is in the range of 1-1.5 microns, and the distance between the projection on the substrate of the boundary of the third branch segment close to the second sub-electrode and the projection on the substrate of the fourth boundary of the third via hole is in the range of 1-1.5 microns; The distance between the projection on the substrate of the boundary of at least one of the first sub-electrode and the second sub-electrode close to the electrode connecting segment and the first boundary of at least one of the first via hole, the second via hole and the third via hole along the second direction is greater than the distance between the first boundary and the second boundary of at least one of the first via hole, the second via hole and the third via hole along the second direction, and the distance between the projection on the substrate of the boundary of the first branch segment away from the electrode connecting segment and the second boundary of at least one of the first via hole, the second via hole and the third via hole along the second direction is greater than the distance between the first boundary and the second boundary of at least one of the first via hole, the second via hole and the third via hole along the second direction; The distance between the projection on the substrate of the boundary of at least one of the first sub-electrode and the second sub-electrode close to the electrode connecting segment and the second boundary of at least one of the first via hole, the second via hole and the third via hole along the second direction is in the range of 1-1.5 microns.

9. The transistor device of claim 3, wherein, The first electrode comprises an electrode connecting segment, a first branch segment and a second branch segment, the electrode connecting segment extends at least partially along a first direction, the first branch segment and the second branch segment are arranged along the first direction, and at least one branch segment extends along a second direction, and the electrode connecting segment is connected with the first branch segment and the second branch segment respectively; the first direction intersects with the second direction; The second electrode extends along the second direction, and the projection on the substrate of the second electrode is located between the projection on the substrate of the first branch segment and the projection on the substrate of the second branch segment; The projection on the substrate of the second boundary is located on one side of the first boundary close to the projection on the substrate of the electrode connecting segment.

10. The transistor device of claim 9, wherein, The first boundary, the second boundary, the third boundary and the fourth boundary are in the shape of straight lines; The first boundary, the second boundary, the third boundary and the fourth boundary are in the shape of straight lines. The first branch segment is adjacent to the second electrode, the distance between the projection of the boundary of the first branch segment on the substrate and the projection of the third boundary on the substrate along the first direction is in the range of 1-1.5 microns, the distance between the projection of the boundary of the second electrode on the substrate and the projection of the second boundary on the substrate along the second direction is in the range of 1-1.5 microns, and the distance between the projection of the boundary of the third branch segment on the substrate and the projection of the fourth boundary on the substrate along the first direction is in the range of 1-1.5 microns. The first branch segment is adjacent to the second electrode, the distance between the projection of the boundary of the first branch segment on the substrate and the projection of the third boundary on the substrate along the first direction is in the range of 1-1.5 microns, the distance between the projection of the boundary of the second electrode on the substrate and the projection of the second boundary on the substrate along the second direction is in the range of 1-1.5 microns, and the distance between the projection of the boundary of the third branch segment on the substrate and the projection of the fourth boundary on the substrate along the first direction is in the range of 1-1.5 microns.

11. The transistor device of claim 9, wherein, The first boundary, the third boundary and the fourth boundary are linear, and the shape of the second boundary is matched with the shape of the electrode connection segment. The first branch segment is adjacent to the second electrode, the distance between the projection of the boundary of the first branch segment on the substrate and the projection of the third boundary on the substrate along the first direction is in the range of 1-1.5 microns, the distance between the projection of the boundary of the second electrode on the substrate and the projection of the second boundary on the substrate along the second direction is in the range of 1-1.5 microns, and the distance between the projection of the boundary of the third branch segment on the substrate and the projection of the fourth boundary on the substrate along the first direction is in the range of 1-1.5 microns. The first branch segment is adjacent to the second electrode, the distance between the projection of the boundary of the first branch segment on the substrate and the projection of the third boundary on the substrate along the first direction is in the range of 1-1.5 microns, the distance between the projection of the boundary of the second electrode on the substrate and the projection of the second boundary on the substrate along the second direction is in the range of 1-1.5 microns, and the distance between the projection of the boundary of the third branch segment on the substrate and the projection of the fourth boundary on the substrate along the first direction is in the range of 1-1.5 microns.

12. The transistor device of claim 9, wherein, The via includes: a first via and a second via, the first via and the second via are arranged along the first direction; The projection of the first via on the substrate is located between the projection of the first branch segment on the substrate and the projection of the second electrode on the substrate, and the projection of the second via on the substrate is located between the projection of the second electrode on the substrate and the projection of the second branch segment on the substrate; The first branch segment is adjacent to the second electrode, the distance between the projection of the boundary of the first branch segment on the substrate and the projection of the third boundary on the substrate along the first direction is in the range of 1-1.5 microns, the distance between the projection of the boundary of the second electrode on the substrate and the projection of the second boundary on the substrate along the second direction is in the range of 1-1.5 microns, and the distance between the projection of the boundary of the third branch segment on the substrate and the projection of the fourth boundary on the substrate along the first direction is in the range of 1-1.5 microns. A distance between a normal projection of a third boundary of the first via on the substrate and a normal projection of a boundary of the first branch segment close to the first via on the substrate along the first direction is greater than or equal to 0, a distance between a normal projection of a fourth boundary of the first via on the substrate and a normal projection of a boundary of the second electrode close to the first via on the substrate along the first direction is greater than or equal to 0, a distance between a normal projection of a third boundary of the second via on the substrate and a normal projection of a boundary of the second electrode close to the second via on the substrate along the first direction is greater than or equal to 0, and a distance between a normal projection of a fourth boundary of the second via on the substrate and a normal projection of a boundary of the second branch segment close to the second via on the substrate along the first direction is greater than or equal to 0.

13. The transistor device of claim 9, wherein, The via includes a first via and a second via, and the first via and the second via are arranged along a first direction; A normal projection of the first via on the substrate at least partially overlaps a normal projection of the first branch segment on the substrate and does not overlap a normal projection of the second electrode on the substrate, and a normal projection of the second via on the substrate at least partially overlaps a normal projection of the second branch segment on the substrate and does not overlap a normal projection of the second electrode on the substrate; A normal projection of the first branch segment on the substrate at least partially overlaps a normal projection of a first boundary, a second boundary and a third boundary of the first via on the substrate, and a normal projection of the second branch segment on the substrate at least partially overlaps a normal projection of a first boundary, a second boundary and a fourth boundary of the second via on the substrate; A distance between a normal projection of a boundary of the first branch segment close to the second electrode on the substrate and a normal projection of a third boundary of the first via on the substrate is in a range of 1 micrometer to 1.5 micrometers, and a distance between a normal projection of a boundary of the second branch segment close to the second electrode on the substrate and a normal projection of a fourth boundary of the second via on the substrate is in a range of 1 micrometer to 1.5 micrometers.

14. The transistor device of claim 6 or 11, wherein, The plurality of boundaries further include a first convex boundary, a second convex boundary, a third convex boundary, a fourth convex boundary, a fifth convex boundary, a sixth convex boundary, a seventh convex boundary and an eighth convex boundary, the first convex boundary, the third convex boundary, the fifth convex boundary and the seventh convex boundary extend along a first direction, and the second convex boundary, the fourth convex boundary, the sixth convex boundary and the eighth convex boundary extend along a second direction; The third boundary is connected with the first boundary in sequence through the first convex boundary, the second convex boundary, the third convex boundary and the fourth convex boundary, and the fourth boundary is connected with the first boundary in sequence through the fifth convex boundary, the sixth convex boundary, the seventh convex boundary and the eighth convex boundary; A normal projection of the first electrode and the second electrode on the substrate does not overlap a normal projection of at least one of the first convex boundary, the second convex boundary, the third convex boundary, the fourth convex boundary, the fifth convex boundary, the sixth convex boundary, the seventh convex boundary and the eighth convex boundary on the substrate. The distance between the second protruding boundary and the fourth protruding boundary along the second direction is in the range of 1-4 microns, and the distance between the sixth protruding boundary and the eighth protruding boundary along the second direction is in the range of 1-4 microns.

15. The transistor device of any one of claims 7, 8, 12, and 13, wherein, The distance between the second electrode boundary close to the electrode connecting segment and the first boundary of the plurality of vias along the second direction is greater than the distance between the first and second boundaries of the plurality of vias along the second direction, and the distance between the first branch segment boundary away from the electrode connecting segment and the second boundary of at least one via of the plurality of vias along the second direction is greater than the distance between the first and second boundaries of the at least one via along the second direction. The distance between the second electrode boundary close to the electrode connecting segment and the second boundary of at least one via of the plurality of vias along the second direction is in the range of 1-1.5 microns.

16. The transistor device of claim 2, wherein, The first electrode and the second electrode extend along the second direction, and the projection of at least one of the first electrode and the second electrode on the substrate does not overlap with the projection of the gate electrode on the substrate. The via includes a plurality of boundaries, including a first boundary, a second boundary, a third boundary and a fourth boundary, the first and second boundaries extend along the first direction, the third and fourth boundaries extend along the second direction, the first, fourth, second and third boundaries are sequentially connected, and the first, second, third and fourth boundaries are linear. The distance between the first target boundary and the first boundary on the substrate along the second direction is less than the distance between the first target boundary and the second boundary on the substrate along the second direction, and the distance between the second target boundary and the second boundary on the substrate along the second direction is less than the distance between the second target boundary and the first boundary on the substrate along the second direction, the first target boundary is a boundary extending along the first direction where the first electrode and the active layer overlap, and the second target boundary is a boundary extending along the first direction where the second electrode and the active layer overlap.

17. The transistor device of claim 16, wherein, The projection of at least one of the first electrode and the second electrode on the substrate at least partially overlaps with the projection of the first and second boundaries on the substrate, respectively, and does not overlap with the projection of the third and fourth boundaries on the substrate. Alternatively, the projection of the via on the substrate does not overlap with the projection of the first and second electrodes on the substrate, respectively. Or, the normal projection of the via on the substrate partially overlaps with the normal projection of the first electrode on the substrate and does not overlap with the normal projection of the second electrode on the substrate, and the normal projection of the first electrode on the substrate respectively overlaps with the normal projection of the first boundary and the second boundary on the substrate; The distance between the normal projection of the first target boundary on the substrate and the normal projection of the first boundary on the substrate along the second direction is in the range of 1-1.5 microns, and the distance between the normal projection of the second target boundary on the substrate and the normal projection of the second boundary on the substrate along the second direction is in the range of 1-1.5 microns.

18. The transistor device of claim 2, wherein, The first electrode comprises a first electrode connecting part and a second electrode connecting part connected to each other, the first electrode connecting part extends along the first direction, and the second electrode connecting part extends along the second direction; part of the normal projection of the first electrode connecting part on the substrate partially overlaps with the normal projection of the active layer on the substrate, and another part of the normal projection of the first electrode connecting part on the substrate does not overlap with the normal projection of the gate electrode on the substrate, and the normal projection of the second electrode connecting part on the substrate is within the range of the normal projection of the active layer on the substrate; Part of the normal projection of the second electrode on the substrate does not overlap with the normal projection of the gate electrode on the substrate; The via comprises a plurality of boundaries, the plurality of boundaries comprising a first boundary, a second boundary, a third boundary and a fourth boundary, the first boundary and the second boundary extend along the first direction, the third boundary and the fourth boundary extend along the second direction, the first boundary, the fourth boundary, the second boundary and the third boundary are connected in turn, and the shapes of the first boundary, the second boundary, the third boundary and the fourth boundary are linear; The distance between the normal projection of the first target boundary on the substrate and the normal projection of the first boundary on the substrate along the second direction is less than the distance between the normal projection of the first target boundary on the substrate and the normal projection of the second boundary on the substrate along the second direction, and the distance between the normal projection of the second target boundary on the substrate and the normal projection of the second boundary on the substrate along the second direction is less than the distance between the normal projection of the second target boundary on the substrate and the normal projection of the first boundary on the substrate along the second direction, the first target boundary is the boundary close to the first boundary and extending along the first direction of the second electrode connecting part, and the second target boundary is the boundary close to the first boundary and extending along the first direction of the second electrode connecting part.

19. The transistor device of claim 1, wherein, The active layer comprises a first active connecting part and a second active connecting part connected to each other, the first active connecting part extends at least partially along the first direction, and the second active connecting part extends at least partially along the second direction; the first electrode comprises a first electrode connecting part and a second electrode connecting part connected to each other, the first electrode connecting part extends along the first direction, and the second electrode connecting part extends along the second direction; A part of the first active connection portion has a projection on the substrate that overlaps with a projection of the gate electrode on the substrate, another part of the first electrode connection portion has a projection on the substrate that does not overlap with a projection of the gate electrode on the substrate, a part of the second active connection portion has a projection on the substrate that overlaps with a projection of the gate electrode on the substrate, another part of the second electrode connection portion has a projection on the substrate that does not overlap with a projection of the gate electrode on the substrate, the projection of the first electrode on the substrate is within the projection of the first active connection portion on the substrate, and the projection of the second electrode on the substrate is within the projection of the second active connection portion on the substrate; The projection of the via on the substrate is within the projection of the active layer on the substrate and overlaps with the projections of the first active connection portion and the second active connection portion on the substrate; The via includes a plurality of boundaries, the plurality of boundaries including a first boundary, a second boundary, a third boundary, and a fourth boundary, the first boundary and the second boundary extending along a first direction, the third boundary and the fourth boundary extending along a second direction, the first boundary, the fourth boundary, the second boundary, and the third boundary being connected in sequence, and the first boundary, the second boundary, the third boundary, and the fourth boundary being linear in shape; The distance between the projection of the first target boundary on the substrate and the projection of the first boundary on the substrate along the second direction is less than the distance between the projection of the first target boundary on the substrate and the projection of the second boundary on the substrate along the second direction, the distance between the projection of the second target boundary on the substrate and the projection of the second boundary on the substrate along the second direction is less than the distance between the projection of the second target boundary on the substrate and the projection of the first boundary on the substrate along the second direction, the first target boundary is a boundary of the second electrode connection portion close to the first boundary and extending along the first direction, and the second target boundary is a boundary of the second electrode connection portion close to the first boundary and extending along the first direction.

20. The transistor device of claim 18 or 19, wherein, The projection of the first electrode connection portion on the substrate at least partially overlaps with the projection of the third boundary on the substrate, the projection of the second electrode connection portion on the substrate does not overlap with the projections of the plurality of boundaries on the substrate, the projection of the second electrode on the substrate partially overlaps with the projections of the first boundary and the second boundary on the substrate and does not overlap with the projection of the fourth boundary on the substrate; Alternatively, the projection of the first electrode connection portion on the substrate at least partially overlaps with the projection of the third boundary on the substrate, the projection of the second electrode connection portion on the substrate partially overlaps with the projections of the first boundary and the second boundary on the substrate respectively, the projection of the second electrode on the substrate partially overlaps with the projections of the first boundary and the second boundary on the substrate and does not overlap with the projection of the fourth boundary on the substrate; Alternatively, the projection of the via on the substrate does not overlap with the projections of the first electrode and the second electrode on the substrate respectively and is located between the projection of the second electrode connection portion on the substrate and the projection of the second electrode on the substrate. Or, the orthogonal projection of the via on the substrate partially overlaps with the orthogonal projection of the first electrode on the substrate and does not overlap with the orthogonal projection of the second electrode on the substrate, and the orthogonal projection of the first electrode connection on the substrate partially overlaps with the orthogonal projection of the third boundary on the substrate, and the orthogonal projection of the second electrode connection on the substrate partially overlaps with the orthogonal projection of the first boundary and the second boundary on the substrate respectively; The distance between the orthogonal projection of the first target boundary on the substrate and the orthogonal projection of the first boundary on the substrate along the second direction is in the range of 1-1.5 microns, and the distance between the orthogonal projection of the second target boundary on the substrate and the orthogonal projection of the second boundary on the substrate along the second direction is in the range of 1-1.5 microns.

21. The transistor device of claim 20, wherein, When the orthogonal projection of the via on the substrate does not overlap with the orthogonal projection of the first electrode and the second electrode on the substrate respectively, the distance between the orthogonal projection of the boundary of the first electrode close to the via on the substrate and the orthogonal projection of the third boundary of the via on the substrate along the first direction is greater than or equal to 0, and the distance between the orthogonal projection of the boundary of the second electrode close to the via on the substrate and the orthogonal projection of the fourth boundary of the via on the substrate along the first direction is greater than or equal to 0; The distance between the orthogonal projection of the boundary of the active layer close to the first boundary on the substrate and the orthogonal projection of the first boundary on the substrate along the second direction is greater than the distance between the orthogonal projection of the boundary of the active layer close to the first boundary on the substrate and the orthogonal projection of the first target boundary on the substrate along the second direction; The distance between the orthogonal projection of the boundary of the active layer close to the second boundary on the substrate and the orthogonal projection of the second boundary on the substrate along the second direction is greater than the distance between the orthogonal projection of the boundary of the active layer close to the second boundary on the substrate and the orthogonal projection of the second target boundary on the substrate along the second direction, or the distance between the orthogonal projection of the boundary of the active layer close to the first boundary on the substrate and the orthogonal projection of the first boundary on the substrate along the second direction is less than the distance between the orthogonal projection of the boundary of the active layer close to the first boundary on the substrate and the orthogonal projection of the first target boundary on the substrate along the second direction; The distance between the orthogonal projection of the boundary of the active layer close to the second boundary on the substrate and the orthogonal projection of the second boundary on the substrate along the second direction is less than the distance between the orthogonal projection of the boundary of the active layer close to the second boundary on the substrate and the orthogonal projection of the second target boundary on the substrate along the second direction.

22. The transistor device of claim 20, wherein, When the orthogonal projection of the via on the substrate partially overlaps with the orthogonal projection of the first electrode on the substrate and does not overlap with the orthogonal projection of the second electrode on the substrate, The distance between the orthogonal projection of the boundary of the active layer close to the first boundary on the substrate and the orthogonal projection of the first boundary on the substrate along the second direction is greater than the distance between the orthogonal projection of the boundary of the active layer close to the first boundary on the substrate and the orthogonal projection of the first target boundary on the substrate along the second direction, and the distance between the orthogonal projection of the boundary of the active layer close to the second boundary on the substrate and the orthogonal projection of the second boundary on the substrate along the second direction is greater than the distance between the orthogonal projection of the boundary of the active layer close to the second boundary on the substrate and the orthogonal projection of the second target boundary on the substrate along the second direction.

23. The transistor device of claim 2, wherein, The first electrode comprises a first electrode connecting part, a second electrode connecting part, a third electrode connecting part and a fourth electrode connecting part; the first electrode connecting part and the fourth electrode connecting part extend along a first direction, the third electrode connecting part extends along a second direction, the second electrode connecting part is connected with the first electrode connecting part and the third electrode connecting part respectively, the first electrode connecting part is arranged at an obtuse angle with the second electrode connecting part, the second electrode connecting part is arranged at an obtuse angle with the third electrode connecting part, the fourth electrode connecting part is arranged at a right angle with the third electrode connecting part, and the second electrode extends along the second direction; The orthographic projection of the part of at least one of the first electrode and the second electrode on the substrate does not overlap with the orthographic projection of the gate electrode on the substrate.

24. The transistor device of claim 23, wherein, The via hole comprises a first boundary, a second boundary, a third boundary and a fourth boundary; the first boundary and the second boundary extend along a first direction, the third boundary and the fourth boundary extend along a second direction, the first boundary, the fourth boundary, the second boundary and the third boundary are connected in sequence, and the shapes of the first boundary, the second boundary, the third boundary and the fourth boundary are linear; The orthographic projection of the second electrode on the substrate overlaps with the orthographic projection of the second boundary on the substrate, the orthographic projection of the first electrode connecting part on the substrate overlaps with the orthographic projection of the third boundary on the substrate, the orthographic projections of the second electrode connecting part and the third electrode connecting part on the substrate do not overlap with the orthographic projections of the multiple boundaries on the substrate, and the orthographic projection of the fourth electrode connecting part on the substrate overlaps with the orthographic projection of the fourth boundary on the substrate.

25. The transistor device of claim 23, wherein, The via hole comprises a first boundary, a second boundary, a third boundary, a fourth boundary and a fifth boundary; the first boundary and the second boundary extend along a first direction, the third boundary and the fourth boundary extend along a second direction, the first boundary, the fifth boundary, the fourth boundary, the second boundary and the third boundary are connected in sequence, the shapes of the first boundary, the second boundary, the third boundary, the fourth boundary and the fifth boundary are linear, the fifth boundary is arranged at an obtuse angle with the first boundary, and the fourth boundary is arranged at an obtuse angle with the fifth boundary; The orthographic projection of the first electrode connecting part on the substrate overlaps with the orthographic projections of the first boundary and the third boundary on the substrate respectively, the orthographic projection of the second electrode connecting part on the substrate overlaps with the orthographic projection of the fifth boundary on the substrate, the orthographic projection of the third electrode connecting part on the substrate overlaps with the orthographic projection of the fourth boundary on the substrate, and the orthographic projection of the fourth electrode connecting part on the substrate does not overlap with the orthographic projections of the multiple boundaries on the substrate; Or, the first electrode is not overlapped with the plurality of boundaries on the substrate, the second electrode is overlapped with the second boundary on the substrate, the third electrode connection part is overlapped with the second boundary on the substrate between the boundary close to the second boundary of the active layer and the boundary close to the second boundary of the substrate along the second direction, the first electrode connection part is overlapped with the first boundary on the substrate between the boundary close to the first boundary of the via hole and the boundary of the first boundary on the substrate along the second direction, the second electrode connection part is overlapped with the second boundary on the substrate between the boundary close to the second boundary of the via hole and the boundary of the second boundary on the substrate, and the third electrode connection part is overlapped with the third boundary on the substrate between the boundary close to the third boundary of the via hole and the boundary of the third boundary on the substrate along the second direction.

26. The transistor device of claim 23, wherein, The via hole comprises a first boundary, a second boundary, a third boundary, a fourth boundary, a fifth boundary, a sixth boundary and a seventh boundary, the first boundary, the fourth boundary and the sixth boundary extend along a second direction, the third boundary, the fifth boundary and the seventh boundary extend along a first direction, the first boundary to the seventh boundary are sequentially connected, and at least one of the first boundary to the seventh boundary is in a straight line shape; The second boundary is arranged at an obtuse angle with the first boundary and the third boundary respectively, the third boundary and the fourth boundary are arranged at a right angle, the fourth boundary and the fifth boundary are arranged at a right angle, the fifth boundary and the sixth boundary are arranged at a right angle, the sixth boundary and the seventh boundary are arranged at a right angle, the seventh boundary and the first boundary are arranged at a right angle, and the distance between the sixth boundary and the first boundary is less than the distance between the fourth boundary and the first boundary; The first electrode connection part is overlapped with the first boundary and the seventh boundary on the substrate respectively, the second electrode connection part is overlapped with the second boundary on the substrate, the third electrode connection part is overlapped with the third boundary on the substrate, and the fourth electrode connection part is not overlapped with the plurality of boundaries on the substrate, and the second electrode is overlapped with the fourth boundary, the fifth boundary and the sixth boundary on the substrate respectively. Or, the first electrode and the second electrode are not overlapped with the plurality of boundaries on the substrate.

27. The transistor device of claim 26, wherein, When the first electrode and the second electrode are not overlapped with the plurality of boundaries on the substrate, The distance between the orthographic projection on the substrate of the border of the first electrode connecting part close to the border of the via hole and the orthographic projection on the substrate of the first border is greater than or equal to 0, the distance between the orthographic projection on the substrate of the border of the second electrode connecting part close to the border of the via hole and the orthographic projection on the substrate of the second border is greater than or equal to 0, the distance between the orthographic projection on the substrate of the border of the third electrode connecting part close to the border of the via hole and the orthographic projection on the substrate of the third border is greater than or equal to 0, the distance between the orthographic projection on the substrate of the border of the second electrode close to the via hole and extending along the second direction and the orthographic projection on the substrate of the fifth border is greater than or equal to 0, and the distance between the orthographic projection on the substrate of the border of the second electrode close to the via hole and extending along the first direction and the orthographic projection on the substrate of the sixth border is greater than or equal to 0; The distance between the orthographic projection on the substrate of the border of the active layer close to the fourth border and the orthographic projection on the substrate of the fourth border along the second direction is greater than the distance between the orthographic projection on the substrate of the border of the third electrode connecting part close to the fourth border and the orthographic projection on the substrate of the fourth border along the second direction, the distance between the orthographic projection on the substrate of the border of the active layer close to the seventh border and the orthographic projection on the substrate of the seventh border along the second direction is greater than the maximum distance between the orthographic projection on the substrate of the border of the second electrode close to the seventh border and the orthographic projection on the substrate of the seventh border along the second direction, or the distance between the orthographic projection on the substrate of the border of the active layer close to the fourth border and the orthographic projection on the substrate of the fourth border along the second direction is less than the distance between the orthographic projection on the substrate of the border of the third electrode connecting part close to the fourth border and the orthographic projection on the substrate of the fourth border along the second direction, and the distance between the orthographic projection on the substrate of the border of the active layer close to the seventh border and the orthographic projection on the substrate of the seventh border along the second direction is less than the maximum distance between the orthographic projection on the substrate of the border of the second electrode close to the seventh border and the orthographic projection on the substrate of the seventh border along the second direction; The maximum distance between the orthographic projection on the substrate of the border of the second electrode close to the seventh border and the orthographic projection on the substrate of the seventh border along the second direction is in the range of 1 micrometer to 1.5 micrometers, and the distance between the orthographic projection on the substrate of the border of the third electrode connecting part close to the fourth border and the orthographic projection on the substrate of the fourth border along the second direction is in the range of 1 micrometer to 1.5 micrometers.

28. The transistor device of claim 26, wherein, The number of the transistor devices is two, and the target transistor device at least partially symmetrical to the first transistor device relative to a straight line extending along the second direction is the second transistor device; The second electrode of the first transistor device and the second electrode of the second transistor device are the same electrode.

29. The transistor device of claim 1, wherein, The gate electrode comprises a first gate electrode and a second gate electrode connected to each other, and the transistor device further comprises a connecting electrode located on the side of the first electrode and the second electrode away from the substrate; The orthographic projection on the substrate of the active layer at least partially overlaps the orthographic projection on the substrate of the first gate electrode and does not overlap the orthographic projection on the substrate of the second gate electrode, and the connecting electrode is electrically connected to the second gate electrode; The connecting electrode is a transparent electrode.

30. The transistor device of claim 1, wherein, In a direction perpendicular to the substrate, the active layer comprises: a first active layer and a second active layer, the second active layer is disposed on a side of the first active layer away from the substrate, the second active layer comprises: a first active structure and a second active structure; A normal projection of the second active layer on the substrate is located within a range of a normal projection of the first active layer on the substrate, a normal projection of the first active structure on the substrate is located within a range of a normal projection of the first electrode on the substrate, and a normal projection of the second active structure on the substrate is located within a range of a normal projection of the second electrode on the substrate; The thickness of the first active layer is greater than the thickness of the second active layer, and the electrical conductivity of the second active layer is greater than the electrical conductivity of the first active layer.

31. The transistor device of claim 1, wherein, The thickness of the via along the direction perpendicular to the substrate is in a range of 1500 angstroms to 3500 angstroms.

32. A display substrate, comprising: A plurality of the transistor devices according to any one of claims 1 to 31. 33.The display substrate of claim 32, wherein, The display substrate has a display area and a non-display area, the display area is provided with a plurality of first circuits, and the non-display area is provided with a plurality of second circuits, at least one circuit in the first circuit and the second circuit comprises at least one switching device; the second circuit comprises: a gate drive circuit, a source drive circuit, a multiplexing circuit, an electrostatic discharge circuit, an array test circuit and a light-up test circuit; At least one switching device in at least one circuit in the first circuit and the second circuit is a transistor device. 34.The display substrate of claim 32, wherein, The gate drive circuit comprises a plurality of shift registers, and at least one stage of shift registers comprises: an input transistor and an output transistor; The input transistor and the output transistor are the transistor devices.

35. The display substrate of claim 32, further comprising: A light sensing structure configured to convert a light signal into an electrical signal; The light sensing structure comprises: at least one light sensing switching device, and the at least one light sensing switching device is the transistor device.

36. A method of fabricating a transistor device, wherein, A method configured to prepare the transistor device according to any one of claims 1 to 31, the method comprising: forming a gate electrode of the transistor device on a substrate; forming a gate insulating layer and an active layer of the transistor device on the gate electrode, the gate insulating layer comprises: a first insulating layer and a second insulating layer which are stacked and disposed on the substrate, one of the first insulating layer and the second insulating layer is provided with a via; a normal projection of the via on the substrate at least partially overlaps with a normal projection of the active layer on the substrate; forming a first electrode and a second electrode on the active layer; the forming of the gate insulating layer and the active layer of the transistor device on the gate electrode comprises: forming a first insulating layer on the gate electrode, the first insulating layer is provided with a via; forming a second insulating layer on the first insulating layer; forming a raw semiconductor layer on the second insulating layer, the raw semiconductor layer comprises: a first active layer and a third active layer; forming a first electrode, a second electrode and an active layer on the raw semiconductor layer, the active layer comprises: a first active layer and a second active layer.

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