Communication between independent monolithically integrated circuits

Abstract

The invention relates to a semiconductor device (10) comprising a monolithic semiconductor substrate (14) on which a first integrated circuit (12) and a separate second integrated circuit (16) are located. In addition, a first communication interface (18) is provided as part of the first integrated circuit (12), and a second communication interface (20) is provided as part of the second integrated circuit (16). Furthermore, the semiconductor device (10) comprises a connection line (22) which is at least partly located outside the monolithic semiconductor substrate (14) and by means of which the first communication interface (18) and the second communication interface (20) are connected for data transmission purposes.

Description

[0001] Description

[0002] Communication between independent, monolithically integrated circuits

[0003] The invention relates to a semiconductor device and a method for transferring data between two independent integrated circuits arranged separately on a monolithic semiconductor substrate.

[0004] Single-chip systems typically incorporate multiple independent functional units in the form of separate, monolithically integrated circuits on a single semiconductor substrate. These functional units can be implemented as simple logic functions, sensors, memory, or data processing devices, for example. A major advantage of single-chip systems is the ability to integrate a wide variety of functions onto the same semiconductor substrate. In a preferred application, multiple independent data processing devices can be integrated onto the same substrate. With multiple independent data processing devices, if one of them fails, the remaining devices can continue to operate without any negative impact.Such single-chip systems can be used, among other things, to control processes with high safety requirements regarding fault tolerance and / or operational reliability. Communication between the independent functional units is particularly necessary for such applications. This communication typically occurs from a sender to one or more receivers. In this way, for example, deviations in command execution can be detected by different, independent data processing units. This makes it possible to distribute different inputs and tasks across different data processing units and / or to compare outputs and derive a common response (vote).When establishing a communication link, particularly in safety-critical applications, a key challenge lies in ensuring the independence of the functional units of the single-chip system during communication between them. Until now, communication links between independent functional units have been integrated directly onto the monolithic semiconductor substrate. This created a physical connection between the independent functional units, which could facilitate mutual physical interference. Consequently, achieving the highest safety requirements has not been possible. Often, a layout for a physical communication interface had to be specifically designed and implemented for this purpose.Compared to commercially available communication interface layouts, also known as standard I / O cells, custom-designed communication interfaces are therefore more complex and costly. Furthermore, the voltage withstand capability, short-circuit withstand capability, and overall load capacity of these custom-designed interfaces are typically lower than those of standard I / O cells. Additionally, safety-related requirements, such as the independence and fault tolerance of the functional units, generally need to be tested in each individual layout of the custom-designed communication interfaces. Moreover, the integrated communication interfaces are usually interconnected for data transmission using metal traces integrated onto the monolithic semiconductor substrate.To minimize heat conduction and potential fault currents or overvoltages between the otherwise independent functional units, specific metallization layers and special cable routing were often chosen. Furthermore, additional distances and / or devices were required for thermal and / or electrical decoupling between the independent functional units. For this reason, it has not yet been possible to achieve the highest safety requirements, such as safety requirement level 4 as defined in standards EN 50129, IEC 61508, or IEC 61511.

[0005] The invention is based on the objective of providing an improved semiconductor device, which is implemented in particular as a single-chip system.

[0006] This problem is solved by a semiconductor device having the features of claim 1.

[0007] Furthermore, the invention is based on the objective of providing an improved method for transferring data between two independent integrated circuits arranged separately on a monolithic semiconductor substrate.

[0008] This problem is solved by a method with the features of a subordinate method claim.

[0009] Advantageous embodiments are the subject of dependent subclaims. The semiconductor device according to the invention comprises a monolithic semiconductor substrate on which a first integrated circuit and a second integrated circuit, implemented separately, are arranged. Preferably, the first integrated circuit and the second integrated circuit are implemented independently in accordance with standards EN 50129, IEC 61508, or IEC 61511. Furthermore, the semiconductor device according to the invention comprises a first communication interface and a second communication interface. In this context, a communication interface is a physical interface which, according to the OSI standard model, is assigned to layer 1. The first communication interface is part of the first integrated circuit. The second communication interface is part of the second integrated circuit.Furthermore, according to the invention, a connecting line is provided that is arranged at least partially outside the monolithic semiconductor substrate. In particular, this externally arranged connecting line is located within a chip package. The first communication interface and the second communication interface are connected to each other for data transmission via this connecting line. This eliminates the need for an integrated connecting line. The risk of potentially damaging thermal or electrical energy being transmitted between two integrated circuits can thus be reduced. This makes it possible to achieve high safety requirements, such as safety integrity level (SIL) 4 as defined in one of the standards EN 50129, IEC 61508, or IEC 61511. The independence of the two integrated circuits can be maintained despite the communication connection.

[0010] Preferably, the semiconductor device is implemented as a single-chip system. The single-chip system is also known as a system-on-a-chip. Advantageously, the first integrated circuit and the second integrated circuit are each part of a single-chip system.

[0011] An advantageous further development provides that the first communication interface and / or the second communication interface are implemented as prefabricated standard I / O cells. In the context of the present invention, a standard I / O cell is understood to be a prefabricated and / or pre-designed section of an integrated circuit in the sense of microelectronics. These standard I / O cells are a versatile, prefabricated layout that can be selected from a standard library according to predetermined functions and / or properties. In this way, a custom chip design can be created cost-effectively and efficiently.

[0012] Using standard I / O cells, communication interfaces can be selected according to specific requirements, including predetermined voltage withstand, short-circuit withstand, current rating, and / or robustness. This eliminates the need for complex, custom-designed layouts for communication interfaces. Individual testing of custom-developed layouts and integrated connecting cables is also unnecessary. In contrast, standard I / O cells can be selected and used cost-effectively. Furthermore, different types of communication interfaces can be combined, each potentially powered by its own separate voltage source.

[0013] A further advantageous improvement provides that the connecting cable has an electrical resistance for the purpose of power limitation. The electrical resistance effectively limits the electrical power that can be transmitted via the connecting cable. This reduces the risk of fault current and / or overvoltage transmission. Damage to independent integrated circuits due to electrical power transmitted via the connection can therefore be effectively prevented. Additionally, in the event of an overvoltage, an excessive potential drops across the resistance. This allows the voltage in a protected functional unit to remain limited.

[0014] Furthermore, an advantageous embodiment provides that the interconnect is arranged within a housing of the semiconductor device. The housing expediently protects the semiconductor device against external influences such as moisture, UV radiation, and / or dirt. A short interconnect length also minimizes electromagnetic interference from the surrounding environment. Additionally, metal shielding can be incorporated to further reduce electromagnetic interference. Such housings are often made of a resin and / or plastic that is molded around the semiconductor device. Moreover, this allows for small distances between independent integrated circuits. Furthermore, it prevents the interconnect from penetrating integrated barriers that separate independent integrated circuits.This allows for a barrier with a high level of protection against overvoltage and / or thermal influences. Preferably, the connecting line is a single wire. This enables reliable communication between independent functional units. Furthermore, high data transmission rates can be achieved.

[0015] Preferably, the connecting wire is made of a metal such as copper, aluminum, or gold. The wire itself can, for example, be designed as the aforementioned resistor. Furthermore, the wire can be designed as a fuse, such as a fusible link. The need for a specific design and selection of predetermined metallization layers, as well as a special integrated conductor routing, is eliminated. Instead, a simple, easy-to-handle connecting wire can be used for data transmission.

[0016] In an advantageous implementation, the first and second communication interfaces are implemented differently. This increases fault tolerance. For example, failures due to a common cause can be avoided. This makes it possible to provide a failure behavior for the first communication interface that is statistically independent of the failure behavior of the second communication interface.

[0017] In an advantageous alternative embodiment, it is provided that a portion of the first communication interface intended for sending data and a portion of the second communication interface intended for sending data are identical in construction but implemented in a first manner. Alternatively or additionally, it is provided that a portion of the first communication interface intended for receiving data and a portion of the second communication interface intended for receiving data are identical in construction but implemented in a second manner, different from the first. This alternative approach can enhance the detection of communication link failures, for example, in conjunction with data encoding or encoding of associated communication interfaces. Failures due to a common cause can thus be avoided.Furthermore, statistically independent failure behavior of the first communication interface and the second communication interface can be achieved in an alternative way.

[0018] In a further advantageous embodiment, the first integrated circuit and the second integrated circuit are separated from each other by means of a barrier. In particular, the barrier is designed to physically separate the aforementioned integrated circuits. Advantageously, the barrier separates a section of the monolithic semiconductor substrate, which has doped regions of the first integrated circuit, from another section of the monolithic semiconductor substrate, which has doped regions of the second integrated circuit. Preferably, the barrier extends down between the doped regions of the first integrated circuit and the doped regions of the second integrated circuit to the monolithic, and in particular undoped, semiconductor substrate.This allows the two separate integrated circuits to be thermally and / or electrically shielded from each other. In this way, the operational reliability and fault tolerance of the semiconductor device, especially the single-chip system, can be increased cost-effectively.

[0019] Furthermore, an advantageous refinement provides that the monolithic semiconductor substrate is free of an integrated interconnect for communication between the first and second integrated circuits. This allows for minimal safety distances between independent integrated circuits. Moreover, it enables a compact arrangement of multiple independent integrated circuits on the monolithic semiconductor substrate. In addition, any thermal and / or electrical hazard emanating from a neighboring integrated circuit can be minimized.

[0020] Preferably, the first integrated circuit and / or the second integrated circuit each include a data processing device. This makes it possible to implement a fail-safe control system based on a single-chip system. High safety requirements can be met cost-effectively and reliably. Single-chip systems with independent data processing devices are also cost-effective and inexpensive to implement.

[0021] The data processing device can be, for example, a microcontroller, a processor, or another programmable hardware component. The data processing device is advantageously configured to read, receive, write, transmit, and / or manage data. Particularly preferably, the data processing device is part of a computer with a storage device designed to store and / or manage data. Furthermore, the invention provides a method for transferring data between two independent integrated circuits arranged separately on a monolithic semiconductor substrate.

[0022] The method according to the invention provides that data is transmitted, at least partially, outside the monolithic semiconductor substrate. This eliminates the need for an interconnect integrated with the monolithic semiconductor substrate. Furthermore, it prevents the interconnect from penetrating a barrier intended to ensure the independence of the two separately arranged integrated circuits. This also allows for a high level of safety. The transmission of harmful thermal and / or electrical energy via the interconnect is prevented. This enables high fault tolerance and high operational reliability of the separately arranged integrated circuits. In particular, a reliable and safely operable single-chip system can be provided.Furthermore, a communication link between independent integrated circuits can be implemented in a cost-effective and efficient manner.

[0023] An advantageous further development of the method provides that the data is transmitted via a connecting cable running within a housing surrounding the monolithic semiconductor substrate. The housing is, in particular, of the type described above. Advantageously, the housing protects the semiconductor device against external influences such as moisture, UV radiation, and / or dirt. Furthermore, a short cable length minimizes electromagnetic interference from the environment. Additionally, metal shielding can be provided to reduce electromagnetic interference. This prevents the corruption of the transmitted data and thus enables reliable and dependable communication.

[0024] In a further advantageous development of the method, the reliability of data transmission is monitored using a computer-implemented algorithm, particularly by means of predetermined patterns. For example, the computer-implemented algorithm includes a channel security coding method, a handshake procedure, and / or the generation and verification of checksums. This enables rapid detection of communication link failures. This can make a significant contribution to achieving a high level of security.

[0025] One advantageous implementation involves monitoring a memory shared by communication interfaces and / or a coded interface used for data transmission. In this context, the memory and the coded interface are assigned to Layer 2 of the OSI standard model. For example, the shared memory can be subjected to memory checks. This allows for the detection of not only memory errors but also failures in cross-channel connections. Monitoring a coded interface enables rapid and reliable detection of a failure of a communication interface or part thereof.If, during monitoring of the coded interface, it is determined that a code does not correspond to a predetermined code, a failure of a communication interface or part thereof can be detected in a cost-effective manner.

[0026] The properties, features, and advantages of the invention described above, as well as the manner in which they are achieved, are explained in more detail in the following description of the exemplary embodiment of the invention and its variations, in conjunction with the figures. Where appropriate, the same reference numerals are used in the figures for the same or corresponding elements of the invention. The exemplary embodiment and its variations serve to illustrate the invention and do not limit the invention to the combinations of features specified therein, including functional features. Furthermore, all features specified in the exemplary embodiment can be considered in isolation and combined appropriately with the features of any claim. The figures described below are schematic drawings and not to scale.

[0027] They show:

[0028] FIG 1 shows an embodiment of a semiconductor device according to the invention;

[0029] FIG 2 illustrates an example of a method according to the invention for transferring data between two independent integrated circuits arranged separately on the embodiment of a semiconductor device described in more detail in connection with FIG 1, using a schematic flowchart.

[0030] FIG 1 shows a schematic representation of an embodiment of a semiconductor device 10. The semiconductor device 10 has a semiconductor substrate 14. Two independent integrated circuits 12, 16 are arranged separately on this semiconductor substrate 14.

[0031] In the present embodiment, the two independent integrated circuits 12, 16 are physically separated from each other by means of a barrier 26. The barrier 26 advantageously separates a section of the monolithic semiconductor substrate 14 with doped regions of a first integrated circuit 12 of the two integrated circuits 12, 16 from another section of the monolithic semiconductor substrate 14 with doped regions of a second integrated circuit 16 of the two integrated circuits 12, 16. Silicon dioxide or an insulating material with comparable properties is provided as an example material for the barrier 26. This allows a reliable thermal barrier to be achieved. Furthermore, a barrier with high dielectric strength can be provided for the purpose of shielding against overvoltages.

[0032] As an example, the two integrated circuits 12 and 16 are each intended for the purpose of controlling a process. For this purpose, in the embodiment described here, the two integrated circuits 12 and 16 each have a data processing device 28 and a memory 30. Depending on the application, further integrated sensors (not shown in detail) or other integrated logic circuits may be provided.

[0033] Furthermore, a first communication interface 18 is provided as part of the first integrated circuit 12. A second communication interface 20 is also provided as part of the second integrated circuit 16. The first communication interface 18 and the second communication interface 20 are each configured to transmit data between the two independent integrated circuits 12 and 16. For this purpose, a connecting line 22 is provided, which connects the first communication interface 18 to the second communication interface 20 for data transmission. The connecting line 22 is located outside the monolithic semiconductor substrate 14. In this way, the monolithic semiconductor substrate 14 is free of an integrated connecting line used for communication between the first integrated circuit 12 and the second integrated circuit 16.In the exemplary embodiment described here, the connecting cable 22 is arranged in a housing 24. This housing 24 is designed to protect the semiconductor device 10 from external influences, such as moisture or UV radiation. The housing is typically made of resin or plastic, with which the semiconductor device 10 is completely encased. Preferably, the connecting cable 22 is designed as a wire made of metal, such as aluminum, gold, or copper. This allows for a reliable data transmission connection with high data rates.

[0034] In a preferred embodiment, the first communication interface 18 and the second communication interface 20 are each implemented as a pre-configured standard I / O cell. This allows robust communication interfaces 18 and 20 to be selected from a chip manufacturer's standard libraries. As a result, a layout for a single-chip system can be designed and implemented cost-effectively and efficiently. Furthermore, this allows for the selection of predetermined voltage withstand capability, short-circuit withstand capability, current handling capacity, and / or robustness of the communication interfaces 18 and 20 as required.

[0035] In another preferred embodiment, the first communication interface 18 has a layout that is diverse with respect to the layout of the second communication interface 20. This can apply to the layout of either communication interface 18 or 20 itself, and / or to the layout of an integration of either communication interface 18 or 20. This allows a failure in a communication interface to be detected.

[0036] Alternatively, for this purpose it may be provided that a part of the first communication interface 18 intended for sending data and a part of the second communication interface 20 intended for sending data are identical in construction in a first way, and that a part of the first communication interface 18 intended for receiving data and a part of the second communication interface 20 intended for receiving data are identical in construction in a second way different from the first way.

[0037] Preferably, the connecting line 22 has an electrical resistance 32, which is provided for the purpose of limiting the transmissible electrical power. This allows for a high degree of independence with regard to the failure behavior of a transmitter and a receiver. This electrical resistance 32 can be provided, for example, by appropriately dimensioning the connecting line 32. Alternatively or additionally, the connecting line 22 can be designed as a fuse, which interrupts a communication link in the event of a predetermined electrical energy. This reduces the risk of overvoltage transmission via the connecting line 22. In this way, the two integrated circuits 12, 16 can be reliably operated as independent functional units despite a communication link.This allows for the fulfillment of high safety requirements. In particular, a safety requirement level 4, for example in accordance with one of the standards EN 50129, IEC 61508 or IEC 61511, can be achieved. This makes it possible to provide a reliable single-chip system with which highly critical control processes can be implemented. For example, this enables the safe and reliable control of railway or aircraft operations. With the present embodiment of the semiconductor device 10, a high level of functional reliability and / or high availability can therefore be provided, depending on the situation. In the preferred application, this allows for the provision of a functionally reliable single-chip system that meets the highest requirements.

[0038] FIG 2 illustrates an example of a method 100 for transferring data between the two independent integrated circuits 12, 16 arranged separately on the monolithic semiconductor substrate 14, using a schematic flowchart. Advantageously, the method 100 is carried out with the semiconductor device 10 described in more detail in connection with FIG 1.

[0039] In the example of method 100, it is provided that the data are transmitted at least section by section outside the semiconductor substrate 14 by means of the connecting line 22 102. Preferably, the data is transmitted 102 by means of the connecting line 22 in such a way that this data runs within the housing 24 surrounding the monolithic semiconductor substrate 14.

[0040] Furthermore, in the example of method 100 described here, the reliability of data transmission 102 is monitored by means of a computer-implemented algorithm 104. This enables rapid failure detection and high operational reliability of the semiconductor device 10. Moreover, high safety requirements can be met in this way. Preferably, the reliability of data transmission 102 is monitored by means of predetermined patterns 104. This allows a failure of a communication interface 18, 20, or a part thereof to be reliably and cost-effectively detected using known test mechanisms. This makes it possible to achieve a high level of safety for the operation of the semiconductor device 10. In particular, semiconductor devices 10 implemented as a single-chip system can be provided cost-effectively and reliably for safety-critical applications.Furthermore, in the event of a communication link failure, reliable measures can be taken to prevent damage.

[0041] Although the invention has been illustrated and described in detail by the preferred embodiment and its variations, the invention is not limited by the disclosed examples and other variations can be derived from them by a person skilled in the art without leaving the scope of protection of the invention.

[0042] Regardless of the grammatical gender of a particular term, persons with male, female or other gender identities are included.

Claims

Patent claims 1. Semiconductor device (10) comprising: - a monolithic semiconductor substrate (14) on which a first integrated circuit (12) and a separately designed second integrated circuit (16) are arranged; - a first communication interface (18) which is part of the first integrated circuit (12); - a second communication interface (20) which is part of the second integrated circuit (16); - a connecting line (22) arranged at least partially outside the monolithic semiconductor substrate (14), by means of which the first communication interface (18) and the second communication interface (20) are connected for the purpose of data transmission.

2. Semiconductor device (10) according to claim 1 , characterized in that the first communication interface (18) and / or the second communication interface (20) are designed as prefabricated standard IO cells.

3. Semiconductor device (10) according to claim 1 or 2, characterized in that the connecting line (22) has an electrical resistance (32) for the purpose of limiting power.

4. Semiconductor device (10) according to one of the preceding claims, characterized in that the connecting line (22) is arranged inside a housing (24) of the semiconductor device (10).

5. Semiconductor device (10) according to one of the preceding claims, characterized in that the connecting line (22) is designed as a wire.

6. Semiconductor device (10) according to one of the preceding claims, characterized in that The material for the connecting line (22) is a metal, such as aluminium, copper or gold.

7. Semiconductor device (10) according to one of the preceding claims, characterized in that the first communication interface (18) and the second communication interface (20) are designed differently.

8. Semiconductor device (10) according to one of claims 1 to 6, characterized in that a part of the first communication interface (18) intended for the purpose of sending data and a part of the second communication interface (20) intended for the purpose of sending data are identical in construction in a first manner and / or a part of the first communication interface (18) intended for the purpose of receiving data and a part of the second communication interface (20) intended for the purpose of receiving data are identical in construction in a second manner different from the first manner.

9. Semiconductor device (10) according to one of the preceding claims, characterized in that the first integrated circuit (12) and the second integrated circuit (16) are separated from each other by means of a barrier (26).

10. Semiconductor device (10) according to one of the preceding claims, characterized in that the monolithic semiconductor substrate (14) is free of an integrated interconnect for the purpose of communication between the first integrated circuit (12) and the second integrated circuit (16).

11. Semiconductor device (10) according to one of the preceding claims, characterized in that the first integrated circuit (12) and / or the second integrated circuit (16) each comprises a data processing device (28).

12. Method (100) for transferring (102) data between two independent integrated circuits (12, 16) arranged separately on a monolithic semiconductor substrate (14), in which the data are transferred at least partially outside the monolithic semiconductor substrate (14) (102).

13. Method (100) according to claim 12, wherein the data are transmitted by means of a connecting line (22) (102) which runs within a housing (24) surrounding the monolithic semiconductor substrate (14).

14. Method (100) according to claim 12 or 13, wherein the reliability of the transmission (102) of data is monitored by means of a computer-implemented algorithm, in particular by means of predetermined patterns (104).

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