Method and system for performing an auto correlation operation during processing of baseband input signal

Abstract

Disclosed is a method for performing an auto correlation operation during processing of a baseband input signal is disclosed. The method comprises receiving the baseband input signal comprising at least one of a time dimension, a frequency dimension, and a spatial dimension, and the baseband input signal comprising one or more resource elements. The method comprises performing a vectorization of the baseband input signal based on restructuring of the one or more resource elements into a plurality of vectors along the spatial dimension. Further, the method comprises inserting the vectorized baseband input signal into a first vector register among a set of vector registers, based on arrangement of the plurality of vectors in an adjacent manner. The method comprises replicating a first version of the vectorized baseband input signal from the first vector register into a second vector register and performing an auto correlation operation.

Description

METHOD AND SYSTEM FOR PERFORMING AN AUTO CORRELATION OPERATION DURING PROCESSING OF BASEBAND INPUT SIGNAL

[0001] The disclosure relates to the field of signal processing, and more particularly relates to a method and a system for performing an auto correlation operation during processing of baseband input signal.

[0002] Baseband signal processing in 5th generation (5G) new radio (NR) networks may present significant challenges to processing units due to high computational demands of real-time signal manipulation. These challenges arise from the need to support high data rates, massive multiple-input multiple-output (MIMO) configurations, and stringent latency requirements. As such, efficient baseband processing is essential to ensure seamless communication and optimal network performance.

[0003] Auto correlation is a fundamental operation in baseband signal processing, used to evaluate signal similarity over time. The auto correlation plays a crucial role in pattern recognition, channel estimation, and synchronization. Traditional methods of performing auto correlation typically rely on scalar processing or multi-core parallelism. However, the scalar processing is inefficient for handling large datasets, and the multi-core parallelism often suffers from memory bandwidth limitations and synchronization overheads, which negatively impact performance.

[0004] To address these limitations, reduced instruction set computer five (RISC-V) vector processors are increasingly employed for auto correlation tasks. The RISC-V vector processors offer several advantages, including enhanced parallelism, improved memory access efficiency, scalability, and energy efficiency. Unlike conventional scalar or multi-core systems, the RISC-V vector processors may execute operations on multiple data elements concurrently, thereby increasing computational throughput while reducing power consumption.

[0005] In physical layer (PHY) of physical uplink shared channel (PUSCH) receiver, the auto correlation of multi-dimensional resource elements is both essential and computationally intensive. These resource elements comprise user data, control information, and reference signals, across time, frequency, and spatial domains, and are processed in an uplink direction. The high dimensionality of these elements, particularly in scenarios involving advanced modulation schemes and large-scale deployments, significantly increases the computational demands of the auto correlation process.

[0006] Auto correlation plays a crucial role in demodulation and channel estimation by evaluating similarity between received signal and delayed versions of itself. The auto correlation operation is especially demanding in a frequency domain equalization (FDEQ) module, where Hermitian property of an auto correlation matrix and large data volumes impose heavy computational burdens. The requirement for real-time processing further amplifies these challenges, often exceeding the capabilities of the traditional methods.

[0007] In addition, the rapid evolution of 5G NR standards and the anticipated demands of 6th generation (6G) systems make the development of fixed-function custom hardware increasingly impractical and cost-inefficient. Thus, achieving optimal performance on RISC-V vector processors requires more than just parallel execution capabilities.

[0008] A significant bottleneck in RISC-V vector processing is memory access efficiency. The auto correlation tasks often involve strided memory access patterns, particularly during frequency domain subcarrier processing. These non-contiguous memory accesses introduce latency that undermines the benefits of vectorization. Therefore, optimizing memory layout and access strategies is critical for performance.

[0009] Figure 1a illustrates a conventional baseband signal processing architecture, in accordance with related art. As shown, in conventional baseband processing architectures 100, an input signal 102-A is typically stored in a PUSCH data memory 104-A, where the input signal 102-A is subjected to high-latency memory and compute operations. The conventional baseband processing architecture often rely on multi-core processors 106-A, with each core operating either as a scalar core or employing sub-optimal vector processing techniques. While such configurations offer flexibility, they suffer from inefficient data parallelism and frequent memory access delays, leading to performance bottlenecks in time-sensitive operations such as the auto correlation. Moreover, hardware accelerators 108-A such as application-specific integrated circuits (ASICs) or application-specific instruction-set processors (ASIPs), are often tightly coupled to specific software specifications. These hardware accelerators 108 make them expensive and impractical to update, particularly in environments where frequent software upgrades are required to keep pace with evolving 5G NR and future 6G standards.

[0010] Figure 1b illustrates an auto correlation computation flow in the conventional baseband signal processing, in accordance with the related art. In conventional 5G NR signal processing architecture, time is structured hierarchically to support precise scheduling and processing. A radio frame is defined as a 10 millisecond (ms) duration and is divided into 10 sub-frames, each 1 ms long. Each sub-frame comprises 2 slots, where each slot spans 0.5 ms and contains 14 OFDM symbols under a normal cyclic prefix configuration. The input signal for physical uplink shared channel (PUSCH) processing consists of resource elements (REs) 102-B, which are the smallest units of time-frequency resources. The REs 102-B carry modulated data, control information, and reference signals and are arranged across time, frequency, and spatial domains. During the auto correlation computation flow 104-B, the received REs 102-B are first stored in the PUSCH data memory. From there, signal segments are extracted over defined symbol windows and processed to compute similarity of the signal segments with delayed versions of the signal segments. The operation involves complex multiply-accumulate (MAC) computations and generates an auto correlation matrix 106-B, which exhibits Hermitian symmetry. The auto correlation matrix 106-B is used for channel estimation, equalization, and signal demodulation, producing refined data symbols as final output for higher-layer decoding.

[0011] However, the traditional baseband signal processing architectures as discussed in Figure 1a and Figure 1b face significant performance bottlenecks in auto correlation due to unstructured input layouts, strided memory access patterns, and limited parallelism in scalar or sub-optimal vector implementations. These inefficiencies result in high memory latency and underutilization of compute resources, particularly when processing multi-dimensional resource elements in real-time.

[0012] Therefore, there lies a need for an improved solution that can address the above-mentioned issues and the limitations of the existing systems and methods.

[0013] In accordance with an example embodiment of the disclosure, a method for performing an auto correlation operation during processing of a baseband input signal. The method includes receiving the baseband input signal comprising one or more resource elements. The baseband input signal is a multi-dimensional signal comprising at least one of a time dimension, a frequency dimension, and a spatial dimension. The method includes performing a vectorization of the baseband input signal based on restructuring of the one or more resource elements into a plurality of vectors along the spatial dimension. Further, the method includes inserting the vectorized baseband input signal into a first vector register among a set of vector registers, based on arrangement of the plurality of vectors in an adjacent manner. Furthermore, the method includes replicating a first version of the vectorized baseband input signal from the first vector register into a second vector register within the set of vector registers. Moreover, the method includes performing an auto correlation operation on the vectorized baseband input signal in the first vector register and the second vector register.According to an example embodiment of the disclosure, a system for performing an auto correlation operation during processing of a baseband input signal is disclosed. The system includes memory storing instructions and one or more processors (302) communicatively coupled to the memory. The instructions, when executed by the one or more processors (302) individually or collectively, cause the system to receive the baseband input signal comprising one or more resource elements. The baseband input signal is a multi-dimensional signal comprising at least one of a time dimension, a frequency dimension, and a spatial dimension. The instructions, when executed by the one or more processors individually or collectively, cause the system to perform a vectorization of the baseband input signal based on restructuring of the one or more resource elements into a plurality of vectors along the spatial dimension. The vectorization of the baseband input signal is performed within the memory of the one or more processors. Further, the instructions, when executed by the one or more processors individually or collectively, cause the system to insert the vectorized baseband input signal from the memory into a first vector register among a set of vector registers in the one or more processors, based on arrangement of the plurality of vectors in an adjacent manner. Furthermore, the instructions, when executed by the one or more processors individually or collectively, cause the system to replicate a first version of the vectorized baseband input signal from the first vector register into a second vector register within the set of vector registers. Moreover, the instructions, when executed by the one or more processors individually or collectively, cause the system to perform an auto correlation operation on the vectorized baseband input signal in the first vector register and the second vector register.

[0014] According to an example embodiment of the disclosure, one or more non-transitory computer-readable storage media storing computer-executable instructions that, when executed by at least one processor of a system, cause the system to perform operations, the operations comprising receiving the baseband input signal comprising one or more resource elements, wherein the baseband input signal is a multi-dimensional signal comprising at least one of a time dimension, a frequency dimension, and a spatial dimension, performing a vectorization of the baseband input signal based on restructuring of the one or more resource elements into a plurality of vectors along the spatial dimension, inserting the vectorized baseband input signal into a first vector register among a set of vector registers, based on arrangement of the plurality of vectors in an adjacent manner, replicating a first version of the vectorized baseband input signal from the first vector register into a second vector register within the set of vector registers, and performing an auto correlation operation on the vectorized baseband input signal in the first vector register and the second vector register.

[0015] To further clarify the advantages and features of the disclosure, a more particular description of the disclosure will be rendered by reference to specific embodiments thereof, which are illustrated in the appended drawings. It is appreciated that these drawings depict only typical embodiments of the disclosure and are therefore not to be considered limiting of its scope. The disclosure will be described and explained with additional specificity and detail with the accompanying drawings.

[0016] The accompanying drawings, which are incorporated in and are a part of this disclosure, illustrate various example embodiments and together with the description, serve to explain the disclosed principles. The same reference numbers may be used throughout the figures to reference like features and components. The above and other aspects, features and advantages of certain embodiments of the disclosure will be more apparent from the following detailed description, taken in conjunction with the accompanying drawings, in which:

[0017] Figure 1a illustrates a conventional baseband signal processing architecture, in accordance with related art;

[0018] Figure 1b illustrates an auto correlation computation flow in the conventional baseband signal processing, in accordance with related art;

[0019] Figure 2 illustrates an example environment depicting a system performing an auto correlation operation during processing of a baseband input signal, in accordance with various embodiments of the disclosure;

[0020] Figure 3 illustrates a block diagram of the system for performing the auto correlation operation during the processing of the baseband input signal, in accordance with various embodiments of the disclosure;

[0021] Figure 4 illustrates a schematic workflow performing the auto correlation operation during the processing of the baseband input signal, in accordance with various embodiments of the disclosure;

[0022] Figure 5 illustrates a process flow of complex data processing, in accordance with related art;

[0023] Figure 6 illustrates a process flow of complex data processing through custom extension, in accordance with various embodiments of the disclosure;

[0024] Figure 7 illustrates a process flow of whitening-based channel estimation, in accordance with related art;

[0025] Figure 8 illustrates a process flow of data restructuring, in accordance with various embodiments of the disclosure;

[0026] Figure 9 illustrates a process flow of data restructuring to eliminate strided loading, in accordance with various embodiments of the disclosure;

[0027] Figure 10 illustrates a process flow of exploiting pipelining and Single Instruction, Multiple Data (SIMD) width, in accordance with various embodiments of the disclosure;

[0028] Figure 11a and Figure 11b illustrate a process flow of memory dependency, in accordance with various embodiments of the disclosure; and

[0029] Figure 12 illustrates a process flow of a method for performing the auto correlation operation during the processing of a baseband input signal, in accordance with various embodiments of the disclosure.

[0030] It should be appreciated by those skilled in the art that any block diagrams herein represent conceptual views of illustrative systems embodying the principles of the disclosure. Similarly, it will be appreciated that any flowcharts, flow diagrams, state transition diagrams, pseudo code, and the like represent various processes which may be substantially represented in computer readable medium and executed by a computer or processor, whether or not such computer or processor is explicitly shown.

[0031] In the disclosure, the word "exemplary" is used herein to refer, for example, to "serving as an example, instance, or illustration." Any embodiment or implementation of the disclosure described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments.

[0032] While the disclosure is susceptible to various modifications and alternative forms, various example embodiments are shown by way of example in the drawings and will be described in greater detail below. It should be understood, however that it is not intended to limit the disclosure to the particular forms disclosed, but on the contrary, the disclosure is to cover all modifications, equivalents, and alternatives falling within the scope of the disclosure.

[0033] The term "some" as used herein is defined as "none, or one, or more than one, or all." Accordingly, the terms "none," "one," "more than one," "more than one, but not all" or "all" would all fall under the definition of "some." The term "some embodiments" may refer to no embodiments or to one embodiment or to several embodiments or to all embodiments. Accordingly, the term "some embodiments" is defined as meaning "no embodiment, or one embodiment, or more than one embodiment, or all embodiments."

[0034] The terminology and structure employed herein are for describing, teaching, and illuminating some embodiments and their specific features and elements and do not limit, restrict, or reduce the spirit and scope of the claims or their equivalents.

[0035] More specifically, any terms used herein such as but not limited to "includes," "comprises," "has," "consists," and grammatical variants thereof do NOT specify an exact limitation or restriction and certainly do NOT exclude the possible addition of one or more features or elements, unless otherwise stated, and furthermore must NOT be taken to exclude the possible removal of one or more of the listed features and elements, unless otherwise stated with the limiting language "MUST comprise" or "NEEDS TO include."

[0036] Unless otherwise defined, all terms, and especially any technical and / or scientific terms, used herein may be taken to have the same meaning as commonly understood by one having an ordinary skill in the art.

[0037] Reference is made herein to some "embodiments." It should be understood that an embodiment is an example of a possible implementation of any features and / or elements presented in the attached claims. Some embodiments have been described for the purpose of illuminating one or more of the potential ways in which the specific features and / or elements of the attached claims fulfill the requirements of uniqueness, utility, and non-obviousness.

[0038] Use of the phrases and / or terms such as but not limited to "a first embodiment," "a further embodiment," "an alternate embodiment," "one embodiment," "an embodiment," "multiple embodiments," "some embodiments," "other embodiments," "a further embodiment", "furthermore embodiment", "additional embodiment" or variants thereof do NOT necessarily refer to the same embodiments. Unless otherwise specified, one or more particular features and / or elements described in connection with one or more embodiments may be found in one embodiment or may be found in more than one embodiment, or may be found in all embodiments, or may be found in no embodiments.

[0039] Although one or more features and / or elements may be described herein in the context of only a single embodiment, or alternatively in the context of more than one embodiment, or further alternatively in the context of all embodiments, the features and / or elements may instead be provided separately or in any appropriate combination or not at all. Conversely, any feature and / or element described in the context of separate embodiments may alternatively be realized as existing together in the context of a single embodiment.

[0040] Any particular and all details set forth herein are used in the context of some embodiments and therefore should NOT be necessarily taken as limiting factors to the attached claims. The attached claims and their legal equivalents can be realized in the context of embodiments other than the ones used as illustrative examples in the description below.

[0041] Further, skilled artisans will appreciate those elements in the drawings that are illustrated for simplicity and may not have necessarily been drawn to scale. For example, the flow charts illustrate the method in terms of the most prominent steps involved to help improve understanding of aspects of the disclosure. Furthermore, in terms of the construction of the device, one or more components of the device may have been represented in the drawings by conventional symbols, and the drawings may show only those specific details that are pertinent to understanding the embodiments of the disclosure so as not to obscure the drawings with details that will be readily apparent to those of ordinary skill in the art having the benefit of the description herein.

[0042] The disclosure provides an optimized approach to baseband auto correlation for vector processing units by restructuring resource elements of a baseband signal to enable high-speed vectorized processing. By leveraging reduced instruction set computer five (RISC-V) vector extensions, the disclosure enhances the efficiency and scalability of signal computation.

[0043] The disclosure is to provide a system and method that overcomes the limitations found in prior art methods and systems related to baseband input signal processing.

[0044] The disclosure is to restructure resource elements across spatial antenna dimensions to achieve vectorization of the baseband input signals for high performance RISC-V vector processing, simultaneously reduce high latency computations, and compute an auto correlation matrix.

[0045] The disclosure is to linearly load the restructured and vectorized input resource elements into a first vector register file. The loaded vectors are replicated into a second vector register file and slid to left by one element. The auto correlation is performed between operands of the first and the second vector registers. An output of the auto correlation is stored as diagonal entries into a memory.

[0046] Embodiments of the disclosure will be described below in detail with reference to the accompanying drawings.

[0047] Figure 2 illustrates an example environment 200 depicting a system 208 performing an auto correlation operation during processing of a baseband input signal, in accordance with various embodiments of the disclosure.

[0048] Referring to Figure 2, the environment 200 depicts an implementation of a system 208 performing an auto correlation operation during the processing of the baseband input signal. A communication network may serve as a backbone for data exchange between devices, utilizing either wired connections or wireless transmission channels. In long term evolution (LTE) and fifth generation (5G) wireless networks (hereinafter collectively referred to as "the network"), multiple protocol layers may operate in a coordinated manner to ensure reliable and efficient signal transmission. At a foundational level, a physical layer (PHY) may be responsible for processing the baseband input signals. In one non-limiting example, the baseband input signals may comprise unmodulated signals that carry raw data prior to modulation or frequency translation.

[0049] A physical uplink shared channel (PUSCH) receiver 202 may be implemented within the PHY layer to process uplink transmissions from user equipment (UE) to a base station, such as an evolved nodeB (eNB) in LTE or a next-generation nodeB (gNB) in 5G. The PUSCH receiver 202 may facilitate the transfer of diverse data types, including but not limited to voice, video, and application-specific traffic. The PUSCH receiver 202 may dynamically allocate uplink resources based on current network conditions, thereby optimizing transmission performance and spectral efficiency of the baseband input signals.

[0050] The PHY layer for the PUSCH receiver, including the PUSCH receiver 202 itself, may incorporate a RISC-V digital signal processor (DSP) architecture 204. The RISC-V DSP 204 may be configured to accelerate execution of PHY layer kernels, which may include reusable and computationally intensive signal processing functions such as filtering, correlation, modulation, channel estimation, fast fourier transform (FFT), inverse FFT (IFFT), and equalization. To support these tasks, the RISC-V DSP 204 may utilize vector extensions and custom instruction extensions, thereby enabling parallel and optimized execution of these kernels to meet real-time processing requirements applied to the baseband input signals.

[0051] Further, the PUSCH receiver 202 may perform multiple signal processing functions on the baseband input signals, including but not limited to demodulation, decoding, power control, multiple-input multiple-output (MIMO) processing, and error correction. However, since wireless channels may suffer from impairments such as noise, interference, and multipath fading, an advanced signal processing methods may be applied to preserve quality and integrity of the received baseband input signals.

[0052] One such method may be frequency domain equalization (FDEQ) 206, which may be implemented as a sub-module within the PHY layer. The FDEQ method 206 may operate in a frequency domain to mitigate frequency-selective distortion in the baseband input signals, improving receiver's ability to recover an intended signal from noise and interference. To enable precise equalization and decoding, upstream synchronization and signal refinement may be necessary. Accordingly, the FDEQ method 206 may include the system 208 which may perform an auto correlation-based processing on the baseband input signals to refine synchronization accuracy and estimate interference characteristics. The system 208 may enhance robustness and clarity of the baseband input signals, particularly under challenging or degraded radio conditions.

[0053] In an example embodiment, the system 208 may be configured to receive the baseband input signal. In a non-limiting example, the baseband input signal is a multi-dimensional signal comprising at least one of a time dimension, a frequency dimension, and a spatial dimension. Further, the baseband input signal comprises one or more resource elements. In a non-limiting example, the one or more resource elements distributed across the time dimension are indicated as a plurality of an orthogonal frequency division multiplexing (OFDM) symbols, across the frequency dimension is indicated as a plurality of subcarriers, and across the spatial dimension is indicated as at least one antenna. Furthermore, the one or more resource elements are arranged in a non-stride pattern into the plurality of vectors.

[0054] For instance, in an LTE or 5G system, the baseband input signal may consist of resource elements arranged over multiple orthogonal frequency division multiplexing (OFDM) symbols (time dimension) and subcarriers (frequency dimension), while also spanning multiple antenna ports in a multiple input multiple output (MIMO) configuration (spatial dimension). Further, one or more resource elements represent a smallest unit of resource allocation, carrying modulation symbols that convey user data or control information.

[0055] In an example embodiment, the system 208 may be configured to perform a vectorization of the baseband input signal based on restructuring of the one or more resource elements into a plurality of vectors along the spatial dimension. In a non-limiting example, the vectorization of the baseband input signal is performed within a memory of a processor. In an example embodiment, the vectorization of the baseband input signal may refer to a process of organizing multi-dimensional baseband data, for instance, along the spatial dimension, into vector formats suitable for efficient parallel processing. By representing the baseband input signal as vectors, signal processing methodologies may leverage vector operations and hardware accelerators, such as the RISC-V DSPs 204 with vector extensions, to perform computations such as filtering, correlation, and equalization more efficiently and with reduced latency.

[0056] In an example embodiment, the system 208 may be configured to insert the vectorized baseband input signal from the memory into a first vector register among a set of vector registers in the processor, based on an arrangement of the plurality of vectors in an adjacent manner. In a non-limiting example, a set of vector registers in the processor is may be a collection of registers designed to hold vectors that enable parallel processing of the baseband input signal. In a non-limiting example, the first vector register in the set of vector registers is may be an initial or lowest-indexed register.

[0057] In an example embodiment, the system 208 may be configured to replicate a first version of the vectorized baseband input signal from the first vector register into a second vector register within the set of vector registers. In a non-limiting example, the first version of the vectorized baseband input signal is a slided version. In a non-limiting example, the second vector register may be a next sequential register following the first vector register within the set of vector registers in the processor.

[0058] Further, to replicate the first version of the vectorized baseband input signal in the second vector register, the system 208 may be configured to shift the plurality of vectors of the first vector to left by one element. The system 208 may be configured to obtain the first version of the vectorized baseband input signal in the second vector register based on replicating the shifted plurality of vectors into the second vector register.

[0059] In an example embodiment, the system 208 may be configured to perform the auto correlation operation on the vectorized baseband input signal in the first vector register and the second vector register.

[0060] In an example embodiment, the system 208 may be configured to obtain a set of correlation values based on performing the auto correlation on the vectorized baseband input signal in the first vector register and the second vector register.

[0061] In an example embodiment, the system 208 may be configured to store the set of correlation values diagonally in the memory.

[0062] In a non-limiting example, the set of correlation values indicates a similarity between the vectorized baseband input signal in the first vector register and the vectorized baseband input signal in the second vector register, along the spatial dimension. In a non-limiting example, the set of correlation values is computed by sliding the first vector register over the second vector register and measuring a weighted sum at each offset. Accordingly, detects matching patterns for synchronization, channel estimation, or signal detection. For example, a baseband input signal is represented as a vector [0.9, 1.1, 1.0, 0.95] and a reference signal as [1.0, 1.0, 1.0]. To compute correlation, the reference signal is slid over the baseband input signal. At lag 0 (no shift), the first three elements of the baseband input signal [0.9, 1.1, 1.0] are compared with the reference signal, resulting in a correlation value of 3.0. At lag 1 (reference shifted by one position), the next segment [1.1, 1.0, 0.95] is compared, yielding a correlation value of 3.05.

[0063] In an example embodiment, the system 208 may be configured to transpose the spatial dimension and the frequency dimension of the baseband input signal to create a transposed radio signal comprising one or more transposed resource elements. For example, if a baseband input signal is arranged in a way so that rows represent antennas and columns represent frequencies, therefore, transposing the baseband input signal may make the rows represent frequencies and the columns represent antennas. In a non-limiting example, the transposed radio signal is a version of the baseband input signal where an order of the spatial (antenna) dimension and the frequency dimension are swapped.

[0064] In an example embodiment, the system 208 may be configured to load, into the memory, the transposed radio signal and generate, in the memory, a first-sequence radio signal comprising one or more first-sequence resource elements from the transposed radio signal.

[0065] In an example embodiment, the system 208 may be configured to perform the auto correlation operation of the one or more transposed resource elements with the one or more first-sequence resource elements.

[0066] Figure 3 illustrates a block diagram of the system 208 for performing the auto correlation operation during processing of the baseband input signal, in accordance with various embodiments of the disclosure.

[0067] In an example embodiment, the system 208 may include at least a processor 302, a memory 304, a plurality of modules 306, and a data unit 308. The processor 302, the memory 304, the plurality of modules 306, and the data unit 308 are communicably coupled with each other.

[0068] In an example embodiment, the at least one processor 302 may be in communication with the memory 304. The at least one processor 302 may be a single processing unit or several units, all of which could include multiple computing units. The at least one processor 302 may be implemented as one or more microprocessors, microcomputers, microcontrollers, digital signal processors, central processing units, state machines, logic circuitries, and / or any devices that manipulate signals based on operational instructions. Among other capabilities, the at least one processor 302 may be configured to fetch and execute computer-readable instructions and data stored in the memory 304. The at least one processor 302 according to an embodiment of the disclosure may include various processing circuitry and / or multiple processors. For example, as used herein, including the claims, the term "processor" may include various processing circuitry, including at least one processor, wherein one or more of at least one processor, individually and / or collectively in a distributed manner, may be configured to perform various functions described herein. As used herein, when "a processor", "at least one processor", and "one or more processors" are described as being configured to perform numerous functions, these terms cover situations, for example and without limitation, in which one processor performs some of recited functions and another processor(s) performs other of recited functions, and also situations in which a single processor may perform all recited functions. Additionally, the at least one processor may include a combination of processors performing various of the recited / disclosed functions, e.g., in a distributed manner. At least one processor may execute program instructions to achieve or perform various functions.

[0069] In an example embodiment, the memory 304 may include any non-transitory computer-readable medium known in the art including, for example, volatile memory, such as static random-access memory (SRAM) and dynamic random-access memory (DRAM), and / or non-volatile memory, such as read-only memory (ROM), erasable programmable ROM, flash memories, hard disks, optical disks, and magnetic tapes. The memory 304, also, stores processor instructions which, when executed, may cause the at least one processor 302 to execute the instructions for performing an auto correlation operation during processing of baseband input signal.

[0070] In an example embodiment, the plurality of modules 306 may be configured to perform the auto correlation operation during the processing of the baseband input signal.

[0071] In an example embodiment, the data unit 308 amongst other things, includes routines, programs, objects, components, data structures, and like, which perform particular tasks or implement data types. The data unit 308 may also be implemented as signal processor(s), state machine(s), logic circuitries, and / or any other device or component that manipulates signals based on operational instructions. Further, the data unit 308 may be implemented in hardware, instructions executed by a processing unit, or by a combination thereof. The processing unit may comprise a processor, such as the at least one processor 302, a state machine, a logic array, or any other suitable devices capable of processing instructions. The processing unit may be a general-purpose processor which executes instructions to cause the general-purpose processor to perform the required tasks or, the processing unit may be dedicated to performing the required functions. In another embodiment of the disclosure, the data unit 308 may be machine-readable instructions (software) that, when executed by the processor 302, perform any of the described functionalities.

[0072] Figure 4 illustrates a schematic workflow performing the auto correlation operation during the processing of the baseband input signal, in accordance with various embodiments of the disclosure.

[0073] The autocorrelation operation of the baseband input signals may be described as a multi-step process optimized for high-performance execution through custom instruction extensions and memory restructuring techniques.

[0074] At operation 402, the system 208 may utilize custom instruction extensions such as complex multiply and accumulate (CMAC), along with operations on adjacent real and imaginary resource elements, to enable efficient complex-valued computations.

[0075] At operation 404, the system 208 may restructure multi-dimensional baseband input signal to eliminate costly computations and enhance vectorization. The restructuring may include a shift in memory access patterns from a frequency domain (sub-carriers) to a spatial domain (antennas), improving data locality and computational efficiency.

[0076] At operation 406, the system 208 may further restructure the baseband input signals to support linear loading of vector elements, reducing reliance on inefficient strided memory accesses.

[0077] At operation 408, the system 208 may merge two spatial dimensions, typically antennas and receiver jobs, into a single dimension, thereby facilitating linear loading of large vector elements and streamlining vector operations.

[0078] At operation 412, the system 208 may compute an autocorrelation matrix through diagonal entry-wise operations. For computation, at operation 410, the system 208 may correlate the first vector register with various slided and shifted versions of the second vector register. The results obtained after correlation are stored along diagonal entries using strided storage patterns, completing the autocorrelation computation in an efficient and vector-friendly manner.

[0079] Figure 5 illustrates a process flow of complex data processing, in accordance with related art.

[0080] Referring to Figure 5, real resource elements 502 and imaginary resource elements 504 may be loaded into separate vectors 506 and 508, respectively, using strided load operations. The real and imaginary resource elements 502, and 504 may be organized into four input vectors 506 and 508 respectively, and may be subjected to complex operations at operation 510. A result of the complex operation may produce two distinct output vectors 512, and 514, e.g., one for real components and other for imaginary components. The output vectors 512, and 514 may be stored back into the memory separately using strided store instructions. However, implementation of the process as discussed in Figure 5 may offer limited single instruction, multiple data (SIMD) exploitation due to use of smaller vector sizes. In a non-limiting example, exploiting SIMD involves identifying tasks where the same operation may be applied to multiple data elements and utilizing SIMD instructions to perform these operations in parallel.

[0081] Figure 6 illustrates a process flow of complex data processing through custom extension, in accordance with various embodiments of the disclosure.

[0082] Referring to Figure 6, the system 208 may use an element length (ELEN) of 64bit and a single element width (SEW) of 32bit. The system 208 may load the real resource element 602 and the imaginary resource element 604 together in a linear fashion to obtain an input vector. Thereafter, the system 208 may perform a complex operation on the input vector resulting in a single vector 606 containing both real and imaginary elements allowing for linear storage in output memory. Thus, the system 208 may allow llightweight linear loading of the real resource element and the imaginary resource elements into two separate vectors. The linear storing of the real resource element and the imaginary resource elements from the single vector 606 in output memory. In this way, the system 208 may allow for more SIMD exploitation due to larger vector sizes.

[0083] Figure 7 illustrates a process flow of whitening-based channel estimation, in accordance with related art.

[0084] The autocorrelation functions in the whitening-based channel estimation are critical for optimizing signal processing performance. However, the whitening-based channel estimation may introduce a significant computational complexity. The whitening-based channel estimation process involves complex conjugate multiplications across multiple antennas 702 and accumulation over all subcarriers within relevant resource blocks. Further, to improve throughput, SIMD operations 704 (conditional multiply high, CMULH) are applied along the subcarrier dimension, enabling efficient vectorized computation. However, this vectorization introduces a need for a horizontal accumulation step, which becomes a major performance bottleneck. Specifically, the high-latency reduction (e.g., horizontal sum) across the subcarrier vector introduces delays that degrade overall processing efficiency.

[0085] Figure 8 illustrates a process flow of data restructuring, in accordance with various embodiments of the disclosure.

[0086] To eliminate the horizontal accumulation along the subcarrier dimension as discussed in Figure 7, the system 208 may transition the SIMD operations from the frequency domain e.g. subcarrier based, to time domain e.g. antenna-based. Thus, the system 208 may require an accumulator to accumulate results of the SIMD operations, as the horizontal accumulation may be replaced with vertical accumulation. The system 208 may introduce strided loading e.g. loading elements separated by a fixed distance in the memory.

[0087] Figure 9 illustrates a process flow of data restructuring to eliminate strided loading, in accordance with various embodiments of the disclosure.

[0088] To eliminate the strided loading as discussed in Figure 8, the baseband input signals 902 may be restructured in a way to allow time domain based loading instead of frequency domain based loading with unit strides e.g. adjacent data elements. The strided loading may be a heavier operation compared to the unit strides e.g. normal loading which is for the one or more resource elements lying adjacent to each other. To eliminate strided memory access, computation 904 may be performed for restructuring such that elements in the time-domain dimension are stored contiguously. This enables unit-stride memory loading, allowing efficient retrieval of the baseband input signals from the memory. This optimization requires system 208 to reorganize the baseband input signals such that a matrix 906 is formed in the memory with a time-domain-major order, that is, the time-domain dimension is aligned along rows if the data is stored in a row-major format.

[0089] Figure 10 illustrates a process flow of exploiting pipelining and SIMD width, in accordance with various embodiments of the disclosure.

[0090] For optimizing the RISC-V vector processing, it is critical to maximize amount of baseband input signals processed in parallel to enhance performance through efficient pipelining and full utilization of SIMD width. However, with a constraint of 16 antennas, the traditional methodologies limit use of wider vector registers and length multiplier (LMUL) capability in the SIMD architectures. Thus, hampering vector combining and reducing pipelining efficiency. To exploit pipelining and the SIMD width, the system 208 may merge two independent dimensions of computation: antennas and receiver jobs 1002. Since accumulation in the autocorrelation process is performed over sub-carriers, and not across antennas or receiver jobs, the two spatial dimensions remain independent and may be fused without affecting correctness, as shown in 1004. By restructuring the baseband input signals to combine antennas and receiver jobs, workload per vector instruction increases, enabling better exploitation of the SIMD width and deeper pipelining, as shown in 1006. Thus, the system 208 may boost overall performance.

[0091] Figures 11a and Figure 11b illustrate a process flow of memory dependency, in accordance with various embodiments of the disclosure.

[0092] In the RISC-V vector processing, performance may be further optimized by minimizing memory dependency, which introduces latency and slightly reduces computational efficiency. The memory dependency occurs when data must be repeatedly fetched from memory, delaying processing. One common operation in signal processing and related applications involves multiplying a vector (an ordered set of numerical values) with either a scalar or another vector. Traditionally, this scalar may be retrieved from the memory, contributing to the latency.

[0093] To mitigate this drawback, the system 208 may instead perform a multiplication between the vector and a shifted (or "slided") version of itself, thereby avoiding need to access external the memory for each scalar value. This operation effectively computes the autocorrelation 1104, a measure of similarity between a signal and a delayed version of itself. The result of this process is the autocorrelation matrix 1106, which captures how elements of the vector correlate at different shifts. The autocorrelation matrix 1106 may contain autocorrelation information. The autocorrelation matrix 1106 is inherently sparse and primarily contributes values along its diagonal, the system 208 may need to store the diagonal elements using strided storage. The strided storage is lower resource-intensive than dense memory access, thereby further reducing memory bandwidth requirements and improving overall system efficiency.

[0094] Figure 12 illustrates a process flow of a method for performing an auto correlation operation during the processing of a baseband input signal, in accordance with various embodiments of the disclosure.

[0095] The method 1200 may be a computer-implemented method executed, for example, by the system 208 and / or the processor 302. For the sake of brevity, constructional and operational features of the system 208 that are already explained in the description of Figures 2-11 are not explained in detail in the description of Figure 12.

[0096] At operation 1202, the method 1200 may include receiving, by the processor 302, the baseband input signal. In a non-limiting example, the baseband input signal is the multi-dimensional signal comprising at least one of the time dimension, the frequency dimension, and the spatial dimension, and the baseband input signal comprises one or more resource elements.

[0097] Further, the baseband input signal comprises one or more resource elements. In a non-limiting example, the one or more resource elements distributed across the time dimension is indicated as the plurality of the OFDM symbols, across the frequency dimension is indicated as the plurality of subcarriers, and across the spatial dimension is indicated as the at least one antenna. Furthermore, the one or more resource elements are arranged in the non-stride pattern into the plurality of vectors. Further, the one or more resource elements represent the smallest unit of resource allocation, carrying modulation symbols that convey user data or control information.

[0098] At operation 1204, the method 1200 may include performing the vectorization of the baseband input signal based on restructuring of the one or more resource elements into the plurality of vectors along the spatial dimension. In a non-limiting example, the vectorization of the baseband input signal is performed within the memory 304 of the processor 302.

[0099] At operation 1206, the method 1200 may include inserting the vectorized baseband input signal from the memory into the first vector register among the set of vector registers in the processor 302, based on the arrangement of the plurality of vectors in the adjacent manner.

[0100] At operation 1208, the method 1200 may include replicating the first version of the vectorized baseband input signal from the first vector register into the second vector register within the set of vector registers. In a non-limiting example, the first version of the vectorized baseband input signal is the slided version. In a non-limiting example, the second vector register may be the next sequential register following the first vector register within the set of vector registers in the processor.

[0101] Further, to replicate the first version of the vectorized baseband input signal in the second vector register, the method 1200 may include shifting the plurality of vectors of the first vector to left by one element. The method 1200 may include obtaining the first version of the vectorized baseband input signal in the second vector register based on replicating the shifted plurality of vectors into the second vector register.

[0102] At operation 1210, the method 1200 may include performing the auto correlation operation on the vectorized baseband input signal in the first vector register and the second vector register.

[0103] The method 1200 may include obtaining the set of correlation values based on performing the auto correlation on the vectorized baseband input signal in the first vector register and the second vector register.

[0104] In an example embodiment, the method 1200 may include storing the set of correlation values diagonally into the memory 304. In a non-limiting example, the set of correlation values indicates a similarity between the vectorized baseband input signal in the first vector register and the vectorized baseband input signal in the second vector register, along the spatial dimension.

[0105] In an example embodiment, the method 1200 may include transposing the spatial dimension and the frequency dimension of the baseband input signal to create the transposed radio signal comprising one or more transposed resource elements.

[0106] In an example embodiment, the method 1200 may include loading, into the memory 304, the transposed radio signal and generating, in the memory 304, the first-sequence radio signal comprising the one or more first-sequence resource elements from the transposed radio signal.

[0107] In an example embodiment, the method 1200 may include performing the auto correlation operation of the one or more transposed resource elements with the one or more first-sequence resource elements.

[0108] The disclosure enhances performance of the auto correlation in the physical layer (PHY) baseband signal.

[0109] The disclosure enhances vector-level parallelism and reduces costly horizontal summations that lead to achieving high-performance baseband processing.

[0110] The language used in the disclosure has been principally selected for readability and instructional purposes, and it may not have been selected to delineate or circumscribe the disclosed subject matter. It is therefore intended that the scope of the disclosure not be limited by this detailed description. Accordingly, the disclosure of the various example embodiments of the disclosure is intended to be illustrative, not limiting, of the scope of the disclosure, including the appended claims and their equivalents.

[0111] While various aspects and embodiments have been disclosed herein, other aspects and embodiments will be apparent to those skilled in the art. The various aspects and embodiments disclosed herein are for purposes of illustration and are not intended to be limiting. It will also be understood that any of the embodiment(s) described herein may be used in conjunction with any other embodiment(s) described herein.

Claims

1.A method (1200) for performing an auto correlation operation during processing of a baseband input signal, the method comprising:receiving (1202) the baseband input signal comprising one or more resource elements, wherein the baseband input signal is a multi-dimensional signal comprising at least one of a time dimension, a frequency dimension, and a spatial dimension;performing (1204) a vectorization of the baseband input signal based on restructuring of the one or more resource elements into a plurality of vectors along the spatial dimension;inserting (1206) the vectorized baseband input signal into a first vector register among a set of vector registers, based on arrangement of the plurality of vectors in an adjacent manner;replicating (1208) a first version of the vectorized baseband input signal from the first vector register into a second vector register within the set of vector registers; andperforming (1210) an auto correlation operation on the vectorized baseband input signal in the first vector register and the second vector register.2.The method of claim 1, further comprising:obtaining a set of correlation values based on performing the auto correlation on the vectorized baseband input signal in the first vector register and the second vector register,wherein the set of correlation values indicate a similarity between the vectorized baseband input signal in the first vector register and the vectorized baseband input signal in the second vector register, along the spatial dimension.3.The method of claim 1, wherein the one or more resource elements distributed across the time dimension is indicated as a plurality of an orthogonal frequency division multiplexing (OFDM) symbols, across the frequency dimension is indicated as a plurality of subcarriers, and across the spatial dimension is indicated as at least one antenna.4.The method of claim 1, further comprising:transposing the spatial dimension and the frequency dimension of the baseband input signal to create a transposed radio signal comprising one or more transposed resource elements;loading the transposed radio signal;generating a first-sequence radio signal comprising one or more first-sequence resource elements from the transposed radio signal; andperforming the auto correlation operation of the one or more transposed resource elements with the one or more first-sequence resource elements.5.The method of claim 1, wherein the one or more resource elements are arranged in a non-stride pattern into the plurality of vectors.6.The method of claim 1, wherein replicating the first version of the vectorized baseband input signal in the second vector register comprising:shifting the plurality of vectors of the first vector to left by one element; andobtaining the first version of the vectorized baseband input signal in the second vector register based on replicating the shifted plurality of vectors into the second vector register.7.The method of claim 1, wherein the first version of the vectorized baseband input signal is a slided version.8.The method of claim 1, further comprising:storing the set of correlation values diagonally.9.A system (208) for performing an auto correlation operation during processing of a baseband input signal, the system (208) comprising:memory (304) storing instructions; andone or more processors (302) communicatively coupled to the memory (304),wherein the instructions, when executed by the one or more processors (302) individually or collectively, cause the system to:receive the baseband input signal comprising one or more resource elements, wherein the baseband input signal is a multi-dimensional signal comprising at least one of a time dimension, a frequency dimension, and a spatial dimension;perform a vectorization of the baseband input signal based on restructuring of the one or more resource elements into a plurality of vectors along the spatial dimension, wherein the vectorization of the baseband input signal is performed within the memory of the one or more processors;insert the vectorized baseband input signal from the memory into a first vector register among a set of vector registers in the one or more processors, based on arrangement of the plurality of vectors in an adjacent manner;replicate a first version of the vectorized baseband input signal from the first vector register into a second vector register within the set of vector registers; andperform an auto correlation operation on the vectorized baseband input signal in the first vector register and the second vector register.10.The system of claim 9, wherein the instructions, when executed by the one or more processors (302) individually or collectively, cause the system to:obtain a set of correlation values based on performing the auto correlation on the vectorized baseband input signal in the first vector register and the second vector register,wherein the set of correlation values indicate a similarity between the vectorized baseband input signal in the first vector register and the vectorized baseband input signal in the second vector register, along the spatial dimension.11.The system of claim 9, wherein the one or more resource elements distributed across the time dimension is indicated as a plurality of an orthogonal frequency division multiplexing (OFDM) symbols, across the frequency dimension is indicated as a plurality of subcarriers, and across the spatial dimension is indicated as at least one antenna.12.The system of claim 9, wherein the instructions, when executed by the one or more processors (302) individually or collectively, cause the system to:transpose the spatial dimension and the frequency dimension of the baseband input signal to create a transposed radio signal comprising one or more transposed resource elements;load, into the memory (302), the transposed radio signal;generate, in the memory (302), a first-sequence radio signal comprising one or more first-sequence resource elements from the transposed radio signal; andperform the auto correlation operation of the one or more transposed resource elements with the one or more first-sequence resource elements.13.The system of claim 9, wherein the one or more resource elements are arranged in a non-stride pattern into the plurality of vectors.14.The system of claim 9, wherein to replicate the first version of the vectorized baseband input signal in the second vector register, the instructions, when executed by the one or more processors (302) individually or collectively, cause the system to:shift the plurality of vectors of the first vector to left by one element; andobtain the first version of the vectorized baseband input signal in the second vector register based on replicating the shifted plurality of vectors into the second vector register,wherein the first version of the vectorized baseband input signal is a slided version,wherein the one or more processors (302) are configured tostore the set of correlation values diagonally into the memory (304).15.One or more non-transitory computer-readable storage media storing computer-executable instructions that, when executed by at least one processor of a system, cause the system to perform operations, the operations comprising:receiving the baseband input signal comprising one or more resource elements, wherein the baseband input signal is a multi-dimensional signal comprising at least one of a time dimension, a frequency dimension, and a spatial dimension;performing a vectorization of the baseband input signal based on restructuring of the one or more resource elements into a plurality of vectors along the spatial dimension;inserting the vectorized baseband input signal into a first vector register among a set of vector registers, based on arrangement of the plurality of vectors in an adjacent manner;replicating a first version of the vectorized baseband input signal from the first vector register into a second vector register within the set of vector registers; andperforming an auto correlation operation on the vectorized baseband input signal in the first vector register and the second vector register.

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