Machine learning-based evaluation of bump configurations for circuit designs

Abstract

Systems and methods are presented for machine learning (ML)-based evaluation of bump configurations. A method may include steps of accessing an input circuit design and evaluating a bump configuration of the input circuit design that specifies a link between a source bump and sink bumps in the input circuit design. Evaluating the bump configuration can include generating an evaluation matrix based on locations of the source bump and the sink bumps in the input circuit design, constructing an evaluation image from the evaluation matrix based on matrix values in the evaluation matrix, and generating an evaluation value for the evaluation image using an evaluation ML model trained to generate evaluation values for bump configurations in circuit designs. The method may also include adjusting the bump configuration between the source bump and the sink bumps in the input circuit design based on the evaluation value.

Description

MACHINE LEARNING-BASED EVALUATION OF BUMP CONFIGURATIONS FOR CIRCUIT DESIGNSBACKGROUND

[0001] Electronic circuits, such as integrated circuits, are used in nearly every facet of modern society, from automobiles to mobile devices to personal computers. Design of circuits may involve many steps, known as a "design flow." The particular steps of a design flow are often dependent upon the type of circuit being designed, its complexity, the design team, and the circuit fabricator or foundry that will manufacture the circuit. Electronic design automation (EDA) applications support the design and verification of circuits prior to fabrication. EDA applications may implement various EDA procedures, e.g., functions, tools, or features to analyze, test, or verify a circuit design at various stages of the design flow.BRIEF DESCRIPTION OF THE DRAWINGS

[0002] Certain examples are described in the following detailed description and in reference to the drawings.

[0003] Figure 1 shows an example of a computing system that supports machine learning (ML)-based evaluation of bump configurations for circuit designs.

[0004] Figure 2 shows an example of bumps of a circuit design, including source bumps and sink bumps arranged in an overlay top-down view.

[0005] Figure 3 shows an example generation of an evaluation value through an evaluation ML model for a bump configuration of a circuit design.

[0006] Figure 4 shows another example generation of an evaluation value through an evaluation ML model for a bump configuration of a circuit design.

[0007] Figure 5 shows an example training of an evaluation ML model through training evaluation images constructed from training bump configurations.

[0008] Figure 6 shows an example of logic that a system may implement to support ML-based evaluation of bump configurations for circuit designs.

[0009] Figure 7 shows an example of a computing system that supports ML-based evaluation of bump configurations for circuit designs.DETAILED DESCRIPTION

[0010] Electronic circuits, such as integrated circuits (ICs), are used in nearly every facet of modem society, from automobiles to microwaves to personal computers. The design, verification, and physical manufacture of circuit devices often involve several steps, sometimes referred to as a "design flow." The particular steps of a design flow are dependent upon various factors, such as the type of integrated circuit being designed, its complexity, the design team, and the integrated circuit fabricator (e.g., foundry) that will manufacture the physical circuit. Typically, software and hardware tools can verify the circuit designs at various stages of the design flow, for example through complex rule checks, software-based simulations, hardware-based emulation, and various other techniques supported by modern EDA technology. These steps of a design flow aid in the discovery of errors in circuit designs, and allow design teams and engineers to correct or otherwise improve the designs prior to, during, or after physical manufacture.

[0011] Several steps are common to most design flows of IC design. Initially, the specification for a new circuit can be transformed into or otherwise generated as a logical design. Logical designs are sometimes referred to as a register transfer level (RTL) description of a circuit. With logical designs, a circuit can be described in terms of both the exchange of signals between hardware registers and the logical operations that are performed on those signals. The logical design typically employs a Hardware Design Language (HDL), such as the Very high-speed integrated circuit Hardware Design Language (VHDL). The logic of the circuit is then analyzed to confirm that the design will accurately perform the functions desired for the circuit. This analysis is sometimes referred to as "functional verification."

[0012] After the accuracy of the logical design is confirmed through functional verification, a logical design can be converted into a device design by synthesis software. The device design, which is typically in the form of a schematic or netlist, can describe the specific electronic devices (e.g., transistors, resistors, andcapacitors) that form the circuit design, along with the interconnections between these electronic devices. This device design generally corresponds to the level of representation displayed in conventional circuit diagrams. The relationships between the electronic devices are then analyzed to confirm that the circuit described by the device design will correctly perform the desired functions. This analysis is sometimes referred to as "formal verification." Additionally, preliminary timing estimates for portions of the circuit are often made at this stage, using an assumed characteristic speed for each device, and incorporated into the verification process.

[0013] Once the electronic devices components and their interconnections are established, the design can again be transformed in a design flow. In particular, the next transformation may be to a physical design that describes specific geometric elements that form the circuit design. This type of physical version of a circuit design is often referred to as a "layout" design or “physical layout” (and may simply be referred to as a “layout”). The geometric elements, which typically are polygons, define the shapes that will be created in various layers of material to physically manufacture the circuit. Automated place and route tools can be used to define or generate the physical layouts, especially for wires that will be used to interconnect the circuit devices in the physical representation of the circuit design. Each layer of a circuit can have a corresponding layer representation in the layout design, and the geometric shapes described in a layer representation will define the relative locations of the circuit elements that will make up the circuit device (e.g., of transistors, resistors, capacitors, etc.). For example, shapes in the layer representation of a metal layer will define the locations of the metal wires used to connect the circuit devices.

[0014] Integrated circuit layout descriptions can be provided in many different formats. The Graphic Data System II (GDSII) format is a popular format for transferring and archiving two-dimensional graphical IC layout data. Among other features, GDSII contains a hierarchy of structures, each structure containing layout elements (e.g., polygons, paths or poly-lines, circles and textboxes). Other layout formats include an open-source format named Open Access, Milkyway by Synopsys, Inc., EDDM by Siemens EDA (formerly Mentor Graphics Corporation), and the Open Artwork System Interchange Standard (OASIS) format proposed by Semiconductor Equipment and Materials International (SEMI). These various industry formats are used to define the geometrical information in IC layout designs that are employed tomanufacture integrated circuits. Once the circuit design is finalized, the layout portion of the design can be used by fabrication tools to manufacture the device using a photolithographic process.

[0015] Typically, a designer will perform a number of verification processes on the layout design. For example, the layout design may be analyzed to confirm that it accurately represents the circuit devices and their relationships described in the device design. In this process, a layout-versus-schematic (LVS) tool can extract a netlist from the layout design and compare it with the netlist taken from the circuit schematic. LVS can be augmented by formal equivalence checking, which checks whether two circuits perform exactly the same function without demanding isomorphism.

[0016] The layout design also may be analyzed to confirm that it complies with various design requirements, such as minimum spacings between geometric elements and minimum linewidths of geometric elements. Such checks may be part of a design rule checking (DRC) process performed on layout design. DRC tools can take, as an input, a physical layout (e.g., in the GDSII or OASIS standard format) as well as a rule deck which specifies the specific rule checks to perform on the layout design. As checks in a DRC process can be specific to a particular circuit fabrication process, rule decks are typically provided by a foundry or circuit manufacturer specifying the particular rules that circuit designs must adhere to for circuit fabrication via the foundry (e.g., at a specified technology node or specific fabrication process parameters). Put another way, foundry-provided rule decks can include a list of rules specific to the semiconductor fabrication process employed by the foundry or otherwise selected for use in circuit manufacture. As such, a set of rules for a particular fabrication process can be referred to as a run-set, rule deck, or just a deck. An example format used for implementation of rule decks is the Standard Verification Rule Format (SVRF) by Siemens EDA (formerly Mentor Graphics Corporation).

[0017] There are many different fabrication processes for manufacturing a circuit, but most processes include a series of steps that deposit layers of different materials on a substrate, expose specific portions of each layer to radiation, and then etch the exposed (or non-exposed) portions of the layer away. For example, a simple semiconductor device component could be manufactured by the following steps. First, a positive-type epitaxial layer is grown on a silicon substrate through chemical vapor deposition. Next, a nitride layer is deposited over the epitaxial layer. Then specificareas of the nitride layer are exposed to radiation, and the exposed areas are etched away, leaving behind exposed areas on the epitaxial layer, (i.e., areas no longer covered by the nitride layer). The exposed areas then are subjected to a diffusion or ion implantation process, causing dopants, for example phosphorus, to enter the exposed epitaxial layer and form charged wells. This process of depositing layers of material on the substrate or subsequent material layers, and then exposing specific patterns to radiation, etching, and dopants or other diffusion materials, is repeated a number of times, allowing the different physical layers of the circuit to be manufactured.

[0018] Each time that a layer of material is exposed to radiation, a photomask (mask) must be created to expose only the desired areas to the radiation, and to protect the other areas from exposure. The mask is created from circuit layout data. That is, the geometric elements described in a physical layout define the relative locations or areas of the circuit wafer that will be exposed to radiation through the mask. A mask or reticle writing tool is used to create the mask based upon the design layout, after which the mask can be used in a photolithographic process for fabrication of physical circuits. One or more resolution enhancement techniques (RETs) are often employed to improve the resolution of the image that the mask forms on the substrate during the photolithographic process. One of these techniques is optical proximity correction (OPC). OPC can be rule-based, model-based, or both. In rule-based OPC, the proximity effects are characterized, and specific solutions are devised for specific geometric configurations. The layout design is then searched using a DRC tool or a geometric-based software engine to find these geometric configurations. Once they are found, the specific solutions are applied. Through various steps of a design flow, the design, manufacture, and fabrication of circuits can be performed and supported through EDA technology.

[0019] While various steps of a design flow are described herein, circuit manufacture processes continue to evolve and may include any additional or alternative flow steps. Moreover, the intricacy of each step in a design flow can be immense, especially as circuit designs continue to increase in complexity and the transistors and other devices that form a circuit are merely a few atoms wide. As such, accurate and effective design flow steps may increase the efficiency of circuit design and improvements at any given step in the design flow can yield significant benefits.

[0020] With advances in EDA technology, increasing chip complexities and new chip structures can significantly increase the computational requirements for circuit analyses and simulations. As one example, 3-dimensional integrated circuit (3DIC) structures can be achieved by stacking multiple chips on top of one another. 3DICs can be constructed by vertically stacking multiple chips or wafers together into a single package, and electrical interconnections and signal exchanges between the different chips within the 3DIC can be achieved in various ways, including through bump and bonding technologies. A bump (also referred to as a micro-bump or hybrid bump) may refer to any connection structure or element used to support the connection of two different circuits, e.g., as part of a 3DIC package. The physical form of a bump may be as copper microbumps or as copper pads for hybrid bonding connection techniques, and bumps may be used to interconnect stacked circuits in 3DIC structures.

[0021] As an illustrative structure, a 3DIC package may include an interposer upon which multiple systems on a chip (SoCs) may be vertically stacked onto the interposer, other SoCs, or other interposers. The stacked SoCs and interposer circuits may be connected through bumps that are constructed on surfaces of the interposer and the SoCs that contact one another. Such bumps may align together when the circuits are vertically stacked, allowing for electrical interconnections between the stacked circuits. Hybrid bonding or other circuit attachment processes may be employed to physically attach the circuits. Note that, as used herein, a bump may refer to any individual connection element (e.g., electrical interconnection point) of a circuit, and need not be a physical bump that extrudes from a wafer or circuit. For example, copper pillars or copper pads in hybrid bonding-based circuit interconnection structures may have smooth circuit surfaces, but each of the copper interconnections of such circuit structures may be referred as a bump since each is used to interconnect circuits in a 3DIC package. With increasing design complexities, the number of bumps used in circuits of 3DIC packages is rapidly increasing. A single SoC in a 3DIC package may include thousands, millions, to tens of millions of bumps, with bump numbers continually increasing as modem circuit technologies evolve.

[0022] The spike in bump counts for circuits designed for 3DIC packages can result in significant complexity increases in circuit designs. For example, circuits designed for 3DIC packages may comprise bumps on multiple different surfaces, e.g., a bottomand top surface of the circuit that interface with other circuits of the 3DIC package. Bumps located on each of opposite surfaces of the same circuit may need to be interconnected with one another, traversing through the various layers of the circuit. As one example, example power or ground signals may propagate layer-by-layer through an entire circuit design, and then such signals can further propagate to other circuits of a 3DIC package through interconnected bumps. Bumps on different surfaces of the same circuit design may be linked through bump configurations, which may refer to a link between one or more bumps on a first surface of a circuit design to one or more bumps on a second surface of the circuit design. One such use case for bump configurations is the splitting of power or ground nets from a single source bump (e.g., located on a bottom surface of an interposer circuit design as a single pin to a power source) to multiple sink bumps (e.g., located on a top surface of the circuit design, through which a power signal can be propagated to other circuits of the 3DIC package). Any suitable bump configuration is possible in modern circuit designs.

[0023] Bump configurations can impact circuit behavior, performance, and efficiency. With thousands or millions of bumps on a single surface of a circuit design possibly linked to thousands or millions of other bumps on a different surface of a circuit design can lead to a near unfathomable number of possible bump configurations for even simple circuits of 3DIC packages. Bump configurations that link source bumps with sink bumps that are lengthy distances from one another can result in increased voltage drops, higher resistance between metal traces, and heat issues. Thus, the quality of bump configurations can be an important metric by which to verify or ensure proper circuit performance.

[0024] Conventional assessment techniques of bump configurations are difficult and costly. Graph theory techniques can be employed to build a bump connectivity graph, such as using a Voronoi diagram. In such conventional graph-based techniques, edges and nodes of the Voronoi diagram can be collected and analyzed to determine cost metrics. Through such cost metrics, comparison of different bump configurations can be quantified. However, to employ such graph theory techniques, entire surfaces of circuit designs may need to be processed and analyzed. With modem bump counts continually increasing to number in the millions and more, the complexity of such analyses and computational latency to perform such graph-based assessments is becoming prohibitive in cost.

[0025] The disclosure herein may provide systems, methods, devices, and logic for ML-based evaluations of bump configurations for circuit designs. The various technical features described herein may be referred to as bump configuration evaluation technology. As described herein, the bump configuration evaluation technology of the present disclosure may utilize ML-based evaluation techniques for bump configurations. Bump configurations may be converted into an image representation, including through generation of evaluation matrices that can represent relative locations of source bumps, sink bumps, and other bumps proximate to bumps of a bump configuration. Such evaluation images may be analyzed by an evaluation ML model, which may take the form of a convolutional neural network. Image classification by the evaluation ML model can be used to generate an evaluation value for the bump configuration, allowing for efficient and accurate assessment of bump configurations of a circuit design. Compared to conventional graph theory assessments, the bump configuration evaluation technology of the present disclosure may provide improved speed, efficiency, and accuracy for bump assessments, which may reduce the design turnaround times. Reduced latency and costs may thereby improve EDA systems and EDA design flows, reducing design latency, and increasing performance scalability and efficiency.

[0026] These and other technical features and technical benefits of the bump configuration evaluation technology are presented herein.

[0027] Figure 1 shows an example of a computing system that supports ML-based evaluation of bump configurations for circuit designs. The computing system 100 may take the form of a single or multiple computing devices such as application servers, compute nodes, desktop or laptop computers, smart phones or other mobile devices, tablet devices, embedded controllers, and more. In some implementations, the computing system 100 hosts, instantiates, executes, supports, or implements an EDA application or EDA system that supports circuit design and analysis, and may accordingly provide or implement any of the bump configuration evaluation technology described herein.

[0028] As an example implementation to support any combination of the bump configuration evaluation technology described herein, the computing system 100 shown in Figure 1 includes a bump configuration engine 110. The computing system 100 may implement the bump configuration engine 110 (including componentsthereof) in various ways, for example as hardware and programming. The programming for the bump configuration engine 110 may take the form of processorexecutable instructions stored on a non-transitory machine-readable storage medium and the hardware for the bump configuration engine 110 may include a processor to execute those instructions. A processor may take the form of single processor or multi-processor systems, and in some examples, the computing system 100 implements multiple engines using the same computing system features or hardware components (e.g., a common processor or a common storage medium).

[0029] In operation, the bump configuration engine 110 may access an input circuit design and evaluate a bump configuration of the input circuit design that specifies a link between a source bump and sink bumps in the input circuit design. The source bump may represent a connection element between circuits of a 3DIC structure on a first surface of the input circuit design and the sink bumps may represent connection elements between circuits of the 3DIC structure on a second surface of the input surface design. The bump configuration engine 110 may evaluate the bump configuration by generating an evaluation matrix based on locations of the source bump and the sink bumps in the input circuit design, constructing an evaluation image from the evaluation matrix based on matrix values in the evaluation matrix, and generating an evaluation value for the evaluation image using an evaluation ML model trained to generate evaluation values for bump configurations in circuit designs. In operation, the bump configuration engine 110 may also adjust the bump configuration between the source bump and the sink bumps in the input circuit design based on the evaluation value.

[0030] These and other technical features and technical benefits of the bump configuration evaluation technology are described in greater detail next.

[0031] Figure 2 shows an example of bumps of a circuit design, including source bumps and sink bumps arranged in an overlay top-down view. In the example of Figure 2, an input circuit design 210 is shown. The input circuit design 210 may be any digital representation of a circuit, including in any suitable circuit design format. The input circuit design 210 may represent a circuit (e.g., wafer) for a 3DIC structure, and a 3DIC structure may be any suitable 3DIC package or design in which multiple circuits (e.g., wafers) are stacked together. In some examples, the bump configuration engine 110 may access input circuit designs in the form of physical layouts of individualcircuits of a 3DIC structure, for example input physical layouts provided as part of parasitic extraction or circuit verification steps in an EDA design flow. Thus, the input circuit design 210 may be for a SoC, interposer, or other circuit of a 3DIC structure. As the input circuit design 210 may be designed for inclusion in a 3DIC structure, the input circuit design 210 may include bumps to support interconnecting the circuit represented by the input circuit design 210 with other circuits or elements of the 3DIC structure.

[0032] The bump configuration engine 110 may access the input circuit design 210 in any number of ways. For instance, the bump configuration engine 110 may load the input circuit design 210 from a memory, receive the input circuit design 210 over a network connection, or identify the input circuit design 210 via user input. Any suitable mechanism by which the bump configuration engine 110 can read or load circuit data may be utilized to access the input circuit design 210. As the input circuit design 210 may be stacked between multiple different elements of a 3DIC structure, the input circuit design 210 may include bumps on multiple different surfaces. In the example of Figure 2, different bumps are shown for a bottom surface 212 and a top surface 214 of the input circuit design 210. The bottom surface 212 of the input circuit design 210 may contact or interconnect with a 3DIC element positioned underneath the input circuit design 210. The top surface 214 of the input circuit design 210 may contact or interconnect with another 3DIC element positioned on top of the input circuit design 210. Bumps of the input circuit design 210 located on the bottom surface 212 and top surface 214 may provide interconnection points to such 3DIC elements of a 3DIC package (e.g., other circuits, interposers, motherboard, etc.).

[0033] Bump configurations may be specified in the input circuit design 210 to link the bumps of the bottom surface 212 to bumps of the top surface 214. In particular, links between bumps may indicate that an electrical path (e.g., a net) traverses from the bottom surface 212 to the top surface 214 of the input circuit design 210 (or vice versa) through the bumps of a given bump configuration, thus allowing signal propagation across the input circuit design 210 and between other elements of a 3DIC structure. Such links may be in the form of electrical connections traversing through the various layers of the input circuit design 210, e.g., in the form of vias or other interconnects. In the example of Figure 2, bumps of the bottom surface 212 are shown as source bumps 220 and bumps of the top surface are shown as sink bumps 230. Asource bump may refer to any bump located on a given surface and a sink bump may refer to any bump located on a different surface that the source bump is located on.

[0034] As a continuing example used herein, bump configurations may be formed or specified to split power or ground nets, such as VDD, VCC, VSS, GND, etc. As such examples, the source bumps 220 may be in the form of power pins or ground pins, e.g., that connect to a power source or ground plane, and bump configurations in the input circuit design 210 may link multiple sink bumps 230 to a single source bump 220 (thus splitting a power or ground source into multiple nets that can be propagated across the various circuits, interposers, and elements of 3DIC package). While such an example is a continuing illustration used herein, bump configurations may be specified between source bumps and sink bumps in any suitable manner and signal type, e.g., one-to-one, one-to-many, many-to-one, or many-to-many.

[0035] To help understand bump configurations and linking of source bumps and sink bumps in circuit designs, an overlay top-down view of bumps of the input circuit design 210 is shown in Figure 2. The overlay top-down view may depict bumps positioned on different surfaces of the input circuit design 210 together in a single top- down view. In some examples, the sink bumps 230 of the top surface 214 may be overlayed upon source bumps of the bottom surface 212 in a top-down view, or vice versa. The top-down view may align the top and bottom surfaces along an axis normal / perpendicular to 2-dimensional planes (2D) of the bottom surface 212 and top surface 214, e.g., along a z-axis of a 3D coordinate system used to represent the input circuit design 210. The overlay top-down view may indicate a relative proximity between various source bumps 220 of the bottom surface 212 and sink bumps 230 of the top surface 214, e.g., in a 2D plane formed by overlaying the bottom surface 212 and the top surface 214 together into a single plane.

[0036] The overlay top-down view of bumps of a circuit design may allow for visualization or representation of bumps of different surfaces in a common 2D plane. Thus, horizontal coordinates (e.g., x-coordinates) and vertical coordinates (e.g., y- coordinates) can be used to represent locations of bumps on different surfaces (e.g., with different z-coordinates). The coordinates of a given bump may be represented or specified as a center location of the given bump (or any other location within or otherwise attributed to the given bump). Sink bumps closer to a given source bump in the overlay top-down view (e.g., as a 2D distance) may be closer in distance thanother sink bumps further in distance in in the overlay top-down view (noting that actual distance between source and sink bumps would require traversing across the layers of the input circuit design 210 between the bottom surface 212 and top surface 214). Another way of understanding or representing an overlay top-down view of bumps is to consider only the x-coordinates and y-coordinates of the bump locations in the input circuit design 210, and disregarding the z-coordinates that can specify a surface or layer that the bumps are located on.

[0037] In some examples, the input circuit design 210 may itself specify bump configurations between bumps of different surfaces. For example, circuit designers may design splitting of power or ground signals in the input circuit design 210 by electrically connecting multiple sink bumps of the top surface 214 to a given source bump of the bottom surface 212, for example through vias generated through routing tools or other EDA processes. The link between the given source bump of a first surface and multiple sink bumps of a second surface of the input circuit design 210 may be a bump configuration in the input circuit design 210. As 3DIC circuits may include thousands or millions of bumps between the contact surfaces to other 3DIC elements, the input circuit design 210 may include a significantly large number of bump configurations. The bump configuration evaluation technology of the present disclosure may provide effective assessment techniques to efficiently evaluate bump configurations, including through ML-based technologies. Evaluations of bump configurations may be generated in the form of evaluation values, including in any of the ways described herein. Example evaluations provided by the bump configuration evaluation technology are described next.

[0038] Figure 3 shows an example generation of an evaluation value through an evaluation ML model for a bump configuration of a circuit design. In Figure 3, an overlay top-down view of various bumps of the input circuit design 210 is shown which includes various source bumps and sink bumps. In particular, Figure 3 depicts a bump configuration 310 that links a source bump 312 with multiple sink bumps 314. The bump configuration 310 shown in Figure 3 links the source bump 312 (filled in black) with eight (8) sink bumps 314 (each filled in black). Other surrounding source bumps and sink bumps that are not part of the bump configuration 310 are shown in Figure 3 as well, visualized without a black fill.

[0039] The bump configuration engine 110 may evaluate any number of bump configurations of the input circuit design 210, including the bump configuration 310 shown in Figure 3. Evaluation of the bump configuration 310 may include generating an evaluation matrix for the bump configuration 310, constructing an evaluation image from the evaluation matrix for the bump configuration 310, and generating an evaluation value for the bump configuration 310 through an evaluation ML model that can receive, as an input, the evaluation image for the bump configuration 310. Each of these steps and features are described in greater detail herein.

[0040] To support evaluation of the bump configuration 310, the bump configuration engine 110 may generate a representation of the bump configuration 310 in a matrix form. An evaluation matrix generated by the bump configuration engine 110 for a given bump configuration may map or represent relative locations of the linked bumps in the given bump configuration (or other proximate bumps), including with assigned matrix values for the various bumps mapped into the evaluation matrix. Mapping of relative locations may be achieved through matrix rows and columns. As an example, the columns of an evaluation matrix may represent different horizontal coordinates among the bumps of the given bump configuration and rows of the evaluation matrix may represent different vertical coordinates among the bumps of the given bump configuration.

[0041] To illustrate through Figure 3, the bump configuration engine 110 may generate the evaluation matrix 320 for the bump configuration 310. In doing so, the bump configuration engine 110 may determine the dimensions of the evaluation matrix 320 as an ‘M’ x ’N’ matrix, with ‘M’ number of rows and ‘N’ number of columns. The bump configuration engine 110 may determine the value of ‘M’ for the row dimension of the evaluation matrix 320 based on (e.g., as equal to) a number of unique y- coordinate values among the source bump 312 and the sink bumps 314. A 2D plot of the bumps of the bump configuration 310 along a horizontal x-axis and a vertical y- axis is shown in Figure 3 to help illustrate evaluation matrix generations by the bump configuration engine 110. In the example of Figure 3, the bump configuration engine 110 may determine that the source bump 312 and sink bumps 314 of the bump configuration 310 include five (5) unique vertical coordinate values. This can be seen in the 2D plot of Figure 3, in which the source bump 312 and the sink bumps 314 are plotted across five (5) different values on the y-axis, shown as Yi , Y2, Y3, Y4, and Y5.Note that the number of unique y-coordinate values among the source bump 312 and the sink bumps 314 may be less than total number of bumps in the bump configuration 310, as some of the sink bumps or the source bump may have the same y-coordinate value. As seen in Figure 3, two (2) of the sink bumps 314 have the same y-coordinate value of Y3, four (4) of the sink bumps 314 have the same y-coordinate value of Y4, and two (2) of the sink bumps 314 have the same y-coordinate value of Y5. In this example, the bump configuration engine 110 may determine the row dimension of the evaluation matrix 320 as equal to the number of unique y-coordinate values among the source bump 312 and the sink bumps 314 of the bump configuration 310, in this example with a determination of ‘M’ = 5.

[0042] Turning to the column dimension of the evaluation matrix 320, the bump configuration engine 110 may determine the value of ‘N’ for the column dimension based on (e.g., as equal to) a number of unique x-coordinate values among the source bump 312 and the sink bumps 314. In the example of Figure 3, the bump configuration engine 110 may determine that the source bump 312 and the sink bumps 314 of the bump configuration 310 include five (5) unique horizontal coordinate values. This can be seen in the 2D plot of Figure 3, in which the source bump 312 and the sink bumps 314 are plotted across five (5) different values on the x-axis, shown as Xi , X2, X3, X4, and X5. Thus, the number of unique x-coordinate values among the source bump 312 and sink bumps 314 may be less than total number of bumps in the bump configuration 310, as some of the sink bumps or the source bump may have the same x-coordinate value. As seen in Figure 3, three (3) of the sink bumps 314 have the same x- coordinate value of X2, three (3) of the sink bumps 314 have the same x-coordinate value of X3, and two (2) of the sink bumps 314 have the same x-coordinate value of X4. In this example, the bump configuration engine 110 may determine the column dimension of the evaluation matrix 320 as equal to the number of unique x-coordinate values among the source bump 312 and sink bumps 314 of the bump configuration 310, in this example ‘N’ = 5.

[0043] Thus, in the example of Figure 3, the bump configuration engine 110 may determine the dimensions of the evaluation matrix 320 to be a 5 x 5 matrix. In that regard, the bump configuration engine 110 may determine a number of rows in an evaluation matrix based on a number of unique vertical coordinate values (e.g., unique y-coordinate values) among a source bump (e.g., on a first surface) and sink bumps(e.g., on a second surface). Likewise, the bump configuration engine 110 may determine a number of columns in an evaluation matrix based on a number of unique horizontal coordinate values (e.g., x-coordinate values) among the source bump on the first surface and the sink bumps on the second surface. Each element of the evaluation matrix 320 may represent a different location, and each column may correspond to a respective horizontal coordinate value among the unique horizontal coordinate values and each row may correspond to a respective vertical coordinate value among the unique vertical coordinate values. To further illustrate, element^ may specify the matrix element at row ‘i’ and column ‘j’ of the evaluation matrix 320, which may correspond to location (Xj, Y) of the unique x and y-coordinate values among the bumps of the bump configuration 310.

[0044] Note that the bump configuration engine 110 need not visually plot the bumps of the bump configuration 310 to determine matrix dimensions for the bump configuration 310. In some implementations, the bump configuration engine 110 may determine the location (e.g., x-y coordinates) of each of the bumps in the bump configuration 310. Then, the bump configuration engine 110 may process the y- coordinate values of the bumps to determine the row dimension size ‘M’ for the evaluation matrix 320 and process the x-coordinate values of the bumps to determine the column dimension ‘N’ size for the evaluation matrix 320. Such processing may include sorting the y-coordinate values in an ascending (or descending) order, removing any duplicate values among the sorted y-coordinate values, or both. Similar processing may be performed for the x-coordinate values among the bumps of the bump configuration 310. In some implementations, removal of duplicate values may comprise identifying x or y-coordinate values as duplicates if such values are within a threshold range from one another (e.g., coordinate value difference is less than 0.05, 0.001 , 0.0005, or any other configurable difference threshold). As such, the bump configuration engine 110 may identify unique coordinate values among the bumps of a bump configuration 310 and determine dimensions of the evaluation matrix 320 accordingly.

[0045] In generating the evaluation matrix 320, the bump configuration engine 110 may populate the evaluation matrix 320 for the bump configuration 310 with matrix values. The bump configuration may populate matrix values for each element of the evaluation matrix 320 based on the locations of the source bump 312 and the sinkbumps 314, including a first value for the source bump 312, a second value for the sink bumps 314, and a third value for locations without the source bump 312 and the sink bumps 314, wherein the first value, the second value, and the third value are different from one another. In the example of Figure 3, the bump configuration engine 110 uses a first value of “0.8” for the source bump 312, a second value of “0.2” for the sink bumps 314, and a third value of “0”. As each of the rows and columns may represent a different unique x and y-coordinate value among the bumps of the bump configuration 310, the bump configuration engine 110 may populate each of the elements of the evaluation matrix 320 based on what is located at the location represented by each element.

[0046] To illustrate, elemental) of the evaluation matrix 320 may represent a location with coordinates (Xi,Yi). None of the bumps of the bump configuration 310 are located at (Xi,Yi), and the bump configuration engine 110 may thus populate elemental) of the evaluation matrix 320 with the third value (e.g., 0). As another illustration, element^) of the evaluation matrix 320 may represent a location with coordinates (X2,YI). None of the bumps of the bump configuration 310 are located at (X2,YI), and the bump configuration engine 110 may thus populate element^) of the evaluation matrix 320 with the third value (e.g., 0). To further illustrate, element^) of the evaluation matrix 320 may represent a location with coordinates (Xs,Yi). The bump configuration engine 110 may determine that the source bump 312 of the bump configuration 310 is located at (Xs,Yi). Accordingly, the bump configuration engine 110 may populate element^) of the evaluation matrix 320 with the first value (e.g., 0.8). For the sink bumps 314, as an illustrative example, element^) of the evaluation matrix 320 may represent a location with coordinates (X2,YS). The bump configuration engine 110 may determine that one of the sink bumps 314 of the bump configuration 310 is located at (X2,YS). Accordingly, the bump configuration engine 110 may populate element^) of the evaluation matrix 320 with the second value (e.g., 0.2). In a consistent manner, the bump configuration engine 110 may populate matrix values for each of the elements of the evaluation matrix 320, and the populated matrix values of the evaluation matrix 320 for the bump configuration 310 are shown in Figure 3.

[0047] The bump configuration engine 110 may construct an evaluation image from the evaluation matrix 320 generated for the bump configuration 310. In constructing an evaluation image, the bump configuration engine 110 may encode data stored orrepresented through the evaluation matrix 320 into an image format. Thus, construction of evaluation images may encompass or comprise any sort of conversion, encoding, or transformation of matrix data of the evaluation matrix 320 into image data of an evaluation image. Images may be particularly suitable for adapting machinelearning technologies, such as convolutional neural networks, for bump configuration evaluations. In some examples, the bump configuration engine 110 may construct the evaluation image 330 from the evaluation matrix 320 based on the matrix values in the evaluation matrix 320 by converting each element of the evaluation matrix 320 into a block of pixels (also referred to herein as a pixel block) in the evaluation image 330 colored with a pixel color based on the matrix value populated for each element. In the example of Figure 3, the bump configuration engine 110 constructs the evaluation image 330, which may be in the form of a grayscale image with a respective pixel block representative of each element of the evaluation matrix 320, and each pixel block colored with a grayscale color specified by the matrix value of each element of the evaluation matrix 320. Thus, the upper-right pixel block of the evaluation image 330 in Figure 3 may represent element^) of the evaluation matrix 320. The bump configuration engine 110 may color this upper-right pixel block with a grayscale tone color = 0.8, as specified by the matrix value of element^) of the evaluation matrix 320, which may represent the source bump 312 of the bump configuration.

[0048] In a similar manner, the bump configuration engine 110 may color other pixel blocks with a grayscale tone color = 0.2 for pixel blocks representing elements of the evaluation matrix for the sink bumps 314 of the bump configuration 310. Pixel blocks for elements without the source bump 312 or any of the sink bumps 314 may be colored white (e.g., grayscale tone color = 0) in the evaluation image 330. Grayscale coloring of pixel blocks is provided as but one illustrative example in Figure 3. Any suitable coloring of pixel blocks is contemplated for use in construction of evaluation images. As used herein, “coloring” of a pixel block by the bump configuration engine 110 may include any mechanism, technique, or process by which to differentiate pixel blocks of an evaluation image based on the matrix value populated for each element of the evaluation matrix 320. Example differentiations the bump configuration engine 110 may apply to “color” a pixel block with a different “pixel color” include different patterning applications, symbol insertions, or use of any other visual differentiator for pixel blocks in an evaluation image.

[0049] The bump configuration engine 110 may determine the size of pixel blocks in the evaluation image 330 in any suitable manner. In some examples, the bump configuration engine 110 may generate evaluation images for bump configurations in an input circuit design 210 with a fixed image size (e.g., 400 x 400 pixels, or any other configurable image size). As bump configurations may vary in positioning of source and sink bumps, the matrix dimensions of evaluation matrices generated for various bump configurations may differ, resulting in a varying number of pixel blocks among different evaluation images generated for different evaluation matrices. The bump configuration engine 110 may partition evaluation images of the fixed image size based on the number of columns and rows determined for corresponding evaluation matrices. As an illustrative example, a first evaluation image generated for a 12 x 6 evaluation matrix of a first bump configuration may have seventy-two (72) pixel blocks (one for each matrix element) and a second evaluation image generated for an 8 x 7 evaluation matrix of a second bump configuration may have fifty-six (56) pixel blocks. The bump configuration engine 110 may generate evaluation images for both bump configurations of the same image size, and thus the pixel blocks of the first evaluation image may differ in size from the pixel blocks of the second evaluation image. In other examples, the bump configuration engine 110 may generate evaluation images of differing sizes, e.g., with a fixed pixel block size for each element of evaluation matrices.

[0050] In any manner described herein, the bump configuration engine 110 may construct evaluation images from evaluation matrices, such as the evaluation image 330 shown in Figure 3. Through the evaluation image 330, the bump configuration engine 110 may generate an evaluation value for the bump configuration 310, particularly through use of an evaluation ML model trained to generate evaluation values for bump configurations in circuit designs. Figure 3 shows such an example through the evaluation ML model 340. The evaluation ML model 340 may be trained and configured to receive evaluation images as inputs and generate evaluation values as outputs for the provided evaluation images. In some implementations, the evaluation ML model 340 takes the form of a convolutional neural network trained to classify input evaluation images, which the convolutional neural network may output as evaluation values.

[0051] The evaluation ML model 340 may generate evaluation values of any type, format, or configuration. An evaluation value generated by the evaluation ML model 340 may refer to any indicator by which to specify an assessment of a bump configuration. Evaluation values generated by the evaluation ML model 340 may be expressed as classifications (e.g., “good”, “neutral”, “poor”, etc.), numerical values or ranges (on a 1 -10 scale), or in any other suitable or configurable manner. The specific type or format of evaluation values generated by the evaluation ML model 340 may be controlled or otherwise configured through training of the evaluation ML model 340, e.g., via labels in training data used to train the evaluation ML model 340. Other example aspects and features for training of the evaluation ML model 340 are described further below with reference to Figure 5.

[0052] In Figure 3, the bump configuration engine 110 inputs the evaluation image 330 to the evaluation ML model 340. The evaluation ML model 340 outputs the evaluation value 350, which can provide an assessment of the bump configuration 310 of the input circuit design 210. Thus, in the example of Figure 3, the bump configuration engine 110 may evaluate the bump configuration 310 of the input circuit design 210 through generation of an evaluation value 350 via the evaluation ML model 340. In Figure 3, the bump configuration engine 110 generates the evaluation matrix 320 with dimensions based on (e.g., equal to) the number of unique x and y-coordinate values among the source bump 312 and sink bumps 314 in the bump configuration 310. In some implementations, the bump configuration engine 110 may consider, account for, or otherwise map other circuit elements (e.g., other source bumps) in generation of an evaluation matrix for the bump configuration 310. By doing so, the bump configuration engine 110 may further evaluate bump configurations based on the location of other bumps (e.g., other source bumps) proximate to the bumps of a bump configuration. Example features of such consideration of other source bumps are described next with reference to Figure 4.

[0053] Figure 4 shows another example generation of an evaluation value through an evaluation ML model for a bump configuration of a circuit design. In the example of Figure 4, the bump configuration engine 110 may evaluate the bump configuration 310 as described in Figure 3. As explained above, the bump configuration 310 specified in an input circuit design 210 may link the source bump 312 with eight (8) sink bumps 314. In evaluating the bump configuration 310, the bump configurationengine 110 may further account for other source bumps proximate to the source bump 312 and sink bumps 314 of the bump configuration 310. As an example of doing so, the bump configuration engine 110 may generate an evaluation matrix that further accounts for (e.g., maps locations of) any source bumps located proximate to the bumps of the bump configuration 310. While the example of Figure 4 is described in terms of accounting for other source bumps proximately located to the bumps of the bump configuration 310, the bump configuration evaluation technology described herein may account for any other circuit element (e.g., other sink bumps) in a consistent manner as described herein.

[0054] The bump configuration engine 110 may identify other source bumps of an input circuit design 210 as proximate to the bumps of a bump configuration 310 in various ways. As one example, the bump configuration engine 110 may identify proximate bumps as those included in a window that surrounds the particular bumps linked in the bump configuration 310. An example of such a window is shown in Figure 4 as the window 410. The bump configuration engine 110 may determine, for example, a minimum-sized window that surrounds, bounds, or otherwise encloses the bumps of the bump configuration 310 (e.g., as measured through the center location of the bumps, bump perimeter, or any other quantifiable metric by which to determine enclosure of individual bumps). Other sized windows are contemplated herein that enclose the source bump 312 and the sink bumps 314 of the bump configuration 310. In the example of Figure 4, the bump configuration engine 110 may determine any other source bumps located within the window 410 generated for the bump configuration 310 as proximate to the bumps of the bump configuration 310. As seen in Figure 4, two additional source bumps (aside from the source bump 312) are located within the window 410, and the bump configuration engine 110 may identify these other source bumps 416 as proximate to the bumps of the bump configuration 310. As such, the bump configuration engine 110 may account for the locations of these other source bumps 416 in generation of an evaluation matrix and construction of an evaluation image for the bump configuration 310.

[0055] Accounting for the other source bumps 416 in generation of an evaluation matrix for the bump configuration 310 is shown in Figure 4 via a 2D plot of the source bump 312, the sink bumps 314, and the other source bumps 416. In the example of Figure 4, the bump configuration engine 110 generates the evaluation matrix 420 forthe bump configuration engine 110 as a 6 x 7 matrix with six (6) rows and seven (7) columns. The bump configuration engine 110 may determine the evaluation matrix 420 to have a dimension of six (6) rows based on (e.g., as equal to) a number of unique y-coordinate values among the source bump 312, the sink bumps 314, and the other source bumps 416. A 2D plot of the bumps of the bump configuration 310 together with the other source bumps 416 proximate to the bumps of the bump configuration 310 is shown in Figure 4 along a horizontal x-axis and a vertical y-axis. In the example of Figure 4, the bump configuration engine 110 may determine that the source bump 312, the sink bumps 314, and the other source bumps 416 include six (6) unique vertical coordinate values. This can be seen in the 2D plot of Figure 4, in which the source bump 312, the sink bumps 314, and other source bumps 416 are plotted across six (6) different values on the y-axis, shown as Yi , Y2, Y3, Y4, Y5, and Ye.

[0056] For the column dimension of the evaluation matrix 420, the bump configuration engine 110 may determine the evaluation matrix 420 to have seven (7) columns based on (e.g., as equal to) a number of unique x-coordinate values among the source bump 312, the sink bumps 314, and the other source bumps 416. In the example of Figure 4, the bump configuration engine 110 may determine that the source bump 312, the sink bumps 314, and other source bumps 416 include seven (7) unique horizontal coordinate values. This can be seen in the 2D plot of Figure 4, in which the source bump 312, sink bumps 314, and other source bumps 416 are plotted across seven (7) different values on the x-axis, shown as Xi , X2, X3, X4, X5, Xe, and X7.

[0057] Accordingly, in the example of Figure 4, the bump configuration engine 110 may determine the dimensions of the evaluation matrix 420 to be a 7 x 6 matrix. In that regard, the bump configuration engine 110 may determine a number of rows in an evaluation matrix based on a number of unique vertical coordinate values (e.g., y- coordinate values) among a source bump (e.g., on a first surface), sink bumps (e.g., on the second surface), and any other source bumps on the first surface in a window that surrounds the source bump and the sink bumps. Likewise, the bump configuration engine 110 may determine a number of columns in the evaluation matrix based on a number of unique horizontal coordinate values (e.g., x-coordinate values) among the source bump on the first surface, the sink bumps on the second surface, and any other source bumps on the first surface in a window that surrounds the source bump andthe sink bumps. As described herein, each element of the evaluation matrix 320 may represent a different location, and each column may correspond to a respective horizontal coordinate value among the unique horizontal coordinate values and each row may correspond to a respective vertical coordinate value among the unique vertical coordinate values.

[0058] In generating the evaluation matrix 420, the bump configuration engine 110 may populate each of the elements the evaluation matrix 420 with a matrix value, e.g., doing so in a similar manner as described for generation of the evaluation matrix 320 of Figure 3. In Figure 3, a first value, second value, and third value are used to populated matrix values. In Figure 4, the bump configuration engine 110 may apply a fourth value for the other source bumps 416. Elements of the evaluation matrix 420 that represent locations of the other source bumps 416 may be populated with a matrix value that differs from those of the source bump 312 (e.g., populated with a first value of 0.8) and the sink bumps 314 (e.g., populated a second value of 0.2). In the example of Figure 4, the bump configuration engine 110 populates elements that represent the locations of the other source bumps 416 with a value of 0.5. Elements that represent locations without the source bump 312, any of the sink bumps 314, and any of the other source bumps 416 may be populated with a value of 0 (e.g., the third value of 0 as described in Figure 3 above). As each of the rows and columns may represent a different unique x and y-coordinate value among the bumps of the bump configuration 310 and the other source bumps 416, the bump configuration engine 110 may populate each of the elements of the evaluation matrix 420 based on what is located at the location represented by each element.

[0059] To provide an illustration for the other source bumps 416, element^) of the evaluation matrix 420 may represent a location with coordinates (Xs.Yi). The bump configuration engine 110 may determine that one of the other source bumps 416 proximate to the bump configuration 310 is located at (Xs.Yi). Accordingly, the bump configuration engine 110 may populate element^) of the evaluation matrix 420 with a value of 0.5, which may be a fourth value used by the bump configuration engine 110 in evaluation matrix generation. The first, second, and third values may be consistent with those described above for the evaluation matrix 320 in Figure 3, with the third value of 0 being used for elements / locations in the evaluation matrix 420 at which none of the source bump 312, sink bumps 314, and other source bumps 416 are located.In such a manner, the bump configuration engine 110 may generate an evaluation matrix 420 for a bump configuration 310 that accounts for other source bumps 416 in a window 410 that surrounds the bumps of a bump configuration 310. In Figure 4, the bump configuration engine 110 generates the evaluation matrix 420 with each matrix element populated with values based on locations of the source bump 312, the sink bumps 314, the other source bumps 316, and locations with none of these bumps.

[0060] The bump configuration engine 110 may then construct an evaluation image from the evaluation matrix 420 generated for the bump configuration 310, doing so in a similar manner as described above for the evaluation matrix 320. In doing so, the bump configuration engine 110 may encode data of the evaluation matrix 420 into the evaluation image 430 of Figure 4. As the evaluation matrix 420 of Figure 4 includes four (4) different matrix values, the bump configuration engine 110 may color pixel spaces of the generated evaluation image 430 with four different colors. In Figure 4, the bump configuration engine 110 constructs the evaluation image 430 in the form of a grayscale image with a respective pixel block representative of each element of the evaluation matrix 420, and each pixel block colored with a grayscale color specified by the matrix value of each element of the evaluation matrix 420. For matrix values representing the other source bumps 416, the bump configuration engine 110 may color such corresponding pixel blocks with a grayscale tone color = 0.5. Coloring of pixel blocks representing the source bump 312 (e.g., grayscale tone color = 0.8), sink bumps 314 (e.g., grayscale tone color = 0.2), and locations without any of the source bump 312, sink bumps 314, and other source bumps 416 (e.g., grayscale tone color = 0) may be converted similarly as described above for Figure 3. Then, the bump configuration engine 110 may provide the constructed evaluation image 430 as an input to the evaluation ML model 340 and obtain an evaluation value 450 for the bump configuration 310 accordingly.

[0061] Through evaluation of bump configurations, the bump configuration engine can obtain a quantified assessment of a specified link between bumps in an input circuit design 210. For bump configurations qualified as “poor” or below a quality threshold, changes to the bump configuration can improve design and functionality of such circuits. The bump configuration 110 may adjust a bump configuration between a source bump and sink bumps in an input circuit design based on the evaluation value generated for the bump configuration. Some examples are provided in the context ofthe bump configuration 310, e.g., when evaluation value 350 or 450 generated for the bump configuration 310 fails to satisfy the quality threshold.

[0062] As one example adjustment to the bump configuration 310, the bump configuration engine 110 may specify a link between a different source bump and the sink bumps 314 in the input circuit design 210, instead of the source bump 312. For example, the bump configuration engine 110 may select one of the other source bumps 416 to assign to the sink bumps 314 instead of the source bump 312. Thus, the bump configuration engine 110 may modify the bump configuration 310 such that source bump 312 is removed from the bump configuration 310 and instead replaced with one of the other source bumps 416. The bump configuration engine 110 may select another source bump (e.g., among the other source bumps 416) that is closest in distance to a centroid of the bumps of the bump configuration 310, e.g., a centroid of the sink bumps 314 with x and y-coordinates computed as an average of the x and y-coordinates of the sink bumps 314. Any other suitable selection mechanism may be employed by the bump configuration engine 110 to select a different source bump (e.g., to replace the source bump 312) of the bump configuration.

[0063] The bump configuration engine 110 may present any number of visual indicators for bump configurations with evaluation values that fail to satisfy the quality threshold. For example, the bump configuration engine 110 may output a listing of low quality bump configurations in the input circuit design 210 that fail the quality threshold, highlight such low quality bump configurations in an overlay top-down view of bumps of the input circuit design 210, provide evaluation value statistics for assessed bump configurations, and more. Any suitable statistics or metrics can be computed and visualized by the bump configuration engine 110 to support analysis and adjustment of bump configurations for circuit designs. As yet another example, manual or user-made adjustments may be made to bump configurations that fail to satisfy the quality threshold, which can be identified or presented through any number of visual indicators.

[0064] The bump configuration engine 110 may implement or perform any other suitable application or technique to support manufacture of the input circuit design, including with adjusted bump configurations. For example, the bump configuration engine 110 may store, transmit, or provide circuit designs with adjusted bump configurations for physical manufacture. In some implementations, a systemimplementing the bump configuration engine 110 may manufacture circuit designs with bump configurations evaluated or adjusted through the features described herein.

[0065] Figure 5 shows an example training of an evaluation ML model through training evaluation images constructed from training bump configurations. In the example of Figure 5, the bump configuration engine 110 may train the evaluation ML model 340. The bump configuration engine 110 may train the evaluation ML model 340 via any type of unsupervised, supervised, or semi-supervised machine learning techniques. Neural networks, monotonic machine learning models, cluster-based ML technologies, matrix models, reinforced learning models, or any other suitable machine learning implementations are contemplated herein, and the bump configuration engine 110 may construct or train any type of ML model accordingly and in support of any aspect of EDA design flows. In any suitable manner, the bump configuration engine 110 may train the evaluation ML model 340. As noted herein, the bump configuration engine 110 may implement or construct the evaluation ML model 340 as a convolutional neural network (CNN), which may be particularly- efficient for image classifications.

[0066] The bump configuration engine 110 may train the evaluation ML model 340 through training bump configurations 510. The training bump configurations may be any set of bump configurations, which the bump configuration engine 1 10 may obtain from circuit designs or as synthetic training data generated for ML trainings. The training bump configurations 510 may take any form that links any number of source bumps with any number of sink bumps, and may include location data (e.g., x-y coordinates) for the bumps included in the training bump configurations 510. The training bump configurations 510 may be accompanied with evaluation values 520, and an individual evaluation value may serve as a label for an individual training bump configuration. The evaluation values 520 for the training bump configurations 510 may be specified through, in some implementations, user input. For example, circuit designers may assess the training bump configurations 510 and assign evaluation values 520 for each of the training bump configurations 510.

[0067] The specific evaluation values 520 used to label the training bump configurations 510 may control the type and format of evaluation values that the evaluation ML model 340 can output. In that regard, the bump configuration engine 110 may control or specify operation of the evaluation ML model 340 through thetraining data (including the labels, as evaluation values 520) used to train the evaluation ML model. As such, the bump configuration engine 110 may control the evaluation ML model 340 to generate evaluation values in the form of a numerical scale by obtaining evaluation values 520 for the training bump configurations 510 specified in the numerical scale (e.g., ratings of 1 -10). As another example, the bump configuration engine 110 may control the evaluation ML model 340 to generate evaluation values in the form of a 3-tier classification of “good”, “neutral”, and “poor” by obtaining evaluation values 520 for the training bump configurations 510 specified according to the 3-tier classification. Any suitable type or format of evaluation values 520 as labels for ML training data and evaluation ML model outputs is contemplated herein.

[0068] The bump configuration engine 110 may convert the training bump configurations 510 into training evaluation images 530, doing so in any of the ways described herein. Construction of the training evaluation images 530 may comprise generation of evaluation matrices, which may, in some implementations, account for other source bumps proximate to the source bump(s) and sink bump(s) that form a given training bump configuration. The form, image size, pixel block size, pixel coloring, or any other relevant parameter of the constructed training evaluation images 530 may be controlled or specified by the bump configuration engine 110 to control or specify the type of images that the evaluation ML model 340 is particularly configured to take as inputs. For example, training evaluation images 350 in the form of grayscale images in which pixel blocks are colored based on matrix values of an evaluation images can be used to train the evaluation ML model 340. In that regard, the format, process, and parameters by which the bump configuration engine 110 constructs the training evaluation images 530 may define the format, process, and parameters by which the evaluation ML model 340 can receive input evaluation images (e.g., in an active mode after training).

[0069] Training of the evaluation ML model 340 may be performed through the training evaluation images 530 labeled with the evaluation values 520 for the training bump configurations 510 from which the training evaluation images 530 are constructed. As such, the bump configuration engine 110 may train the evaluation ML model 340 with training data that comprises training evaluation images 530 constructed from training bump configurations 510 between source bumps and sinkbumps. Such training data may comprise labels, as evaluation values 520, for the training evaluation images 530. Once trained, the evaluation ML model 340 may then be used to support ML-based evaluations of bump configurations, e.g., in any of the various ways described herein. In some implementations, the bump configuration engine 110 may itself implement the evaluation ML model 340. In other implementations, the bump configuration engine 110 may access, train, or construct the evaluation ML model 340 as a discrete or separate logical entity. In some implementations, the bump configuration engine 110 may instantiate, deploy, or utilize multiple instances of a trained evaluation ML model, which may allow for evaluations of multiple bump configurations in parallel.

[0070] Through any combination of the features herein, the bump configuration evaluation technology of the present disclosure may provide technical improvements to EDA computing systems and processes. Technical benefits of the evaluation ML model 340 (e.g., as compared to traditional graph theory assessment or determination of bump configurations) include speed, accuracy, and efficiency. Instead of the traditional graph theories that can require tedious calculations of edges and nodes across thousands or millions of bumps in circuit designs, the bump configuration evaluation technology described herein can support mapping of source bumps (e.g., power or ground sources) into 2D evaluation matrices and construction of evaluation images thereof. ML model-based image classification can support the evaluation of bump configurations with increased speed and accuracy as compared to conventional graph theories. Moreover, the ML-based bump configuration evaluations may provide improved scalability, as instances of the evaluation ML model can be executed in parallel (e.g., in a GPU farm), allowing for concurrent processing and evaluation of multiple bump configurations in parallel.

[0071] Figure 6 shows an example of logic 600 that a system may implement to support ML-based evaluation of bump configurations for circuit designs. For example, the computing system 100 may implement the logic 600 as hardware, executable instructions stored on a machine-readable medium, or as a combination of both. The computing system 100 may implement the logic 600 via the bump configuration engine 110, through which the computing system 100 may perform or execute the logic 600 as a method to support ML-based evaluation of bump configurations for circuit designs. The following description of the logic 600 is provided using the bumpconfiguration engine 110 as an example implementation. Any other implementation options by computing systems are possible.

[0072] In implementing the logic 600, the bump configuration engine 110 may access an input circuit design (602) and evaluate a bump configuration of the input circuit design that specifies a link between a source bump and sink bumps in the input circuit design (604). The bump configuration engine 110 may evaluate the bump configuration by generating an evaluation matrix based on locations of the source bump and the sink bumps in the input circuit design (606), constructing an evaluation image from the evaluation matrix based on matrix values in the evaluation matrix (608), and generating an evaluation value for the evaluation image using an evaluation ML model trained to generate evaluation values for bump configurations in circuit designs (610), doing so in any of the ways described herein. In implementing the logic 600, the bump configuration engine 110 may also adjust the bump configuration between the source bump and the sink bumps in the input circuit design based on the evaluation value (612), e.g., via any of the ways described herein.

[0073] The logic 600 shown in Figure 6 provides an illustrative example by which a computing system 100 may support or implement various features of the bump configuration evaluation technology described herein. Additional or alternative steps in the logic 600 are contemplated herein, including according to any of the various features described herein for the bump configuration engine 110.

[0074] Figure 7 shows an example of a computing system 700 that supports ML- based evaluation of bump configurations for circuit designs. The computing system 700 may include a processor 710, which may take the form of a single or multiple processors. The processor(s) 710 may include a central processing unit (CPU), microprocessor, or any hardware device suitable for executing instructions stored on a machine-readable medium. The computing system 700 may include a machine- readable medium 720. The machine-readable medium 720 may take the form of any non-transitory electronic, magnetic, optical, or other physical storage device that stores executable instructions, such as the bump configuration instructions 722 shown in Figure 7. As such, the machine-readable medium 720 may be, for example, Random Access Memory (RAM) such as a dynamic RAM (DRAM), flash memory, spin-transfer torque memory, an Electrically-Erasable Programmable Read-Only Memory (EEPROM), a storage drive, an optical disk, and the like.

[0075] The computing system 700 may execute instructions stored on the machine- readable medium 720 through the processor 710. Executing the instructions (e.g., the bump configuration instructions 722) may cause the computing system 700 to perform or implement any of the bump configuration evaluation technology described herein, including according to any aspect of the bump configuration engine 110.

[0076] For example, execution of the bump configuration instructions 722 by the processor 710 may cause the computing system 700 to access an input circuit design and evaluate a bump configuration of the input circuit design that specifies a link between a source bump and sink bumps in the input circuit design. Execution of the bump configuration instructions 722 may cause the computing system 700 to evaluate the bump configuration by generating an evaluation matrix based on locations of the source bump and the sink bumps in the input circuit design, constructing an evaluation image from the evaluation matrix based on matrix values in the evaluation matrix, and generating an evaluation value for the evaluation image using an evaluation ML model trained to generate evaluation values for bump configurations in circuit designs, doing so in any of the ways described herein. Execution of the bump configuration instructions 722 may also cause the computing system 700 to adjust the bump configuration between the source bump and the sink bumps in the input circuit design based on the evaluation value, e.g., via any of the ways described herein.

[0077] Any combination of the bump configuration evaluation technology as described herein may be implemented via the bump configuration instructions 722.

[0078] The systems, methods, devices, and logic described above, including the bump configuration engine 110, may be implemented in many different ways in many different combinations of hardware, logic, circuitry, and executable instructions stored on a machine-readable medium. For example, the bump configuration engine 110, may include circuitry in a controller, a microprocessor, or an application specific integrated circuit (ASIC), or may be implemented with discrete logic or components, or a combination of other types of analog or digital circuitry, combined on a single integrated circuit or distributed among multiple integrated circuits. A product, such as a computer program product, may include a storage medium and machine-readable instructions stored on the medium, which when executed in an endpoint, computer system, or other device, cause the device to perform operations according to any ofthe description above, including according to any features of the bump configuration engine 110.

[0079] The processing capability of the systems, devices, and engines described herein, including the bump configuration engine 110, may be distributed among multiple system components, such as among multiple processors and memories, optionally including multiple distributed processing systems or cloud / network elements. Parameters, databases, and other data structures may be separately stored and managed, may be incorporated into a single memory or database, may be logically and physically organized in many different ways, and may be implemented in many ways, including data structures such as linked lists, hash tables, or implicit storage mechanisms. Programs may be parts (e.g., subroutines) of a single program, separate programs, distributed across several memories and processors, or implemented in many different ways, such as in a library (e.g., a shared library).

[0080] While various examples and features have been described above, many more implementations are possible.

Claims

CLAIMS1 . A method comprising: by a computing system: accessing an input circuit design; evaluating a bump configuration of the input circuit design that specifies a link between a source bump and sink bumps in the input circuit design, wherein the source bump represents a connection element between circuits of a 3-dimension integrated circuit (3DIC) structure on a first surface of the input circuit design and the sink bumps represent connection elements between circuits of the 3DIC structure on a second surface of the input surface design, including by: generating an evaluation matrix based on locations of the source bump and the sink bumps in the input circuit design; constructing an evaluation image from the evaluation matrix based on matrix values in the evaluation matrix; and generating an evaluation value for the evaluation image using an evaluation machine learning (ML) model trained to generate evaluation values for bump configurations in circuit designs; and adjusting the bump configuration between the source bump and the sink bumps in the input circuit design based on the evaluation value.

2. The method of claim 1 , wherein generating the evaluation matrix comprises: determining a number of rows in the evaluation matrix based on a number of unique vertical coordinate values among the source bump on the first surface and the sink bumps on the second surface; and determining a number of columns in the evaluation matrix based on a number of unique horizontal coordinate values among the source bump on the first surface and the sink bumps on the second surface.

3. The method of claim 1 , wherein generating the evaluation matrix comprises: determining a number of rows in the evaluation matrix based on a number of unique vertical coordinate values among the source bump on the first surface, the sink bumps on the second surface, and any other source bumps on the first surface in a window that surrounds the source bump and the sink bumps; anddetermining a number of columns in the evaluation matrix based on a number of unique horizontal coordinate values among the source bump on the first surface, the sink bumps on the second surface, and any other source bumps on the first surface in a window that surrounds the source bump and the sink bumps.

4. The method of any of claims 1-3, wherein generating the evaluation matrix comprises populating matrix values for each element of the evaluation matrix based on the locations of the source bump and the sink bumps, including a first value for the source bump, a second value for the sink bumps, and a third value for locations without the source bump and the sink bumps, wherein the first value, the second value, and the third value are different from one another.

5. The method of claim 4, wherein constructing the evaluation image from the evaluation matrix based on the matrix values in the evaluation matrix comprises converting each element of the evaluation matrix into a pixel block in the evaluation image colored with a pixel color based on the matrix value populated for each element.

6. The method of any of claims 1-5, wherein adjusting the bump configuration comprises specifying a link between a different source bump and the sink bumps in the input circuit design, instead of the source bump.

7. The method of any of claims 1-6, further comprising training the evaluation ML model with training data that comprises training evaluation images constructed from training bump configurations between source bumps and sink bumps, the training data comprising labels, as evaluation values, for the training evaluation images.

8. A system comprising: a processor; and a non-transitory machine-readable medium comprising instructions that, when executed by the processor, cause a computing system to: access an input circuit design;evaluate a bump configuration of the input circuit design that specifies a link between a source bump and sink bumps in the input circuit design, wherein the source bump represents a connection element between circuits of a 3-dimension integrated circuit (3DIC) structure on a first surface of the input circuit design and the sink bumps represent connection elements between circuits of the 3DIC structure on a second surface of the input surface design, including by: generating an evaluation matrix based on locations of the source bump and the sink bumps in the input circuit design; constructing an evaluation image from the evaluation matrix based on matrix values in the evaluation matrix; and generating an evaluation value for the evaluation image using an evaluation machine learning (ML) model trained to generate evaluation values for bump configurations in circuit designs; and adjust the bump configuration between the source bump and the sink bumps in the input circuit design based on the evaluation value.

9. The system of claim 8, wherein the instructions, when executed, cause the computing system to generate the evaluation matrix by: determining a number of rows in the evaluation matrix based on a number of unique vertical coordinate values among the source bump on the first surface and the sink bumps on the second surface; and determining a number of columns in the evaluation matrix based on a number of unique horizontal coordinate values among the source bump on the first surface and the sink bumps on the second surface.

10. The system of claim 8, wherein the instructions, when executed, cause the computing system to generate the evaluation matrix by: determining a number of rows in the evaluation matrix based on a number of unique vertical coordinate values among the source bump on the first surface, thesink bumps on the second surface, and any other source bumps on the first surface in a window that surrounds the source bump and the sink bumps; and determining a number of columns in the evaluation matrix based on a number of unique horizontal coordinate values among the source bump on the first surface, the sink bumps on the second surface, and any other source bumps on the first surface in a window that surrounds the source bump and the sink bumps.11 . The system of any of claims 8-10, wherein the instructions, when executed, cause the computing system to generate the evaluation matrix by populating matrix values for each element of the evaluation matrix based on the locations of the source bump and the sink bumps, including a first value for the source bump, a second value for the sink bumps, and a third value for locations without the source bump and the sink bumps, wherein the first value, the second value, and the third value are different from one another.

12. The system of claim 11 , wherein the instructions, when executed, cause the computing system to construct the evaluation image from the evaluation matrix based on the matrix values in the evaluation matrix by converting each element of the evaluation matrix into a pixel block in the evaluation image colored with a pixel color based on the matrix value populated for each element.

13. The system of any of claims 8-12, wherein the instructions, when executed, cause the computing system to adjust the bump configuration by specifying a link between a different source bump and the sink bumps in the input circuit design, instead of the source bump.

14. The system of any of claims 8-13, wherein the instructions, when executed, further cause the computing system to train the evaluation ML model with training data that comprises training evaluation images constructed from training bump configurations between source bumps and sink bumps, the training data comprising labels, as evaluation values, for the training evaluation images.

15. A non-transitory machine-readable medium comprising instructions that, when executed by the processor, cause a computing system to perform a method according to any of claims 1-7.

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