Discrete power transistor configured with enhanced harmonic termination and process of implementing the same

Abstract

A packaged transistor device includes an RF signal input lead, an RF signal output lead, and a discrete transistor having a transistor structure arranged and / or formed on a substrate. The packaged transistor device also includes at least one harmonic reduction circuit arranged and / or formed on the substrate of the discrete transistor.

Description

DISCRETE POWER TRANSISTOR CONFIGURED WITH ENHANCED HARMONIC TERMINATION AND PROCESS OF IMPLEMENTING THE SAMECROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims the benefit from U.S. Non-Provisional Application No. 18 / 787,245 filed on July 29, 2024, which is hereby incorporated by reference in its entirety for all purposes as if fully set forth herein.FIELD OF THE DISCLOSURE

[0002] The disclosure relates to a discrete power transistor configured with enhanced harmonic termination. The disclosure further relates to a process of implementing a discrete power transistor configured with enhanced harmonic termination.BACKGROUND OF THE DISCLOSURE

[0003] Improved linearity during high-frequency operation is a goal in radio frequency (RF) power transistor technologies. Many factors can affect the linearity of a device in various RF power transistor technologies, including changing input and impedance with signal level, changing capacitances and their derivatives with signal levels, breakdown and substrate conduction effects, class of operation, and changing transconductance and its derivatives with bias and signal levels. In addition, in some applications, it may be desirable for an RF power transistor to achieve a desired level of linearity over a wide range of operating frequencies and / or output power levels. However, these linearity requirements in current implementations of radio frequency (RF) power transistors limit efficiency under high- frequency operation

[0004] Accordingly, radio frequency (RF) power transistor implementations having greater efficiency under high-frequency operation are needed.SUMMARY OF THE DISCLOSURE

[0005] The foregoing needs are met, to a great extent, by the disclosure, wherein in one aspect a discrete power transistor configured with enhanced harmonic termination is provided. Further, the foregoing needs are met, to a great extent, by the disclosure, wherein in one aspect a process of implementing a discrete power transistor configured with enhanced harmonic termination is provided.

[0006] In one aspect, a packaged transistor device includes an RF signal input lead. The packaged transistor device in addition includes an RF signal output lead. The packaged transistor device moreover includes a discrete transistor having a transistor structure arranged and / or formed on a substrate. The packaged transistor device also includes at least one harmonic reduction circuit arranged and / or formed on the substrate of the discrete transistor.

[0007] In one aspect, a process includes providing an RF signal input lead. The process in addition includes providing an RF signal output lead. The process moreover includes forming and arranging a discrete transistor having a transistor structure on a substrate. The process also includes forming and arranging at least one harmonic reduction circuit on the substrate of the discrete transistor.

[0008] In one aspect, a packaged transistor device includes an RF signal input lead. The packaged transistor device in addition includes an RF signal output lead. The packaged transistor device moreover includes a discrete transistor having a transistor structure arranged and / or formed on a substrate. The packaged transistor device also includes at least one harmonic reduction circuit arranged and / or formed on the substrate of the discrete transistor. The packaged transistor device further includes where a structure of the at least one harmonic reduction circuit is arranged at least partially on the substrate, is arranged at least partially on the transistor structure, and / or is arranged at least partially on the substrate and the transistor structure.

[0009] In one aspect, a process includes providing an RF signal input lead. The process in addition includes providing an RF signal output lead. The process moreover includes forming and arranging a discrete transistor having a transistor structure on a substrate. The process also includes forming and arranging at least one harmonic reduction circuit on the substrate of the discrete transistor. The process further includes where a structure of the at least one harmonic reduction circuit is arranged at least partially on the substrate, is arranged at least partially on the transistor structure, and / or is arranged at least partially on the substrate and the transistor structure.

[0010] There has thus been outlined, rather broadly, certain aspects of the disclosure in order that the detailed description thereof herein may be better understood, and in order that the present contribution to the art may be betterappreciated. There are, of course, additional aspects of the disclosure that will be described below and which will form the subject matter of the claims appended hereto.

[0011] In this respect, before explaining at least one aspect of the disclosure in detail, it is to be understood that the disclosure is not limited in its application to the details of construction and to the arrangements of the components set forth in the following description or illustrated in the drawings. The disclosure is capable of aspects in addition to those described and of being practiced and carried out in various ways. Also, it is to be understood that the phraseology and terminology employed herein, as well as the abstract, are for the purpose of description and should not be regarded as limiting.

[0012] As such, those skilled in the art will appreciate that the conception upon which this disclosure is based may readily be utilized as a basis for the designing of other structures, methods and systems for carrying out the several purposes of the disclosure. It is important, therefore, that the claims be regarded as including such equivalent constructions insofar as they do not depart from the spirit and scope of the disclosure.BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 illustrates a packaged transistor device according to aspects of the disclosure.

[0014] Figure 2 illustrates another packaged transistor device according to aspects of the disclosure.

[0015] Figure 3 illustrates another packaged transistor device according to aspects of the disclosure.

[0016] Figure 4 illustrates another packaged transistor device according to aspects of the disclosure.

[0017] Figure 5 illustrates another packaged transistor device according to aspects of the disclosure.

[0018] Figure 6 illustrates another packaged transistor device according to aspects of the disclosure.

[0019] Figure 7 illustrates a cross-sectional view of an exemplary implementation of the discrete transistor according to aspects of the disclosure.

[0020] Figure 8 illustrates a cross-sectional view of an exemplary implementation of the at least one capacitor according to aspects of the disclosure.

[0021] Figure 9 illustrates a cross-sectional view of an exemplary implementation of the at least one inductive element according to aspects of the disclosure.

[0022] Figure 10 illustrates a top view of the at least one inductive element according to Figure 9.

[0023] Figure 11 illustrates a cross-sectional view of an exemplary combined implementation of the at least one capacitor and the at least one inductive element according to aspects of the disclosure.

[0024] Figure 12 illustrates an exemplary implementation of the transistor structure that may include a plurality of unit cell transistors in accordance with an aspect of the disclosure.

[0025] Figure 13 is a schematic cross-sectional view taken along line XIII- XIII of Figure 12.

[0026] Figure 14 illustrates a partial schematic circuit diagram of the discrete transistor according to aspects of the disclosure.

[0027] Figure 15 illustrates a partial schematic circuit diagram of the discrete transistor according to aspects of the disclosure.

[0028] Figure 16 illustrates a partial schematic circuit diagram of the discrete transistor according to aspects of the disclosure.

[0029] Figure 17 illustrates a partial schematic circuit diagram of the discrete transistor according to aspects of the disclosure.

[0030] Figure 18 illustrates a partial schematic circuit diagram of the discrete transistor according to aspects of the disclosure.

[0031] Figure 19 illustrates an exemplary implementation of the discrete transistor according to aspects of the disclosure.

[0032] Figure 20 illustrates an exemplary implementation of the discrete transistor according to aspects of the disclosure.

[0033] Figure 21 illustrates an exemplary implementation of the discrete transistor according to aspects of the disclosure.

[0034] Figure 22 illustrates an exemplary implementation of the discrete transistor according to aspects of the disclosure.

[0035] Figure 23 illustrates an exemplary implementation of the discrete transistor according to aspects of the disclosure.

[0036] Figure 24 illustrates an exemplary implementation of the discrete transistor according to aspects of the disclosure.

[0037] Figure 25 illustrates an exemplary implementation of the discrete transistor according to aspects of the disclosure.

[0038] Figure 26 and Figure 27 illustrate simulated results of the harmonic reduction circuit and / or the harmonic reduction circuit implementing bandpass topology versus the harmonic reduction circuit and / or the harmonic reduction circuit implementing low-pass topology.

[0039] Figure 28 illustrates a perspective view of a package according to the disclosure.

[0040] Figure 29 illustrates a cross-sectional view of the package according to Figure 28.

[0041] Figure 30 illustrates a perspective view of a package according to the disclosure.

[0042] Figure 31 shows a process of making a package according to the disclosure.DETAILED DESCRIPTION

[0043] The disclosure will now be described with reference to the drawing figures, in which like reference numerals refer to like parts throughout. Aspects of the disclosure advantageously provide a discrete power transistor configured with enhanced harmonic termination. Further, aspects of the disclosure advantageously provide a process of implementing a discrete power transistor configured with enhanced harmonic termination.

[0044] Currently, second harmonic terminations are achieved through the use of a chip and wire technique. Forming a shunt inductor to ground through a separate physical capacitor. This technique works well from 0.4 GHz - 3.0 GHz, but becomes practically difficult to implement above 3 GHz.

[0045] The disclosed discrete power transistor with enhanced harmonic termination may implement a capacitor buried underneath a wirebond pad, a capacitor under a wirebond with an inductor in a white space, a capacitor and inductor in a white space, an inductor on top of a capacitor in a white space, aninductor printed in a white space available between wirebond pads, and / or the like. It may be important with this approach that a final die size either does not grow, or the increase is acceptable for performance gains at higher frequency, where a second harmonic (2F0) termination could not otherwise be implemented.

[0046] In aspects, a second harmonic match may be implemented by absorbing an inductor into a fundamental match as a bandpass structure. This may make a physical realization of this component as compact as possible. Using a bandpass match provides for higher performance.

[0047] In particular, current technology utilizes a chip and wire with manufacturing variability. Realization of this technique monolithically will further improve performance and will reduce variability.

[0048] In aspects, implementation of the disclosed discrete power transistor with enhanced harmonic termination results in limited or no increase in chip size. In aspects, the disclosed discrete power transistor with enhanced harmonic termination may implement an inductor on capacitor configuration. In aspects, the disclosed discrete power transistor with enhanced harmonic termination may implement a bond on capacitor configuration.

[0049] In aspects, the disclosed discrete power transistor with enhanced harmonic termination may have applications in cellular infrastructure base station radios, aerospace and defense telecommunications and radar. And wherever the need for enhanced efficiency in a transistor based design may exist.

[0050] Figure 1 illustrates a packaged transistor device according to aspects of the disclosure.

[0051] Figure 2 illustrates another packaged transistor device according to aspects of the disclosure.

[0052] Figure 3 illustrates another packaged transistor device according to aspects of the disclosure.

[0053] In particular, Figure 1 , Figure 2, and Figure 3 Illustrate a packaged transistor device 100. In aspects, the packaged transistor device 100 may include a discrete transistor 200, an RF signal input lead 140, an RF signal output lead 180, and / or the like.

[0054] The discrete transistor 200 may include a transistor structure 202 and an enhanced harmonic structure as further described herein. In particular, thetransistor structure 202 may be arranged and / or formed on a substrate 210 and the enhanced harmonic structure may be arranged and / or formed on the substrate 210.

[0055] With reference to Figure 1 and Figure 3, the discrete transistor 200 may further include a harmonic reduction circuit 204. In aspects, the harmonic reduction circuit 204 and the transistor structure 202 may be arranged and / or formed on the substrate 210. In aspects, the harmonic reduction circuit 204 may be configured as the enhanced harmonic structure, an enhanced harmonic termination structure, an enhanced harmonic circuit, an enhanced harmonic termination circuit structure, and / or the like.

[0056] With reference to Figure 2 and Figure 3, the discrete transistor 200 may further include a harmonic reduction circuit 206. In aspects, the harmonic reduction circuit 206 and the transistor structure 202 may be arranged and / or formed on the substrate 210. In aspects, the harmonic reduction circuit 206 may be configured as the enhanced harmonic structure, an enhanced harmonic termination structure, an enhanced harmonic circuit, an enhanced harmonic termination circuit structure, and / or the like.

[0057] In aspects, the packaged transistor device 100 may include the harmonic reduction circuit 204. In this aspect, the harmonic reduction circuit 204 and the transistor structure 202 may be arranged and / or formed on the substrate 210.

[0058] In aspects, the packaged transistor device 100 may include the harmonic reduction circuit 206. In this aspect, the harmonic reduction circuit 206 and the transistor structure 202 may be arranged and / or formed on the substrate 210.

[0059] In aspects, the packaged transistor device 100 may include the harmonic reduction circuit 204 and the harmonic reduction circuit 206. In this aspect, the harmonic reduction circuit 204, the harmonic reduction circuit 206, and the transistor structure 202 may be arranged and / or formed on the substrate 210.

[0060] In aspects, the harmonic reduction circuit 204 and / or the harmonic reduction circuit 206 may implement a capacitor buried underneath a wirebond pad of the discrete transistor 200; and 2) an inductor printed in a white space available between wirebond pads of the discrete transistor 200. It may be important with this approach that a final die size of the discrete transistor 200 either does not grow, or the increase is acceptable for performance gains at higher frequency, where a second harmonic (2F0) could not usually be used.

[0061] In aspects, the harmonic reduction circuit 204 and / or the harmonic reduction circuit 206 may be implemented by absorbing an inductor into a fundamental match as a bandpass structure. This may make a physical realization of the discrete transistor 200 as compact as possible. Using a bandpass match provides for higher performance.

[0062] In aspects, implementation of the discrete transistor 200 with the harmonic reduction circuit 204 and / or the harmonic reduction circuit 206 as disclosed may result in limited or no increase in chip size of the discrete transistor 200. In aspects, the harmonic reduction circuit 204 and / or the harmonic reduction circuit 206 may implement an inductor on capacitor configuration. In aspects, the harmonic reduction circuit 204 and / or the harmonic reduction circuit 206 may implement a bond on capacitor configuration.

[0063] In aspects, the packaged transistor device 100 and / or the discrete transistor 200 may be configured to connect the RF signal input lead 140 to a control electrode of the discrete transistor 200 and / or the transistor structure 202. For example, the packaged transistor device 100 and / or the discrete transistor 200 may be configured to connect the RF signal input lead 140 to a gate of a FET; or the packaged transistor device 100 and / or the discrete transistor 200 may be configured to connect the RF signal input lead 140 to a base of a bipolar transistor.

[0064] In aspects, the discrete transistor 200 may be configured to connect the harmonic reduction circuit 204 to a control electrode of the transistor structure 202. For example, the discrete transistor 200 may be configured to connect the harmonic reduction circuit 204 to a gate of a FET; or the discrete transistor 200 may be configured to connect the harmonic reduction circuit 204 to a base of a bipolar transistor. In aspects, the packaged transistor device 100 may be configured to connect the RF signal input lead 140 to the harmonic reduction circuit 204 of the discrete transistor 200.

[0065] In aspects, the packaged transistor device 100 and / or the discrete transistor 200 may be configured to connect the RF signal output lead 180 to an output electrode of the discrete transistor 200 and / or the transistor structure 202. For example, the packaged transistor device 100 and / or the discrete transistor 200 may be configured to connect the RF signal output lead 180 to a drain of a FET; or the packaged transistor device 100 and / or the discrete transistor 200 may be configuredto connect the RF signal output lead 180 to a collector or emitter of a bipolar transistor. The RF signal input lead 140 and the RF signal output lead 180 may extend outside the packaged transistor device 100. The source of the discrete transistor 200 may be grounded.

[0066] In aspects, the discrete transistor 200 may be configured to connect the harmonic reduction circuit 206 to an output electrode of the transistor structure 202. For example, the discrete transistor 200 may be configured to connect the harmonic reduction circuit 206 to a drain D of a FET; or the discrete transistor 200 may be configured to connect the harmonic reduction circuit 206 to a collector or emitter of a bipolar transistor. In aspects, the discrete transistor 200 may be configured to connect the RF signal output lead 180 to the harmonic reduction circuit 206.

[0067] In aspects, the substrate 210 may be made of Silicon Carbide (SiC). In another aspect, the substrate 210 may be GaAs, GaN, or other material suitable for the applications described herein. In another aspect, the substrate 210 may include sapphire, spinel, ZnO, silicon, and / or any other material capable of supporting growth of Group lll-nitride materials.

[0068] In aspects, the packaged transistor device 100 may be implemented as a RF package, a RF amplifier package, a RF power amplifier package, a RF power transistor package, a RF power amplifier transistor package, a power transistor package, and / or the like as described herein.

[0069] According to aspects of the disclosure, the packaged transistor device 100 implementing the discrete transistor 200 having the harmonic reduction circuit 204 and / or the harmonic reduction circuit 206 within the discrete transistor 200 may be configured such that harmonic reduction can occur before the signal reaches the RF signal output lead 180. Thus, the packaged transistor device 100 implementing the discrete transistor 200 having the harmonic reduction circuit 204 and / or the harmonic reduction circuit 206 within the discrete transistor 200 may improve linearity of the packaged transistor device 100 by reducing second and / or higher order harmonics within the discrete transistor 200 itself. Placing the harmonic reduction circuit 204 and / or the harmonic reduction circuit 206 within the discrete transistor 200 may improve the performance across a broad range of frequencies and / or output power levels. Furthermore, design of an external output matching circuit may be simplified,since the signal output from the packaged transistor device 100 may have lower energy at harmonic frequencies.

[0070] In aspects shown in Figure 1 and Figure 3, the packaged transistor device 100 may include the discrete transistor 200 and the discrete transistor 200 may include the harmonic reduction circuit 204 connected to a control electrode of the transistor structure 202. The discrete transistor 200 implementing the harmonic reduction circuit 204 may be configured to reduce the energy at a harmonic frequency, such as the second harmonic frequency, in the input signal.

[0071] In aspects illustrated in Figure 2 and Figure 3, the discrete transistor 200 may be configured with the harmonic reduction circuit 206 at the output (drain) of the transistor structure 202. The harmonic reduction circuit 206 may be configured to reduce the energy at a harmonic frequency, such as the second harmonic frequency, in the output signal.

[0072] In aspects, the discrete transistor 200 may be implemented as a gallium nitride (GaN) silicon carbide (SiC) transistor. In aspects, the discrete transistor 200 may be implemented as one or more of a wide band-gap semiconductor device, an ultra-wideband device, a GaN based device, a Metal Semiconductor Field-Effect Transistor (MESFET), a Metal Oxide Field Effect Transistor (MOSFET), a Junction Field Effect Transistor (JFET), a Bipolar Junction Transistor (BJT), an Insulated Gate Bipolar Transistor (IGBT), a high-electron-mobility transistor (HEMT), a Wide Band Gap (WBG) semiconductor, a component such as a General-Purpose Broadband component, a Telecom component, a L-Band component, a S-Band component, a X- Band component, a C-Band component, a Ku-Band component, a Satellite Communications component, a Doherty configuration, and / or the like. In aspects of the packaged transistor device 100, the discrete transistor 200 may be implemented as a RF power transistor and may include a plurality of transistor cells operating in parallel. In aspects, the discrete transistor 200 may include laterally diffused MOSFETS (LDMOSFET) or other semiconductor devices, such as bipolar devices, MESFET devices, HBTs and HEMT devices. In aspects, the discrete transistor 200 may be made using narrow or wide bandgap semiconductors. In aspects, the discrete transistor 200 may include silicon LDMOS and / or bipolar transistors, and / or lll-V devices such as GaAs MESFETs, InGaP HBTs, GaN HEMT devices, GaN bipolar transistors, and / or the like

[0073] In aspects, the packaged transistor device 100 may be mounted on an application interface, such as a printed circuit board (not shown). An external output matching circuit may also be mounted on the application interface. A bias / RF diplexer (not shown) may be connected to the external output matching circuit to connect the transistor output to an RF output. Furthermore, a DC power supply (not shown) may be connected to the RF signal output lead 180. It will be appreciated that the base of the packaged transistor device 100 can refer to any structural member on which the discrete transistor 200 is mounted, and accordingly can correspond to a substrate, flange, die carrier, or the like.

[0074] Figure 4 illustrates another packaged transistor device according to aspects of the disclosure.

[0075] Figure 5 illustrates another packaged transistor device according to aspects of the disclosure.

[0076] Figure 6 illustrates another packaged transistor device according to aspects of the disclosure.

[0077] In particular, Figure 4, Figure 5, and Figure 6 illustrates that the packaged transistor device 100 may further include an input matching circuit 104 and / or an output matching circuit 106. However, other implementations of the packaged transistor device 100 may only include the input matching circuit 104; and other implementations of the packaged transistor device 100 may only include the output matching circuit 106.

[0078] With reference to Figure 4 and Figure 6, the discrete transistor 200 may further include the harmonic reduction circuit 204. With reference to Figure 5 and Figure 6, the discrete transistor 200 may further include the harmonic reduction circuit 206.

[0079] In aspects, the packaged transistor device 100 and / or the discrete transistor 200 may be configured to connect the input matching circuit 104 to a control electrode of the discrete transistor 200 and / or the transistor structure 202. For example, the packaged transistor device 100 and / or the discrete transistor 200 may be configured to connect the input matching circuit 104 to a gate of a FET; or the packaged transistor device 100 and / or the discrete transistor 200 may be configured to connect the input matching circuit 104 to a base of a bipolar transistor.

[0080] In aspects, the packaged transistor device 100 and / or the discrete transistor 200 may be configured to connect the output matching circuit 106 to an output electrode of the discrete transistor 200 and / or the transistor structure 202. For example, the packaged transistor device 100 and / or the discrete transistor 200 may be configured to connect the output matching circuit 106 to a drain of a FET; or the packaged transistor device 100 and / or the discrete transistor 200 may be configured to connect the output matching circuit 106 to a collector or emitter of a bipolar transistor.

[0081] In aspects shown in Figure 4 and Figure 6, the packaged transistor device 100 may include the input matching circuit 104 and the discrete transistor 200 may include the harmonic reduction circuit 204 connected to a control electrode of the transistor structure 202. The packaged transistor device 100 implementing the discrete transistor 200 and the harmonic reduction circuit 204 may be configured to reduce the energy at a harmonic frequency, such as the second harmonic frequency, in the input signal.

[0082] In aspects shown in Figure 5 and Figure 6, the packaged transistor device 100 may include the output matching circuit 106 and the discrete transistor 200 may be configured with the harmonic reduction circuit 206 at the output (drain) of the transistor structure 202. The harmonic reduction circuit 206 may be configured to reduce the energy at a harmonic frequency, such as the second harmonic frequency, in the output signal.

[0083] Figure 7 illustrates a cross-sectional view of an exemplary implementation of the discrete transistor according to aspects of the disclosure.

[0084] In particular, Figure 7 illustrates an exemplary implementation of the discrete transistor 200. In aspects, the discrete transistor 200 may implement the harmonic reduction circuit 204, the discrete transistor 200 may implement the harmonic reduction circuit 206, and / or the discrete transistor 200 may implement the harmonic reduction circuit 204 and the harmonic reduction circuit 206.

[0085] In aspects, a structure of the harmonic reduction circuit 204 may be arranged at least partially on the substrate 210, may be arranged at least partially on the transistor structure 202, and / or may be arranged at least partially on the substrate 210 and the transistor structure 202. In aspects, the harmonic reduction circuit 204may include at least one inductive element 220, at least one capacitor 222, at least one resistor 224, and / or the like.

[0086] In aspects, a structure of the harmonic reduction circuit 206 may be arranged at least partially on the substrate 210, may be arranged at least partially on the transistor structure 202, and / or may be arranged at least partially on the substrate 210 and the transistor structure 202. In aspects, the harmonic reduction circuit 206 may include at least one inductive element 220, at least one capacitor 222, at least one resistor 224, and / or the like.

[0087] In aspects, a structure of the transistor structure 202 may be arranged at least partially on the substrate 210, may be arranged at least partially on the harmonic reduction circuit 204, may be arranged at least partially on the harmonic reduction circuit 206, and / or may be arranged at least partially on the substrate 210, the harmonic reduction circuit 204, and / or the harmonic reduction circuit 206.

[0088] Figure 8 illustrates a cross-sectional view of an exemplary implementation of the at least one capacitor according to aspects of the disclosure.

[0089] In particular, Figure 8 illustrates an exemplary implementation of the at least one capacitor 222. In aspects, the at least one capacitor 222 may include at least one dielectric layer 262, at least one capacitor top metal 264, at least one capacitor bottom metal 266, and / or the like. In particular, the at least one capacitor 222 may form a capacitor with the at least one capacitor top metal 264 and the at least one capacitor bottom metal 266 having the at least one dielectric layer 262 therebetween. In aspects, a structure of the at least one capacitor 222 may be arranged at least partially on the substrate 210, may be arranged at least partially on the transistor structure 202, and / or may be arranged at least partially on the substrate 210 and the transistor structure 202.

[0090] Figure 9 illustrates a cross-sectional view of an exemplary implementation of the at least one inductive element according to aspects of the disclosure.

[0091] In particular, Figure 9 illustrates an exemplary implementation of the at least one inductive element 220. In aspects, the at least one inductive element 220 may include at least one inductor metal 274 and / or the like. In particular, the at least one inductive element 220 may form an inductor by arrangement of the at least one inductor metal 274 on the substrate 210. In aspects, a structure of the at least oneinductive element 220 may be arranged at least partially on the substrate 210, may be arranged at least partially on the transistor structure 202, and / or may be arranged at least partially on the substrate 210 and the transistor structure 202.

[0092] Figure 10 illustrates a top view of an exemplary combined implementation of the at least one capacitor and the at least one inductive element according to aspects of the disclosure.

[0093] Figure 11 illustrates a cross-sectional view of the exemplary combined implementation of the at least one capacitor and the at least one inductive element according to Figure 10.

[0094] As illustrated in Figure 10, in aspects the at least one inductive element 220 may implement a spiral structural configuration of the at least one inductor metal 274. Further, the at least one capacitor 222 may form a capacitor with the at least one capacitor top metal 264 and the at least one capacitor bottom metal 266 having the at least one dielectric layer 262 therebetween as illustrated in Figure 11 ; and the at least one inductive element 220 may form an inductor by arrangement of the at least one inductor metal 274 on at least one dielectric layer 272 as illustrated in Figure 10 and Figure 11 .

[0095] In aspects, a structure of the at least one capacitor 222 may be arranged at least partially on the substrate 210, may be arranged at least partially on the transistor structure 202, may be arranged at least partially on the substrate 210 and the transistor structure 202, and / or may be arranged at least partially on the at least one inductive element 220 (not shown). In aspects, a structure of the at least one inductive element 220 may be arranged at least partially on the substrate 210, may be arranged at least partially on the transistor structure 202, may be arranged at least partially on the substrate 210 and the transistor structure 202, and / or may be arranged at least partially on the at least one capacitor 222.

[0096] Figure 12 illustrates an exemplary implementation of the transistor structure that may include a plurality of unit cell transistors in accordance with an aspect of the disclosure.

[0097] In particular, Figure 12 illustrates an exemplary implementation of the transistor structure 202 that may include a plurality of unit cells 430. In aspects, the transistor structure 202 may include a gate bus 402 that may be connected to a plurality of gate fingers 406 that may extend in parallel in a first direction (e.g., the Z-direction indicated in Figure 12) that connect to or form part of a gate. A source bus 410 may be connected to a plurality of parallel ones of source contacts 416 that connect to or form part of a source. In some aspects, the source bus 410 may be connected to a ground voltage node on an underside of the transistor structure 202. A drain bus 420 may be connected to a plurality of drain contacts 426 that connect to or form part of a drain.

[0098] As can be seen in Figure 12, each gate finger 406 may run along the Z-direction between a pair of adjacent ones of the source contact 416 and the drain contact 426. The transistor structure 202 may include the plurality of unit cells 430, where each one of the plurality of unit cells 430 includes an implementation of a transistor. One of the plurality of unit cells 430 is illustrated by the dashed box in Figure 12, and includes a gate finger 406 that extends between adjacent ones of the source contact 416 and the drain contact 426.

[0099] The "gate width" refers to the distance by which the gate finger 406 overlaps with its associated one of the source contact 416 and drain contact 426 in the Z-direction. That is, "width" of a gate finger 406 refers to the dimension of the gate finger 406 that extends in parallel to and adjacent an implementation of the source contact 416 and the drain contact 426 (the distance along the Z-direction). Each of the plurality of unit cells 430 may share one of the source contact 416 and / or the drain contact 426 with one or more adjacent ones of the plurality of unit cells 430. Although a particular number of the of the plurality of unit cells 430 is illustrated in Figure 12, it will be appreciated that the transistor structure 202 may include more or less of the plurality of unit cells 430.

[0100] Figure 13 is a schematic cross-sectional view taken along line XIII- XIII of Figure 12.

[0101] Referring to Figure 13, the transistor structure 202 may include the substrate 210, a buffer layer 110, a barrier layer 108, and / or the like. The source contact 416 and the drain contact 426 may be on the barrier layer 108. The gate fingers 406 may be on the substrate 210 between the source contacts 416 and the drain contacts 426. While the gate fingers 406, the source contact 416, and the drain contacts 426 are all shown schematically in Figure 12 and Figure 13 as having a similar "dimension," it will be appreciated that each may have different shapes and dimensions consistent with the disclosure.

[0102] Figure 14 illustrates a partial schematic circuit diagram of the discrete transistor according to aspects of the disclosure.

[0103] In particular, Figure 14 illustrates a partial schematic circuit diagram of the discrete transistor 200 that includes the harmonic reduction circuit 204 and the transistor structure 202 arranged on the substrate 210. In aspects, the harmonic reduction circuit 204 may be connected to the control terminal (gate) of the transistor structure 202. In aspects illustrated in Figure 14, the harmonic reduction circuit 204 may include the at least one inductive element 220 in series with the at least one capacitor 222. More specifically, the harmonic reduction circuit 204 illustrated in Figure 14 may be implemented as an RCL circuit (resistor - capacitor - inductor circuit). In other aspects not illustrated, the harmonic reduction circuit 204 may be implemented as an RLC (resistor - inductor - capacitor circuit), an LRC circuit (inductor - resistor - capacitor circuit), a circuit having any arrangement of at least one inductor, resistor, and capacitor and / or the like.

[0104] In aspects, the inductance of the at least one inductive element 220 and the capacitance of the at least one capacitor 222 may be selected so as to provide a bandpass implementation. In aspects, the at least one capacitor 222 may be implemented as a shunt capacitor. In aspects, the inductance of the at least one inductive element 220 and the capacitance of the at least one capacitor 222 may be selected so as to provide a short circuit and / or low impedance path to ground for signals at a harmonic frequency, such as the second harmonic frequency, relative to the fundamental operating frequency of the discrete transistor 200 at the input to the transistor structure 202.

[0105] Figure 15 illustrates a partial schematic circuit diagram of the discrete transistor according to aspects of the disclosure.

[0106] In particular, Figure 15 illustrates a partial schematic circuit diagram of the discrete transistor 200 that includes the harmonic reduction circuit 206 and the transistor structure 202 arranged on the substrate 210. In aspects, the harmonic reduction circuit 206 may be coupled to an output terminal (drain) of the transistor structure 202.

[0107] In aspects, the inductance of the at least one inductive element 220 and the capacitance of the at least one capacitor 222 may be selected so as to provide a bandpass implementation. In aspects, the harmonic reduction circuit 206 may includethe at least one inductive element 220 in series with the at least one capacitor 222, which may be implemented as a shunt capacitor. The inductance of the at least one inductive element 220 and the capacitance of the at least one capacitor 222 may be selected so as to provide short circuits and / or low impedance paths to ground for signals at a harmonic frequency, such as the second harmonic frequency, relative to the fundamental operating frequency of the discrete transistor 200 at the output of the discrete transistor 200.

[0108] Figure 16 illustrates a partial schematic circuit diagram of the discrete transistor according to aspects of the disclosure.

[0109] In particular, Figure 16 illustrates a partial schematic circuit diagram of the discrete transistor 200 that includes the harmonic reduction circuit 206 and / or the harmonic reduction circuit 204 and the transistor structure 202 arranged on the substrate 210. In aspects, the inductance of the at least one inductive element 220 and the capacitance of the at least one capacitor 222 may be selected so as to provide a bandpass implementation.

[0110] In aspects, the harmonic reduction circuit 206 and / or the harmonic reduction circuit 204 may include an implementation of the at least one inductive element 220 in series with an implementation of the at least one capacitor 222 and the harmonic reduction circuit 206 and / or the harmonic reduction circuit 204 may include another implementation of the at least one inductive element 220 in series with another implementation of the at least one capacitor 222. Additionally, the harmonic reduction circuit 206 and / or the harmonic reduction circuit 204 may include a further implementation of the at least one inductive element 220 in series with an implementation of the at least one capacitor 222.

[0111] Figure 17 illustrates a partial schematic circuit diagram of the discrete transistor according to aspects of the disclosure.

[0112] In particular, Figure 17 illustrates a partial schematic circuit diagram of the discrete transistor 200 that includes the harmonic reduction circuit 206 and / or the harmonic reduction circuit 204 and the transistor structure 202 arranged on the substrate 210. In aspects, the inductance of the at least one inductive element 220 and the capacitance of the at least one capacitor 222 may be selected so as to provide a bandpass implementation.

[0113] In aspects, the harmonic reduction circuit 206 and / or the harmonic reduction circuit 204 may include an implementation of the at least one inductive element 220 in series with an implementation of the at least one capacitor 222 and the harmonic reduction circuit 206 and / or the harmonic reduction circuit 204 may include another implementation of the at least one inductive element 220 in series with another implementation of the at least one capacitor 222. Additionally, the harmonic reduction circuit 206 and / or the harmonic reduction circuit 204 may include a further implementation of the at least one inductive element 220 in series with an implementation of the at least one capacitor 222. As illustrated in Figure 17, in aspects the at least one inductive element 220 may implement a spiral structural configuration of the at least one inductor metal 274.

[0114] Figure 18 illustrates a partial schematic circuit diagram of the discrete transistor according to aspects of the disclosure.

[0115] In particular, Figure 18 illustrates a partial schematic circuit diagram of the discrete transistor 200 that includes the harmonic reduction circuit 206 and / or the harmonic reduction circuit 204 and the transistor structure 202 arranged on the substrate 210. In aspects, the inductance of the at least one inductive element 220 and the capacitance of the at least one capacitor 222 may be selected so as to provide a bandpass implementation.

[0116] In aspects, the harmonic reduction circuit 206 and / or the harmonic reduction circuit 204 may include the at least one inductive element 220 in series with the at least one capacitor 222; and the harmonic reduction circuit 206 and / or the harmonic reduction circuit 204 may include another implementation of the at least one inductive element 220 in series with another implementation of the at least one capacitor 222.

[0117] Figure 19 illustrates an exemplary implementation of the discrete transistor according to aspects of the disclosure.

[0118] In particular, Figure 19 illustrates an exemplary implementation of the discrete transistor 200 with partial details and arrangements of the transistor structure 202 and the harmonic reduction circuit 206 and / or the harmonic reduction circuit 204.

[0119] In aspects, the discrete transistor 200 may include one or more bond pads 226. In aspects, the one or more bond pads 226 may connect to the input matching circuit 104, the output matching circuit 106, the RF signal input lead 140, theRF signal output lead 180, and / or the like. In aspects, the discrete transistor 200 may include one or more vias 230.

[0120] In aspects, the harmonic reduction circuit 204 and / or the harmonic reduction circuit 206 may implement the at least one capacitor 222 in a whitespace between the one or more bond pads 226 of the discrete transistor 200. In aspects, the at least one inductive element 220 may be printed in a white space available adjacent the at least one capacitor 222 and / or implementations of the one or more bond pads 226 of the discrete transistor 200.

[0121] In aspects, the harmonic reduction circuit 204 and / or the harmonic reduction circuit 206 may be implemented by absorbing the at least one inductive element 220 into a fundamental match as a bandpass structure. This may make a physical realization of the discrete transistor 200 as compact as possible. Using a bandpass match provides for higher performance.

[0122] In aspects, implementation of the discrete transistor 200 with the harmonic reduction circuit 204 and / or the harmonic reduction circuit 206 as disclosed may result in limited or no increase in chip size of the discrete transistor 200. In aspects, the harmonic reduction circuit 204 and / or the harmonic reduction circuit 206 may implement an inductor on capacitor configuration. In aspects, the harmonic reduction circuit 204 and / or the harmonic reduction circuit 206 may implement a bond on the at least one capacitor 222.

[0123] As further illustrated in Figure 19, the at least one capacitor 222 may be arranged on the substrate 210 adjacent the at least one resistor 224. Further, the at least one resistor 224 may be arranged on the substrate 210 adjacent the one or more bond pads 226 and the at least one capacitor 222. In aspects, the at least one resistor 224 may connect the one or more bond pads 226 to the at least one capacitor 222.

[0124] Additionally, the at least one inductive element 220 may be arranged on the substrate 210 adjacent the at least one capacitor 222. In aspects, the at least one inductive element 220 may be connected to the at least one capacitor 222 and the one or more vias 230.

[0125] In aspects, the harmonic reduction circuit 204 and / or the harmonic reduction circuit 206 may implement the at least one capacitor 222 buried underneath the one or more bond pads 226 of the discrete transistor 200. In aspects, the at least one inductive element 220 may be printed in a white space availablebetween implementations of the one or more bond pads 226 of the discrete transistor 200.

[0126] In aspects, the harmonic reduction circuit 204 and / or the harmonic reduction circuit 206 may be implemented by absorbing the at least one inductive element 220 into a fundamental match as a bandpass structure. This may make a physical realization of the discrete transistor 200 as compact as possible. Using a bandpass match provides for higher performance.

[0127] In aspects, implementation of the discrete transistor 200 with the harmonic reduction circuit 204 and / or the harmonic reduction circuit 206 as disclosed may result in limited or no increase in chip size of the discrete transistor 200. In aspects, the harmonic reduction circuit 204 and / or the harmonic reduction circuit 206 may implement an inductor on capacitor configuration. In aspects, the harmonic reduction circuit 204 and / or the harmonic reduction circuit 206 may implement a bond on the at least one capacitor 222.

[0128] Figure 20 illustrates an exemplary implementation of the discrete transistor according to aspects of the disclosure.

[0129] In particular, Figure 20 illustrates an exemplary implementation of the discrete transistor 200 generally consistent with Figure 19 and further illustrates an exemplary construction of the transistor structure 202 implemented as a FET.

[0130] Figure 21 illustrates an exemplary implementation of the discrete transistor according to aspects of the disclosure.

[0131] In particular, Figure 21 illustrates an exemplary implementation of the discrete transistor 200 with partial details and arrangements of the transistor structure 202 and the harmonic reduction circuit 206 and / or the harmonic reduction circuit 204.

[0132] As further illustrated in Figure 21 , the at least one capacitor 222 may be arranged on the substrate 210 adjacent the at least one resistor 224. Further, the at least one resistor 224 may be arranged on the substrate 210 adjacent the one or more bond pads 226 and the at least one capacitor 222. In aspects, the at least one resistor 224 may connect the one or more bond pads 226 to the at least one capacitor 222.

[0133] Additionally, the at least one inductive element 220 may be arranged on the substrate 210 under the at least one capacitor 222. In aspects, the at least one inductive element 220 may be connected to the at least one capacitor 222 and the one or more vias 230.

[0134] In aspects, the harmonic reduction circuit 204 and / or the harmonic reduction circuit 206 may implement the at least one capacitor 222 buried underneath the one or more bond pads 226 of the discrete transistor 200. In aspects, the at least one inductive element 220 may be printed in a white space available between implementations of the one or more bond pads 226 of the discrete transistor 200.

[0135] In aspects, the harmonic reduction circuit 204 and / or the harmonic reduction circuit 206 may be implemented by absorbing the at least one inductive element 220 into a fundamental match as a bandpass structure. This may make a physical realization of the discrete transistor 200 as compact as possible. Using a bandpass match provides for higher performance.

[0136] In aspects, implementation of the discrete transistor 200 with the harmonic reduction circuit 204 and / or the harmonic reduction circuit 206 as disclosed may result in limited or no increase in chip size of the discrete transistor 200. In aspects, the harmonic reduction circuit 204 and / or the harmonic reduction circuit 206 may implement an inductor on capacitor configuration. In aspects, the harmonic reduction circuit 204 and / or the harmonic reduction circuit 206 may implement the one or more bond pads 226 adjacent the at least one capacitor 222.

[0137] Figure 22 illustrates an exemplary implementation of the discrete transistor according to aspects of the disclosure.

[0138] In particular, Figure 22 illustrates an exemplary implementation of the discrete transistor 200 consistent with Figure 21 and further illustrates an exemplary construction of the transistor structure 202 implemented as a FET.

[0139] Figure 23 illustrates an exemplary implementation of the discrete transistor according to aspects of the disclosure.

[0140] In particular, Figure 23 illustrates an exemplary implementation of the discrete transistor 200 with partial details and arrangements of the transistor structure 202 and the harmonic reduction circuit 206 and / or the harmonic reduction circuit 204.

[0141] As further illustrated in Figure 23, the at least one capacitor 222 may be arranged on the substrate 210 adjacent the at least one resistor 224. Further, the at least one resistor 224 may be arranged on the substrate 210 adjacent the one or more bond pads 226 and the at least one capacitor 222. In aspects, the at least one resistor 224 may connect the one or more bond pads 226 to the at least one capacitor 222.

[0142] Additionally, the at least one inductive element 220 may be arranged on the substrate 210 adjacent the at least one capacitor 222. In aspects, the at least one inductive element 220 may be connected to the at least one capacitor 222 and the one or more vias 230. In aspects, the one or more bond pads 226 may be connected to the gate bus 402 through another implementation of the at least one resistor 224.

[0143] In aspects, the harmonic reduction circuit 204 and / or the harmonic reduction circuit 206 may implement the at least one capacitor 222 buried underneath the one or more bond pads 226 of the discrete transistor 200. In aspects, the at least one inductive element 220 may be printed in a white space available between implementations of the one or more bond pads 226 of the discrete transistor 200.

[0144] In aspects, the harmonic reduction circuit 204 and / or the harmonic reduction circuit 206 may be implemented by absorbing the at least one inductive element 220 into a fundamental match as a bandpass structure. This may make a physical realization of the discrete transistor 200 as compact as possible. Using a bandpass match provides for higher performance.

[0145] In aspects, implementation of the discrete transistor 200 with the harmonic reduction circuit 204 and / or the harmonic reduction circuit 206 as disclosed may result in limited or no increase in chip size of the discrete transistor 200. In aspects, the harmonic reduction circuit 204 and / or the harmonic reduction circuit 206 may implement an inductor on capacitor configuration. In aspects, the harmonic reduction circuit 204 and / or the harmonic reduction circuit 206 may implement a bond the at least one capacitor 222.

[0146] Figure 24 illustrates an exemplary implementation of the discrete transistor according to aspects of the disclosure.

[0147] In particular, Figure 24 illustrates an exemplary implementation of the discrete transistor 200 with partial details and arrangements of the transistor structure 202 and the harmonic reduction circuit 206 and / or the harmonic reduction circuit 204.

[0148] As further illustrated in Figure 24, the at least one capacitor 222 may be arranged on the substrate 210 under the one or more bond pads 226. Additionally, the at least one inductive element 220 may be arranged on the substrate 210 adjacent the at least one capacitor 222. In aspects, the at least one inductive element 220 may beconnected to the at least one capacitor 222 and the one or more vias 230. In aspects, the one or more bond pads 226 may be connected to the drain bus 420.

[0149] In aspects, the harmonic reduction circuit 204 and / or the harmonic reduction circuit 206 may implement the at least one capacitor 222 buried underneath the one or more bond pads 226 of the discrete transistor 200. In aspects, the at least one inductive element 220 may be printed in a white space available between implementations of the one or more bond pads 226 of the discrete transistor 200.

[0150] In aspects, the harmonic reduction circuit 204 and / or the harmonic reduction circuit 206 may be implemented by absorbing the at least one inductive element 220 into a fundamental match as a bandpass structure. This may make a physical realization of the discrete transistor 200 as compact as possible. Using a bandpass match provides for higher performance.

[0151] In aspects, implementation of the discrete transistor 200 with the harmonic reduction circuit 204 and / or the harmonic reduction circuit 206 as disclosed may result in limited or no increase in chip size of the discrete transistor 200. In aspects, the harmonic reduction circuit 204 and / or the harmonic reduction circuit 206 may implement an inductor on capacitor configuration. In aspects, the harmonic reduction circuit 204 and / or the harmonic reduction circuit 206 may implement a bond the at least one capacitor 222.

[0152] Figure 25 illustrates an exemplary implementation of the discrete transistor according to aspects of the disclosure.

[0153] In particular, Figure 25 illustrates an exemplary implementation of the discrete transistor 200 with partial details and arrangements of the transistor structure 202 and the harmonic reduction circuit 206 and / or the harmonic reduction circuit 204.

[0154] As further illustrated in Figure 25, the at least one capacitor 222 may be arranged on the substrate 210 buried under the one or more bond pads 226. Additionally, the at least one inductive element 220 may be arranged on the substrate 210 adjacent the at least one capacitor 222. In aspects, the at least one inductive element 220 may be connected to the at least one capacitor 222 and the one or more vias 230. In aspects, the one or more bond pads 226 may be connected to the gate bus 402.

[0155] In aspects, the harmonic reduction circuit 204 and / or the harmonic reduction circuit 206 may implement the at least one capacitor 222 buried underneath the one or more bond pads 226 of the discrete transistor 200. In aspects, the at least one inductive element 220 may be printed in a white space available between implementations of the one or more bond pads 226 of the discrete transistor 200.

[0156] In aspects, the harmonic reduction circuit 204 and / or the harmonic reduction circuit 206 may be implemented by absorbing the at least one inductive element 220 into a fundamental match as a bandpass structure. This may make a physical realization of the discrete transistor 200 as compact as possible. Using a bandpass match provides for higher performance.

[0157] In aspects, implementation of the discrete transistor 200 with the harmonic reduction circuit 204 and / or the harmonic reduction circuit 206 as disclosed may result in limited or no increase in chip size of the discrete transistor 200. In aspects, the harmonic reduction circuit 204 and / or the harmonic reduction circuit 206 may implement an inductor on capacitor configuration. In aspects, the harmonic reduction circuit 204 and / or the harmonic reduction circuit 206 may implement a bond the at least one capacitor 222.

[0158] Figure 26 and Figure 27 illustrate simulated results of the harmonic reduction circuit and / or the harmonic reduction circuit implementing bandpass topology versus the harmonic reduction circuit and / or the harmonic reduction circuit implementing low-pass topology.

[0159] In particular, Figure 26 and Figure 27 illustrate simulated results of the harmonic reduction circuit 204 and / or the harmonic reduction circuit 206 implementing bandpass topology versus the harmonic reduction circuit 204 and / or the harmonic reduction circuit 206 implementing low-pass topology. The Zh1 is the impedance looking from a gate of the discrete transistor 200 back into the input matching circuit 104. In aspects, a superior input second harmonic termination may be on capacitors side of a short. Accordingly, the bandpass topology is superior to the low-pass topology for this type of implementation of matching.

[0160] Figure 28 illustrates a perspective view of a package according to the disclosure.

[0161] Figure 29 illustrates a cross-sectional view of the package according to Figure 28.

[0162] Figure 28 and Figure 29 may include any one or more other features, components, arrangements, and the like as described herein. In particular, Figure 28 and Figure 29 illustrate that the packaged transistor device 100 may be implemented as a RF package, a RF amplifier package, a RF power amplifier package, a RF power transistor package, a RF power amplifier transistor package, and / or the like as described herein. The packaged transistor device 100 may include the input matching circuit 104, the discrete transistor 200, and the output matching circuit 106.

[0163] The packaged transistor device 100 may be implemented to include an open cavity configuration suitable for use with the discrete transistor 200 of the disclosure. In particular, the open cavity configuration may utilize an open cavity package design. In some aspects, the open cavity configuration may include a lid or other enclosure for protecting interconnects, circuit components, the discrete transistor 200, and / or the like. The packaged transistor device 100 may include a ceramic lid 412, a ceramic body 414, the RF signal input lead 140, the RF signal output lead 180, the discrete transistor 200, and / or the like.

[0164] Inside the packaged transistor device 100, the discrete transistor 200, the input matching circuit 104, and the output matching circuit 106 may be attached to the support component 102 via a die attach material 422. One or more interconnects 114 may couple the discrete transistor 200 to the input matching circuit 104, the output matching circuit 106, the RF signal output lead 180, and the RF signal input lead 140 and / or the like. The one or more interconnects 114 may be implemented as one or more wires, wire bonds, leads, clips, and / or the like.

[0165] The support component 102 may dissipate the heat generated by the discrete transistor 200, the input matching circuit 104, the output matching circuit 106, and / or the like. Further, the ceramic lid 412 may isolate and protect the discrete transistor 200, the input matching circuit 104, the output matching circuit 106, and / or the like from the outside environment. In aspects the packaged transistor device 100 may include a plurality of parallel implementations of the RF signal input lead 140, the RF signal output lead 180, the discrete transistor 200, and / or the like.

[0166] The support component 102 may be implemented as a metal submount and may be implemented as a support, a surface, a package support, apackage surface, a package support surface, a flange, a metal flange, a heat sink, a common source support, a common source surface, a common source package support, a common source package surface, a common source package support surface, a common source flange, a common source heat sink, a leadframe, a metal leadframe and / or the like. The support component 102 may include an insulating material, a dielectric material, and / or the like.

[0167] Figure 30 illustrates a perspective view of a package according to the disclosure.

[0168] In aspects, the packaged transistor device 100 may include an overmold configuration 450 that may substantially surround the RF signal input lead 140, the RF signal output lead 180, the discrete transistor 200 (obscured by the over-mold configuration 450), and / or the like, which are mounted on the support component 102 (obscured by the over-mold configuration 450). The over-mold configuration 450 may be formed of a plastic, a mold compound, a plastic compound, a polymer, a polymer compound, a plastic polymer compound, and / or the like. The over-mold configuration 450 may be injection molded, transfer molded, and / or compression molded around the RF signal input lead 140, the RF signal output lead 180, the discrete transistor 200, and / or the like, thereby providing protection for the RF signal input lead 140, the RF signal output lead 180, the discrete transistor 200, and / or the like from the outside environment.

[0169] Figure 31 shows a process of making a package according to the disclosure.

[0170] Figure 31 may include any one or more other features, components, arrangements, and the like as described herein. In particular, Figure 30 illustrates a process of forming a package 700 that relates to the packaged transistor device 100 as described herein. It should be noted that the aspects of the process of forming a package 700 may be performed in a different order consistent with the aspects described herein. Additionally, it should be noted that portions of the process of forming a package 700 may be performed in a different order consistent with the aspects described herein. Moreover, the process of forming a package 700 may be modified to have more or fewer processes consistent with the various aspects disclosed herein.

[0171] Initially, the process of forming a package 700 may include a process of forming the support 702. More specifically, the support component 102 may be constructed, configured, and / or arranged as described herein. In one aspect, the process of forming the support 702 may include forming the support component 102 as a printed circuit board, a MMIC, support, a surface, a package support, a package surface, a package support surface, a flange, a heat sink, a common source heat sink, and / or the like.

[0172] The process of forming a package 700 may include the process of forming a discrete transistor 704. More specifically, the process of forming a discrete transistor 704 may include forming the discrete transistor 200 as described herein. In aspects, the process of forming a discrete transistor 704 may include forming the discrete transistor 200 with the harmonic reduction circuit 204 on the substrate 210 as described herein, forming the discrete transistor 200 with the harmonic reduction circuit 206 on the substrate 210 as described herein, forming the discrete transistor 200 with the at least one inductive element 220 on the substrate 210 as described herein, forming the discrete transistor 200 with the at least one capacitor 222 on the substrate 210 as described herein, forming the discrete transistor 200 with the at least one resistor 224 on the substrate 210 as described herein, and / or the like.

[0173] Thereafter, the process of forming a discrete transistor 704 may further include attaching the discrete transistor 200 to the support component 102. In this regard, the discrete transistor 200 may be mounted on the upper surface of the support component 102 by an adhesive, soldering, sintering, eutectic bonding, ultrasonically welding, and / or the like as described herein. Additionally, the input matching circuit 104 and / or the output matching circuit 106 may be mounted on the upper surface of the support component 102 by an adhesive, soldering, sintering, eutectic bonding, ultrasonically welding, and / or the like as described herein.

[0174] The process of forming a package 700 may include a process of forming the one or more interconnects 706. More specifically, the one or more interconnects 114 may be constructed, configured, and / or arranged as described herein. In one aspect, the process of forming the one or more interconnects 706 may include forming the one or more interconnects 114 by forming one or more wires, leads, vias, edge platings, circuit traces, tracks, and / or the like. In one aspect, the process of forming the one or more interconnects 706 may include connecting the one or moreinterconnects 706 by an adhesive, soldering, sintering, eutectic bonding, ultrasonic welding, a clip component, and / or the like as described herein.

[0175] The process of forming a package 700 may include a process of enclosing the package 708. More specifically, the packaged transistor device 100 may be constructed, configured, and / or arranged as described herein. In one aspect, the process of enclosing the package 708 may include forming an open cavity configuration, an over-mold configuration, and / or the like.

[0176] In one aspect, the process of forming a package 700 may include processing utilizing a surface mount technology (SMT) line. A surface mount technology (SMT) line may utilize numerous processes including solder printing, component placement, solder reflow, and / or the like. Additional processes may include a flux cleaning step to remove all flux residues, wire bonding, dicing, mounting to dicing tape, dicing, either mechanical sawing or laser cutting, or a combination of both, and component testing. Additionally, the discrete transistor 200 may be arranged on dicing tape that may then serve as input for the Die Attach equipment.

[0177] The packaged transistor device 100 may be implemented as an RF package and the discrete transistor 200 may be implemented as a radio frequency device that may include, connect, support, or the like a transmitter, transmitter functions, a receiver, receiver functions, a transceiver, transceiver functions, matching network functions, harmonic termination circuitry, and the like. The discrete transistor 200 may be implemented as a radio frequency device may be configured to, may support, or the like transmitting a radio wave and modulating that wave to carry data with allowable transmitter power output, harmonics, and / or band edge requirements. The discrete transistor 200 device may be configured to, may support, or the like receiving a radio wave and demodulating the radio wave. The discrete transistor 200 implemented as a radio frequency device may be configured to, may support, or the like transmitting a radio wave and modulating that wave to carry data with allowable transmitter power output, harmonics, and / or band edge requirements; and may be configured to, may support, or the like receiving a radio wave and demodulating the radio wave. The packaged transistor device 100 may be implemented in any number of different applications. In this regard, the packaged transistor device 100 may be implemented in applications implementing high video bandwidth power amplifier transistors, a single path radio frequency power transistor, a single stage radiofrequency power transistor, a multipath radio frequency power transistor, a Doherty configuration a multistage radio frequency power transistor, a GaN based radio frequency power amplifier module, a laterally-diffused metal-oxide semiconductor (LDMOS) device, a LDMOS radio frequency power amplifier module, a radio frequency power device, an ultra-wideband device, a GaN based device, a Metal Semiconductor Field-Effect Transistor (MESFET), a Metal Oxide Field Effect Transistor (MOSFET), a Junction Field Effect Transistor (JFET), a Bipolar Junction Transistor (BJT), an Insulated Gate Bipolar Transistor (IGBT), a high-electron-mobility transistor (HEMT), a Wide Band Gap (WBG) semiconductor, a power module, a gate driver, a component such as a General-Purpose Broadband component, a Telecom component, a L-Band component, a S-Band component, a X-Band component, a C- Band component, a Ku-Band component, a Satellite Communications component, and / or the like. The packaged transistor device 100 may be implemented as a power package. The packaged transistor device 100 may be implemented as a power package and may implement applications and components as described herein.

[0178] The packaged transistor device 100 may be implemented as a radio frequency package. The packaged transistor device 100 may be implemented as a radio frequency package and may implement applications and components as described herein. The packaged transistor device 100 implemented as a radio frequency package may include, connect, support, or the like a transmitter, transmitter functions, a receiver, receiver functions, a transceiver, transceiver functions, and the like. The packaged transistor device 100 implemented as a radio frequency package may be configured to, may support, or the like transmitting a radio wave and modulating that wave to carry data with allowable transmitter power output, harmonics, and / or band edge requirements. The packaged transistor device 100 implemented as a radio frequency package may be configured to, may support, or the like receiving a radio wave and demodulating the radio wave. The packaged transistor device 100 implemented as a radio frequency package may be configured to, may support, or the like transmitting a radio wave and modulating out that wave to carry data with allowable transmitter power output, harmonics, and / or band edge requirements; and may be configured to, may support, or the like receiving a radio wave and demodulating the radio wave.

[0179] The packaged transistor device 100 implementing the discrete transistor 200 having the harmonic reduction circuit 204 and / or the harmonic reduction circuit 206 within the discrete transistor 200 may be useful in a wide range of applications in which linearity is important. For example, a packaged power transistor according to embodiments of the invention may have application in systems, such as LTE, NR, 5G and future 6G systems. In general, embodiments of the invention may be useful in any application in which linear performance is desired from a power transistor.

[0180] Accordingly, the disclosure has set forth radio frequency (RF) power transistor configurations having greater linearity during high-frequency operation is needed.

[0181] One EXAMPLE: a packaged transistor device includes an RF signal input lead. The packaged transistor device in addition includes an RF signal output lead. The packaged transistor device moreover includes a discrete transistor comprising a transistor structure arranged and / or formed on a substrate. The packaged transistor device also includes at least one harmonic reduction circuit arranged and / or formed on the substrate of the discrete transistor.

[0182] The above-noted EXAMPLE may further include any one or a combination of more than one of the following EXAMPLES: The packaged transistor device of the above-noted EXAMPLE where the discrete transistor is configured to connect the at least one harmonic reduction circuit to a control electrode of the transistor structure. The packaged transistor device of the above-noted EXAMPLE where the at least one harmonic reduction circuit is coupled to an output electrode of the transistor structure. The packaged transistor device of the above-noted EXAMPLE where the substrate comprises silicon carbide (SiC). The packaged transistor device of the above-noted EXAMPLE where the discrete transistor is implemented as a gallium nitride (GaN) silicon carbide (SiC) transistor. The packaged transistor device of the above-noted EXAMPLE includes an input matching circuit and / or an output matching circuit. The packaged transistor device of the above-noted EXAMPLE where a structure of the at least one harmonic reduction circuit is arranged at least partially on the substrate, is arranged at least partially on the transistor structure, and / or is arranged at least partially on the substrate and the transistor structure. The packaged transistor device of the above-noted EXAMPLE where a structure of the transistor structure is arranged at least partially on thesubstrate and / or is arranged at least partially on the at least one harmonic reduction circuit. The packaged transistor device of the above-noted EXAMPLE where the at least one harmonic reduction circuit comprises at least one inductive element, at least one capacitor, and / or at least one resistor. The packaged transistor device of the above-noted EXAMPLE where the at least one capacitor comprises at least one dielectric layer, at least one capacitor top metal, at least one capacitor bottom metal; and where the at least one capacitor forms a capacitor with the at least one capacitor top metal and the at least one capacitor bottom metal having the at least one dielectric layer therebetween. The packaged transistor device of the above-noted EXAMPLE where a structure of the at least one capacitor is arranged at least partially on the substrate, is arranged at least partially on the transistor structure, and / or is arranged at least partially on the substrate and the transistor structure. The packaged transistor device of the above-noted EXAMPLE where the at least one inductive element comprises at least one inductor metal; and where the at least one inductive element forms an inductor by arrangement of the at least one inductor metal on the substrate of the discrete transistor. The packaged transistor device of the above-noted EXAMPLE where a structure of the at least one inductive element is arranged at least partially on the substrate, is arranged at least partially on the transistor structure, and / or is arranged at least partially on the substrate and the transistor structure. The packaged transistor device of the above-noted EXAMPLE where a structure of the at least one inductive element is arranged at least partially on the substrate, is arranged at least partially on the transistor structure, is arranged at least partially on the substrate and the transistor structure, and / or is arranged at least partially on the at least one capacitor. The packaged transistor device of the above-noted EXAMPLE where an inductance of the at least one inductive element and a capacitance of the at least one capacitor is selected to provide a bandpass implementation. The packaged transistor device of the above-noted EXAMPLE where an inductance of the at least one inductive element and a capacitance of the at least one capacitor is selected to provide a short circuit and / or low impedance path to ground for signals at a harmonic frequency. The packaged transistor device of the above-noted EXAMPLE where the at least one harmonic reduction circuit comprises an implementation of the at least one inductive element in series with an implementation of the at least one capacitor and the at least one harmonic reductioncircuit. The packaged transistor device of the above-noted EXAMPLE where the at least one harmonic reduction circuit comprises the at least one inductive element in series with the at least one capacitor; and where the at least one harmonic reduction circuit comprises another implementation of the at least one inductive element in series with another implementation of the at least one capacitor. The packaged transistor device of the above-noted EXAMPLE where the at least one capacitor is buried underneath one or more bond pads of the discrete transistor. The packaged transistor device of the above-noted EXAMPLE where the at least one inductive element is between implementations of one or more bond pads of the discrete transistor. The packaged transistor device of the above-noted EXAMPLE where the at least one inductive element is printed between implementations of one or more bond pads of the discrete transistor. The packaged transistor device of the abovenoted EXAMPLE where the at least one inductive element is arranged on the substrate adjacent the at least one capacitor. The packaged transistor device of the above-noted EXAMPLE where the at least one inductive element is connected to the at least one capacitor and one or more vias. The packaged transistor device of the above-noted EXAMPLE where the at least one harmonic reduction circuit is implemented by absorbing the at least one inductive element into a fundamental match as a bandpass structure. The packaged transistor device of the above-noted EXAMPLE where the discrete transistor comprises one or more bond pads; and where the one or more bond pads connect to an input matching circuit, an output matching circuit, the RF signal input lead, and / or the RF signal output lead. The packaged transistor device of the above-noted EXAMPLE where at least one capacitor is arranged on the substrate and adjacent at least one resistor; and where the at least one resistor is arranged on the substrate and adjacent one or more bond pads and the at least one capacitor. The packaged transistor device of the abovenoted EXAMPLE where one or more bond pads are connected to a drain bus of the transistor structure. The packaged transistor device of the above-noted EXAMPLE where one or more bond pads are connected to a gate bus of the transistor structure. The packaged transistor device of the above-noted EXAMPLE where the at least one harmonic reduction circuit comprises two implementations of the at least one harmonic reduction circuit. The packaged transistor device of the above-noted EXAMPLE includes: an open cavity configuration; a support component; and one ormore interconnects coupled to the discrete transistor, an input matching circuit, an output matching circuit, the RF signal output lead, and / or the RF signal input lead. The packaged transistor device of the above-noted EXAMPLE includes: an overmold configuration; a support component; and one or more interconnects coupled to the discrete transistor, an input matching circuit, an output matching circuit, the RF signal output lead, and / or the RF signal input lead.

[0183] One EXAMPLE: a process includes providing an RF signal input lead. The process in addition includes providing an RF signal output lead. The process moreover includes forming and arranging a discrete transistor comprising a transistor structure on a substrate. The process also includes forming and arranging at least one harmonic reduction circuit on the substrate of the discrete transistor.

[0184] The above-noted EXAMPLE may further include any one or a combination of more than one of the following EXAMPLES: The process of the above-noted EXAMPLE where the discrete transistor is configured to connect the at least one harmonic reduction circuit to a control electrode of the transistor structure. The process of the above-noted EXAMPLE where the at least one harmonic reduction circuit is coupled to an output electrode of the transistor structure. The process of the above-noted EXAMPLE where the substrate comprises silicon carbide (SiC). The process of the above-noted EXAMPLE where the discrete transistor is implemented as a gallium nitride (GaN) silicon carbide (SiC) transistor. The process of the above-noted EXAMPLE includes an input matching circuit and / or an output matching circuit. The process of the above-noted EXAMPLE where a structure of the at least one harmonic reduction circuit is arranged at least partially on the substrate, is arranged at least partially on the transistor structure, and / or is arranged at least partially on the substrate and the transistor structure. The process of the above-noted EXAMPLE where a structure of the transistor structure is arranged at least partially on the substrate and / or is arranged at least partially on the at least one harmonic reduction circuit. The process of the above-noted EXAMPLE where the at least one harmonic reduction circuit comprises at least one inductive element, at least one capacitor, and / or at least one resistor. The packaged transistor device of the above-noted EXAMPLE where the at least one capacitor comprises at least one dielectric layer, at least one capacitor top metal, at least one capacitor bottom metal; and where the at least one capacitor forms a capacitor with the atleast one capacitor top metal and the at least one capacitor bottom metal having the at least one dielectric layer therebetween. The packaged transistor device of the above-noted EXAMPLE where a structure of the at least one capacitor is arranged at least partially on the substrate, is arranged at least partially on the transistor structure, and / or is arranged at least partially on the substrate and the transistor structure. The packaged transistor device of the above-noted EXAMPLE where the at least one inductive element comprises at least one inductor metal; and where the at least one inductive element forms an inductor by arrangement of the at least one inductor metal on the substrate of the discrete transistor. The packaged transistor device of the above-noted EXAMPLE where a structure of the at least one inductive element is arranged at least partially on the substrate, is arranged at least partially on the transistor structure, and / or is arranged at least partially on the substrate and the transistor structure. The packaged transistor device of the above-noted EXAMPLE where a structure of the at least one inductive element is arranged at least partially on the substrate, is arranged at least partially on the transistor structure, is arranged at least partially on the substrate and the transistor structure, and / or is arranged at least partially on the at least one capacitor. The packaged transistor device of the above-noted EXAMPLE where an inductance of the at least one inductive element and a capacitance of the at least one capacitor is selected to provide a bandpass implementation. The packaged transistor device of the abovenoted EXAMPLE where an inductance of the at least one inductive element and a capacitance of the at least one capacitor is selected to provide a short circuit and / or low impedance path to ground for signals at a harmonic frequency. The packaged transistor device of the above-noted EXAMPLE where the at least one harmonic reduction circuit comprises an implementation of the at least one inductive element in series with an implementation of the at least one capacitor and the at least one harmonic reduction circuit. The packaged transistor device of the above-noted EXAMPLE where the at least one harmonic reduction circuit comprises the at least one inductive element in series with the at least one capacitor; and where the at least one harmonic reduction circuit comprises another implementation of the at least one inductive element in series with another implementation of the at least one capacitor. The packaged transistor device of the above-noted EXAMPLE where the at least one capacitor is buried underneath one or more bond pads of the discretetransistor. The packaged transistor device of the above-noted EXAMPLE where the at least one inductive element is between implementations of one or more bond pads of the discrete transistor. The packaged transistor device of the above-noted EXAMPLE where the at least one inductive element is printed between implementations of one or more bond pads of the discrete transistor. The packaged transistor device of the above-noted EXAMPLE where the at least one inductive element is arranged on the substrate adjacent the at least one capacitor. The packaged transistor device of the above-noted EXAMPLE where the at least one inductive element is connected to the at least one capacitor and one or more vias. The packaged transistor device of the above-noted EXAMPLE where the at least one harmonic reduction circuit is implemented by absorbing the at least one inductive element into a fundamental match as a bandpass structure. The process of the above-noted EXAMPLE where the discrete transistor comprises one or more bond pads; and where the one or more bond pads connect to an input matching circuit, an output matching circuit, the RF signal input lead, and / or the RF signal output lead. The process of the above-noted EXAMPLE where at least one capacitor is arranged on the substrate and adjacent at least one resistor; and where the at least one resistor is arranged on the substrate and adjacent one or more bond pads and the at least one capacitor. The process of the above-noted EXAMPLE where one or more bond pads are connected to a drain bus of the transistor structure. The process of the above-noted EXAMPLE where one or more bond pads are connected to a gate bus of the transistor structure. The process of the above-noted EXAMPLE where the at least one harmonic reduction circuit comprises two implementations of the at least one harmonic reduction circuit. The process of the above-noted EXAMPLE includes: providing a support component; coupling one or more interconnects to the discrete transistor, an input matching circuit, an output matching circuit, the RF signal output lead, and / or the RF signal input lead; and forming an open cavity configuration. The process of the above-noted EXAMPLE includes: providing a support component; coupling one or more interconnects to the discrete transistor, an input matching circuit, an output matching circuit, the RF signal output lead, and / or the RF signal input lead; and forming an over-mold configuration.

[0185] One EXAMPLE: a packaged transistor device includes an RF signal input lead. The packaged transistor device in addition includes an RF signal outputlead. The packaged transistor device moreover includes a discrete transistor comprising a transistor structure arranged and / or formed on a substrate. The packaged transistor device also includes at least one harmonic reduction circuit arranged and / or formed on the substrate of the discrete transistor. The packaged transistor device further includes where a structure of the at least one harmonic reduction circuit is arranged at least partially on the substrate, is arranged at least partially on the transistor structure, and / or is arranged at least partially on the substrate and the transistor structure.

[0186] The above-noted EXAMPLE may further include any one or a combination of more than one of the following EXAMPLES: The packaged transistor device of the above-noted EXAMPLE where the discrete transistor is configured to connect the at least one harmonic reduction circuit to a control electrode of the transistor structure. The packaged transistor device of the above-noted EXAMPLE where the at least one harmonic reduction circuit is coupled to an output electrode of the transistor structure. The packaged transistor device of the above-noted EXAMPLE where the substrate comprises silicon carbide (SiC). The packaged transistor device of the above-noted EXAMPLE where the discrete transistor is implemented as a gallium nitride (GaN) silicon carbide (SiC) transistor. The packaged transistor device of the above-noted EXAMPLE includes an input matching circuit and / or an output matching circuit. The packaged transistor device of the above-noted EXAMPLE where a structure of the transistor structure is arranged at least partially on the substrate and / or is arranged at least partially on the at least one harmonic reduction circuit. The packaged transistor device of the above-noted EXAMPLE where the at least one harmonic reduction circuit comprises at least one inductive element, at least one capacitor, and / or at least one resistor. The packaged transistor device of the above-noted EXAMPLE where the at least one capacitor comprises at least one dielectric layer, at least one capacitor top metal, at least one capacitor bottom metal; and where the at least one capacitor forms a capacitor with the at least one capacitor top metal and the at least one capacitor bottom metal having the at least one dielectric layer therebetween. The packaged transistor device of the above-noted EXAMPLE where a structure of the at least one capacitor is arranged at least partially on the substrate, is arranged at least partially on the transistor structure, and / or is arranged at least partially on the substrate and thetransistor structure. The packaged transistor device of the above-noted EXAMPLE where the at least one inductive element comprises at least one inductor metal; and where the at least one inductive element forms an inductor by arrangement of the at least one inductor metal on the substrate of the discrete transistor. The packaged transistor device of the above-noted EXAMPLE where a structure of the at least one inductive element is arranged at least partially on the substrate, is arranged at least partially on the transistor structure, and / or is arranged at least partially on the substrate and the transistor structure. The packaged transistor device of the abovenoted EXAMPLE where a structure of the at least one inductive element is arranged at least partially on the substrate, is arranged at least partially on the transistor structure, is arranged at least partially on the substrate and the transistor structure, and / or is arranged at least partially on the at least one capacitor. The packaged transistor device of the above-noted EXAMPLE where an inductance of the at least one inductive element and a capacitance of the at least one capacitor is selected to provide a bandpass implementation. The packaged transistor device of the abovenoted EXAMPLE where an inductance of the at least one inductive element and a capacitance of the at least one capacitor is selected to provide a short circuit and / or low impedance path to ground for signals at a harmonic frequency. The packaged transistor device of the above-noted EXAMPLE where the at least one harmonic reduction circuit comprises an implementation of the at least one inductive element in series with an implementation of the at least one capacitor and the at least one harmonic reduction circuit. The packaged transistor device of the above-noted EXAMPLE where the at least one harmonic reduction circuit comprises the at least one inductive element in series with the at least one capacitor; and where the at least one harmonic reduction circuit comprises another implementation of the at least one inductive element in series with another implementation of the at least one capacitor. The packaged transistor device of the above-noted EXAMPLE where the at least one capacitor is buried underneath one or more bond pads of the discrete transistor. The packaged transistor device of the above-noted EXAMPLE where the at least one inductive element is between implementations of one or more bond pads of the discrete transistor. The packaged transistor device of the above-noted EXAMPLE where the at least one inductive element is printed between implementations of one or more bond pads of the discrete transistor. The packagedtransistor device of the above-noted EXAMPLE where the at least one inductive element is arranged on the substrate adjacent the at least one capacitor. The packaged transistor device of the above-noted EXAMPLE where the at least one inductive element is connected to the at least one capacitor and one or more vias. The packaged transistor device of the above-noted EXAMPLE where the at least one harmonic reduction circuit is implemented by absorbing the at least one inductive element into a fundamental match as a bandpass structure. The packaged transistor device of the above-noted EXAMPLE where the discrete transistor comprises one or more bond pads; and where the one or more bond pads connect to an input matching circuit, an output matching circuit, the RF signal input lead, and / or the RF signal output lead. The packaged transistor device of the above-noted EXAMPLE where at least one capacitor is arranged on the substrate and adjacent at least one resistor; and where the at least one resistor is arranged on the substrate and adjacent one or more bond pads and the at least one capacitor. The packaged transistor device of the above-noted EXAMPLE where one or more bond pads are connected to a drain bus of the transistor structure. The packaged transistor device of the above-noted EXAMPLE where one or more bond pads are connected to a gate bus of the transistor structure. The packaged transistor device of the abovenoted EXAMPLE where the at least one harmonic reduction circuit comprises two implementations of the at least one harmonic reduction circuit. The packaged transistor device of the above-noted EXAMPLE includes: an open cavity configuration; a support component; and one or more interconnects coupled to the discrete transistor, an input matching circuit, an output matching circuit, the RF signal output lead, and / or the RF signal input lead. The packaged transistor device of the above-noted EXAMPLE includes: an over-mold configuration; a support component; and one or more interconnects coupled to the discrete transistor, an input matching circuit, an output matching circuit, the RF signal output lead, and / or the RF signal input lead.

[0187] One EXAMPLE: a process includes providing an RF signal input lead. The process in addition includes providing an RF signal output lead. The process moreover includes forming and arranging a discrete transistor comprising a transistor structure on a substrate. The process also includes forming and arranging at least one harmonic reduction circuit on the substrate of the discrete transistor. Theprocess further includes where a structure of the at least one harmonic reduction circuit is arranged at least partially on the substrate, is arranged at least partially on the transistor structure, and / or is arranged at least partially on the substrate and the transistor structure.

[0188] The above-noted EXAMPLE may further include any one or a combination more than one of the following EXAMPLES: The process of the abovenoted EXAMPLE where the discrete transistor is configured to connect the at least one harmonic reduction circuit to a control electrode of the transistor structure. The process of the above-noted EXAMPLE where the at least one harmonic reduction circuit is coupled to an output electrode of the transistor structure. The process of the above-noted EXAMPLE where the substrate comprises silicon carbide (SiC). The process of the above-noted EXAMPLE where the discrete transistor is implemented as a gallium nitride (GaN) silicon carbide (SiC) transistor. The process of the abovenoted EXAMPLE includes an input matching circuit and / or an output matching circuit. The process of the above-noted EXAMPLE where a structure of the transistor structure is arranged at least partially on the substrate and / or is arranged at least partially on the at least one harmonic reduction circuit. The process of the abovenoted EXAMPLE where the at least one harmonic reduction circuit comprises at least one inductive element, at least one capacitor, and / or at least one resistor. The packaged transistor device of the above-noted EXAMPLE where the at least one capacitor comprises at least one dielectric layer, at least one capacitor top metal, at least one capacitor bottom metal; and where the at least one capacitor forms a capacitor with the at least one capacitor top metal and the at least one capacitor bottom metal having the at least one dielectric layer therebetween. The packaged transistor device of the above-noted EXAMPLE where a structure of the at least one capacitor is arranged at least partially on the substrate, is arranged at least partially on the transistor structure, and / or is arranged at least partially on the substrate and the transistor structure. The packaged transistor device of the above-noted EXAMPLE where the at least one inductive element comprises at least one inductor metal; and where the at least one inductive element forms an inductor by arrangement of the at least one inductor metal on the substrate of the discrete transistor. The packaged transistor device of the above-noted EXAMPLE where a structure of the at least one inductive element is arranged at least partially on thesubstrate, is arranged at least partially on the transistor structure, and / or is arranged at least partially on the substrate and the transistor structure. The packaged transistor device of the above-noted EXAMPLE where a structure of the at least one inductive element is arranged at least partially on the substrate, is arranged at least partially on the transistor structure, is arranged at least partially on the substrate and the transistor structure, and / or is arranged at least partially on the at least one capacitor. The packaged transistor device of the above-noted EXAMPLE where an inductance of the at least one inductive element and a capacitance of the at least one capacitor is selected to provide a bandpass implementation. The packaged transistor device of the above-noted EXAMPLE where an inductance of the at least one inductive element and a capacitance of the at least one capacitor is selected to provide a short circuit and / or low impedance path to ground for signals at a harmonic frequency. The packaged transistor device of the above-noted EXAMPLE where the at least one harmonic reduction circuit comprises an implementation of the at least one inductive element in series with an implementation of the at least one capacitor and the at least one harmonic reduction circuit. The packaged transistor device of the above-noted EXAMPLE where the at least one harmonic reduction circuit comprises the at least one inductive element in series with the at least one capacitor; and where the at least one harmonic reduction circuit comprises another implementation of the at least one inductive element in series with another implementation of the at least one capacitor. The packaged transistor device of the above-noted EXAMPLE where the at least one capacitor is buried underneath one or more bond pads of the discrete transistor. The packaged transistor device of the above-noted EXAMPLE where the at least one inductive element is between implementations of one or more bond pads of the discrete transistor. The packaged transistor device of the above-noted EXAMPLE where the at least one inductive element is printed between implementations of one or more bond pads of the discrete transistor. The packaged transistor device of the above-noted EXAMPLE where the at least one inductive element is arranged on the substrate adjacent the at least one capacitor. The packaged transistor device of the above-noted EXAMPLE where the at least one inductive element is connected to the at least one capacitor and one or more vias. The packaged transistor device of the above-noted EXAMPLE where the at least one harmonic reduction circuit is implemented by absorbing the atleast one inductive element into a fundamental match as a bandpass structure. The process of the above-noted EXAMPLE where the discrete transistor comprises one or more bond pads; and where the one or more bond pads connect to an input matching circuit, an output matching circuit, the RF signal input lead, and / or the RF signal output lead. The process of the above-noted EXAMPLE where at least one capacitor is arranged on the substrate and adjacent at least one resistor; and where the at least one resistor is arranged on the substrate and adjacent one or more bond pads and the at least one capacitor. The process of the above-noted EXAMPLE where one or more bond pads are connected to a drain bus of the transistor structure. The process of the above-noted EXAMPLE where one or more bond pads are connected to a gate bus of the transistor structure. The process of the abovenoted EXAMPLE where the at least one harmonic reduction circuit comprises two implementations of the at least one harmonic reduction circuit. The process of the above-noted EXAMPLE includes: providing a support component; coupling one or more interconnects to the discrete transistor, an input matching circuit, an output matching circuit, the RF signal output lead, and / or the RF signal input lead; and forming an open cavity configuration. The process of the above-noted EXAMPLE includes: providing a support component; coupling one or more interconnects to the discrete transistor, an input matching circuit, an output matching circuit, the RF signal output lead, and / or the RF signal input lead; and forming an over-mold configuration.

[0189] The adhesive of the disclosure may be utilized in an adhesive bonding process that may include applying an intermediate layer to connect surfaces to be connected. The adhesive may be organic or inorganic; and the adhesive may be deposited on one or both surfaces of the surface to be connected. The adhesive may be utilized in an adhesive bonding process that may include applying adhesive material with a particular coating thickness, at a particular bonding temperature, for a particular processing time while in an environment that may include applying a particular tool pressure. In one aspect, the adhesive may be a conductive adhesive, an epoxy-based adhesive, a conductive epoxy-based adhesive, and / or the like.

[0190] The solder of the disclosure may be utilized to form a solder interface that may include solder and / or be formed from solder. The solder may be any fusible metal alloy that may be used to form a bond between surfaces to be connected. Thesolder may be a lead-free solder, a lead solder, a eutectic solder, or the like. The lead- free solder may contain tin, copper, silver, bismuth, indium, zinc, antimony, traces of other metals, and / or the like. The lead solder may contain lead, other metals such as tin, silver, and / or the like. The solder may further include flux as needed.

[0191] The sintering of the disclosure may utilize a process of compacting and forming a conductive mass of material by heat and / or pressure. The sintering process may operate without melting the material to the point of liquefaction. The sintering process may include sintering of metallic nano or hybrid powders in pastes or epoxies. The sintering process may include sintering in a vacuum. The sintering process may include sintering with the use of a protective gas.

[0192] The eutectic bonding of the disclosure may utilize a eutectic soldering process that may form a eutectic system. The eutectic system may be used between surfaces to be connected. The eutectic bonding may utilize metals that may be alloys and / or intermetallics that transition from solid to liquid state, or from liquid to solid state, at a specific composition and temperature. The eutectic alloys may be deposited by sputtering, evaporation, electroplating, and / or the like.

[0193] The ultrasonically welding of the disclosure may utilize a process whereby high-frequency ultrasonic acoustic vibrations are locally applied to components being held together under pressure. The ultrasonically welding may create a solid-state weld between surfaces to be connected. In one aspect, the ultrasonically welding may include applying a sonicated force.

[0194] It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the disclosure. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0195] It will be understood that when an element such as a layer, region, or substrate is referred to as being "on" or extending "onto" another element, it can be directly on or extend directly onto another element or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or extending "directly onto" another element, there are no intervening elements present.Likewise, it will be understood that when an element such as a layer, region, or substrate is referred to as being "over" or extending "over" another element, it can be directly over or extend directly over another element or intervening elements may also be present. In contrast, when an element is referred to as being "directly over" or extending "directly over" another element, there are no intervening elements present. It will also be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to another element or intervening elements may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present.

[0196] Relative terms such as "below" or "above" or "upper" or "lower" or "horizontal" or "vertical" may be used herein to describe a relationship of one element, layer, or region to another element, layer, or region as illustrated in the Figures. It will be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures.

[0197] The terminology used herein is for the purpose of describing particular aspects only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises," "comprising," "includes," and / or "including" when used herein specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0198] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0199] The many features and advantages of the disclosure are apparent from the detailed specification, and, thus, it is intended by the appended claims to coverall such features and advantages of the disclosure which fall within the true spirit and scope of the disclosure. Further, since numerous modifications and variations will readily occur to those skilled in the art, it is not desired to limit the disclosure to the exact construction and operation illustrated and described, and, accordingly, all suitable modifications and equivalents may be resorted to that fall within the scope of the disclosure.

Claims

CLAIMS:1 . A packaged transistor device comprising: an RF signal input lead; an RF signal output lead; a discrete transistor comprising a transistor structure arranged and / or formed on a substrate; and at least one harmonic reduction circuit arranged and / or formed on the substrate of the discrete transistor.

2. The packaged transistor device according to claim 1 , wherein the discrete transistor is configured to connect the at least one harmonic reduction circuit to a control electrode of the transistor structure.

3. The packaged transistor device according to claim 1 , wherein the at least one harmonic reduction circuit is coupled to an output electrode of the transistor structure.

4. The packaged transistor device according to claim 1 , wherein the substrate comprises silicon carbide (SiC).

5. The packaged transistor device according to claim 1 , wherein the discrete transistor is implemented as a gallium nitride (GaN) silicon carbide (SiC) transistor.

6. The packaged transistor device according to claim 1 , further comprising an input matching circuit and / or an output matching circuit.

7. The packaged transistor device according to claim 1 , wherein a structure of the at least one harmonic reduction circuit is arranged at least partially on the substrate, is arranged at least partially on the transistor structure, and / or is arranged at least partially on the substrate and the transistor structure.

8. The packaged transistor device according to claim 1 , wherein a structure of the transistor structure is arranged at least partially on the substrate and / or is arranged at least partially on the at least one harmonic reduction circuit.

9. The packaged transistor device according to claim 1 , wherein the at least one harmonic reduction circuit comprises at least one inductive element, at least one capacitor, and / or at least one resistor.

10. The packaged transistor device according to claim 9, wherein the at least one capacitor comprises at least one dielectric layer, at least one capacitor top metal, at least one capacitor bottom metal; and wherein the at least one capacitor forms a capacitor with the at least one capacitor top metal and the at least one capacitor bottom metal having the at least one dielectric layer therebetween.11 . The packaged transistor device according to claim 9, wherein a structure of the at least one capacitor is arranged at least partially on the substrate, is arranged at least partially on the transistor structure, and / or is arranged at least partially on the substrate and the transistor structure.

12. The packaged transistor device according to claim 9, wherein the at least one inductive element comprises at least one inductor metal; and wherein the at least one inductive element forms an inductor by arrangement of the at least one inductor metal on the substrate of the discrete transistor.

13. The packaged transistor device according to claim 9, wherein a structure of the at least one inductive element comprises at least one inductor metal arranged at least partially on the substrate, is arranged at least partially on the transistor structure, and / or is arranged at least partially on the substrate and the transistor structure.

14. The packaged transistor device according to claim 9, wherein a structure of the at least one inductive element is arranged at least partially on the substrate, is arranged at least partially on the transistor structure, is arranged at least partially on the substrate and the transistor structure, and / or is arranged at least partially on the at least one capacitor.

15. The packaged transistor device according to claim 9, wherein an inductance of the at least one inductive element and a capacitance of the at least one capacitor is selected to provide a bandpass implementation.

16. The packaged transistor device according to claim 9, wherein an inductance of the at least one inductive element and a capacitance of the at least one capacitor is selected to provide a short circuit and / or low impedance path to ground for signals at a harmonic frequency.

17. The packaged transistor device according to claim 9, wherein the at least one harmonic reduction circuit comprises an implementation of the at least one inductive element in series with an implementation of the at least one capacitor and the at least one harmonic reduction circuit.

18. The packaged transistor device according to claim 9, wherein the at least one harmonic reduction circuit comprises the at least one inductive element in series with the at least one capacitor; and wherein the at least one harmonic reduction circuit comprises another implementation of the at least one inductive element in series with another implementation of the at least one capacitor.

19. The packaged transistor device according to claim 9, wherein the at least one capacitor is buried underneath one or more bond pads of the discrete transistor.

20. The packaged transistor device according to claim 9,wherein the at least one capacitor is buried underneath one or more bond pads of the discrete transistor; and wherein the at least one inductive element is arranged in a whitespace of the transistor structure.21 . The packaged transistor device according to claim 9, wherein the at least one capacitor is arranged in a whitespace of the transistor structure; and wherein the at least one inductive element is arranged in a whitespace of the transistor structure.

22. The packaged transistor device according to claim 9, wherein the at least one inductive element is between implementations of one or more bond pads of the discrete transistor.

23. The packaged transistor device according to claim 9, wherein the at least one inductive element is printed in a whitespace between implementations of one or more bond pads of the discrete transistor.

24. The packaged transistor device according to claim 9, wherein the at least one inductive element is printed between implementations of one or more bond pads of the discrete transistor.

25. The packaged transistor device according to claim 9, wherein the at least one inductive element is arranged on the substrate adjacent the at least one capacitor.

26. The packaged transistor device according to claim 9, wherein the at least one inductive element is connected to the at least one capacitor and one or more vias.

27. The packaged transistor device according to claim 9, wherein the at least one harmonic reduction circuit is implemented by absorbing the at least one inductive element into a fundamental match as a bandpass structure.

28. The packaged transistor device according to claim 1 , wherein the discrete transistor comprises one or more bond pads; and wherein the one or more bond pads connect to an input matching circuit, an output matching circuit, the RF signal input lead, and / or the RF signal output lead.

29. The packaged transistor device according to claim 1 , wherein at least one capacitor is arranged on the substrate and adjacent at least one resistor; and wherein the at least one resistor is arranged on the substrate and adjacent one or more bond pads and the at least one capacitor.

30. The packaged transistor device according to claim 1 , wherein one or more bond pads are connected to a drain bus of the transistor structure.31 . The packaged transistor device according to claim 1 , wherein one or more bond pads are connected to a gate bus of the transistor structure.

32. The packaged transistor device according to claim 1 , wherein the at least one harmonic reduction circuit comprises two implementations of the at least one harmonic reduction circuit.

33. The packaged transistor device according to claim 1 , further comprising: an open cavity configuration; a support component; and one or more interconnects coupled to the discrete transistor, an input matching circuit, an output matching circuit, the RF signal output lead, and / or the RF signal input lead.

34. The packaged transistor device according to claim 1 , further comprising: an over-mold configuration; a support component; and one or more interconnects coupled to the discrete transistor, an input matching circuit, an output matching circuit, the RF signal output lead, and / or the RF signal input lead.

35. A process of implementing a packaged transistor device comprising: providing an RF signal input lead; providing an RF signal output lead; forming and arranging a discrete transistor comprising a transistor structure on a substrate; and forming and arranging at least one harmonic reduction circuit on the substrate of the discrete transistor.

36. The process of implementing a packaged transistor device according to claim 35, wherein the discrete transistor is configured to connect the at least one harmonic reduction circuit to a control electrode of the transistor structure.

37. The process of implementing a packaged transistor device according to claim 35, wherein the at least one harmonic reduction circuit is coupled to an output electrode of the transistor structure.

38. The process of implementing a packaged transistor device according to claim 35, wherein the substrate comprises silicon carbide (SiC).

39. The process of implementing a packaged transistor device according to claim 35, wherein the discrete transistor is implemented as a gallium nitride (GaN) silicon carbide (SiC) transistor.

40. The process of implementing a packaged transistor device according to claim 35, further comprising an input matching circuit and / or an output matching circuit.41 . The process of implementing a packaged transistor device according to claim 35, wherein a structure of the at least one harmonic reduction circuit is arranged at least partially on the substrate, is arranged at least partially on the transistor structure, and / or is arranged at least partially on the substrate and the transistor structure.

42. The process of implementing a packaged transistor device according to claim 35, wherein a structure of the transistor structure is arranged at least partially on the substrate and / or is arranged at least partially on the at least one harmonic reduction circuit.

43. The process of implementing a packaged transistor device according to claim 35, wherein the at least one harmonic reduction circuit comprises at least one inductive element, at least one capacitor, and / or at least one resistor.

44. The process of implementing a packaged transistor device according to claim 43, wherein the at least one capacitor comprises at least one dielectric layer, at least one capacitor top metal, at least one capacitor bottom metal; and wherein the at least one capacitor forms a capacitor with the at least one capacitor top metal and the at least one capacitor bottom metal having the at least one dielectric layer therebetween.

45. The process of implementing a packaged transistor device according to claim 43, wherein a structure of the at least one capacitor is arranged at least partially on the substrate, is arranged at least partially on the transistor structure, and / or is arranged at least partially on the substrate and the transistor structure.

46. The process of implementing a packaged transistor device according to claim 43, wherein the at least one inductive element comprises at least one dielectric layer and at least one inductor metal; and wherein the at least one inductive element forms an inductor by arrangement of the at least one inductor metal on the at least one dielectric layer.

47. The process of implementing a packaged transistor device according to claim 43, wherein a structure of the at least one inductive element comprises at least one inductor metal arranged at least partially on the substrate, is arranged at least partially on the transistor structure, and / or is arranged at least partially on the substrate and the transistor structure.

48. The process of implementing a packaged transistor device according to claim 43, wherein a structure of the at least one inductive element is arranged at least partially on the substrate, is arranged at least partially on the transistor structure, is arranged at least partially on the substrate and the transistor structure, and / or is arranged at least partially on the at least one capacitor.

49. The process of implementing a packaged transistor device according to claim 43, wherein an inductance of the at least one inductive element and a capacitance of the at least one capacitor is selected to provide a bandpass implementation.

50. The process of implementing a packaged transistor device according to claim 43, wherein an inductance of the at least one inductive element and a capacitance of the at least one capacitor is selected to provide a short circuit and / or low impedance path to ground for signals at a harmonic frequency.51 . The process of implementing a packaged transistor device according to claim 43, wherein the at least one harmonic reduction circuit comprises an implementation of the at least one inductive element in series with an implementation of the at least one capacitor and the at least one harmonic reduction circuit.

52. The process of implementing a packaged transistor device according to claim 43, wherein the at least one harmonic reduction circuit comprises the at least one inductive element in series with the at least one capacitor; and wherein the at least one harmonic reduction circuit comprises another implementation of the at least one inductive element in series with another implementation of the at least one capacitor.

53. The process of implementing a packaged transistor device according to claim 43, wherein the at least one capacitor is buried underneath one or more bond pads of the discrete transistor.

54. The process of implementing a packaged transistor device according to claim 43, wherein the at least one capacitor is buried underneath one or more bond pads of the discrete transistor; and wherein the at least one inductive element is arranged in a whitespace of the transistor structure.

55. The process of implementing a packaged transistor device according to claim 43, wherein the at least one capacitor is arranged in a whitespace of the transistor structure; and wherein the at least one inductive element is arranged in a whitespace of the transistor structure.

56. The process of implementing a packaged transistor device according to claim 43, wherein the at least one inductive element is between implementations of one or more bond pads of the discrete transistor.

57. The process of implementing a packaged transistor device according to claim 43, wherein the at least one inductive element is printed in a whitespace between implementations of one or more bond pads of the discrete transistor.

58. The process of implementing a packaged transistor device according to claim 43, wherein the at least one inductive element is printed between implementations of one or more bond pads of the discrete transistor.

59. The process of implementing a packaged transistor device according to claim 43, wherein the at least one inductive element is arranged on the substrate adjacent the at least one capacitor.

60. The process of implementing a packaged transistor device according to claim 43, wherein the at least one inductive element is connected to the at least one capacitor and one or more vias.61 . The process of implementing a packaged transistor device according to claim 43, wherein the at least one harmonic reduction circuit is implemented by absorbing the at least one inductive element into a fundamental match as a bandpass structure.

62. The process of implementing a packaged transistor device according to claim 35, wherein the discrete transistor comprises one or more bond pads; and wherein the one or more bond pads connect to an input matching circuit, an output matching circuit, the RF signal input lead, and / or the RF signal output lead.

63. The process of implementing a packaged transistor device according to claim 35, wherein at least one capacitor is arranged on the substrate and adjacent at least one resistor; and wherein the at least one resistor is arranged on the substrate and adjacent one or more bond pads and the at least one capacitor.

64. The process of implementing a packaged transistor device according to claim 35, wherein one or more bond pads are connected to a drain bus of the transistor structure.

65. The process of implementing a packaged transistor device according to claim 35, wherein one or more bond pads are connected to a gate bus of the transistor structure.

66. The process of implementing a packaged transistor device according to claim 35, wherein the at least one harmonic reduction circuit comprises two implementations of the at least one harmonic reduction circuit.

67. The process of implementing a packaged transistor device according to claim 35, further comprising: providing a support component; coupling one or more interconnects to the discrete transistor, an input matching circuit, an output matching circuit, the RF signal output lead, and / or the RF signal input lead; and forming an open cavity configuration.

68. The process of implementing a packaged transistor device according to claim 35, further comprising: providing a support component; coupling one or more interconnects to the discrete transistor, an input matching circuit, an output matching circuit, the RF signal output lead, and / or the RF signal input lead; and forming an over-mold configuration.

69. A packaged transistor device comprising: an RF signal input lead; an RF signal output lead;a discrete transistor comprising a transistor structure arranged and / or formed on a substrate; and at least one harmonic reduction circuit arranged and / or formed on the substrate of the discrete transistor, wherein a structure of the at least one harmonic reduction circuit is arranged at least partially on the substrate, is arranged at least partially on the transistor structure, and / or is arranged at least partially on the substrate and the transistor structure.

70. The packaged transistor device according to claim 69, wherein the discrete transistor is configured to connect the at least one harmonic reduction circuit to a control electrode of the transistor structure.71 . The packaged transistor device according to claim 69, wherein the at least one harmonic reduction circuit is coupled to an output electrode of the transistor structure.

72. The packaged transistor device according to claim 69, wherein the substrate comprises silicon carbide (SiC).

73. The packaged transistor device according to claim 69, wherein the discrete transistor is implemented as a gallium nitride (GaN) silicon carbide (SiC) transistor.

74. The packaged transistor device according to claim 69, further comprising an input matching circuit and / or an output matching circuit.

75. The packaged transistor device according to claim 69, wherein a structure of the transistor structure is arranged at least partially on the substrate and / or is arranged at least partially on the at least one harmonic reduction circuit.

76. The packaged transistor device according to claim 69, wherein the at least one harmonic reduction circuit comprises at least one inductive element, at least one capacitor, and / or at least one resistor.

77. The packaged transistor device according to claim 76, wherein the at least one capacitor comprises at least one dielectric layer, at least one capacitor top metal, at least one capacitor bottom metal; and wherein the at least one capacitor forms a capacitor with the at least one capacitor top metal and the at least one capacitor bottom metal having the at least one dielectric layer therebetween.

78. The packaged transistor device according to claim 76, wherein a structure of the at least one capacitor is arranged at least partially on the substrate, is arranged at least partially on the transistor structure, and / or is arranged at least partially on the substrate and the transistor structure.

79. The packaged transistor device according to claim 76, wherein the at least one inductive element comprises at least one dielectric layer and at least one inductor metal; and wherein the at least one inductive element forms an inductor by arrangement of the at least one inductor metal on the at least one dielectric layer.

80. The packaged transistor device according to claim 76, wherein a structure of the at least one inductive element comprises at least one inductor metal arranged at least partially on the substrate, is arranged at least partially on the transistor structure, and / or is arranged at least partially on the substrate and the transistor structure.81 . The packaged transistor device according to claim 76, wherein a structure of the at least one inductive element is arranged at least partially on the substrate, is arranged at least partially on the transistor structure, is arranged at least partially on the substrate and the transistor structure, and / or is arranged at least partially on the at least one capacitor.

82. The packaged transistor device according to claim 76, wherein an inductance of the at least one inductive element and a capacitance of the at least one capacitor is selected to provide a bandpass implementation.

83. The packaged transistor device according to claim 76, wherein an inductance of the at least one inductive element and a capacitance of the at least one capacitor is selected to provide a short circuit and / or low impedance path to ground for signals at a harmonic frequency.

84. The packaged transistor device according to claim 76, wherein the at least one harmonic reduction circuit comprises an implementation of the at least one inductive element in series with an implementation of the at least one capacitor and the at least one harmonic reduction circuit.

85. The packaged transistor device according to claim 76, wherein the at least one harmonic reduction circuit comprises the at least one inductive element in series with the at least one capacitor; and wherein the at least one harmonic reduction circuit comprises another implementation of the at least one inductive element in series with another implementation of the at least one capacitor.

86. The packaged transistor device according to claim 76, wherein the at least one capacitor is buried underneath one or more bond pads of the discrete transistor.

87. The packaged transistor device according to claim 76, wherein the at least one capacitor is buried underneath one or more bond pads of the discrete transistor; and wherein the at least one inductive element is arranged in a whitespace of the transistor structure.

88. The packaged transistor device according to claim 76,wherein the at least one capacitor is arranged in a whitespace of the transistor structure; and wherein the at least one inductive element is arranged in a whitespace of the transistor structure.

89. The packaged transistor device according to claim 76, wherein the at least one inductive element is between implementations of one or more bond pads of the discrete transistor.

90. The packaged transistor device according to claim 76, wherein the at least one inductive element is printed in a whitespace between implementations of one or more bond pads of the discrete transistor.91 . The packaged transistor device according to claim 76, wherein the at least one inductive element is printed between implementations of one or more bond pads of the discrete transistor.

92. The packaged transistor device according to claim 76, wherein the at least one inductive element is arranged on the substrate adjacent the at least one capacitor.

93. The packaged transistor device according to claim 76, wherein the at least one inductive element is connected to the at least one capacitor and one or more vias.

94. The packaged transistor device according to claim 76, wherein the at least one harmonic reduction circuit is implemented by absorbing the at least one inductive element into a fundamental match as a bandpass structure.

95. The packaged transistor device according to claim 69, wherein the discrete transistor comprises one or more bond pads; and wherein the one or more bond pads connect to an input matching circuit, an output matching circuit, the RF signal input lead, and / or the RF signal output lead.

96. The packaged transistor device according to claim 69, wherein at least one capacitor is arranged on the substrate and adjacent at least one resistor; and wherein the at least one resistor is arranged on the substrate and adjacent one or more bond pads and the at least one capacitor.

97. The packaged transistor device according to claim 69, wherein one or more bond pads are connected to a drain bus of the transistor structure.

98. The packaged transistor device according to claim 69, wherein one or more bond pads are connected to a gate bus of the transistor structure.

99. The packaged transistor device according to claim 69, wherein the at least one harmonic reduction circuit comprises two implementations of the at least one harmonic reduction circuit.

100. The packaged transistor device according to claim 69, further comprising: an open cavity configuration; a support component; and one or more interconnects coupled to the discrete transistor, an input matching circuit, an output matching circuit, the RF signal output lead, and / or the RF signal input lead.101 . The packaged transistor device according to claim 69, further comprising: an over-mold configuration; a support component; and one or more interconnects coupled to the discrete transistor, an input matching circuit, an output matching circuit, the RF signal output lead, and / or the RF signal input lead.

102. A process of implementing a packaged transistor device comprising: providing an RF signal input lead; providing an RF signal output lead; forming and arranging a discrete transistor comprising a transistor structure on a substrate; and forming and arranging at least one harmonic reduction circuit on the substrate of the discrete transistor, wherein a structure of the at least one harmonic reduction circuit is arranged at least partially on the substrate, is arranged at least partially on the transistor structure, and / or is arranged at least partially on the substrate and the transistor structure.

103. The process of implementing a packaged transistor device according to claim 102, wherein the discrete transistor is configured to connect the at least one harmonic reduction circuit to a control electrode of the transistor structure.

104. The process of implementing a packaged transistor device according to claim 102, wherein the at least one harmonic reduction circuit is coupled to an output electrode of the transistor structure.

105. The process of implementing a packaged transistor device according to claim 102, wherein the substrate comprises silicon carbide (SiC).

106. The process of implementing a packaged transistor device according to claim 102, wherein the discrete transistor is implemented as a gallium nitride (GaN) silicon carbide (SiC) transistor.

107. The process of implementing a packaged transistor device according to claim 102, further comprising an input matching circuit and / or an output matching circuit.

108. The process of implementing a packaged transistor device according to claim 102, wherein a structure of the transistor structure is arranged at least partially on the substrate and / or is arranged at least partially on the at least one harmonic reduction circuit.

109. The process of implementing a packaged transistor device according to claim 102, wherein the at least one harmonic reduction circuit comprises at least one inductive element, at least one capacitor, and / or at least one resistor.

110. The process of implementing a packaged transistor device according to claim 109, wherein the at least one capacitor comprises at least one dielectric layer, at least one capacitor top metal, at least one capacitor bottom metal; and wherein the at least one capacitor forms a capacitor with the at least one capacitor top metal and the at least one capacitor bottom metal having the at least one dielectric layer therebetween.

111. The process of implementing a packaged transistor device according to claim 109, wherein a structure of the at least one capacitor is arranged at least partially on the substrate, is arranged at least partially on the transistor structure, and / or is arranged at least partially on the substrate and the transistor structure.

112. The process of implementing a packaged transistor device according to claim 109, wherein the at least one inductive element comprises at least one dielectric layer and at least one inductor metal; and wherein the at least one inductive element forms an inductor by arrangement of the at least one inductor metal on the at least one dielectric layer.

113. The process of implementing a packaged transistor device according to claim 109, wherein a structure of the at least one inductive element comprises at least one inductor metal arranged at least partially on the substrate, is arranged atleast partially on the transistor structure, and / or is arranged at least partially on the substrate and the transistor structure.

114. The process of implementing a packaged transistor device according to claim 109, wherein a structure of the at least one inductive element is arranged at least partially on the substrate, is arranged at least partially on the transistor structure, is arranged at least partially on the substrate and the transistor structure, and / or is arranged at least partially on the at least one capacitor.

115. The process of implementing a packaged transistor device according to claim 109, wherein an inductance of the at least one inductive element and a capacitance of the at least one capacitor is selected to provide a bandpass implementation.

116. The process of implementing a packaged transistor device according to claim 109, wherein an inductance of the at least one inductive element and a capacitance of the at least one capacitor is selected to provide a short circuit and / or low impedance path to ground for signals at a harmonic frequency.

117. The process of implementing a packaged transistor device according to claim 109, wherein the at least one harmonic reduction circuit comprises an implementation of the at least one inductive element in series with an implementation of the at least one capacitor and the at least one harmonic reduction circuit.

118. The process of implementing a packaged transistor device according to claim 109, wherein the at least one harmonic reduction circuit comprises the at least one inductive element in series with the at least one capacitor; and wherein the at least one harmonic reduction circuit comprises another implementation of the at least one inductive element in series with another implementation of the at least one capacitor.

119. The process of implementing a packaged transistor device according to claim 109, wherein the at least one capacitor is buried underneath one or more bond pads of the discrete transistor.

120. The process of implementing a packaged transistor device according to claim 109, wherein the at least one capacitor is buried underneath one or more bond pads of the discrete transistor; and wherein the at least one inductive element is arranged in a whitespace of the transistor structure.121 . The process of implementing a packaged transistor device according to claim 109, wherein the at least one capacitor is arranged in a whitespace of the transistor structure; and wherein the at least one inductive element is arranged in a whitespace of the transistor structure.

122. The process of implementing a packaged transistor device according to claim 109, wherein the at least one inductive element is between implementations of one or more bond pads of the discrete transistor.

123. The process of implementing a packaged transistor device according to claim 109, wherein the at least one inductive element is printed in a whitespace between implementations of one or more bond pads of the discrete transistor.

124. The process of implementing a packaged transistor device according to claim 109, wherein the at least one inductive element is printed between implementations of one or more bond pads of the discrete transistor.

125. The process of implementing a packaged transistor device according to claim 109, wherein the at least one inductive element is arranged on the substrate adjacent the at least one capacitor.

126. The process of implementing a packaged transistor device according to claim 109, wherein the at least one inductive element is connected to the at least one capacitor and one or more vias.

127. The process of implementing a packaged transistor device according to claim 109, wherein the at least one harmonic reduction circuit is implemented by absorbing the at least one inductive element into a fundamental match as a bandpass structure.

128. The process of implementing a packaged transistor device according to claim 102, wherein the discrete transistor comprises one or more bond pads; and wherein the one or more bond pads connect to an input matching circuit, an output matching circuit, the RF signal input lead, and / or the RF signal output lead.

129. The process of implementing a packaged transistor device according to claim 102, wherein at least one capacitor is arranged on the substrate and adjacent at least one resistor; and wherein the at least one resistor is arranged on the substrate and adjacent one or more bond pads and the at least one capacitor.

130. The process of implementing a packaged transistor device according to claim 102, wherein one or more bond pads are connected to a drain bus of the transistor structure.131 . The process of implementing a packaged transistor device according to claim 102, wherein one or more bond pads are connected to a gate bus of the transistor structure.

132. The process of implementing a packaged transistor device according to claim 102, wherein the at least one harmonic reduction circuit comprises two implementations of the at least one harmonic reduction circuit.

133. The process of implementing a packaged transistor device according to claim 102, further comprising: providing a support component; coupling one or more interconnects to the discrete transistor, an input matching circuit, an output matching circuit, the RF signal output lead, and / or the RF signal input lead; and forming an open cavity configuration.

134. The process of implementing a packaged transistor device according to claim 102, further comprising: providing a support component; coupling one or more interconnects to the discrete transistor, an input matching circuit, an output matching circuit, the RF signal output lead, and / or the RF signal input lead; and forming an over-mold configuration.

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