Data transfer to reconfigurable electronic equipment using a web platform

Abstract

A system and method for hardware configuration (hardware description transfer) and data transfer for reconfigurable electronic equipment, such as an FPGA board (4) and a CPLD, uses a web platform (2). The system and method simplify a process of developing dedicated electronic circuits, allowing users to configure, prototype and transfer data to these devices directly through a web browser (33) on a computational device (1), eliminating a need for proprietary software installation and additional devices, bringing ease of use, practicality, portability, flexibility and high performance to this process. A cloud-based approach enables the computational device, such as a smartphone, a laptop computer and a tablet, to be used to update, configure and monitor reconfigurable electronic equipment, making these activities more convenient.

Description

[0001] DATA TRANSFER TO RECONFIGURABLE ELECTRONIC EQUIPMENT USING A WEB PLATFORM

[0002] BACKGROUND

[0003] Field

[0004] The present invention relates to devices and methods of a system for hardware configuration of reconfigurable electronic equipment and programmable logic devices through an online web platform.

[0005] Related Art

[0006] The development of dedicated electronic circuits for specific applications, as well as the design of semiconductor chips, or integrated circuits, is a complex, costly, and generally time-consuming process. It is common to perform simulations, verifications, and other validation and prototyping steps before manufacturing integrated circuits. Additionally, due to high costs involved, depending on scale, an investment in silicon manufacturing for some integrated circuits is not always justified. A programmable logic device, such as a Field Programmable Gate Array (FPGA) and a Complex Programmable Logic Device (CPLD), is an integrated circuit that can receive circuits specified by an engineer, and in this configuration, behave as a designed circuit - hence, a programmable logic device is reconfigurable electronic equipment.

[0007] Reconfigurable electronic equipment is widely used for specific applications where the volume is low, and the manufacture of dedicated silicon chips is not justified, as well as for prototyping and simulation. Therefore, the functions of reconfigurable electronic equipment are determined by their developers after they are manufactured, unlike Full-Custom Integrated Circuits (Full-Custom IC) and Application-Specific Integrated Circuits (ASIC).

[0008] The market for reconfigurable electronic equipment is vast, given their characteristics of flexibility, parallel data processing, and low latency. Some examples of use include: digital signal processing, image processing, artificial intelligence and data transmission. These applications can be implemented in various sectors, such as the electric sector, telecommunications, multimedia, military and automotive. Considering the characteristics of reconfiguable electronic equipment as programmable hardware, the configuration (programming) process of their functionality is crucial for their use. In fact, the configuration (programming or transfer) of a circuit designed by engineers in a FPGA board is generally performed by specific proprietary software, associated with software licenses and device drivers, making prototyping processes and faster and broader adoption by less advanced users more difficult.

[0009] Most known reconfiguable electronic equipment save configuration and usage data for the FPGA board in two different components: in the static random-access memory (SRAM), which is typically integrated into a chip on the FPGA board and loses its data when the device is disconnected from its power source, or in a FLASH memory, which is typically not integrated into a chip on the FPGA board and retains data even when the device is disconnected from its power source.

[0010] The industry standard process for programming the FPGA board into both of the components above requires the following: a computer with a Universal Serial Bus (USB) connection, proprietary software on a local disk of the computer to manage the programming process, and a physical programming device that must be connected to both the computer and the FPGA board, responsible for receiving data from the computer and sending it to the FPGA board.

[0011] A change in the paradigm of programming the FPGA board has been observed in several technologies released in recent years. An example is shown in United States Patent No. 11,863,406 B2 which deals with a programming service for an FPGA over a network, where a network service provider receives requests to implement digital logic on one or more FPGAs and produces the necessary files and / or information for programming the device(s). With this, a computing instance related to the requested FPGA(s) is allocated, where the programming and use of the devices are done.

[0012] In U.S. Pat. No. 11,115,293 B2, the focus is on using a remote computer (virtual machine instance in the cloud) that has an FPGA board attached as a high-performance co-processing accessory - in this case, the FPGA board is not near or with a user, but is located remotely, which hinders prototyping and validation activities of devices that interact with the physical world: for example, control systems, data acquisition, and other interactive applications. A method and device for remote updating of multiple FPGA board images using a soft-core processor is presented in China patent CN105573789B. The device architecture allows the storage and selection of various hardware description images for FPGAs, supporting multiple FPGAs and different application scenarios without the need for multiple updates, ensuring efficient and flexible updating. In this case, the focus is on updating the processor configured within the FPGA. Disadvantageously, a user does not have direct access to the FPGA.

[0013] The technology described in China document CN102609287B also outlines a methodology for remote updating of FPGA boards. Disadvantageously, a user does not have direct access to the FPGA boards.

[0014] The invention described in China document CN 118036516A proposes USB technology for the Joint Test Action Group (JTAG) standard - a technology responsible for enabling the connection between a computer and a JTAG device through a USB port. This technology operates via a high-speed integrated development software, comprising a USB connector, a USB-to-JTAG circuit and a JTAG connector, a switching circuit and a programmable logic device. However, this solution disadvantageously requires installation of integrated development software on a computer.

[0015] The technology described in U.S. Pat. No. 10,031,993 Bl also presents a methodology for updating the configuration of FPGA boards, which can be done through a computer network, but still relies on specific software or infrastructure for the update process.

[0016] The China document CN203786727U addresses the characteristics and limitations of the traditional and currently existing systems for configuring FPGA boards, and presents an approach focused on low cost and, like all other cases, based on software for computational devices such as personal computers.

[0017] BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The present invention is illustrated by way of example and is not limited by the accompanying figures, in which like references indicate similar elements.

[0019] FIG. 1 presents one embodiment of the architecture of a system, showing the cloud, where a computational device communicates with a web platform in accordance with the invention, which, in turn, communicates with a standalone programmer for programming a reconfigurable electronic device.

[0020] FIG. 2 illustrates a possible configuration of the standalone programmer shown in FIG. 1, which may include a touchscreen, WiFi and Ethernet connectivity, as well as a USB connection for connecting to the reconfigurable electronic device to be programmed.

[0021] FIG. 3 presents an example of using the standalone programmer connected via a USB cable to the reconfigurable electronic device, such as an FPGA board, to be programmed.

[0022] FIG. 4 illustrates an alternative scenario where a computational device, through a web browser, can load data into a reconfigurable electronic device reconfigurable directly via a USB cable without a need for any additional / intermediary programming hardware, equipment, or devices.

[0023] FIG. 5A illustrates a front view of a USB programming device.

[0024] FIG. 5B is a back view of the USB programming device shown in FIG. 5A.

[0025] FIG. 6 presents a circuit board of the USB programming device.

[0026] FIG. 7 shows the operation of the programming device when connected to a computational device for programming a reconfigurable electronic device via a USB cable.

[0027] FIG. 8 illustrates an example of an electronic development board with a reconfigurable electronic device directly connected to the electronic development board.

[0028] FIG. 9 illustrates the electronic development board of FIG. 8 coupled to the computational device.

[0029] FIG. 10A presents a wireless communication approach for programming / configuring the reconfigurable electronic device, including a computational device, a programming device, a USB cable and an FPGA board.

[0030] FIG. 10B is another view of a wireless communication approach for programming / configuring the reconfigurable electronic device shown in FIG. 10A, including a power bank. FIG. 11 is a functional block diagram of the circuit board of the USB programming device.

[0031] FIG. 12A is a flow diagram of operation of custom firmware of the standalone programmer.

[0032] FIG. 12B is a flow diagram of operation of custom firmware of the standalone programmer.

[0033] FIG. 12C is a flow diagram of operation of custom firmware of the standalone programmer.

[0034] FIG. 12D is a flow diagram of operation of custom firmware of the standalone programmer.

[0035] FIG. 13 is a flow diagram of the operation of the custom protocols used in communication between the web platform and the standalone programmer.

[0036] FIG. 14 illustrates a display on the touchscreen of the standalone programmer with a menu of functionalities and information.

[0037] FIG. 15 presents information displayed on the computational device generated by the web platform at the initial stage of programming, regardless of the programming method or device.

[0038] FIG. 16 presents information displayed on the computational device generated by web platform with the programming process completed, regardless of the programming method or device.

[0039] DETAILED DESCRIPTION

[0040] Known solutions disadvantageously need proprietary software on a local disk, which often requires substantial computational resources, burdening a user's machine, and uses a complex and unintuitive installation and configuration process of software and drivers. Moreover, developers become dependent on the software available for a specific model of an FPGA board being used. In 2024, some software tools have emerged that bring known solutions to the web / cloud environment, but known solutions still need the installation of specific device drivers, which can even negatively impact the use of other devices due to device driver conflicts.

[0041] Known solutions disadvantageously need additional hardware to program an FPGA. This requirement adds extra costs to users, and, in most cases, a programming device is only suited for the specific FPGA board for which it was developed, which makes the portability of the project more difficult. Another disadvantage related to known solutions is a necessity to have a physical connection between a user’s computer and the programming device, thereby limiting collaboration between teams and restricting programming to the user who possesses the programming device.

[0042] Although at least one known solution, such as U.S. Pat. No. 11,863,406 B2, operates in the cloud, the system and method in accordance with the invention operates directly from a web browser, allowing engineers to quickly test, prototype, and develop different versions of circuits on FPGAs connected to a personal computer via a USB cable or on FPGAs connected to networked programmers.

[0043] FIG. 1 presents one embodiment of the architecture of the system and method for data transfer to reconfigurable electronic equipment where a computational device 1, such as a laptop computer, communicates with an online, or web-based, platform (hereinafter “web platform 2”), installed on a server 19 in the cloud. The web platform 2 comprises software for programming reconfigurable electronic equipment. The web platform 2 comprises software for transferring a circuit description to the reconfigurable electronic equipment. The web platform 2 also comprises software for communicating with a web browser on the computational device 1. The web platform 2, in turn, communicates with a standalone programmer 3 in one embodiment. The standalone programmer 3 communicates, in one embodiment via a USB cable 8, with reconfigurable electronic equipment such as a FPGA 4. The system and method in accordance with the invention comprises various methods for programming reconfigurable electronic equipment or a programmable logic device, i.e., loading a synthesized bitstream into a configuration memory of the reconfigurable electronic equipment or programmable logic device to meet desired requirements.

[0044] In one embodiment, the reconfigurable electronic equipment or programmable logic device comprises an FPGA board 4 which supports a wider range of circuits and applications than other programmable logic devices, e.g., a CPLD. These expanded capabilities align with the use cases addressed by the web platform 2 and give designers maximum flexibility for future feature additions. From a tooling standpoint, FPGAs and CPLDs are programmed similarly: the logic is described in a hardware description language (e.g., Verilog), synthesized, fitted, converted into a non-volatile programming file, and loaded into the FPGA or CPLD over JTAG (Test Clock, Test Mode Select, Test Data Input, and Test Data Output) with a USB programming device.

[0045] There is needed a system for programming digital circuits into an FPGA board 4 from any computer that includes a web browser. The system and method in accordance with the invention advantageously does not require specific tools or installations on a computer or computational device 1 of a user, such as a developer, because of the way that the FPGA board 4 is interfaced through the web platform 2. When the FPGA board 4 connects wirelessly 9 to the computational device 1 (see FIGs. 10A and 10B), no cable or driver installation is necessary. When the FPGA board 4 is attached to a USB port 32 of the computational device 1 (see FIG. 4), the FPGA board operates as a fully plug-and-play device, relying on standard USB classes that are recognized natively by Windows, macOS and Linux. The web platform 2 enables development of the FPGA board 4 directly on the web browser, without the need of any other specific software on the computational device 1 of the user.

[0046] The system and method in accordance with the invention utilizes an Internet connection (or a local network / Intranet). The web platform 2 can be accessed through a web browser such as Firefox, Chrome, Safari, Edge and Opera, which can be installed on any operating system, including Windows, macOS, Android and Linux, and on various types of computational devices, including laptop computers and mobile phones. The system and method for data transfer to reconfigurable electronic equipment using a web platform is based on an integration between hardware and software and the recent World Wide Web Consortium (W3C) specifications "Web Serial API", "WebBluetooth" and "WebUSB", which allow web browsers to have direct access to devices connected via USB ports and Bluetooth communication.

[0047] A possible use case is the availability of the web platform 2 that enables digital circuit design The web platform 2 supports multiple models of FPGA boards from major market suppliers. The web platform 2 incorporates toolchains for different FPGA board brands / models in the cloud and exposes them through a single interface. At run-time, the user selects a target FPGA board 4 from a drop-down list on a web browser on the computational device 1 of the user, and the web platform 2 automatically invokes an appropriate back-end flow and constraint set, allowing the same design environment to generate bitstreams for many FPGA board families without installing local software on the computational device of the user. Once a project is started, a user has two options: 1.) upload the programming file to the web platform 2 and then write the programming file to a FPGA board 4, or 2.) use the completehardware design flow within the web platform 2 as described hereinafter. A programming file is a non-volatile configuration file - often called a bitstream, bit file or configuration file - that contains routing, look-up-table, and I / O settings required to configure the FPGA board 4. The non-volatile configuration file is loaded into the configuration memory of the FPGA board 4 during a programming, i.e., a configuration, step. Once the non-volatile configuration file is transferred to the FPGA board 4, the FPGA board transforms itself into the circuit that was initially described using a hardware description language (HDL). Uploading a pre-generated programming file, i.e., bitstream file, lets the user bypass synthesis and go straight to a programming page, providing the fastest path to device configuration; however, the bitstream must be created with third-party tools, re-introducing installation, licensing, and maintenance burdens that the web platform 2 is designed to eliminate.

[0048] If the user chooses to use the complete hardware-design flow within the web platform 2 with all facilities that there are in the web platform, it can be done through a proprietary collaborative visual language based on a “drag and drop” block-style interface or by using the Verilog HDL, which is widely used in the hardware / FPGA board developer community. The proprietary collaborative visual language automatically converts the utilized blocks used into Verilog HDL, ensuring continuity in the development process.

[0049] After completing the project, the user has an option to perform functional simulations to verify whether it meets the established requirements. After that, with a single click, the user initiates the entire synthesis process as described hereinbelow to generate a FPGA configuration file, i.e., a bitstream file.

[0050] A first step in a method in accordance with the invention is hardware design synthesis, which generates a gate-level architecture from the FPGA design in an HDL. A gate-level architecture is the lowest structural abstraction of a digital design, in which a circuit is described purely in terms of logic gates (AND, OR, NOT, NAND, NOR, etc.) and flip-flops, mapping all operations onto a standard-cell library of the FPGA board and the interconnecting nets between them. The gate-level architecture is produced by synthesizing a higher-level RTL description, e.g., Verilog HDL. Based on the gate-level architecture, a “place and route” step is performed, where, according to the quantity and type of logic gates identified in the hardware design synthesis step, connections between logical units of the target FPGA board 4 are generated. Once the “place and route” step is completed, all information needed to generate a bitstream file - such as routing, lookup-table, and I / O settings - is available to a bitstream- generation step. A bitstream file is a final file used for programming the FPGA board 4. This action is performed by back-end software on the server 19.

[0051] The entire design flow described above is executed on the web platform 2 without the need for software installation on the computational device 1 or advanced system configurations of the computational device while providing an intuitive human-machine interface such as a touchscreen 5.

[0052] Once the bitstream file is available, whether generated through a web platform 2 or third- party software, the next step is a programming step. This can be done using one of three different programming methods:

[0053] 1. Standalone programmer 3 (see FIG. 2) which provides a flexible setup without a need of a direct connection to the computational device 1, but requires an Internet connection for the standalone programmer;

[0054] 2. USB or Bluetooth-based programming system which includes a programming device 10 (see FIG. 10A) that does not require any driver installation or setup on the computational device 1, but requires a direct connection to the computational device; and

[0055] 3. USB serial programmer integrated into an electronic development board 16 (see FIG. 8) which does not require any extra programming hardware besides the electronic development board, but sometimes can require driver installation and setup on the computational device 1.

[0056] STANDALONE PROGRAMMER

[0057] The first programming method uses the standalone programmer 3 (see FIG. 2). The standalone programmer 3 includes Internet connectivity via integrated WiFi or an Ethernet port 6, a USB port 7 and power supply input 20. The standalone programmer 3 includes the touchscreen 5 and a single-board computer (SBC) within a plastic case. The SBC runs custom firmware in accordance with the invention that handles all the connectivity and programming functions. The custom firmware is a modified version of an open- source FPGA board flashing tool and includes other embedded functionalities such as integration with the server 19 and serial communication. The custom firmware handles all the communication between the server 19 and a connected FPGA board 4. The custom firmware runs the touchscreen 5, showing options and information for the user. The custom firmware connects to the server 19, and receives the compressed bitstream through network protocols, decompresses the compressed bitstream and handles the FPGA board communication and programming, supporting multiple FPGA board models. The custom firmware is not merely a wrapper around open-source flashing tools; rather, it is a purpose-built, embedded system firmware that introduces cloud-integrated, compression-aware, vendor-agnostic FPGA flashing capabilities, which are not taught or suggested by existing tools. FIGs. 12A, 12B, 12C and 12D are flow diagrams of operation of the custom firmware in accordance with the invention.

[0058] The SBC runs the custom firmware, manages cloud communication, decompresses bitstreams, and controls the programming process. The standalone programmer 3 also includes a status touchscreen module, which provides user feedback and instructions during the programming workflow. The standalone programmer 3 further includes a USB interface controller, which is part of the SBC, enabling connection and communication with the target FPGA board 4. The SBC is connectable to the FPGA board 4 via its USB port 25.

[0059] With the standalone programmer 3 connected to the Internet, either wirelessly 9 through WiFi or via a wired Ethernet connection (not shown), the user can enter a unique credential code and a project code, which are provided in advance by the web platform 2.

[0060] The standalone programmer 3 authenticates with the server 19 via the web platform 2 using the unique credential code (an essential step for access), requests the bitstream file for the project, and validates whether a user is authorized to program the project. Finally, the standalone programmer 3 provides feedback to the user. If the entered data is correct, the touchscreen 5 of the standalone programmer 3 instructs the user to connect a target programmable, or reconfigurable, electronic device such as the FPGA board 4, which has been pre-defined on the web platform 2, by the user via a drop-down menu, via a USB cable 8 to the standalone programmer 3 and select the option to start programming. By "predefined" it is meant that the specific FPGA board 4 (including its model, vendor, and programming parameters) is selected in advance by the user on the web platform 2 via the drop-down menu. This selection links the project to the target FPGA board 4, allowing the standalone programmer 3 to automatically recognize and configure itself for the correct FPGA board when the user connects it.

[0061] FIG. 1 presents the architecture of the system and method for data transfer to reconfigurable electronic equipment using the web platform 2, demonstrating the cloud, where a computational device 1, such as a laptop computer, communicates either wirelessly 9 through WiFi or via a wired Ethernet connection (not shown) with the web platform on the server 19, which in turn communicates with the standalone programmer 3 for circuit and other information on the FPGA board 4.

[0062] FIG. 1 illustrates that the standalone programmer 3 just requires an Internet connection and no nearby computational device 1, thereby enabling remote activities via the Internet. The computational device 1 uses the web platform 2 for generating or uploading the bitstream file. The communication between the web platform 2 and the standalone programmer 3 is via encrypted custom protocols. The custom protocols send the bitstream file to the standalone programmer 3. The custom protocols split the compressed file in packets, and sends the packets to the standalone programmer 3 with an encrypted connection. The custom protocols are a unique method specifically designed to transmit compressed FPGA board bitstreams over the Internet directly to the standalone programmer 3, something not available in known solutions. The custom protocols are designed specifically to ensure secure, reliable, and device-aware transfer of compressed FPGA board bitstreams over the Internet to the standalone programmer 3, operating over standard transport layers but adding a proprietary application layer that includes bitstream- specific packet framing, error recovery, and validation of the target FPGA board 4. Each bitstream is compressed and then split into packets with checksums, allowing the standalone programmer 3 to validate, reassemble, and decompress the bitstream autonomously, even under unstable network conditions. This approach enables remote and secure configuration of the target FPGA board 4. See FIG. 13 for a flow diagram of the operation of the custom protocols.

[0063] The process initiates with a serial port connection request, prompting the web platform 2 to ask the user for permission to access the connected standalone programmer 3. Upon granting this permission, the connection is successfully established. These initial steps represent the generic initialization phase of the operation. Following the connection, the compressed bitstream is transmitted to the standalone programmer 3 in a series of chunks. Once all chunks have been successfully received, the data undergoes decompression, and a checksum verification is performed to ensure the integrity of the transmitted data. If this verification is successful, the user then proceeds to flash the connected FPGA. No known protocol provides this complete functionality for flashing of a standalone FPGA board over the Internet. The communication between the standalone programmer 3 and the FPGA board 4 is via the USB cable 8.

[0064] FIG. 2 illustrates a possible configuration of the standalone programmer 3, which may include the touchscreen 5, an Ethernet port 6, and a USB port 7 for connecting another device.

[0065] The standalone programmer 3 checks whether the FPGA board 4 is properly connected. If not, the standalone programmer 3 displays an error message on the touchscreen 5 and suggests actions to mitigate the issue. If the FPGA board 4 is correctly connected, the standalone programmer 3 starts the programming process, sending the bitstream content to the FPGA board and displaying the programming status on the touchscreen 5. Upon completion, the standalone programmer 3 provides a log of the process. If the bitstream is successfully programmed in the FPGA, the user can disconnect the USB connection and use the FPGA board 4.

[0066] With the standalone programmer 3, advantageously FPGAs can be programmed on demand from anywhere in the world without a need for software (proprietary or otherwise) and driver installations on the computational device 1 of a user. This eliminates the requirement for the computational device 1 of a user to be directly connected to the FPGA board 4. The method in accordance with the invention provides greater autonomy and flexibility for project development, facilitating remote activities.

[0067] Additionally, the standalone programmer 3 is compatible with different brands and models of FPGAs, via its internal software, making it a cross-platform solution. Examples of FPGA board brands compatible with this technology include Altera / Intel, Xilinx, GoWin and Lattice. This high compatibility differentiates it from other programmers on the market, increasing the range of choices available to FPGA board hardware developers.

[0068] FIG. 3 shows an example of using the standalone programmer 3 connected via the USB cable 8 to a reconfigurable electronic device to be programmed, such as to a USB port 25 of the FPGA board 4. An output from the FPGA board 4 is obtained from an HDMI port 26 which can be coupled to a display (not shown). The FPGA board 4 includes a processor 30 and a USB-serial converter 22. After the FPGA board 4 is programmed, the user can use the FPGA board 4 while it is disconnected from the standalone programmer 3. The standalone programmer 3 includes the SBC (not shown) with software / firmware that integrates / glues everything together from the FPGA board 4, the standalone programmer 3 up to the server 19.

[0069] FIG. 4 illustrates an alternative scenario where the computational device 1, through a web browser 33 displayed on a screen 34 of the computational device, can load data into the FPGA board 4 directly via the USB cable 8 without the need for any additional / intermediary programming hardware, equipment, or devices. In this case, the web browser itself handles the connection with an USB programmer embedded in the FPGA board 4. After the FPGA board 4 is programmed, the user can use the FPGA board 4 while it is disconnected from the web browser. The web browser uses a web assembly version of an open-source FPGA board flashing tool. The web assembly version of an open-source FPGA board flashing tool enables running the FPGA board flashing tool inside the web browser, without the need of any additional software on the computational device 1 of the user. The web assembly version of an open-source FPGA board flashing tool handles the USB connection through the web browser. The web assembly version of an open-source FPGA board flashing tool supports various types of FPGAs, from multiple vendors.

[0070] USB OR BLUETOOTH-BASED PROGRAMMING SYSTEM

[0071] The second programming method is based on using the programming device 10 that acts as an interface between the computational device 1 and the FPGA board 4. In one embodiment, the programming device 10 includes a USB connector 14 (slave / device type) for communication with the FPGA board 4, and a USB connector 13 for communication with the computational device 1. In another embodiment, the programming device 10 communicates with the computational device 1 wirelessly 9 (see FIGs. 10A and 10B). Several FPGAs exist on the market, such as the "USB Blaster" manufactured by Altera Corporation of San Jose, California. However, with the web platform 2, the programming device 10 is controlled directly from a web browser, thereby eliminating a need for specific software installations on the computational device 1 of the user and advantageously enhancing usability and compatibility with a wide range of computational devices capable of running a web browser.

[0072] The programming process starts with a web page of a browser of the computational device 1 of a user requesting the online server 19 for the bitstream file for the user’s project. The server 19 synthesizes the user's project, generates the bitstream and compresses it to a file. The server 19 returns the compressed file. The server 19 contains the user's project, the block diagrams, all the information about the project, and all the synthesis files and configuration files. The server 19 programs the compressed bitstream file to the FPGA board 4. The compressed bitstream is available only in the online server 19. The method in accordance with the invention works with the file sent from the server 19. The web page then communicates with the standalone programmer 3 to transfer this file and begin programming the FPGA board 4. Independently of the programming process, if the FPGA board 4 has a serial connection to the standalone programmer 3, it can transmit this file to the standalone programmer via the serial connection. This functionality is enabled through a proprietary protocol, part of this technology, allowing the collection of diagnostic / debugging data during operation of the FPGA board 4 with the configured bitstream.

[0073] FIGs. 5A and 5B show front and rear views, respectively, of the programming device 10 including the USB connector 13 for coupling to the computational device 1 and the USB connector 14 for coupling to the FPGA board 4. Advantageously, the programming device 10 supports various brands and models of FPGA boards, along with access to debugging and testing ports (not shown). Inside the programming device 10 is a circuit board 21 (see FIG. 6).

[0074] FIG. 6 illustrates the circuit board 21 of the programming device 10 which includes a specialized microprocessor 11, an industry- standard debugging and programming port 12, a USB connector 13 for connection to the developer’s, i.e., the user’s, computational device 1, and a USB connector 14 for connection to the FPGA board 4 that is to be programmed, and a red- green-blue light-emitting diode (LED) indicator 15 for user indication. An optional Bluetooth Low Energy (BLE) communication module 31 can also be used via the debugging and programming port 12, to provide wireless communication to the programming device 10. The specialized microprocessor 11 converts the USB protocol into a Universal Asynchronous Receiver / Transmitter (UART) protocol by converting parallel data into a serial format. The UART protocol is a serial communication protocol for transmitting data between devices.

[0075] The specialized microprocessor 11 runs an embedded system capable of communicating with various models of FPGA boards. The specialized microprocessor 11 is connected to the USB port 7 (host / master type) and to JTAG standard pins for communication with the FPGA board 4 (any of these connections can program the FPGA, depending on availability). The FED indicator 15 displays, for user interaction, different colors and patterns depending on operational status of the programming device 10.

[0076] The circuit board 21 of the programming device 10 is custom-designed to integrate the specialized microprocessor 11 (an embedded Einux-capable system-on-chip) with the USB connector 13 and the USB connector 14, enabling the programming device 10 to act as a bridge between the computational device 1 of the user and the FPGA board 4. The programming device 10 includes a programming port 12 used not only for initial firmware loading and debugging but also for connecting the optional BEE communication module 31 to enable wireless connectivity. The programming device 10 is necessary because no known off-the-shelf board provided this combination of dual-role USB ports (host+device), low- level FPGA board interface control, and compact, low-power operation within a single PCB. The programming device 10 is a fully portable programming solution for the FPGA board 4 that removes a need for local software and host drivers on the computational device 1 of the user, combining off-the-shelf components in a novel architecture that enables features not found in known programmers for FPGA boards.

[0077] A functional block diagram of the circuit board 21 of the programming device 10 is shown in FIG. 11. The driver- less interface 27 represents the serial interface that enables the programming device 10 to connect to the computational device 1 without the need for driver installation. This is because communication between the programming device 10 and the web platform 2 is implemented using protocols layered on top of generic serial communication abstraction layers. The circuit board 21 of the programming device 10 does not include an FPGA board because the programming device is for programming an external FPGA board.

[0078] FIG. 7 shows the operation of the programming device 10 when connected to the computational device 1 via the USB cable 8 for programming the FPGA board 4.

[0079] With the USB or Bluetooth-based programming system in accordance with the invention, hardware developers have access to the programming device 10 capable of communicating with FPGAs of various brands and models, either via the USB protocol or the JTAG communication standard. Furthermore, programming the FPGA board 4 can be carried out without requiring software installations or compatibility drivers on the computational device 1 because the programming device 10 uses natively compatible hardware to USB and Bluetooth connections.

[0080] The USB or Bluetooth-based programming system in accordance with the invention represents a significant improvement over known programmers because it is flexible in terms of the model and brand of the FPGA board used, as well as the programming method (via USB or JTAG). No software or driver installation is required on the computational device 1, thereby making the USB or Bluetooth-based programming system compatible with any computer because the USB or Bluetooth-based programming system in accordance with the invention is entirely web-based and operates through data network communication, WebUSB, WebSerial, or WebBluetooth. These aspects contribute to greater autonomy in project development, ease of use of the involved devices, increased portability, and enhanced performance.

[0081] USB SERIAL PROGRAMMER INTEGRATED INTO AN ELECTRONIC DEVELOPMENT BOARD

[0082] FIG. 8 illustrates an example of the electronic development board 16. The electronic development board 16 includes an embedded USB programmer and the FPGA board 4. The FPGA board 4 includes a user-accessible USB-to-serial data converter 22 and a USB connector 23 with integrated serial port. The electronic development board 16 includes the FPGA board 4, another USB connector 18, and various peripherals such as dual in-line package switches 28, buttons, potentiometer 29, accelerometer and a liquid crystal display (not shown) that may be connected to the FPGA board 4, which can be used for development tests, practices and showcases. The FPGA board 4 can be programmed directly by the computational device 1, by the standalone programmer 3 or by the programming device 10.

[0083] The programming device 10 can be integrated as part of the electronic development board 16. By integrating the programming device 10 into the electronic development board 16, a connection between the programming device 10 and the FPGA board 4 remains flexible, allowing communication via either USB or JTAG, depending exclusively on FPGA board compatibility. Additionally, data communication between the programming device 10 and the web platform 2 may be facilitated through the WebUSB or WebSerial APIs, thus ensuring convenient user access.

[0084] Through the integrated programming system in accordance with the invention, data may be displayed and circuit information from the FPGA board 4 can be collected by means of serial port monitoring software. The serial port monitoring software streamlines the development and verification process, making the development and verification process more efficient, straightforward and accessible. Moreover, the same USB cable 8 employed for programming the FPGA board 4 also provides access to the serial port monitoring software, thus optimizing the use of connections of the electronic development board 16.

[0085] FIG. 9 illustrates a connection between the USB port 32 of the computational device 1 and the USB connector 18 of the electronic development board 16 containing the FPGA board 4. The connection between the computational device 1 and the electronic development board 16 is established via the USB cable 8. The electronic development board 16 can be programmed directly from the computational device 1.

[0086] FIGs. 10A and 10B present a wireless 9 communication approach for programming / configuring the FPGA board 4, from any computational device 1 equipped with a web browser and Bluetooth communication, using the programming device 10 connected via the USB cable 8. In this case, the programming device 10 does not need to be connected to the computational device 1, as data transfer is wireless, for example, via Bluetooth, but it requires a 5-volt power supply, which can be provided by any device with a USB port, such as a power bank 17 shown in FIG. 10B. The USB connector 13 functions for both communication and power. FIGs. 10A and 10B depict a scenario where programming and behavior monitoring of the FPGA board 4 can be performed wirelessly, allowing a smartphone, tablet, or other devices to execute the programming and behavior monitoring of the FPGA board without requiring specific software installations on the computational device 1 of the user. In such scenario, users can select, directly from the web browser, the programming device 10 via Bluetooth and transfer the data to configure the FPGA board 4.

[0087] FIG. 11 is a functional block diagram of the circuit board 21 of the programming device 10.

[0088] FIGs. 12A, 12B, 12C and 12D are flow diagrams of the operation of the firmware of the standalone programmer 3, as more fully explained hereinbelow.

[0089] FIG. 13 is a flow diagram of the operation of the custom protocols used in communication between the web platform 2 and the standalone programmer 3.

[0090] FIG. 14 shows a more detailed view the touchscreen 5 of the standalone programmer 3, displaying a menu with the respective operations and settings: Run, Auto, Serial and Exit. An “ID” tag and a “Log” tab can be seen, where information and settings, such as the user ID and project ID, as well as details regarding the programming processes carried out, are displayed. In FIG. 14, there are three additional tabs shown. In the first tab, "Program" there are four buttons in the left portion of the touchscreen 5. FIG. 12A is a flow diagram of the operation of the firmware of the standalone programmer 3 associated with a “Run” button on the touchscreen 5 of the standalone programmer. The "Run" button connects to the server 19 and verifies if there is a new update in the design and downloads the latest bitstream, and then flashes the bitstream to the connected FPGA board 4. FIG. 12B is a flow diagram of the operation of the firmware of the standalone programmer 3 associated with an “Auto” button on the touchscreen 5 of the standalone programmer. The "Auto" button enables the automatic verification of the design updates in the server 19, and then automatically downloads and flashes the bitstream to the FPGA. FIG. 12C is a flow diagram of the operation of the firmware of the standalone programmer 3 associated with a “Serial” button on the touchscreen 5 of the standalone programmer. The "Serial" button enables or disables the serial wireless communication, where the device establishes a duplex communication connection, sending and receiving serial data from the FPGA board 4 to the server 19. FIG. 12D is a flow diagram of the operation of the firmware of the standalone programmer 3 associated with an “Exit” button on the touchscreen 5 of the standalone programmer. The "Exit" button closes the connection. In the right portion of the touchscreen 5, there is an area 35 that can show flashing information such as connection status, the flashing progress bar, and, if there is an error, which error happened. The flashing information is displayed only in the touchscreen 5 of the standalone programmer 3, and not in the web platform 2. In the "ID" tab, there are all the options to configure the user ID for the connection with the server 19. In the "Log" tab, there are logs from the flashing functionalities, for debugging purposes.

[0091] FIG. 15 presents information, generated by the web platform 2, displayed by a web browser 33 on a screen 34 of the computational device 1 at an initial stage of programming, regardless of the programming method or device. In FIG. 15, there is a top bar, containing buttons to access different screens from the web platform 2. In the main part of the screen of the web platform 2, there are three buttons: "Start Synthesis", "Load RISC-V CPU on FPGA" and "Flashing". The "Start Synthesis" button starts the process of synthesis of the block diagram for the user, generates all the configuration files and bitstream files, and then compresses it. The "Flashing" button opens an interface that allows the user to configure and write the bitstream to the FPGA board 4, and "Load RISC-V CPU on FPGA" button loads a RISC-V CPU on the FPGA board, which is a similar process to the flashing process, but for sending RISC-V firmware to the FPGA board. Below in FIG. 15, there is a visual diagram that shows synthesis steps, in real time, and if there are any errors during synthesis. If any error occurs, the user can see where it happened to be able to troubleshoot and find a fix.

[0092] FIG. 16 presents information, generated by the web platform 2, displayed by the web browser 33 on the screen 34 of the computational device 1 with the programming process completed, regardless of the programming method or device. In FIG. 16, there is a top bar, containing buttons to access different screens from the web platform 2. In the main part of the screen of the web platform 2, there are three buttons: "Start Synthesis", "Load RISC-V CPU on FPGA" and "Flashing". The "Start Synthesis" button starts the process of synthesis of the user block diagram and generates all the configuration files and bitstream files, and then compresses it. The "Flashing" button opens an interface that allows the user to configure and write the bitstream to the FPGA board 4, and the "Load RISC-V CPU on FPGA" button loads a RISC- V CPU on the FPGA board, which is a similar process to the flashing process, but for sending RISC-V firmware to the FPGA board. Below, there are two buttons, "Connect" and "Flash", and a checkbox "Keep Program after power-cycle". The "Connect" button opens a menu to establish a connection between the web browser on the computational device 1 and the standalone programmer 3 coupled to the computational device. The "Flashing" button starts the programming process, sending the bitstream to the standalone programmer 3, and the "Keep Program after power-cycle" button, when checked, flashes the bitstream to the nonvolatile memory of the FPGA board 4, and when unchecked, flashes the bitstream to the volatile memory of the FPGA board. FIG. 16 also shows the connection status, which can be "DISCONNECTED" or "CONNECTED", and corresponds to the status of the standalone programmer 3, and the lower portion of FIG. 16 shows a terminal screen, showing all the logs from the flashing process. It helps in the visualization of the process, and, when any error occurs, it helps troubleshooting.

[0093] FIGs. 15 and 16 show information, generated by the web platform 2, displayed by the web browser 33 on the screen 34 of the computational device 1 during the programming process of the programmable logic circuit, including stages of bitstream generation, connection with the programmable logic circuit, and transfer completion.

[0094] A method for data transfer to reconfigurable electronic equipment using a web platform 2 on a web browser 33 on a computational device 1 integrates hardware and software, allowing the configuration of circuits and software on development boards or products through transfer of circuit descriptions to reconfigurable electronic equipment, such as a FPGA board 4 and a CPLD from the web browser, thereby eliminating a need to install specialized software, device drivers, permissions or any other requirements the computational device.

[0095] The method for data transfer to reconfigurable electronic equipment using a web platform 2 uses a computational device 1 with any operating system installed, any web browser installed, wherein the web platform is accessible through the web browser 33 for executing data transfer to the reconfigurable electronic equipment.

[0096] In some embodiments, the computational device 1 is a mobile device such as a notebook, a mobile phone and a tablet, having Wi-Fi and / or Ethernet communication for connecting to the Internet for remote updating and monitoring of the reconfigurable electronic equipment; and an ability to connect to the reconfigurable electronic equipment, directly and physically using a USB communication port, with or without use of a USB cable, or directly and remotely using Bluetooth wireless communication. The web platform 2 uses the W3C specifications, Web Serial API, WebBluetooth and WebUSB to allow the web browser 33 to have direct access to the reconfigurable electronic equipment connected to the USB ports of a programming device 3, 10 or via Bluetooth communication.

[0097] The method for data transfer to reconfigurable electronic equipment using a web platform includes the steps of: providing a diagram editor with a proprietary block-based visual language in a “drag and drop” style, where each block can be selected from a collaboratively available block library, each block graphically representing Verilog HDL code with its interfaces, composed of inputs and / or outputs to connect to other blocks, forming a final diagram with all logical units necessary to perform functions or present certain behaviors within an application; allowing creation of new blocks to be made available and used in the diagram editor with the proprietary block-based visual language in a “drag and drop” style; and providing an editor for coding in Verilog HDL.

[0098] The web platform 2 automatically converts utilized blocks of the block-style interface into Verilog HDL code when the project developed with block diagrams is to be transferred to the reconfigurable electronic equipment.

[0099] The web platform 2 allows functional simulation of Verilog HDL code representing a project, with an objective of verifying operational and behavioral characteristics for the application in which the reconfigurable electronic equipment will be inserted.

[0100] The method for data transfer to reconfigurable electronic equipment using a web platform, includes the steps of: selecting technology employed in the reconfigurable electronic equipment, defining the configurations and characteristics for the subsequent steps; transforming the Verilog HDL code of a project into code representing its architecture with logic gates; executing place and route processing according to the quantity and type of logic gates identified in the previous step, generating connections between the logical units of the reconfigurable electronic equipment, considering its intrinsic characteristics; automatic final encoding for the generation of the bitstream file to be used in programming; and executing programming or transfer of the bitstream file, whether it was generated by the web platform or by external or third-party software imported into the web platform.

[0101] The method for data transfer to reconfigurable electronic equipment using a web platform is executable in one of the following ways: via a standalone programmer 3; via a USB or Bluetooth programming device 10; and via a USB programmer integrated into an electronic development board 16.

[0102] The method for data transfer to reconfigurable electronic equipment using a web platform, includes the steps of: providing a server 19; providing a standalone programmer 3 with a touchscreen 5, Internet connection through integrated Wi-Fi or Ethernet cable connection 6, a USB input 7 and a power supply input 20; providing an authentication and file request system for programming, through which a user of the server 19 must directly enter a unique credential code and a project code, provided by the web platform, into the standalone programmer 3 for authentication on the server and request of the project’s bitstream file from the server, with consequent authorization validation for programming operation of the project’s bitstream file and returning to the status of these initial authentication and request steps from the server 19 to a user; and providing a data programming system onto the reconfigurable electronic equipment, after validation by the authentication and request system on the server 19, and performing the following sub-steps: requesting the user, via the touchscreen 5, to connect the reconfigurable electronic equipment to the standalone programmer 3 using a USB cable 8 and select the option to start programming, if the connection with the reconfigurable electronic equipment is not verified, displaying an error message on the touchscreen 5 with suggested actions for mitigation, if the connection with the reconfigurable electronic equipment is verified, the programming process is started, displaying its status on the touchscreen 5, and providing a report on the programming process on the touchscreen 5, if it was started and completed, allowing the user to use the reconfigurable electronic equipment after disconnecting the USB connection from the standalone programmer 3.

[0103] The user can select an automatic mode, where no user interaction with the reconfigurable electronic equipment is necessary for remote and automated activities. In this case, whenever the user updates a project on the web platform 2, and the design is successfully synthesized, it is automatically updated on the FPGA board 4 connected to the standalone programmer 3.

[0104] The programming process onto the reconfigurable electronic equipment, starts after the connection between the reconfigurable electronic equipment and the computational device 1 is established, the user selecting the project to be programmed, and the user clicking a specific button on the web platform 2 to start such programming process.

[0105] The programming is executed through USB or Bluetooth, using a programming device 10 that interfaces between the computational device 1 and the reconfigurable electronic equipment, equipped with a USB device / slave connector and / or wireless communication capability using Bluetooth technology, directly controlled directly by a web browser.

[0106] The programming device 10 includes a specialized microprocessor 11 that performs conversion between the USB protocol and the UART serial protocol, establishing the latter connection with the processor 30 running an embedded system for communication with various models of reconfigurable electronic equipment, through a USB connector or JTAG pins.

[0107] The reconfigurable electronic equipment is programmed by: requesting the user's project bitstream file by the web platform 2, accessed through the web browser running on the computational device 1, from the server; returning the compressed bitstream file to the web platform; the web platform communicating with the programming device to transfer the bitstream file to it; and starting the programming process.

[0108] The method for data transfer to reconfigurable electronic equipment using a web platform includes, in one embodiment, using a serial connection, if available on the reconfigurable electronic equipment, enabling data transmission to its second serial port through the custom protocol, allowing the collection of diagnostic or debugging data during the use of the reconfigurable electronic equipment after programming.

[0109] The method for data transfer to reconfigurable electronic equipment using a web platform includes, in one embodiment, a FPGA board 4 being integrated into an electronic development board 16 using a USB connector or Bluetooth communication to connect to the computational device 1, with the web platform 2 being accessed through the web browser 33 running on the computational device.

[0110] What is claimed is:

Claims

CLAIMS1. A method for data transfer to reconfigurable electronic equipment comprising the steps of: providing reconfigurable electronic equipment; providing a web platform on a server wherein the web platform transfers a circuit description to the reconfigurable electronic equipment via an Internet connection; providing a web browser on a computational device, the web browser communicatively coupled to the server via the Internet; and providing a programming device communicatively coupled to the web browser and to the reconfiguable electronic equipment, wherein the web platform: provides a diagram editor with a proprietary block-based visual language in a “drag and drop” style, where each block is selectable from a collaboratively available block library, each block graphically representing Verilog HDL code with its interfaces composed of inputs and / or outputs to connect blocks, forming a final diagram with logical units for performing functions or for presenting behaviors within an application, allows creation of blocks to be made available and used in the diagram editor with the proprietary block-based visual language in a “drag and drop” style, and provides an editor for coding in Verilog HDL.

2. The method for data transfer to reconfigurable electronic equipment of claim 1, wherein the web platform uses W3C specifications, Web Serial API, WebBluetooth and WebUSB to allow the web browser to have direct access to the reconfigurable electronic equipment.

3. The method for data transfer to reconfigurable electronic equipment of claim 1, wherein the circuit description is loaded into the reconfigurable electronic equipment directly from the web browser without additional software, configuration and plugins running on the computational device.

4. The method for data transfer to reconfigurable electronic equipment of claim 1, wherein the reconfigurable electronic equipment is a FPGA board.

5. The method for data transfer to reconfigurable electronic equipment of claim 1, wherein the programming device includes a specialized microprocessor that performs conversion between a USB protocol and a UART serial protocol and establishing the UART serial protocol with a processor of reconfigurable electronic equipment, through one of a USB connector and JTAG pins.

6. A method for data transfer to reconfigurable electronic equipment using a web platform, comprising the steps of: selecting technology employed in the reconfigurable electronic equipment, defining configurations and characteristics for programming into the reconfigurable electronic equipment; transforming Verilog HDL code of a project into code representing its architecture with logic gates; executing place and route processing according to quantity and type of logic gates identified in the defining step, generating connections between logical units of the reconfigurable electronic equipment, considering its intrinsic characteristics; final encoding for the generation of a bitstream file to be used in programming; and executing one of programming and transferring of the bitstream file, whether it was generated by the web platform or by external or third-party software imported into the web platform.

7. A method for data transfer to reconfigurable electronic equipment, comprising the steps of: providing a server; installing a web platform on the server; providing a standalone programmer with a touchscreen, a USB input, and an Internet connection through one of integrated Wi-Fi and an Ethernet cable connection; providing an authentication and file request system for programming, through which a user of the server directly enters a credential code and a project code, provided by the web platform, into the standalone programmer for authentication on the server and request of a bitstream file from the server; the server returning to the user a status of the authentication and the request step of a bitstream file; and providing a data programming system onto the reconfigurable electronic equipment, and performing the following sub-steps: requesting the user, via the touchscreen, to connect the reconfigurable electronic equipment to the standalone programmer using a USB cable and to select an option to start programming, if the Internet connection with the reconfigurable electronic equipment is not verified, displaying an error message on the touchscreen with suggested actions for mitigation, if the Internet connection with the reconfigurable electronic equipment is verified, the programming is started, displaying its status on the touchscreen, and providing a report on the programming on the touchscreen, if it was started and completed, allowing the user to use the reconfigurable electronic equipment after disconnecting the standalone programmer from the Internet connection.

8. The method of claim 7, wherein the reconfigurable electronic equipment is programmed by: requesting the bitstream file by the web platform from the server; returning a compressed bitstream file to the web platform; the web platform communicating with the standalone programmer to transfer the bitstream file to it; and starting programming the reconfigurable electronic equipment.

9. The method of claim 8, wherein a programming process onto the reconfigurable electronic equipment, starts after the connection between the reconfigurable electronic equipment and a computational device is established, a user selecting a project to be programmed, and the user clicking a specific button on the standalone programmer to start such programming process.

10. The method of claim 8, including transferring data to reconfigurable electronic equipment using encrypted custom protocols, the encrypted custom protocols comprising the steps of: establishing communication between the web platform and the standalone programmer; sending the bitstream file from the web platform to the standalone programmer; compressing the bitstream file; splitting the compressed bitstream file into packets with checksums; sending the packets with checksums to the standalone programmer with an encrypted connection; and the standalone programmer validating, reassembling, and decompressing the bitstream file autonomously, even under unstable network conditions.

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