Gate drive circuit and display panel

Abstract

A gate drive circuit (GM) and a display panel. Each first control module (10) controls signals transmitted to a first node (N1) and a second node (N2), and, on the basis of signals of the first node (N1) and the second node (N2) and a corresponding clock signal (CK), a stage transmission module (30) outputs a stage transmission signal (Cas); an output control module (20) controls signal transmission between the first node (N1) and a third node (N3) on the basis of a frequency division control signal (FD) and the signal of the first node (N1); an output module (40) outputs a gate control signal (Nscan) on the basis of signals of the third node (N3) and a fourth node (N4) and the corresponding clock signal (CK).

Description

Gate drive circuit and display panel

[0001] The present application claims priority to the Chinese patent application No. 202411069460.X, filed on August 5, 2024, the disclosure of which is incorporated herein in its entirety as part of the present application. TECHNICAL FIELD

[0002] The present application relates to, but is not limited to, the technical field of display, in particular to a gate drive circuit and a display panel. BACKGROUND

[0003] If the same refresh frequency is used for the area displaying static pictures and the area displaying dynamic pictures of a display panel, the display panel will have high power consumption. Thus, to reduce the power consumption of the display panel, it is desirable that the gate control signals applied to the sub-pixels corresponding to the display of static pictures and dynamic pictures have different frequencies. Therefore, it is necessary to provide a gate drive circuit capable of outputting gate control signals meeting the requirements to support the design of the display panel to realize different refresh frequencies for different display areas. SUMMARY

[0004] The embodiments of the present application provide a gate drive circuit and a display panel, which can control the frequency of the output multiple gate control signals.

[0005] The embodiments of the present application provide a gate drive circuit, which includes a plurality of cascaded gate drive sub-circuits and a frequency division control line for transmitting a frequency division control signal to the plurality of gate drive sub-circuits; the gate drive sub-circuit includes a first control module, an output control module, a stage transmission module and an output module. The first control module is electrically connected with a first node and a second node, and the first control module is configured to control the signal transmitted to the first node according to the received start signal, and control the second node to be electrically connected with the first power supply end or the second power supply end according to the signal of the first node. The output control module is electrically connected with the frequency division control line, the first node, a third node and a fourth node, and the output control module is configured to control the signal transmission between the first node and the third node according to the frequency division control signal and the signal of the first node, and control the fourth node to be electrically connected with the first power supply end or the second power supply end according to the signal of the third node. The stage transmission module is electrically connected with the first node and the second node, and the stage transmission module is configured to receive a corresponding clock signal and output a stage transmission signal according to the signals of the first node and the second node. The output module is electrically connected with the third node and the fourth node, and the output module is configured to receive a corresponding clock signal and output a gate control signal according to the signals of the third node and the fourth node.

[0006] The display panel provided by the present application comprises any of the above-mentioned gate drive circuits, a plurality of gate control lines and a plurality of sub-pixels. The plurality of gate control lines are electrically connected to the gate drive circuit, and the plurality of gate control lines are configured to transmit corresponding gate control signals. The plurality of sub-pixels are electrically connected to the corresponding gate control lines. BRIEF DESCRIPTION OF DRAWINGS

[0007] FIG. 1 is a structural schematic diagram of a gate drive circuit provided by an embodiment of the present application;

[0008] FIGS. 2A and 2B are principle block diagrams of a gate drive sub-circuit provided by an embodiment of the present application;

[0009] FIG. 3 is a structural schematic diagram of a gate drive sub-circuit provided by an embodiment of the present application;

[0010] FIG. 4 is a timing diagram corresponding to the gate drive sub-circuit provided by an embodiment of the present application;

[0011] FIGS. 5A to 5D are structural schematic diagrams of a display panel provided by an embodiment of the present application;

[0012] FIGS. 6A and 6B are structural schematic diagrams of a sub-pixel provided by an embodiment of the present application;

[0013] FIG. 7 is a timing diagram corresponding to the pixel drive circuit shown in FIG. 6A provided by an embodiment of the present application;

[0014] FIG. 8 is a schematic diagram of a high-frequency and low-frequency picture display principle provided by an embodiment of the present application;

[0015] FIG. 9 is a timing diagram of gate control signals corresponding to different frames provided by an embodiment of the present application. Embodiments of the present application

[0016] The following is a summary of the subject matter described in detail herein, which is not intended to limit the scope of the claims. For the purpose of making the purpose, technical solution and effect of the present application clearer and more explicit, the present application is further described in detail below with reference to the drawings and embodiments. Obviously, the described embodiments are only a part of the embodiments of the present application, not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative efforts fall within the scope of protection of the present application. In addition, it should be understood that the specific embodiments described herein are only used to illustrate and explain the present application, and are not used to limit the present application. In the present application, the orientation words such as "upper" and "lower" generally refer to the upper and lower of the device in the actual use or working state, and the specific direction of the drawing surface in the drawing; and "inner" and "outer" refer to the outline of the device.

[0017] The application provides a gate drive circuit and a display panel. The gate drive circuit comprises a plurality of cascaded gate drive sub-circuits and a frequency division control line for transmitting a frequency division control signal to the plurality of gate drive sub-circuits. In the gate drive sub-circuit, a first control module controls signals transmitted to a first node and a second node, so that a stage transmission module outputs a stage transmission signal according to the signals of the first node and the second node and a corresponding clock signal. A output control module controls signal transmission between the first node and a third node according to the frequency division control signal and the signal of the first node, so that the signal transmission path between the first node and the third node is controllable, thereby making the gate control signal output by an output module according to the signals of the third node and a fourth node have or not have an effective level, and then realizing frequency controllability of the gate control signal output by the gate drive sub-circuit.

[0018] Specifically, FIG. 1 is a structural schematic diagram of a gate drive circuit provided by an embodiment of the application. The application provides a gate drive circuit GM, which comprises a plurality of cascaded gate drive sub-circuits GA and a frequency division control line FL for transmitting a frequency division control signal FD to the plurality of gate drive sub-circuits GA. The plurality of gate drive sub-circuits GA are electrically connected to a plurality of clock lines, and the plurality of gate drive sub-circuits GA are configured to output a gate control signal Nscan.

[0019] FIGS. 2A and 2B are principle block diagrams of a gate drive sub-circuit provided by an embodiment of the application, and FIG. 3 is a structural schematic diagram of the gate drive sub-circuit. The gate drive sub-circuit GA comprises a first control module 10, an output control module 20, a stage transmission module 30 and an output module 40.

[0020] The first control module 10 is electrically connected to a first node N1 and a second node N2. The first control module 10 is configured to control signals transmitted to the first node N1 according to a received start signal STV, and to control the first power supply end VGL or the second power supply end VGH to be electrically connected to the second node N2 according to the signal of the first node N1.

[0021] The output control module 20 is electrically connected to the frequency division control line FL, the first node N1, a third node N3 and a fourth node N4. The output control module 20 is configured to control signal transmission between the first node N1 and the third node N3 according to the frequency division control signal FD and the signal of the first node N1, and to control the first power supply end VGL or the second power supply end VGH to be electrically connected to the fourth node N4 according to the signal of the third node N3.

[0022] The stage transmission module 30 is electrically connected to the first node N1 and the second node N2. The stage transmission module 30 is configured to receive a corresponding clock signal CK and output a stage transmission signal Cas according to the signals of the first node N1 and the second node N2.

[0023] The output module 40 is electrically connected with the third node N3 and the fourth node N4, and the output module 40 is configured to receive the corresponding clock signal CK and output the gate control signal Nscan according to the signals of the third node N3 and the fourth node N4.

[0024] The first control module 10 controls the signals transmitted to the first node N1 and the second node N2, so that the stage transmission module 30 outputs the stage transmission signal Cas according to the signals of the first node N1 and the second node N2 and the corresponding clock signal CK. The output control module 20 controls the signal transmission between the first node N1 and the third node N3 according to the frequency division control signal FD and the signal of the first node N1, so that the signal transmission path between the first node N1 and the third node N3 is controllable, thereby making the gate control signal Nscan output by the output module 40 according to the signals of the third node N3 and the fourth node N4 and the corresponding clock signal CK have an effective level or not have an effective level, and then realizing that the frequency of the gate control signal Nscan output by the gate drive sub-circuit GA is controllable.

[0025] Optionally, the first m gate drive sub-circuits GA in the multi-stage gate drive sub-circuit GA can use the start signal stv as the starting signal STV. Wherein, m≥1. As shown in FIG. 1, the starting signal STV corresponding to the first gate drive sub-circuit GA(1) is the start signal stv, and the start signal stv can be generated by a timing controller or the like.

[0026] Optionally, the starting signal STV corresponding to the nth gate drive sub-circuit GA(n) is the (n-A)th stage transmission signal Cas(n-A) output by the (n-A)th gate drive sub-circuit GA(n-A). Wherein, n>1, A≥1. As shown in FIG. 1, the starting signal STV corresponding to the nth gate drive sub-circuit GA(n) is the (n-1)th stage transmission signal Cas(n-1) output by the (n-1)th gate drive sub-circuit GA(n-1).

[0027] Optionally, in the same gate drive sub-circuit GA, the clock signals CK accessed by the stage transmission module 30 and the output module 40 can be the same, so as to reduce the number of clock signals CK used by the gate drive sub-circuit GA, and facilitate to reduce the layout space of the gate drive sub-circuit GA.

[0028] Optionally, the multi-stage gate drive sub-circuit GA can share X clock signals CK transmitted by X clock lines, so as to reduce the number of clock signals CK used by the gate drive circuit GM and reduce the layout space of the gate drive circuit GM. Wherein, X>1.

[0029] The clock signal CK corresponding to the (2k+1)th gate driving sub-circuit GA (2k+1) is the first clock signal CK1 transmitted by the first clock line CKL1, and the clock signal CK corresponding to the (2k+2)th gate driving sub-circuit GA (2k+2) is the second clock signal CK2 transmitted by the second clock line CKL2, so that the multiple gate driving sub-circuits GA can share the clock signals CK transmitted by the two clock lines. Wherein, k≥0.

[0030] As shown in FIG. 1, the clock signal CK corresponding to the (6k+1)th gate driving sub-circuit GA (6k+1) is the first clock signal CK1 transmitted by the first clock line CKL1, the clock signal CK corresponding to the (6k+2)th gate driving sub-circuit GA (6k+2) is the second clock signal CK2 transmitted by the second clock line CKL2, the clock signal CK corresponding to the (6k+3)th gate driving sub-circuit GA (6k+3) is the third clock signal CK3 transmitted by the third clock line CKL3, the clock signal CK corresponding to the (6k+4)th gate driving sub-circuit GA (6k+4) is the fourth clock signal CK4 transmitted by the fourth clock line CKL4, the clock signal CK corresponding to the (6k+5)th gate driving sub-circuit GA (6k+5) is the fifth clock signal CK5 transmitted by the fifth clock line CKL5, and the clock signal CK corresponding to the (6k+6)th gate driving sub-circuit GA (6k+6) is the sixth clock signal CK6 transmitted by the sixth clock line CKL6, so that the multiple gate driving sub-circuits GA can share the clock signals CK transmitted by the six clock lines. Wherein, k≥0.

[0031] Optionally, the voltage supplied by the first power supply end VGL is less than the voltage supplied by the second power supply end VGH.

[0032] Please continue to refer to FIG. 3, the output module 40 includes a first output transistor To1, a second output transistor To2, and a first capacitor C1.

[0033] The first output transistor To1 includes a control end electrically connected with the third node N3, a first source-drain end configured to receive a corresponding clock signal CK, and a second source-drain end electrically connected with a first output end of the gate driving sub-circuit GA for outputting a gate control signal Nscan.

[0034] The second output transistor To2 includes a control end electrically connected with the fourth node N4, a first source-drain end electrically connected with the first power supply end VGL, and a second source-drain end electrically connected with the first output end.

[0035] The first capacitor C1 is connected in series between the control end of the first output transistor To1 and the second source-drain end of the first output transistor To1.

[0036] Optionally, the gate driving sub-circuit GA can include a plurality of output modules 40, and the clock signals CK corresponding to the plurality of output modules 40 can or can not have a phase difference.

[0037] Optionally, when the gate driving sub-circuit GA includes a plurality of output modules 40, the clock signals CK corresponding to the stage transmission signal Cas are different from the clock signals CK corresponding to the output modules 40, so that in the same gate driving sub-circuit GA, the stage in which the stage transmission signal Cas outputs the effective level can correspond to the stage in which the plurality of output modules 40 output the effective level.

[0038] Optionally, when the gate driving sub-circuit GA includes a plurality of output modules 40, the gate driving sub-circuit GA can include at least one output control module 20. For example, when the plurality of output modules 40 are electrically connected to the same third node N3 and the same fourth node N4, the gate driving sub-circuit GA includes one output control module 20, so that the signal transmission between the plurality of output modules 40 and the first node N1 is controlled by the output control module 20. For another example, the third node N3 includes a plurality of first sub-nodes, and the fourth node N4 includes a plurality of second sub-nodes. Each output module 40 is electrically connected to a first sub-node and a second sub-node. Each output module 40 receives a corresponding clock signal CK and outputs a gate control signal Nscan according to the signals of the corresponding first sub-node and second sub-node. Each output control module 20 is electrically connected to the frequency division control line FL, the first node N1, a first sub-node, and a second sub-node. Each output control module 20 is configured to control the signal transmission between the first node N1 and the corresponding first sub-node according to the received frequency division control signal FD and the signal of the first node N1, and control the electrical connection between the first power supply end VGL or the second power supply end VGH and the corresponding second sub-node according to the signal of the first sub-node. The gate driving sub-circuit GA can set one output control module 20 for each output module 40, so as to control the signal transmission between the plurality of output modules 40 and the first node N1 through the plurality of output control modules 20.

[0039] Optionally, when the gate driving sub-circuit GA includes a plurality of output control modules 20, the frequency division control signals FD corresponding to the plurality of output control modules 20 are different, so as to realize the independent control of the plurality of output control modules 20.

[0040] Please continue to refer to FIGS. 2A-2B and 3. The output control module 20 includes an output control unit 201. The output control unit 201 is electrically connected between the first node N1 and the third node N3. The output control unit 201 is configured to control the signal transmission between the first node N1 and the third node N3 according to the frequency division control signal FD and the signal of the first node N1.

[0041] Optionally, the output control unit 201 includes a first switch transistor Ts1 and a second switch transistor Ts2.

[0042] The first switch transistor Ts1 includes a control terminal electrically connected with the first node N1, a first source-drain terminal electrically connected with the frequency division control line FL, and a second source-drain terminal.

[0043] The second switch transistor Ts2 includes a control terminal electrically connected with the second source-drain terminal of the first switch transistor Ts1, a first source-drain terminal electrically connected with the first node N1, and a second source-drain terminal electrically connected with the third node N3.

[0044] Please continue to refer to FIGS. 2A-2B and 3, the output control module 20 includes a first inverting unit 202 electrically connected with the third node N3 and the fourth node N4, and configured to control the first power supply terminal VGL or the second power supply terminal VGH to be electrically connected with the fourth node N4 according to the signal of the third node N3, so that the potential of the third node N3 and the potential of the fourth node N4 change in opposite changing trends (i.e., when the potential of the third node N3 is raised, the potential of the fourth node N4 is pulled down; when the potential of the third node N3 is pulled down, the potential of the fourth node N4 is raised), so that the first output transistor To1 and the second output transistor To2 are not turned on at the same time.

[0045] Optionally, the first inverting unit 202 includes a first transistor T1 and a second transistor T2.

[0046] The first transistor T1 includes a control terminal electrically connected with the third node N3, a first source-drain terminal electrically connected with the first power supply terminal VGL, and a second source-drain terminal electrically connected with the fourth node N4.

[0047] The second transistor T2 includes a control terminal and a first source-drain terminal electrically connected with the second power supply terminal VGH, and a second source-drain terminal electrically connected with the fourth node N4.

[0048] It should be noted that the voltage relationship supplied by the first power supply terminal VGL and the second power supply terminal VGH can be determined according to the types of the first output transistor To1, the second output transistor To2, the first transistor T1, and the second transistor T2.

[0049] Please continue to refer to FIG. 3, the stage transfer module 30 includes a first stage transfer transistor Tc1, a second stage transfer transistor Tc2, and a second capacitor C2.

[0050] The first stage transfer transistor Tc1 includes a control terminal electrically connected with the first node N1, a first source-drain terminal configured to receive a corresponding clock signal CK, and a second source-drain terminal electrically connected with a second output terminal of the gate drive circuit GM for outputting a stage transfer signal Cas.

[0051] The second pass transistor Tc2 includes a control terminal electrically connected to the second node N2, a first source-drain terminal electrically connected to the first power supply terminal VGL, and a second source-drain terminal electrically connected to the second output terminal.

[0052] The second capacitor C2 is connected in series between the control terminal of the first pass transistor Tc1 and the second source-drain terminal of the first pass transistor Tc1.

[0053] Please continue to refer to FIGS. 2A-2B and 3, the first control module 10 includes a starting unit 101, the starting unit 101 is electrically connected to the first node N1, and the starting unit 101 is configured to transmit the starting signal STV to the first node N1 according to the starting signal STV.

[0054] Optionally, the starting unit 101 includes a third transistor T3, the third transistor T3 includes a control terminal configured to receive the starting signal STV and a first source-drain terminal, and a second source-drain terminal electrically connected to the first node N1.

[0055] In some embodiments, the starting unit 101 is configured to control the electrical connection between the third power supply terminal and the first node N1 according to the starting signal STV. Wherein, the voltage supplied by the third power supply terminal can be determined according to whether the first output transistor To1 is a P-type transistor or an N-type transistor, and the voltage supplied by the third power supply terminal is equal to the voltage supplied by the first power supply terminal VGL or the second power supply terminal VGH.

[0056] Please continue to refer to FIGS. 2A-2B and 3, the first control module 10 includes a second inverting unit 102, the second inverting unit 102 is electrically connected to the first node N1 and the second node N2, and the second inverting unit 102 is configured to control the electrical connection between the first power supply terminal VGL or the second power supply terminal VGH and the second node N2 according to the signal of the first node N1, so that the potential of the first node N1 and the potential of the second node N2 change in opposite changing trends (i.e., when the potential of the first node N1 is raised, the potential of the second node N2 is pulled down; when the potential of the first node N1 is pulled down, the potential of the second node N2 is raised), so that the first pass transistor Tc1 and the second pass transistor Tc2 are not turned on at the same time.

[0057] Optionally, the second inverting unit 102 includes a fourth transistor T4 and a fifth transistor T5.

[0058] The fourth transistor T4 includes a control terminal electrically connected to the first node N1, a first source-drain terminal electrically connected to the first power supply terminal VGL, and a second source-drain terminal electrically connected to the second node N2.

[0059] The fifth transistor T5 includes a control terminal and a first source-drain terminal electrically connected with the second power supply terminal VGH, and a second source-drain terminal electrically connected with the second node N2.

[0060] By electrically connecting the first inverting unit 202 and the second inverting unit 102 with the first power supply terminal VGL and the second power supply terminal VGH, the number of power supply terminals introduced by the gate driving sub-circuit GA is reduced, which is conducive to reducing power consumption. It should be noted that the first inverting unit 202 and the second inverting unit 102 can also share the first power supply terminal VGL and the second power supply terminal VGH.

[0061] Please continue to refer to FIGS. 2A-2B and 3. In order to restore the effective level of the stage transmission signal Cas and the gate control signal Nscan to the invalid level state after outputting, the gate driving sub-circuit GA further includes a second control module 50 electrically connected with the first node N1 and the third node N3. The second control module 50 is configured to control the electrical connection between the first node N1, the third node N3 and the first power supply terminal VGL according to the received pull-down control signal PD.

[0062] Optionally, the second control module 50 includes a sixth transistor T6 and a seventh transistor T7.

[0063] The sixth transistor T6 includes a control terminal configured to receive the pull-down control signal PD, a first source-drain terminal electrically connected with the first power supply terminal VGL, and a second source-drain terminal electrically connected with the first node N1.

[0064] The seventh transistor T7 includes a control terminal configured to receive the pull-down control signal PD, a first source-drain terminal electrically connected with the first power supply terminal VGL, and a second source-drain terminal electrically connected with the third node N3.

[0065] Optionally, the nth gate driving sub-circuit GA takes the (n+B)th stage transmission signal Cas(n+B) output by the (n+B)th gate driving sub-circuit GA(n+B) as the pull-down control signal PD. Wherein, B≥1. As shown in FIG. 1, the nth gate driving sub-circuit GA(n) takes the (n+1)th stage transmission signal Cas(n+1) output by the (n+1)th gate driving sub-circuit GA(n+1) as the pull-down control signal PD.

[0066] Please continue to refer to FIGS. 2A-2B and 3. In order to make the stage transmission signal Cas have a stable invalid level state, the gate driving sub-circuit GA includes a potential maintaining module 60. The potential maintaining module 60 is electrically connected with the first node N1 and the second node N2. The potential maintaining module 60 is configured to control the electrical connection between the first power supply terminal VGL and the first node N1 according to the signal of the second node N2, so as to maintain the stability of the potential of the first node N1 by the first power supply terminal VGL.

[0067] Optionally, the potential maintaining module 60 comprises an eighth transistor T8, the eighth transistor T8 comprises a control terminal electrically connected with the second node N2, a first source-drain terminal electrically connected with the first power supply end VGL, and a second source-drain terminal electrically connected with the first node N1.

[0068] Please continue to refer to FIG. 2A-2B and FIG. 3. In order to make each of the multi-stage gate driving sub-circuit GA output high-quality stage transmission signal Cas and gate control signal Nscan, the gate driving sub-circuit GA comprises a reset module 70 electrically connected with the first node N1, and the reset module 70 is configured to control the first power supply end VGL to be electrically connected with the first node N1 according to the received reset control signal RST, so that the potential of the first node N1 can be reset by the voltage supplied by the first power supply end VGL.

[0069] Optionally, the reset module 70 comprises a reset transistor Tre, the reset transistor Tre comprises a control terminal configured to receive the reset control signal RST, a first source-drain terminal electrically connected with the first power supply end VGL, and a second source-drain terminal electrically connected with the first node N1.

[0070] Optionally, the multi-stage gate driving sub-circuits GA share the same reset control signal RST, so that the potentials of the first nodes N1 of the multi-stage gate driving sub-circuits GA can be reset at the same time.

[0071] It should be noted that each transistor included in the gate driving sub-circuit GA can be a P-type transistor or an N-type transistor. The control terminal corresponds to the gate of the transistor, the first source-drain terminal corresponds to one of the source and the drain of the transistor, and the second source-drain terminal corresponds to the other of the source and the drain of the transistor.

[0072] FIG. 4 is a timing diagram of the corresponding gate driving sub-circuit provided by the embodiment of the present application. Taking each transistor included in the gate driving sub-circuit GA as an N-type transistor, the starting signal STV corresponding to the first-stage gate driving sub-circuit GA(1) is a start signal stv, the starting signal STV corresponding to the nth-stage gate driving sub-circuit GA(n) is the (n-1)th-stage stage transmission signal Cas(n-1) output by the (n-1)th-stage gate driving sub-circuit GA(n-1), the nth-stage gate driving sub-circuit GA(n) takes the (n+1)th-stage stage transmission signal Cas(n+1) output by the (n+1)th-stage gate driving sub-circuit GA(n+1) as the pull-down control signal PD, and the multi-stage gate driving sub-circuit GA can share the clock signal CK transmitted by six clock lines. Taking the output module 40 and the output control module 20 included in each gate driving sub-circuit GA as an example, the working principle of the gate driving circuit GM is described.

[0073] Reset stage ta: the reset control signal RST is high, and the start signal stv is low. The reset transistor Tre in the multi-stage gate drive sub-circuit GA is turned on, the first power supply end VGL is electrically connected with the first node N1, so that the first stage transfer transistor Tc1 is cut off, and the multi-stage gate drive circuit GM is in the closed state.

[0074] First stage t1: the reset control signal RST is low, the start signal stv is high, and the first clock signal CK1 transmitted by the first clock line CKL1 and the sixth clock signal CK6 transmitted by the sixth clock line CKL6 are low.

[0075] In the first stage gate drive sub-circuit GA(1), the third transistor T3, the first switch transistor Ts1, the fourth transistor T4 and the first stage transfer transistor Tc1 are turned on, the reset transistor Tre, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8 and the second stage transfer transistor Tc2 are cut off, and the first stage cascade signal Cas(1) is low. If the frequency division control signal FD is low in the first stage t1, the second switch transistor Ts2, the first output transistor To1 and the first transistor T1 are cut off, and the second output transistor To2 is turned on. If the frequency division control signal FD is high in the first stage t1, the second switch transistor Ts2, the first output transistor To1 and the first transistor T1 are turned on, and the second output transistor To2 is cut off. Thus, the first stage gate control signal Nscan(1) is low.

[0076] The gate drive sub-circuit GA cascaded after the first stage gate drive sub-circuit GA(1) makes the cascade signal Cas and the gate control signal Nscan output by the gate drive sub-circuit GA cascaded after the first stage gate drive sub-circuit GA(1) maintain low level because the corresponding start signal stv is low.

[0077] Second stage t2: the frequency division control signal FD and the first clock signal CK1 are high, and the reset control signal RST, the start signal stv, the second clock signal CK2 and the sixth clock signal CK6 are low.

[0078] In the first stage gate drive sub-circuit GA(1), the first switch transistor Ts1, the second switch transistor Ts2, the first transistor T1, the fourth transistor T4, the first stage transfer transistor Tc1 and the first output transistor To1 are turned on, and the reset transistor Tre, the third transistor T3, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the second stage transfer transistor Tc2 and the second output transistor To2 are cut off. Thus, the first stage cascade signal Cas(1) and the first stage gate control signal Nscan(1) are high.

[0079] The action performed by the second-stage gate drive sub-circuit GA(2) is similar to the action performed by the first-stage gate drive sub-circuit GA(1) in the first stage t1. The action performed by the third-stage gate drive sub-circuit GA(3) is similar to the action performed by the second-stage gate drive sub-circuit GA(2) in the first stage t1. In this way, the working states of the gate drive sub-circuits GA cascaded after the first-stage gate drive sub-circuit GA(1) are obtained. Thus, the cascade signals Cas and the gate control signals Nscan output by the gate drive sub-circuits GA cascaded after the first-stage gate drive sub-circuit GA(1) are all kept at low levels.

[0080] The third stage t3: the frequency division control signal FD and the second clock signal CK2 are at high levels, the reset control signal RST, the start signal stv, the first clock signal CK1, the third clock signal CK3 to the sixth clock signal CK6 are at low levels.

[0081] In the first-stage gate drive sub-circuit GA(1), the second transistor T2, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the second switch transistor Ts2, the second cascade transistor Tc2 and the second output transistor To2 are turned on, and the reset transistor Tre, the first switch transistor Ts1, the first transistor T1, the third transistor T3, the fourth transistor T4, the first cascade transistor Tc1 and the first output transistor To1 are turned off. Thus, the first-stage cascade signal Cas(1) and the first-stage gate control signal Nscan(1) are at low levels.

[0082] The action performed by the second-stage gate drive sub-circuit GA(2) is similar to the action performed by the first-stage gate drive sub-circuit GA(1) in the second stage t2. The action performed by the third-stage gate drive sub-circuit GA(3) is similar to the action performed by the second-stage gate drive sub-circuit GA(2) in the second stage t2. In this way, the working states of the gate drive sub-circuits GA cascaded after the first-stage gate drive sub-circuit GA(1) are obtained. Thus, the second-stage cascade signal Cas(2) and the second-stage gate control signal Nscan(2) are at high levels. The cascade signals Cas and the gate control signals Nscan output by the gate drive sub-circuits GA cascaded after the second-stage gate drive sub-circuit GA(2) are all kept at low levels.

[0083] The fourth stage t4: the frequency division control signal FD and the third clock signal CK3 are at high levels, the reset control signal RST, the start signal stv, the first clock signal CK1, the second clock signal CK2, the fourth clock signal CK4 to the sixth clock signal CK6 are at low levels.

[0084] The p-1th gate driving sub-circuit GA(p-1) performs an action similar to that performed by the 1st gate driving sub-circuit GA(1) in the third stage t3. The pth gate driving sub-circuit GA(p) performs an action similar to that performed by the 1st gate driving sub-circuit GA(1) in the second stage t2. The p+1th gate driving sub-circuit GA(p+1) performs an action similar to that performed by the 1st gate driving sub-circuit GA(1) in the first stage t1. Thus, the 1st stage transmission signal Cas(1) to the p-1th stage transmission signal Cas(p-1) and the 1st gate control signal Nscan(1) to the p-1th gate control signal Nscan(p-1) are low, the pth stage transmission signal Cas(p) and the pth gate control signal Nscan(p) are high, and the transmission signals Cas and the gate control signals Nscan outputted by each gate driving sub-circuit GA cascaded after the pth gate driving sub-circuit GA(p) are all low.

[0085] The fifth stage t5: the fourth clock signal CK4 is high, the frequency division control signal FD, the reset control signal RST, the start signal stv, the first clock signal CK1 to the third clock signal CK3, the fifth clock signal CK5 to the sixth clock signal CK6 are low.

[0086] The pth gate driving sub-circuit GA(p) performs an action similar to that performed by the 1st gate driving sub-circuit GA(1) in the third stage t3. Thus, the 1st stage transmission signal Cas(1) to the pth stage transmission signal Cas(p) and the 1st gate control signal Nscan(1) to the pth gate control signal Nscan(p) are low.

[0087] In the p+1th gate driving sub-circuit GA(p+1), the first switch transistor Ts1, the first transistor T1, the fourth transistor T4, the first transmission transistor Tc1, the first output transistor To1 are turned on, and the reset transistor Tre, the third transistor T3, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the second switch transistor Ts2, the second transmission transistor Tc2, the second output transistor To2 are turned off. Thus, the p+1th stage transmission signal Cas(p+1) and the p+1th gate control signal Nscan(p+1) are high.

[0088] In the gate drive sub-circuit GA(p+2) of the p+2th stage, the second transistor T2, the third transistor T3, the first switch transistor Ts1, the fourth transistor T4, the first stage transfer transistor Tc1, and the second output transistor To2 are turned on, and the reset transistor Tre, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the second stage transfer transistor Tc2, the second switch transistor Ts2, the first output transistor To1, and the first transistor T1 are turned off. Thus, the stage transfer signal Cas(p+2) of the p+2th stage and the gate control signal Nscan(p+2) of the p+2th stage are low.

[0089] The start signal stv corresponding to each gate drive sub-circuit GA cascaded after the gate drive sub-circuit GA(p+2) of the p+2th stage is low, so that the stage transfer signal Cas and the gate control signal Nscan output by each gate drive sub-circuit GA cascaded after the gate drive sub-circuit GA(p+2) of the p+2th stage are kept low.

[0090] The sixth stage t6: the fifth clock signal CK5 is high, and the frequency division control signal FD, the reset control signal RST, the start signal stv, the first clock signal CK1 to the fourth clock signal CK4, and the sixth clock signal CK6 are low.

[0091] The gate drive sub-circuit GA(p+1) of the p+1th stage performs an action similar to that performed by the gate drive sub-circuit GA(1) of the first stage in the third stage t3. Thus, the first stage transfer signal Cas(1) to the p+1th stage transfer signal Cas(p+1) and the first gate control signal Nscan(1) to the p+1th gate control signal Nscan(p+1) are low.

[0092] In the gate drive sub-circuit GA(p+2) of the p+2th stage, the first switch transistor Ts1, the second transistor T2, the fourth transistor T4, the first stage transfer transistor Tc1, and the second output transistor To2 are turned on, and the reset transistor Tre, the first transistor T1, the third transistor T3, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the second switch transistor Ts2, the second stage transfer transistor Tc2, and the first output transistor To1 are turned off. Thus, the stage transfer signal Cas(p+2) of the p+2th stage is high, and the gate control signal Nscan(p+2) of the p+2th stage is low.

[0093] The action performed by the gate driving sub-circuit GA(p+3) is similar to the action performed by the gate driving sub-circuit GA(p+2) at the fifth stage t5, and the start signal stv corresponding to each gate driving sub-circuit GA cascaded after the gate driving sub-circuit GA(p+3) is low. Thus, the cascade signal Cas and the gate control signal Nscan output by each gate driving sub-circuit GA cascaded after the gate driving sub-circuit GA(p+2) remain low.

[0094] The seventh stage t7: the sixth clock signal CK6 is high, the frequency division control signal FD, the reset control signal RST, the start signal stv, the first clock signal CK1 to the fifth clock signal CK5 are low.

[0095] The action performed by the gate driving sub-circuit GA(q) is similar to the action performed by the gate driving sub-circuit GA(p+2) at the sixth stage t6. The action performed by the gate driving sub-circuit GA(q+1) is similar to the action performed by the gate driving sub-circuit GA(p+2) at the fifth stage t5. Thus, the first cascade signal Cas(1) to the (q-1)th cascade signal Cas(q-1) and the first gate control signal Nscan(1) to the qth gate control signal Nscan(q) are low, and the qth cascade signal Cas(q) is high. The cascade signal Cas and the gate control signal Nscan output by each gate driving sub-circuit GA cascaded after the gate driving sub-circuit GA(q) remain low.

[0096] The eighth stage t8: the frequency division control signal FD and the first clock signal CK1 are high, the reset control signal RST, the start signal stv, the second clock signal CK2 to the sixth clock signal CK6 are low.

[0097] The action performed by the qth gate drive sub-circuit GA(q) is similar to the action performed by the first stage gate drive sub-circuit GA(1) at the third stage t3. The action performed by the (q+1)th gate drive sub-circuit GA(q+1) is similar to the action performed by the second stage gate drive sub-circuit GA(2) at the third stage t3. The working principle of each gate drive sub-circuit GA cascaded after the (q+1)th gate drive sub-circuit GA(q+1) is obtained by analogy. Thus, the first stage stage transmission signal Cas(1) to the qth stage stage transmission signal Cas(q) and the first stage gate control signal Nscan(1) to the qth stage gate control signal Nscan(q) are low, and the (q+1)th stage stage transmission signal Cas(q+1) to the (q+1)th stage gate control signal Nscan(q+1) are high. The stage transmission signal Cas and the gate control signal Nscan output by each gate drive sub-circuit GA cascaded after the (q+1)th gate drive sub-circuit GA(q+1) remain low.

[0098] In summary, the stage transmission signal Cas output by the first stage gate drive sub-circuit GA(1) to the (q+1)th gate drive sub-circuit GA(q+1) and each gate drive sub-circuit GA cascaded after the (q+1)th gate drive sub-circuit GA(q+1) can correspond to an output valid level. The first stage gate control signal Nscan(1) output by the first stage gate drive sub-circuit GA(1) to the (p+1)th gate control signal Nscan(p+1) output by the (p+1)th gate drive sub-circuit GA(p+1) and the gate control signal Nscan output by each gate drive sub-circuit GA cascaded after the (q+1)th gate drive sub-circuit GA(q+1) can correspond to an output valid level, while the (p+2)th gate control signal Nscan(p+2) output by the (p+2)th gate drive sub-circuit GA(p+2) to the pth gate control signal Nscan(p) output by the qth gate drive sub-circuit GA(q) can correspond to no output valid level. Therefore, by controlling the frequency division control signal FD to jump between the valid level and the invalid level, the gate control signal Nscan output by the multi-stage gate drive sub-circuit GA can have or not have a valid level, thereby realizing frequency control of the multiple gate control signals Nscan output by the gate drive circuit GM.

[0099] Further, when the frequency dividing control signal FD has the invalid level, the third node N3 in the gate driving sub-circuit GA is not electrically connected with the first node N1 due to the second switch transistor Ts2 being turned off, and the first output transistor To1 is still turned off, the second power supply end VGH can be electrically connected with the fourth node N4 according to the signal of the third node N3 by the first inverting unit 202, so that the second output transistor To2 is kept turned on, and then the first power supply end VGL is electrically connected with the first output end of the gate driving sub-circuit GA, so that the gate control signal Nscan output by the gate driving sub-circuit GA maintains the stable invalid level state, and the influence of the clock signal CK received by the output module 40 on the gate control signal Nscan output from the first output end is reduced.

[0100] FIGS. 5A-5D are structural schematic diagrams of a display panel provided in the embodiments of the present application. The present application further provides a display panel comprising any of the above-mentioned gate driving circuits GM.

[0101] The display panel comprises a plurality of gate control lines GL and a plurality of sub-pixels Spi, the plurality of gate control lines GL are electrically connected with the gate driving circuit GM, the plurality of gate control lines GL are configured to transmit corresponding gate control signals Nscan, the plurality of sub-pixels Spi are electrically connected with corresponding gate control lines GL, and the plurality of sub-pixels Spi are configured to realize the display function of the display panel.

[0102] Optionally, the gate driving circuit GM can be configured as a double-side driving. As shown in FIGS. 5A-5B, the display panel comprises a display area AA and first and second non-display areas NA1 and NA2 located at opposite sides of the display area AA, and the gate driving circuit GM is located in the first and second non-display areas NA1 and NA2, respectively.

[0103] FIGS. 6A-6B are structural schematic diagrams of a sub-pixel provided in the embodiments of the present application, and at least one sub-pixel Spi comprises a light emitting device Di and a pixel driving circuit configured to drive the light emitting device Di to emit light.

[0104] Optionally, the light emitting device Di comprises a light emitting diode. Optionally, the light emitting device Di comprises one of an organic light emitting diode, a sub-millimeter light emitting diode, a micro light emitting diode, etc.

[0105] The pixel driving circuit comprises a driving transistor Tdr, a first storage capacitor Cst1 and a data transistor Tda.

[0106] The driving transistor Tdr includes a first source-drain end electrically connected with the first voltage terminal Vdd, and a second source-drain end electrically connected with the anode of the light emitting device Di. The cathode of the light emitting device Di is electrically connected with the second voltage terminal Vss, and the voltage supplied by the first voltage terminal Vdd is greater than the voltage supplied by the second voltage terminal Vss. The first storage capacitor Cst1 is connected in series between the first voltage terminal Vdd and the control end of the driving transistor Tdr.

[0107] The data transistor Tda is electrically connected with the driving transistor Tdr, and is configured to transmit a data signal to the driving transistor Tdr, so as to make the driving transistor Tdr generate a driving current.

[0108] Optionally, the data transistor Tda includes a first source-drain end configured to receive a data signal transmitted by a corresponding electrically connected data line DL, a second source-drain end electrically connected with the control end of the driving transistor Tdr, and a control end configured to receive the above-mentioned gate control signal Nscan, so as to control whether the driving transistor Tdr receives the data signal in cooperation with the frequency division control signal FD.

[0109] Please continue to refer to FIG. 6A. In some embodiments, the control end of the data transistor Tda receives a first scan signal Pscan1. The data signal is generated by a source driving chip and output to a plurality of data lines DL.

[0110] Please continue to refer to FIG. 6A. The at least one sub-pixel Spi includes a compensation transistor Tc and a reset transistor Tr.

[0111] The compensation transistor Tc includes a control end receiving a second scan signal Scan2, a first source-drain end electrically connected with the second source-drain end of the driving transistor Tdr, and a second source-drain end electrically connected with the control end of the driving transistor Tdr.

[0112] The reset transistor Tr includes a first source-drain end electrically connected with a reset line VLr, a second source-drain end electrically connected with the control end of the driving transistor Tdr, and a control end receiving a third scan signal Scan3.

[0113] Optionally, each gate control line GL is electrically connected with the control end of the compensation transistor Tc or the reset transistor Tr of a plurality of sub-pixels Spi located in the same row, so as to take the gate control signal Nscan as the second scan signal Scan2 or the third scan signal Scan3.

[0114] Optionally, the display panel comprises two gate driving circuits GM, the two gate driving circuits GM comprise a first gate driving circuit and a second gate driving circuit, and the first gate driving circuit and the second gate driving circuit are not cascaded. The frequency division control line FL comprises a first frequency division control line electrically connected with the first gate driving circuit and a second frequency division control line electrically connected with the second gate driving circuit. The plurality of cascaded gate driving sub-circuits included in the first gate driving circuit are electrically connected with the control end of the compensation transistor Tc of the plurality of sub-pixels Spi through the corresponding first sub-gate control line, and the plurality of cascaded gate driving sub-circuits included in the second gate driving circuit are electrically connected with the control end of the reset transistor Tr of the plurality of sub-pixels Spi through the corresponding second sub-gate control line. The plurality of gate control lines GL comprise the first sub-gate control line and the second sub-gate control line.

[0115] Optionally, the gate driving circuit GM electrically connected with the plurality of first sub-gate control lines is located in at least one of the first non-display area and the second non-display area, and the gate driving circuit GM electrically connected with the plurality of second sub-gate control lines is located in at least one of the first non-display area and the second non-display area.

[0116] Optionally, the compensation transistor Tc and the reset transistor Tr are silicon transistors or oxide transistors, and the compensation transistor Tc and the reset transistor Tr are P-type transistors or N-type transistors. Optionally, in order to reduce the leakage of the control end of the driving transistor Tdr to the output end of the driving transistor Tdr and the reset line VLr, the compensation transistor Tc and the reset transistor Tr are oxide transistors. In order to be compatible with the existing process, the compensation transistor Tc and the reset transistor Tr are N-type transistors. It can be understood that the active layer of the oxide transistor comprises indium gallium zinc oxide and the like.

[0117] Please continue to refer to FIG. 6A. The at least one sub-pixel Spi comprises a first light-emitting control transistor Te1 and a second light-emitting control transistor Te2.

[0118] The first light-emitting control transistor Te1 comprises a control end receiving a light-emitting control signal EM, a first source-drain end electrically connected with the first voltage end Vdd, and a second source-drain end electrically connected with the first source-drain end of the driving transistor Tdr.

[0119] The second light-emitting control transistor Te2 comprises a control end receiving a light-emitting control signal EM, a first source-drain end electrically connected with the second source-drain end of the driving transistor Tdr, and a second source-drain end electrically connected with the anode of the light-emitting device Di.

[0120] Optionally, the display panel comprises an emission driving circuit, the emission driving circuit is electrically connected with the plurality of sub-pixels Spi, and the emission driving circuit is configured to generate a plurality of light-emitting control signals EM.

[0121] Please continue to refer to FIG. 6A, the sub-pixel Spi includes a first initial transistor Ti1, the first initial transistor Ti1 includes a control end receiving a fourth scan signal Scan4, a first source-drain end configured to receive a first initial signal transmitted by a first initial line VL1, and a second source-drain end electrically connected with an anode of the light emitting device Di.

[0122] In some embodiments, the sub-pixel Spi includes a second storage capacitor Cst2, the second storage capacitor Cst2 is connected in series between the control end of the data transistor Tda and the control end of the driving transistor Tdr, as shown in FIG. 6A.

[0123] In some embodiments, in order to improve the threshold voltage shift of the driving transistor Tdr caused by the display frequency switching, the sub-pixel Spi includes a second initial transistor Ti2, the second initial transistor Ti2 includes a control end configured to receive the fourth scan signal Scan4, a first source-drain end configured to receive a second initial signal transmitted by a second initial line VL2, and a second source-drain end electrically connected with the first source-drain end of the driving transistor Tdr, as shown in FIG. 6A.

[0124] Please continue to refer to FIG. 6B, the pixel circuit structure of the sub-pixel can also adopt a 4T1C structure. That is, the sub-pixel includes a driving transistor Tdr, a data transistor Tda, a reset transistor Tr, a first initial transistor Ti1, and a first storage capacitor Cst1. Among them, the first scan signal Pscan1 received by the control end of the data transistor Tda can be the above-mentioned gate control signal Nscan, so as to control whether the driving transistor Tdr receives the data signal in cooperation with the frequency division control signal FD.

[0125] FIG. 7 is a timing diagram corresponding to the pixel driving circuit shown in FIG. 6A provided by the embodiments of the present application. Taking the compensation transistor Tc and the reset transistor Tr as N-type transistors, and the driving transistor Tdr, the data transistor Tda, the first light emitting control transistor Te1, the second light emitting control transistor Te2, the first initial transistor Ti1, and the second initial transistor Ti2 as P-type transistors as examples, the working principle of the pixel driving circuit shown in FIG. 6A is described.

[0126] In the first reset stage Si1: the light emitting control signal EM and the first scan signal Pscan1 are high, and the third scan signal Scan3, the second scan signal Scan2, and the fourth scan signal Scan4 are low. The first initial signal transmitted by the first initial line VL1 is transmitted to the anode of the light emitting device Di, so as to reset the anode potential of the light emitting device Di; the second initial signal transmitted by the second initial line VL2 is transmitted to the input end and the output end of the driving transistor Tdr, so as to reset the potential of the input end and the output end of the driving transistor Tdr.

[0127] In the second reset stage Si2, the third scan signal Scan3, the emission control signal EM, the first scan signal Pscan1, and the fourth scan signal Scan4 are high, and the second scan signal Scan2 is low. The reset transistor Tr is turned on, and the reset signal Vr is transmitted to the gate of the driving transistor Tdr to reset the potential of the control terminal of the driving transistor Tdr.

[0128] In the data writing stage Sw, the second scan signal Scan2, the emission control signal EM, and the fourth scan signal Scan4 are high, and the third scan signal Scan3 and the first scan signal Pscan1 are low. The data transistor Tda and the compensation transistor Tc are turned on, and the data signal is transmitted to the control terminal of the driving transistor Tdr.

[0129] In the third reset stage Si3, the emission control signal EM and the first scan signal Pscan1 are high, the third scan signal Scan3, the second scan signal Scan2, and the fourth scan signal Scan4 are low, the first initial signal is transmitted to the anode of the light emitting device Di, and the second initial signal is transmitted to the input terminal and the output terminal of the driving transistor Tdr.

[0130] In the light emitting stage Sd, the first scan signal Pscan1 and the fourth scan signal Scan4 are high, the emission control signal EM, the third scan signal Scan3, and the second scan signal Scan2 are low, the first light emitting control transistor Te1 and the second light emitting control transistor Te2 are turned on, and the driving transistor Tdr generates a driving current to drive the corresponding light emitting device Di to emit light.

[0131] In the fourth reset stage Si4 and the fifth reset stage Si5, the emission control signal EM and the first scan signal Pscan1 are high, the third scan signal Scan3, the second scan signal Scan2, and the fourth scan signal Scan4 are low, the first initial signal is transmitted to the anode of the light emitting device Di, and the second initial signal is transmitted to the input terminal and the output terminal of the driving transistor Tdr.

[0132] The write frame WF includes the first reset stage Si1, the second reset stage Si2, the data writing stage Sw, the third reset stage Si3, and the light emitting stage Sd, and the hold frame HF includes the fourth reset stage Si4, the fifth reset stage Si5, and the light emitting stage Sd.

[0133] FIG. 8 is a schematic diagram of high-frequency and low-frequency picture display principles provided by the embodiment of the present application, which illustrates a static picture display of a display panel as an example, and describes the write frame WF and the hold frame HF in combination with the sub-pixel shown in FIG. 6A.

[0134] When the display panel is in the first display mode, the display panel has a first refresh frequency, and a display period of the display panel includes a write frame WF and a hold frame HF. When the display panel is in the second display mode, the display panel has a second refresh frequency, and a display period of the display panel includes a write frame WF. The first refresh frequency is less than the second refresh frequency. The first display mode can be a low-frequency display mode, and the second display mode can be a high-frequency display mode.

[0135] When the display panel displays in the high-frequency display mode (for example, the second refresh frequency is equal to 120 Hz), the display panel needs to perform 120 times of refresh operations of display data within 1 second, that is, 120 frames of pictures are included within 1 second, and the refresh operation of display data is performed for each frame of display. (That is, the sub-pixel Spi matches the timing of the write frame WF shown in FIG. 7 for each frame.) When the display panel displays in the low-frequency display mode (for example, the first refresh frequency is equal to 1 Hz), the display panel also includes 120 frames of pictures within 1 second, but only the first frame of picture performs the refresh operation of display data (that is, the sub-pixel Spi only matches the timing of the write frame WF shown in FIG. 7 for the first frame F1), and the picture data signal of the first frame F1 is maintained for the next 119 frames of pictures without performing the refresh operation of display data (that is, the sub-pixel Spi matches the timing of the hold frame HF shown in FIG. 7 for the next 119 frames after the first frame F1).

[0136] The frame in which the refresh operation of display data is performed can be recorded as a write frame WF, and the frame in which the refresh operation of display data is not performed can be recorded as a hold frame HF. Then, in the write frame WF, the second scan signal Scan2 corresponding to the compensation transistor Tc, the third scan signal Scan3 corresponding to the reset transistor Tr, and the first scan signal Pscan1 corresponding to the data transistor Tda all need to have an effective level, so that the original data signal stored in the control end of the driving transistor Tdr is covered by the newly written data signal, so that the sub-pixel Spi re-implements display according to the newly written data signal in the write frame WF. In the hold frame HF, the second scan signal Scan2 corresponding to the compensation transistor Tc and the third scan signal Scan3 corresponding to the reset transistor Tr of part of the sub-pixels Spi are maintained at an invalid level, so that the compensation transistor Tc and the reset transistor Tr are turned off, so that the control end of the driving transistor Tdr does not store new data signals. In the hold frame HF, the first scan signal Pscan1 corresponding to the data transistor Tda can maintain the same frequency as the write frame WF. Alternatively, in the hold frame HF, the first scan signal Pscan1 corresponding to the data transistor Tda can be maintained at an invalid level, so that the frequency of the first scan signal Pscan1 corresponding to the data transistor Tda in the hold frame HF is lower than the frequency of the write frame WF.

[0137] Fig. 9 is a timing diagram of the gate control signal corresponding to different frames, taken as an example that both the transistor Tc and the reset transistor Ti are controlled by the gate control signal Nscan, to illustrate the principle of implementing frequency division display for the display panel using the gate drive circuit GM, in combination with the analysis of Figs. 4 and 7 and the sub-pixel shown in Fig. 6A. In Fig. 9, the gate control signal Nscan can represent the second scan signal Scan2 or the third scan signal Scan3.

[0138] In the first frame F1 of a display period, in order to write new data signals to the control ends of the driving transistors Tdr of the plurality of sub-pixels Spi, the plurality of gate drive sub-circuits GA all output the gate control signal Nscan having an effective level, so that the plurality of rows of sub-pixels Spi in the display panel all undergo the write frame WF stage shown in Fig. 7.

[0139] In the second frame F2 of a display period, if the first L-1 rows of sub-pixels Spi of the display panel are displayed in the high-frequency display mode and the Lth row of sub-pixels Spi and the subsequent rows of sub-pixels Spi are displayed in the low-frequency display mode, the third scan signal Scan3, the second scan signal Scan2 and the first scan signal Pscan1 applied to the first L-1 rows of sub-pixels Spi all need to have effective pulses, so that the first L rows of sub-pixels Spi all undergo the write frame WF stage shown in Fig. 7. The third scan signal Scan3 and the second scan signal Scan2 applied to the Lth row of sub-pixels Spi and the subsequent rows of sub-pixels Spi do not need to have effective pulses, so that the Lth row of sub-pixels Spi and the subsequent rows of sub-pixels Spi all undergo the hold frame HF stage shown in Fig. 7. The second frame F2 is located after the first frame F1, and L>1.

[0140] Correspondingly, if the first p+1 gate drive sub-circuits GA(1) to GA(p+1) provide the first L-1 rows of sub-pixels Spi with the required third scan signal Scan3 or second scan signal Scan2, and each gate drive sub-circuit GA cascaded after the p+1 gate drive sub-circuit GA(p+1) provides the Lth row of sub-pixels Spi and the subsequent rows of sub-pixels Spi with the required third scan signal Scan3 or second scan signal Scan2, then the gate control signal Nscan output by the first p+1 gate control signals Nscan(1) to Nscan(p+1) all need to correspondingly output an effective level, and the gate control signal Nscan output by each gate drive sub-circuit GA cascaded after the p+1 gate drive sub-circuit GA does not have an effective level.

[0141] Thus, for the first row of sub-pixels Spi~the (L-1)th row of sub-pixels Spi, the second frame F2 is still the write frame WF; and for the Lth row of sub-pixels Spi and the subsequent rows of sub-pixels Spi, the second frame F2 is the hold frame HF. Therefore, corresponding to the second frame F2, the control end of the driving transistor Tdr of the first row of sub-pixels Spi~the (L-1)th row of sub-pixels Spi has the data signal write, and the control end of the driving transistor Tdr of the Lth row of sub-pixels Spi and the subsequent rows of sub-pixels Spi does not have the data signal write, the first row of sub-pixels Spi~the (L-1)th row of sub-pixels Spi and the Lth row of sub-pixels Spi and the subsequent rows of sub-pixels Spi have a difference in the refresh frequency corresponding to the second frame F2, so that the display panel realizes the frequency division display function.

[0142] In the third frame F3 of a display period, in the Lth row of sub-pixels Spi and the subsequent rows of sub-pixels Spi, the Lth row of sub-pixels Spi~the (L+O-1)th row of sub-pixels Spi are displayed in the high-frequency display mode, and the (L+O)th row of sub-pixels Spi and the subsequent rows of sub-pixels Spi are displayed in the low-frequency display mode. Then, the third scan signal Scan3, the second scan signal Scan2 and the first scan signal Pscan1 applied to the Lth row of sub-pixels Spi~the (L+O-1)th row of sub-pixels Spi all need to have effective pulses, so that the Lth row of sub-pixels Spi~the (L+O-1)th row of sub-pixels Spi all experience the write frame WF stage shown in FIG. 7. And the third scan signal Scan3 and the second scan signal Scan2 applied to the (L+O)th row of sub-pixels Spi and the subsequent rows of sub-pixels Spi do not need to have effective pulses, so that the (L+O)th row of sub-pixels Spi and the subsequent rows of sub-pixels Spi all experience the hold frame HF stage shown in FIG. 7. Wherein, the third frame F3 is between the second frame F2 and the fourth frame F4, and O>1.

[0143] Correspondingly, if the first-stage gate driving sub-circuit GA(1)~the (q-1)th-stage gate driving sub-circuit GA(q-1) provide the third scan signal Scan3 or the second scan signal Scan2 required by the first row of sub-pixels Spi~the (L+O-1)th row of sub-pixels Spi, each gate driving sub-circuit GA cascaded after the (q-1)th-stage gate driving sub-circuit GA provides the third scan signal Scan3 or the second scan signal Scan2 required by the (L+O)th row of sub-pixels Spi and the subsequent rows of sub-pixels Spi. Then, the gate control signal Nscan output by the first-stage gate control signal Nscan(1)~the (q-1)th-stage gate control signal Nscan(q-1) all need to correspond to the output effective level, and the gate control signal Nscan output by each gate driving sub-circuit GA cascaded after the (q-1)th-stage gate driving sub-circuit GA does not have the effective level.

[0144] Therefore, the timing shown in FIG. 9 corresponds to the partition frequency division design of 120Hz, 60Hz and 30Hz in FIG. 5C, so that the display panel has three different refresh frequencies corresponding to one display period.

[0145] In addition, if the Lth row of sub-pixels Spi and the subsequent rows of sub-pixels Spi are located in the low-frequency display mode, the Lth row of sub-pixels Spi to the L+O-1th row of sub-pixels Spi are still in the high-frequency display mode. That is, the third scan signal Scan3 and the second scan signal Scan2 applied to the Lth row of sub-pixels Spi to the L+O-1th row of sub-pixels Spi do not need to have an effective pulse, so that the Lth row of sub-pixels Spi to the L+O-1th row of sub-pixels Spi all experience the hold frame HF stage shown in FIG. 7. The third scan signal Scan3, the second scan signal Scan2 and the first scan signal Pscan1 applied to the L+Oth row of sub-pixels Spi and the subsequent rows of sub-pixels Spi all need to have an effective pulse, so that the L+Oth row of sub-pixels Spi and the subsequent rows of sub-pixels Spi all experience the write frame WF stage shown in FIG. 7. Therefore, in the same display period, the refresh frequency of the display area of the display panel can change from high to low (for example, 120Hz, 60Hz and 30Hz in FIG. 5C), or from low to high (for example, 120Hz, 60Hz and 90Hz in FIG. 5C).

[0146] Similarly, referring to the design of the partition frequency division of the display panel using the sub-pixel structure shown in FIG. 6A, the design of the partition frequency division of the display panel using the sub-pixel structure shown in FIG. 6B can be obtained.

[0147] From the above analysis, it can be seen that in the write frame WF, the plurality of gate driving sub-circuits GA included in the gate driving circuit GM all output the gate control signal Nscan with an effective level, so that the plurality of sub-pixels Spi all display according to the newly written data signal in the write frame WF. In the hold frame HF, the gate control signal Nscan output by part of the gate driving sub-circuits GA included in the gate driving circuit GM does not have an effective level, so that part of the sub-pixels Spi still display according to the data signal written in the write frame WF. Accordingly, in at least one hold frame HF, the frequency division control signal FD has at least one jump between the effective level and the invalid level, so as to control whether the gate control signal Nscan output by the plurality of gate driving sub-circuits GA has an effective level.

[0148] In addition, the gate driving circuit GM can not only support the up-down frequency division of the display panel, but also support the left-right frequency division of the display panel.

[0149] Optionally, the reset stage ta and the first stage t1 shown in FIG. 4 can correspond to a vertical blanking interval of the display panel.

[0150] As shown in FIGS. 5B and 5D, the display panel includes two gate drive circuits GM, and the plurality of gate control lines GL include a plurality of first gate control lines GL1, each of which includes first sub-lines GL11 and second sub-lines GL12 arranged discontinuously. Each of the first gate control lines GL1 is electrically connected to a plurality of sub-pixels Spi in the same row, one of the two gate drive circuits GM is electrically connected to the plurality of first sub-lines GL11, and the other of the two gate drive circuits GM is electrically connected to the plurality of second sub-lines GL12, so that the gate control signal Nscan transmitted by the first sub-lines GL11 is independent of the gate control signal Nscan transmitted by the second sub-lines GL12, and thus the sub-pixels Spi electrically connected to the first sub-lines GL11 and the second sub-lines GL12 can independently perform the timing of the write frame WF and the hold frame HF, i.e., the frequency of the gate control signal received by the sub-pixels Spi electrically connected to the first sub-lines GL11 is independent of the frequency of the gate control signal received by the sub-pixels Spi electrically connected to the second sub-lines GL12, and thus the data refresh frequency of the sub-pixels Spi electrically connected to the first sub-lines GL11 and the data refresh frequency of the sub-pixels Spi electrically connected to the second sub-lines GL12 can be independent, so that the display panel realizes left-right frequency division design. The frequency of the gate control signal received by the sub-pixels Spi electrically connected to the first sub-lines GL11 (e.g., 120 Hz) is different from the frequency of the gate control signal received by the sub-pixels Spi electrically connected to the second sub-lines GL12 (e.g., 60 Hz), so that the display panel realizes left-right frequency division design. The frequency control method of the gate control signal Nscan corresponding to the left-right frequency division design can be referred to the related descriptions of FIGS. 4, 5A and 5C, which will not be described here in detail.

[0151] Please continue to refer to FIGS. 5B and 5D. On the basis that the plurality of gate control lines GL include a plurality of first gate control lines GL1, the plurality of gate control lines GL can also include a plurality of second gate control lines GL2, each of which is electrically connected to a plurality of sub-pixels Spi in the same row. The display panel includes a gate drive circuit GM electrically connected to the plurality of second gate control lines GL2, or the gate drive circuit GM electrically connected to the plurality of first gate control lines GL1 is also electrically connected to the plurality of second gate control lines GL2. Each of the second gate control lines GL2 is not arranged discontinuously, so that the display panel realizes up-down frequency division design while realizing left-right frequency division.

[0152] It should be noted that the refresh frequencies shown in FIGS. 5C-5D are only used as an example to illustrate the frequency division partition design, and are not used to limit the present application. The gate drive circuit GM provided by the present application supports the display panel to realize flexible and various forms of partition frequency division design, and thus is beneficial to reduce the power consumption of the display product and improve the endurance of the portable display device. Moreover, the gate drive circuit GM provided by the present application has a simple structure, and the method for realizing the partition frequency division design of the display panel is simple, which is beneficial to reduce the cost.

[0153] Those skilled in the art should understand that modifications or equivalent replacements can be made to the embodiments of the present application without departing from the spirit and scope of the present application, and such modifications or equivalent replacements should be covered in the scope of the present application. The embodiments can be combined with each other but will not be described one by one.

[0154] The principles and implementation manners of the present application are described by applying specific examples herein, and the above description of the embodiments is only used to help understand the method of the present application and its core idea; meanwhile, for those skilled in the art, the specific implementation manners and application ranges will be changed according to the idea of the present application, and in view of the above, the content of the specification should not be understood as a limitation of the present application.

Claims

1. A gate drive circuit, wherein, The gate drive sub-circuit comprises: The gate drive sub-circuit comprises: The first control module is electrically connected with the first node and the second node, and is configured to control the signal transmitted to the first node according to the received start signal, and control the first power supply end or the second power supply end to be electrically connected with the second node according to the signal of the first node; The output control module is electrically connected with the frequency division control line, the first node, the third node and the fourth node, and is configured to control the signal transmission between the first node and the third node according to the frequency division control signal and the signal of the first node, and control the first power supply end or the second power supply end to be electrically connected with the fourth node according to the signal of the third node; The stage transmission module is electrically connected with the first node and the second node, and is configured to receive a corresponding clock signal and output a stage transmission signal according to the signals of the first node and the second node; and The output module is electrically connected with the third node and the fourth node, and is configured to receive a corresponding clock signal and output a gate control signal according to the signals of the third node and the fourth node.

2. The gate drive circuit according to claim 1, wherein The output control module comprises: The output control unit is electrically connected between the first node and the third node, and is configured to control the signal transmission between the first node and the third node according to the frequency division control signal and the signal of the first node; and The first inverting unit is electrically connected with the third node and the fourth node, and is configured to control the first power supply end or the second power supply end to be electrically connected with the fourth node according to the signal of the third node.

3. The gate drive circuit of claim 2, wherein, The output control unit comprises: The first switch transistor comprises a control end electrically connected with the first node, a first source-drain end electrically connected with the frequency division control line, and a second source-drain end; and The second switch transistor comprises a control end electrically connected with the second source-drain end of the first switch transistor, a first source-drain end electrically connected with the first node, and a second source-drain end electrically connected with the third node.

4. The gate drive circuit of claim 2, wherein, The first inverting unit comprises: The first transistor comprises a control end electrically connected with the third node, a first source-drain end electrically connected with the first power supply end, and a second source-drain end electrically connected with the fourth node; and The second transistor comprises a control end and a first source-drain end electrically connected with the second power supply end, and a second source-drain end electrically connected with the fourth node.

5. The gate drive circuit of claim 1, wherein, The output module comprises: The first output transistor comprises a control end electrically connected with the third node, a first source-drain end configured to receive a corresponding clock signal, and a second source-drain end electrically connected with a first output end of the gate drive sub-circuit for outputting the gate control signal; The second output transistor comprises a control end electrically connected with the fourth node, a first source-drain end electrically connected with the first power supply end, and a second source-drain end electrically connected with the first output end; and A first capacitor is connected in series between the control terminal of the first output transistor and the second source / drain terminal of the first output transistor.

6. The gate drive circuit of claim 1, wherein, The stage transmission module comprises: A first stage transmission transistor comprises a control terminal electrically connected to the first node, a first source / drain terminal configured to receive a corresponding clock signal, and a second source / drain terminal electrically connected to the second output terminal of the gate drive sub-circuit for outputting the stage transmission signal; A second stage transmission transistor comprises a control terminal electrically connected to the second node, a first source / drain terminal electrically connected to the first power supply terminal, and a second source / drain terminal electrically connected to the second output terminal; and A second capacitor is connected in series between the control terminal of the first stage transmission transistor and the second source / drain terminal of the first stage transmission transistor.

7. The gate drive circuit of claim 1, wherein, The first control module comprises: A starting unit electrically connected to the first node and configured to transmit the starting signal to the first node according to the starting signal; A second inverting unit electrically connected to the first node and the second node and configured to control the electrical connection between the first power supply terminal or the second power supply terminal and the second node according to the signal of the first node.

8. The gate drive circuit of claim 7, wherein, The starting unit comprises: A third transistor comprising a control terminal configured to receive the starting signal and a first source / drain terminal, and a second source / drain terminal electrically connected to the first node.

9. The gate drive circuit of claim 7, wherein, The second inverting unit comprises: A fourth transistor comprising a control terminal electrically connected to the first node, a first source / drain terminal electrically connected to the first power supply terminal, and a second source / drain terminal electrically connected to the second node; and A fifth transistor comprising a control terminal electrically connected to the second power supply terminal and a first source / drain terminal, and a second source / drain terminal electrically connected to the second node.

10. The gate drive circuit of claim 1, wherein, The gate drive sub-circuit comprises: A second control module electrically connected to the first node and the third node and configured to control the electrical connection between the first node and the third node and the first power supply terminal according to a received pull-down control signal.

11. The gate drive circuit of claim 10, wherein, The second control module comprises: A sixth transistor comprising a control terminal configured to receive the pull-down control signal, a first source / drain terminal electrically connected to the first power supply terminal, and a second source / drain terminal electrically connected to the first node; and A seventh transistor comprising a control terminal configured to receive the pull-down control signal, a first source / drain terminal electrically connected to the first power supply terminal, and a second source / drain terminal electrically connected to the third node.

12. The gate drive circuit of claim 1, wherein, The gate drive sub-circuit comprises: A potential maintaining module electrically connected to the first node and the second node and configured to control the electrical connection between the first power supply terminal and the first node according to the signal of the second node.

13. The gate drive circuit of claim 12, wherein, The potential maintaining module comprises: An eighth transistor comprising a control terminal electrically connected to the second node, a first source / drain terminal electrically connected to the first power supply terminal, and a second source / drain terminal electrically connected to the first node.

14. The gate drive circuit of claim 1, wherein, The gate drive sub-circuit comprises: A reset module electrically connected to the first node and configured to control the electrical connection between the first power supply terminal and the first node according to a received reset control signal.

15. The gate drive circuit of claim 14, wherein, The reset module comprises: a reset transistor comprising a control terminal configured to receive the reset control signal, a first source-drain terminal electrically connected to the first power supply terminal, and a second source-drain terminal electrically connected to the first node.

16. A display panel, wherein, comprise: The gate drive circuit according to any one of claims 1-15; a plurality of gate control lines electrically connected to the gate drive circuit and configured to transmit corresponding gate control signals; and a plurality of sub-pixels electrically connected to corresponding gate control lines.

17. The display panel of claim 16, wherein, The display panel comprises two gate drive circuits, and the plurality of gate control lines comprises a plurality of first gate control lines, each of which comprises intermittently arranged first sub-lines and second sub-lines. Each of the first gate control lines is electrically connected to a plurality of sub-pixels located in the same row, and one of the two gate drive circuits is electrically connected to the plurality of first sub-lines, and the other is electrically connected to the plurality of second sub-lines.

18. The display panel of claim 16, wherein, When the display panel is in a first display mode, a display period of the display panel comprises a write frame and a hold frame. In the write frame, the plurality of gate drive sub-circuits included in the gate drive circuit output the gate control signal with an effective level; in the hold frame, part of the gate control signal output by the gate drive sub-circuit does not have an effective level.

19. The display panel of claim 18, wherein, In at least one of the hold frames, the frequency of the gate control signal has at least one jump between the effective level and the invalid level.

20. The display panel of claim 17, wherein, The frequency of the gate control signal received by the sub-pixel electrically connected to the first sub-line is not equal to the frequency of the gate control signal received by the sub-pixel electrically connected to the second sub-line.

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