Array substrate and display panel

Abstract

Disclosed in the embodiments of the present application are an array substrate and a display panel. The array substrate comprises a light-shielding layer and a thin film transistor disposed on the light-shielding layer, wherein a first electrode and a first contact portion have a first contact surface therebetween, and a second electrode and a second contact portion have a second contact surface therebetween; and in the top view of the array substrate, at least one of the first contact surface and the second contact surface has an overlapping region with the light-shielding layer, and an active layer has a non-overlapping region with the light-shielding layer.

Description

Array substrate and display panel TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to an array substrate and a display panel. BACKGROUND

[0002] In the prior art array substrate, for the thin film transistor of top gate type, a light shielding layer is usually used to shield the thin film transistor to reduce the leakage current of the thin film transistor. In some products, the light shielding layer is used to fully shield the active layer of the thin film transistor to avoid the risk of disconnection caused by the active layer climbing the topography of the light shielding layer. However, the full shielding of the active layer by the light shielding layer increases the area of the light shielding layer, resulting in a decrease in the aperture ratio of the display panel. SUMMARY

[0003] The array substrate and the display panel provided by the embodiments of the present application can realize the electrical conduction function of the thin film transistor while improving the aperture ratio.

[0004] In one aspect, the embodiments of the present application provide an array substrate, comprising:

[0005] a substrate;

[0006] a light shielding layer disposed on the substrate;

[0007] a first insulating layer disposed on a side of the light shielding layer away from the substrate;

[0008] an active layer disposed on a side of the first insulating layer away from the substrate, the active layer comprising a first contact portion, a channel and a second contact portion;

[0009] a gate electrode disposed on a side of the active layer away from the substrate and in a layer different from the active layer;

[0010] an insulating structure layer disposed on a side of the active layer away from the substrate, the insulating structure layer being provided with a first through hole and a second through hole, the first through hole exposing the first contact portion, and the second through hole exposing the second contact portion; and

[0011] a first electrode and a second electrode disposed on a side of the insulating structure layer away from the substrate, the first electrode covering the first through hole and connected to the first contact portion, the second electrode covering the second through hole and connected to the second contact portion, the first electrode having a first contact surface with the first contact portion, and the second electrode having a second contact surface with the second contact portion;

[0012] In a top view of the array substrate, at least one of the first contact surface and the second contact surface has an overlapping area with the light shielding layer, and the active layer has a non-overlapping area with the light shielding layer.

[0013] In another aspect, the embodiments of the present application also provide a display panel, which comprises the array substrate as described in any of the above embodiments. BRIEF DESCRIPTION OF DRAWINGS

[0014] FIG. 1 is a schematic view of a cross section of an array substrate according to an embodiment of the present application;

[0015] FIG. 2 is a schematic view of a plane of an array substrate according to an embodiment of the present application;

[0016] FIG. 3 is a second schematic view of a plane of an array substrate according to an embodiment of the present application;

[0017] FIG. 4 is a third schematic view of a plane of an array substrate according to an embodiment of the present application;

[0018] FIG. 5 is a fourth schematic view of a plane of an array substrate according to an embodiment of the present application;

[0019] FIG. 6 is a fifth schematic view of a plane of an array substrate according to an embodiment of the present application;

[0020] FIG. 7 is a sixth schematic view of a plane of an array substrate according to an embodiment of the present application;

[0021] FIG. 8 is a schematic view of a structure of a display panel according to an embodiment of the present application. Embodiments of the present application

[0022] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the present application. In addition, it should be understood that the specific embodiments described herein are only used to illustrate and explain the present application, and are not used to limit the present application. In the present application, the embodiments can be combined with each other but are not described one by one, and the positional words such as "upper" and "lower" are generally used to refer to the upper and lower of the device in the actual use or working state, and the specific is the direction of the drawing in the drawings; and "inner" and "outer" are used in relation to the outline of the device; the words "first", "second", "third" and the like are only used as labels, and do not impose a numerical requirement or establish an order.

[0023] The embodiments of the present application provide an array substrate and a display panel, which will be described in detail below. It should be noted that the description order of the following embodiments is not limited as the preferred order of the embodiments.

[0024] In one aspect, the embodiments of the present application provide an array substrate, which comprises:

[0025] a substrate;

[0026] a light shielding layer disposed on the substrate;

[0027] a first insulating layer disposed on a side of the light shielding layer away from the substrate;

[0028] an active layer disposed on a side of the first insulating layer away from the substrate, the active layer comprising a first contact portion, a channel, and a second contact portion;

[0029] a gate disposed on a side of the active layer away from the substrate and different from the active layer;

[0030] an insulating structure layer disposed on a side of the active layer away from the substrate, the insulating structure layer being provided with a first through hole and a second through hole, the first through hole exposing the first contact portion, and the second through hole exposing the second contact portion; and

[0031] a first electrode and a second electrode disposed on a side of the insulating structure layer away from the substrate, the first electrode covering the first through hole and connected to the first contact portion, the second electrode covering the second through hole and connected to the second contact portion, the first electrode having a first contact surface with the first contact portion, and the second electrode having a second contact surface with the second contact portion;

[0032] wherein, in a top view of the array substrate, at least one of the first contact surface and the second contact surface has an overlapping area with the light shielding layer, and the active layer has a non-overlapping area with the light shielding layer.

[0033] Optionally, in some embodiments of the present application, in a top view of the array substrate, at least one of the first contact surface and the second contact surface has a partial overlapping area with the light shielding layer, and the active layer has a partial overlapping area with the light shielding layer.

[0034] Optionally, in some embodiments of the present application, in a top view of the array substrate, the light shielding layer has a profile edge, and a portion of the first contact surface is located on a side of the profile edge away from the light shielding layer.

[0035] Optionally, in some embodiments of the present application, in a top view of the array substrate, the first contact portion and the channel are arranged and connected along a first direction.

[0036] the profile edge comprises a first side edge extending along a second direction intersecting the first direction, and a portion of the first contact surface is located on a side of the first side edge away from the light shielding layer.

[0037] Optionally, in some embodiments of the application, in a top view of the array substrate, the first contact surface overlaps with the light-shielding layer by a first area, and the first area is between 1 / 3 and 2 / 3 of an area of the first contact surface.

[0038] Optionally, in some embodiments of the application, in a top view of the array substrate, the light-shielding layer has a profile edge, and a portion of the second contact surface is located on a side of the profile edge away from the light-shielding layer.

[0039] Optionally, in some embodiments of the application, in a top view of the array substrate, the channel and the second contact portion are arranged and connected along the first direction;

[0040] The profile edge includes a second side edge opposite to the first side edge, the second side edge extends along the second direction, and a portion of the second contact surface is located on a side of the second side edge away from the light-shielding layer.

[0041] Optionally, in some embodiments of the application, the second contact portion includes a connecting sub-portion and a contact sub-portion connected to the connecting sub-portion, in a top view of the array substrate, the channel and the connecting sub-portion are arranged and connected along the first direction, and the contact sub-portion extends along the second direction;

[0042] The profile edge includes a second side edge opposite to the first side edge, the second side edge extends along the second direction, and a portion of the second contact surface and a portion of the contact sub-portion are located on a side of the second side edge away from the light-shielding layer.

[0043] Optionally, in some embodiments of the application, the profile edge further includes a third side edge connected between the first side edge and the second side edge, the third side edge extends along the first direction, and a portion of the second contact surface and a portion of the contact sub-portion are located on a side of the third side edge away from the light-shielding layer.

[0044] Optionally, in some embodiments of the application, the active layer further includes an intermediate portion, the channel includes a first channel and a second channel spaced from each other, the intermediate portion includes a first sub-portion, a second sub-portion and a third sub-portion connected in sequence, the first sub-portion is connected to the first channel, the third sub-portion is connected to the second channel, the first contact portion is connected to a side of the first channel away from the first sub-portion, and the second contact portion is connected to a side of the second channel away from the third sub-portion.

[0045] In a top view of the array substrate, the first contact portion, the first channel and the first sub-portion extend and are arranged along the first direction, the second sub-portion is arranged along the second direction, at least part of the second contact portion, the second channel and the third sub-portion extend and are arranged along the first direction.

[0046] Optionally, in some embodiments of the present application, in a top view of the array substrate, part of the second contact surface is located on a side of the first side edge away from the light shielding layer.

[0047] Optionally, in some embodiments of the present application, in a top view of the array substrate, the profiled edge further comprises a second side edge and an intermediate side edge, the second side edge is parallel to the first side edge and located on a side of the first side edge close to the second channel, the intermediate side edge is connected to the first side edge and the second side edge; in the first direction, the length of the second contact portion is less than the length of the first contact portion.

[0048] Part of the second contact surface is located on a side of the second side edge away from the light shielding layer.

[0049] Optionally, in some embodiments of the present application, the second contact portion comprises a connecting sub-portion and a contact sub-portion connected to the connecting sub-portion, in a top view of the array substrate, the connecting sub-portion, the second channel and the third sub-portion extend and are arranged along the first direction, and the contact sub-portion is arranged along the second direction.

[0050] The profiled edge further comprises a second side edge, an intermediate side edge and a third side edge, the second side edge is parallel to the first side edge and located on a side of the first side edge close to the second channel, the intermediate side edge is connected to the first side edge and the second side edge, the third side edge is arranged along the first direction and connected to a side of the second side edge away from the first side edge, in the first direction, the length of the second contact portion is less than the length of the first contact portion.

[0051] Part of the second contact surface is located on a side of the second side edge away from the light shielding layer, and part of the second contact surface is located on a side of the third side edge away from the light shielding layer.

[0052] Optionally, in some embodiments of the present application, in a top view of the array substrate, the profiled edge further comprises an opposite side edge arranged opposite to the first side edge, part of the second sub-portion is located on a side of the opposite side edge away from the light shielding layer, and a portion of the second sub-portion overlapping with the light shielding layer is connected to the first sub-portion and the third sub-portion.

[0053] Optionally, in some embodiments of the present application, in the top view of the array substrate, the second contact surface overlaps with the light-shielding layer by a second area, and the second area is between 1 / 3 and 2 / 3 of the area of the second contact surface.

[0054] Optionally, in some embodiments of the present application, in the top view of the array substrate, the second contact surface overlaps with the light-shielding layer by a second area, and the second area is between 1 / 4 and 1 / 3 of the area of the second contact surface.

[0055] In another aspect, the embodiments of the present application also provide a display panel, which comprises the array substrate according to any one of the above embodiments.

[0056] The array substrate according to the embodiments of the present application comprises a light-shielding layer and a thin film transistor disposed on the light-shielding layer. In the top view of the array substrate, the light-shielding layer has a profile edge, at least one of the first contact surface and the second contact surface overlaps with the light-shielding layer, and the active layer has a non-overlapping area with the light-shielding layer. That is, at least part of the first contact surface and / or the second contact surface is disposed in the light-shielding layer, so as to ensure that part of the first contact part and / or the second contact part overlaps with the light-shielding layer. The overlapping part does not need to climb, thereby avoiding the risk of breaking due to climbing, and ensuring that the source and the drain are electrically connected with the active layer, respectively. The active layer has a non-overlapping area with the light-shielding layer, so that part of the first contact part and / or the second contact part is disposed outside the light-shielding layer, which can reduce the area of the light-shielding layer, and thus improve the aperture ratio.

[0057] Please refer to FIG. 1 and FIG. 2, the embodiments of the present application provide an array substrate 100, which comprises a substrate 11, a light-shielding layer 12, a first insulating layer 131, an active layer py, a gate g, an insulating structure layer jy, a first electrode s and a second electrode d.

[0058] The light-shielding layer 12 is disposed on the substrate 11. The first insulating layer 131 is disposed on the side of the light-shielding layer 12 away from the substrate 11. The active layer py is disposed on the side of the first insulating layer 131 away from the substrate 11, and the active layer py comprises a first contact part p1, a channel gd and a second contact part p2. The gate g is disposed on the side of the active layer py away from the substrate 11 and is disposed in a layer different from the active layer py.

[0059] The insulating structure layer jy is disposed on the side of the active layer py away from the substrate 11. The insulating structure layer jy is provided with a first through hole k1 and a second through hole k2, the first through hole k1 exposes the first contact part p1, and the second through hole k2 exposes the second contact part p2.

[0060] The first electrode s and the second electrode d are arranged on the side of the insulating structure layer jy away from the substrate 11. The first electrode s covers the first through hole k1 and is connected to the first contact portion p1, and the second electrode d covers the second through hole k2 and is connected to the second contact portion p2. The first electrode s has a first contact surface k11 with the first contact portion p1, and the second electrode d has a second contact surface k21 with the second contact portion p2.

[0061] In a top view of the array substrate 100, at least one of the first contact surface k11 and the second contact surface k21 overlaps the light shielding layer 12, and the active layer py does not overlap the light shielding layer 12.

[0062] It should be understood that the gate g, the active layer py, the first electrode s, and the second electrode d are used to form a thin film transistor tft. The array substrate 100 of the embodiment of the present application uses the light shielding layer 12 to shield the thin film transistor tft. One of the first electrode s and the second electrode d is a source electrode, and the other of the first electrode s and the second electrode d is a drain electrode. Hereinafter, the first electrode s is taken as the source electrode, and the second electrode d is taken as the drain electrode, but the present application is not limited thereto.

[0063] In a top view of the array substrate 100, at least one of the first contact surface k11 and the second contact surface k21 overlaps the light shielding layer 12, and the active layer py does not overlap the light shielding layer 12. At least part of the first contact surface k11 and / or the first contact surface k21 is arranged in the light shielding layer 12, so as to ensure that at least part of the first contact portion p1 and / or the second contact portion p2 overlaps the light shielding layer 12. The overlapping part does not need to climb, thereby avoiding the risk of breakage due to climbing, and ensuring that the source electrode s and the drain electrode d are respectively electrically connected to the active layer py. The active layer py does not overlap the light shielding layer 12, so that part of the first contact portion p1 and / or the second contact portion p2 is arranged outside the light shielding layer 12, which can reduce the area of the light shielding layer 12 and further improve the aperture ratio.

[0064] Optionally, in some embodiments, in a top view of the array substrate 100, at least one of the first contact surface k11 and the second contact surface k21 fully overlaps the light shielding layer 12, and the active layer py partially overlaps the light shielding layer 12. That is, the orthographic projection of at least one of the first contact surface k11 and the second contact surface k21 is arranged in the light shielding layer 12, which can improve the stability of the connection between at least one of the first electrode s and the second electrode d and the active layer py. Part of the active layer py overlaps the light shielding layer 12, which can reduce the area of the light shielding layer 12.

[0065] Optionally, in some embodiments, in the top view of the array substrate 100, at least one of the first contact surface k11 and the second contact surface k21 has a local overlapping area with the light shielding layer 12, and the active layer py has a local overlapping area with the light shielding layer 12.

[0066] In the top view of the array substrate 100 (see FIG. 1), the light shielding layer 12 has a profile edge Lk, and at least one of the first contact surface k11 and the second contact surface k21 is located on the side of the profile edge Lk away from the light shielding layer 12. That is, the first contact surface k11 and / or the second contact surface k21 is arranged outside the light shielding layer 12 to ensure that the first contact part p1 and / or the second contact part p2 overlaps with the light shielding layer 12, and the overlapping part does not need to climb, avoiding the risk of breaking due to climbing, and ensuring that the source s and the drain d are electrically connected to the active layer py, respectively. The part of the first contact surface k11 and / or the second contact surface k21 arranged outside the light shielding layer 12 can further reduce the area of the light shielding layer 12, thereby improving the aperture ratio.

[0067] In FIG. 2, the insulating structure layer jy includes a second insulating layer 132 and a third insulating layer 133. The second insulating layer 132 covers the active layer py and the first insulating layer 131. The third insulating layer 133 covers the gate g and the second insulating layer 132. The first electrode s and the second electrode d are arranged on the third insulating layer 133.

[0068] In the top view of the array substrate 100 (see FIG. 1), the first contact surface k11 and the second contact surface k21 each have a local overlapping area with the light shielding layer 12, and the active layer py has a local overlapping area with the light shielding layer 12.

[0069] Optionally, in some embodiments, the insulating structure layer jy can include the second insulating layer 132, the gate g, the first electrode s and the second electrode d are arranged on the second insulating layer 132, and the first through-hole k1 and the second through-hole k2 each penetrate the second insulating layer 132, thereby saving the third insulating layer 133. Alternatively, the second insulating layer 132 and the third insulating layer 133 can be provided. The second insulating layer 132 covers the channel gd region of the active layer py. The third insulating layer 133 directly covers the gate g and the non-channel region of the active layer py. The first electrode s and the second electrode d are arranged on the third insulating layer 133. The first through-hole k1 and the second through-hole k2 each penetrate the third insulating layer 133.

[0070] Optionally, the first through-hole k1 is circular, but is not limited thereto, and can also be rectangular, elliptical or other polygonal shapes, etc. The second through-hole k2 is circular, but is not limited thereto, and can also be rectangular, elliptical or other polygonal shapes, etc.

[0071] Optionally, the area of the first contact surface k11 is equal to the area of the second contact surface k21, but is not limited thereto, and the two can also be different.

[0072] Optionally, the material of the light shielding layer 12 can be an inorganic metal material such as chromium, molybdenum, manganese, etc., or a metal oxide material such as CrO x , MoO x , MnO2, etc., or a mixed film layer formed by a metal and a metal oxide; or an organic black resin material such as black polystyrene, black photoresist, etc.

[0073] The light shielding layer 12 can be an inorganic metal material such as chromium, molybdenum, manganese, etc. in a single-layer structure, or can be a multi-layer structure including a molybdenum-aluminum-molybdenum (Mo / Al / Mo) metal layer structure, an aluminum-molybdenum (Al / Mo) metal layer structure, a molybdenum-copper (Mo / Cu) metal layer structure, or a molybdenum-titanium-copper (Mo / Ti / Cu) metal layer structure, including but not limited to the above materials.

[0074] The light shielding layer 12 can also be reused as a signal trace.

[0075] The thickness of the light shielding layer 12 is between 400 angstroms and 5000 angstroms, such as 400 angstroms, 500 angstroms, 1000 angstroms, 2000 angstroms, 3000 angstroms, 4000 angstroms, or 5000 angstroms.

[0076] The slope angle a of the light shielding layer 12 is between 30 degrees and 90 degrees, such as 30 degrees, 35 degrees, 40 degrees, 45 degrees, 50 degrees, 55 degrees, 60 degrees, 65 degrees, 70 degrees, 75 degrees, 80 degrees, 85 degrees, or 90 degrees.

[0077] It can be understood that the greater the slope angle a of the light shielding layer 12, the greater the risk of the active layer py breaking in the slope area of the light shielding layer 12, so in order to reduce the risk of the active layer py breaking, the slope angle a can be less than or equal to 80 degrees.

[0078] Optionally, the active layer py can include polycrystalline silicon, monocrystalline silicon, amorphous silicon, or an oxide semiconductor. The first contact p1 and the second contact p2 are formed by conductorization of a semiconductor material. The first contact p1 and the second contact p2 each include a semiconductor layer and a dopant particle doped in the semiconductor layer, wherein the dopant particle is an N-type metal element, but is not limited thereto, such as a P-type metal element.

[0079] Optionally, the gate g, the first electrode s, and the second electrode d can be formed using a metal element selected from chromium, copper, aluminum, gold, silver, zinc, molybdenum, tantalum, titanium, tungsten, manganese, nickel, iron, neodymium, cobalt, an alloy including any of the above metal elements, or an alloy combining any of the above metal elements, etc. In addition, the gate g, the first electrode s, and the second electrode d can have a single-layer structure or a laminated structure of two or more layers.

[0080] Optionally, in some embodiments of the present application, in the top view of the array substrate 100, the part of the first contact surface k11 is located on the side of the profile edge Lk away from the light shielding layer 12.

[0081] It should be understood that the part of the first contact surface k11 is arranged outside the light shielding layer 12, so that the part of the first contact part p1 overlaps the light shielding layer 12, and the overlapping part does not need to climb, avoiding the risk of breaking due to climbing, and ensuring that the source electrode s and the active layer py are electrically connected; and the part of the first contact part p1 is arranged outside the light shielding layer 12, which can reduce the area of the light shielding layer 12, thereby improving the aperture ratio.

[0082] Optionally, in some embodiments of the present application, in the top view of the array substrate 100, the overlapping area of the first contact surface k11 and the light shielding layer 12 is a first area, and the first area is between 1 / 3 and 2 / 3 of the area of the first contact surface k11.

[0083] It should be understood that the larger the overlapping area of the first contact surface k11 and the light shielding layer 12, the larger the area of the light shielding layer 12 required, the smaller the aperture ratio, and the larger the planar connection area of the first electrode s and the first contact part p1, the better the connection stability. Therefore, selecting the first area to be between 1 / 3 and 2 / 3 of the area of the first contact surface k11 can meet the stability of electrical connection and better improve the aperture ratio.

[0084] Optionally, the first area can be 1 / 3, 1 / 2 or 2 / 3 of the area of the first contact surface k11, etc.

[0085] Optionally, in some embodiments of the present application, in the top view of the array substrate 100, the first contact part p1 and the channel gd are arranged and connected along the first direction F1.

[0086] The profile edge Lk includes a first side edge L1, and the first side edge L1 is arranged and extends along a second direction F2 intersecting the first direction F1, and the part of the first contact surface k11 is located on the side of the first side edge L1 away from the light shielding layer 12.

[0087] In FIG. 1, the first direction F1 is a vertical direction, and the second direction F2 is a horizontal direction, and the first direction F1 and the second direction F2 are perpendicular, but are not limited thereto, for example, the first direction F1 and the second direction F2 can be non-perpendicular.

[0088] Optionally, the profile edge Lk of the light shielding layer 12 is rectangular, but is not limited thereto, for example, it can be circular, elliptical, trapezoidal or polygonal, etc. It can be understood that the profile edge Lk of the light shielding layer 12 can be appropriately adjusted according to the shape of the active layer py.

[0089] Optionally, the contour edge Lk further comprises a second side edge L2, a third side edge L3 and a fourth side edge L4. The first side edge L1 and the second side edge L2 are oppositely arranged and extend along the second direction F2. The third side edge L3 and the fourth side edge L4 are oppositely arranged and extend along the first direction F1. The first side edge L1 is connected to the third side edge L3 and the fourth side edge L4, and the second side edge L2 is also connected to the third side edge L3 and the fourth side edge L4.

[0090] The active layer py extends along the first direction F1. The third side edge L3 and the fourth side edge L4 are both located outside the active layer py. The channel gd overlaps with the gate g.

[0091] Optionally, in some embodiments of the present application, in the top view of the array substrate 100, a part of the second contact surface k21 is located on the side of the contour edge Lk away from the light shielding layer 12.

[0092] It should be understood that the part of the second contact surface k21 arranged outside the light shielding layer 12 makes the part of the second contact portion p2 overlap with the light shielding layer 12, and the overlapping part does not need to climb, avoiding the risk of breaking due to climbing, and ensuring that the drain electrode d and the active layer py are electrically connected. The part of the second contact portion p2 arranged outside the light shielding layer 12 can reduce the area of the light shielding layer 12, thereby improving the aperture ratio.

[0093] Optionally, in the top view of the array substrate 100, the channel gd and the second contact portion p2 are arranged and connected along the first direction F1. A part of the second contact surface k21 is located on the side of the second side edge L2 away from the light shielding layer 12.

[0094] Optionally, in some embodiments of the present application, in the top view of the array substrate 100, the overlapping area of the second contact surface k21 and the light shielding layer 12 is a second area, and the second area is between 1 / 3 and 2 / 3 of the area of the second contact surface k21.

[0095] It should be understood that the larger the overlapping area of the second contact surface k21 and the light shielding layer 12, the larger the area of the light shielding layer 12 required, the smaller the aperture ratio, and the larger the planar connection area of the second electrode d and the second contact portion p2, and the better the connection stability. Therefore, selecting the second area to be between 1 / 3 and 2 / 3 of the area of the second contact surface k21 can not only meet the stability of electrical connection, but also better improve the aperture ratio.

[0096] Optionally, the second area can be 1 / 3, 1 / 2 or 2 / 3 of the area of the second contact surface k21, etc.

[0097] Compared with the prior art light shielding layer fully shielding the active layer, the planar area of the light shielding layer 12 of the array substrate 100 disclosed in FIG. 2 can be saved by 8% to 15%.

[0098] FIG. 3 shows an array substrate 100 according to one or more embodiments of the disclosure, and is a schematic plan view corresponding to FIG. 1. In FIG. 3, the parts different from the above-described embodiments will be described to avoid redundant elaboration.

[0099] Optionally, in some embodiments of the present application, the second contact part p2 includes a connecting sub-part p21 and a contact sub-part p22 connected to the connecting sub-part p21. In the top view of the array substrate 100, the channel gd and the connecting sub-part p21 are arranged and connected along the first direction F1, and the contact sub-part p22 is arranged along the second direction F2.

[0100] The profile edge Lk includes a second side edge L2 opposite to the first side edge L1, the second side edge L2 extending along the second direction F2, and a part of the second contact surface k21 and a part of the contact sub-part p22 are located on the side of the second side edge L2 away from the light shielding layer 12.

[0101] It should be understood that the second side edge L2 divides the contact sub-part p22 into two parts, and the part overlapping the light shielding layer 12 connects the connecting sub-part p21 and the second electrode d, to ensure the reliability of the electrical connection between the second electrode d and the active layer py.

[0102] And the part of the contact sub-part p22 is located outside the light shielding layer 12, which can further reduce the area of the light shielding layer 12, thereby improving the aperture ratio.

[0103] Optionally, in some embodiments of the present application, the profile edge Lk further includes a third side edge L3 connected between the first side edge L1 and the second side edge L2. The third side edge L3 extends along the first direction F1. A part of the second contact surface k21 and a part of the contact sub-part p22 are located on the side of the third side edge L3 away from the light shielding layer 12.

[0104] Wherein, the second contact surface k21 is cut by the second side edge L2 and the third side edge L3 at the same time, so that most of the area of the second contact surface k21 is outside the light shielding layer 12, further improving the aperture ratio.

[0105] Optionally, in the top view of the array substrate 100, the overlapping area of the second contact surface k21 and the light shielding layer 12 is a second area, and the second area is between 1 / 4 and 1 / 3 of the area of the second contact surface k21, such as 1 / 4, 7 / 24 or 1 / 3.

[0106] Optionally, the second area is 1 / 4 of the area of the second contact surface k21, so that the maximum width of the second area is the length of the radius of the second contact surface k21, ensuring the reliability of the connection between the second electrode d and the second contact part p2, while reducing the area of the light shielding layer 12 as much as possible to improve the aperture ratio.

[0107] In comparison with the prior art light-shielding layer fully shielding the active layer, the planar area of the light-shielding layer 12 of the array substrate 100 disclosed in FIG. 3 can be saved by 8% to 15%.

[0108] FIG. 4 shows the array substrate 100 according to one or more embodiments disclosed, and is a schematic plan view corresponding to FIG. 1. In FIG. 4, the parts different from the above-described embodiments will be described to avoid redundant elaboration.

[0109] Optionally, in some embodiments of the present application, the active layer py further comprises an intermediate portion p3, and the channel gd comprises a first channel gd1 and a second channel gd2 spaced from each other. The intermediate portion p3 comprises a first sub-portion p31, a second sub-portion p32 and a third sub-portion p33 connected in sequence. The first sub-portion p31 is connected to the first channel gd1, and the third sub-portion p33 is connected to the second channel gd2. The first contact portion p1 is connected to a side of the first channel gd1 away from the first sub-portion p31, and the second contact portion p2 is connected to a side of the second channel gd2 away from the third sub-portion p33.

[0110] In the top view of the array substrate 100, the first contact portion p1, the first channel gd1 and the first sub-portion p31 extend and are arranged along the first direction F1, the second sub-portion p32 extends along the second direction F2, and at least part of the second contact portion p2, the second channel gd2 and the third sub-portion p33 extend and are arranged along the first direction F1.

[0111] It can be understood that the active layer py has a double channel, and the thin film transistor tft of the double channel has better performance. The gate g extends along the second direction F2 and is arranged to overlap the first channel gd1 and the second channel gd2 at the same time. The intermediate portion p3 can be formed by conducting the semiconductor material. The intermediate portion p3 comprises a semiconductor layer and a dopant particle doped in the semiconductor layer, wherein the dopant particle is an N-type metal element, but is not limited thereto, for example, the dopant particle can also be a P-type metal element. The dopant particle in the intermediate portion p3 is the same as that of the first contact portion p1, which facilitates forming the first contact portion p1, the second contact portion p2 and the intermediate portion p3 in the same process.

[0112] In FIG. 4, the first contact portion p1 and the second contact portion p2 are located on the same side of the gate g. In the first direction F1, the first contact portion p1 and the second contact portion p2 are equal in distance or have a small gap to the respective connected channels gd.

[0113] In FIG. 4, the profile edge Lk of the light shielding layer 12 includes a first side edge L1, an opposite side edge L5, a third side edge L3 and a fourth side edge L4. The first side edge L1 and the opposite side edge L5 are oppositely arranged and extend along the second direction F2. The third side edge L3 and the fourth side edge L4 are oppositely arranged and extend along the first direction F1. The first side edge L1 is connected to the third side edge L3 and the fourth side edge L4, and the opposite side edge L5 is also connected to the third side edge L3 and the fourth side edge L4.

[0114] Optionally, in some embodiments of the present application, in the top view of the array substrate 100, the part of the second contact surface k21 is located on the side of the first side edge L1 away from the light shielding layer 12.

[0115] It should be noted that the part of the first contact surface k11 and the part of the second contact surface k21 are both located on the side of the first side edge L1 away from the light shielding layer 12, which facilitates the patterning of the light shielding layer 12 and reduces the difficulty of patterning the light shielding layer 12.

[0116] Optionally, the first area is between 1 / 3 and 2 / 3 of the area of the first contact surface k11. The second area is between 1 / 3 and 2 / 3 of the area of the second contact surface k21.

[0117] It should be understood that the larger the overlapping area of the first contact surface k11 and the second contact surface k21 with the light shielding layer 12, the larger the area of the light shielding layer 12 required, and the smaller the aperture ratio. The larger the planar connection area of the first electrode s and the first contact part p1 and the second electrode d and the second contact part p2, the better the stability of the connection. Therefore, selecting the first area to be between 1 / 3 and 2 / 3 of the area of the first contact surface k11 and the second area to be between 1 / 3 and 2 / 3 of the area of the second contact surface k21 can both satisfy the stability of the electrical connection and improve the aperture ratio.

[0118] Optionally, the first area can be 1 / 3, 1 / 2 or 2 / 3 of the area of the first contact surface k11. The second area can be 1 / 3, 1 / 2 or 2 / 3 of the area of the second contact surface k21.

[0119] Optionally, the first area is equal to the second area. The first area is half of the area of the first contact surface k11, and the second area is half of the area of the second contact surface k21.

[0120] Compared with the prior art light shielding layer that fully shields the active layer, the planar area of the light shielding layer 12 of the array substrate 100 disclosed in FIG. 4 can be saved by 5% to 10%.

[0121] FIG. 5 shows an array substrate 100 according to one or more embodiments of the disclosure, and is a schematic plan view corresponding to FIG. 1. In FIG. 5, portions different from the above-described embodiments will be described to avoid redundant elaboration.

[0122] In some embodiments of the present application, in the top view of the array substrate 100, the profile edge Lk further comprises an opposite side edge L5 opposite to the first side edge L1, and a part of the second sub-portion p32 is located on a side of the opposite side edge L5 away from the light shielding layer 12, and the part of the second sub-portion p32 overlapping the light shielding layer 12 is connected to the first sub-portion p31 and the third sub-portion p33.

[0123] It should be understood that the opposite side edge L5 divides the second sub-portion p32 into two parts, and the part overlapping the light shielding layer 12 is connected to the first sub-portion p31 and the third sub-portion p33 to ensure the reliability of the overall electrical connection of the active layer py.

[0124] And the part of the second sub-portion p32 located outside the light shielding layer 12 can further reduce the area of the light shielding layer 12, thereby improving the aperture ratio.

[0125] Among them, compared with the prior art of shielding the active layer, the planar area of the light shielding layer 12 of the array substrate 100 disclosed in FIG. 5 can save 10% to 14%.

[0126] FIG. 6 shows an array substrate 100 according to one or more embodiments of the disclosure, and is a schematic plan view corresponding to FIG. 1. In FIG. 6, portions different from the above-described embodiments will be described to avoid redundant elaboration.

[0127] In some embodiments of the present application, in the top view of the array substrate 100, the profile edge Lk further comprises a second side edge L2 and an intermediate side edge L6. Optionally, the intermediate side edge L6 extends along the first direction F1.

[0128] The second side edge L2 is parallel to the first side edge L1 and located on a side of the first side edge L1 close to the second channel gd2, and the intermediate side edge L6 is connected to the first side edge L1 and the second side edge L2. In the first direction F1, the length of the second contact portion p2 is less than the length of the first contact portion p1.

[0129] A part of the second contact surface k21 is located on a side of the second side edge L2 away from the light shielding layer 12.

[0130] It can be understood that by shortening the length of the second contact portion p2, the area of the light shielding layer 12 is reduced, and the aperture ratio is further improved.

[0131] Optionally, the first area is between 1 / 3 and 2 / 3 of the area of the first contact surface k11. The second area is between 1 / 3 and 2 / 3 of the area of the second contact surface k21.

[0132] It should be understood that the larger the overlapping areas of the first contact surface k11 and the second contact surface k21 with the light shielding layer 12, the larger the area of the light shielding layer 12 required, the smaller the aperture ratio, and the larger the planar connection area of the first electrode s and the first contact portion p1 and the second electrode d and the second contact portion p2, and the better the stability of the connection. Therefore, selecting the first area to be between 1 / 3 and 2 / 3 of the area of the first contact surface k11 and the second area to be between 1 / 3 and 2 / 3 of the area of the second contact surface k21 can both satisfy the stability of the electrical connection and better improve the aperture ratio.

[0133] Optionally, the first area can be 1 / 3, 1 / 2, or 2 / 3 of the area of the first contact surface k11. The second area can be 1 / 3, 1 / 2, or 2 / 3 of the area of the second contact surface k21.

[0134] Optionally, the first area is equal to the second area. The first area is half of the area of the first contact surface k11, and the second area is half of the area of the second contact surface k21.

[0135] Compared with the prior art in which the light shielding layer fully shields the active layer, the planar area of the light shielding layer 12 of the array substrate 100 disclosed in FIG. 6 can be saved by 15% to 20%.

[0136] FIG. 7 shows an array substrate 100 according to one or more embodiments disclosed, and is a schematic plan view corresponding to FIG. 1. In FIG. 7, only the parts different from the above-described embodiments will be described to avoid redundant elaboration.

[0137] In some embodiments of the present application, the second contact portion p2 includes a connection sub-portion p21 and a contact sub-portion p22 connected to the connection sub-portion p21. In the top view of the array substrate 100, the connection sub-portion p21, the second channel gd2, and the third sub-portion p33 extend and are arranged along the first direction F1, and the contact sub-portion p22 extends and is arranged along the second direction F2.

[0138] The contour edge Lk further includes a second side edge L2 and an intermediate side edge L6 and a third side edge L3. The second side edge L2 is parallel to the first side edge L1 and is located on the side of the first side edge L1 close to the second channel gd2. The intermediate side edge L6 is connected to the first side edge L1 and the second side edge L2. The third side edge L3 extends and is arranged along the first direction F1 and is connected to the side of the second side edge L2 away from the first side edge L1. In the first direction F1, the length of the second contact portion p2 is smaller than the length of the first contact portion p1.

[0139] The partial second contact surface k21 is located on the side of the second side edge L2 away from the light shielding layer 12, and the partial second contact surface k21 is located on the side of the third side edge L3 away from the light shielding layer 12.

[0140] It should be noted that the second contact part p2 adopts a bending design, and the second contact surface k21 can be arranged at the intersection of the second side edge L2 and the third side edge L3, so as to further reduce the area of the light shielding layer 12, thereby improving the aperture ratio.

[0141] Optionally, the first area is between 1 / 3 and 2 / 3 of the area of the first contact surface k11. The second area is between 1 / 3 and 2 / 3 of the area of the second contact surface k21.

[0142] It should be understood that the greater the overlapping area of the first contact surface k11 and the second contact surface k21 with the light shielding layer 12, the greater the area of the light shielding layer 12 required, and the smaller the aperture ratio. The larger the planar connection area of the first electrode s and the first contact part p1 and the second electrode d and the second contact part p2, the better the stability of the connection. Therefore, selecting the first area to be between 1 / 3 and 2 / 3 of the area of the first contact surface k11 and the second area to be between 1 / 3 and 2 / 3 of the area of the second contact surface k21 can meet the stability of the electrical connection and improve the aperture ratio.

[0143] Optionally, the first area can be 1 / 3, 1 / 2 or 2 / 3 of the area of the first contact surface k11. The second area can be 1 / 3, 1 / 2 or 2 / 3 of the area of the second contact surface k21.

[0144] Optionally, the second area is between 1 / 4 and 1 / 3 of the area of the second contact surface k21, such as 1 / 4, 7 / 24 or 1 / 3.

[0145] Optionally, the second area is 1 / 4 of the area of the second contact surface k21, so that the maximum width of the second area is the radius length of the second contact surface k21, which ensures the reliability of the connection between the second electrode d and the second contact part p2 while reducing the area of the light shielding layer 12 as much as possible to improve the aperture ratio.

[0146] Compared with the prior art in which the light shielding layer fully shields the active layer, the planar area of the light shielding layer 12 of the array substrate 100 disclosed in FIG. 7 can be saved by 20% to 23%.

[0147] Referring to FIG. 8, the application also provides a display panel 1000 comprising the array substrate 100 according to any one of the above embodiments.

[0148] It should be noted that the structure of the array substrate 100 is similar or identical to the structure of the array substrate 100 of any one of the above embodiments, and thus will not be described again here.

[0149] Optionally, the display panel 1000 further comprises a counter substrate 200 and a liquid crystal layer 300 disposed between the array substrate 100 and the counter substrate 200.

[0150] In some embodiments, the display panel 1000 can also be an electroluminescent display panel, such as an organic light-emitting diode display panel.

[0151] The array substrate of the embodiments of the present application comprises a light shielding layer and a thin film transistor disposed on the light shielding layer. In the top view of the array substrate, the light shielding layer has a profile edge, at least one of the first contact surface and the second contact surface has an overlapping area with the light shielding layer, and the active layer has a non-overlapping area with the light shielding layer. That is, at least part of the first contact surface and / or the second contact surface is disposed within the light shielding layer to ensure that part of the first contact portion and / or the second contact portion overlaps with the light shielding layer. The overlapping part does not need to climb, avoiding the risk of breaking due to climbing, and ensuring that the source and the drain are electrically connected to the active layer, respectively. The active layer has a non-overlapping area with the light shielding layer, so that part of the first contact portion and / or the second contact portion is disposed outside the light shielding layer, which can reduce the area of the light shielding layer and thus improve the aperture ratio.

[0152] The above describes in detail the array substrate and the display panel provided by the embodiments of the present application. The principles and implementation manners of the present application are described by applying specific examples. The above description of the embodiments is only used to help understand the method of the present application and its core idea. Meanwhile, for those skilled in the art, according to the idea of the present application, the specific implementation manner and application range will be changed. In summary, the content of the specification should not be understood as a limitation of the present application.

Claims

1. An array substrate, comprising: a substrate; a light shielding layer disposed on the substrate; a first insulating layer disposed on a side of the light shielding layer away from the substrate; an active layer disposed on a side of the first insulating layer away from the substrate, the active layer comprising a first contact portion, a channel, and a second contact portion; a gate disposed on a side of the active layer away from the substrate and different from the active layer; an insulating structure layer disposed on a side of the active layer away from the substrate, the insulating structure layer being provided with a first through hole and a second through hole, the first through hole exposing the first contact portion, and the second through hole exposing the second contact portion; and a first electrode and a second electrode disposed on a side of the insulating structure layer away from the substrate, the first electrode covering the first through hole and connected to the first contact portion, the second electrode covering the second through hole and connected to the second contact portion, the first electrode having a first contact surface with the first contact portion, and the second electrode having a second contact surface with the second contact portion; wherein, in a top view of the array substrate, at least one of the first contact surface and the second contact surface has an overlapping area with the light shielding layer, and the active layer has a non-overlapping area with the light shielding layer.

2. The array substrate according to claim 1, wherein, In the top view of the array substrate, at least one of the first contact surface and the second contact surface has a partial overlapping area with the light shielding layer, and the active layer has a partial overlapping area with the light shielding layer.

3. The array substrate according to claim 2, wherein, In the top view of the array substrate, the light shielding layer has a profile edge, and a portion of the first contact surface is located on a side of the profile edge away from the light shielding layer.

4. The array substrate according to claim 3, wherein, In the top view of the array substrate, the first contact portion and the channel are arranged and connected along a first direction. The profile edge comprises a first side edge extending along a second direction intersecting the first direction, and a portion of the first contact surface is located on a side of the first side edge away from the light shielding layer.

5. The array substrate according to claim 4, wherein, In the top view of the array substrate, an overlapping area of the first contact surface with the light shielding layer is a first area, and the first area is between 1 / 3 and 2 / 3 of an area of the first contact surface.

6. The array substrate according to claim 4, wherein, In the top view of the array substrate, the light shielding layer has a profile edge, and a portion of the second contact surface is located on a side of the profile edge away from the light shielding layer.

7. The array substrate according to claim 6, wherein, In the top view of the array substrate, the channel and the second contact portion are arranged and connected along the first direction. The profile edge comprises a second side edge opposite to the first side edge and extending along the second direction, and a portion of the second contact surface is located on a side of the second side edge away from the light shielding layer.

8. The array substrate of claim 6, wherein, The second contact portion comprises a connecting sub-portion and a contact sub-portion connected to the connecting sub-portion, in the top view of the array substrate, the channel and the connecting sub-portion are arranged and connected along a first direction, and the contact sub-portion extends along a second direction. The profiled edge further comprises a second side edge opposite to the first side edge, the second side edge extends along the second direction, and a part of the second contact surface and a part of the contact sub-portion are located on a side of the second side edge away from the light shielding layer.

9. The array substrate of claim 8, wherein, The profiled edge further comprises a third side edge connected between the first side edge and the second side edge, the third side edge extends along the first direction, and a part of the second contact surface and a part of the contact sub-portion are located on a side of the third side edge away from the light shielding layer.

10. The array substrate of claim 6, wherein, The active layer further comprises an intermediate portion, the channel comprises a first channel and a second channel spaced from each other, the intermediate portion comprises a first sub-portion, a second sub-portion and a third sub-portion connected in sequence, the first sub-portion is connected to the first channel, the third sub-portion is connected to the second channel, the first contact portion is connected to a side of the first channel away from the first sub-portion, and the second contact portion is connected to a side of the second channel away from the third sub-portion; In a top view of the array substrate, the first contact portion, the first channel and the first sub-portion extend and arrange along the first direction, the second sub-portion extends along the second direction, and at least part of the second contact portion, the second channel and the third sub-portion extend and arrange along the first direction.

11. The array substrate of claim 10, wherein, In a top view of the array substrate, a part of the second contact surface is located on a side of the first side edge away from the light shielding layer.

12. The array substrate of claim 10, wherein, In a top view of the array substrate, the profiled edge further comprises a second side edge and an intermediate side edge, the second side edge is parallel to the first side edge and located on a side of the first side edge close to the second channel, and the intermediate side edge is connected between the first side edge and the second side edge; in the first direction, a length of the second contact portion is smaller than a length of the first contact portion. A part of the second contact surface is located on a side of the second side edge away from the light shielding layer.

13. The array substrate of claim 10, wherein, The second contact portion comprises a connecting sub-portion and a contact sub-portion connected to the connecting sub-portion, in a top view of the array substrate, the connecting sub-portion, the second channel and the third sub-portion extend and arrange along the first direction, and the contact sub-portion extends along the second direction; The profiled edge further comprises a second side edge, an intermediate side edge and a third side edge, the second side edge is parallel to the first side edge and located on a side of the first side edge close to the second channel, the intermediate side edge is connected between the first side edge and the second side edge, and the third side edge extends along the first direction and is connected to a side of the second side edge away from the first side edge; in the first direction, a length of the second contact portion is smaller than a length of the first contact portion. A part of the second contact surface is located on a side of the second side edge away from the light shielding layer, and a part of the second contact surface is located on a side of the third side edge away from the light shielding layer.

14. The array substrate according to any one of claims 10 to 13, wherein, In a top view of the array substrate, the profiled edge further comprises an opposite side edge opposite to the first side edge, and the second sub-portion is located on a side of the opposite side edge away from the light shielding layer, and the portion of the second sub-portion overlapping the light shielding layer is connected to the first sub-portion and the third sub-portion.

15. The array substrate according to any one of claims 7, 11-12, wherein, In a top view of the array substrate, an overlapping area of the second contact surface and the light shielding layer is a second area, and the second area is between 1 / 3 and 2 / 3 of an area of the second contact surface.

16. The array substrate according to claim 9 or 13, wherein, In a top view of the array substrate, an overlapping area of the second contact surface and the light shielding layer is a second area, and the second area is between 1 / 4 and 1 / 3 of an area of the second contact surface.

17. A display panel comprising an array substrate, the array substrate comprising: a substrate; a light shielding layer disposed on the substrate; a first insulating layer disposed on a side of the light shielding layer away from the substrate; an active layer disposed on a side of the first insulating layer away from the substrate, the active layer comprising a first contact portion, a channel, and a second contact portion; a gate disposed on a side of the active layer away from the substrate and different from the active layer; an insulating structure layer disposed on a side of the active layer away from the substrate, the insulating structure layer being provided with a first through hole and a second through hole, the first through hole exposing the first contact portion, and the second through hole exposing the second contact portion; and a first electrode and a second electrode disposed on a side of the insulating structure layer away from the substrate, the first electrode covering the first through hole and connected to the first contact portion, the second electrode covering the second through hole and connected to the second contact portion, the first electrode having a first contact surface with the first contact portion, and the second electrode having a second contact surface with the second contact portion; wherein, in a top view of the array substrate, at least one of the first contact surface and the second contact surface has an overlapping area with the light shielding layer, and the active layer has a non-overlapping area with the light shielding layer.

18. The display panel of claim 17, wherein, In a top view of the array substrate, at least one of the first contact surface and the second contact surface has a partial overlapping area with the light shielding layer, and the active layer has a partial overlapping area with the light shielding layer.

19. The display panel of claim 18, wherein, In a top view of the array substrate, the light shielding layer has a profiled edge, and a portion of the first contact surface is located on a side of the profiled edge away from the light shielding layer.

20. The display panel of claim 19, wherein, In a top view of the array substrate, the first contact portion and the channel are arranged and connected along a first direction; the profiled edge comprises a first side edge extending along a second direction intersecting the first direction, and a portion of the first contact surface is located on a side of the first side edge away from the light shielding layer.

Images