Memory chip and manufacturing method therefor, memory, and electronic device

Abstract

The present application relates to the field of storage, and provides a memory chip and a manufacturing method therefor, a memory, and an electronic device. By disposing a plate line driver circuit on a second chip other than a first chip, the orthographic projection of the plate line driver circuit on a first substrate at least partially overlaps the orthographic projection of a memory array on the first substrate, thereby improving AE of the memory and increasing the capacity density thereof. The memory chip comprises a first chip and a second chip. The first chip comprises a first substrate, and a memory array and a plate line that are disposed on the first substrate. The memory array comprises a plurality of ferroelectric memory cells, and the ferroelectric memory cells are electrically connected to the plate line. The second chip comprises a second substrate, and a plate line driver circuit disposed on the second substrate. The second chip and the first chip are stacked. The memory array, the plate line, and the plate line driver circuit are located between the first substrate and the second substrate. The plate line driver circuit is electrically connected to the plate line. The orthographic projections of the plate line driver circuit and the memory array on the first substrate at least partially overlap.

Description

Memory chip, preparation method thereof, memory and electronic device

[0001] The present application claims priority to the Chinese patent application No. 202411066959.5, filed on August 5, 2024, and entitled "Memory chip, preparation method thereof, memory and electronic device", the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] Embodiments of the present application relate to the field of storage, and in particular to a memory chip, a preparation method thereof, a memory and an electronic device. BACKGROUND

[0003] In recent years, as the size of the traditional 1T1C (one transistor one capacitor) dynamic random-access memory (DRAM) gradually encounters bottlenecks in miniaturization, ferroelectric random-access memory (FeRAM) based on 1TnC (one transistor n capacitors, n is a positive integer) has become an important option for further improving the integration density of the memory.

[0004] The ferroelectric memory includes a ferroelectric memory array, a word line driver, a plate line driver, a sense amplifier, and the like. The ferroelectric memory array includes a word line (WL), a bit line (BL), a plate line (PL), and the like. Among them, the main body of the word line driver, the sense amplifier, and the plate line driver, which are complementary metal oxide semiconductor (CMOS) devices, are prepared by a front end of line (FEOL) process, and the ferroelectric memory array is prepared by a back end of line (BEOL) process.

[0005] In the prior art, the sense amplifier can be covered by the ferroelectric memory array, but the plate line driving circuit cannot be completely covered by the ferroelectric memory array, at least part of the plate line driving circuit is located outside the projection periphery of the ferroelectric memory array, thereby reducing the array efficiency (AE) of the ferroelectric memory. Moreover, the capacitor and the plate line electrically connected with the capacitor are connected to the conductive layer on the side of the memory array away from the substrate through a via hole, and the conductive layer is connected to the plate line driving circuit arranged between the substrate and the ferroelectric memory array through a deep hole. The deep hole has a large depth, and the resistivity of the metal material filled in the deep hole is usually high. The deeper the deep hole, the greater the resistance on the link between the plate line and the plate line driving circuit, thereby prolonging the transition time of the pull-up and pull-down on the plate line. SUMMARY

[0006] To solve the above technical problems, the present application provides a storage chip and a preparation method thereof, a memory, and an electronic device. By arranging the plate line driving circuit on the second chip other than the first chip, the orthographic projection of the plate line driving circuit and the memory array on the first substrate at least partially overlaps, thereby improving the AE of the memory and improving the capacity density.

[0007] In a first aspect, the present application provides a storage chip, which includes a first chip and a second chip. The first chip includes a first substrate, and a memory array and a plate line arranged on the first substrate; the memory array includes a plurality of ferroelectric memory cells, and the ferroelectric memory cells are electrically connected with the plate line. The second chip includes a second substrate, and a plate line driving circuit arranged on the second substrate; the second chip is conjugated with the first chip, the memory array, the plate line, and the plate line driving circuit are located between the first substrate and the second substrate, and the plate line driving circuit is electrically connected with the plate line. Wherein, the orthographic projection of the plate line driving circuit and the memory array on the first substrate at least partially overlaps.

[0008] In the present application, the storage array and the plate line are manufactured on the first chip, the plate line driving circuit is manufactured on the second chip other than the first chip, and the plate line driving circuit and the plate line are interconnected by stacking the first chip and the second chip. In the embodiments of the present application, the plate line driving circuit is arranged on the second chip other than the first chip, so that the orthographic projection of the plate line driving circuit and the storage array on the first substrate at least partially overlaps. In this way, the plate line driving circuit is arranged more in the projection range of the storage array, the area outside the projection of the storage array is greatly reduced, the area constraint of the chip caused by the plate line driving circuit is eliminated, and the AE of the memory is improved, and the capacity density is improved. At the same time, the present application can realize the electrical connection between the plate line and the plate line driving circuit at the connection between the first chip and the second chip. As mentioned above, the plate line can be prepared by a subsequent process, so it is only necessary to lead the plate line to the connection between the first chip and the second chip. It is not necessary to use the conductive layer on the side of the plate line away from the first substrate and the deep hole connecting the conductive layer and the plate line driving circuit to realize the electrical connection between the plate line and the plate line driving circuit. Therefore, the embodiments of the present application can also avoid the large resistance on the link between the plate line and the plate line driving circuit caused by the large depth of the deep hole and the filling of the metal material with high resistivity in the deep hole, thereby causing the long conversion time of the pull-up and pull-down on the plate line.

[0009] In some possible implementations, the first chip further includes a first conductive lead, and the second chip further includes a second conductive lead. The first conductive lead is arranged on the side of the storage array and the plate line away from the first substrate, and the second conductive lead is arranged on the side of the plate line driving circuit away from the second substrate. The plate line is in one-to-one correspondence with and electrically connected to the first conductive lead and the second conductive lead, and the plate line driving circuit is electrically connected to the plate line through the second conductive lead and the first conductive lead to apply a voltage to the plurality of plate lines through the second conductive lead and the first conductive lead.

[0010] In some possible implementations, the first chip further includes a first dielectric layer arranged on the side of the first conductive lead away from the first substrate, and a first via hole is formed in the first dielectric layer. The second chip further includes a second dielectric layer arranged on the side of the second conductive lead away from the second substrate, and a second via hole is formed in the second dielectric layer. The first via hole and the second via hole are filled with a conductive material, and the memory chip further includes a conductive structure arranged between the first dielectric layer and the second dielectric layer. The first conductive lead is electrically connected to the second conductive lead corresponding thereto through the first via hole, the conductive structure, and the second via hole.

[0011] In this way, the plate line is led out to the conductive structure through the first conductive lead and the conductive material in the first via hole, and the plate line driving circuit is led out to the conductive structure through the second conductive lead and the conductive material in the second via hole, and finally the plate line driving circuit and the plate line are electrically connected.

[0012] In some possible implementation manners, if the first chip and the second chip are fixedly connected through a welding process, the conductive structure is a solder ball, and the first chip and the second chip are fixedly connected through the solder ball.

[0013] Alternatively, the first chip and the second chip are fixedly connected through hybrid bonding, and the conductive structure includes a first metal sheet and a second metal sheet, the first metal sheet is embedded into one side of the first dielectric layer facing the second dielectric layer, and the second metal sheet is embedded into one side of the second dielectric layer facing the first dielectric layer.

[0014] Both of the above two manners can achieve fixed connection of the first chip and the second chip, and can also make the plate line in the first chip be led out to the conductive structure at the connection position through the first conductive lead, and make the plate line driving circuit in the second chip be led out to the conductive structure at the connection position through the second conductive lead, so as to achieve electrical connection of the plate line in the first chip and the plate line driving circuit in the second chip.

[0015] In some possible implementation manners, the first chip further includes a comparator and a word line driving circuit, the comparator and the word line driving circuit are arranged between the first substrate and the storage array, and a projection of the comparator on the first substrate at least partially overlaps with a projection of the storage array on the first substrate, so as to avoid AE reduction of the memory caused by the fact that the sensitive amplifier is arranged outside the projection periphery of the storage array.

[0016] In some possible implementation manners, the ferroelectric storage unit includes a transistor and at least one ferroelectric capacitor, the ferroelectric capacitor stores information based on a ferroelectric effect, and can have a larger dielectric constant and a smaller volume relative to a traditional capacitor. The first chip further includes a word line and a bit line, the transistor includes a gate, a first electrode and a second electrode, and the ferroelectric capacitor includes a first electrode and a second electrode. The gate is electrically connected with the word line, the first electrode is electrically connected with the bit line, the second electrode is electrically connected with the first electrode, and the second electrode is electrically connected with the plate line.

[0017] When an electric field is applied to the transistor of the storage unit, the central atoms stay in a low-energy state along the direction of the electric field; conversely, when the electric field is reversed and applied to the transistor, the central atoms move in the crystal along the direction of the electric field and stay in another low-energy state. A large number of central atoms moving in the crystal cell are coupled to form a ferroelectric domain, and the ferroelectric domain forms a polarization charge under the action of the electric field. The polarization charge formed by the ferroelectric domain under the electric field without inversion is higher, and the polarization charge formed by the ferroelectric domain under the electric field with inversion is lower. The binary stable state of such ferroelectric material makes the ferroelectric material be used as a memory.

[0018] In a second aspect, the present application provides a memory including a controller and the storage chip of the first aspect, the controller being configured to control the storage array in the storage chip to read and write data.

[0019] The second aspect and any kind of implementation manner of the second aspect correspond to the first aspect and any kind of implementation manner of the first aspect respectively. The technical effects corresponding to the second aspect and any kind of implementation manner of the second aspect can refer to the technical effects corresponding to the first aspect and any kind of implementation manner of the first aspect, which will not be described herein again.

[0020] In a third aspect, the present application provides an electronic device, which comprises a processor and the memory of the second aspect, and the processor is configured to read and write data from and to the memory through the controller.

[0021] The third aspect and any kind of implementation manner of the third aspect correspond to the first aspect and any kind of implementation manner of the first aspect respectively. The technical effects corresponding to the third aspect and any kind of implementation manner of the third aspect can refer to the technical effects corresponding to the first aspect and any kind of implementation manner of the first aspect, which will not be described herein again.

[0022] In a fourth aspect, the present application provides a preparation method of a memory chip, which comprises: forming a memory array and a plate line on a first substrate to obtain a first chip; forming a plate line driving circuit on a second substrate to obtain a second chip; the memory array comprises a plurality of ferroelectric memory cells, and the ferroelectric memory cells are electrically connected with the plate line; and stacking the first chip and the second chip, the memory array, the plate line, and the plate line driving circuit are located between the first substrate and the second substrate, the plate line driving circuit is electrically connected with the plate line; wherein the projection of the plate line driving circuit and the memory array on the first substrate at least partially overlaps.

[0023] In some possible implementation manners, after the memory array and the plate line are formed on the first substrate, and the plate line driving circuit is formed on the second substrate, before the first chip and the second chip are stacked, the preparation method of the memory chip further comprises: forming a first conductive lead on a side of the memory array and the plate line away from the first substrate; forming a second conductive lead on a side of the plate line driving circuit away from the second substrate; the plate line is one-to-one corresponding and electrically connected with the first conductive lead and the second conductive lead, and the plate line driving circuit is electrically connected with the plate line through the second conductive lead and the first conductive lead.

[0024] In some possible implementation manners, after the first conductive lead is formed on the side of the storage array and the plate line away from the first substrate, the preparation method of the storage chip further includes: forming a first dielectric layer on the side of the first conductive lead away from the first substrate, a first through hole is formed in the first dielectric layer, and a conductive material is filled in the first through hole. After the second conductive lead is formed on the side of the plate line driving circuit away from the second substrate, the preparation method of the storage chip further includes: forming a second dielectric layer on the side of the second conductive lead away from the second substrate, a second through hole is formed in the second dielectric layer, and a conductive material is filled in the second through hole. The first chip and the second chip are stacked and arranged, including: forming a conductive structure between the first dielectric layer and the second dielectric layer, and the first conductive lead is electrically connected through the first through hole, the conductive structure, and the second through hole and the second conductive lead corresponding to the second through hole.

[0025] In some possible implementation manners, the first chip and the second chip are stacked and arranged, including: welding the first chip and the second chip, and the conductive structure is a solder ball.

[0026] Alternatively, the first chip and the second chip are stacked and arranged, including: forming a first recess in the first dielectric layer and a second recess in the second dielectric layer; the opening of the first recess faces the second dielectric layer, and the opening of the second recess faces the first dielectric layer. Then, a first metal sheet is filled in the first recess, and a second metal sheet is filled in the second recess. Then, the first chip and the second chip are bonded.

[0027] The fourth aspect and any one of the implementation manners of the fourth aspect correspond to the first aspect and any one of the implementation manners of the first aspect respectively. For technical effects corresponding to the first aspect and any one of the implementation manners of the first aspect, refer to the above description, which will not be described here again. BRIEF DESCRIPTION OF DRAWINGS

[0028] FIG. 1a is a block diagram of modules in an electronic device according to an embodiment of the present application;

[0029] FIG. 1b is an interaction diagram of modules in a memory according to an embodiment of the present application;

[0030] FIG. 2a is a circuit diagram of a ferroelectric storage array according to an embodiment of the present application;

[0031] FIG. 2b is a circuit diagram of a ferroelectric storage array according to an embodiment of the present application;

[0032] FIG. 3 is a circuit diagram of a ferroelectric storage array according to an embodiment of the present application;

[0033] FIG. 4 is a diagram of arrangement positions of modules in a storage chip according to the related art;

[0034] Fig. 5 is a structural schematic diagram of a storage chip provided by an embodiment of the present application;

[0035] Fig. 6 is a structural schematic diagram of a storage chip provided by an embodiment of the present application;

[0036] Fig. 7 is a structural schematic diagram of a storage chip provided by an embodiment of the present application;

[0037] Fig. 8 is a structural schematic diagram of a storage chip provided by an embodiment of the present application;

[0038] Fig. 9a is a preparation process diagram of a storage chip provided by an embodiment of the present application;

[0039] Fig. 9b is a preparation process diagram of a storage chip provided by an embodiment of the present application;

[0040] Fig. 9c is a preparation process diagram of a storage chip provided by an embodiment of the present application;

[0041] Fig. 10 is a preparation flow diagram of a storage chip provided by an embodiment of the present application;

[0042] Fig. 11a is a preparation process diagram of a storage chip provided by an embodiment of the present application;

[0043] Fig. 11b is a preparation process diagram of a storage chip provided by an embodiment of the present application;

[0044] Fig. 12a is a preparation process diagram of a storage chip provided by an embodiment of the present application;

[0045] Fig. 12b is a preparation process diagram of a storage chip provided by an embodiment of the present application. DETAILED DESCRIPTION

[0046] The technical solutions in the embodiments of the present application will be clearly and completely described with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are some, but not all of the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art without creative work fall within the protection scope of the present application.

[0047] The term "and / or" in the present application is only used to describe the association relationship of the associated objects, which means that there can be three relationships, for example, A and / or B can mean that A exists alone, A and B exist together, and B exists alone.

[0048] The terms "first" and "second" and the like in the specification and claims of the embodiments of the present application are used to distinguish different objects, and are not used to describe a specific order of the objects. For example, the first target object and the second target object are used to distinguish different target objects, and are not used to describe a specific order of the target objects.

[0049] In the embodiments of the present application, the word "exemplary" or "for example" is used to mean serving as an example, instance, or illustration. Any embodiment or design presented as "exemplary" or "for example" in the embodiments of the present application is not necessarily to be construed as preferred or advantageous over other embodiments or designs. Rather, use of the word "exemplary" or "for example" is intended to present concepts in a concrete manner.

[0050] In the description of the embodiments of the present application, the meaning of "plurality" is two or more, unless otherwise specified. For example, a plurality of processing units means two or more processing units; a plurality of systems means two or more systems.

[0051] The embodiments of the present application provide an electronic device, which can be a consumer electronic product, a home electronic product, a vehicle-mounted electronic product, a financial terminal product, a communication electronic product, and the like, including a memory.

[0052] The consumer electronic product is, for example, a mobile phone, a tablet computer, a notebook computer, a personal computer (PC), a personal digital assistant (PDA), a smart wearable product (for example, a smart watch, a smart bracelet, and the like), a virtual reality (VR) terminal device, an augmented reality (AR) terminal device, a drone, and the like. The home electronic product is, for example, a smart door lock, a television, a smart sound box, a refrigerator, a sweeping robot, and the like. The vehicle-mounted electronic product is, for example, a vehicle-mounted navigator, a vehicle-mounted display, and the like. The financial terminal product is, for example, an automated teller machine (ATM) machine, a self-service terminal, and the like. The communication electronic product is, for example, a server, a memory, a radar, a base station, and the like.

[0053] FIG. 1a is a structural schematic diagram of a memory in an electronic device provided by the present application. The electronic device includes a memory and other chips or independent devices, which can include a processor. As shown in FIG. 1b, the memory includes a storage array, a controller, a row decoder, a column decoder, and the like. The processor can send an address of a selected storage unit to the row decoder and the column decoder through the controller. After decoding the received address, the row decoder and the column decoder determine a storage unit in the storage array as the selected storage unit, and then perform a read-write operation on the selected storage unit.

[0054] In some embodiments, the memory of the present application can be ferroelectric memory, which includes ferroelectric random access memory (FeRAM or FRAM) and ferroelectric field-effect transistor (FeFET) memory. As a new type of memory, ferroelectric memory has greater performance than traditional DRAM in terms of non-volatility, capacity density, etc. The storage unit in the ferroelectric memory includes a transistor and a ferroelectric capacitor, and the ferroelectric capacitor stores information based on the ferroelectric effect. The ferroelectric capacitor includes two electrodes and a ferroelectric material, such as a ferroelectric thin film, disposed between the two electrodes. Due to the nonlinear characteristics of the ferroelectric material, the dielectric constant of the ferroelectric material can not only be adjusted, but also become very large near the phase transition temperature. Therefore, compared with traditional capacitors, the ferroelectric capacitor can have a larger dielectric constant and a smaller volume.

[0055] The working principle of the ferroelectric memory is as follows: when an electric field is applied to the ferroelectric capacitor of the storage unit, the central atoms stay in a low-energy state along the direction of the electric field; on the contrary, when the electric field is reversed and applied to the ferroelectric capacitor, the central atoms move in the crystal along the direction of the electric field and stay in another low-energy state. A large number of central atoms move in the crystal unit cell to form a ferroelectric domain, and the ferroelectric domain forms a polarization charge under the action of the electric field. The polarization charge formed by the ferroelectric domain under the electric field is high, and the polarization charge formed by the ferroelectric domain without inversion under the electric field is low. The binary stable state of such ferroelectric material makes the ferroelectric material can be used as a memory. The ferroelectric thin film can use common ferroelectric materials, such as Hf 0.5 Zr 0.5 O2, or antiferromagnetic materials such as PbZrO3, NH4H2PO4, etc.

[0056] FIGS. 2a and 2b show a circuit diagram of a storage array including a plurality of storage units, each of which includes a transistor and a ferroelectric capacitor connected to the transistor. For each storage unit, the gate of the transistor is connected to a word line WL, the first electrode is connected to a bit line BL, and the second electrode is connected to a plate line PL through the ferroelectric capacitor.

[0057] FIG. 2a shows that in a storage unit, the second electrode of a transistor is electrically connected to a ferroelectric capacitor. FIG. 2b shows that in a storage unit, the second electrode of a transistor is electrically connected to a plurality of ferroelectric capacitors. The node at which the second electrode of the transistor is electrically connected to the ferroelectric capacitor can be node FN.

[0058] As shown in FIG. 3, in addition to the storage array shown in FIG. 2a and FIG. 2b, the ferroelectric memory further includes a plate line driving (PL Driver) circuit, a word line driving (WL Driver) circuit, a comparator (e.g., a sense amplifier SA), etc. Among them, the plate line driving circuit is electrically connected with a plurality of plate lines PL, and is configured to apply different voltage values to the plate lines PL in different stages; the word line driving circuit is electrically connected with a plurality of word lines WL, and is configured to apply different voltage values to the word lines WL in different stages; the sense amplifier SA is electrically connected with a bit line BL, and is configured to read data or write data to the storage unit.

[0059] As mentioned in the background, the word line driving circuit, the sense amplifier, the plate line driving circuit, the storage array, the plate line PL, etc. are all arranged on the same chip. Among them, the main body of the word line driving circuit, the sense amplifier, and the plate line driving circuit CMOS device is prepared by a front-end process, and the storage array, the plate line PL, etc. are prepared by a back-end process. That is, the word line driving circuit, the sense amplifier, and the plate line driving circuit are usually arranged between the substrate and the storage array.

[0060] As shown in FIG. 4, the sense amplifier 13 can be usually covered by the storage array 14, while the plate line driving circuit 11 cannot be completely covered by the storage array 14, at least part of the plate line driving circuit 11 is located outside the projection periphery of the storage array 14, thereby causing the AE of the memory to decrease. In order to improve the AE, the related art compresses the area of each peripheral driving circuit (such as the plate line driving circuit) as much as possible. However, the area of the sense amplifier 13 is relatively large, and it is not suitable to be compressed too much, and it will almost occupy the entire position directly below the storage array 14.

[0061] In addition, the capacitor and the plate line PL electrically connected with the capacitor are connected to the conductive layer on the side of the storage array 14 away from the substrate through a via, and then the conductive layer is connected to the plate line driving circuit 11 arranged between the substrate 10 and the storage array 14 through a deep hole. The depth of the deep hole is large, and the resistivity of the metal material filled in the deep hole is usually high. The deeper the depth of the deep hole is, the greater the resistance on the link between the plate line PL and the plate line driving circuit 11 is, thereby causing the conversion time of the pull-up and pull-down on the plate line PL to be longer.

[0062] Based on this, as shown in FIG. 5, the embodiment of the present application provides a storage chip, and the memory can include the storage chip. The storage chip includes a first chip 20 and a second chip 30. The storage array 14 is arranged on the first chip 20, the plate line driving circuit 11 is arranged on the second chip 30, and the relative positions of the storage array 14 and the plate line driving circuit 11 are reasonably designed, so as to improve the AE of the memory.

[0063] Specifically, the memory chip includes a first chip 20 and a second chip 30. The first chip 20 includes a first substrate 21, and a memory array 22 and a plate line PL disposed on the first substrate 21. The memory array 22 includes a plurality of ferroelectric memory cells, and the ferroelectric memory cells are electrically connected with the plate line PL. The second chip 30 includes a second substrate 31, and a plate line driving circuit 32 disposed on the second substrate 31. The second chip 30 is disposed in a face-to-face stack with the first chip 20, and the memory array 22, the plate line PL, and the plate line driving circuit 32 are located between the first substrate 21 and the second substrate 31. In other words, after the first chip 20 and the second chip 30 are disposed in a face-to-face stack, the plate line driving circuit 32 is located on a side of the second substrate 31 facing the first chip 20, and the plate line PL and the memory array 22 are located on a side of the first substrate 21 facing the second chip 30. In addition, the plate line driving circuit 32 is electrically connected with the plate line PL, and is configured to provide a voltage to the plate line PL. Moreover, a normal projection of the plate line driving circuit 32 and the memory array 22 on the first substrate 21 at least partially overlaps.

[0064] In the present application, the memory array 22 and the plate line PL are manufactured on the first chip 20, the plate line driving circuit 32 is manufactured on the second chip 30 other than the first chip 20, and the plate line driving circuit 32 and the plate line PL are interconnected by stacking the first chip 20 and the second chip 30. In the present embodiment, the plate line driving circuit 32 is disposed on the second chip other than the first chip 20, so that the normal projection of the plate line driving circuit 32 and the memory array 22 on the first substrate 21 at least partially overlaps. In this way, the plate line driving circuit 32 is more disposed in the projection range of the memory array 22, and the area outside the projection of the memory array 22 is greatly reduced, so that the area constraint of the plate line driving circuit 32 on the chip is eliminated, thereby improving the AE of the memory and improving the capacity density. Meanwhile, the present application can achieve the electrical connection between the plate line PL and the plate line driving circuit 32 at the connection between the first chip 20 and the second chip 30. As mentioned above, the plate line PL can be prepared by a subsequent process, so that the plate line PL only needs to be led to the connection between the first chip 20 and the second chip 30. Unlike the prior art, the plate line PL and the plate line driving circuit 11 are not electrically connected by borrowing the conductive layer on the side of the plate line PL away from the first substrate 21 and the deep hole connecting the conductive layer and the plate line driving circuit 11. Therefore, the present embodiment can also avoid the problem that the deep hole is too deep and the metal material with high resistivity is filled in the deep hole, resulting in a large resistance on the link between the plate line PL and the plate line driving circuit 11, thereby causing a long conversion time of pull-up and pull-down on the plate line PL.

[0065] In some possible implementations, the plate line driving circuit 32 is more disposed in the projection range of the memory array 22, which can be divided into the following cases:

[0066] The first case, as shown in FIG. 5, the orthographic projection of the plate line driving circuit 32 on the first substrate 21 exactly overlaps the orthographic projection of the storage array 22 on the first substrate 21.

[0067] The second case, as shown in FIG. 6, the orthographic projection area of the plate line driving circuit 32 on the first substrate 21 is greater than the orthographic projection area of the storage array 22 on the first substrate 21, and the orthographic projection of the storage array 22 on the first substrate 21 is located within the orthographic projection range of the plate line driving circuit 32 on the first substrate 21.

[0068] The third case, as shown in FIG. 7, the orthographic projection area of the plate line driving circuit 32 on the first substrate 21 is less than the orthographic projection area of the storage array 22 on the first substrate 21, and the orthographic projection of the plate line driving circuit 32 on the first substrate 21 is located within the orthographic projection range of the storage array 22 on the first substrate 21.

[0069] Of course, based on the orthographic projection area of the plate line driving circuit 32 on the first substrate 21 and the orthographic projection area of the storage array 22 on the first substrate 21, the relative position relationship between the plate line driving circuit 32 and the storage array 22 can also be other, and the embodiments of the present application do not limit this, as long as the plate line driving circuit 32 is as much as possible to be arranged within the projection range of the storage array 22.

[0070] In addition, it should be understood that the orthographic projection of the plate line driving circuit 32 on the first substrate 21 refers to the projection of the plate line driving circuit 32 vertically projected on the first substrate 21 along the direction of the second chip 30 pointing to the first chip 20. The orthographic projection of the storage array 22 on the first substrate 21 refers to the projection of the storage array 22 vertically projected on the first substrate 21 along the direction of the second chip 30 pointing to the first chip 20.

[0071] In some possible implementation manners, the storage array 22 can be arranged between the plate line PL and the first substrate 21; or the storage array 22 can also be arranged on the side of the plate line PL away from the first substrate 21.

[0072] In some embodiments, as mentioned above, the present application changes the setting position of the plate line driving circuit 32. In addition, as shown in FIGS. 5-7, if the first chip 20 is regarded as a chip of the prior art comprising the word line driving circuit 12, the sense amplifier 13, the plate line driving circuit 11, the memory array 14, and the plate line PL, the positions of the word line driving circuit 12, the sense amplifier 13, the memory array 14, and the plate line PL do not change, the main body of the word line driving circuit 12 and the sense amplifier 13 can still be prepared by a front-end process, the memory array 14 and the plate line PL can still be prepared by a back-end process, and the word line driving circuit 12 and the sense amplifier 13 are arranged between the first substrate 21 and the memory array 14 and the plate line PL. In addition, the orthogonal projection of the sense amplifier 13 on the first substrate 21 overlaps the orthogonal projection of the memory array 22 on the first substrate 21.

[0073] The first chip 20 can further comprise a word line WL and a bit line BL, and the transistor in the memory cell comprises a gate, a first electrode, and a second electrode. The ferroelectric capacitor in the memory cell comprises a first electrode and a second electrode. The gate is electrically connected to the word line WL, the first electrode is electrically connected to the bit line BL, the second electrode is electrically connected to the first electrode, and the second electrode is electrically connected to the plate line PL. In some embodiments, the first electrode is a source electrode, and the second electrode is a drain electrode. In other embodiments, the first electrode is a drain electrode, and the second electrode is a source electrode.

[0074] In addition, the second chip can be a logic chip, and the second chip can further comprise other logic circuits in addition to the plate line driving circuit 32, as long as the setting position of the other logic circuits does not affect the orthogonal projection of the plate line driving circuit 32 on the first substrate 21, and the orthogonal projection of the memory array 22 on the first chip 21 at least partially overlaps.

[0075] In some embodiments, as shown in FIGS. 5-7, the first chip 20 further comprises a first conductive lead 23, and the second chip 30 further comprises a second conductive lead 33. The first conductive lead 23 is arranged on the side of the memory array 22 and the plate line PL away from the first substrate 21, and the second conductive lead 33 is arranged on the side of the plate line driving circuit 32 away from the second substrate 31. In addition, the plate line PL is one-to-one corresponding to and electrically connected to the first conductive lead 23 and the second conductive lead 33, and the plate line driving circuit 32 is electrically connected to the plate line PL through the second conductive lead 33 and the first conductive lead 23, so as to apply a voltage to the plurality of plate lines PL through the second conductive lead 33 and the first conductive lead 23.

[0076] In some possible implementations, the plurality of first conductive leads 23 can be arranged in the same layer or in different layers, which is determined by the arrangement of the first conductive leads 23. As shown in FIG. 5, in order to facilitate wiring, the plurality of first conductive leads 23 are arranged in two layers.

[0077] The plurality of second conductive leads 33 can be arranged in the same layer or different layers, which is determined by the arrangement of the second conductive leads 33. As shown in FIG. 5, in order to facilitate wiring, the plurality of second conductive leads 33 are arranged in two layers.

[0078] In some possible implementations, as shown in FIG. 5, a dielectric layer is further arranged between the first conductive lead 23 and the plate line PL, and a via is formed in the dielectric layer. The plate line PL is electrically connected to the first conductive lead 23 through conductive material in the via.

[0079] Similarly, a dielectric layer is further arranged between the second conductive lead 33 and the plate line driving circuit 32, and a via is formed in the dielectric layer. The plate line driving circuit 32 is electrically connected to the second conductive lead 33 through conductive material in the via.

[0080] In some embodiments, as shown in FIGS. 5-7, the first chip 20 further includes a first dielectric layer 24 arranged on a side of the first conductive lead 23 away from the first substrate 21, and a first via is formed in the first dielectric layer 24. The second chip 30 further includes a second dielectric layer 34 arranged on a side of the second conductive lead 33 away from the second substrate 31, and a second via is formed in the second dielectric layer 34. The first via and the second via are filled with conductive material. The memory chip further includes a conductive structure 40 arranged between the first dielectric layer 24 and the second dielectric layer 34. The first conductive lead 23 is electrically connected to the second conductive lead 33 corresponding thereto through the first via, the conductive structure 40, and the second via. That is, the plate line PL is led out to the conductive structure 40 through the first conductive lead 23 and the conductive material in the first via, and the plate line driving circuit 33 is led out to the conductive structure 40 through the second conductive lead 33 and the conductive material in the second via, so as to finally realize electrical connection between the plate line driving circuit 33 and the plate line PL.

[0081] The stacking manner of the first chip 20 and the second chip 30 is different, and the material of the conductive structure 40 is also different.

[0082] For example, as shown in FIG. 8, if the first chip 20 and the second chip 30 are stacked by a soldering process, the conductive structure 40 is a solder ball, and the first chip 20 and the second chip 30 are stacked through the solder ball.

[0083] Specifically, solder is printed on the pads 401 of the first dielectric layer 24 and the second dielectric layer 34, and then the solder is solidified to obtain the solder ball 40, so as to connect the first chip 20 and the second chip by using the solder ball 40.

[0084] For example, as shown in FIGS. 5-7, the first chip 20 and the second chip 30 are stacked by a hybrid bonding process, and the conductive structure 40 includes a first metal sheet 41 and a second metal sheet 42, the first metal sheet 41 is embedded in the first dielectric layer 24 towards the second dielectric layer 34, and the second metal sheet 42 is embedded in the second dielectric layer 34 towards the first dielectric layer 24.

[0085] Specifically, as shown in FIGS. 9a and 9b, the first dielectric layer 24 is provided with a first recess towards the second dielectric layer 34, and the second dielectric layer 34 is provided with a second recess towards the first dielectric layer 24, and the first metal sheet 41 is filled in the first recess, and the second metal sheet 42 is filled in the second recess. In the direction from the first chip 20 to the second chip 30, the thickness of the first metal sheet 41 can be less than the depth of the first recess, and the thickness of the second metal sheet 42 can be less than the depth of the second recess. Then, as shown in FIG. 9c, the first chip 20 and the second chip 30 are aligned and bonded. As shown in FIG. 5, after annealing, the first metal sheet 41 and the second metal sheet 42 are expanded to contact and realize electrical connection.

[0086] In some possible implementation manners, the material of the first metal sheet 41 and the second metal sheet 42 is not limited in the embodiment of the application, as long as the first metal sheet 41 and the second metal sheet 42 can conduct electricity. Optionally, the material of the first metal sheet 41 and the second metal sheet 42 can include copper Cu.

[0087] In addition, the first chip 20 and the second chip 30 can also be stacked by other manners, which are not limited in the embodiment of the application.

[0088] In another embodiment, the application further provides a preparation method of a storage chip, as shown in FIG. 10, which can be realized by the following manner:

[0089] S110, as shown in FIG. 11a, a storage array 22 and a plate line PL are formed on a first substrate 21 to obtain a first chip 20. As shown in FIG. 11b, a plate line driving circuit 32 is formed on a second substrate 31 to obtain a second chip 30. The storage array 22 includes a plurality of ferroelectric storage cells, and the ferroelectric storage cells are electrically connected with the plate line PL.

[0090] In some possible implementation manners, the embodiment of the present application does not limit the sequence of forming the storage array 22 and the plate line PL on the first substrate 21 and forming the plate line driving circuit 32 on the second substrate 31. The storage array 22 and the plate line PL can be formed on the first substrate 21 first, and then the plate line driving circuit 32 is formed on the second substrate 31. Alternatively, the plate line driving circuit 32 can be formed on the second substrate 31 first, and then the storage array 22 and the plate line PL are formed on the first substrate 21. Alternatively, the storage array 22 and the plate line PL are formed on the first substrate 21 at the same time, and the plate line driving circuit 32 is formed on the second substrate 31.

[0091] In some possible implementation manners, the storage array 22 and the plate line PL formed on the first substrate 21 can also be formed by a front-end process on the first substrate 21, and the word line driving circuit 12 and the sense amplifier 13 are formed on the first substrate 21. In addition, the orthographic projection of the sense amplifier 13 on the first substrate 21 at least partially overlaps the orthographic projection of the storage array 22 on the first substrate 21.

[0092] Optionally, the storage array 22 completely covers the sense amplifier 13, or a part of the sense amplifier 13 is covered by the storage array 22, and the other part is outside the projection range of the storage array 22.

[0093] S120, as shown in FIGS. 5-7, the first chip 20 and the second chip 30 are stacked and arranged, and the storage array 22, the plate line PL and the plate line driving circuit 32 are located between the first substrate 21 and the second substrate 31. It can also be said that after the first chip 20 and the second chip 30 are stacked and arranged face to face, the plate line driving circuit 32 is located on the side of the second substrate 31 facing the first chip 20, and the plate line PL and the storage array 22 are located on the side of the first substrate 21 facing the second chip 30. In addition, the plate line driving circuit 32 is electrically connected with the plate line PL, and is used to provide a voltage to the plate line PL. In addition, the orthographic projection of the plate line driving circuit 32 and the storage array 22 on the first substrate 21 at least partially overlaps.

[0094] In the present application, the storage array 22 and the plate line PL are fabricated on the first chip 20, the plate line driving circuit 32 is fabricated on the second chip 30 other than the first chip 20, and the plate line driving circuit 32 and the plate line PL are interconnected by stacking the first chip 20 and the second chip 30. In the embodiments of the present application, the plate line driving circuit 32 is arranged on the second chip other than the first chip 20, so that the orthographic projection of the plate line driving circuit 32 on the first substrate 21 at least partially overlaps the orthographic projection of the storage array 22 on the first substrate 21. In this way, the plate line driving circuit 32 is arranged more in the projection range of the storage array 22, the area outside the projection of the storage array 22 is greatly reduced, the area constraint of the chip caused by the plate line driving circuit 32 is eliminated, and the AE of the memory is improved, and the capacity density is improved. At the same time, the present application can realize the electrical connection between the plate line PL and the plate line driving circuit 32 at the connection between the first chip 20 and the second chip 30. As mentioned above, the plate line PL can be prepared by a subsequent process, so it is only necessary to lead the plate line PL to the connection between the first chip 20 and the second chip 30. Unlike the prior art, the plate line PL and the plate line driving circuit 11 are not electrically connected by borrowing the conductive layer on the side of the plate line PL away from the first substrate 21 and the deep hole connecting the conductive layer and the plate line driving circuit 11. Therefore, the embodiments of the present application can also avoid the problem that the deep hole is too deep and the metal material with high resistivity is filled in the deep hole, resulting in a large resistance on the link between the plate line PL and the plate line driving circuit 11, and thus a long conversion time of pull-up and pull-down on the plate line PL.

[0095] In some possible implementations, the plate line driving circuit 32 is arranged more in the projection range of the storage array 22, which can be divided into the following cases:

[0096] The first case is shown in FIG. 5, in which the orthographic projection of the plate line driving circuit 32 on the first substrate 21 exactly overlaps the orthographic projection of the storage array 22 on the first substrate 21.

[0097] The second case is shown in FIG. 6, in which the orthographic projection area of the plate line driving circuit 32 on the first substrate 21 is greater than the orthographic projection area of the storage array 22 on the first substrate 21, and the orthographic projection of the storage array 22 on the first substrate 21 is located in the orthographic projection range of the plate line driving circuit 32 on the first substrate 21.

[0098] The third case is shown in FIG. 7, in which the orthographic projection area of the plate line driving circuit 32 on the first substrate 21 is less than the orthographic projection area of the storage array 22 on the first substrate 21, and the orthographic projection of the plate line driving circuit 32 on the first substrate 21 is located in the orthographic projection range of the storage array 22 on the first substrate 21.

[0099] Of course, based on the area of the orthographic projection of the plate line driving circuit 32 on the first substrate 21 and the area of the orthographic projection of the storage array 22 on the first substrate 21, the relative positional relationship between the plate line driving circuit 32 and the storage array 22 can also be other, and the embodiments of the present application do not limit this, as long as the plate line driving circuit 32 is arranged as much as possible in the projection range of the storage array 22.

[0100] In some embodiments, as shown in FIGS. 12a and 12b, after step S110, before step S120, the preparation method of the storage chip can further include: forming a first conductive lead 23 on the side of the storage array 22 and the plate line PL away from the first substrate 21. A second conductive lead 33 is formed on the side of the plate line driving circuit 32 away from the second substrate 31. The plate line PL corresponds to the first conductive lead 23 and the second conductive lead 33 one by one and is electrically connected, and the plate line driving circuit 32 is electrically connected with the plate line PL through the second conductive lead 33 and the first conductive lead 23, so as to apply voltage to the plurality of plate lines PL through the second conductive lead 33 and the first conductive lead 23.

[0101] In some possible implementation manners, the plurality of first conductive leads 23 can be arranged in the same layer or in different layers, which is determined by the arrangement of the first conductive leads 23. As shown in FIG. 5, in order to facilitate wiring, the plurality of first conductive leads 23 are arranged in two layers.

[0102] The plurality of second conductive leads 33 can be arranged in the same layer or in different layers, which is determined by the arrangement of the second conductive leads 33. As shown in FIG. 5, in order to facilitate wiring, the plurality of second conductive leads 33 are arranged in two layers.

[0103] In some possible implementation manners, as shown in FIG. 5, a dielectric layer is further arranged between the first conductive lead 23 and the plate line PL, a through hole is formed in the dielectric layer, and the plate line PL is electrically connected with the first conductive lead 23 through the conductive material in the through hole.

[0104] Similarly, a dielectric layer is further arranged between the second conductive lead 33 and the plate line driving circuit 32, a through hole is formed in the dielectric layer, and the plate line driving circuit 32 is electrically connected with the second conductive lead 33 through the conductive material in the through hole.

[0105] In some embodiments, as shown in FIG. 12a, after the first conductive lead 23 is formed on the side of the storage array 22 and the plate line PL away from the first substrate 21, the preparation method of the storage chip further includes: forming a first dielectric layer 24 on the side of the first conductive lead 23 away from the first substrate 21, forming a first through hole in the first dielectric layer 24, and filling the first through hole with conductive material.

[0106] As shown in FIG. 12b, after the second conductive lead 33 is formed on the side of the board line driving circuit 32 away from the second substrate 31, the preparation method of the storage chip further includes: forming a second dielectric layer 34 on the side of the second conductive lead 33 away from the second substrate 31, the second dielectric layer 34 is provided with a second through hole, and the second through hole is filled with a conductive material.

[0107] Then, the stacking of the first chip 20 and the second chip 30 in step S120 can include: forming a conductive structure 40 between the first dielectric layer 24 and the second dielectric layer 34, the first conductive lead 34 is electrically connected to the second conductive lead 34 through the first through hole, the conductive structure 40, and the second through hole. That is, the board line PL is led out to the conductive structure 40 through the conductive material in the first conductive lead 23 and the first through hole, and the board line driving circuit 33 is led out to the conductive structure 40 through the conductive material in the second conductive lead 33 and the second through hole, finally realizing the electrical connection between the board line driving circuit 33 and the board line PL.

[0108] The fixed connection mode of the first chip 20 and the second chip 30 is different, and the material of the conductive structure 40 is also different.

[0109] For example, as shown in FIG. 8, if the first chip 20 and the second chip 30 are fixedly connected through a soldering process, the conductive structure 40 is a solder ball, and the first chip 20 and the second chip 30 are fixedly connected through the solder ball.

[0110] Specifically, solder paste is printed on the pads 401 of the first dielectric layer 24 and the second dielectric layer 34, and then the solder paste is solidified to obtain the solder ball 40, so as to connect the first chip 20 and the second chip 30 by using the solder ball 40.

[0111] For another example, as shown in FIGS. 5-7, the first chip 20 and the second chip 30 are fixedly connected through a hybrid bonding process, and the conductive structure 40 includes a first metal sheet 41 and a second metal sheet 42, the first metal sheet 41 is embedded into the side of the first dielectric layer 24 facing the second dielectric layer 34, and the second metal sheet 42 is embedded into the side of the second dielectric layer 34 facing the first dielectric layer 24.

[0112] Specifically, as shown in FIG. 9a and FIG. 9b, the first dielectric layer 24 is provided with a first recess on the side facing the second dielectric layer 34, the second dielectric layer 34 is provided with a second recess on the side facing the first dielectric layer 24, the first recess is filled with the first metal sheet 41, and the second recess is filled with the second metal sheet 42. In the direction from the first chip 20 to the second chip 30, the thickness of the first metal sheet 41 can be less than the depth of the first recess, and the thickness of the second metal sheet 42 can be less than the depth of the second recess. Then, as shown in FIG. 9c, the first chip 20 and the second chip 30 are aligned and bonded. As shown in FIG. 5, after annealing, the first metal sheet 41 and the second metal sheet 42 expand to contact each other, thereby realizing electrical connection.

[0113] In some possible implementation manners, the material of the first metal sheet 41 and the second metal sheet 42 is not limited in the embodiments of the present application, as long as the first metal sheet 41 and the second metal sheet 42 can conduct electricity. Optionally, the material of the first metal sheet 41 and the second metal sheet 42 can include copper Cu.

[0114] In addition, the first chip 20 and the second chip 30 can be fixedly connected in other manners, which are not limited in the embodiments of the present application.

[0115] The above merely provides a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art can easily think of changes or replacements within the technical range disclosed in the present application, which should be covered in the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A memory chip, characterized by, The first chip and the second chip are stacked together, the storage array, the plate line and the plate line driving circuit are located between the first substrate and the second substrate, and the plate line driving circuit is electrically connected with the plate line. The plate line driving circuit and the storage array at least partially overlap in the orthographic projection on the first substrate. The first chip further comprises a first conductive lead, and the second chip further comprises a second conductive lead. The first conductive lead is arranged on the side of the storage array and the plate line away from the first substrate, and the second conductive lead is arranged on the side of the plate line driving circuit away from the second substrate. The plate line is one-to-one corresponding and electrically connected with the first conductive lead and the second conductive lead, and the plate line driving circuit is electrically connected with the plate line through the second conductive lead and the first conductive lead.

2. The memory chip of claim 1, wherein, 3. The storage chip according to claim 2, wherein The first chip further comprises a first dielectric layer arranged on the side of the first conductive lead away from the first substrate, and a first through hole is arranged in the first dielectric layer. The second chip further comprises a second dielectric layer arranged on the side of the second conductive lead away from the second substrate, and a second through hole is arranged in the second dielectric layer. The first through hole and the second through hole are filled with conductive material, and the storage chip further comprises a conductive structure arranged between the first dielectric layer and the second dielectric layer, and the first conductive lead is electrically connected with the second conductive lead corresponding thereto through the first through hole, the conductive structure and the second through hole.

4. The storage chip according to claim 3, wherein The conductive structure is a solder ball, and the first chip and the second chip are fixedly connected through the solder ball; or The first chip and the second chip are fixedly connected through hybrid bonding, the conductive structure comprises a first metal sheet and a second metal sheet, the first metal sheet is embedded into the side of the first dielectric layer facing the second dielectric layer, and the second metal sheet is embedded into the side of the second dielectric layer facing the first dielectric layer. The first chip further comprises a comparator and a word line driving circuit, the comparator and the word line driving circuit are arranged between the first substrate and the storage array, and the orthographic projection of the comparator on the first substrate at least partially overlaps with the orthographic projection of the storage array on the first substrate. The ferroelectric storage unit comprises a transistor and at least one ferroelectric capacitor, and the first chip further comprises a word line and a bit line.

5. The memory chip according to any one of claims 1 to 4, characterized in that, The transistor comprises a gate, a first pole and a second pole, and the ferroelectric capacitor comprises a first electrode and a second electrode.

6. The memory chip of claim 5, wherein, ​ ​ The gate is electrically connected with the word line, the first pole is electrically connected with the bit line, the second pole is electrically connected with the first electrode, and the second electrode is electrically connected with the plate line.

7. A memory, comprising: The memory chip comprises a controller configured to control reading and writing of data from and to the memory array in the memory chip.

8. An electronic device, comprising: The memory comprises a processor configured to control reading and writing of data from and to the memory via the controller.

9. A method of manufacturing a memory chip, characterized by, The memory chip comprises: forming a memory array and a plate line on a first substrate to obtain a first chip; forming a plate line driving circuit on a second substrate to obtain a second chip; the memory array comprises a plurality of ferroelectric memory cells, and the ferroelectric memory cells are electrically connected with the plate line; stacking the first chip and the second chip, the memory array, the plate line, and the plate line driving circuit are located between the first substrate and the second substrate, and the plate line driving circuit is electrically connected with the plate line; wherein the plate line driving circuit and the memory array on the first substrate at least partially overlap in orthographic projection.

10. The method of claim 9, wherein the step of forming the memory chip is performed by a method comprising: After the memory array and the plate line are formed on the first substrate, and the plate line driving circuit is formed on the second substrate, before the first chip and the second chip are stacked, the preparation method of the memory chip further comprises: forming a first conductive lead on a side of the memory array and the plate line away from the first substrate; forming a second conductive lead on a side of the plate line driving circuit away from the second substrate; the plate line is one-to-one corresponding and electrically connected with the first conductive lead and the second conductive lead, and the plate line driving circuit is electrically connected with the plate line through the second conductive lead and the first conductive lead.

11. The method of claim 10, wherein the step of forming the memory chip is performed by a method comprising: After the first conductive lead is formed on the side of the memory array and the plate line away from the first substrate, the preparation method of the memory chip further comprises: forming a first dielectric layer on a side of the first conductive lead away from the first substrate, a first through hole is formed in the first dielectric layer, and a conductive material is filled in the first through hole; after the second conductive lead is formed on the side of the plate line driving circuit away from the second substrate, the preparation method of the memory chip further comprises: forming a second dielectric layer on a side of the second conductive lead away from the second substrate, a second through hole is formed in the second dielectric layer, and a conductive material is filled in the second through hole; the stacking of the first chip and the second chip comprises: forming a conductive structure between the first dielectric layer and the second dielectric layer, and the first conductive lead is electrically connected with the second conductive lead corresponding thereto through the first through hole, the conductive structure, and the second through hole.

12. The preparation method of the memory chip according to claim 11, wherein the stacking of the first chip and the second chip comprises: welding the first chip and the second chip, and the conductive structure is a solder ball; or A first recess is formed in the first dielectric layer, and a second recess is formed in the second dielectric layer; the opening of the first recess faces the second dielectric layer, and the opening of the second recess faces the first dielectric layer; A first metal sheet is filled in the first recess, and a second metal sheet is filled in the second recess; The first chip and the second chip are bonded.

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