Ethernet processing core, chip, electronic device, and data processing method of ethernet processing core

Abstract

The present disclosure provides an Ethernet processing core, comprising: a read-write control module, a read timing adjustment unit, a write timing adjustment unit, a first processing unit, and a second processing unit, wherein the first processing unit and the second processing unit are micro-processing units; the read-write control module is used for arbitrating an internal data processing request and an external data processing request to determine a current data processing request to be processed; the first processing unit is used for, when the data processing request is an internal data read processing request, reading first target data from a target memory and caching the first target data; and the second processing unit is used for, when the data processing request is an internal data write processing request, acquiring second target data from the write timing adjustment unit on the basis of the data processing request, and writing the second target data into the target memory. The present disclosure also provides a chip, an electronic device, and a data processing method of an Ethernet processing core.

Description

Ethernet processing core, chip, electronic device and data processing method of ethernet processing core

[0001] Cross-reference to Related Applications

[0002] This patent application claims priority to Chinese Patent Application No. 202411093524.X, filed August 8, 2024, in the State Intellectual Property Office of China, the disclosure of which is incorporated herein in its entirety by reference. TECHNICAL FIELD

[0003] The present disclosure relates to the field of communication technology, and in particular, to an Ethernet processing core, chip, electronic device and data processing method of Ethernet processing core. BACKGROUND

[0004] Ethernet is one of the most commonly used communication protocol standards in today's local area networks, and GMAC (Gigabit Media Access Control) protocol is one of the media access control protocols used for Ethernet communication. The GMAC protocol defines the format of Ethernet frames, transmission rates, maximum length of frames, and other regulations, and also specifies the data transmission method and collision detection mechanism between nodes in the Ethernet.

[0005] In the Ethernet, the GMAC protocol is usually implemented in a network card chip for controlling the sending and receiving of data. The GMAC protocol supports multiple transmission rates, including 10 Mbps, 100 Mbps, 1 Gbps, etc., and also supports full-duplex and half-duplex communication modes. In the network part, the GMAC system framework is usually composed of a MAC controller and a PHY (Physical Layer) module. The CPU (Central Processing Unit), MAC controller, and PHY module are not integrated in the same chip. Since the PHY module contains a large number of analog devices, and the MAC controller is a typical digital circuit, considering the chip area and the mixed analog / digital architecture, the MAC controller is usually integrated into the SoC (System on Chip), while the PHY module is left outside the SoC. The MAC controller mainly completes the packaging of IP datagrams of the data link layer into network frames and sends the data to the PHY module. The PHY module mainly completes the speed negotiation, converts the digital signal to the analog signal, and finally outputs the signal to the network cable.

[0006] When the PHY module transmits a data packet to the CPU in the Ethernet network, a method of calling a GMAC IP core provided by an IP (Intellectual Property) company is used to realize the transmission. The GMAC IP core is connected to a chip external interface on one side and to a SoC bus on the other side. After processing a physical layer data packet, data is extracted and placed in the internal storage of the chip. Alternatively, the data packet is read from the internal storage of the SoC, processed, and then transmitted to the external PHY module through the chip interface.

[0007] The GMAC IP core is not flexible enough. Some functions may not be used, but the logic area is occupied. It is not customized according to the application scenario. For example, the GMAC IP core supports MII (Media Independent Interface) interface, RGMII (Reduced Gigabit Media Independent Interface) interface, GMII (Gigabit Media Independent Interface) interface, RMII (Reduced Media Independent Interface) interface, etc. However, the actual project application only uses the RMII interface, and other logic is wasted. For another example, the rate negotiation and collision detection functions are not needed in the project, resulting in redundant area of the GMAC IP core. SUMMARY

[0008] The present disclosure provides an Ethernet processing core, a chip, an electronic device and an Ethernet processing core data processing method.

[0009] In a first aspect, the embodiments of the present disclosure provide an Ethernet processing core, comprising a read-write control module, a read timing adjustment unit, a write timing adjustment unit, a first processing unit and a second processing unit, the first processing unit and the second processing unit being micro processing units; the read-write control module is configured to arbitrate internal data processing requests and external data processing requests, and determine a current data processing request to be processed; the first processing unit is configured to read first target data from a target memory and cache the first target data, in a case that the data processing request is an internal data processing request and the internal data processing request is a data reading request; the read timing adjustment unit is configured to obtain the first target data from the first processing unit, cache the first target data after adjusting an external input-output bit width of the first target data to an internal processing bit width, and send the first target data to a network device; the write timing adjustment unit is configured to receive second target data sent by the network device, cache the second target data after adjusting an internal processing bit width of the second target data to an external input-output bit width; and the second processing unit is configured to obtain the second target data from the write timing adjustment unit according to the data processing request, and write the second target data into a target memory, in a case that the data processing request is an internal data processing request and the data processing request is a data writing request.

[0010] In a second aspect, the embodiments of the present disclosure provide a chip, comprising a target memory and an Ethernet processing core as described above, the Ethernet processing core being connected with the target memory through a bus.

[0011] In a third aspect, the embodiments of the present disclosure further provide an electronic device, comprising a chip as described above.

[0012] In a fourth aspect, the embodiments of the present disclosure further provide an Ethernet processing core data processing method, which is applied to the Ethernet processing core as described above, and includes: arbitrating an internal data processing request and an external data processing request to determine a current data processing request to be processed; in a case where the data processing request is an internal data processing request and the internal data processing request is a data reading request, reading first target data from a target memory according to the data processing request, and caching the first target data; caching the first target data after adjusting an external input / output bit width of the first target data to an internal processing bit width, and sending the first target data to a network device; or, in a case where the data processing request is an internal data processing request and the data processing request is a data writing request, receiving second target data sent by the network device, caching the second target data after adjusting an internal processing bit width of the second target data to an external input / output bit width; obtaining the second target data according to the data processing request, and writing the second target data into the target memory. BRIEF DESCRIPTION OF DRAWINGS

[0013] In the drawings of the embodiments of the present disclosure:

[0014] FIG. 1 is a schematic diagram of an application scenario of the embodiments of the present disclosure;

[0015] FIG. 2 is a schematic diagram of a structure of an Ethernet processing core provided by the embodiments of the present disclosure;

[0016] FIG. 3 is a schematic diagram of a working process of an Ethernet processing core provided by the embodiments of the present disclosure;

[0017] FIG. 4 is a schematic diagram of a structure of a first processing unit provided by the embodiments of the present disclosure;

[0018] FIG. 5 is a schematic diagram of an external interface of an Ethernet processing core provided by the embodiments of the present disclosure;

[0019] FIG. 6 is a schematic diagram of a structure of a chip provided by the embodiments of the present disclosure;

[0020] FIG. 7 is a schematic diagram of a flow of an Ethernet processing core data processing method provided by the embodiments of the present disclosure. DETAILED DESCRIPTION

[0021] In order for those skilled in the art to better understand the technical solutions of the present disclosure, the embodiments of the present disclosure are described in detail below with reference to the drawings.

[0022] The embodiments of the present disclosure will be described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the present disclosure are shown. This disclosure may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and fully convey the scope of the disclosure to those skilled in the art.

[0023] The accompanying drawings, which are included to provide a further understanding of the embodiments of the present disclosure and are incorporated in and constitute a part of this specification, illustrate embodiments of the present disclosure and together with the description serve to explain the present disclosure and, to those skilled in the art, fully convey the scope of the present disclosure.

[0024] The present disclosure can be described with reference to plan views and / or cross-sectional views by idealized figures to provide a generic understanding of the methods of the present disclosure. Thus, the illustrations provided are schematic and are non-limiting according to their nature.

[0025] The embodiments of the present disclosure and the features thereof can be combined with each other, if not in conflict.

[0026] The terms used in the present disclosure are merely used to describe particular embodiments, and are not intended to limit the present disclosure. As used in the present disclosure, the term "and / or" includes any and all combinations of one or more of the associated listed items. As used in the present disclosure, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. As used in the present disclosure, the term "comprises," "comprising," "consists of," and "consisting of" specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0027] Unless otherwise defined, all terms used in the present disclosure, including technical and scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted in an overly formal or overly strict sense unless expressly so defined herein.

[0028] The present disclosure is not limited to the embodiments shown in the drawings, but includes modifications of configurations formed based on a manufacturing process. Therefore, the regions exemplified in the drawings have a schematic property, and the shape of the regions shown in the drawings exemplifies a specific shape of a region of an element, but is not intended to be restrictive.

[0029] Embodiments of the present disclosure provide an Ethernet processing core, which is an IP core in a chip of an electronic device.

[0030] FIG. 1 is a schematic diagram of an application scenario of embodiments of the present disclosure.

[0031] As shown in FIG. 1, the electronic device 100 can receive and store data transmitted by the network device 200, and transmit the data stored by itself to the network device 200. The electronic device 100 includes a chip (SoC), a CPU and an RMII interface module. The chip includes a target memory and an Ethernet processing core. In the embodiment of the present disclosure, the target memory can be a DDR (Double Data Rate Synchronous Dynamic Random) memory, and the Ethernet processing core can be a GMAC module. The network device 200 can include a MAC controller.

[0032] The network device 200 and the electronic device 100 realize data transmission through a PHY module and an RJ45 module. The MAC controller and the GMAC module are used to package IP datagrams at the data link layer into network frames and transmit the data to the PHY module. The PHY module is used to perform speed negotiation, convert digital signals into analog signals and then transmit the analog signals through a network cable. The RMII interface is a logical interface of the chip, and the RJ45 module is a physical interface crystal head.

[0033] FIG. 2 is a structural schematic diagram of an Ethernet processing core provided by the embodiment of the present disclosure. As shown in FIG. 2, the Ethernet processing core 10 (i.e., the GMAC in FIG. 1) includes a read-write control module 1, a first processing unit 21, a second processing unit 22, a read timing adjustment unit 31 and a write timing adjustment unit 32. The first processing unit 21 and the second processing unit 22 are micro processing units.

[0034] The read-write control module 1 is used to arbitrate internal data processing requests and external data processing requests, and determine the current data processing request to be processed.

[0035] The first processing unit 21 is used to read first target data from the target memory and buffer the first target data, in the case that the data processing request is an internal data processing request and the internal data processing request is a data reading request.

[0036] The read timing adjustment unit 31 is used to obtain the first target data from the first processing unit 21, buffer the first target data after adjusting the external input-output bit width of the first target data to an internal processing bit width, and transmit the first target data to the network device 200.

[0037] The write timing adjustment unit 32 is used to receive second target data transmitted by the network device 200, and buffer the second target data after adjusting the internal processing bit width of the second target data to an external input-output bit width.

[0038] The second processing unit 22 is used to obtain the second target data from the write timing adjustment unit 32 according to the data processing request, and write the second target data into the target memory, in the case that the data processing request is an internal data processing request and the data processing request is a data writing request.

[0039] The internal data processing request refers to a data processing request inside the processing unit (i.e., the first processing unit 21 and the second processing unit 22), and the external data processing request refers to a hardware accelerator logic outside the processing unit. The target memory can include but is not limited to DDR, and the network device 200 can include but is not limited to BMC (Baseboard Management Controller). The first processing unit 21 and the second processing unit 22 are programmable micro processing units. The embodiment of the present disclosure adopts a softening idea to set the processing unit. Since the microcode can be reconfigured after tape-out, defects can be normally solved, and protocol upgrades can be seamlessly supported on existing devices.

[0040] The embodiment of the present disclosure arbitrates the read and write requests of the processing unit (i.e., the first processing unit 21 and the second processing unit 22) inside and the external hardware accelerator by using the read-write control module 1, and realizes data processing in a softening manner. By using the micro processing unit, the IP core can be customized according to the needs, the chip area and power consumption are maximally saved, the individual needs of users are met, and the flexibility of the IP core is improved.

[0041] In some embodiments, the read timing adjustment unit 31 and the write timing adjustment unit 32 can include a cache unit. For example, the cache unit can be a FIFO (First Input First Output). Correspondingly, the second processing unit 22 is configured to obtain the second target data from the write timing adjustment unit 32, i.e., the second processing unit 22 can read the second target data from the cache unit of the write timing adjustment unit 32.

[0042] In some embodiments, the read timing adjustment unit 31 is further configured to perform CDC (Clock Domain Crossing) processing on the cached first target data, and convert an external low-speed clock domain into an internal high-speed clock domain. The write timing adjustment unit 32 is further configured to perform CDC processing on the cached second target data, and convert the internal high-speed clock domain into the external low-speed clock domain. The second processing unit 22 can obtain the second target data processed by the CDC from the write timing adjustment unit 32.

[0043] FIG. 3 is a schematic diagram of a working process of an Ethernet processing core provided by the embodiment of the present disclosure. The structure and working process of the Ethernet processing core will be described in detail below in combination with FIG. 3.

[0044] In some embodiments, as shown in FIG. 3, the read-write control module 1 comprises a first read-write control unit 11 and a second read-write control unit 12. The first read-write control unit 11 is connected to the read timing adjustment unit 31 and the first processing unit 21 respectively, and the second read-write control unit 12 is connected to the write timing adjustment unit 32 and the second processing unit 22 respectively.

[0045] In the case that the first read-write control unit 11 arbitrates that the current data processing request to be processed is an internal processing request and the data processing request is a data read request issued by the CPU, the first processing unit (MPCORE1) 21 can acquire first target data in the target memory (DDR) 20 according to the data processing request by the DMA (Direct Memory Access) mode, and cache the first target data. For example, the first processing unit (MPCORE1) 21 can read the first target data from the target memory 20 through the internal AXI (Advanced eXtensible Interface) bus; process the first target data, for example, add physical layer packet header information (such as preamble and SFD (Start Frame Delimiter)) in the first target data, and complete CRC (Cyclic Redundancy Check) calculation and PAD (Packet Assembler And Disassembler) addition at the same time. The read timing adjustment unit 31 reads the first target data processed by the first processing unit 21, and caches the first target data in a cache unit with a packet length of 1.5 times, and sends the processed first target data to the network device 200 according to the RMII interface timing after CDC processing.

[0046] In the case that the second read-write control unit 12 arbitrates that the current data processing request to be processed is an internal processing request and the data processing request is a data write request issued by the CPU, the write timing adjustment unit 32 receives the second target data sent by the network device 200 according to the RMII interface timing, caches the second target data in a cache unit with a packet length of 2.5 times, and performs CDC processing. The second processing unit (MPCORE2) 22 can acquire the second target data from the write timing adjustment unit 32 according to the data processing request, cache the second target data, strip the packet header information (preamble and SFD) of the second target data, complete the reporting of the CRC check result at the same time, and send the second target data to the target memory (DDR) 20 through the internal AXI bus by the DMA mode.

[0047] Figure 4 is a structural schematic diagram of the first processing unit according to an embodiment of the present disclosure. The functions and working processes of the first processing unit will be described below in combination with Figure 4.

[0048] As shown in Figure 4, the first processing unit includes a first execution unit (EXU) 211, a first cache unit (Regfile) 212, and a second cache unit (DTCM) 213. The first execution unit 211 is configured to, in a case where the data processing request is an internal data processing request and the internal data processing request is a data reading request, read first target data from the target memory 20, cache the first target data in the second cache unit 213, process the first target data to obtain processed first target data, cache the processed first target data to the first cache unit 212, move the processed first target data from the first cache unit 212 to the second cache unit 213, and instruct the read timing adjustment unit 31 to modify the data state of the second cache unit 213 to a readable state.

[0049] The read timing adjustment unit 31 is configured to, in a case where the data state of the second cache unit 213 is a readable state, read and cache the processed first target data from the second cache unit 213, and modify the data state of the second cache unit 213 to a writable state.

[0050] The first processing unit 21 can further include an instruction fetch module (Instruction Fetch Unit, IFU) 214, a tightly coupled instruction memory (Instruction Tightly Coupled Mermory, ITCM) 215, and a decoding module (Decode) 216. The instruction fetch module 214 is connected to the tightly coupled instruction memory 215 and the decoding module 216, respectively. The decoding module 216 is connected to the first execution unit 211. The tightly coupled instruction memory 215 is a cache space for instructions, supports offline reading and writing, the instruction fetch module 214 reads instructions from the tightly coupled instruction memory 215, and the decoding module 216 decodes the instructions and sends them to the first execution unit 211 for execution.

[0051] In some embodiments, the first cache unit 212 can include two first ping-pong register groups, each of which includes a first preset number of registers. After each register in one of the first ping-pong register groups is filled with processed first target data, the processed first target data is moved from the filled first ping-pong register group to the second cache unit 213. Correspondingly, the first execution unit 211 is configured to read a first preset number of first target data from the target memory 20. The first processing unit 21 uses the ping-pong register groups to cache the preset number of data as a group of data, and correspondingly, the data is transmitted in units of the group of data, which can reduce the data transmission frequency and reduce the burden of the AXI bus.

[0052] In some embodiments, the read timing adjustment unit 31 is configured to send a complete data packet of the first target data to the network device 200. When the FIFO of the read timing adjustment unit 31 is full, the first processing unit 21 is blocked from writing. After a complete data packet is stored in the FIFO of the read timing adjustment unit 31, the data packet is sent to the network device 200 outside the chip, which can ensure continuous data transmission.

[0053] In some embodiments, the read timing adjustment unit 31 is further configured to send each data packet of the first target data to the network device 200 according to a preset packet sending interval. The packet sending interval can be set and adjusted based on requirements, which improves the flexibility of data reading.

[0054] In some embodiments, the read timing adjustment unit 31 can further be configured to send a first interrupt notification to the CPU after sending the first target data to the network device 200, so that the CPU configures the next data reading task.

[0055] It should be noted that the internal structure of the second processing unit 22 is the same as that of the first processing unit 21. In some embodiments, the second processing unit 22 includes a second execution unit, a third cache unit, and a fourth cache unit. The second execution unit is configured to, in a case where the data processing request is an internal data processing request, the data processing request is a data writing request, and the data state of the fourth cache unit is a writable state, obtain second target data from the write timing adjustment unit, cache the second target data in the fourth cache unit, and instruct the write timing adjustment unit to modify the data state of the fourth cache unit to a readable state; and in a case where it is determined that the data state of the fourth cache unit is a readable state, import the second target data from the fourth cache unit to the third cache unit, process the second target data to obtain processed second target data, cache the processed second target data to the third cache unit, and move the processed second target data from the third cache unit to the fourth cache unit; and write the processed second target data from the fourth cache unit to the target memory 20.

[0056] The second processing unit 22 can further include an instruction fetch module (IFU), a tightly coupled instruction memory (ITCM) and a decode module (Decode), the instruction fetch module being connected to the tightly coupled instruction memory and the decode module, and the decode module being connected to the second execution unit. The tightly coupled instruction memory is a cache space of instructions, supporting off-line read and write. The instruction fetch module reads instructions from the tightly coupled instruction memory, and the decode module decodes the instructions and sends them to the second execution unit, which executes the instructions.

[0057] In some embodiments, the third cache unit can include two second ping-pong register groups, each of which includes a second preset number of registers; and the second execution unit is configured to write the processed second target data of the second preset number from the fourth cache unit to the target memory 20; wherein when each register in one of the second ping-pong register groups is full, the processed second target data is moved from the full second ping-pong register group to the fourth cache unit.

[0058] In some embodiments, the second execution unit is further configured to send a second interrupt notification to the CPU after writing the processed second target data to the target memory 20.

[0059] In some embodiments, the first read-write control unit 11 and the second read-write control unit 12 are configured to arbitrate the internal data processing request and the external data processing request in a polling manner.

[0060] The first read-write control unit 11 and the second read-write control unit 12 complete the read-write arbitration between the internal control information of the processing unit 2 and the hardware accelerator logic by reading and writing the register values of the DTCM of the first processing unit 21 and the second processing unit 22, and the arbitration manner is a polling manner. For example, a time period T1 for processing unit internal data processing and a time period T2 for processing unit external data processing are set in advance, T1 and T2 are alternated, and the register values of the DTCM are used to identify the current data processing time period. If there are both internal data processing requests and external data processing requests to be processed at present, the register values of the DTCM are used for arbitration. If it is determined that the current time period is the time period T1 for processing unit internal data processing, the internal data processing request is processed at present.

[0061] In some embodiments, as shown in FIG. 3, the write timing adjustment unit 32 can also be configured to send a first indication to the read timing adjustment unit 31 when the cache occupancy rate of the write timing adjustment unit 32 is greater than a first threshold, and send a second indication to the read timing adjustment unit 31 when the cache occupancy rate of the write timing adjustment unit 32 is less than a second threshold, wherein the first threshold is greater than the second threshold. Correspondingly, the read timing adjustment unit 31 is configured to send a first preset frame according to a first preset frame value corresponding to the first indication, and send a second preset frame according to a second preset frame value corresponding to the second indication.

[0062] The first threshold is an upper limit threshold of the storage capacity of the FIFO, and the second threshold is a lower limit threshold of the storage capacity of the FIFO. When the FIFO reaches the upper limit of the storage, the write timing adjustment unit 32 instructs the read timing adjustment unit 31 to send a pauseoff frame. When the FIFO reaches the lower limit of the storage, the write timing adjustment unit 32 instructs the read timing adjustment unit 31 to send a pauseon frame. By sending the flow control frame, i.e., inserting the pauseoff frame and the pauseon frame, the flow control function can be realized.

[0063] Since the RMII interface does not have a back pressure interface, the back pressure function cannot be realized. Therefore, the flow control function is realized by inserting the flow control frame in the embodiments of the present disclosure. Correspondingly, in some embodiments, the read timing adjustment unit 31 is configured to, when the first target data packet is being sent to the network device when the first indication is received, send the first preset frame according to the first preset frame value corresponding to the first indication after the sending of the data packet is completed, and when the first target data packet is being sent to the network device when the second indication is received, send the second preset frame according to the second preset frame value corresponding to the second indication after the sending of the data packet is completed. That is, the sending of the flow control frame cannot interrupt the original data transmission, and the flow control frame is sent after the original data transmission is completed, so as to ensure continuous data flow.

[0064] To clearly illustrate the scheme of the embodiments of the present disclosure, the packet sending process of the Ethernet processing core is described in detail below in combination with FIG. 3. The packet sending process includes the following steps S101 to S112.

[0065] In step S101, the first processing unit (MPCORE1) 21 determines the data stored in the read target memory (DDR) 20 according to the data reading task configured by the CPU.

[0066] In step S102, the first processing unit (MPCORE1) 21 reads 8 32-bit data at a time and caches them in the DTCM 213.

[0067] In step S103, the first processing unit (MP CORE1) 21 performs PAD addition, CRC check, FCS addition, SDF and preamble addition on the read data.

[0068] In step S104, the first processing unit (MP CORE1) 21 caches the processed data into 2 sets of ping-pong registers in the Regfile 212, each set including 8 registers.

[0069] In step S105, the first processing unit (MP CORE1) 21 moves the processed data from the ping-pong registers to the DTCM 213 and modifies the data state of the DTCM 213 to a readable state.

[0070] In step S106, the first read-write control unit 11 completes arbitration judgment of the DTCM read-write by the first processing unit (MP CORE1) 21 inside and outside the CPU logic, determines the current request to be processed, and ensures that there is no read-write error.

[0071] In step S107, after the read timing adjustment unit 31 caches the read data into the FIFO, the data state of the DTCM 213 in the first processing unit (MP CORE1) 21 is modified to a non-writable state, facilitating the transmission of the next data.

[0072] In step S108, the read timing adjustment unit 31 completes the CDC conversion of the internal high-speed clock and the low-speed peripheral clock.

[0073] In step S109, the FIFO in the read timing adjustment unit 31 is full, and the first processing unit (MP CORE1) 21 is back-pressured to write, and after storing a complete data packet, the data can be sent to the outside of the chip.

[0074] In step S110, the read timing adjustment unit 31 sends the data packet according to the packet sending interval configured by the CPU.

[0075] In step S111, until a data packet is processed, the read timing adjustment unit 31 sends an interrupt notification to the CPU.

[0076] In step S112, the CPU receives the interrupt notification and continues to configure the next data read task.

[0077] To clearly illustrate the scheme of the embodiments of the present disclosure, the following will be combined with FIG. 3 to describe in detail the packet receiving process of the Ethernet processing core. The packet receiving process includes the following steps S201 to S209.

[0078] In step S201, the second processing unit (MPCORE2) 22 fetches 2-bit width data from the DDR 20 and caches in the DTCM of the second processing unit (MPCORE2) 22, the write timing adjustment unit 32 converts the 2-bit data into 32 bits, and writes the super-long packet alarm (1 bit) + received packet length (12 bits) + valid byte (3 bits) + data (32 bits) for a total of 48 bits into the FIFO.

[0079] In step S202, the write timing adjustment unit 32 performs CDC processing on the data written into the FIFO, converting from the peripheral low-speed clock domain to the internal high-speed clock domain.

[0080] In step S203, when the FIFO stores a complete data packet, the second processing unit (MPCORE2) 22 reads the data from the FIFO according to the data state of the DTCM being writable, and writes the read data into the DTCM of the second processing unit (MPCORE2) 22, and after the second processing unit (MPCORE2) 22 writes the data, modifies the data state of the DTCM to be readable.

[0081] In step S204, the second read-write control unit 12 performs arbitration judgment on internal and external logic read-write requests of the second processing unit (MPCORE2) 22, to ensure that there is no read-write error.

[0082] In step S205, the second processing unit (MPCORE2) 22 reads the data in the DTCM according to the data state of the DTCM being readable, writes the data into the 2-ping-pong register groups in the Regfile of the second processing unit (MPCORE2) 22 after SFD and preamble stripping, and each ping-pong register includes 8 registers.

[0083] In step S206, the second processing unit (MPCORE2) 22 performs MAC filtering, VLAN (Virtual Local Area Network) filtering, and CRC checking on the data in the ping-pong register group.

[0084] In step S207, once the 8 registers in a group of ping-pong registers are full, the second processing unit (MPCORE2) 22 moves the data from the group of ping-pong registers to the DTCM for caching by SW8 instruction.

[0085] In step S208, the second processing unit (MPCORE2) 22 writes the data from the DTCM to the DDR 20.

[0086] In step S209, the second processing unit (MPCORE2) 22 sends an interrupt to the CPU to inform the CPU of the completion of processing of each data packet, and the CPU can configure a new data write task.

[0087] To clearly illustrate the scheme of the embodiments of the present disclosure, the flow control process of the Ethernet processing core is described in detail below in combination with FIG. 3. The flow control process is as follows:

[0088] The FIFO of the write timing adjustment unit 32 can generate a pause off instruction and a pause on instruction when the storage capacity reaches the upper and lower limits, respectively, and the upper and lower limits can be adjusted. The write timing adjustment unit 32 sends the pause off instruction and the pause on instruction to the read timing adjustment unit 31. When the read timing adjustment unit 31 receives the pause off instruction, it can insert a pause off frame according to the pause off frame value configured by the CPU, but cannot interrupt the sending of the original service data packet, and when the original data packet is being transmitted, the pause off frame is sent after the original data packet is completed. When the read timing adjustment unit 31 receives the pause on instruction, it can insert a pause on frame according to the pause on frame value configured by the CPU, and similarly cannot interrupt the sending of the original data packet.

[0089] FIG. 5 is a schematic diagram of an external interface of the Ethernet processing core provided by the embodiments of the present disclosure. As shown in FIG. 5, the external interface of the Ethernet processing core can include an AXI bus interface (AXI MASTER), an APB (Advanced Peripheral Bus) interface (APB SLAVE) interface, an interrupt request interface (adb_intr_o), and a transceiver interface (GMII / MII, RGMII). The AXI MASTER interface is interconnected with an external bus, and is used to read and write data to the memory, i.e., to load a task descriptor, read and send data, and write back the state of the task descriptor and write received data. The APB SLAVE interface is interconnected with a bus, and is used to configure a register and implement bus writing and register state reading. The GMII / MII / RGMII interface is time-division multiplexed, and only one interface is valid at the same time. The interrupt request interface is interconnected with a CPU, and is used for data packet sending and receiving.

[0090] The PHY module side interface is taken as an example of RMII in the embodiments of the present disclosure, and other physical interfaces, such as RevMII interface, SMII interface, SGMII interface, TBI (Ten Bit Interface) interface, RTBI (Reduced TBI) interface, SMA (Small A Type) interface, etc., are also within the protection scope of the embodiments of the present disclosure. The processing module of the embodiments of the present disclosure is programmable and expandable, and therefore, by adding microcode, other network functions such as token control, message frame structure change, self-negotiation function, fragmentation and reassembly, hash calculation function, 1588 timestamp, collision detection, etc., can also be realized. The chip of the embodiments of the present disclosure can include one or more soft cores (i.e., Ethernet processing cores), and the Ethernet processing core can also be a non-MP (Micro Processor, microprocessor) structure.

[0091] The embodiments of the present disclosure provide a self-developed IP core, which has the characteristics of strong flexibility, can be customized according to needs, can select one or several interfaces required by a project for use, and can save area and power consumption to the greatest extent; and uses a softening idea, because the microcode can be reconfigured after tape-out, if there is a BUG leak, it can be normally solved, and if there is a protocol upgrade, it can be seamlessly supported on the existing device.

[0092] The embodiments of the present disclosure also provide a chip, as shown in FIG. 6, which includes the target memory 20 as described above and the Ethernet processing core 10 as described above. The Ethernet processing core 10 is connected with the target memory 20 through a bus.

[0093] The embodiments of the present disclosure also provide an Ethernet processing core data processing method, which is applied to the Ethernet processing core 10 as described above, as shown in FIG. 7, and includes the following steps S11 to S13.

[0094] In step S11, the internal data processing request and the external data processing request are arbitrated to determine the current data processing request to be processed.

[0095] The read-write control module 1 arbitrates the received data processing request to determine whether the current data processing request to be processed is an internal data processing request or an external data processing request. If it is an internal data processing request, the following step S12 or step S13 is executed. The internal data processing request refers to a data processing request inside the processing module, and the external data processing request refers to a hardware accelerator logic outside the processing module.

[0096] In step S12, in the case that the data processing request is an internal data processing request and the internal data processing request is a data read request, first target data is read from the target memory according to the data processing request, and the first target data is cached; the first target data is cached after the external input / output width of the first target data is adjusted to an internal processing width, and the first target data is sent to the network device.

[0097] If it is an internal data read request, the first target data is read from the target memory 20 by using the first processing unit 21 and the read timing adjustment unit 31, and is cached and sent to the network device 200 after being processed, so as to realize data reading.

[0098] In step S13, in the case that the data processing request is an internal data processing request and the data processing request is a data write request, second target data sent by the network device is received, the internal processing width of the second target data is adjusted to an external input / output width after being cached; the cached second target data is obtained according to the data processing request, and the second target data is written into the target memory.

[0099] If it is an internal data write request, the second target data sent by the network device 200 is processed by using the write timing adjustment unit 32 and the second processing unit 22, and is cached and sent to the target memory 20, so as to realize data writing.

[0100] In some embodiments, the first processing unit includes a first execution unit, a first cache unit and a second cache unit; and the step of reading first target data from the target memory according to the data processing request and caching the first target data (i.e., step S12) in the case that the data processing request is an internal data processing request and the internal data processing request is a data read request includes the following steps: the first execution unit reads the first target data from the target memory according to the data processing request, caches the first target data in the second cache unit, processes the first target data to obtain processed first target data, caches the processed first target data in the first cache unit; the processed first target data is moved from the first cache unit to the second cache unit, and the data state of the second cache unit is modified to a readable state; in the case that the data state of the second cache unit is in the readable state, the processed first target data is read from the second cache unit and cached, and the data state of the second cache unit is modified to a writable state.

[0101] In some embodiments, the second processing unit comprises a second execution unit, a third cache unit and a fourth cache unit; the step of obtaining the cached second target data according to the data processing request and writing the second target data into the target memory (i.e., step S13) comprises the following steps: in the case that the data processing request is an internal data processing request and the data processing request is a data write request, and the data state of the fourth cache unit is a writable state, the second execution unit obtains the cached second target data, caches the second target data in the fourth cache unit, and modifies the data state of the fourth cache unit to a readable state; or, in the case that the data processing request is an internal data processing request and the data processing request is a data write request, and the data state of the fourth cache unit is a readable state, the second target data is imported from the fourth cache unit to the third cache unit, the second target data is processed to obtain processed second target data, the processed second target data is cached to the third cache unit, the processed second target data is moved from the third cache unit to the fourth cache unit, and the processed second target data is written from the fourth cache unit to the target memory.

[0102] In some embodiments, the step of arbitrating the internal data processing request and the external data processing request (i.e., step S11) comprises arbitrating the internal data processing request and the external data processing request in a polling manner.

[0103] The first read-write control unit 11 and the second read-write control unit 12 complete the read-write arbitration between the internal control information of the processing unit 2 and the logic of the hardware accelerator by reading and writing the register values of the DTCM of the first processing unit 21 and the second processing unit 22, and the arbitration manner adopts a polling manner. For example, the time period T1 of the internal data processing of the processing unit and the time period T2 of the external data processing of the processing unit are set in advance, T1 and T2 are alternated, the current data processing time period is identified by the register values of the DTCM, if there are both internal data processing requests and external data processing requests to be processed at present, the register values of the DTCM are used for arbitration, if it is determined that the current time period is the time period T1 of the internal data processing of the processing unit, the internal data processing request is processed at present.

[0104] In some embodiments, the Ethernet processing core data processing method can further comprise the following steps S21 and S22.

[0105] In step S21, in the case that the cache occupancy rate of the write timing adjustment unit of the Ethernet processing core is greater than a first threshold value, a first preset frame is sent according to a first preset frame value.

[0106] In step S22, in the case that the cache occupancy rate of the write timing adjustment unit of the Ethernet processing core is less than a second threshold value, a second preset frame is sent according to a second preset frame value; the first threshold value is greater than the second threshold value.

[0107] The first threshold is an upper limit threshold of the storage capacity of the FIFO of the write timing adjustment unit 31, and the second threshold is a lower limit threshold of the storage capacity of the FIFO of the write timing adjustment unit 31. When the FIFO reaches the upper limit of storage, the write timing adjustment unit 32 instructs the read timing adjustment unit 31 to send a pauseoff frame, and when the FIFO reaches the lower limit of storage, the write timing adjustment unit 32 instructs the read timing adjustment unit 31 to send a pauseon frame. By sending flow control frames, i.e., inserting pauseoff frames and pauseon frames, the flow control function can be achieved.

[0108] Those of ordinary skill in the art can understand that all or some of the functional modules / units in the steps, systems, and devices disclosed above can be implemented as software, firmware, hardware, and appropriate combinations thereof.

[0109] In a hardware implementation, the division between the functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component can have multiple functions, or one function or step can be performed by several physical components in cooperation.

[0110] Some or all of the physical components can be implemented as software executed by a processor, such as a central processing unit (CPU), a digital signal processor, or a microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit. Such software can be distributed on computer-readable media, which can include computer storage media (or non-transitory media) and communication media (or transitory media). As is well known to those of ordinary skill in the art, the term computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data. Computer storage media includes, but is not limited to, random access memory (RAM, more specifically SDRAM, DDR, etc.), read only memory (ROM), electrically erasable programmable read only memory (EEPROM), FLASH memory or other magnetic disk storage; compact disc read-only memory (CD-ROM), digital versatile discs (DVD) or other optical disk storage; magnetic cassettes, magnetic tapes, magnetic disk storage or other magnetic storage devices; any other medium that can be used to store the desired information and that can be accessed by a computer; and any other medium that can be used to store the desired information and that can be accessed by a computer. Furthermore, it is common technical knowledge among those of ordinary skill in the art that communication media typically includes computer readable instructions, data structures, program modules or other data in modulated data signals such as carrier waves or other transport mechanisms, and can include any information delivery medium.

[0111] The present disclosure has disclosed example embodiments, and while specific terminology has been employed, it is merely in the service of a general descriptive purpose and should not be construed as limiting. In some instances, it will be apparent to those skilled in the art that features, characteristics, and / or elements described in connection with a particular embodiment can be used in conjunction with other embodiments unless otherwise explicitly stated. As such, those skilled in the art will appreciate that various changes can be made in form and detail without departing from the scope of the disclosure as set forth in the appended claims.

Claims

1. An Ethernet processing core, comprising a read-write control module, a read timing adjustment unit, a write timing adjustment unit, a first processing unit and a second processing unit, the first and second processing units being micro processing units; the read-write control module is configured to arbitrate internal data processing requests and external data processing requests, and determine a current data processing request to be processed; the first processing unit is configured to read first target data from a target memory and cache the first target data, in a case that the data processing request is an internal data processing request and the internal data processing request is a data read request; the read timing adjustment unit is configured to obtain the first target data from the first processing unit, cache the first target data after adjusting an external input-output bit width of the first target data to an internal processing bit width, and send the first target data to a network device; the second processing unit is configured to obtain second target data from the write timing adjustment unit according to the data processing request, and write the second target data to the target memory, in a case that the data processing request is an internal data processing request and the data processing request is a data write request; and the write timing adjustment unit is configured to receive second target data sent by the network device, and cache the second target data after adjusting an internal processing bit width of the second target data to an external input-output bit width; and the second processing unit is configured to obtain the second target data from the write timing adjustment unit according to the data processing request, and write the second target data to a target memory, in a case that the data processing request is an internal data processing request and the data processing request is a data write request. the first processing unit comprises a first execution unit, a first cache unit and a second cache unit; 2. The Ethernet processing core of claim 1, wherein, the first execution unit is configured to read the first target data from the target memory, cache the first target data in the second cache unit, process the first target data to obtain processed first target data, cache the processed first target data to the first cache unit, move the processed first target data from the first cache unit to the second cache unit, and instruct the read timing adjustment unit to modify a data state of the second cache unit to a readable state, in a case that the data processing request is the internal data processing request and the internal data processing request is the data read request; the read timing adjustment unit is configured to read the processed first target data from the second cache unit and cache the processed first target data, and modify the data state of the second cache unit to a writable state, in a case that the data state of the second cache unit is the readable state. ​ 3. The Ethernet processing core of claim 2, wherein, The first cache unit includes two first ping-pong register groups, each of which includes a first preset number of registers; when each register included in one of the two first ping-pong register groups is full, the processed first target data is moved from the one first ping-pong register group to the second cache unit. The first execution unit is configured to read the first preset number of first target data from the target memory.

4. The Ethernet processing core of claim 1, wherein, The read timing adjustment unit is configured to send a complete data packet of the first target data to the network device.

5. The Ethernet processing core of claim 1, wherein, The read timing adjustment unit is further configured to send each data packet of the first target data to the network device according to a preset packet sending interval.

6. The Ethernet processing core of claim 1, wherein, The second processing unit includes a second execution unit, a third cache unit and a fourth cache unit. The second execution unit is configured to: in a case where the data processing request is an internal data processing request and the data processing request is a data write request, and the data state of the fourth cache unit is a writable state, obtain the second target data from the write timing adjustment unit, cache the second target data in the fourth cache unit, and instruct the write timing adjustment unit to modify the data state of the fourth cache unit to a readable state; and in a case where it is determined that the data state of the fourth cache unit is a readable state, import the second target data from the fourth cache unit to the third cache unit, process the second target data to obtain processed second target data, cache the processed second target data to the third cache unit, move the processed second target data from the third cache unit to the fourth cache unit, and write the processed second target data from the fourth cache unit to the target memory.

7. The Ethernet processing core of claim 6, wherein, The third cache unit includes two second ping-pong register groups, each of which includes a second preset number of registers. The second execution unit is configured to write the second preset number of processed second target data from the fourth cache unit to the target memory; wherein when each register included in one of the two second ping-pong register groups is full, the processed second target data is moved from the one second ping-pong register group to the fourth cache unit.

8. The Ethernet processing core of claim 1, wherein, The read-write control module includes a first read-write control unit and a second read-write control unit, the first read-write control unit is connected with the read timing adjustment unit and the first processing unit respectively, and the second read-write control unit is connected with the write timing adjustment unit and the second processing unit respectively. The first read-write control unit and the second read-write control unit are configured to arbitrate the internal data processing request and the external data processing request in a polling manner.

9. The Ethernet processing core of claim 1, wherein, The write timing adjustment unit is further configured to: send a first indication to the read timing adjustment unit if the cache occupancy rate of the write timing adjustment unit is greater than a first threshold; and send a second indication to the read timing adjustment unit if the cache occupancy rate of the write timing adjustment unit is less than a second threshold, the first threshold being greater than the second threshold. The read timing adjustment unit is configured to: send a first preset frame according to a first preset frame value corresponding to the first indication; and send a second preset frame according to a second preset frame value corresponding to the second indication.

10. A chip comprising a target memory and an Ethernet processing core according to any one of claims 1 to 9, the Ethernet processing core being connected to the target memory through a bus.

11. An electronic device comprising the chip according to claim 10.

12. An Ethernet processing core data processing method, the method being applied to the Ethernet processing core according to any one of claims 1 to 9, the method comprising: arbitrating an internal data processing request and an external data processing request to determine a current data processing request to be processed; in a case where the data processing request is an internal data processing request and the internal data processing request is a data read request, reading first target data from a target memory according to the data processing request, caching the first target data, caching the first target data after adjusting an external input / output bit width of the first target data to an internal processing bit width, and sending the first target data to a network device; or in a case where the data processing request is an internal data processing request and the data processing request is a data write request, receiving second target data sent by the network device, caching the second target data after adjusting an internal processing bit width of the second target data to an external input / output bit width, obtaining the cached second target data according to the data processing request, and writing the second target data into the target memory. The first processing unit comprises a first execution unit, a first cache unit and a second cache unit, 13. The method of claim 12, wherein, in a case where the data processing request is an internal data processing request and the internal data processing request is a data read request, reading the first target data from the target memory according to the data processing request, and caching the first target data, comprising: the first execution unit reads the first target data from the target memory according to the data processing request, caches the first target data in the second cache unit, processes the first target data to obtain processed first target data, caches the processed first target data in the first cache unit; moving the processed first target data from the first cache unit to the second cache unit, and modifying a data state of the second cache unit to a readable state; and in a case where the data processing request is an internal data processing request and the internal data processing request is a data write request, receiving second target data sent by the network device, caching the second target data after adjusting an internal processing bit width of the second target data to an external input / output bit width, obtaining the cached second target data according to the data processing request, and writing the second target data into the target memory. In a case where the data state of the second cache unit is a readable state, the processed first target data is read from the second cache unit and cached, and the data state of the second cache unit is modified to a writable state.

14. The method of claim 12, wherein, The second processing unit comprises a second execution unit, a third cache unit and a fourth cache unit, According to the data processing request, the second target data cached is obtained, and the second target data is written into the target memory, comprising: In a case where the data processing request is an internal data processing request and the data processing request is a data write request, and the data state of the fourth cache unit is a writable state, the second execution unit obtains the second target data cached, caches the second target data in the fourth cache unit, and modifies the data state of the fourth cache unit to a readable state; or, In a case where the data processing request is an internal data processing request and the data processing request is a data write request, and the data state of the fourth cache unit is a readable state, the second target data is imported from the fourth cache unit to the third cache unit, the second target data is processed to obtain processed second target data, the processed second target data is cached to the third cache unit, the processed second target data is moved from the third cache unit to the fourth cache unit, and the processed second target data is written from the fourth cache unit to the target memory.

15. The method of claim 12, wherein, The arbitration on the internal data processing request and the external data processing request comprises: The arbitration on the internal data processing request and the external data processing request is performed in a polling manner.

16. The method of claim 12, further comprising: In a case where the cache occupancy rate of the write timing adjustment unit of the Ethernet processing core is greater than a first threshold value, a first preset frame is sent according to a first preset frame value; In a case where the cache occupancy rate of the write timing adjustment unit of the Ethernet processing core is less than a second threshold value, a second preset frame is sent according to a second preset frame value; The first threshold value is greater than the second threshold value.

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