Printed circuit board, interposer and electronic device

Abstract

The present application relates to the technical field of electronics. Provided are a printed circuit board, an interposer and an electronic device. The printed circuit board is provided with a first mounting area, a second mounting area and a third mounting area, the first mounting area being used for mounting a system on chip, the second mounting area being used for mounting a first memory or an interposer, and the third mounting area being used for mounting a second memory; the first mounting area is provided with a first-type signal pin and a second-type signal pin, the second mounting area is provided with a third-type signal pin, a fourth-type signal pin and a fifth-type signal pin, and the third mounting area is provided with a sixth-type signal pin; the first-type signal pin is electrically connected to the third-type signal pin by means of a first-type signal line in the printed circuit board, the second-type signal pin is electrically connected to the fourth-type signal pin by means of a second-type signal line in the printed circuit board, and the fifth-type signal pin is electrically connected to the sixth-type signal pin by means of a third-type signal line in the printed circuit board.

Description

Printed circuit board, adapter board and electronic device

[0001] Cross Reference to Related Applications

[0002] The present application claims priority to Chinese Patent Application No. 202411079994.0, filed on August 07, 2024, the contents of which are incorporated herein by reference in its entirety. TECHNICAL FIELD

[0003] The present application relates to the field of electronic technology, and in particular, to a printed circuit board, an adapter board and an electronic device. BACKGROUND

[0004] At present, there are various types of memories, such as integrated memories and separate memories, wherein the integrated memories refer to memories integrated with memories and flash memories, and the separate memories refer to memories separated from memories and flash memories. In order to save costs and improve the flexibility of electronic product design, the printed circuit board of the electronic product, such as the mainboard, often needs to be compatible with multiple types of memories. However, in the related art, different printed circuit boards are designed for different types of memories for installation, which not only has high cost, but also has poor flexibility. SUMMARY

[0005] The embodiments of the present application provide a printed circuit board, an adapter board and an electronic device, which can be compatible with the installation of multiple types of memories through the printed circuit board, thereby reducing the development cost of the electronic product and improving the flexibility of memory selection.

[0006] In a first aspect, the embodiments of the present application provide a printed circuit board, which is provided with a first mounting area, a second mounting area and a third mounting area, the first mounting area is used for mounting a system on chip, the second mounting area is used for mounting a first memory or an adapter board, and the third mounting area is used for mounting a second memory.

[0007] The first mounting area is provided with first type signal pins and second type signal pins, the second mounting area is provided with third type signal pins, fourth type signal pins and fifth type signal pins, and the third mounting area is provided with sixth type signal pins.

[0008] The first type signal pins are electrically connected to the third type signal pins through first type signal lines in the printed circuit board, the second type signal pins are electrically connected to the fourth type signal pins through second type signal lines in the printed circuit board, and the fifth type signal pins are electrically connected to the sixth type signal pins through third type signal lines in the printed circuit board.

[0009] The first memory is a memory integrated with flash memory and internal memory, the second memory is flash memory or internal memory, the first type of signal line is used for transmitting internal memory signals, the second type of signal line is used for transmitting flash memory signals, the third type of signal line is used for transmitting internal memory signals when the second memory is internal memory, and the third type of signal line is used for transmitting flash memory signals when the second memory is flash memory.

[0010] In a second aspect, an adapter board is provided. The first surface of the adapter board is provided with a seventh type of signal pin, an eighth type of signal pin and a ninth type of signal pin. The first surface of the adapter board is used to connect with a printed circuit board. The second surface of the adapter board is provided with a fourth mounting area. The fourth mounting area is used to mount a third memory. The fourth mounting area is provided with a tenth type of signal pin.

[0011] The seventh type of signal pin and the tenth type of signal pin are electrically connected through a fourth type of signal line in the adapter board. The eighth type of signal pin and the ninth type of signal pin are electrically connected through a fifth type of signal line in the adapter board.

[0012] The first surface of the adapter board is a surface used to mount the adapter board to the printed circuit board. The second surface of the adapter board is opposite to the first surface of the adapter board. One of the fourth type of signal line and the fifth type of signal line is used to transmit internal memory signals, and the other is used to transmit flash memory signals. The third memory is flash memory or internal memory.

[0013] In a third aspect, an electronic device is provided. The electronic device includes the printed circuit board, the system-level chip and the first memory provided in the first aspect.

[0014] The system-level chip is mounted on the first mounting area of the printed circuit board. An eleventh type of signal pin of the system-level chip is electrically connected with a first type of signal pin of the first mounting area. A twelfth type of signal pin of the system-level chip is electrically connected with a second type of signal pin of the first mounting area.

[0015] The first memory is mounted on the second mounting area of the printed circuit board. A thirteenth type of signal pin of the first memory is electrically connected with a third type of signal pin of the second mounting area. A fourteenth type of signal pin of the first memory is electrically connected with a fourth type of signal pin of the second mounting area.

[0016] In a fourth aspect, an electronic device is provided. The electronic device includes the printed circuit board provided in the first aspect, the adapter board provided in the second aspect, the system-level chip, the second memory and the third memory.

[0017] The system-level chip is mounted on the first mounting area of the printed circuit board, the eleventh type of signal pin of the system-level chip is electrically connected with the first type of signal pin of the first mounting area, and the twelfth type of signal pin of the system-level chip is electrically connected with the second type of signal pin of the first mounting area.

[0018] The adapter board is mounted on the second mounting area of the printed circuit board, the seventh type of signal pin of the adapter board is electrically connected with the third type of signal pin of the second mounting area, the eighth type of signal pin of the adapter board is electrically connected with the fourth type of signal pin of the second mounting area, and the ninth type of signal pin of the adapter board is electrically connected with the fifth type of signal pin of the second mounting area.

[0019] The second memory is mounted on the third mounting area of the printed circuit board, and the fifteenth type of signal pin of the second memory is electrically connected with the sixth type of signal pin of the third mounting area.

[0020] The third memory is mounted on the fourth mounting area of the adapter board, and the sixteenth type of signal pin of the third memory is electrically connected with the tenth type of signal pin of the fourth mounting area.

[0021] In the embodiments of the present application, the printed circuit board is provided with the first mounting area, the second mounting area and the third mounting area, the first mounting area is used for mounting the system-level chip, the second mounting area is used for mounting the first memory or the adapter board, and the third mounting area is used for mounting the second memory. Therefore, the integrated memory (i.e. the first memory) and the separated memory (i.e. the second memory) can be mounted on the printed circuit board, that is, the printed circuit board supports the mounting of different types of memories, which is beneficial to reduce the development cost of electronic products and improve the flexibility of memory selection. In addition, in the case of mounting the first memory on the printed circuit board, the signal lines reserved for the second memory (i.e. the signal lines between the fifth type of signal pin and the sixth type of signal pin) are suspended and have no connection with the signal lines of the first memory, and there is no signal line stub problem, so that the influence of the signal lines reserved for the second memory on the signals of the first memory can be avoided. BRIEF DESCRIPTION OF DRAWINGS

[0022] FIG. 1a is a schematic diagram of mounting an integrated memory on a PCB1 according to an embodiment of the present application;

[0023] FIG. 1b is a schematic diagram of mounting an integrated memory on a PCB1 according to an embodiment of the present application;

[0024] FIG. 1c is a schematic diagram of mounting a separated memory on a PCB2 according to an embodiment of the present application;

[0025] Fig. 1d is a schematic diagram of mounting the integrated memory on the PCB 2 according to an embodiment of the present application;

[0026] Fig. 2 is a schematic diagram of mounting the separated memory through the adapter plate according to an embodiment of the present application;

[0027] Fig. 3 is a side view of a printed circuit board according to an embodiment of the present application;

[0028] Fig. 4 is a top view of a printed circuit board according to an embodiment of the present application;

[0029] Fig. 5a is a schematic diagram of mounting the integrated memory on the printed circuit board according to an embodiment of the present application;

[0030] Fig. 5b is a schematic diagram of mounting the separated memory on the printed circuit board according to an embodiment of the present application;

[0031] Fig. 6a is a schematic diagram of mounting the integrated memory on the printed circuit board according to an embodiment of the present application;

[0032] Fig. 6b is a schematic diagram of mounting the separated memory on the printed circuit board according to an embodiment of the present application;

[0033] Fig. 7 is a schematic diagram of the distribution of the first mounting area, the second mounting area and the third mounting area of the printed circuit board according to an embodiment of the present application;

[0034] Fig. 8 is a schematic diagram of the adapter plate according to an embodiment of the present application;

[0035] Fig. 9a is a schematic diagram of the pin distribution of the first memory according to an embodiment of the present application;

[0036] Fig. 9b is a schematic diagram of the pin distribution of the first side of the adapter plate according to an embodiment of the present application;

[0037] Fig. 9c is a schematic diagram of the pin distribution of the second mounting area of the printed circuit board according to an embodiment of the present application;

[0038] Fig. 10 is a schematic diagram of an electronic device according to an embodiment of the present application;

[0039] Fig. 11 is a schematic diagram of another electronic device according to an embodiment of the present application. DETAILED DESCRIPTION

[0040] The technical solutions in the embodiments of the present application will be clearly described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all of the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art belong to the scope of protection of the present application.

[0041] The terms "first", "second", etc. in the specification and claims of the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described herein, and the objects distinguished by "first", "second", etc. are generally a class, and do not limit the number of objects, for example, the first object can be one or more. In addition, "and / or" in the specification and claims indicates at least one of the connected objects, and the character " / ", generally indicates that the front and rear associated objects are in a "or" relationship.

[0042] For ease of understanding, some content related to the embodiments of the present application is described below:

[0043] In the design of electronic devices, such as the design of mobile phones or tablets, flash memory and memory chips are often used, and different types of chips may have different packaging and ball maps. For example, the number of chip pins (PINs) is different, the layout of chip pins is different, the size of chip is different, the definition of chip pins is different, etc. For example, for a 254 ball UFS-based multi-chip package (uMCP), i.e., a 254 ball uMCP, which integrates UFS2.2 and SDRAM LPDDR4X, and a 200 ball separate LPDDR4X, the number of pins, the layout of pins, and the size of chips are different. For a 153 ball separate UFS and a 153 ball separate eMMC, the number of pins and the layout of pins are the same, but the definition of each pin is different. It should be noted that the specific packaging and ball map of the above 254 ball uMCP, 200 ball separate LPDDR4X, 153 ball separate UFS and 153 ball separate eMMC can be referred to related technologies, and the embodiments of the present application do not repeat them.

[0044] For the storage chips commonly used in electronic devices, according to the protocol, it can be divided into memory: LPDDR4X, LPDDR5, LPDDR5X; flash memory: eMMC, UFS2.2, UFS3.1, UFS4.0, etc. According to the packaging, it can be divided into embedded multi-chip packaging (eMCP), uMCP, separate UFS, separate eMMC, separate LPDDR, packaging on packaging (POP) LPDDR, etc.

[0045] Table 1

[0046] In the design of electronic products, combinations of the types of materials (i.e. memories) listed in Table 1 may be used. The characteristics of these combinations are that the protocols of the memories are the same and the packages are different. The circuit board design principle of this type of combination is as follows:

[0047] For example, eMCP / uMCP (LPDDR4X) and separate LPDDR4X are chips with the same LPDDR4X protocol but different packages. Two printed circuit boards (PCBs) are needed to be designed, for example, as shown in FIGS. 1a-1d, or an adapter board is added to the same PCB to realize the use in the same electronic product, for example, as shown in FIG. 2. When the separate flash memory eMMC / UFS is of the same type as the flash memory of the integrated storage MCP, a signal switching circuit needs to be added to realize the corresponding connection of the signals. The commonly used signal switching circuit is a jumper resistor, which is pasted according to the corresponding path resistance.

[0048] It should be further pointed out that in the design of 0Ω resistor common pad signal line, according to the needs of pasting the corresponding path or the signal line using serial connection exists stake line, these designs exist the shortcomings of deteriorating signal quality, increasing the area of PCB design, and poor consistency of the path, which will also reduce the reliability and stability of the system, and bring risks to the long-term use of the product. In addition, in the case of signal switching through a two-way signal switching switch chip, such design is limited by the bandwidth of the switch chip and cannot be applied to 6GHz or 12GHz high-speed signals. The insertion loss and channel isolation of the switch chip are also difficult to be low, and the application of multiple signals will increase the PCB design area and material cost, and the realizability is low.

[0049] The printed circuit board, adapter board and electronic device provided by the embodiments of the present application will be described in detail in combination with the drawings and specific embodiments and their application scenarios.

[0050] The embodiment of the present application provides a printed circuit board, referring to FIG. 3 and FIG. 4, FIG. 3 is a side view of the printed circuit board provided by the embodiment of the present application, and FIG. 4 is a top view of the printed circuit board provided by the embodiment of the present application. It should be noted that the printed circuit board shown in FIG. 3 and FIG. 4 is only an example of the printed circuit board provided by the embodiment of the present application, and does not constitute a limitation on the printed circuit board provided by the embodiment of the present application. In addition, each short vertical line in FIG. 3 represents a signal pin on the printed circuit board, and the printed circuit board provided by the embodiment of the present application can also include other signal pins, for example, a signal pin connected to ground, a signal pin connected to a power supply, etc., which is not limited in the embodiment.

[0051] As shown in FIG. 3 and FIG. 4, the printed circuit board 10 is provided with a first mounting area 101, a second mounting area 102 and a third mounting area 103, the first mounting area 101 is used for mounting a system on chip (SoC), the second mounting area 102 is used for mounting a first memory or a conversion board, and the third mounting area 103 is used for mounting a second memory.

[0052] The first mounting area 101 is provided with a first type of signal pin 1011 and a second type of signal pin 1012, the second mounting area 102 is provided with a third type of signal pin 1021, a fourth type of signal pin 1022 and a fifth type of signal pin 1023, and the third mounting area 103 is provided with a sixth type of signal pin 1031.

[0053] The first type of signal pin 1011 is electrically connected with the third type of signal pin 1021 through a first type of signal line 104 in the printed circuit board 10, the second type of signal pin 1012 is electrically connected with the fourth type of signal pin 1022 through a second type of signal line 105 in the printed circuit board, and the fifth type of signal pin 1023 is electrically connected with the sixth type of signal pin 1031 through a third type of signal line 106 in the printed circuit board.

[0054] The first memory is a memory integrated with a flash memory and a memory, the second memory is a flash memory or a memory, the first type of signal line 104 is used for transmitting a memory signal, the second type of signal line 105 is used for transmitting a flash memory signal, the third type of signal line 106 is used for transmitting a memory signal in the case that the second memory is a memory, and the third type of signal line 106 is used for transmitting a flash memory signal in the case that the second memory is a flash memory.

[0055] In the embodiment, the above-mentioned conversion board can be used for mounting a third memory. Alternatively, the above-mentioned conversion board can also be used for electrically connecting the third type of signal pin 1021 or the fourth type of signal pin 1022 with the fifth type of signal pin 1023.

[0056] The first memory can also be referred to as an integrated memory, which integrates a flash memory and a memory. For example, the first memory can include, but is not limited to, uMCP or eMCP4, such as uMCP4X, uMCP5, eMCP4X, or uMCP5X, etc.

[0057] The second memory and the third memory can also be referred to as separate memories, such as a separate memory and a separate flash memory. One of the second memory and the third memory is a memory, and the other is a flash memory. For example, the second memory is a memory, and the third memory is a flash memory, or the third memory is a memory, and the second memory is a flash memory. For example, the flash memory can include, but is not limited to, UFS2.2, UFS3.0, UFS3.1, UFS4.0, or eMMC, etc. The memory can include, but is not limited to, LPDDR4, LPDDR4X, LPDDR5, or LPDDR5X, etc.

[0058] The protocol type of the memory of the first memory can be the same as or different from the protocol type of the memory of the second memory and the third memory. The protocol type of the flash memory of the first memory can be the same as or different from the protocol type of the flash memory of the second memory and the third memory.

[0059] The integrated memory (i.e., the first memory) and the separate memory (i.e., the second memory and the third memory) can be reasonably set according to requirements.

[0060] For ease of description, the first memory is referred to as an integrated memory, one of the second memory and the third memory is referred to as a separate memory, and the other is referred to as a separate flash memory.

[0061] The first type of signal pin (i.e., PIN) 1011 is used to input a memory signal from the SoC or output a memory signal to the SoC, and can include at least one signal pin. The second type of signal pin 1012 is used to input a flash memory signal from the SoC or output a flash memory signal to the SoC, and can include at least one signal pin.

[0062] The third type of signal pin 1021 is used to input a memory signal from the integrated memory or the separate memory or output a memory signal to the integrated memory or the separate memory, and can include at least one signal pin. The fourth type of signal pin 1022 is used to input a flash memory signal from the integrated memory or the separate flash memory or output a flash memory signal to the integrated memory or the separate flash memory, and can include at least one signal pin.

[0063] The fifth type of signal pin 1023 is used to input or output memory signals from or to the third type of signal pin, or is used to input or output flash memory signals from or to the fourth type of signal pin. It should be noted that when the first memory is installed in the second mounting area, the fifth type of signal pin 1023 is suspended, that is, the fifth type of signal pin 1023 is not electrically connected to any of the third type of signal pin and the fourth type of signal pin; when the adapter plate is installed in the second mounting area, the fifth type of signal pin 1023 can be electrically connected to the third type of signal pin or the fourth type of signal pin through the adapter plate.

[0064] Taking the fifth type of signal pin 1023 as a flash memory signal pin as an example, the fifth type of signal pin 1023 can include pins of various signals required for flash memory operation, for example, taking UFS as an example, the fifth type of signal pin 1023 can include but is not limited to DIN0_t, DIN0_c, DIN1_t, DIN1_c, DOUT0_t, DOUT0_c, DOUT1_t, DOUT1_c, REF_CLK, and the like. Exemplarily, the meanings of the various signal pins can be as shown in Table 2.

[0065] Table 2

[0066] The sixth type of signal pin 1031 is used to input or output memory signals from or to the separate memory, or is used to input or output flash memory signals from or to the separate flash memory.

[0067] The board material, number of layers, number of stages, dielectric constant, and the like of the printed circuit board can be reasonably set according to requirements. For example, the board material of the printed circuit board can be FR-4 board material, the number of layers of the printed circuit board can be greater than or equal to 8 layers, and the number of stages of the printed circuit board can be greater than or equal to 2 stages. In addition, the design of the internal signal lines of the printed circuit board can be adjusted in terms of line width, line spacing, ground isolation, layer spacing, size and position of punching, and the like according to signal simulation to meet the signal quality requirements under high speed of flash memory signals, for example, for UFS, the speed can reach 3GHz, 6GHz, 12GHz, and the like, and for eMMC, the speed can reach 200MHz.

[0068] It should be noted that the higher the number of stages of the printed circuit board, the more conducive to achieving design requirements, but the higher the cost. In some optional embodiments, the printed circuit board can be a mainboard of an electronic device.

[0069] The various signal lines of the printed circuit board satisfy the design requirements of the corresponding signals, wherein the design requirements can include but are not limited to eye diagram, insertion loss, return loss, impedance, etc. Taking the second memory as an example, the design of the second type of signal line of the printed circuit board satisfies the design requirements of the signals of the flash memory in the integrated memory, for example, the design of the signal line 105 as shown in FIG. 5a satisfies the design requirements of the signals of the flash memory in the integrated memory; the combined design of the second type of signal line of the printed circuit board, the fifth type of signal line of the adapter board and the third type of signal line of the printed circuit board satisfies the design requirements of the signals of the separate flash memory, for example, the combined design of the signal line 105, the signal line 204 and the signal line 106 as shown in FIG. 5b satisfies the design requirements of the signals of the separate flash memory.

[0070] The SoC, the first memory, the adapter board and the second memory can be mounted on the printed circuit board by means of patching, or can be mounted on the printed circuit board by means of plugging, etc., which is not limited in the embodiment.

[0071] The application of the printed circuit board provided by the embodiment of the present application is illustrated as follows in combination with the drawings:

[0072] In the case of selecting to install the integrated memory (i.e. the first memory) 40 on the printed circuit board 10, for example, as shown in FIG. 5a, the integrated memory 40 is installed on the second mounting area 102 of the printed circuit board 10, the signal line 104 (i.e. the first type of signal line) represents the signal line of the memory, the signal line 105 (i.e. the second type of signal line) represents the signal line of the flash memory, the position of the separate flash memory (i.e. the third mounting area 103) is left empty without installing the chip, and the signal line 106 (i.e. the third type of signal line) represents the signal line reserved for connecting the signal pins of the flash memory, which is not connected at this time. It should be noted that in FIG. 5a, the separate flash memory and its ball and the colorless filling ball below the integrated memory represent the meaning that there is no integrated memory in the case of installing the integrated memory, so that the signal line reserved for the separate flash memory will not affect the signals of the integrated memory.

[0073] In the case of selecting to install the separate memory on the printed circuit board 10, for example, as shown in FIG. 5b, the adapter board 20 is installed on the second mounting area 102 of the printed circuit board 10, the separate memory (i.e. the third memory) 60 is installed on the adapter board, wherein the signal line 104 (i.e. the first type of signal line) and the signal line 203 (i.e. the fourth type of signal line) represent the signal lines of the memory, the signal line 105 (i.e. the second type of signal line) represents the signal line of the flash memory, and the separate flash memory (i.e. the second memory) 50 is installed in the position reserved for the separate flash memory (i.e. the third mounting area 103) on the printed circuit board 10, and the signal line 106 (i.e. the third type of signal line) represents the signal line reserved for connecting the signal pin of the flash memory. In this case, the fifth type of signal pin 1023 of the second mounting area 102 is electrically connected to the fourth type of signal pin 1022 through the signal line (i.e. the signal line 204) of the adapter board 20, thereby enabling the separate flash memory. Specifically, the connection path of the signal pin of the SoC and the corresponding signal pin of the separate flash memory, taking the signal transmission path from the SoC to the separate flash memory as an example, the flash memory signal ball on the SoC chip is connected to the ball (i.e. the flash memory signal pin ball) of the adapter board through the signal line 105 of the printed circuit board, enters the adapter board, is connected to the newly added flash memory signal pin ball through the signal line 204 in the adapter board, the newly added flash memory signal pin ball is welded to the printed circuit board, and then is connected to the corresponding signal pin ball of the separate flash memory through the signal line 106; the signal transmission path from the separate flash memory to the SoC is opposite to the above path.

[0074] As can be seen from the above, the printed circuit board provided in the embodiment supports the installation of different types of memories, which is conducive to reducing the design and development cost of electronic products, increasing the flexibility of electronic product production material supply, and meeting the needs of storage capacity expansion, performance differentiation, etc.

[0075] The printed circuit board provided in the embodiment is provided with a first mounting area, a second mounting area and a third mounting area, the first mounting area is used to install a system-on-chip, the second mounting area is used to install a first memory or an adapter board, and the third mounting area is used to install a second memory. Therefore, the integrated memory (i.e. the first memory) and the separate memory (i.e. the second memory) can be installed on the printed circuit board, i.e. the printed circuit board supports the installation of different types of memories, which is conducive to reducing the development cost of electronic products and improving the flexibility of memory selection in the electronic product design process. In addition, in the case of installing the first memory on the printed circuit board, the signal lines (i.e. the signal lines between the fifth type of signal pin and the sixth type of signal pin) reserved for the second memory on the printed circuit board are suspended and have no connection with the signal lines of the first memory, and there is no signal line stub problem, so that the influence of the signal lines reserved for the second memory on the signal of the first memory can be avoided.

[0076] Optionally, in the case that the second memory is a memory and the third memory is a flash memory, the protocol type of the memory integrated in the first memory is the same as the protocol type of the second memory, and the protocol type of the flash memory integrated in the first memory is the same as the protocol type of the third memory.

[0077] Alternatively,

[0078] In the case that the second memory is a flash memory and the third memory is a memory, the protocol type of the memory integrated in the first memory is the same as the protocol type of the third memory, and the protocol type of the flash memory integrated in the first memory is the same as the protocol type of the second memory.

[0079] In the embodiment, the protocol type of the memory of the integrated memory is the same as the protocol type of the separated memory, and the protocol type of the flash memory of the integrated memory is the same as the protocol type of the separated flash memory, wherein the protocol type can include a Joint Electron Device Engineering Council (JEDEC) protocol type.

[0080] Exemplarily, the combination between the integrated memory and the separated memory can include any one of the following:

[0081] Combination 1: the integrated memory is uMCP (UFS2.2 or UFS2.1+LPDDR4X or LPDDR4), the separated memory is LPDDR4X or LPDDR4, and the separated flash memory is UFS2.1 or UFS2.2;

[0082] Combination 2: the integrated memory is uMCP (UFS3.1 or UFS3.0+LPDDR5 or LPDDR5X), the separated memory is LPDDR5 or LPDDR5X, and the separated flash memory is UFS3.0 or UFS3.1;

[0083] Combination 3: the integrated memory is uMCP (UFS4.0 or UFS4.1+LPDDR5 or LPDDR5X), the separated memory is LPDDR5 or LPDDR5X, and the separated flash memory is UFS4.0 or UFS4.1;

[0084] Combination 4: the integrated memory is eMCP (eMMC5.x+LPDDR4X or LPDDR4), the separated memory is LPDDR4X or LPDDR4, and the separated flash memory is eMMC5.x;

[0085] Combination 5: integrated memory is eMCP (eMMC4.x+LPDDR3), separate memory is LPDDR3, and separate flash memory is eMMC4.x.

[0086] In this embodiment, the protocol type of the memory of the integrated memory is the same as that of the separate memory, and the protocol type of the flash memory of the integrated memory is the same as that of the separate flash memory. In this way, the integrated memory and the separate memory can directly share the same signal pins on the printed circuit board, and thus the signal wiring of the printed circuit board can be simplified.

[0087] In some optional embodiments, the protocol type of the memory of the integrated memory can also be different from that of the separate memory, and the protocol type of the flash memory of the integrated memory can also be different from that of the separate flash memory. In this case, the SoC can perform protocol conversion on the memory signal or the flash signal. For example, in the case of installing a memory of a first protocol type on the printed circuit board, the SoC inputs a memory signal of the first protocol type to the first type of signal pins of the printed circuit board; in the case of installing a memory of a second protocol type on the printed circuit board, the SoC inputs a memory signal of the second protocol type to the first type of signal pins of the printed circuit board; similarly, in the case of installing a flash memory of a third protocol type on the printed circuit board, the SoC inputs a flash signal of the third protocol type to the second type of signal pins of the printed circuit board; in the case of installing a flash memory of a fourth protocol type on the printed circuit board, the SoC inputs a flash signal of the fourth protocol type to the second type of signal pins of the printed circuit board. In this way, the integrated memory and the separate memory can also directly share the same signal pins on the printed circuit board, and thus the signal wiring of the printed circuit board can be simplified.

[0088] Optionally, the first mounting area 101, the second mounting area 102 and the third mounting area 103 are arranged on the same surface of the printed circuit board.

[0089] Alternatively,

[0090] The first mounting area 101 and the second mounting area 102 are arranged on the first surface of the printed circuit board, and the third mounting area 103 is arranged on the second surface of the printed circuit board. The first surface and the second surface are two opposite surfaces.

[0091] In an embodiment, the first mounting area 101, the second mounting area 102 and the third mounting area 103 are arranged on the same surface of the printed circuit board. For example, as shown in FIGS. 5a and 5b, the first mounting area 101, the second mounting area 102 and the third mounting area 103 are arranged on the top surface of the printed circuit board, which is advantageous for shortening the signal wiring.

[0092] In another embodiment, the first mounting area 101, the second mounting area 102 and the third mounting area 103 are arranged on opposite surfaces of the printed circuit board, for example, as shown in FIG. 6a and FIG. 6b, the first mounting area 101 and the second mounting area 102 are arranged on the top surface of the printed circuit board, and the third mounting area 103 is arranged on the bottom surface of the printed circuit board, which is conducive to avoiding the concentration of memories on the same surface of the printed circuit board, and thus is conducive to reducing the size of the printed circuit board.

[0093] It should be further noted that, in the case of the same signal wire length, the signal quality when the third mounting area 103 is arranged on the top surface of the printed circuit board is better than the signal quality when the third mounting area 103 is arranged on the bottom surface of the printed circuit board.

[0094] In some optional embodiments, the third mounting area 103 can be arranged at a position opposite to the fifth type of signal pin in the second surface, which is conducive to shortening the signal wire length between the fifth type of signal pin and the sixth type of signal pin.

[0095] Optionally, at least one of the following is met between the first mounting area 101 and the second mounting area 102:

[0096] The second mounting area 102 is located on a first side of the first mounting area 101, and the first side is a side of the first mounting area 101 closest to the distance between the first type of signal pin 1011 or the second type of signal pin 1012.

[0097] The distance between the first mounting area 101 and the second mounting area 102 is less than or equal to a first threshold value.

[0098] The first threshold value can be reasonably set according to actual needs, for example, the first threshold value is 1mm or 1.5mm, etc.

[0099] In some optional embodiments, the edge of the first mounting area 101 and the edge of the second mounting area 102 are parallel, for example, the vertical edge of the first mounting area 101 and the vertical edge of the second mounting area 102 are parallel, or the horizontal edge of the first mounting area 101 and the horizontal edge of the second mounting area 102 are parallel.

[0100] It can be understood that the relative positions of the first mounting area and the second mounting area can be determined according to the distribution positions of the various types of signal pins of the first mounting area 101 and the distribution positions of the corresponding various types of signal pins in the second mounting area 102.

[0101] In some optional embodiments, the lower edge of the first mounting area 101 in the horizontal direction can be aligned with the lower edge of the second mounting area 102 in the horizontal direction, or the upper edge of the first mounting area 101 in the horizontal direction can be aligned with the upper edge of the second mounting area 102 in the horizontal direction, or the center point of the first mounting area 101 and the center point of the second mounting area 102 can be located on the same horizontal line.

[0102] For example, as shown in FIG. 7, when the first type of signal pin 1011 or the second type of signal pin 1012 is located on the right side of the first mounting area 101, the second mounting area 102 is arranged on the right side of the first mounting area 101, the second mounting area 102 is parallel to the edge of the first mounting area 101, and the center point of the second mounting area 102 and the center point of the first mounting area 101 are located on the same horizontal line. This layout is conducive to shortening the signal line between the first mounting area 101 and the second mounting area 102, thereby facilitating the guarantee of signal quality.

[0103] Optionally, the third mounting area 103 and the second mounting area 102 satisfy at least one of the following conditions:

[0104] The third mounting area 103 is located on the second side of the second mounting area 102, and the second side is the side of the second mounting area 102 closest to the fifth type of signal pin 1023;

[0105] The distance between the third mounting area 103 and the second mounting area 102 is less than or equal to a second threshold value.

[0106] In some optional embodiments, the fifth type of signal pin 1023 can be arranged close to the third type of signal pin or close to the fourth type of signal pin, which is conducive to further shortening the signal line.

[0107] The second threshold value can be reasonably set according to actual needs, for example, the second threshold value is 1mm or 1.5mm, etc.

[0108] In some optional embodiments, the edge of the third mounting area 103 and the edge of the second mounting area 102 are parallel, for example, the vertical edge of the third mounting area 103 and the vertical edge of the second mounting area 102 are parallel, or the horizontal edge of the third mounting area 103 and the horizontal edge of the second mounting area 102 are parallel.

[0109] It can be understood that the relative positions of the third mounting area and the second mounting area can be determined according to the distribution positions of the various types of signal pins of the third mounting area 103 and the distribution positions of the corresponding various types of signal pins in the second mounting area 102.

[0110] In some optional embodiments, the lower edge of the third mounting area 103 in the horizontal direction can be aligned with the lower edge of the second mounting area 102 in the horizontal direction, or the upper edge of the third mounting area 103 in the horizontal direction can be aligned with the upper edge of the second mounting area 102 in the horizontal direction, or the center point of the third mounting area 103 can be located on the same horizontal line as the center point of the second mounting area 102.

[0111] For example, as shown in FIG. 7, when the fifth type of signal pin 1023 is located on the right side of the second mounting area 102, the third mounting area 103 is arranged on the right side of the second mounting area 102, i.e., at position 1, the third mounting area 103 is parallel to the edge of the second mounting area 102, and the center point of the third mounting area 103 is located on the same horizontal line as the center point of the second mounting area 102. This layout is beneficial for shortening the signal lines between the third mounting area 103 and the second mounting area 102, and thus is beneficial for ensuring the signal quality. It should be noted that for positions 1 to 4 on the same plane, the farther from position 1, the worse the signal quality. For example, the signal quality at different positions can be ranked as follows: position 1 is better than position 2, position 2 is better than position 3, and position 3 is better than position 4.

[0112] Optionally, the second memory is a flash memory, and the third memory is a memory.

[0113] In this embodiment, the separate memory is mounted on the second mounting area by the adapter plate, i.e., the separate memory is arranged close to the SoC, and the separate flash memory is mounted on the third mounting area, for example, as shown in FIG. 5a or FIG. 5b. This layout is beneficial for reducing the signal line length of the memory. Since the signal line length of the memory is usually shorter than that of the flash memory, this layout is beneficial for ensuring the signal quality of both the memory and the flash memory.

[0114] It should be further noted that the different line types shown in FIGS. 5a, 5b, 6a and 6b of the present embodiment only distinguish different types of devices, different types of signal lines, different types of signal pins ball, etc., and do not constitute a limitation of the printed circuit board provided by the present embodiment. In addition, the small round balls shown in the above FIGS. 5a, 5b, 6a and 6b schematically represent the solder balls corresponding to the signal pins.

[0115] The embodiment of the present application further provides a conversion board, and FIG. 8 is a side view of a conversion board provided by the embodiment of the present application. It should be noted that the conversion board shown in FIG. 8 is only an example of the conversion board provided by the embodiment of the present application, and does not constitute a limitation on the conversion board provided by the embodiment of the present application. In addition, each short vertical line in FIG. 8 represents a signal pin on the conversion board. The conversion board provided by the embodiment of the present application can further include other signal pins, for example, a signal pin connected to ground, a signal pin connected to a power supply, etc., which are not limited by the embodiment.

[0116] Referring to FIG. 8, the first surface 201 of the conversion board 20 provided by the embodiment of the present application is provided with a seventh type of signal pin 2011, an eighth type of signal pin 2012 and a ninth type of signal pin 2013. The first surface 201 of the conversion board 20 is used to be connected with a printed circuit board. The second surface 202 of the conversion board 20 is provided with a fourth mounting area 2021 used to mount a third memory. The fourth mounting area 2021 is provided with a tenth type of signal pin 2022.

[0117] The seventh type of signal pin 2011 is electrically connected with the tenth type of signal pin 2022 through a fourth type of signal line 203 in the conversion board 20. The eighth type of signal pin 2012 and the ninth type of signal pin 2013 are electrically connected through a fifth type of signal line 204 in the conversion board.

[0118] The first surface 201 of the conversion board is a surface used to mount the conversion board to the printed circuit board. The second surface 202 of the conversion board is opposite to the first surface 201 of the conversion board. One of the fourth type of signal line 203 and the fifth type of signal line 204 is used to transmit a memory signal, and the other is used to transmit a flash memory signal. The third memory is a flash memory or a memory.

[0119] The printed circuit board, the first memory, the second memory and the third memory involved in the embodiment can refer to the related description of the foregoing printed circuit board embodiment, which is not described herein.

[0120] Specifically, the seventh type of signal pin 2011 is used to be electrically connected with a third type of signal pin of a printed circuit board. The eighth type of signal pin 2012 is used to be electrically connected with a fourth type of signal pin of the printed circuit board. The ninth type of signal pin 2013 is used to be electrically connected with a fifth type of signal pin of the printed circuit board.

[0121] In the above-mentioned seventh type of signal pin 2011 is used to be electrically connected with the third type of signal pin of the printed circuit board, the above-mentioned eighth type of signal pin 2012 is used to be electrically connected with the fourth type of signal pin of the printed circuit board, and the above-mentioned ninth type of signal pin 2013 is used to be electrically connected with the fifth type of signal pin of the printed circuit board. For example, in the case of mounting the above-mentioned adapter plate on the printed circuit board, the above-mentioned seventh type of signal pin 2011 is welded with the third type of signal pin of the printed circuit board, the above-mentioned eighth type of signal pin 2012 is welded with the fourth type of signal pin of the printed circuit board, and the above-mentioned ninth type of signal pin 2013 is welded with the fifth type of signal pin of the printed circuit board.

[0122] It should be noted that in the case of welding the above-mentioned seventh type of signal pin 2011 with the third type of signal pin of the printed circuit board, the above-mentioned seventh type of signal pin 2011 and the third type of signal pin of the printed circuit board can be shown as the black ball in FIG. 5b; in the case of welding the above-mentioned eighth type of signal pin 2012 with the fourth type of signal pin of the printed circuit board, the above-mentioned eighth type of signal pin 2012 and the fourth type of signal pin of the printed circuit board can be shown as the green ball in FIG. 5b; and in the case of welding the above-mentioned ninth type of signal pin 2013 with the fifth type of signal pin of the printed circuit board, the above-mentioned ninth type of signal pin 2013 and the fifth type of signal pin of the printed circuit board can be shown as the blue ball in FIG. 5b.

[0123] The material, number of layers, number of stages, dielectric constant, etc. of the adapter plate can be reasonably set according to the needs. For example, the material of the adapter plate can be FR-4 material, and the material of the adapter plate can be a medium glass transition temperature (i.e. Tg) material or a high Tg material, etc. The number of layers of the adapter plate can be greater than or equal to 6 layers, the number of stages of the adapter plate can be greater than or equal to 2 stages, or can be any stage, etc. It should be noted that in the case of the adapter plate being 6 layers and any stage, the design difficulty is lower, the PCB area is smaller, and the cost is optimal in a comprehensive manner.

[0124] The size of the adapter plate can also be reasonably set according to the needs. For example, the size of the adapter plate can be the same as the size of the third memory, or each side can be larger than a predetermined length, for example, 0.2mm, which is beneficial for fixing glue and cutting the adapter plate during production. The first surface of the adapter plate can be pre-tinned, which is beneficial for welding and fixing glue. Alternatively, a steel mesh brush tinning furnace can be used to achieve a pre-set tinning height; or a tinning ball furnace can be used to achieve tinning.

[0125] In addition, the design of the signal lines in the adapter plate can be adjusted according to signal simulation, such as line width, line spacing, ground isolation, layer spacing, size and position of the hole, to meet the signal quality requirements at high speed of the flash memory signal. For example, the rate of UFS can reach 3GHz, 6GHz, 12GHz, etc., and the rate of eMMC can reach 200MHz.

[0126] It can be understood that the signal pins on the first surface of the adapter plate correspond to the signal pins on the second mounting area of the printed circuit board, and the signal pins on the second surface of the adapter plate correspond to the signal pins of the third memory.

[0127] Specifically, in the case of mounting the adapter plate on the second mounting area of the printed circuit board, the seventh type of signal pin 2011 is electrically connected to the third type of signal pin of the printed circuit board, the eighth type of signal pin 2012 is electrically connected to the fourth type of signal pin of the printed circuit board, and the ninth type of signal pin 2013 is electrically connected to the fifth type of signal pin of the printed circuit board. That is, in the case of mounting a separate memory through a printed circuit board, the adapter circuit board can realize communication between the SoC and the separate memory.

[0128] As can be seen from the above, based on the adapter plate provided in the embodiment, the wiring reserved on the printed circuit board for the separate memory does not affect the signals of the integrated memory, and the printed circuit board can be mounted with a separate memory.

[0129] Optionally, the ninth type of signal pin 2013 on the first surface of the adapter plate corresponds to the fifth type of signal pin of the printed circuit board.

[0130] Optionally, the arrangement of the target pins on the first surface of the adapter plate is the same as the arrangement of the pins on the first surface of the first memory, wherein the target pins are the same pins on the first surface of the adapter plate as the pins on the first surface of the memory, the first surface of the first memory is the surface for mounting the first memory to the printed circuit board, and the first memory is a memory integrated with flash memory and memory.

[0131] It can be understood that since the second mounting area of the printed circuit board can be compatible with the mounting of the first memory and the adapter plate, the first surface of the adapter plate can include pins that are the same as the pins on the fifth surface of the first memory. In addition, the first surface of the adapter plate also includes newly added pins, i.e., the ninth type of signal pin 2013, which corresponds to the fifth type of signal pin of the printed circuit board. It should be noted that the pin arrangement of the second mounting area of the printed circuit board can be in a mirror image relationship with the pin arrangement of the first surface of the adapter plate.

[0132] Exemplarily, taking the first memory as the 254ball eMCP for example, a schematic diagram of the pin distribution of the first memory can be as shown in FIG. 9a, a schematic diagram of the pin distribution of the first surface of the adapter board can be as shown in FIG. 9b, and a schematic diagram of the pin distribution of the second mounting area of the printed circuit board can be as shown in FIG. 9c. It can be known that the pin distribution of the first surface of the adapter board newly adds the ninth type of signal pin 2013 compared with the pin distribution of the first memory, and the pin distribution of the first surface of the adapter board is a mirror image of the pin distribution of the second mounting area of the printed circuit board.

[0133] The embodiment sets the arrangement of the target pin of the first surface of the adapter board to be the same as the arrangement of the pin of the first surface of the first memory, and the ninth type of signal pin 2013 of the first surface of the adapter board is correspondingly arranged with the fifth type of signal pin of the printed circuit board, so as to facilitate mounting the adapter board and the first memory at the same position of the printed circuit board.

[0134] The design of the printed circuit board and the adapter board of the embodiment of the application is described below by way of example:

[0135] For the routing of the flash memory signal in the printed circuit board and the adapter board, taking the flash memory as the UFS for example, according to the signal quality requirement of the UFS 4.0 device with the current highest rate of 12GHz, the total length of the signal line is ensured to be as small as possible, for example, the maximum difference between the differential pairs is 0.1mm, and the maximum difference between the differential pairs is 3mm. The impedance design is differential 80Ω-100Ω, and single-ended 40Ω-50Ω. The shorter the total length of the signal line is, the smaller the insertion loss is, and the better it is, at least meeting the requirement of the UFS standard protocol. The interval between the UFS signal line and other signal lines is greater than or equal to a target value, wherein the target value can be the minimum value of 2 times the signal line width and 3 times the PCB layer height, and the other signal lines can include a transmission signal line (TX) and a reception signal line (RX). The UFS signal line is preferentially wrapped with ground to meet the requirements of the SoC manufacturer and the storage manufacturer. When the PCB design routing is punched, the surrounding should have a companion ground hole reaching the same layer. Through the above design, the insertion loss, return loss, crosstalk, impedance and the like can meet the requirements of the SoC and the memory device, and finally ensure that the signal eye diagram quality meets the standard.

[0136] The data signal of the UFS device is a differential serial signal, and a general device has 2 lanes, each lane has 4 signal lines (TX and RX each has two), and the UFS signal quality requires different requirements with different signal rates; the data signal of the eMMC is a single-ended parallel signal, and a general device has 8, the signal rate is lower than the UFS, the highest is 200MHz, and the corresponding signal quality requirement is different from the UFS; the signal types of the separated LPDDR device are more, and the signal quantity is also more, which has differential serial signal and single-ended parallel signal, the highest rate of LPDDR4X is 2133MHz, the highest rate of LPDDR5X is 4266MHz or more, and the corresponding signal quality requirement is also different.

[0137] For the memory signal traces in the above-mentioned printed circuit board and adapter board, taking the memory as LPDDR as an example, according to the different types of LPDDR, the design requirements are different, the basic principle is to ensure that the total length of the signal line is as small as possible, the impedance design is differential 80Ω-100Ω, single-ended 40Ω-50Ω, and the total length of the signal line is shorter, the insertion loss is smaller, and the better; the signal lines of the same type are kept at a distance of more than 1 times the line width, and the different types of signal lines are wrapped with the ground, and the distance between the ground is more than 1 times the line spacing, so that the crosstalk meets the requirements of the SoC manufacturer and the storage manufacturer; When the PCB design traces are punched, the surrounding should have a companion ground hole reaching the same layer; through the above design, the insertion loss, return loss, crosstalk, impedance and other requirements of the SOC and the memory device can be met, and finally the signal eye diagram quality can be ensured to meet the standard.

[0138] As can be seen from the above, in the design of the printed circuit board and the adapter board, the high signal quality requirement of the multi-path, rate at least 12GHz high-speed signal can be realized through the selection of the board material, the design of the laminated layer, the design of the signal line, the design of the via, etc. The area occupied by the above-mentioned printed circuit board is small.

[0139] The electronic device provided in the embodiments of the present application is shown in FIG. 10. Referring to FIG. 10, the electronic device 1 includes the printed circuit board 10, the system-on-chip 30 and the first memory 40 provided in any of the above embodiments;

[0140] The system-on-chip 30 is mounted on the first mounting area 101 of the printed circuit board 10, the eleventh type of signal pin 3011 of the system-on-chip 30 is electrically connected with the first type of signal pin 1011 of the first mounting area 101, and the twelfth type of signal pin 3012 of the system-on-chip 30 is electrically connected with the second type of signal pin 1012 of the first mounting area 101.

[0141] The first memory 40 is mounted on the second mounting area 102 of the printed circuit board 10, the thirteenth signal pin 4011 of the first memory 40 is electrically connected with the third signal pin 1021 of the second mounting area 102, and the fourteenth signal pin 4012 of the first memory 40 is electrically connected with the fourth signal pin 1022 of the second mounting area 102.

[0142] In particular, the printed circuit board 10 is provided with a first mounting area 101, a second mounting area 102 and a third mounting area 103, the system-level chip 30 is mounted on the first mounting area 101 of the printed circuit board 10, the eleventh signal pin 3011 of the system-level chip 30 is electrically connected with the first signal pin 1011 of the first mounting area 101, the first signal pin 1011 of the first mounting area 101 is electrically connected with the third signal pin 1021 of the second mounting area 102 through the first signal line 104 in the printed circuit board 10; the twelfth signal pin of the system-level chip 30 is electrically connected with the second signal pin 1012 of the first mounting area 101, and the second signal pin 1012 of the first mounting area 101 is electrically connected with the fourth signal pin 1022 of the second mounting area 102 through the second signal line 105 in the printed circuit board 10. The first memory 40 is mounted on the second mounting area 102 of the printed circuit board 10, the thirteenth signal pin 4011 of the first memory 40 is electrically connected with the third signal pin 1021 of the second mounting area 102, and the fourteenth signal pin 4012 of the first memory 40 is electrically connected with the fourth signal pin 1022 of the second mounting area 102. The third mounting area 103 is used for mounting the second memory, and the sixth signal pin 1031 of the third mounting area 103 is electrically connected with the fifth signal pin 1023 of the second mounting area 102 through the third signal line 106 in the printed circuit board 10. It can be understood that in the embodiment, the second memory is not mounted on the third mounting area 103.

[0143] The eleventh signal pin is used for inputting or outputting memory signals. The twelfth signal pin is used for inputting or outputting flash memory signals. The eleventh signal pin of the system-level chip 30 is electrically connected with the first signal pin of the first mounting area, and the twelfth signal pin of the system-level chip 30 is electrically connected with the second signal pin of the first mounting area, for example, the eleventh signal pin of the system-level chip 30 is welded with the first signal pin of the first mounting area, and the twelfth signal pin of the system-level chip 30 is welded with the second signal pin of the first mounting area.

[0144] The thirteenth type signal pin of the first memory is electrically connected with the third type signal pin of the second mounting area, and the fourteenth type signal pin of the first memory is electrically connected with the fourth type signal pin of the second mounting area. For example, the thirteenth type signal pin of the first memory is welded with the third type signal pin of the second mounting area, and the fourteenth type signal pin of the first memory is welded with the fourth type signal pin of the second mounting area.

[0145] It should be noted that in the case of installing the first memory on the second mounting area of the printed circuit board 10, the fifth type signal pin on the printed circuit board 10 is in a suspended state, so that the signal wiring reserved for the second memory will not affect the signal of the first memory.

[0146] It should be further noted that the details of the printed circuit board and the first memory of the embodiment can refer to the related descriptions of the foregoing embodiments, which will not be repeated here.

[0147] The embodiment of the application further provides an electronic device, and FIG. 11 is a schematic diagram of an electronic device according to an embodiment of the application. Referring to FIG. 11, the electronic device 2 includes the printed circuit board 10 according to any of the foregoing embodiments, the adapter board 20 according to any of the foregoing embodiments, a system-level chip 30, a second memory 50, and a third memory 60.

[0148] The system-level chip 30 is mounted on the first mounting area 101 of the printed circuit board 10, the eleventh type signal pin 3011 of the system-level chip 30 is electrically connected with the first type signal pin 1011 of the first mounting area 101, and the twelfth type signal pin 3012 of the system-level chip 30 is electrically connected with the second type signal pin 1012 of the first mounting area 101.

[0149] The adapter board 20 is mounted on the second mounting area 102 of the printed circuit board 10, the seventh type signal pin 2011 of the adapter board 20 is electrically connected with the third type signal pin 1021 of the second mounting area 102, the eighth type signal pin 2012 of the adapter board 20 is electrically connected with the fourth type signal pin 1022 of the second mounting area 102, and the ninth type signal pin 2013 of the adapter board 20 is electrically connected with the fifth type signal pin 1023 of the second mounting area 102.

[0150] The second memory 50 is mounted on the third mounting area 103 of the printed circuit board 10, and the fifteenth type signal pin 5011 of the second memory 50 is electrically connected with the sixth type signal pin 1031 of the third mounting area 103.

[0151] The third memory 60 is installed on the fourth installation area of the adapter board 20, and a sixteenth signal pin 6011 of the third memory 60 is electrically connected with a tenth signal pin 2022 of the fourth installation area.

[0152] Specifically, the printed circuit board 10 is provided with a first installation area 101, a second installation area 102 and a third installation area 103, the system-level chip 30 is installed on the first installation area 101 of the printed circuit board 10, and an eleventh signal pin of the system-level chip 30 is electrically connected with a first signal pin of the first installation area 101, the first signal pin 1011 of the first installation area 101 is electrically connected with a third signal pin 1021 of the second installation area 102 through a first signal line 104 in the printed circuit board 10; a twelfth signal pin of the system-level chip 30 is electrically connected with a second signal pin of the first installation area 101, and the second signal pin 1012 of the first installation area 101 is electrically connected with a fourth signal pin 1022 of the second installation area 102 through a second signal line 105 in the printed circuit board 10.

[0153] The adapter board 20 is installed on the second installation area 102 of the printed circuit board 10, a seventh signal pin of the adapter board 20 is electrically connected with a third signal pin of the second installation area 102, an eighth signal pin of the adapter board 20 is electrically connected with a fourth signal pin of the second installation area 102, and a ninth signal pin of the adapter board 20 is electrically connected with a fifth signal pin of the second installation area 102. The third memory 60 is installed on the fourth installation area 2021 of the adapter board 20, a sixteenth signal pin of the third memory 60 is electrically connected with a tenth signal pin of the fourth installation area 2021, and the tenth signal pin of the third memory 60 is electrically connected with a seventh signal pin of the adapter board 20 through a fourth signal line 203 in the adapter board 20.

[0154] The second memory 50 is installed on the third installation area 103 of the printed circuit board 10, the fifteenth type signal pin of the second memory 50 is electrically connected with the sixth type signal pin 1031 of the third installation area 103, and the sixth type signal pin 1031 of the third installation area 103 is electrically connected with the fifth type signal pin 1023 of the second installation area 102 through the third type signal line 106 in the printed circuit board. The seventh type signal pin of the adapter plate is electrically connected with the third type signal pin of the second installation area, the eighth type signal pin of the adapter plate is electrically connected with the fourth type signal pin of the second installation area, and the ninth type signal pin of the adapter plate is electrically connected with the fifth type signal pin of the second installation area, for example, the seventh type signal pin of the adapter plate is welded with the third type signal pin of the second installation area, the eighth type signal pin of the adapter plate is welded with the fourth type signal pin of the second installation area, and the ninth type signal pin of the adapter plate is welded with the fifth type signal pin of the second installation area.

[0155] The fifteenth type signal pin of the second memory is electrically connected with the sixth type signal pin of the third installation area, for example, the fifteenth type signal pin of the second memory is welded with the sixth type signal pin of the third installation area.

[0156] The sixteenth type signal pin of the third memory is electrically connected with the tenth type signal pin of the fourth installation area, for example, the sixteenth type signal pin of the third memory is welded with the tenth type signal pin of the fourth installation area.

[0157] It should be noted that the printed circuit board, the adapter plate, the system level chip, the second memory and the third memory of the embodiment can refer to the related description of the foregoing embodiments, which will not be repeated here.

[0158] It should be noted that the electronic device can be a mobile phone, a tablet computer, a notebook computer, a palm computer, a vehicle-mounted electronic device, a Mobile Internet Device (MID), an augmented reality (AR) / virtual reality (VR) device, a robot, a wearable device, an ultra-mobile personal computer (UMPC), a netbook, or a personal digital assistant (PDA), and the like, and can also be a server, a Network Attached Storage (NAS), a personal computer (PC), a television (TV), a cashier machine, or a self-service machine, and the like, and embodiments of the present application are not limited specifically.

[0159] It should be noted that in this document, the terms "comprise", "contain" or any other variant thereof are intended to cover non-exclusive inclusions, so that a process, method, article or device that includes a series of elements not only includes those elements, but also includes other elements not explicitly listed, or further includes elements inherent to such a process, method, article or device. Without more limitations, the element defined by the statement "comprises a" does not exclude the presence of other identical elements in the process, method, article or device that includes the element.

[0160] The embodiments of the present application are described above in combination with the drawings, but the present application is not limited to the specific embodiments described above, and the specific embodiments described above are merely illustrative rather than limiting, and a person of ordinary skill in the art can make many forms under the inspiration of the present application without departing from the scope of the present application and the scope protected by the claims.

Claims

1. A printed circuit board, the printed circuit board being provided with a first mounting area, a second mounting area and a third mounting area, the first mounting area being configured to mount a system on chip, the second mounting area being configured to mount a first memory or a riser, and the third mounting area being configured to mount a second memory; the first mounting area being provided with a first type of signal pin and a second type of signal pin, the second mounting area being provided with a third type of signal pin, a fourth type of signal pin and a fifth type of signal pin, and the third mounting area being provided with a sixth type of signal pin; the first type of signal pin being electrically connected to the third type of signal pin through a first type of signal line in the printed circuit board, the second type of signal pin being electrically connected to the fourth type of signal pin through a second type of signal line in the printed circuit board, and the fifth type of signal pin being electrically connected to the sixth type of signal pin through a third type of signal line in the printed circuit board; the first memory being a memory integrated with a flash memory and a memory, the second memory being a flash memory or a memory, the first type of signal line being configured to transmit a memory signal, the second type of signal line being configured to transmit a flash memory signal, the third type of signal line being configured to transmit a memory signal in the case that the second memory is a memory, and the third type of signal line being configured to transmit a flash memory signal in the case that the second memory is a flash memory.

2. The printed circuit board of claim 1, wherein, in the case that the second memory is a memory, a protocol type of the memory integrated in the first memory is the same as a protocol type of the second memory; or in the case that the second memory is a flash memory, a protocol type of the flash memory integrated in the first memory is the same as a protocol type of the second memory. the first mounting area, the second mounting area and the third mounting area are all provided on a same surface of the printed circuit board; or 3. The printed circuit board according to claim 1 or 2, wherein, the first mounting area and the second mounting area are both provided on a first surface of the printed circuit board, and the third mounting area is provided on a second surface of the printed circuit board, the first surface and the second surface being two opposite surfaces. at least one of the following conditions is met between the first mounting area and the second mounting area: the second mounting area is located on a first side of the first mounting area, the first side being a side of the first mounting area closest to the first type of signal pin or the second type of signal pin; and 4. The printed circuit board of claim 3, wherein, a distance between the first mounting area and the second mounting area is less than or equal to a first threshold value. at least one of the following conditions is met between the third mounting area and the second mounting area: the third mounting area is located on a second side of the second mounting area, the second side being a side of the second mounting area closest to the fifth type of signal pin; and 5. The printed circuit board of claim 3, wherein, a distance between the third mounting area and the second mounting area is less than or equal to a second threshold value. the second memory is a flash memory. ​ 6. The printed circuit board of claim 1, wherein, ​ 7. An adapter board, a first surface of the adapter board is provided with a seventh type signal pin, an eighth type signal pin and a ninth type signal pin, the first surface of the adapter board is used to connect with a printed circuit board, a second surface of the adapter board is provided with a fourth mounting area, the fourth mounting area is used to mount a third memory, the fourth mounting area is provided with a tenth type signal pin; the seventh type signal pin and the tenth type signal pin are electrically connected through a fourth type signal line in the adapter board, the eighth type signal pin and the ninth type signal pin are electrically connected through a fifth type signal line in the adapter board; the first surface of the adapter board is a surface used to mount the adapter board to the printed circuit board, the second surface of the adapter board is opposite to the first surface of the adapter board, one of the fourth type signal line and the fifth type signal line is used to transmit a memory signal, and the other is used to transmit a flash memory signal, the third memory is a flash memory or a memory.

8. The adapter plate of claim 7, wherein, The ninth type signal pin of the first surface of the adapter board is correspondingly provided with a fifth type signal pin of the printed circuit board.

9. An electronic device comprising the printed circuit board, the system level chip and the first memory of any one of claims 1 to 6; wherein, the system level chip is mounted on the first mounting area of the printed circuit board, an eleventh type signal pin of the system level chip is electrically connected with a first type signal pin of the first mounting area, a twelfth type signal pin of the system level chip is electrically connected with a second type signal pin of the first mounting area; the first memory is mounted on the second mounting area of the printed circuit board, a thirteenth type signal pin of the first memory is electrically connected with a third type signal pin of the second mounting area, a fourteenth type signal pin of the first memory is electrically connected with a fourth type signal pin of the second mounting area.

10. An electronic device comprising the printed circuit board of any one of claims 1 to 6, the adapter board of any one of claims 7 to 8, a system level chip, a second memory and a third memory; wherein, the system level chip is mounted on the first mounting area of the printed circuit board, an eleventh type signal pin of the system level chip is electrically connected with a first type signal pin of the first mounting area, a twelfth type signal pin of the system level chip is electrically connected with a second type signal pin of the first mounting area; the adapter board is mounted on the second mounting area of the printed circuit board, a seventh type signal pin of the adapter board is electrically connected with a third type signal pin of the second mounting area, an eighth type signal pin of the adapter board is electrically connected with a fourth type signal pin of the second mounting area, a ninth type signal pin of the adapter board is electrically connected with a fifth type signal pin of the second mounting area; the second memory is mounted on the third mounting area of the printed circuit board, a fifteenth type signal pin of the second memory is electrically connected with a sixth type signal pin of the third mounting area; The third memory is installed on a fourth installation area of the adapter plate, and a sixteenth signal pin of the third memory is electrically connected with a tenth signal pin of the fourth installation area.

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