Semiconductor device

Abstract

Provided is a novel semiconductor device. This invention involves a first transistor, a second transistor, and a light receiving element. One terminal of the light receiving element is connected to a first terminal of the first transistor, a second terminal of the first transistor is connected to a gate of the second transistor, the first transistor includes a first oxide semiconductor in a channel formation region, the second transistor includes a second oxide semiconductor in a channel formation region, the first oxide semiconductor is indium gallium zinc oxide, and the second oxide semiconductor is indium oxide.

Description

Semiconductor Devices

[0001] One embodiment of the present invention relates to a semiconductor device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. The technical field of one embodiment of the invention disclosed in this specification and the like relates to an object, a method, a driving method, or a manufacturing method. Alternatively, one embodiment of the present invention relates to a process, a machine, manufacture, or a composition of matter. More specifically, examples of the technical field of one embodiment of the present invention disclosed in this specification and the like include semiconductor devices, display devices, light-emitting devices, power storage devices, optical devices, imaging devices, lighting devices, projection devices, electro-optical devices, light-receiving devices, detection devices, power supply devices, communication devices, information processing devices, arithmetic units, control devices, memory devices, input devices, output devices, input / output devices, signal processing devices, arithmetic processing devices, electronic computers, electronic devices, systems including these devices, and driving methods or manufacturing methods thereof.

[0003] A technique for forming a transistor using an oxide semiconductor thin film formed over a substrate has attracted attention. For example, Patent Document 1 discloses an imaging device having a pixel circuit including a transistor that includes an oxide semiconductor and has extremely low off-state current.

[0004] JP 2011-119711 A

[0005] Takashi Koida, "High Mobility Transparent Conductive Film," National Institute of Advanced Industrial Science and Technology, AIST Photovoltaic Power Generation Research Results Report 2019, Internet <URL: https: / / unit.aist.go.jp / rpd-envene / PV / ja / results / 2019 / oral / T13.pdf>

[0006] An object of one embodiment of the present invention is to provide a high-performance imaging device. Another object of one embodiment of the present invention is to provide an imaging device that can acquire a high-resolution image. Another object of one embodiment of the present invention is to provide an imaging device having high-density pixels. Another object of one embodiment of the present invention is to provide a small-sized imaging device. Another object of one embodiment of the present invention is to provide an imaging device or the like that can operate at high speed. Another object of one embodiment of the present invention is to provide an imaging device with high reliability. Another object of one embodiment of the present invention is to provide a novel imaging device or the like. Another object of one embodiment of the present invention is to provide a semiconductor device that can be applied to the imaging device. Another object of one embodiment of the present invention is to provide a novel semiconductor device or the like. Another object of one embodiment of the present invention is to provide a method for driving the imaging device or the semiconductor device.

[0007] The above-mentioned problem does not preclude the existence of other problems. A person skilled in the art can naturally derive other problems from the description in this specification, drawings, claims, etc., and can extract other problems from the description in this specification, drawings, claims, etc. Note that one embodiment of the present invention does not necessarily solve all of these problems (the above-mentioned problem and other problems).

[0008] (1) One embodiment of the present invention is a semiconductor device including a first transistor, a second transistor, and a light-receiving element, in which one terminal of the light-receiving element is electrically connected to a first terminal of the first transistor and a second terminal of the first transistor is electrically connected to a gate of the second transistor, the first transistor includes a first oxide semiconductor in a channel formation region, and the second transistor includes a second oxide semiconductor in a channel formation region.

[0009] (2) One embodiment of the present invention is a semiconductor device including a first transistor, a second transistor, and a light-receiving element, in which one terminal of the light-receiving element is electrically connected to a first terminal of the first transistor and a second terminal of the first transistor is electrically connected to a gate of the second transistor, the first transistor includes a first oxide semiconductor in a channel formation region, the second transistor includes a second oxide semiconductor in a channel formation region, each of the first oxide semiconductor and the second oxide semiconductor contains indium, and the indium content in the second oxide semiconductor is higher than the indium content in the first oxide semiconductor.

[0010] (3) One embodiment of the present invention is a semiconductor device including a first transistor, a second transistor, and a light-receiving element. One terminal of the light-receiving element is electrically connected to a first terminal of the first transistor. A second terminal of the first transistor is electrically connected to a gate of the second transistor. The first transistor includes a first oxide semiconductor in a channel formation region. The second transistor includes a second oxide semiconductor in a channel formation region. The first oxide semiconductor is indium gallium zinc oxide. The second oxide semiconductor is indium oxide.

[0011] (4) In any one of (1) to (3), the light-receiving element may include a third transistor and a fourth transistor, wherein a first terminal of the third transistor is electrically connected to a second terminal of the first transistor and a gate of the second transistor, a first terminal of the fourth transistor is electrically connected to a second terminal of the second transistor, a second terminal of the light-receiving element is electrically connected to a first wiring, a first terminal of the second transistor is electrically connected to a second wiring, a second terminal of the third transistor is electrically connected to a second wiring, a gate of the first transistor is electrically connected to a third wiring, a gate of the third transistor is electrically connected to a fourth wiring, a gate of the fourth transistor is electrically connected to a fifth wiring, and a second terminal of the fourth transistor is electrically connected to a sixth wiring, and the third transistor may include a first oxide semiconductor in a channel formation region, and the fourth transistor may include a second oxide semiconductor in a channel formation region.

[0012] (5) In any one of (1) to (3) above, the light receiving element may be provided in a first layer, the first transistor may be provided in a second layer above the first layer, and the second transistor may be provided in a third layer above the second layer.

[0013] According to one embodiment of the present invention, a high-performance imaging device can be provided. According to one embodiment of the present invention, an imaging device capable of acquiring a high-resolution image can be provided. According to one embodiment of the present invention, an imaging device having high-density pixels can be provided. According to one embodiment of the present invention, a small-sized imaging device can be provided. According to one embodiment of the present invention, an imaging device capable of high-speed operation can be provided. According to one embodiment of the present invention, a highly reliable imaging device can be provided. According to one embodiment of the present invention, a novel imaging device can be provided. According to one embodiment of the present invention, a semiconductor device applicable to the imaging device can be provided. According to one embodiment of the present invention, a novel semiconductor device can be provided. According to one embodiment of the present invention, a method for driving the imaging device or a method for driving the semiconductor device can be provided.

[0014] Note that the above effects do not preclude the existence of other effects. A person skilled in the art can naturally derive other effects from the description in this specification, drawings, claims, etc., and can extract other effects from the description in this specification, drawings, claims, etc. Note that one embodiment of the present invention does not necessarily have all of these effects (the above effects and other effects).

[0015] FIGS. 1A and 1B are circuit diagrams illustrating an example of the configuration of a semiconductor device. FIGS. 2A and 2B are circuit diagrams illustrating an example of the configuration of a semiconductor device. FIG. 3A is a cross-sectional view illustrating an example of the configuration of a semiconductor device. FIG. 3B is a top view illustrating an example of the configuration of a semiconductor device. FIG. 4A is a top view illustrating an example of the configuration of a semiconductor device. FIGS. 4B, 4C, and 4D are cross-sectional views illustrating an example of the configuration of a semiconductor device. FIG. 5 is a cross-sectional view illustrating an example of the configuration of a semiconductor device. FIGS. 6A, 6B, and 6C are cross-sectional views illustrating an example of the configuration of a semiconductor device. FIG. 7 is a cross-sectional view illustrating an example of the configuration of a semiconductor device. FIG. 8 is a cross-sectional view illustrating an example of the configuration of a semiconductor device. FIG. 9 is a cross-sectional view illustrating an example of the configuration of a semiconductor device. FIG. 10 is a cross-sectional view illustrating an example of the configuration of a semiconductor device. FIG. 11 is a cross-sectional view illustrating an example of the configuration of a semiconductor device. FIGS. 12A and 12B are cross-sectional views illustrating an example of the configuration of a semiconductor device. FIG. 13 is a cross-sectional view illustrating an example of the configuration of a semiconductor device. FIG. 14 is a cross-sectional view illustrating an example of the configuration of a semiconductor device. FIG. 15 is a cross-sectional view illustrating an example of the configuration of a semiconductor device. FIG. 16 is a cross-sectional view illustrating an example of the configuration of a semiconductor device. 17A and 17B are block diagrams illustrating an example configuration of an imaging device. FIG. 18 is a circuit diagram illustrating an example configuration of an imaging device. FIG. 19 is a timing chart illustrating an example operation of an imaging device. FIGS. 20A and 20B are diagrams illustrating carrier concentration dependence of Hall mobility. FIG. 20C is a cross-sectional view illustrating an indium oxide film. FIG. 21A is a diagram illustrating a package that houses an imaging device. FIG. 21B is a diagram illustrating a module that houses an imaging device. FIGS. 22A, 22B, 22C, 22D, 22E, and 22F are diagrams illustrating electronic devices. FIGS. 23A and 23B are diagrams illustrating a moving object. 24A1, 24A2, 24A3, 24A4, 24A5, 24A6, 24A7 and 24B1, 24B2, 24B3, 24B4, 24B5, and 24B6 are diagrams for explaining electrical connections.

[0016] In this specification, a semiconductor device refers to a device that utilizes semiconductor characteristics, such as a circuit including a semiconductor element (e.g., a transistor or a diode), or a device having such a circuit. It also refers to any device that can function by utilizing semiconductor characteristics. Examples of semiconductor devices include electronic circuits including semiconductor elements, chips equipped with electronic circuits, electronic components with chips housed in packages, and electronic devices equipped with electronic components. Furthermore, display devices, light-emitting devices, power storage devices, optical devices, imaging devices, lighting devices, projection devices, electro-optical devices, light-receiving devices, detection devices, power supply devices, communication devices, information processing devices, arithmetic units, control devices, memory devices, input devices, output devices, input / output devices, signal processing devices, arithmetic processing devices, electronic computers, and electronic devices may themselves be semiconductor devices and may also include semiconductor devices.

[0017] The following description of the embodiments will be given with reference to the drawings. However, the embodiments can be implemented in many different forms. Therefore, it will be readily understood by those skilled in the art that various changes can be made to the embodiments and their details without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the following description of the embodiments.

[0018] In this specification and the like, the configuration shown in each embodiment can be appropriately combined with the configuration shown in another embodiment to form one aspect of the present invention. Furthermore, when multiple configurations are shown in one embodiment, these configurations can be appropriately combined to form one aspect of the present invention.

[0019] In addition, in the drawings illustrating the embodiments, the same reference numerals may be used in common between different drawings for the same parts or parts having similar functions in the configuration of the invention, thereby omitting repeated description thereof. Furthermore, when the drawings indicate similar functions, for example, the same hatching patterns may be used and no particular reference numerals may be used. Furthermore, in the drawings, for example, in perspective views or top views (also called "plan views"), the illustration of some components may be omitted for ease of understanding. Furthermore, in the drawings, for example, the illustration of some hidden lines may be omitted. Furthermore, in the drawings, for example, the illustration of hatching patterns may be omitted.

[0020] In addition, in the drawings, the size, layer thickness, or region may be exaggerated for clarity. Therefore, the drawings are not limited to, for example, their size or aspect ratio. The drawings are schematic illustrations to facilitate understanding of the present invention and are not limited to, for example, the shapes or values ​​shown in the drawings. For example, in an actual manufacturing process, layers or resist masks may be unintentionally thinned by processes such as etching. However, these may not be reflected in the drawings to facilitate understanding. Furthermore, for example, in actual circuit operation, variations in voltage or current may occur due to noise or timing errors. However, these may not be reflected in the drawings to facilitate understanding.

[0021] Furthermore, in this specification and drawings, components may be classified by function and shown as independent elements. However, it may be difficult to separate components by function, and one element may be involved in multiple functions, or one function may be involved across multiple elements. Therefore, the elements shown in this specification and drawings may not be limited to the descriptions therein, and may be rephrased appropriately.

[0022] Furthermore, in this specification and drawings, when the same reference numeral is used for multiple elements, and particularly when it is necessary to distinguish between them, the reference numeral may be accompanied by an identifying symbol such as "A", "b", "_1", "[n]", or "[m, n]". Furthermore, when explaining matters common to multiple elements accompanied by identifying symbols, or when it is not necessary to distinguish between them, the elements may be described without the identifying symbol.

[0023] In this specification and the like, the "conductive state" or "on state" of a transistor refers to, for example, a state in which the source and drain of the transistor are considered to be electrically short-circuited, or a state in which a current can flow between the source and drain (also referred to as a state in which a current can flow). For example, a state in which the voltage between the gate and source of an n-channel transistor is higher than the threshold voltage, or a state in which the voltage between the gate and source of a p-channel transistor is lower than the threshold voltage, may be referred to as the "conductive state" or "on state." In addition, the "non-conductive state," "cutoff state," or "off state" of a transistor refers to a state in which the source and drain of the transistor are considered to be electrically cut off. For example, a state in which the voltage between the gate and source of an n-channel transistor is lower than the threshold voltage, or a state in which the voltage between the gate and source of a p-channel transistor is higher than the threshold voltage, may be referred to as the "non-conductive state," "cutoff state," or "off state."

[0024] In this specification and the like, the voltage between the gate and the source (gate-source) (based on the source potential unless otherwise specified) may be referred to as the "gate voltage," the voltage between the drain and the source (drain-source) (based on the source potential unless otherwise specified) may be referred to as the "drain voltage," and the voltage between the backgate and the source (backgate-source) (based on the source potential unless otherwise specified) may be referred to as the "backgate voltage." Furthermore, the current flowing between the drain and the source (positive in the direction from the drain to the source unless otherwise specified) may be referred to as the "drain current." Note that, in an n-channel transistor, terms such as "high gate voltage," "high drain voltage," and "high backgate voltage" can be interchangeable with terms such as "low gate voltage," "low drain voltage," and "low backgate voltage" in a p-channel transistor, as appropriate. Furthermore, in an n-channel transistor, descriptions such as a low gate voltage, a low drain voltage, and a low back gate voltage can be interchanged with descriptions such as a high gate voltage, a high drain voltage, and a high back gate voltage in a p-channel transistor, as appropriate.

[0025] In this specification and the like, unless otherwise specified, the "off-state current" of a transistor refers to the drain current when the transistor is in an off state. Note that in this specification and the like, the off-state current and the current flowing between the gate and the source and drain (also referred to as gate leakage current) may be collectively referred to as leakage current.

[0026] In this specification and the like, one of the source or drain (also referred to as two input / output terminals) of a transistor may be referred to as a first terminal, and the other of the source or drain of the transistor may be referred to as a second terminal. That is, a transistor has at least a gate (also referred to as a gate terminal), a first terminal, and a second terminal. One terminal of a capacitor (also referred to as one of a pair of terminals) may be referred to as a first terminal, and the other terminal of the capacitor (also referred to as the other of the pair of terminals) may be referred to as a second terminal. One terminal of a display element may be referred to as a first terminal, and the other terminal of the display element may be referred to as a second terminal. One terminal of a liquid crystal element may be referred to as a first terminal, and the other terminal of the liquid crystal element may be referred to as a second terminal. One terminal of a light-emitting element may be referred to as a first terminal, and the other terminal of the light-emitting element may be referred to as a second terminal. One terminal of a light-receiving element may be referred to as a first terminal, and the other terminal of the light-receiving element may be referred to as a second terminal. In addition, one of the anode or cathode of the diode (also referred to as one of a pair of terminals) may be referred to as a first terminal, and the other of the anode or cathode of the diode (also referred to as the other of the pair of terminals) may be referred to as a second terminal.

[0027] Embodiment 1 A semiconductor device according to one embodiment of the present invention will be described with reference to the drawings. At least a part of the semiconductor device according to one embodiment of the present invention can be used for an image sensor, an imaging device including the image sensor, or the like.

[0028] <Structure Example 1 of Semiconductor Device> FIGS. 1A, 1B, 2A, and 2B are circuit diagrams illustrating a semiconductor device 100 of one embodiment of the present invention.

[0029] The semiconductor device 100 includes a pixel circuit 101 and a light-receiving element PD. The pixel circuit 101 includes at least a transistor M11 and a transistor M12. The semiconductor device 100 can also be referred to as a pixel. In other words, the semiconductor device 100 can be said to correspond to one pixel of an image sensor included in an imaging device.

[0030] The light receiving element PD has a function of passing a current according to the intensity of light irradiated onto the light receiving element PD. Examples of light receiving elements include photodiodes, phototransistors, photoconductive elements, and photomultiplier tubes. Examples of photodiodes include PN photodiodes, PIN photodiodes, and avalanche photodiodes. Examples of materials used for photodiodes include simple semiconductors (such as silicon and germanium) whose main component is a single element, compound semiconductors (such as indium gallium arsenide), oxide semiconductors, and organic semiconductors. The above-mentioned various photodiodes can be used as the light receiving element PD of the semiconductor device 100.

[0031] One terminal of the light receiving element PD is connected to one of the source or drain of the transistor M11. The other terminal of the light receiving element PD is connected to a wiring VL1. The other of the source or drain of the transistor M11 is connected to the gate of the transistor M12. The gate of the transistor M11 is connected to a wiring TX. The other of the source or drain of the transistor M12 is connected to a wiring VL2.

[0032] As shown in Figure 1A, one terminal of the light-receiving element PD can be the cathode of the photodiode, and the other terminal of the light-receiving element PD can be the anode of the photodiode. Alternatively, as shown in Figure 1B, one terminal of the light-receiving element PD can be the anode of the photodiode, and the other terminal of the light-receiving element PD can be the cathode of the photodiode. In the following description, unless otherwise specified, it is assumed that one terminal of the light-receiving element PD is the cathode of the photodiode, and the other terminal of the light-receiving element PD is the anode of the photodiode, as shown in Figure 1A.

[0033] One terminal of the light receiving element PD may be referred to as a node SN. The gate of the transistor M12 may be referred to as a node FD. Note that the terms "node" and "wiring" may be interchangeable.

[0034] The wiring TX functions as a signal line. For example, the wiring TX has a function of transmitting a signal output from a circuit (e.g., a driver circuit) provided outside the semiconductor device 100 to the semiconductor device 100. The wiring VL1 and the wiring VL2 each function as a power supply line. For example, the wiring VL1 and the wiring VL2 each have a function of transmitting a potential output from a circuit (e.g., a power supply circuit) provided outside the semiconductor device 100 to the semiconductor device 100. Note that at least one of the wiring VL1 and the wiring VL2 may function as a signal line.

[0035] The transistor M11 functions as a switching element that controls the transfer of charge between the node SN and the node FD. The transistor M12 functions as an amplifying element (also referred to as a voltage-current converting element) that causes a current to flow according to the potential of the node FD.

[0036] In the semiconductor device 100, by applying a reverse bias to the light-receiving element PD (i.e., by making the potential of the node SN higher than the potential of the wiring VL1), a current corresponding to the intensity of irradiated light flows from the node SN to the wiring VL1. Here, by turning on the transistor M11, charges are accumulated in the nodes SN and FD, and the potentials of the nodes SN and FD gradually decrease. After a predetermined time has elapsed, the transistor M11 is turned off, thereby holding the potential of the node FD. At this time, the potential held in the node FD becomes a potential corresponding to the intensity of light irradiated onto the light-receiving element PD. Therefore, a drain current corresponding to the intensity of light irradiated onto the light-receiving element PD can flow through the transistor M12.

[0037] The semiconductor device 100 may include a transistor (corresponding to a transistor M13 described later) that functions as a switch element that controls whether or not a predetermined potential is supplied to each of the node SN and the node FD. The semiconductor device 100 may also include a transistor (corresponding to a transistor M14 described later) that functions as a switch element that controls whether or not a drain current flowing through the transistor M12 is output from the semiconductor device 100. The semiconductor device 100 may also include a capacitive element (corresponding to a capacitive element C11 described later) that functions to stabilize the potential held at the node FD.

[0038] As shown in FIG. 2A, the semiconductor device 100 may further include a transistor M13 and a transistor M14.

[0039] The source or drain of transistor M13 is connected to the other of the source or drain of transistor M11 and to the gate of transistor M12 (corresponding to node FD). The other of the source or drain of transistor M13 is connected to wiring VL2. The gate of transistor M13 is connected to wiring RS. The source or drain of transistor M14 is connected to the other of the source or drain of transistor M12. The other of the source or drain of transistor M14 is connected to wiring WX. The gate of transistor M14 is connected to wiring SE.

[0040] The wiring RS and the wiring SE each function as a signal line. For example, the wiring RS and the wiring SE each function to transmit a signal output from a circuit (e.g., a driver circuit) provided outside the semiconductor device 100 to the semiconductor device 100. The wiring WX also functions as a signal line. For example, the wiring WX functions to transmit a signal output from the semiconductor device 100 (corresponding to the drain current flowing through the transistor M12) to a circuit (e.g., a readout circuit) provided outside the semiconductor device 100.

[0041] The transistor M13 functions as a switching element that controls whether a potential is supplied from the wiring VL2 to the node FD (also referred to as initializing the potential of the node FD). The transistor M14 functions as a switching element that controls whether a drain current flowing through the transistor M12 is output from the semiconductor device 100.

[0042] As shown in FIG. 2B, the semiconductor device 100 may further include a capacitive element C11.

[0043] One terminal of the capacitor C11 is connected to the other of the source and the drain of the transistor M11 and the gate (corresponding to the node FD) of the transistor M12, and the other terminal of the capacitor C11 is connected to the wiring VL2.

[0044] In the semiconductor device 100, there is a concern that the potential held at the node FD fluctuates due to the influence of parasitic capacitance added to the node FD, which may cause fluctuations in the drain current (corresponding to the signal output from the semiconductor device 100) flowing through the transistor M12. For example, when the semiconductor device 100 is used in an imaging device, fluctuations in the drain current flowing through the transistor M12 become noise in the readout signal, resulting in a decrease in the signal-to-noise ratio. Therefore, by providing the capacitive element C11, fluctuations in the potential held at the node FD can be suppressed, thereby suppressing fluctuations in the drain current flowing through the transistor M12. This can improve the signal-to-noise ratio.

[0045] Examples of the parasitic capacitance include the gate capacitance of the transistor M11 (here, including the parasitic capacitance between the wiring TX and the node FD), the gate capacitance of the transistor M13 (here, including the parasitic capacitance between the wiring RS and the node FD), and the gate capacitance of the transistor M12. Therefore, the capacitance value of the capacitor C11 is preferably larger than the gate capacitance value of the transistor M11. The capacitance value of the capacitor C11 is also preferably larger than the gate capacitance value of the transistor M13. The capacitance value of the capacitor C11 is also preferably larger than the gate capacitance value of the transistor M12.

[0046] 2A and 2B , one of the source and drain of the transistor M13 may be connected to one of the source and drain of the transistor M11 and one terminal (corresponding to the node SN) of the light receiving element PD.

[0047] For example, the other of the source and the drain of the transistor M13 may be connected to the wiring VL1 or to a wiring (not shown) different from the wiring VL2 and the wiring VL1, thereby allowing a potential different from the potential of the wiring VL2 to be supplied to the node FD.

[0048] Furthermore, for example, in the current path from the wiring VL2 through the transistor M12 to the wiring WX, the transistor M14 may be provided between the transistor M12 and the wiring VL2, rather than between the transistor M12 and the wiring WX. In this case, one of the source or drain of the transistor M12 is connected to one of the source or drain of the transistor M14. The other of the source or drain of the transistor M12 is connected to the wiring WX. The other of the source or drain of the transistor M14 is connected to the wiring VL2.

[0049] Also, for example, in the semiconductor device 100 shown in FIG. 2B, the other terminal of the capacitance element C11 may be connected to the wiring VL1, or may be connected to a wiring (not shown) different from either the wiring VL2 or the wiring VL1.

[0050] In one embodiment of the present invention, a transistor including a single crystal semiconductor, a polycrystalline semiconductor, a microcrystalline semiconductor, or an amorphous semiconductor in a channel formation region can be used as a transistor included in the semiconductor device 100. The semiconductor is not limited to a simple semiconductor whose main component is a single element (such as silicon or germanium), but can also be, for example, a compound semiconductor (such as silicon germanium or gallium arsenide), an oxide semiconductor, or the like.

[0051] Furthermore, various types of transistors can be used as the transistors that constitute the semiconductor device 100. For example, MOS field effect transistors, junction field effect transistors, bipolar transistors, or the like can be used.

[0052] Transistors of various structures can be used as transistors constituting the semiconductor device 100. For example, transistors of various structures can be used, such as top-gate transistors (e.g., planar transistors and staggered transistors), bottom-gate transistors (e.g., inverted planar transistors and inverted staggered transistors), dual-gate transistors (structures in which gates are arranged on both sides (e.g., above and below) of a channel formation region), FIN transistors, TRI-GATE transistors, and GAA transistors (gate-all-around transistors). Furthermore, for example, vertical transistors (transistors whose channel length direction is vertical (also referred to as the height direction or the direction perpendicular to the formation surface)) can be used.

[0053] In the semiconductor device 100, the transistor M12 preferably has a large transconductance because it functions as an amplifying element. Increasing the transconductance of the transistor M12 can, for example, increase the read speed of a signal output from the semiconductor device 100. In order to increase the transconductance of the transistor M12, for example, the gate capacitance of the transistor M12 may be reduced. That is, for example, the thickness of the gate insulating film of the transistor M12 may be reduced, or the dielectric constant of the gate insulating film of the transistor M12 may be increased.

[0054] Furthermore, since the transistor M12 functions as an amplifying element, it is preferable that the transistor M12 have high saturation. Increasing the saturation of the transistor M12 can stabilize the signal output from the semiconductor device 100. In order to increase the saturation of the transistor M12, for example, the channel length of the transistor M12 may be increased.

[0055] Furthermore, since the transistor M14 is provided in the current path when the drain current of the transistor M12 is output from the semiconductor device 100, it is preferable that the transistor M14 has a small on-resistance (also referred to as a large on-current). By reducing the on-resistance of the transistor M14, for example, it is possible to stabilize the signal output from the semiconductor device 100. To reduce the on-resistance of the transistor M14, for example, the channel length of the transistor M14 may be reduced. Also, for example, the gate capacitance of the transistor M14 may be reduced. That is, for example, the thickness of the gate insulating film of the transistor M14 may be reduced, or the dielectric constant of the gate insulating film of the transistor M12 may be increased.

[0056] Furthermore, it is preferable that each of the transistors M11 and M13 has a small gate capacitance to reduce the parasitic capacitance applied to the node FD. By reducing the gate capacitance of each of the transistors M11 and M13, for example, fluctuations in the potential held at the node FD can be suppressed, and the signal output from the semiconductor device 100 can be stabilized. To reduce the gate capacitance of each of the transistors M11 and M13, for example, the thickness of the gate insulating film of each of the transistors M11 and M13 may be increased, or the dielectric constant of the gate insulating film of each of the transistors M11 and M13 may be reduced. Furthermore, for example, the area of ​​the channel formation region (corresponding to channel length × channel width) of each of the transistors M11 and M13 may be reduced.

[0057] Based on these technical concepts, for example, the channel length of the transistor M12 may be made longer than the channel length of the transistor M11. Also, for example, the channel length of the transistor M12 may be made longer than the channel length of the transistor M13. Also, for example, the channel length of the transistor M12 may be made longer than the channel length of the transistor M14.

[0058] For example, the gate capacitance of each of the transistors M11 and M13 may be smaller than the gate capacitance of the transistor M12. For example, the thickness of the gate insulating film of each of the transistors M11 and M13 may be larger than the thickness of the gate insulating film of the transistor M12. For example, the dielectric constant of the gate insulating film of each of the transistors M11 and M13 may be smaller than the dielectric constant of the gate insulating film of the transistor M12. For example, the area of ​​the channel formation region of each of the transistors M11 and M13 may be smaller than the area of ​​the channel formation region of the transistor M12. For example, the channel length of each of the transistors M11 and M13 may be smaller than the channel length of the transistor M12. For example, the channel width of each of the transistors M11 and M13 may be smaller than the channel width of the transistor M12.

[0059] In the semiconductor device 100, the transistors M11 and M13 preferably have small off-state currents. Reducing the off-state currents of the transistors M11 and M13 can suppress charge flow into or out of the node FD. Thus, for example, when the semiconductor device 100 is used in an imaging device, fluctuations in the potential held in the node FD can be suppressed, thereby improving the signal-to-noise ratio. Furthermore, the potential of the node FD can be held for a long period of time, enabling a global shutter to be realized. To reduce the off-state currents of the transistors M11 and M13, for example, an OS transistor (a transistor including an oxide semiconductor in a channel formation region) may be used.

[0060] The OS transistor has a characteristic of extremely low off-state current because the band gap of the oxide semiconductor in which the channel is formed is 2 eV or more. The off-state current of an OS transistor per 1 μm of channel width in a room temperature environment is 1 aA (1×10 −１８ A) Below, 1zA (1×10 −２１A) or less, or 1 yA (1 x 10 −２４ In the case of a Si transistor (a transistor including silicon in a channel formation region), the off-state current per 1 μm of channel width in a room temperature environment can be 1 fA (1×10 −１５ A) or more and 1 pA (1 × 10 −１２ Therefore, it can be said that the off-state current of an OS transistor is smaller than that of a Si transistor by about 10 orders of magnitude.

[0061] Furthermore, the off-state current of an OS transistor hardly increases even in a high-temperature environment. Specifically, the off-state current hardly increases even in an environment of room temperature or higher and 200° C. or lower. Furthermore, the on-state current of an OS transistor is unlikely to decrease even in a high-temperature environment. Therefore, a semiconductor device including an OS transistor can operate stably and achieve high reliability even in a high-temperature environment.

[0062] Furthermore, an OS transistor has a high withstand voltage between the source and the drain (also referred to as drain withstand voltage). Therefore, a semiconductor device including an OS transistor can operate stably and with high reliability even when driven at high voltage.

[0063] In addition, the electrical characteristics of an OS transistor may change little due to radiation exposure. For example, the subthreshold slope of an OS transistor changes little due to radiation exposure. Furthermore, the field-effect mobility of an OS transistor changes little due to radiation exposure. Furthermore, an OS transistor can maintain an extremely small off-state current even after radiation exposure. Therefore, a semiconductor device including an OS transistor can operate stably and achieve high reliability even in an environment with strong radiation, such as outer space.

[0064] Furthermore, since OS transistors can be freely arranged on, for example, a silicon substrate on which Si transistors are provided, they can be easily integrated. Furthermore, since OS transistors can be manufactured using the same manufacturing equipment as Si transistors, OS transistors can be manufactured at low cost.

[0065] 1A to 2B , the semiconductor device 100 can have a structure in which, for example, a layer Lta including the transistors M11 and M13 is provided over a layer Lpd including the light-receiving element PD, and a layer Ltb including the transistors M12 and M14 is provided over the layer Lta.

[0066] As a result, by stacking the transistors M11 to M14 on the light receiving element PD, the light receiving area of ​​the light receiving element PD can be increased. This allows for improved sensitivity. Furthermore, by stacking the transistors M12 and M14 on the transistors M11 and M13, the size of one pixel can be reduced. This allows for an increase in resolution while keeping the image sensor size the same. Furthermore, for example, the size of the image sensor can be reduced while keeping the resolution the same.

[0067] Here, the transistors M11 and M13 provided in the layer Lta and the transistors M12 and M14 provided in the layer Ltb may have different characteristics.

[0068] As described above, it is preferable that the transistors M11 and M13 each have a small off-state current. Furthermore, it is preferable that the transistor M12 has a large transconductance, and it is preferable that the transistor M14 has a small on-state resistance. In other words, it is preferable that the transistors M12 and M14 each have a large on-state current. In other words, it can be said that it is preferable that the transistors M12 and M14 each have a high field-effect mobility.

[0069] As a result, for example, when the semiconductor device 100 is used in an imaging device, it is possible to achieve both an improvement in the signal-to-noise ratio and an improvement in the readout speed.

[0070] For example, the off-state current of each of the transistors M11 and M13 may be smaller than the off-state current of each of the transistors M12 and M14. Furthermore, for example, the on-state current of each of the transistors M12 and M14 may be larger than the on-state current of each of the transistors M11 and M13. That is, for example, the field-effect mobility of each of the transistors M12 and M14 may be higher than the field-effect mobility of each of the transistors M11 and M13.

[0071] Therefore, for example, an oxide semiconductor (also referred to as a first oxide semiconductor) including the channel formation regions of the transistors M11 and M13 and an oxide semiconductor (also referred to as a second oxide semiconductor) including the channel formation regions of the transistors M12 and M14 may contain different elements or have different compositions.

[0072] For example, the first oxide semiconductor and the second oxide semiconductor may have different indium contents (ratios of the number of indium atoms to the sum of the numbers of atoms of all metal elements contained in the oxide semiconductors). In this case, for example, the indium content in the second oxide semiconductor may be higher than the indium content in the first oxide semiconductor. For example, an oxide containing indium and zinc (such as indium gallium zinc oxide (IGZO) described later) may be used as the first oxide semiconductor, and indium oxide may be used as the second oxide semiconductor.

[0073] This allows the hole (Hall) mobility of the second oxide semiconductor to be higher than that of the first oxide semiconductor. Therefore, the field-effect mobility of the OS transistors including the second oxide semiconductor (transistors M12 and M14) can be higher than that of the OS transistors including the first oxide semiconductor (transistors M11 and M13). That is, the on-state current of the OS transistors including the second oxide semiconductor (transistors M12 and M14) can be higher than that of the OS transistors including the first oxide semiconductor (transistors M11 and M13).

[0074] Furthermore, when the first oxide semiconductor contains an element such as gallium in addition to indium, the band gap can be made larger than that of the second oxide semiconductor, and therefore the off-state current of the OS transistors including the first oxide semiconductor (the transistors M11 and M13) can be made smaller than that of the OS transistors including the second oxide semiconductor (the transistors M12 and M14).

[0075] <Configuration Example 2 of Semiconductor Device> Next, an example of a stacked structure applicable to the semiconductor device 100 will be described.

[0076] 3A is a cross-sectional view illustrating an example of a stacked structure including a layer Lpd including a light-receiving element PD, a layer Lta including transistors M11 and M13, and a layer Ltb including transistors M12 and M14. FIG. 3B is a top view illustrating an example of a layout of some of the components included in the layers Lta and Ltb shown in FIG. 3A. In FIGS. 3A and 3B, thick dashed lines indicate that the components included in the layer Lta and the components included in the layer Ltb are connected to each other via a conductive layer (not shown). Note that FIG. 3A is a cross-sectional view of the portion indicated by the dashed dotted line AA-BB in FIG. 3B, and is also a cross-sectional view of the channel length direction of each of the transistors M11 to M14.

[0077] 3A, a layer Lta in which the transistors M11 and M13 are provided is disposed on a layer Lpd in which the light receiving element PD is provided, and a layer Ltb in which the transistors M12 and M14 are provided is disposed on the layer Lta. In addition, the layer Ltb is provided with a capacitive element C11.

[0078] One terminal of the light-receiving element PD (here, corresponding to a region in contact with the conductive layer 208_a in the semiconductor region 444) is connected to a conductive layer having a region functioning as one of the source and drain electrodes of the transistor M11 via the conductive layer 208_a, the conductive layer 218_a, the conductive layer 246_a, the conductive layer 248_a, etc., which have a region functioning as the node SN. The other terminal of the light-receiving element PD (here, corresponding to a region in contact with the conductive layer 208_a in the semiconductor region 443) is connected to the conductive layer 208_a, the conductive layer 218_a, the conductive layer 246_a, the conductive layer 248_a, the conductive layer 208_b, the conductive layer 218_b, the conductive layer 246_b, the conductive layer 248_b, etc., which have a region functioning as the wiring VL1. A conductive layer including a region functioning as the other of the source and drain electrodes of the transistor M11 and a region functioning as one of the source and drain electrodes of the transistor M13 is connected to a conductive layer including a region functioning as the gate electrode of the transistor M12 through a conductive layer 248_a, a conductive layer 208_b, a conductive layer 218_b, a conductive layer 246_b, a conductive layer 248_b, or the like, which has a region functioning as the node FD. Note that some conductive layers are not shown in the figure and are indicated by thick dashed lines. The conductive layer including a region functioning as one of the source and drain electrodes of the transistor M12 is connected to a conductive layer 248_b or the like, which has a region functioning as the wiring VL2. The conductive layer including a region functioning as the other of the source and drain electrodes of the transistor M13 is connected to a conductive layer 248_a, a conductive layer 208_b, a conductive layer 218_b, a conductive layer 246_b, a conductive layer 248_b, or the like, which has a region functioning as the wiring VL2. The conductive layer having a region functioning as the other of the source electrode and the drain electrode of the transistor M14 is connected to the conductive layer 248_b having a region functioning as the wiring WX. The conductive layer having a region functioning as the gate electrode of the transistor M11 has a region functioning as the wiring TX. The conductive layer having a region functioning as the gate electrode of the transistor M13 has a region functioning as the wiring RS. The conductive layer having a region functioning as the gate electrode of the transistor M14 has a region functioning as the wiring SE.

[0079] Also, as shown in Figure 3B, each of the conductive layer having a region that functions as wiring TX, the conductive layer having a region that functions as wiring RS, and the conductive layer having a region that functions as wiring SE extends in a first direction (the up-down direction in the drawing), and the conductive layer having a region that functions as wiring WX extends in a second direction (the left-right direction in the drawing) that intersects the first direction.

[0080] Here, the conductive layer having a region that functions as the wiring TX and the conductive layer having a region that functions as the wiring RS are provided on the layer Lta, and the conductive layer having a region that functions as the wiring WX is provided on the layer Ltb. Therefore, it is possible to reduce parasitic capacitance in the region where the conductive layer having a region that functions as the wiring TX and the conductive layer having a region that functions as the wiring RS overlap with the conductive layer having a region that functions as the wiring WX. This makes it possible to improve the readout speed and the signal-to-noise ratio, for example, when the semiconductor device 100 is used in an imaging device.

[0081] 3A and 3B show a configuration in which two transistors, the transistor M11 and the transistor M13, share one island-shaped semiconductor layer 230_a. That is, a portion of the semiconductor layer 230_a functions as the channel formation region of the transistor M11, and another portion functions as the channel formation region of the transistor M13. In addition, in the region between the two channel formation regions of the semiconductor layer 230_a, the other of the source region or the drain region of the transistor M11 is shared with one of the source region or the drain region of the transistor M13. Also, a configuration in which two transistors, the transistor M12 and the transistor M14, share one island-shaped semiconductor layer 230_b is shown. That is, a portion of the semiconductor layer 230_b functions as the channel formation region of the transistor M12, and another portion functions as the channel formation region of the transistor M14. In addition, the other of the source region or the drain region of the transistor M12 and one of the source region or the drain region of the transistor M14 are shared in a region between the two channel formation regions of the semiconductor layer 230_b.

[0082] In this way, by using a structure in which two transistors share one island-shaped semiconductor layer, the area occupied by the transistors can be made smaller than in a structure in which two transistors each have two island-shaped semiconductor layers (that is, a structure in which one transistor has one island-shaped semiconductor layer). Note that a structure in which one transistor has one island-shaped semiconductor layer may also be used.

[0083] In the layer Ltb, an insulating layer 292 is provided to cover the conductive layer 248_b having a region that functions as the node FD. A conductive layer 293 having a region that functions as the wiring VL2 is provided over part of the insulating layer 292. The conductive layer 293 is connected to the conductive layer 294 having a region that functions as the wiring VL2, the conductive layer 248_b, and the like. In a region where the conductive layer 248_b having a region that functions as the node FD and the conductive layer 293 having a region that functions as the wiring VL2 overlap with each other, the conductive layer 248_b has a region that functions as one terminal (also referred to as one electrode) of the capacitor C11, the conductive layer 293 has a region that functions as the other terminal (also referred to as the other electrode) of the capacitor C11, and the insulating layer 292 has a region that functions as a dielectric of the capacitor C11.

[0084] Here, each of the conductive layers may be formed of a conductor having a function as a plug or wiring.

[0085] In this specification and the like, a conductor that functions as a plug or wiring may have multiple components collectively assigned the same reference symbol. The wiring and the plug may be integrated. That is, a portion of the conductor may function as a wiring and a portion of the conductor may function as a plug.

[0086] For each plug or wiring, a conductive material such as a metal material, an alloy material, a nitride material, or an oxide material can be used in a single layer or a laminated layer.

[0087] In particular, it is preferable to use a high-melting-point material that has both heat resistance and conductivity for each plug or wiring. Examples of such materials include tungsten and molybdenum. It is also preferable to use a low-resistance conductive material that can reduce wiring resistance for each plug or wiring. Examples of such materials include aluminum and copper.

[0088] Furthermore, it is preferable to use an insulator made of a material with a high relative dielectric constant (high-k) for the insulating layer 292. By using an insulator made of a high-k material for the insulating layer 292, it is possible to ensure a sufficient capacitance of the capacitive element C11.

[0089] The high-dielectric-constant insulator may be, for example, an oxide, an oxynitride, a nitride oxide, or a nitride containing one or more metal elements selected from aluminum, hafnium, zirconium, and gallium. These materials may also contain silicon. Insulators made of these materials may also be stacked.

[0090] Furthermore, as an insulator of a high dielectric constant material, for example, aluminum oxide, hafnium oxide, zirconium oxide, an oxide having aluminum and hafnium, an oxynitride having aluminum and hafnium, an oxide having silicon and hafnium, an oxynitride having silicon and hafnium, an oxide having silicon and zirconium, an oxynitride having silicon and zirconium, an oxide having hafnium and zirconium, or an oxynitride having hafnium and zirconium can be used.

[0091] Insulators made of the above materials may be stacked. In this case, it is preferable to use a structure in which a high-dielectric-constant material and a material having a higher dielectric strength than the high-dielectric-constant material are stacked.

[0092] As such an insulator, for example, an insulator in which zirconium oxide, aluminum oxide, and zirconium oxide are stacked in this order can be used. Alternatively, for example, an insulator in which zirconium oxide, aluminum oxide, zirconium oxide, and aluminum oxide are stacked in this order can be used. Alternatively, for example, an insulator in which hafnium zirconium oxide, aluminum oxide, hafnium zirconium oxide, and aluminum oxide are stacked in this order can be used. By stacking an insulator with a relatively high dielectric strength, such as aluminum oxide, as the insulator, the dielectric strength can be improved and electrostatic breakdown of a capacitor element having the insulator can be suppressed.

[0093] [Light-Receiving Element PD] Next, the light-receiving element PD provided in the layer Lpd will be described.

[0094] As an example, the light receiving element PD is a pn junction type photodiode (also called a Si photodiode) formed on a silicon substrate, and has a p-type semiconductor region 443 and an n-type semiconductor region 444 provided in a part of the silicon substrate surface side (upper side in the drawing) of the semiconductor region 443.

[0095] Furthermore, on the front surface side of the silicon substrate, an insulating layer 442 is provided in a region that does not overlap with the semiconductor region 444. An insulating layer 441 is provided on the semiconductor region 443, the semiconductor region 444, and the insulating layer 442. An insulating layer 447 is provided on the insulating layer 441. Furthermore, an insulating layer 445 is provided on the rear surface side of the silicon substrate (the lower side in the drawing).

[0096] The light receiving element PD is, for example, a buried photodiode, and can suppress dark current and reduce noise by a thin p-type semiconductor region 443 provided on the silicon substrate surface side of the n-type semiconductor region 444.

[0097] The insulating layer 441 functions as a blocking layer. The insulating layer 442 functions as an element isolation layer. The insulating layer 447 functions as an interlayer insulating film and a planarizing film. The insulating layer 445 functions to suppress the outflow of carriers.

[0098] The insulating layer 442 having a function as an element isolation layer can be formed by a local oxidation of silicon (LOCOS) method, a shallow trench isolation (STI) method, or the like.

[0099] Grooves separating pixels are provided on the back surface of the silicon substrate, and an insulating layer 445 is provided on the back surface of the silicon substrate and in the grooves. The insulating layer 445 prevents carriers generated in the light-receiving element PD from flowing into adjacent pixels. The insulating layer 445 also functions to prevent stray light from entering. Therefore, the insulating layer 445 can suppress color mixing. An anti-reflection film may be provided between the back surface of the silicon substrate and the insulating layer 445.

[0100] The insulating layers may be made of, for example, inorganic insulating films such as silicon oxide and silicon nitride, or organic insulating films such as polyimide and acrylic. The insulating layers may have a multi-layer structure.

[0101] [Transistors M11 to M14] Next, the transistors M11 and M13 provided in the layer Lta and the transistors M12 and M14 provided in the layer Ltb will be described.

[0102] For simplicity of explanation, the transistors provided in the layer Lta and the transistors provided in the layer Ltb are assumed to have the same structure. Note that the transistors provided in the layer Lta and the transistors provided in the layer Ltb may have different structures.

[0103] The transistors provided in the layer Lta and the transistors provided in the layer Ltb may be made to differ in material, film thickness, length, width, etc. of each component, thereby making it possible to make the characteristics of the transistors provided in the layer Lta and the transistors provided in the layer Ltb different.

[0104] 4A to 6C, a configuration example of a transistor 200 that can be applied to each of the transistors M11 to M14 will be described.

[0105] Note that the transistor 200 has a structure in which one transistor has one island-shaped semiconductor layer, but as described above, two transistors may be configured to share one island-shaped semiconductor layer.

[0106] 4A is a top view of the transistor 200. FIG. 4B is a cross-sectional view of the portion indicated by the dashed-dotted line A1-A2 in FIG. 4A, and is also a cross-sectional view of the transistor 200 in the channel length direction. FIG. 4C is a cross-sectional view of the portion indicated by the dashed-dotted line A3-A4 in FIG. 4A, and is also a cross-sectional view of the transistor 200 in the channel width direction. FIG. 4D is a cross-sectional view of the portion indicated by the dashed-dotted line A5-A6 in FIG. 4A. Note that some elements are omitted in the top view of FIG. 4A for clarity. Some elements may also be omitted in the subsequent top views.

[0107] The transistor 200 has a conductive layer 205, an insulating layer 221 on the conductive layer 205, an insulating layer 222 on the insulating layer 221, an insulating layer 224 on the insulating layer 222, a semiconductor layer 230 on the insulating layer 224, conductive layers 242a and 242b on the semiconductor layer 230, an insulating layer 250 on the semiconductor layer 230, and a conductive layer 260 on the insulating layer 250.

[0108] In the transistor 200, the conductive layer 260 functions as a first gate electrode (which can also be referred to as an upper gate electrode or a top gate electrode), and the insulating layer 250 functions as a first gate insulating film. The conductive layer 205 functions as a second gate electrode (which can also be referred to as a lower gate electrode or a bottom gate electrode), and the insulating layers 224, 222, and 221 each function as a second gate insulating film. The conductive layer 242a functions as one of a source electrode and a drain electrode, and the conductive layer 242b functions as the other of the source electrode and the drain electrode.

[0109] Note that the transistor 200 does not necessarily have to include the conductive layer 205. In this case, the conductive layer 260 can be simply called a gate electrode, and the insulating layer 250 can be simply called a gate insulating film.

[0110] An insulating layer 275 is provided over the conductive layer 242a and the conductive layer 242b, and an insulating layer 280 is provided over the insulating layer 275. An opening 289 reaching the insulating layer 222 and the semiconductor layer 230 is formed in the insulating layer 280 and the insulating layer 275, and the opening 289 overlaps with a region between the conductive layer 242a and the conductive layer 242b. In a top view, a side surface of the insulating layer 280 in the opening 289 coincides with a side surface of the conductive layer 242a and a side surface of the conductive layer 242b.

[0111] The insulating layer 250 and the conductive layer 260 are disposed inside the opening 289. An insulating layer 282 is provided in contact with the top surface of the insulating layer 280, the top end of the insulating layer 250, and the top surface of the conductive layer 260. An insulating layer 283 is provided over the insulating layer 282. An insulating layer 216 is provided under the insulating layer 221, an insulating layer 214 is provided under the insulating layer 216 and the conductive layer 205, and an insulating layer 212 is provided under the insulating layer 214. The insulating layer 212, the insulating layer 214, the insulating layer 280, the insulating layer 282, the insulating layer 283, and the insulating layer 285 function as interlayer films.

[0112] Openings reaching the conductive layer 242a are formed in the insulating layers 285, 283, 282, 280, and 275, and the conductive layers 243a and 241a are provided in the openings. The insulating layer 241a is provided in contact with the inner wall of the opening, and the conductive layer 243a is provided inside the insulating layer 241a. Furthermore, openings reaching the conductive layer 242b are formed in the insulating layers 285, 283, 282, 280, and 275, and the conductive layers 243b and 241b are provided in the openings. The insulating layer 241b is provided in contact with the inner wall of the opening, and the conductive layer 243b is provided inside the insulating layer 241b. The conductive layers 243a and 243b function as vias that connect a wiring or the like provided on the transistor 200 to the source or drain of the transistor 200.

[0113] In the semiconductor layer 230, a channel formation region and a source region and a drain region sandwiching the channel formation region are formed, as in the transistor 200. That is, the semiconductor layer 230 has a channel formation region, a source region, and a drain region. At least a part of the channel formation region overlaps with the conductive layer 260. The source region overlaps with the conductive layer 242a, and the drain region overlaps with the conductive layer 242b. Note that the source region and the drain region can be interchanged. The source region and the drain region are n-type regions (low-resistance regions) with a higher carrier concentration than the channel formation region. The semiconductor layer 230 may have a single-layer structure or a stacked structure of two or more layers.

[0114] The shortest distance between the conductive layer 242a and the conductive layer 242b can be defined as the channel length Lch of the transistor 200 (see FIGS. 4A and 4B). The length of the portion where the conductive layer 242a and the conductive layer 242b face each other can be defined as the channel width Wch of the transistor 200 (see FIGS. 4A and 4C).

[0115] A transistor according to one embodiment of the present invention includes a metal oxide (also referred to as an oxide semiconductor) that functions as a semiconductor in a semiconductor layer 230 including a channel formation region. That is, the transistor can be referred to as an OS transistor. Note that in this specification and the like, a semiconductor layer including an oxide semiconductor can be referred to as an oxide semiconductor layer. Furthermore, since the semiconductor layer 230 includes a metal oxide, the semiconductor layer 230 can be referred to as a metal oxide layer.

[0116] An OS transistor has an oxygen vacancy (V Ｏ The presence of oxygen vacancies and impurities may cause fluctuations in electrical characteristics and reduce reliability. Therefore, it is preferable that oxygen vacancies and impurities are reduced as much as possible in the channel formation region of the oxide semiconductor. In other words, it is preferable that the carrier concentration of the channel formation region of the oxide semiconductor is reduced and the channel formation region is made i-type (intrinsic) or substantially i-type.

[0117] On the other hand, the source and drain regions of an OS transistor have more oxygen vacancies than the channel formation region. Ｏ The source and drain regions of an OS transistor are preferably n-type regions having a high carrier concentration and low resistance, as compared with a channel formation region, due to a high concentration of H or an impurity such as hydrogen, nitrogen, or a metal element.

[0118] The band gap of a metal oxide functioning as a semiconductor is preferably 2.0 eV or more, more preferably 2.5 eV or more. By using a metal oxide with a wide band gap for a semiconductor layer, the off-state current of a transistor can be reduced. Since an OS transistor has a small off-state current, the power consumption of a semiconductor device can be sufficiently reduced.

[0119] Here, when an excessive amount of oxygen is supplied to the channel formation region of the semiconductor layer 230, electron traps due to the excess oxygen are formed in the insulating layer 250. As a result, the OS transistor is more likely to experience positive drift degradation in a +GBT (gate bias-temperature) stress test. In other words, the amount of positive drift degradation in the +GBT stress test increases.

[0120] Therefore, in one embodiment of the present invention, the impurity concentration in the channel formation region of the semiconductor layer 230 is preferably low. Furthermore, an appropriate amount of oxygen is preferably supplied to the channel formation region of the semiconductor layer 230. Furthermore, it is preferable to reduce the excessive amount of oxygen in the channel formation region of the semiconductor layer 230.

[0121] The semiconductor layer 230 preferably includes indium oxide. In this case, the semiconductor layer 230 includes indium and oxygen. For example, the semiconductor layer 230 preferably includes an indium oxide film. The higher the ratio of the number of indium atoms to the sum of the numbers of atoms of all metal elements included in the metal oxide (also referred to as the indium (In) content), the higher the field-effect mobility of the transistor. Therefore, by using indium oxide for the semiconductor layer 230, the transistor can have a large on-state current and high frequency characteristics.

[0122] Furthermore, the indium oxide film preferably has crystallinity. For example, the indium oxide film preferably has crystal grains. Examples of films having crystal grains include single-crystal films, polycrystalline films, and amorphous films containing crystal grains. In polycrystalline films, crystal grain boundaries are observed.

[0123] When a metal oxide contains indium and zinc, the metal oxide may have a c-axis aligned crystalline (CAAC) structure. The CAAC structure has fewer crystal grain boundaries in the a-b plane than a polycrystalline structure. Examples of metal oxides containing indium and zinc include indium zinc oxide (In-Zn oxide, also referred to as IZO (registered trademark)) and indium gallium zinc oxide (In-Ga-Zn oxide, also referred to as IGZO).

[0124] In a crystalline oxide semiconductor layer, an indium oxide film is a film through which one or both of hydrogen and oxygen move more easily than, for example, an IGZO film. Therefore, it can be said that an indium oxide film is a film through which one or both of hydrogen and oxygen are more easily supplied and from which one or both of hydrogen and oxygen are more easily discharged than, for example, an IGZO film. Note that it can be said that an indium oxide film is a film that is highly permeable to one or both of hydrogen and oxygen than, for example, an IGZO film. In other words, it can be said that an indium oxide film is a film that has a lower barrier property against one or both of hydrogen and oxygen than, for example, an IGZO film.

[0125] 4A to 4D show an example in which the semiconductor layer 230 has a single-layer structure. The semiconductor layer 230 can have a stacked structure of two or more layers. For example, when the semiconductor layer 230 has a two-layer structure of a first semiconductor layer and a second semiconductor layer on the first semiconductor layer, it is preferable to use a metal oxide (typically indium oxide) applicable to the semiconductor layer 230 described above as the first semiconductor layer, and a metal oxide whose conduction band minimum is located closer to the vacuum level than the conduction band minimum of the first semiconductor layer as the second semiconductor layer. In this case, the first semiconductor layer can mainly function as a current path. That is, the first semiconductor layer has a channel formation region on the surface on the second semiconductor layer side and in the vicinity thereof.

[0126] The above-described structure can reduce carriers trapped at the interface of the first semiconductor layer and its vicinity. In addition, the channel can be located away from the surface of the insulating layer 250, reducing the influence of surface scattering. This can increase the field-effect mobility of the transistor.

[0127] Examples of metal oxides that can be used for the second semiconductor layer include indium gallium oxide (In—Ga oxide), In—Zn oxide, indium tin oxide (In—Sn oxide, also referred to as ITO), indium titanium oxide (In—Ti oxide), indium aluminum zinc oxide (In—Al—Zn oxide, also referred to as IAZO), In—Ga—Zn oxide, indium tin zinc oxide (In—Sn—Zn oxide), indium titanium zinc oxide (In—Ti—Zn oxide), and indium tin oxide containing silicon oxide (ITSO). Alternatively, zinc oxide, aluminum zinc oxide (Al—Zn oxide, also referred to as AZO), and aluminum tin oxide (Al—Sn oxide) can be used.

[0128] Specifically, the In-Zn oxide used in the second semiconductor layer can have a composition of In:Zn = 1:1 [atomic ratio] or thereabouts, In:Zn = 2:1 [atomic ratio] or thereabouts, or In:Zn = 4:1 [atomic ratio] or thereabouts. Furthermore, the IGZO used in the second semiconductor layer can have a composition of In:Ga:Zn = 1:1:1 [atomic ratio] or thereabouts, In:Ga:Zn = 1:3:2 [atomic ratio] or thereabouts, or In:Ga:Zn = 1:3:4 [atomic ratio] or thereabouts. Note that a composition in the vicinity includes a range of plus or minus 30% of the desired atomic ratio.

[0129] The crystallinity of the metal oxide included in the second semiconductor layer is not particularly limited. For example, the second semiconductor layer may include at least one of an amorphous semiconductor (a semiconductor having an amorphous structure), a single-crystal semiconductor (a semiconductor having a single-crystal structure), and a semiconductor having crystallinity other than single crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor having a crystalline region in part).

[0130] Although not shown, in the transistor 200, a crystalline portion may be provided on part of the insulating layer 224, and the semiconductor layer 230 may be provided to cover the crystalline portion.

[0131] The crystalline portion has crystals. The crystalline portion functions as a seed or a nucleus when a process for increasing the crystallinity of the semiconductor layer 230 is performed. In other words, the crystalline portion functions as a seed or a nucleus when crystals grow in the semiconductor layer 230. In this specification and the like, the crystalline portion or the crystals contained in the crystalline portion can be referred to as a seed crystal or a crystal nucleus.

[0132] Here, the indium oxide crystal has a cubic crystal structure (bixbyite type). When indium oxide is used for the semiconductor layer 230, the crystal portion preferably has, for example, a hexagonal or trigonal crystal structure. In this case, the crystal portion has a crystal with a <001> crystal orientation relative to the surface or surface on which the crystal portion is formed, thereby forming the semiconductor layer 230 having a crystal with a <111> crystal orientation. When the crystal of the crystal portion has a <001> crystal orientation relative to the surface or surface on which the crystal portion is formed, the c-axis of the crystal is perpendicular to the surface or surface on which the crystal portion is formed. Note that a crystal with a hexagonal or trigonal crystal structure can sometimes be referred to as a crystal with a layered structure, and therefore the above structure can be considered as a structure in which the semiconductor layer 230 having a crystal with a cubic crystal structure is formed on a crystal portion having a crystal with a layered structure. In other words, it can also be considered as a stacked structure manufactured using a heteroepitaxial growth technique or a technique similar to heteroepitaxial growth.

[0133] In this specification, space groups are expressed using short notation in international notation (or Hermann-Mauguin notation). Crystal planes and crystal orientations are expressed using Miller indices. In crystallography, space groups, crystal planes, and crystal orientations are expressed by adding a superscript bar to the numbers. However, in this specification, due to formatting restrictions, numbers may be expressed by adding a minus sign (-) before them instead of adding a bar above them. Individual orientations indicating directions within a crystal are expressed with [ ], collective orientations indicating all equivalent orientations are expressed with < >, individual planes indicating crystal planes are expressed with ( ), and collective planes with equivalent symmetry are expressed with {}.

[0134] In this specification, the crystal orientation of a crystal refers to the orientation relative to the surface of a film containing the crystal or the surface on which the crystal is formed. For example, a crystal with a crystal orientation of <100> is said to be a crystal whose (100) plane is parallel to the surface of a film containing the crystal or the surface on which the crystal is formed.

[0135] Specifically, zinc oxide, In—Ga oxide, gallium zinc oxide (Ga—Zn oxide, also referred to as GZO), aluminum zinc oxide (Al—Zn oxide, also referred to as AZO), In—Al—Zn oxide, In—Ga—Zn oxide, or In—Sn—Zn oxide can be used as the crystal portion. It is preferable to use In—Ga—Zn oxide as the crystal portion. In this case, the crystal portion contains indium, gallium, zinc, and oxygen. Specifically, it is preferable to use a composition of In:Ga:Zn=1:1:1 [atomic ratio] or a composition thereabout, or a composition of In:Ga:Zn=1:3:2 [atomic ratio] or a composition thereabout. Metal oxides with these compositions are suitable for the crystal portion because they easily form a layered structure.

[0136] In—Ga—Zn oxide and In—Sn—Zn oxide are likely to have a CAAC structure. When an oxide having a CAAC structure is used for the crystal portion, the c-axis of the crystal nucleus is perpendicular to the surface of the crystal portion or the surface on which it is formed. In other words, by using an oxide that is likely to have a CAAC structure for the crystal portion, it is possible to improve the controllability of the crystal orientation of the crystal nucleus.

[0137] When an oxide that easily has a CAAC structure is used for the crystal portion, the semiconductor layer 230 can be formed having crystals with a <111> crystal orientation.

[0138] The crystal portion can also be made of an oxide having a cubic crystal structure. When the crystal of the crystal portion has the same crystal structure as the crystal of the semiconductor layer 230, the semiconductor layer 230 can grow epitaxially using the crystal portion as a nucleus, thereby improving the crystallinity of the semiconductor layer 230. Note that crystals of oxides containing Group 3 elements in the periodic table tend to have a cubic crystal structure. Furthermore, the Group 3 elements in the crystals are primarily present as trivalent cations. Therefore, the crystal portion preferably contains at least one element that can become a trivalent cation. The element that can become a trivalent cation contained in the crystal portion is preferably scandium, yttrium, cerium, gadolinium, erbium, ytterbium, or the like.

[0139] The crystal portion can be made of, for example, an oxide containing one or both of yttrium and zirconium, erbium oxide, etc. Examples of oxides containing one or both of yttrium and zirconium include yttrium oxide, zirconium oxide, and yttrium zirconium oxide.

[0140] Furthermore, indium oxide may be used for the crystalline portion. By using indium oxide for the crystalline portion, the semiconductor layer 230 can be homoepitaxially grown using the crystalline portion as a nucleus, thereby improving the crystallinity of the semiconductor layer 230. In this case, the crystal orientation of the crystals in the crystalline portion and the crystal orientation of the crystals in the semiconductor layer 230 coincide with each other.

[0141] There are no particular limitations on the material that can be used for the crystal portion. The crystal portion may be made of an insulating material, a semiconductor material, or a conductive material. When a semiconductor material is used for the crystal portion, the crystal portion may be considered as part of the semiconductor layer 230.

[0142] The crystal portion may have, in a top view, a substantially circular shape such as a circle or an ellipse, a polygonal shape such as a triangle, a quadrangle (including a rectangle, a rhombus, and a square), a pentagon, or a star-shaped polygon, or a shape with rounded corners. For example, the crystal portion may have a region extending along the top surface of the insulating layer 224. For example, the crystal portion may be provided in contact with the top surface of the insulating layer 224, or may be provided so as to fill a recess or an opening provided in the insulating layer 224. The transistor 200 may not have a crystal portion, for example. For example, the crystal portion may be provided outside the transistor formation region, and the crystal portion may be removed after a process for increasing the crystallinity of the semiconductor layer 230 is performed.

[0143] 5 to 6C are enlarged cross-sectional views of the transistor 200 shown in FIGS. 4A to 4D in the channel length direction.

[0144] By providing an insulating layer containing excess oxygen near the oxide semiconductor layer and performing heat treatment, oxygen can be supplied from the insulating layer to the oxide semiconductor layer, thereby reducing oxygen vacancies. However, excessive oxygen supplied to the source or drain region may cause a decrease in the on-state current or field-effect mobility of the transistor 200. Furthermore, variations in the amount of oxygen supplied to the source or drain region within the substrate surface may cause variations in the characteristics of the transistor. Furthermore, excessively large amounts of oxygen supplied from the insulating layer to the oxide semiconductor layer may adversely affect the electrical characteristics and reliability of the transistor. Furthermore, oxygen may diffuse into conductive layers such as the gate electrode, source electrode, and drain electrode, oxidizing the conductive layers and reducing their conductivity.

[0145] First, it is preferable to form at least one of an insulating layer having a barrier property against hydrogen and an insulating layer having a function of capturing or fixing hydrogen near the semiconductor layer 230, thereby reducing the hydrogen concentration in the channel formation region of the semiconductor layer 230 and its vicinity.

[0146] At least one of the insulating layer 212, the insulating layer 214, the insulating layer 221, the insulating layer 222, the insulating layer 275, the insulating layer 282, and the insulating layer 283 preferably functions as a barrier insulating layer against hydrogen. At least one of the insulating layer 212, the insulating layer 214, the insulating layer 221, the insulating layer 222, the insulating layer 275, the insulating layer 282, and the insulating layer 283 preferably functions as a barrier insulating layer against impurities. At least one of the insulating layer 212, the insulating layer 214, the insulating layer 221, the insulating layer 222, the insulating layer 275, the insulating layer 282, and the insulating layer 283 preferably functions as a barrier insulating layer against oxygen. Note that all of the insulating layer 212, the insulating layer 214, the insulating layer 221, the insulating layer 222, the insulating layer 275, the insulating layer 282, and the insulating layer 283 do not necessarily need to be provided. As long as the insulating layer has sufficient barrier properties against hydrogen, impurities, oxygen, and the like, the insulating layer can be formed by appropriately selecting from the insulating layer 212, the insulating layer 214, the insulating layer 221, the insulating layer 222, the insulating layer 275, the insulating layer 282, and the insulating layer 283. For example, a structure can be used in which the insulating layer 216 and the conductive layer 205 are formed in contact with the upper surface of the insulating layer 212 without providing the insulating layer 214.

[0147] The insulating layer 212, the insulating layer 221, the insulating layer 275, and the insulating layer 283 preferably have a function of suppressing diffusion of hydrogen. For example, the insulating layer 212, the insulating layer 221, the insulating layer 275, and the insulating layer 283 may be formed using silicon nitride, which has a higher hydrogen barrier property.

[0148] The insulating layer 214, the insulating layer 222, and the insulating layer 282 preferably have a function of capturing or fixing hydrogen. For example, aluminum oxide may be used for the insulating layer 214 and the insulating layer 282. For example, hafnium oxide, which is a high-k material, is preferably used for the insulating layer 222, which functions as the second gate insulating film.

[0149] 5, by providing the insulating layer 212 having the function of suppressing hydrogen diffusion under the transistor 200, it is possible to suppress diffusion of hydrogen from the layer below the transistor 200. Furthermore, by providing the insulating layer 214 having the function of capturing or fixing hydrogen, hydrogen contained in the insulating layer 216 or the like can be captured or fixed in the insulating layer 214. This makes it possible to reduce the hydrogen concentration in the semiconductor layer 230 and its vicinity.

[0150] Furthermore, by providing the insulating layer 221 having a function of suppressing hydrogen diffusion under the semiconductor layer 230, it is possible to suppress diffusion of hydrogen from below the semiconductor layer 230. Furthermore, by providing the insulating layer 222 having a function of capturing or fixing hydrogen, hydrogen contained in the insulating layer 224 or the like can be captured or fixed in the insulating layer 222. This makes it possible to reduce the hydrogen concentration in the semiconductor layer 230 and its vicinity.

[0151] Furthermore, by providing an insulating layer 275 having the function of suppressing the diffusion of hydrogen so as to cover the semiconductor layer 230, the conductive layer 242a, the conductive layer 242b, etc., it is possible to suppress the diffusion of hydrogen from the insulating layer 280 to the semiconductor layer 230, the conductive layer 242a, the conductive layer 242b, etc.

[0152] Furthermore, by providing the insulating layer 283 having a function of suppressing hydrogen diffusion over the transistor 200, it is possible to suppress diffusion of hydrogen from above the transistor 200. Furthermore, by providing the insulating layer 282 having a function of capturing or fixing hydrogen, hydrogen contained in the insulating layer 280 or the like can be captured or fixed to the insulating layer 282. This makes it possible to reduce the hydrogen concentration in the semiconductor layer 230 and its vicinity.

[0153] In this manner, by surrounding the transistor 200 from above and below with barrier insulating layers against hydrogen, diffusion of hydrogen into the oxide semiconductor can be reduced, and the hydrogen concentration in the channel formation region can be reduced, thereby improving the electrical characteristics and reliability of the transistor 200.

[0154] Furthermore, excess oxygen is preferably contained in the insulating layer 280. By supplying the oxygen to the semiconductor layer 230 through the insulating layer 250 by heat treatment, oxygen vacancies in the channel formation region can be reduced.

[0155] The insulating layer 282 is preferably formed by a sputtering method in an atmosphere containing oxygen gas, which allows oxygen to be added to the insulating layer 280. The insulating layer 282 may have a single-layer structure or a stacked structure of two or more layers.

[0156] As described above, by performing heat treatment on the insulating layer 280 containing excess oxygen, a suitable amount of oxygen can be supplied to the semiconductor layer 230 through the insulating layer 250. In the heat treatment, the insulating layers 282 and 283 having a barrier property against oxygen are formed on the insulating layer 280, so that the oxygen contained in the insulating layer 280 can be prevented from diffusing excessively from the insulating layer 280. Furthermore, the insulating layer 275 having a barrier property against oxygen is formed between the insulating layer 280 and the semiconductor layer 230, the conductive layer 242a, and the conductive layer 242b, so that the oxygen contained in the insulating layer 280 can be prevented from diffusing excessively from the insulating layer 280. Furthermore, by performing the heat treatment with openings formed in parts of the insulating layer 280, the insulating layer 282, and the insulating layer 283, part of the oxygen contained in the insulating layer 280 can be diffused outward, and the amount of oxygen supplied from the insulating layer 280 to the semiconductor layer 230 can be adjusted.

[0157] 5 shows an example in which the semiconductor layer 230 has a single-layer structure. Note that the semiconductor layer 230 can have a stacked structure of two or more layers. As shown in FIG. 6A, the semiconductor layer 230 can have a two-layer structure of a semiconductor layer 230_1 and a semiconductor layer 230_2 over the semiconductor layer 230_1.

[0158] 6A illustrates a structure in which the insulating layer 250 is in contact with the top surface of the semiconductor layer 230_2, but one embodiment of the present invention is not limited to this. For example, as shown in FIG. 6B , a structure can be adopted in which the semiconductor layer 230_2 in a region overlapping with the opening 289 is removed and the insulating layer 250 is in contact with the side surface of the semiconductor layer 230_2 and the top surface of the semiconductor layer 230_1. With such a structure, the distance between the conductive layer 260 and the semiconductor layer 230_1 can be shortened. Therefore, an electric field from the gate electrode can be suitably applied to the semiconductor layer 230_1.

[0159] The insulating layer 250 preferably has a structure that allows oxygen to diffuse from the insulating layer 280 to the semiconductor layer 230 and prevents the conductive layers 242 a, 242 b, and 260 from being oxidized.

[0160] The insulating layer 250 is formed within the opening 289 in contact with the top surface of the insulating layer 222, the side surface of the insulating layer 224, the side surface and top surface of the semiconductor layer 230, the side surface of the conductive layer 242a, the side surface of the conductive layer 242b, the side surface of the insulating layer 275, and the side surface of the insulating layer 280.

[0161] FIG. 4B shows an example in which the insulating layer 250 has a single-layer structure. The insulating layer 250 can have a stacked structure of two or more layers. In this case, the insulating layer 250 is preferably formed of two or more types of films. By forming the insulating layer 250 into two or more types of films, multiple functions can be imparted to the insulating layer 250. Examples of the functions of the insulating layer 250 include a function of extracting excess oxygen from the semiconductor layer 230, a function of extracting hydrogen from the semiconductor layer 230, and a function of suppressing diffusion of hydrogen into the semiconductor layer 230.

[0162] For example, as shown in FIG. 5, the insulating layer 250 preferably has a stacked structure of an insulating layer 250_1 in contact with the semiconductor layer 230, an insulating layer 250_2 over the insulating layer 250_1, and an insulating layer 250_3 over the insulating layer 250_2.

[0163] The insulating layer 250_1 can be formed using any of the materials applicable to the insulating layer 250. For example, the insulating layer 250_1, which has regions in contact with the side surfaces of the conductive layer 242a and the conductive layer 242b, has a function of capturing or adhering oxygen, thereby preventing the side surfaces of the conductive layer 242a and the conductive layer 242b from being oxidized and forming an oxide film on the side surfaces. This can prevent a decrease in the on-state current or the field-effect mobility of the transistor 200. Furthermore, this structure can reduce the amount of oxygen in the insulating layer 250_2 absorbed by the conductive layer 242a and the conductive layer 242b. Therefore, an appropriate amount of oxygen can be supplied from the insulating layer 250_2 to the semiconductor layer 230, thereby reducing oxygen vacancies in the channel formation region of the semiconductor layer 230.

[0164] Furthermore, by providing the insulating layer 250_1 between the insulating layer 280 and the insulating layer 250_2 and between the insulating layer 250_2 and the semiconductor layer 230, excessive supply of oxygen from the insulating layer 280 to the semiconductor layer 230 can be suppressed, and an appropriate amount of oxygen can be supplied to the semiconductor layer 230. Therefore, the amount of oxygen in the channel formation region of the semiconductor layer 230 and its vicinity can be controlled to an appropriate amount, thereby preventing an excessive positive shift of the transistor 200 and improving reliability. Furthermore, excessive oxidation of the source and drain regions can be suppressed, which can reduce the on-state current or the field-effect mobility of the transistor 200.

[0165] By adopting the above-described structure, the channel formation region can be made i-type or substantially i-type, and the source region and drain region can be made n-type, thereby providing a transistor with excellent electrical characteristics. Furthermore, by adopting the above-described structure, the transistor can have excellent electrical characteristics even when miniaturized or highly integrated. Furthermore, miniaturizing the transistor 200 can improve high-frequency characteristics. Specifically, the cutoff frequency can be improved.

[0166] Furthermore, a high-k material with a high dielectric constant can be used for the insulating layer 250_1. An example of a high-k material is an oxide containing one or both of aluminum and hafnium. Using a high-k material for the insulating layer 250_1 makes it possible to reduce the gate potential applied during transistor operation while maintaining the physical thickness of the gate insulating film. Furthermore, it makes it possible to reduce the equivalent oxide thickness (EOT) of the insulator that functions as the gate insulating film.

[0167] From the above, it is preferable to use an oxide containing one or both of aluminum and hafnium for the insulating layer 250_1, and it is more preferable to use an oxide having an amorphous structure and containing one or both of aluminum and hafnium. Aluminum oxide having an amorphous structure is preferably used because an amorphous film can be formed relatively easily using an ALD method. Aluminum oxide has a function of capturing or fixing oxygen and hydrogen, and therefore can be suitably used for the insulating layer 250_1. Alternatively, hafnium oxide has a high function of capturing or fixing oxygen and hydrogen, and therefore can be suitably used for the insulating layer 250_1.

[0168] For example, the insulating layer 250_2 preferably includes a material with a low dielectric constant, such as a silicon oxide film or a silicon oxynitride film.

[0169] Silicon oxide or silicon nitride is an insulating material with high dielectric strength. This can reduce the gate leakage current of a transistor. Furthermore, a silicon oxide film or a silicon oxynitride film is also a film with high hydrogen permeability. Therefore, the insulating layer 250 may have a three-layer structure including an insulating layer 250_2, an insulating layer 250_1 on the insulating layer 250_2, and an insulating layer 250_3 on the insulating layer 250_1. With this structure, hydrogen in the semiconductor layer 230 can diffuse into the insulating layer 250_1 through the insulating layer 250_2 and be captured or fixed. Therefore, the hydrogen concentration in the semiconductor layer 230 can be reduced.

[0170] The insulating layer 250_3 preferably has a barrier property against hydrogen. With such a structure, diffusion of hydrogen into the semiconductor layer 230 can be suppressed. Furthermore, the insulating layer 250_3 preferably has a barrier property against oxygen. The insulating layer 250_3 is provided between the channel formation region of the semiconductor layer 230 and the conductive layer 260. With such a structure, oxygen contained in the channel formation region of the semiconductor layer 230 can be prevented from diffusing into the conductive layer 260 and forming oxygen vacancies in the channel formation region of the semiconductor layer 230. Furthermore, oxygen contained in the semiconductor layer 230 can be prevented from diffusing into the conductive layer 260 and oxidizing the conductive layer 260. The insulating layer 250_3 is preferably at least less permeable to oxygen than the insulating layer 250_2. Furthermore, the insulating layer 250_3 preferably has a function of suppressing diffusion of hydrogen. This can prevent impurities such as hydrogen contained in the conductive layer 260 from diffusing into the semiconductor layer 230. For example, silicon nitride is preferably used as the insulating layer 250_3.

[0171] The insulating layer 250 can have a three-layer structure in which a hafnium oxide film, a silicon oxide film, and a silicon nitride film are stacked in this order from the semiconductor layer 230 side. The thicknesses of the hafnium oxide film, the silicon oxide film, and the silicon nitride film are 2 nm, 2 nm, and 1 nm, respectively. This structure allows excess oxygen in the semiconductor layer 230 to be discharged to the insulating layer 250, thereby reducing the amount of excess oxygen in the semiconductor layer 230. Furthermore, hydrogen in the semiconductor layer 230 can be captured or fixed. This allows the electrical characteristics and reliability of the transistor 200 to be improved. The insulating layer 250 can also have a three-layer structure in which a silicon oxide film, a hafnium oxide film, and a silicon nitride film are stacked in this order from the semiconductor layer 230 side.

[0172] 6C , an insulating layer 250_4 may be provided over the insulating layer 250_2. The insulating layer 250_4 can be formed using an insulating material that can be used for the insulating layer 250_1. For example, by providing the insulating layer 250_4 having a function of capturing or fixing hydrogen between the insulating layer 250_3 and the insulating layer 250_2, hydrogen contained in the insulating layer 250_2 or the like can be captured or fixed.

[0173] Specifically, the insulating layer 250 preferably has a four-layer structure in which an aluminum oxide film, a silicon oxide film, a hafnium oxide film, and a silicon nitride film are stacked in this order from the semiconductor layer 230 side. With such a structure, hydrogen in the semiconductor layer 230 can be diffused to the insulating layer 250_1 or the insulating layer 250_4 and captured or fixed. Therefore, the hydrogen concentration in the semiconductor layer 230 can be reduced.

[0174] The insulating layer 250 is preferably a thin film. For example, the subthreshold swing value (also referred to as S value) can be reduced by setting the thickness of the insulating layer 250 to 1 nm or more and 20 nm or less, preferably 3 nm or more and 10 nm or less. Note that the S value refers to the amount of change in gate voltage when the drain current is changed by one order of magnitude with the drain voltage held constant in the subthreshold region.

[0175] The thickness of each layer constituting the insulating layer 250 is preferably 0.1 nm to 20 nm, more preferably 0.1 nm to 10 nm, more preferably 0.1 nm to 5.0 nm, more preferably 0.5 nm to 5.0 nm, more preferably 1.0 nm to less than 5.0 nm, and even more preferably 1.0 nm to 3.0 nm. Note that it is sufficient that each layer constituting the insulating layer 250 has a region with the above-described thickness in at least a portion thereof.

[0176] Note that the insulating layer 250 having a four-layer structure may not include the insulating layer 250_3. For example, an insulating layer having a function of capturing or fixing oxygen may be used as the insulating layer 250_1, an insulating layer containing a material with a low dielectric constant may be used as the insulating layer 250_2, and an insulating layer having a function of capturing or fixing hydrogen may be used as the insulating layer 250_4. Specifically, the insulating layer 250 may have a three-layer structure in which an aluminum oxide film, a silicon oxide film, and a hafnium oxide film are stacked in this order from the semiconductor layer 230 side.

[0177] In order to thin the insulating layers 250_1 to 250_4 as described above, the insulating layers 250_1 to 250_4 are preferably deposited by an ALD method. In addition, in order to form the insulating layers 250_1 to 250_4 in the opening 289 with good coverage, the insulating layers 250_1 to 250_4 are preferably deposited by an ALD method.

[0178] It is preferable to use the ALD process two or more times in forming the insulating layer 250 having a stacked structure of multiple insulating films. For example, it is preferable that two or more of the multiple insulating films included in the insulating layer 250 are formed using the ALD process. By forming at least two or more types of insulating films using the ALD process, it is possible to improve the coverage and film thickness uniformity of the insulating layer 250. Furthermore, for example, it is possible to increase productivity by successively forming two or more types of insulating films using the ALD process.

[0179] Although the insulating layer 250 has been described above as having a three-layer structure or a four-layer structure, one embodiment of the present invention is not limited to this. The insulating layer 250 can have a structure including at least one of the insulating layers 250_1 to 250_4. When the insulating layer 250 includes one, two, or three of the insulating layers 250_1 to 250_4, the manufacturing process of the transistor can be simplified and productivity can be improved.

[0180] The conductive layer 205 is disposed so as to overlap with the semiconductor layer 230 and the conductive layer 260. Here, the conductive layer 205 is provided so as to be embedded in an opening formed in the insulating layer 216. The conductive layer 205 is preferably provided so as to extend in the channel width direction as shown in FIGS. 4A and 4C. With such a structure, the conductive layer 205 functions as a wiring when a plurality of transistors are provided.

[0181] 5, the conductive layer 205 preferably includes a conductive layer 205_1 and a conductive layer 205_2. The conductive layer 205_1 is provided in contact with the bottom and inner wall of the opening. The conductive layer 205_2 is provided so as to fill a recess in the conductive layer 205_1 that is formed to conform to the shape of the opening. Here, the height of the top surface of the conductive layer 205 is the same as the height of the top surface of the insulating layer 216.

[0182] Here, the conductive layer 205_1 contains hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N ２ O, NO, NO ２ It is preferable to have a conductive material that has a function of suppressing the diffusion of impurities such as copper atoms, etc. Alternatively, it is preferable to have a conductive material that has a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms and oxygen molecules, etc.).

[0183] By using a conductive material that can reduce hydrogen diffusion for the conductive layer 205_1, impurities such as hydrogen contained in the conductive layer 205_2 can be prevented from diffusing into the semiconductor layer 230 via the insulating layer 216 or the like. Furthermore, by using a conductive material that can suppress oxygen diffusion for the conductive layer 205_1, oxidation of the conductive layer 205_2 and a decrease in conductivity can be suppressed. Examples of conductive materials that can suppress oxygen diffusion include titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, and ruthenium oxide. The conductive layer 205_1 can have a single-layer structure or a stacked-layer structure of the above conductive materials. For example, the conductive layer 205_1 preferably contains titanium nitride.

[0184] The conductive layer 205_2 is preferably formed using a conductor with high conductivity. For example, the conductive layer 205_2 is preferably formed using a conductive material containing tungsten, copper, or aluminum as a main component. For example, the conductive layer 205_2 preferably contains tungsten.

[0185] The conductive layer 205 can function as a second gate electrode. In this case, the threshold voltage (Vth) of the transistor 200 can be adjusted by controlling the potential applied to the conductive layer 205 independently of the potential applied to the conductive layer 260. In particular, applying a negative potential to the conductive layer 205 can increase the Vth of the transistor 200 and reduce the off-state current. Therefore, applying a negative potential to the conductive layer 205 can reduce the drain current when the potential applied to the conductive layer 260 is 0 V, compared to when no negative potential is applied.

[0186] 5 shows a stacked structure of the conductive layer 205_1 and the conductive layer 205_2, but one embodiment of the present invention is not limited thereto. The conductive layer 205 may have a single-layer structure or a stacked structure of three or more layers. For example, the conductive layer 205_1 may have a two-layer structure of a tantalum nitride film and a titanium nitride film over the tantalum nitride film, and the conductive layer 205_2 having a tungsten film may be provided over the conductive layer 205_1. With such a structure, impurities such as hydrogen and metal impurities such as copper contained in the lower layer of the transistor 200 can be prevented from diffusing into the conductive layer 205.

[0187] The insulating layer 224 functions as a second gate insulating film together with the insulating layers 221 and 222 .

[0188] The insulating layer 224 preferably includes, for example, a silicon oxide film or a silicon oxynitride film. This allows oxygen to be supplied from the insulating layer 224 to the semiconductor layer 230, thereby reducing oxygen vacancies. Note that the insulating layer 224 may have a stacked structure of two or more layers. In this case, the insulating layer 224 is not limited to a stacked structure made of the same material, and may have a stacked structure made of different materials.

[0189] The insulating layer 224 is preferably processed into an island shape, similar to the semiconductor layer 230. Thus, when a plurality of transistors 200 are provided, each transistor 200 has an insulating layer 224 of approximately the same size. As a result, the amount of oxygen supplied from the insulating layer 224 to the semiconductor layer 230 in each transistor 200 becomes approximately the same. Therefore, variation in the electrical characteristics of the transistors 200 within the substrate surface can be suppressed.

[0190] Furthermore, by providing the insulating layer 224 in an island shape, at least a part of the lower surface of the conductive layer 260 can be provided below the lower surface of the semiconductor layer 230 (see FIG. 4C ). This allows the conductive layer 260 to be provided facing the upper surface and side surface of the semiconductor layer 230, and therefore the electric field of the conductive layer 260 can be applied to the upper surface and side surface of the semiconductor layer 230.

[0191] However, although not shown, the insulating layer 224 does not necessarily have to be processed into an island shape. When multiple transistors are provided on the same substrate, the insulating layer 224 is formed without being processed into an island shape, so that the semiconductor layer 230 of each transistor is formed on the same insulating layer 224. This can reduce variations in the amount of oxygen supplied from the insulating layer 224 to the semiconductor layer 230 of each transistor. Therefore, variations in the electrical characteristics of each transistor can be reduced.

[0192] The conductive layers 242a and 242b are preferably made of a conductive material that is resistant to oxidation or a conductive material that has a function of suppressing oxygen diffusion. Examples of such a conductive material include a conductive material containing nitrogen and a conductive material containing oxygen. This can suppress a decrease in the conductivity of the conductive layers 242a and 242b.

[0193] For the conductive layers 242a and 242b, it is preferable to use a nitride, such as a nitride containing tantalum, a nitride containing titanium, a nitride containing molybdenum, a nitride containing tungsten, a nitride containing tantalum and aluminum, or a nitride containing titanium and aluminum. For example, tantalum nitride can be used for the conductive layers 242a and 242b. Alternatively, for example, ruthenium, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, ITO, ITSO, or In—Zn oxide may also be used. These materials are preferable because they are conductive materials that are resistant to oxidation or that maintain conductivity even when absorbing oxygen.

[0194] Alternatively, each of the conductive layers 242a and 242b may have a stacked structure. In this case, the above-mentioned conductive material may be used for the lower layer (layer having a large contact area with the semiconductor layer 230) of the conductive layer 242a and the conductive layer 242b, and a conductive material with higher conductivity may be used for the upper layer of the conductive layer 242a and the conductive layer 242b. For example, tantalum nitride may be used for the lower layer, and tungsten may be used for the upper layer. Alternatively, ITO or ITSO may be used for the lower layer, and tungsten may be used for the upper layer.

[0195] The conductive layer 260 is provided in the opening 289 so as to cover the upper surface of the insulating layer 222, the side surface of the insulating layer 224, and the side and upper surface of the semiconductor layer 230 via the insulating layer 250. The height of the upper surface of the conductive layer 260 is the same as the height of the upper end of the insulating layer 250 and the height of the upper surface of the insulating layer 280.

[0196] The inner wall of the opening 289 may be perpendicular to the upper surface of the insulating layer 222 or may have a tapered shape. By making the inner wall tapered, the coverage of the insulating layer 250 provided in the opening 289 can be improved and defects such as voids can be reduced.

[0197] 4A and 4C, the conductive layer 260 is preferably provided to extend in the channel width direction. With this structure, when a plurality of transistors are provided, the conductive layer 260 functions as a wiring.

[0198] 4C , in a cross-sectional view of the transistor 200 in the channel width direction, a curved surface may be formed between the side surface of the semiconductor layer 230 and the top surface of the semiconductor layer 230. In other words, the end of the side surface and the end of the top surface may be curved.

[0199] 5, the conductive layer 260 preferably has a two-layer structure. Here, the conductive layer 260 preferably includes a conductive layer 260_1 and a conductive layer 260_2 disposed on the conductive layer 260_1. For example, the conductive layer 260_1 is preferably disposed so as to surround the bottom and side surfaces of the conductive layer 260_2.

[0200] For example, it is preferable to use titanium nitride for the conductive layer 260_1 and tungsten for the conductive layer 260_2. Alternatively, it is preferable to use tantalum nitride for the conductive layer 260_1 and copper for the conductive layer 260_2. With such a structure, the conductivity of the conductive layer 260 can be increased.

[0201] The conductive layer 260 may also have a stacked structure of three or more layers, such as a tantalum nitride film, a titanium nitride film on the tantalum nitride film, and a tungsten film on the titanium nitride film.

[0202] The insulating layer 216, the insulating layer 280, and the insulating layer 285 preferably have a lower dielectric constant than the insulating layer 222. By using a material with a low dielectric constant as an interlayer film, parasitic capacitance generated between wirings can be reduced.

[0203] For example, the insulating layer 216, the insulating layer 280, and the insulating layer 285 can each be made of a material with a low dielectric constant, which will be described later in the section [Insulating Layer]. In particular, silicon oxide and silicon oxynitride are preferable because they are thermally stable. Furthermore, materials such as silicon oxide, silicon oxynitride, and silicon oxide with vacancies are preferable because they can easily form a region containing excess oxygen.

[0204] Furthermore, the upper surfaces of the insulating layer 216 and the insulating layer 280 may each be flattened.

[0205] It is preferable that the concentration of impurities such as water and hydrogen is reduced in the insulating layer 280. For example, it is preferable that the insulating layer 280 has an oxide containing silicon, such as silicon oxide or silicon oxynitride.

[0206] The conductive layers 243a and 243b are preferably formed using a conductive material containing, for example, tungsten, copper, or aluminum as a main component. The conductive layers 243a and 243b may have a stacked structure.

[0207] 5, the conductive layer 243a and the conductive layer 243b may have a two-layer laminated structure. The conductive layer 243a includes a conductive layer 243a1 formed to fit the shape of the opening and a conductive layer 243a2 formed inside the conductive layer 243a1. The conductive layer 243b includes a conductive layer 243b1 formed to fit the shape of the opening and a conductive layer 243b2 formed inside the conductive layer 243b1.

[0208] The conductive layer 243a1 and the conductive layer 243b1 can be formed as a single layer or a stacked layer using a conductive material applicable to the conductive layer 205_1. By providing the conductive layer 243a1 and the conductive layer 243b1, impurities such as water and hydrogen can be prevented from entering the semiconductor layer 230 through the conductive layer 243a2 and the conductive layer 243b2. Note that the conductive layer 243a2 and the conductive layer 243b2 may be formed using a conductive material applicable to the conductive layer 243a and the conductive layer 243b.

[0209] 4B, the height of the upper surfaces of the conductive layers 243a and 243b is the same as the height of the upper surface of the insulating layer 285. As shown in FIG. 5, the lower part of the conductive layer 243a may be formed so as to be embedded in the conductive layer 242a. Similarly, the lower part of the conductive layer 243b may be formed so as to be embedded in the conductive layer 242b.

[0210] The insulating layers 241a and 241b may be barrier insulating layers applicable to the insulating layer 275 or the like. For example, silicon nitride may be used for the insulating layers 241a and 241b. The insulating layers 241a and 241b are provided in contact with the insulating layers 285, 283, 282, and 275. This can prevent impurities such as water and hydrogen contained in the insulating layer 280 or the like from being mixed into the semiconductor layer 230 through the conductive layers 243a and 243b. Silicon nitride is particularly suitable because it has a high barrier property against hydrogen. Furthermore, oxygen contained in the insulating layer 280 can be prevented from being absorbed by the conductive layers 243a and 243b.

[0211] The insulating layer 241 a and the insulating layer 241 b may have a stacked structure. In this case, a first insulating layer in contact with an inner wall of an opening such as the insulating layer 280 and a second insulating layer therein are preferably formed by combining a barrier insulating layer against oxygen and a barrier insulating layer against hydrogen.

[0212] 3A and 3B , in one embodiment of the present invention, a semiconductor layer (semiconductor layer 230_a) including a channel formation region of the transistor 200 used in the transistors (transistors M11 and M13) provided in the layer Lta may use different materials from a semiconductor layer (semiconductor layer 230_b) including a channel formation region of the transistor 200 used in the transistors (transistors M12 and M14) provided in the layer Ltb. This allows the transistors M11 and M13 to have different characteristics from the transistors M12 and M14. For example, the semiconductor layer 230_a and the semiconductor layer 230_b may use oxide semiconductors containing different elements or having different compositions. For example, the semiconductor layer 230_a and the semiconductor layer 230_b may use oxide semiconductors having different indium contents. As a result, the transistors M11 and M13 can be OS transistors with different characteristics from the transistors M12 and M14.

[0213] The composition of an oxide semiconductor can be analyzed by, for example, energy dispersive X-ray spectrometry (EDX), X-ray photoelectron spectrometry (XPS), inductively coupled plasma mass spectrometry (ICP-MS), or inductively coupled plasma atomic emission spectrometry (ICP-AES). Alternatively, a combination of these techniques may be used for the analysis.

[0214] As described above, in the semiconductor device 100, for example, the off-state current of each of the transistors M11 and M13 may be smaller than the off-state current of each of the transistors M12 and M14. Also, for example, the on-state current of each of the transistors M12 and M14 may be larger than the on-state current of each of the transistors M11 and M13. That is, for example, the field-effect mobility of each of the transistors M12 and M14 may be higher than the field-effect mobility of each of the transistors M11 and M13.

[0215] Based on these technical concepts, for example, the indium content in the semiconductor layer 230_b may be higher than the indium content in the semiconductor layer 230_a. For example, an oxide containing indium and zinc (such as IGZO) may be used for the semiconductor layer 230_a, and indium oxide may be used for the semiconductor layer 230_b.

[0216] This allows the hole mobility of the semiconductor layer 230_b to be higher than that of the semiconductor layer 230_a. Therefore, the field-effect mobility of transistors (transistors M12 and M14) including the semiconductor layer 230_b in their channel formation regions can be higher than that of transistors (transistors M11 and M13) including the semiconductor layer 230_a in their channel formation regions. That is, the on-state current of the transistors (transistors M12 and M14) including the semiconductor layer 230_b in their channel formation regions can be higher than the on-state current of the transistors (transistors M11 and M13) including the semiconductor layer 230_a in their channel formation regions.

[0217] Furthermore, when the semiconductor layer 230_a contains an element such as gallium in addition to indium, the band gap can be made larger than that of the semiconductor layer 230_b. Therefore, the off-state current of the transistors (transistors M11 and M13) including the semiconductor layer 230_a in their channel formation regions can be made smaller than the off-state current of the transistors (transistors M12 and M14) including the semiconductor layer 230_b in their channel formation regions.

[0218] In one embodiment of the present invention, the gate insulating film of the transistor 200 provided in the layer Lta (the transistors M11 and M13) may have a different dielectric constant from that of the transistor 200 provided in the layer Ltb (the transistors M12 and M14). Furthermore, the gate insulating film of the transistor 200 provided in the layer Lta (the transistors M11 and M13) may have a different thickness from that of the transistor 200 provided in the layer Ltb (the transistors M12 and M14). This allows the transistors M11 and M13 to have different characteristics from those of the transistors M12 and M14.

[0219] As described above, in the semiconductor device 100, for example, the gate capacitance of each of the transistors M11 and M13 may be smaller than the gate capacitance of the transistor M12. Furthermore, for example, the dielectric constant of the gate insulating film of each of the transistors M11 and M13 may be smaller than the dielectric constant of the gate insulating film of the transistor M12. Furthermore, for example, the thickness of the gate insulating film of each of the transistors M11 and M13 may be larger than the thickness of the gate insulating film of the transistor M12.

[0220] Based on these technical concepts, for example, the dielectric constant of the gate insulating film of the transistor 200 applied to the transistors (transistors M11 and M13) provided in the layer Lta may be smaller than the dielectric constant of the gate insulating film of the transistor 200 applied to the transistors (transistors M12 and M14) provided in the layer Ltb. Also, for example, as shown in FIG. 7 , the thickness of the gate insulating film of the transistor 200 applied to the transistors (transistors M11 and M13) provided in the layer Lta may be larger than the thickness of the gate insulating film of the transistor 200 applied to the transistors (transistors M12 and M14) provided in the layer Ltb.

[0221] In one embodiment of the present invention, the channel lengths of the transistors M11 to M14 may be different from each other, thereby allowing the transistors M11 to M14 to have different characteristics.

[0222] As described above, it is preferable that the transistor M12 has high saturation because it functions as an amplifying element in the semiconductor device 100. Therefore, in order to increase the saturation of the transistor M12, for example, the channel length of the transistor M12 may be increased.

[0223] Based on these technical concepts, for example, as shown in FIG. 8, the channel length of the transistor M12 may be made longer than the channel lengths of the transistors M11, M13, and M14.

[0224] [Modification 1] FIG. 9 shows a modification of the stacked structure shown in FIG. 3, which differs in that the capacitive element C11 is provided in the layer Lta.

[0225] In the layer Lta, an insulating layer 292 is provided to cover the conductive layer 248_a having a region functioning as the node FD. A conductive layer 293 having a region functioning as the wiring VL2 is provided over part of the insulating layer 292. The conductive layer 293 is connected to the conductive layer 294 having a region functioning as the wiring VL2, the conductive layer 248_a, and the like. In a region where the conductive layer 248_a having a region functioning as the node FD and the conductive layer 293 having a region functioning as the wiring VL2 overlap with each other, the conductive layer 248_a has a region functioning as one terminal (also referred to as one electrode) of the capacitor C11, the conductive layer 293 has a region functioning as the other terminal (also referred to as the other electrode) of the capacitor C11, and the insulating layer 292 has a region functioning as a dielectric of the capacitor C11.

[0226] 10 is a modification of the stacked structure shown in FIG. 3 , which differs in that the transistors M11 and M14 are provided in a layer Lta and the transistors M12 and M13 are provided in a layer Ltb. Another difference is that each of the transistors M11 to M14 has an island-shaped semiconductor layer.

[0227] In the layer Lta, different materials can be used for the semiconductor layer (semiconductor layer 230_a1) including the channel formation region of the transistor 200 used in the transistor M11 and the semiconductor layer (semiconductor layer 230_a2) including the channel formation region of the transistor 200 used in the transistor M14. This allows the transistors M11 and M14 to have different characteristics. For example, the semiconductor layer 230_a1 and the semiconductor layer 230_a2 may use oxide semiconductors containing different elements or having different compositions. For example, the semiconductor layer 230_a1 and the semiconductor layer 230_a2 may use oxide semiconductors with different indium contents. This allows the transistors M11 and M14 to have different characteristics as OS transistors.

[0228] Furthermore, in the layer Ltb, different materials may be used for the semiconductor layer (semiconductor layer 230_b1) including the channel formation region of the transistor 200 used in the transistor M12 and the semiconductor layer (semiconductor layer 230_b2) including the channel formation region of the transistor 200 used in the transistor M13. This allows the transistors M12 and M13 to have different characteristics. For example, the semiconductor layer 230_b1 and the semiconductor layer 230_b2 may use oxide semiconductors containing different elements or having different compositions. For example, the semiconductor layer 230_b1 and the semiconductor layer 230_b2 may use oxide semiconductors with different indium contents. This allows the transistors M12 and M13 to have different characteristics as OS transistors.

[0229] Based on the above technical concept, one embodiment of the present invention may be configured such that the indium content in the semiconductor layer 230_a2 is higher than the indium content in the semiconductor layer 230_a1. For example, an oxide containing indium and zinc (such as IGZO) may be used for the semiconductor layer 230_a1, and indium oxide may be used for the semiconductor layer 230_a2. Alternatively, for example, the indium content in the semiconductor layer 230_b1 may be higher than the indium content in the semiconductor layer 230_b2. For example, an oxide containing indium and zinc (such as IGZO) may be used for the semiconductor layer 230_b2, and indium oxide may be used for the semiconductor layer 230_b1.

[0230] As one embodiment of the present invention, two or more of the stacked structures illustrated or not illustrated above can be applied to the semiconductor device 100 .

[0231] <Configuration Example 3 of Semiconductor Device> Next, an example of a stacked structure when the semiconductor device 100 is used in an imaging device will be described.

[0232] 11 illustrates a layer Lop and a layer Ltc in addition to the stacked structure shown in FIG. 3A. The layer Lop is disposed below the layer Lpd. The layer Ltc is disposed above the layer Ltb.

[0233] [Layer Lop] The layer Lop has a light-shielding layer 451, an optical filter 450, and a microlens array 455. The layer Lop can also be referred to as an optical conversion layer. As indicated by the dotted arrow in Figure 11, light (Light) incident on the semiconductor device 100 is irradiated onto the light-receiving element PD provided on the layer Lpd via the microlens array 455 and the optical filter 450 included in the layer Lop.

[0234] The light-shielding layer 451 can prevent light from flowing into adjacent pixels. A metal layer such as aluminum or tungsten can be used for the light-shielding layer 451. The metal layer may also be stacked with a dielectric film that functions as an anti-reflection film.

[0235] For example, a color filter can be used as the optical filter 450. When the semiconductor device 100 is used in an imaging device, a color image can be obtained by assigning color filters of colors such as R (red), G (green), B (blue), Y (yellow), C (cyan), and M (magenta) to each pixel.

[0236] Furthermore, for example, if a wavelength cut filter is used as the optical filter 450, an imaging device can be provided that can obtain images in various wavelength regions.

[0237] Furthermore, for example, if a filter that blocks light having wavelengths equal to or shorter than visible light is used as the optical filter 450, an infrared imaging device can be realized. Furthermore, for example, if a filter that blocks light having wavelengths equal to or shorter than near-infrared light is used as the optical filter 450, a far-infrared imaging device can be realized. Furthermore, for example, if a filter that blocks light having wavelengths equal to or longer than visible light is used as the optical filter 450, an ultraviolet imaging device can be realized.

[0238] Furthermore, for example, if a scintillator is used for the optical filter 450, an imaging device can be used in an X-ray imaging device or the like to obtain an image that visualizes the intensity of radiation. When radiation such as X-rays that has passed through a subject is incident on the scintillator, it is converted into light (fluorescence) such as visible light or ultraviolet light by the photoluminescence phenomenon. Then, image data can be obtained by detecting this light with the light receiving element PD. An imaging device having this configuration may also be used in a radiation detector or the like.

[0239] The scintillator includes a substance that absorbs the energy of radiation such as X-rays or gamma rays and emits visible light or ultraviolet light when irradiated with the radiation. ２ O ２ S: Tb, Gd ２ O ２ S: Pr, Gd ２ O ２ S: Eu, BaFCl: Eu, NaI, CsI, CaF ２ , BaF ２ , CeF ３ , LiF, LiI, ZnO, etc. dispersed in resin or ceramics can be used.

[0240] A microlens array 455 is provided to cover the optical filter 450. By providing the microlens array 455, condensed light can be irradiated onto the light-receiving element PD, thereby enabling efficient photoelectric conversion in the light-receiving element PD. The microlens array 455 is preferably formed from a resin or glass that is highly transmissive to visible light.

[0241] [Layer Lop] The layer Ltc includes a transistor 310. The transistor 310 can be used as a transistor that forms a driver circuit, a readout circuit, or the like in an imaging device using the semiconductor device 100, for example.

[0242] The transistor 310 will now be described.

[0243] As shown in Figures 12A and 12B, the transistor 310 is provided over a substrate 311 and includes a conductive layer 316 that functions as a gate electrode, an insulating layer 315 that functions as a gate insulating film, a semiconductor region 313 that functions as a channel formation region, a low-resistance region 314a that functions as one of the source region and the drain region, and a low-resistance region 314b that functions as the other of the source region and the drain region.

[0244] The transistor 310 also has an element isolation layer 318 buried in the substrate 311. The element isolation layer 318 is provided between two adjacent transistors 310.

[0245] The substrate 311 may be, for example, a semiconductor substrate. Examples of the semiconductor substrate include a semiconductor substrate made of silicon, germanium, or the like, or a compound semiconductor substrate made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. Other examples include a semiconductor substrate having an insulator region inside the semiconductor substrate, such as an SOI (Silicon On Insulator) substrate. Other examples include a substrate in which a semiconductor is provided on an insulator substrate, or a substrate in which a semiconductor is provided on a conductor substrate. The semiconductor substrate may be a single-crystal semiconductor or a polycrystalline semiconductor.

[0246] In this embodiment, a case where a single crystal silicon substrate is used as the substrate 311 will be described as an example.

[0247] When a single crystal silicon substrate is used as the substrate 311, the transistor 310 can be said to be a Si transistor (a transistor including silicon in a channel formation region).

[0248] The transistor 310 may be either a p-channel type or an n-channel type. For example, by connecting the gate of an n-channel transistor 310 and the gate of a p-channel transistor 310, a CMOS circuit (e.g., a circuit that operates complementarily, a CMOS logic gate, or a CMOS logic circuit) can be configured.

[0249] 12B , the transistor 310 can have a so-called Fin structure in which the top surface and the side surfaces in the channel width direction of a semiconductor region 313 made of a part of a substrate 311 are covered with a conductive layer 316 via an insulating layer 315. This increases the effective channel width, thereby improving the on-state characteristics of the transistor 310. Furthermore, the contribution of the electric field of the gate electrode can be increased, thereby improving the off-state characteristics of the transistor 310.

[0250] Here, the shortest distance between the low-resistance region 314 a and the low-resistance region 314 b in the semiconductor region 313 in the substrate 311 can be defined as the channel length of the transistor 310. Also, the length of the portion of the semiconductor region 313 in the substrate 311 where the low-resistance region 314 a and the low-resistance region 314 b face each other can be defined as the channel width of the transistor 310. For example, in the semiconductor region 313 shown in FIG. 12B , the length of the top surface and the side surface in the channel width direction of the region covered with the conductive layer 316 via the insulating layer 315 may be defined as the channel width of the transistor 310.

[0251] The transistor 310 preferably includes a semiconductor such as a silicon-based semiconductor, and preferably includes single crystal silicon, in the region where the channel of the semiconductor region 313 is formed, the region nearby the region, the low-resistance region 314a that serves as one of the source and drain regions, and the low-resistance region 314b that serves as the other of the source and drain regions. Alternatively, the transistor 310 may be formed of a material containing, for example, germanium, silicon germanium, gallium arsenide, or gallium aluminum arsenide. Alternatively, the transistor 310 may be configured using silicon whose effective mass is controlled by applying stress to the crystal lattice to change the lattice spacing. Alternatively, the transistor 310 may be a high electron mobility transistor (HEMT) using, for example, gallium arsenide, gallium aluminum arsenide, or the like.

[0252] The low resistance region 314a and the low resistance region 314b contain, in addition to the semiconductor material applied to the semiconductor region 313, an element that imparts n-type conductivity, such as arsenic or phosphorus, or an element that imparts p-type conductivity, such as boron.

[0253] For example, a semiconductor material such as silicon containing an element that imparts n-type conductivity, such as arsenic or phosphorus, or an element that imparts p-type conductivity, such as boron, can be used as the conductive layer 316. Alternatively, for example, a conductive material such as a metal material, an alloy material, or an oxide material can be used.

[0254] Note that the work function is determined by the material of a conductor; therefore, the threshold voltage of a transistor can be adjusted by selecting the material of the conductor.

[0255] For example, a material such as titanium nitride or tantalum nitride is preferably used as the conductive layer 316. Furthermore, in order to achieve both conductivity and embeddability, it is preferable to use a stack of metal materials such as tungsten or aluminum. In particular, in terms of heat resistance, it is preferable to use a stack of tungsten, for example.

[0256] An insulating layer 320 , an insulating layer 322 , an insulating layer 324 , and an insulating layer 326 are stacked in this order to cover the transistor 310 .

[0257] For example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, or aluminum nitride is preferably used for the insulating layer 320, the insulating layer 322, the insulating layer 324, and the insulating layer 326. In particular, silicon oxide or silicon oxynitride is preferably used because of its thermal stability.

[0258] In this specification, silicon oxynitride refers to a material whose composition contains more oxygen than nitrogen, silicon nitride oxide refers to a material whose composition contains more nitrogen than oxygen, aluminum oxynitride refers to a material whose composition contains more oxygen than nitrogen, and aluminum nitride oxide refers to a material whose composition contains more nitrogen than oxygen.

[0259] The insulating layer 322 may function as a planarizing film that planarizes steps caused by the transistor 310 or the like provided thereunder. For example, the top surface of the insulating layer 322 may be planarized by planarization treatment using a chemical mechanical polishing (CMP) method or the like to improve the planarity.

[0260] As the insulating layer 324, it is preferable to use an insulator having barrier properties that prevent impurities such as hydrogen from diffusing from the substrate 311 or the transistor 310, which are located below the insulating layer 324, to a region located above the insulating layer 324.

[0261] The insulator having a barrier property against hydrogen can be, for example, silicon nitride formed by chemical vapor deposition (CVD), or a metal oxide such as aluminum oxide, hafnium oxide, or tantalum oxide.

[0262] The insulating layer 326 preferably has a lower dielectric constant than the insulating layer 324. For example, the relative dielectric constant of the insulating layer 326 is preferably less than 4, and more preferably less than 3. Furthermore, for example, the relative dielectric constant of the insulating layer 326 is preferably 0.7 times or less, and more preferably 0.6 times or less, the relative dielectric constant of the insulating layer 324. By using a material with a low dielectric constant as the interlayer film, it is possible to reduce the parasitic capacitance that occurs between wirings.

[0263] Conductive layers 328 (such as conductive layers 328a and 328b) are embedded in the insulating layers 320 and 322. Conductive layers 330 (such as conductive layers 330a and 330b) are embedded in the insulating layers 324 and 326.

[0264] The conductive layer 328 and the conductive layer 330 each function as a plug or a wiring. A wiring layer may be provided over the insulating layer 326 and the conductive layer 330.

[0265] Note that the transistor 310 illustrated in FIGS. 12A and 12B is just an example, and the present invention is not limited to this configuration.

[0266] [Bonding] Next, bonding of the layer Ltb and the layer Ltc will be described with reference to FIG.

[0267] As described above, the semiconductor device 100 that can be used as a pixel of an imaging device is arranged on a silicon substrate, including a layer Lpd on which a light-receiving element PD is provided, a layer Lta on which transistors M11 and M13 are provided, and a layer Ltb on which transistors M12 and M14 are provided. Furthermore, the driving circuit, readout circuit, and the like of the imaging device are arranged on a layer Ltc having a transistor 310 provided on a substrate 311 separate from the silicon substrate. Thus, as shown in FIG. 11 , the layer Ltb and the layer Ltc are bonded together, thereby enabling the semiconductor device 100 and the driving circuit, readout circuit, and the like to be connected to each other. The stacked structure shown in FIG. 11 can also be described as a bond between a silicon substrate located on the layer Lpd, on which the layer Lta and the layer Ltb are stacked in this order, and a substrate 311 located on the layer Ltc.

[0268] An insulating layer 431 and a conductive layer 432 are provided on the surface (upper surface in the drawing) of the layer Ltb. The conductive layer 432 has regions buried in the insulating layer 431 and the insulating layer 288. The surfaces (upper surface in the drawing) of the insulating layer 431 and the conductive layer 432 are flattened so that they are at the same height. The conductive layer 432 has a region in contact with the conductive layer 248_b.

[0269] An insulating layer 433 and a conductive layer 434 are provided on the surface (the lower surface in the drawing) of the layer Ltc. The conductive layer 434 has regions buried in the insulating layer 433 and the insulating layer 326. The surfaces (the lower surfaces in the drawing) of the insulating layer 433 and the conductive layer 434 are flattened so that they are at the same height. The conductive layer 434 has a region in contact with the conductive layer 330.

[0270] Here, the conductive layers 432 and 434 preferably contain the same metal element as a main component, and the insulating layers 431 and 433 preferably contain the same component as a main component.

[0271] For example, Cu, Al, Sn, Zn, W, Ag, Pt, Au, or the like can be used for the conductive layers 432 and 434. Cu, Al, W, or Au is preferably used because of ease of bonding. Furthermore, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, or the like can be used for the insulating layers 431 and 433.

[0272] That is, the same metal material as described above is preferably used for the conductive layer 432 and the conductive layer 434. The same insulating material as described above is preferably used for the insulating layer 431 and the insulating layer 433. With this structure, bonding can be performed at a bonding position (also referred to as a bonding surface) between a surface of the layer Ltb (the upper surface in the drawing) and a surface of the layer Ltc (the lower surface in the drawing).

[0273] Note that the conductive layer 432 and the conductive layer 434 may each have a multilayer structure of multiple conductive layers, in which case the conductive layers serving as bonding surfaces may be made of the same metal material. The insulating layer 431 and the insulating layer 433 may each have a multilayer structure of multiple insulating layers, in which case the insulating layers serving as bonding surfaces may be made of the same insulating material.

[0274] This bonding allows electrical signals to be exchanged or potential interactions to occur between the conductive layers 432 and 434. Furthermore, the insulating layers 431 and 433 can be connected to each other with sufficient mechanical strength.

[0275] Here, to bond metal layers together, a surface activated bonding method can be used, in which oxide films and impurity adsorption layers on the bonding surfaces are removed by sputtering or other methods, and the cleaned and activated bonding surfaces are then brought into contact and bonded. Alternatively, a diffusion bonding method can be used, in which bonding surfaces are bonded using a combination of temperature and pressure. Both methods result in bonding at the atomic level, resulting in excellent mechanical bonding.

[0276] Furthermore, to bond insulating layers together, hydrophilic bonding can be used, in which high flatness is achieved by polishing or other methods, and then the bonding surfaces are brought into contact with each other after being hydrophilically treated with oxygen plasma or other methods to form a temporary bond, and then the final bond is achieved by dehydrating them through heat treatment.Hydrophilic bonding also creates bonds at the atomic level, so it is possible to obtain mechanically excellent bonds.

[0277] When the layer Ltb and the layer Ltc are bonded to each other, an insulating layer and a metal layer are mixed on each bonding surface, and therefore, for example, a surface activated bonding method and a hydrophilic bonding method may be combined.

[0278] For example, a method can be used in which the bonding surfaces are cleaned after polishing, and the bonding surfaces of the metal layers are subjected to an anti-oxidation treatment, followed by a hydrophilic treatment before bonding. Alternatively, the bonding surfaces of the metal layers may be made of a resistant metal such as Au and then subjected to a hydrophilic treatment. Note that bonding methods other than those described above may also be used.

[0279] By the above-described bonding, the conductive layer 248 — b included in the layer Ltb and the conductive layer 330 included in the layer Ltc are connected to each other via the conductive layer 432 and the conductive layer 434 .

[0280] [Modification 1] Note that the layered structure when the semiconductor device 100 is used in an imaging device is not limited to the layered structure shown in FIG. 11 described above, and various layered structures can be used.

[0281] The stacked structure shown in FIG. 13 is a modified example of the stacked structure shown in FIG. 11 . The stacked structure shown in FIG. 13 differs mainly in that the conductive layer 248_a of the layer Lta is connected to the semiconductor region 444 and the semiconductor region 443 of the layer Lpd via the conductive layer 432 and the conductive layer 434 due to the bonding of the layer Lta and the layer Lpd. Another difference is that the conductive layer 218_a of the layer Lta is connected to the conductive layer 248_b of the layer Ltb via the conductive layer 208_a. Another difference is that the conductive layer 218_b of the layer Ltb is connected to the conductive layer 330 of the layer Ltc via the conductive layer 208_b. The stacked structure shown in FIG. 13 can also be said to be a bonding of a silicon substrate located in the layer Lpd and a substrate 311 located in the layer Ltc, which is formed by stacking the layer Ltb and the layer Lta in this order.

[0282] [Variation 2] The stacked structure shown in Figure 14 is a variation of the stacked structure shown in Figure 11. The stacked structure shown in Figure 14 differs mainly in that, by bonding the layer Lta and the layer Ltb together, the conductive layer 248_a of the layer Lta and the conductive layer 248_b of the layer Ltb are connected to each other via the conductive layer 432 and the conductive layer 434. Another difference is that the conductive layer 218_b of the layer Ltb and the conductive layer 330 of the layer Ltc are connected to each other via the conductive layer 208_b. The stacked structure shown in Figure 14 can also be said to be a bonding of a silicon substrate located on the layer Lpd on which the layer Lta is laminated, and a substrate 311 located on the layer Ltc on which the layer Ltb is laminated.

[0283] [Variation 3] The stacked structure shown in Fig. 15 is a variation of the stacked structure shown in Fig. 13. The stacked structure shown in Fig. 15 differs mainly in the configuration of the light-receiving element PD provided in the layer Lpd. Another difference is that no bonding is performed.

[0284] In one embodiment of the present invention, a photodiode including an organic photoelectric conversion material (also referred to as an organic photodiode) can be used as the light-receiving element PD instead of a Si photodiode. The light-receiving element PD shown in FIG. 15 includes a conductive layer 411, a functional layer 412, a photoelectric conversion layer 413, a functional layer 414, and a conductive layer 415.

[0285] 15 , a conductive layer 411 is provided so as to cover a part of the insulating layer 416 and to have a region in contact with the conductive layer 248_a through the insulating layer 416 and the opening provided in the insulating layer 288. Here, the conductive layer 411 in contact with the conductive layer 248_a having a region functioning as the node SN is referred to as the conductive layer 411(SN), and the conductive layer 411 in contact with the conductive layer 248_a having a region functioning as the wiring VL1 is referred to as the conductive layer 411(VL1). An insulating layer 417 is provided so as to cover the insulating layer 416, the conductive layer 411(SN), and the conductive layer 411(VL1). An opening reaching the conductive layer 411(SN) is provided in the insulating layer 417 in a region overlapping with the conductive layer 411(SN). Furthermore, an opening reaching the conductive layer 411(VL1) is provided in the insulating layer 417 in a region overlapping with the conductive layer 411(VL1). The functional layer 412, the photoelectric conversion layer 413, and the functional layer 414 are stacked in this order so as to cover a portion of the insulating layer 417 and the conductive layer 411(SN). An insulating layer 418 is provided so as to cover the remaining portion of the insulating layer 417 and portions of the functional layer 412, the photoelectric conversion layer 413, and the functional layer 414. A conductive layer 415 is provided so as to cover the functional layer 414, the insulating layer 418, and the conductive layer 411(VL1). An insulating layer 419 is provided so as to cover the conductive layer 415.

[0286] The insulating layer 416 can function as a protective film. The insulating layer 417 can have a function of insulating adjacent conductive layers from each other and a function of insulating adjacent light-receiving elements PD from each other. The insulating layer 418 can function as a protective film. The insulating layer 419 can function as an interlayer insulating film and a planarizing film.

[0287] In the region where the conductive layer 411 (SN), the functional layer 412, the photoelectric conversion layer 413, the functional layer 414, and the conductive layer 415 overlap, the conductive layer 411 (SN) corresponds to one terminal of the light receiving element PD, and the conductive layer 415 corresponds to the other terminal of the light receiving element PD.

[0288] One of the functional layer 412 and the functional layer 414 can function as a hole transport layer, and the other of the functional layer 412 and the functional layer 414 can function as an electron transport layer. One of the conductive layer 411 and the conductive layer 415 can function as a pixel electrode, and the other of the conductive layer 411 and the conductive layer 415 can function as a common electrode.

[0289] The hole transport layer (one of the functional layers 412 and 414) may be made of, for example, molybdenum oxide. The electron transport layer (the other of the functional layers 412 and 414) may be made of, for example, C ６０ , C ７０ or derivatives thereof can be used.

[0290] The photoelectric conversion layer 413 may be a mixed layer (bulk heterojunction structure) of an n-type organic semiconductor and a p-type organic semiconductor.

[0291] In the laminated structure shown in FIG. 15, bonding is not necessary.

[0292] [Variation 4] The stacked structure shown in Fig. 16 is a variation of the stacked structure shown in Fig. 11. The stacked structure shown in Fig. 16 differs mainly in that the transistor 300 is provided in the layer Lpd. It also differs in that it does not have the layer Ltc. It also differs in that bonding is not performed.

[0293] Furthermore, the conductive layer 218_a included in the layer Lta and the conductive layer 330 included in the layer Lpd are connected to each other via the conductive layer 208_a. Furthermore, in the layer Lpd, the conductive layer 330 is connected to each of the semiconductor region 444 and the semiconductor region 443 via the conductive layer 328.

[0294] The transistor 300 is a modified example of the transistor 310 and has a so-called planar configuration.

[0295] The above-described transistor 200 may be provided in each of the layer Lta and the layer Ltb in the region where the transistor 300 is provided. These transistors can be used as transistors constituting a driver circuit, a readout circuit, or the like in an imaging device using the semiconductor device 100, for example.

[0296] Note that, as one embodiment of the present invention, two or more of the stacked structures illustrated or not illustrated above can be applied to an imaging device using the semiconductor device 100 .

[0297] <Configuration Example of Imaging Device> Next, an imaging device according to one embodiment of the present invention will be described with reference to the drawings. At least part of the semiconductor device according to one embodiment of the present invention can be used in the imaging device.

[0298] FIG. 17A is a block diagram illustrating an example of the configuration of an imaging device 160 according to one embodiment of the present invention.

[0299] 17A , the imaging device 160 includes a pixel unit 162, a drive circuit 163, and a readout circuit 164. The pixel unit 162 includes a plurality of pixels 161 arranged in a matrix of m rows and n columns (m is an integer of 2 or greater, and n is an integer of 2 or greater), for example. The pixel unit 162 can also be referred to as an image sensor.

[0300] The pixel 161 may include a light receiving element. Note that the pixel 161 may include both a display element and a light receiving element. In this case, the imaging device 160 can have the functions of both a display device and an imaging device.

[0301] 17A, the pixel 161 arranged in the first row and first column is indicated as pixel 161[1,1], the pixel 161 arranged in the first row and nth column is indicated as pixel 161[1,n], the pixel 161 arranged in the mth row and first column is indicated as pixel 161[m,1], and the pixel 161 arranged in the mth row and nth column is indicated as pixel 161[m,n]. Note that the pixel 161 arranged in the uth row and vth column (u is an integer of 1 to m, and v is an integer of 1 to n) may be indicated as pixel 161[u,v]. Note that when describing matters common to each of a plurality of pixels 161, they may be described without the use of identifying symbols such as "[u,v]".

[0302] The imaging device 160 also has m wires 165 arranged in parallel and whose potentials are controlled by a circuit included in a driver circuit 163. The potential of one wire 165 is applied to n pixels 161 arranged in the row direction. Note that a configuration may be adopted in which one wire 165 includes multiple wires in accordance with the configuration of the pixel 161.

[0303] The imaging device 160 also has n wires 166 that are arranged in parallel and whose potentials are controlled by a circuit included in a readout circuit 164. The potential of one wire 166 is applied to m pixels 161 arranged in the column direction. Note that a configuration may be adopted in which one wire 166 includes multiple wires in accordance with the configuration of the pixel 161.

[0304] The driving circuit 163 can include, for example, a horizontal scanning circuit (sometimes called a scan driver or a row driver).

[0305] The readout circuit 164 may include, for example, a current-to-voltage conversion circuit, a correlated double sampling circuit, an analog-to-digital conversion circuit, a parallel-to-serial conversion circuit, and a vertical scanning circuit (sometimes called a data driver or a column driver).

[0306] FIG. 17B is a block diagram illustrating a modified example of the imaging device 160. The imaging device 160 shown in FIG. 17B differs from the imaging device 160 shown in FIG. 17A in that it has two drive circuits 163 arranged to face each other across the pixel portion 162. In the configuration shown in FIG. 17B, the potentials of m wirings 165 are controlled by the two drive circuits 163. By using such a configuration, for example, the substantial wiring load (parasitic capacitance and parasitic resistance) can be reduced to one-fourth of the wiring load in the imaging device 160 shown in FIG. 17A. Therefore, the imaging device 160 can achieve at least one of higher speed, higher definition, higher resolution, and smaller size.

[0307] Note that in one embodiment of the present invention, various transistors can be used as transistors included in the imaging device 160. For example, a Si transistor (a transistor including silicon in a channel formation region) may be used, an OS transistor (a transistor including an oxide semiconductor in a channel formation region) may be used, or both a Si transistor and an OS transistor may be used.

[0308] OS transistors can be easily integrated because they can be freely arranged on, for example, a silicon substrate on which Si transistors are provided. Furthermore, OS transistors can be manufactured at low cost because they can be manufactured using the same manufacturing equipment as Si transistors.

[0309] Therefore, in the imaging device 160, for example, Si transistors including part of a silicon substrate may be used as transistors forming the driver circuit 163 and the readout circuit 164, and OS transistors provided over a silicon substrate may be used as transistors forming the pixel portion 162. Note that OS transistors may be used as at least some of the transistors forming the driver circuit 163 and the readout circuit 164.

[0310] In one embodiment of the present invention, at least a part of the above-described semiconductor device 100 can be used in the pixel 161. Furthermore, at least a part of the above-described transistor 200, transistor 300, transistor 310, or the like can be used in each of the driver circuit 163 and the readout circuit 164.

[0311] [Readout Circuit] FIG. 18 is a circuit diagram illustrating an example of a readout circuit.

[0312] The readout circuit 470 shown in FIG. 18 includes, for example, a current-voltage conversion circuit 471, a correlated double sampling circuit 472, and an analog-to-digital conversion circuit 473.

[0313] The current-voltage conversion circuit 471 includes, for example, a transistor M41. The correlated double sampling circuit 472 includes, for example, a transistor M42, a transistor M43, a capacitance element C41, and a capacitance element C42.

[0314] As shown in FIG. 18 , one of the source or drain of transistor M41 is connected to a wiring WX. The other terminal of the capacitor C41 is connected to one of the source or drain of transistor M42 and one of the source or drain of transistor M43. The other of the source or drain of transistor M43 is connected to one terminal of the capacitor C42. The other of the source or drain of transistor M43 is connected to an input terminal of an analog-to-digital conversion circuit 473. The output terminal of the analog-to-digital conversion circuit 473 is connected to a wiring DOL. The other of the source or drain of transistor M41 is connected to a wiring VL41. The gate of transistor M41 is connected to a wiring NL41. The other of the source or drain of transistor M42 is connected to a wiring VL42. The gate of transistor M42 is connected to a wiring NL42. The gate of transistor M43 is connected to a wiring NL43. The other terminal of the capacitance element C42 is connected to the line VL43.

[0315] The configuration shown in FIG. 18 is an example, and other configurations may be used.

[0316] Here, a circuit configured with the transistor M12 included in the semiconductor device 100 and the transistor M41 included in the current-voltage conversion circuit 471 can function as a source follower. In this case, the transistor M41 functions as a constant current source that supplies a constant drain current. This allows a potential corresponding to the potential of the node FD in the semiconductor device 100 to be output to the wiring WX.

[0317] [Operation Example] Next, the operation of the imaging device 160 will be described. Here, an example of the operation of the pixel 161 will be described in a case where the semiconductor device 100 shown in either FIG. 2A or FIG. 2B is used as the pixel 161 and the readout circuit 470 shown in FIG. 18 is used as the readout circuit 164. FIG. 19 is a timing chart illustrating an example of the operation of the pixel 161. Note that in the explanation of the timing chart, a high potential is represented by "H" and a low potential is represented by "L". It is assumed that "L" is always supplied to the wiring VL1 and "H" is always supplied to the wiring VL2.

[0318] In the period T41, when the potential of the wiring RS is set to "H", the potential of the wiring TX is set to "H", and the potential of the wiring SE is set to "L", the transistors M11 and M13 are each turned on, and the potential of the wiring VL2 is supplied to the node FD at "H" (also referred to as a reset operation).

[0319] In the period T42, when the potential of the wiring RS is set to "L", the potential of the wiring TX is set to "H", and the potential of the wiring SE is set to "L", the transistor M13 is turned off, and the supply of the potential to the wiring VL2 is cut off. Then, in accordance with the intensity of light irradiated to the light-receiving element PD, a current flows from the node FD to the wiring VL1 through the transistor M11 and the light-receiving element PD, and the potential of the node FD gradually decreases (also referred to as an accumulation operation).

[0320] In the period T43, when the potential of the wiring RS is set to "L", the potential of the wiring TX is set to "L", and the potential of the wiring SE is set to "L", the transistor M11 is turned off, and the potential of the node FD is held (also referred to as a holding operation). At this time, by using OS transistors with low off-state current for the transistors M11 and M13 connected to the node FD, charge flow into or out of the node FD can be suppressed, and the data holding time can be extended.

[0321] In the period T44, when the potential of the wiring RS is set to "L", the potential of the wiring TX is set to "L", and the potential of the wiring SE is set to "H", the transistor M14 is turned on, and the source follower formed by the transistor M12 and the transistor M41 included in the read circuit 470 operates, so that the potential held in the node FD is read to the wiring WX (also referred to as a read operation).

[0322] Note that the read circuit 470 can output a signal that does not depend on the threshold voltage of the transistor M12 by using the correlated double sampling circuit 472. In the correlated double sampling circuit 472, for example, the potential held in the node FD in the period T44 is read onto the wiring WX, and then the potential of the wiring RS is set to "H" and the potential of the wiring VL2 is read onto the wiring WX. As a result, correlated double sampling is performed to read the difference between the potential held in the node FD and the potential of the wiring VL2, and a potential that does not depend on the threshold voltage of the transistor M12 is output. The potential output from the correlated double sampling circuit 472 is converted into a digital signal by the analog-to-digital conversion circuit 473, and the digital signal is output to the wiring DOL.

[0323] The digital signal output to the wiring DOL is output to the outside of the imaging device 160. At this time, the signal may be output as a parallel signal as it is, or may be output as a serial signal via a parallel-serial conversion circuit having a vertical scanning circuit or the like.

[0324] The above is an example of the operation of the imaging device 160.

[0325] Note that one embodiment of the present invention is not limited to the configuration examples, operation examples, and the like described in this embodiment. The contents of this embodiment can be implemented by combining them as appropriate. The contents of this embodiment can also be implemented by combining them as appropriate with other embodiments, etc.

[0326] Embodiment 2 In this embodiment, an indium oxide film that can be used for a semiconductor layer of a transistor according to one embodiment of the present invention will be described.

[0327] In this specification and the like, indium oxide having at least a crystalline portion or a crystalline region in a film is referred to as crystalline indium oxide (crystal IO) or crystalline indium oxide (crystalline IO). Examples of crystalline IO or crystalline IO include single-crystalline indium oxide, polycrystalline indium oxide, and microcrystalline indium oxide.

[0328] Indium oxide is a semiconductor material having physical properties that are completely different from those of oxide semiconductors such as In—Ga—Zn oxide (hereinafter also referred to as IGZO) and zinc oxide.

[0329] The carrier concentration dependence of the Hall mobility of indium oxide, silicon, and IGZO will be explained. Figure 20A shows the carrier concentration dependence of the Hall mobility of silicon (Si) and indium oxide (InO Ｘ ) and FIG. 20B is a schematic diagram showing the carrier concentration dependence of the hole mobility for IGZO.

[0330] First, IGZO tends to exhibit higher hole mobility as the carrier concentration increases, as shown by the arrows in Figure 20B. On the other hand, indium oxide tends to exhibit higher hole mobility as the carrier concentration decreases, as shown by the arrows in Figure 20A (see Non-Patent Document 1). This trend is similar to that of silicon; the lower the dopant (impurity) concentration in the material, the less impurity scattering there is and the higher the hole mobility. In other words, the higher the purity and intrinsic indium oxide, the higher the hole mobility. From these results, it can be said that indium oxide, unlike IGZO, is a material with physical properties similar to those of silicon. Note that the characteristics of indium oxide shown in Figure 20A are assumed to be single crystal. Therefore, when indium oxide is non-single crystal (e.g., polycrystalline), the characteristics may differ from those shown in Figure 20A.

[0331] 20A, the range R1 of low carrier concentration has extremely high hole mobility, and therefore can be said to be a range of carrier concentration suitable for, for example, a channel formation region of a transistor. For example, in the case of indium oxide, the range R1 is a range where the carrier concentration value is 1×10 １５ cm −３ The range includes, for example, 1×10 １４ cm −３ That's it, 1 x 10 １８ cm −３ By sufficiently reducing the carrier concentration, the Hall mobility value can be increased to 270 cm ２ It is expected that the resistance can be increased to about / (V·s).

[0332] In addition, in indium oxide, the region where the carrier concentration is in the range R1 may contain an element that lowers the carrier concentration. Examples of elements that lower the carrier concentration include magnesium, calcium, zinc, cadmium, and copper. By substituting these elements for indium, the carrier concentration can be lowered. Examples of elements that lower the carrier concentration include nitrogen, phosphorus, arsenic, and antimony. For example, by substituting nitrogen, phosphorus, arsenic, or antimony for oxygen, the carrier concentration can be lowered.

[0333] On the other hand, the range R2 with a high carrier concentration has a low electrical resistance, and can be said to be a range of carrier concentrations suitable for, for example, the source and drain regions of a transistor, a resistor, or a transparent conductive film. ２０ cm −３ The range includes, for example, 1×10 １９ cm −３ That's it, 1 x 10 ２２ cm −３ By increasing the carrier concentration sufficiently, the resistivity can be reduced to 1×10 −４ It is expected that the resistivity can be reduced to Ω·cm or less.

[0334] In the indium oxide, the region having a carrier concentration in the range R2 may contain an element that increases the carrier concentration. For example, it is preferable that the indium oxide contains an element that is common to the source electrode and the drain electrode of the transistor. Examples of elements that increase the carrier concentration include titanium, zirconium, hafnium, tantalum, tungsten, molybdenum, tin, silicon, and boron. In particular, it is more preferable to use an element whose oxide has conductive or semiconductive properties.

[0335] In this way, indium oxide uses a region with a low carrier concentration as the channel formation region of a transistor, and a region with a high carrier concentration as the source and drain regions of the transistor. In other words, indium oxide can be said to be an oxide capable of valence electron control. Note that IGZO may experience strain in the source and drain regions due to stress from electrodes in contact with the IGZO, resulting in the formation of n-type regions. On the other hand, unlike IGZO, indium oxide is capable of valence electron control, and therefore does not require strain to be formed in the film as with IGZO. Less strain in the film is expected to improve reliability. For example, by separately creating a region with a carrier concentration in the range R1 shown in FIG. 20A and a region with a carrier concentration in the range R2 in the indium oxide film, a so-called n-i-n junction (a junction between an n-type region, an i-type region, and an n-type region) can be created. Note that valence electron control in transistors using silicon is generally known. On the other hand, valence electron control in transistors using indium oxide is a novel technical concept that would not normally be conceived.

[0336] By using the above technical concept, the transistor having indium oxide in this specification and the like has two or more, preferably three or more, more preferably four or more, and most preferably five of the following characteristics (1) to (5): (1) a large on-state current (in other words, high mobility); (2) a small off-state current; (3) a normally-off state; (4) high reliability; and (5) a high cutoff frequency (fT). For example, the transistor having indium oxide in this specification and the like has high mobility, a small off-state current, and is normally-off. The transistor has high mobility and is different from a normally-on transistor.

[0337] Next, an indium oxide film applied to a transistor will be described. The indium oxide film preferably has crystallinity (i.e., has crystal grains). Examples of films having crystal grains include single-crystal films, polycrystalline films, and amorphous films containing crystal grains (also called microcrystalline films). In particular, the indium oxide film is preferably a polycrystalline film, and more preferably a single-crystal film. A single-crystal film does not have grain boundaries. Impurities (typically, insulating impurities, insulating oxides, etc.) that hinder carrier flow tend to segregate at grain boundaries. The use of a single-crystal film can suppress carrier scattering at grain boundaries, thereby realizing a transistor exhibiting high field-effect mobility. Furthermore, the use of a single-crystal film has the excellent effect of suppressing variations in transistor characteristics due to the grain boundaries.

[0338] Furthermore, polycrystalline films are preferable because they can reduce carrier scattering and exhibit high field-effect mobility compared to microcrystalline or amorphous films. When using a polycrystalline film, it is preferable to use a film with as large a crystal grain size as possible and with few crystal grain boundaries. Note that in a transistor using an indium oxide polycrystalline film, if there is no crystal grain boundary in the channel formation region or no crystal grain boundary is observed, the channel formation region is located within a single crystal region included in the polycrystalline film, and therefore the transistor can be considered to be using single-crystal indium oxide.

[0339] The crystallinity of indium oxide can be analyzed by, for example, X-ray diffraction (XRD), transmission electron microscope (TEM), or electron diffraction (ED). Alternatively, a combination of these methods may be used for analysis.

[0340] In this specification and the like, a semiconductor layer in which no crystal grain boundary is observed in the channel formation region, a semiconductor layer in which the channel formation region is included in one crystal grain, or a semiconductor layer in which the crystal axis direction is the same in at least two regions in the channel formation region can be called a single crystal film. Also, a semiconductor layer in which, in the channel formation region, within one crystal grain, the direction of another crystal axis continuously changes around a certain crystal axis or a certain crystal orientation as the axis of rotation can be called a single crystal film.

[0341] Unless otherwise specified, the channel formation region refers to a region of the semiconductor layer that overlaps (or faces) the gate electrode via the gate insulating film, and is located between the region in contact with the source electrode and the region in contact with the drain electrode. The current path in the channel formation region is the shortest distance between the source electrode and the drain electrode. Therefore, the crystal grains, crystal grain boundaries, crystal axes, crystal orientation, etc. in the channel formation region can be confirmed by observing a cross section including the semiconductor layer, source electrode, and drain electrode.

[0342] The indium oxide film in the channel formation region preferably has a lower impurity concentration. Impurities in the indium oxide film in the channel formation region can be a scattering source of carriers, which can lead to a decrease in field-effect mobility. These impurities can also hinder the crystal growth of the indium oxide film. Examples of impurities in the indium oxide film include boron and silicon. The indium oxide film preferably contains these impurities at concentrations of 0.1% or less, and more preferably 0.01% (100 ppm) or less. Carbon, hydrogen, and other elements may be contained in the film-forming gas or precursor during film formation, and may remain in the indium oxide film in greater amounts than the above-mentioned impurities.

[0343] The indium oxide film in the channel formation region may contain an element that can become the same trivalent cation as indium, as long as the crystal maintains a cubic crystal structure (bixbyite type). Examples of such an element include Group 13 elements of the periodic table, such as gallium and aluminum, and Group 3 elements of the periodic table. These elements exist mainly as trivalent cations in oxides, and therefore the carrier concentration of indium oxide can be maintained low.

[0344] By using such an indium oxide film in a transistor, the field effect mobility of the transistor can be increased to 50 cm ２ / (V·s) or more, preferably 100 cm ２ / (V·s) or more, more preferably 150 cm ２ / (V·s) or more, more preferably 200 cm ２ / (V·s) or more, more preferably 250 cm ２ / (V·s) or more.

[0345] One of the features of an indium oxide film is that it has higher oxygen permeability (diffusibility) than an IGZO film. As shown in FIG. 20C, Ｘ Oxygen (O) diffusing into the indium oxide film passes through the indium oxide film and becomes oxygen molecules (O ２ ) and is released as water molecules (H ２ In some cases, oxygen atoms are released as oxygen vacancies (Vo) in the film. If oxygen vacancies (Vo) exist in the film, the diffusing oxygen atoms compensate for the oxygen vacancies. Since oxygen easily diffuses in an indium oxide film, it can be said that oxygen vacancies are more easily compensated for in comparison with an IGZO film.

[0346] As described above, an indium oxide film can more easily reduce oxygen vacancies in the film than an IGZO film. Therefore, by using such an indium oxide film in a transistor, a transistor exhibiting extremely high reliability can be realized.

[0347] Furthermore, as shown in FIG. 20C, the indium oxide film diffuses hydrogen. Hydrogen that diffuses into the indium oxide film from the outside passes through the indium oxide film and becomes hydrogen molecules (H ２ ) or reacts with oxygen contained in the membrane and is released as water molecules.

[0348] A transistor using an indium oxide film is an accumulation-type transistor that uses electrons as majority carriers. Assuming that the carrier relaxation time is constant, the smaller the effective mass of the electrons (carriers), the higher the electron mobility. In other words, by using indium oxide, which has a small effective mass of electrons, for a transistor, the on-state current or field-effect mobility of the transistor can be increased.

[0349] Table 1 shows the results of single crystal indium oxide (here, In ２ O ３ ) and single-crystal silicon (Si). As shown in Table 1, indium oxide is characterized by a small effective mass of electrons and a large effective mass of holes. Indium oxide also has the characteristic that the effective mass of electrons is almost independent of the crystal orientation. Therefore, by using crystalline indium oxide in a transistor, a transistor with high field-effect mobility and high frequency characteristics (also called f characteristics) can be realized. Furthermore, since the effective mass of holes is large, a transistor with extremely small off-current can be realized. For example, by applying an indium oxide film to a vertical transistor, the off-current per 1 μm of channel width can be reduced to 1 fA (1×10) in an environment of 125° C. −１５ A) or less, or 1aA (1 x 10 −１８ A) or less, and under room temperature (25°C) conditions, −１８ A) or less, or 1zA (1 x 10 −２１ Furthermore, as shown in Table 1, indium oxide has a smaller effective mass of electrons and a larger effective mass of holes than silicon, and therefore may be able to realize a transistor with higher field-effect mobility and smaller off-state current than a Si transistor.

[0350]

[0351] It is preferable to provide a seed layer so as to be in contact with at least a portion of the crystalline indium oxide film. The seed layer is preferably made of a material containing crystals with a small difference in lattice constant (also called lattice mismatch) with indium oxide. This can improve the crystallinity of the indium oxide film. Note that a substrate (e.g., a single-crystal substrate) may be used as one of the layers in contact with at least a portion of the crystalline indium oxide film.

[0352] One method for evaluating the degree of lattice mismatch is to use the value of the lattice mismatch shown below. The lattice mismatch Δa [%] of the crystals of the formed film (here, the indium oxide film) with respect to the crystals of the seed layer is expressed as Δa = ((L １ -L ２ ) / L ２ ) × 100, where L １ is the length or lattice constant of the unit lattice vector of the crystal of the formed film, and L ２ is the length of the unit cell vector or the lattice constant of the crystal of the seed layer.

[0353] The smaller the absolute value of the lattice mismatch Δa between the seed layer and the indium oxide film, the more preferable, and it is most preferably 0. For example, Δa can be set to −5% or more and 5% or less, preferably −4% or more and 4% or less, more preferably −3% or more and 3% or less, and even more preferably −2% or more and 2% or less.

[0354] Here, the indium oxide crystal has a cubic crystal structure (bixbyite type). For example, the crystal of yttria-stabilized zirconia (YSZ) can have a cubic crystal structure (fluorite type). The lattice mismatch of the indium oxide crystal with the cubic YSZ crystal is in the range of −2% to 2%, and a single crystal film of indium oxide can be epitaxially grown on the YSZ substrate.

[0355] It should be noted that the crystal structure of the seed layer and the crystal structure of the indium oxide film may not necessarily have the same crystal system or crystal orientation. For example, a film having crystals of a hexagonal or trigonal structure may be used under an indium oxide film having crystals of a cubic structure. For example, by setting the crystal orientation of the surface of the seed layer to

[001] and the crystal orientation of the underside of the indium oxide film to

[111] , the requirements related to the crystal orientation necessary for epitaxial growth can be satisfied. Examples of hexagonal or trigonal crystals include wurtzite structure, YbFe ２ O ４ Type structure, Yb ２ Fe ３ O ７ YbFeFe alloys have the following structures: ２ O ４ Type structure or Yb ２ Fe ３ O ７ An example of a crystal having a ZnO-type structure is IGZO.

[0356] The contents of this embodiment can be implemented by combining them as appropriate. The contents of this embodiment can also be implemented by combining them as appropriate with the contents of other embodiments.

[0357] In this embodiment, an example of a package containing an image sensor chip and a camera module will be described. The image sensor chip can have a structure of an imaging device according to one embodiment of the present invention. Also, an example of an electronic device in which the imaging device according to one embodiment of the present invention can be used will be described.

[0358] 21A is a perspective view of the appearance of a package containing an image sensor chip. The package is a CSP (Chip Size Package) and includes an image sensor bare chip 850, a cover glass 840, and an adhesive 830 that bonds the two together.

[0359] An electrode pad 825 provided outside the pixel array 855 is connected to the rear surface electrode 815 via a through electrode 820. Although not shown, the electrode pad 825 is connected to a circuit constituting the image sensor via wiring or wires. Note that the bare chip 850 may be a laminated chip in which circuits having various functions are laminated.

[0360] 21A illustrates a BGA (Ball Grid Array) in which bumps 810 are formed with solder balls on rear surface electrodes 815. The configuration is not limited to a BGA, and may be an LGA (Land Grid Array) or a PGA (Pin Grid Array). Alternatively, a package in which bare chip 850 is mounted on a QFN (Quad Flat No-Lead Package) or a QFP (Quad Flat Package) may be used.

[0361] 21B is a perspective view of the top surface of a camera module that combines an image sensor chip and a lens. The camera module includes a lens cover 860 and multiple lenses 870 in addition to the configuration of FIG. 21A. An optical filter 880 that absorbs light of a specific wavelength is provided between the lens 870 and the cover glass 840 as needed. For example, in the case of an image sensor that primarily captures visible light, an infrared cut filter or the like can be used as the optical filter 880.

[0362] By housing the image sensor chip in a package of the above-described type, it becomes easy to mount the image sensor chip on a printed circuit board or the like, and the image sensor chip can be incorporated into various semiconductor devices and electronic devices.

[0363] Electronic Devices Examples of electronic devices that can use the imaging device according to one embodiment of the present invention include display devices, personal computers, image storage devices or image playback devices equipped with a recording medium, mobile phones, game consoles including portable devices, portable data terminals, e-book readers, cameras such as video cameras and digital still cameras, goggle displays (head-mounted displays), navigation systems, audio playback devices (car audio, digital audio players, etc.), copiers, facsimiles, printers, printer-combined machines, automated teller machines (ATMs), and vending machines. By using the imaging device according to one embodiment of the present invention in these electronic devices, high-resolution images can be obtained. Furthermore, the electronic devices can be operated at high speed. Furthermore, the electronic devices can be miniaturized. Specific examples of these electronic devices are shown in FIGS. 22A to 22F .

[0364] 22A illustrates an example of a mobile phone, which includes a housing 981, a display portion 982, operation buttons 983, an external connection port 984, a speaker 985, a microphone 986, a camera 987, and the like. The mobile phone includes a touch sensor in the display portion 982. Any operation, such as making a call or inputting text, can be performed by touching the display portion 982 with a finger or a stylus. The imaging device of one embodiment of the present invention can be applied to the mobile phone.

[0365] 22B shows a portable data terminal including a housing 911, a display portion 912, a speaker 913, a camera 919, and the like. Information can be input and output using a touch panel function of the display portion 912. Characters and the like can be recognized from an image acquired by the camera 919 and output as voice through the speaker 913. The imaging device of one embodiment of the present invention can be applied to the portable data terminal.

[0366] 22C illustrates a digital camera including a housing 961, a shutter button 962, a microphone 963, a light-emitting portion 967, a lens 965, and the like. The imaging device of one embodiment of the present invention can be applied to the digital camera.

[0367] 22D shows a wristwatch-type information terminal including a display portion 932, a housing / wristband 933, a camera 939, and the like. The display portion 932 includes a touch panel for operating the information terminal. The display portion 932 and the housing / wristband 933 are flexible and therefore easily worn on the body. The imaging device of one embodiment of the present invention can be applied to this information terminal.

[0368] 22E shows a surveillance camera, which includes a support base 951, a camera unit 952, a protective cover 953, and the like. The camera unit 952 is provided with a rotation mechanism and is installed on the ceiling, enabling imaging of the entire periphery. The imaging device of one embodiment of the present invention can be applied to an element for acquiring an image in the camera unit. Note that the term "surveillance camera" is a common name and is not intended to limit the application. For example, a device having a function as a surveillance camera is also called a camera or a video camera.

[0369] 22F shows a drive recorder including a frame 941, a camera 942, an operation button 943, and an attachment part 944. By installing the drive recorder on the front window of a vehicle or the like via the attachment part 944, the view ahead while the vehicle is traveling can be recorded. Note that a display panel that displays recorded images is provided on the back surface (not shown). The imaging device of one embodiment of the present invention can be applied to the camera 942.

[0370] 23A illustrates a drone, which is an example of a moving object, including a frame 921, an arm 922, a rotor 923, blades 924, a camera 925, a battery 926, and the like, and has a function of autonomously flying, a function of remaining stationary in the air, etc. The imaging device of one embodiment of the present invention can be applied to the camera 925.

[0371] 23B illustrates an external view of an automobile as an example of a moving object. The automobile 890 includes a plurality of cameras 891 and can acquire information about the front, rear, left, right, and above of the automobile 890. The imaging device of one embodiment of the present invention can be applied to the cameras 891. The automobile 890 also includes various sensors (not shown), such as infrared radar, millimeter-wave radar, and laser radar. The automobile 890 analyzes images acquired by the cameras 891 in a plurality of imaging directions 892, determines surrounding traffic conditions such as the presence or absence of guardrails or pedestrians, and can perform autonomous driving. The automobile 890 can also be used in systems that provide road guidance, hazard prediction, and the like.

[0372] In an imaging device according to one embodiment of the present invention, the obtained image data is subjected to arithmetic processing such as a neural network, thereby enabling processing such as increasing the image resolution, reducing image noise, face recognition (for crime prevention purposes, etc.), object recognition (for autonomous driving purposes, etc.), image compression, image correction (wide dynamic range), image restoration for lensless image sensors, positioning, character recognition, and reduction of reflected glare.

[0373] The automobile may be any of an automobile having an internal combustion engine, an electric automobile, a hydrogen automobile, and the like. Furthermore, the mobile object is not limited to an automobile. For example, examples of the mobile object include a train, a monorail, a ship, and an aircraft (helicopter, unmanned aerial vehicle, airplane, rocket), and the like. A computer according to one embodiment of the present invention can be applied to these mobile objects to provide a system using artificial intelligence.

[0374] The contents of this embodiment can be implemented by combining them as appropriate. The contents of this embodiment can also be implemented by combining them as appropriate with the contents of other embodiments.

[0375] (Additional Notes Regarding the Description of the Present Specification, etc.) The following additional notes will be given regarding the above-described embodiments and the explanation of each configuration in the embodiments.

[0376] In this specification, "connection" includes, for example, "electrical connection." When "electrical connection" is used to define the connection relationship between circuit elements as an object, "electrical connection" includes, for example, "direct connection" and "indirect connection." For example, "A and B are directly connected" refers to a connection between A and B without the intervention of a circuit element (e.g., a transistor or a switch; wiring is not considered a circuit element). On the other hand, "A and B are indirectly connected" refers to a connection between A and B via one or more circuit elements. Note that A, B, and C, which will be described later, represent objects such as elements, circuits, wiring, electrodes, terminals, semiconductor layers, and conductive layers.

[0377] Here, when "A and B are indirectly connected," it refers to the following connection relationship, for example. That is, assuming that a circuit is operating, if there is a time during the operation of the circuit when electrical signal transmission or potential interaction occurs between A and B, such a circuit can be defined as an entity, and "A and B are indirectly connected." Note that even if there is a time when electrical signal transmission or potential interaction does not occur between A and B, if there is a time during the operation of the circuit when electrical signal transmission or potential interaction occurs between A and B, it can be defined as "A and B are indirectly connected." Note that "A and B are indirectly connected" is a definition of the connection relationship between circuit elements as an entity. Therefore, for example, even when a power supply voltage is not supplied to a circuit and the circuit is not operating, the circuit can be defined as an entity, and "A and B are indirectly connected" (however, for example, this is limited to the case where electrical signal transmission or potential interaction occurs between A and B during the operation of the circuit when a power supply voltage is supplied to the circuit and the circuit is operating).

[0378] Specific examples of "indirect connection" are shown below. First, an example of "A and B are indirectly connected" is when A and B are connected via the source and drain of one or more transistors, as shown in FIGS. 24A1 and 24A2. Another example of "A and B are indirectly connected" is when A and B are connected via one or more switches. When "A and B are indirectly connected," it is assumed that, assuming the circuit is operating, there is at least one time when one transistor between A and B is in an on state, a conductive state, or a state in which current can flow. Note that "A and B are indirectly connected" also includes cases where one transistor between A and B is in an off state or a non-conductive state. When "A and B are indirectly connected," if multiple transistors are connected between A and B, it is assumed that, assuming the circuit is operating, each of the multiple transistors between A and B is in an on state, a conductive state, or a state in which current can flow. In other words, when "A and B are indirectly connected," it is not necessary for all of the multiple transistors to be in an on state, a conductive state, or a state in which current can flow simultaneously. Therefore, when "A and B are indirectly connected," it also includes cases in which the multiple transistors between A and B are in an off state or a non-conductive state at the same time or at different times. As another example, as shown in FIG. 24A3, when A and C are connected via the source and drain of transistor TrP and B and C are connected via the source and drain of transistor TrQ, it can be defined as "A and C are indirectly connected," "B and C are indirectly connected," or "A and B are indirectly connected." However, as will be described later, when a constant potential V is supplied to C from a power supply, GND, or the like, it can be said that "A and C are indirectly connected" or "B and C are indirectly connected," but it cannot be said that "A and B are indirectly connected."

[0379] While we have provided examples of cases where an "indirect connection" can and cannot be established, we will now present another example of a case where an "indirect connection" cannot be established. Even if an electrical signal exchange or potential interaction occurs between A and B during the operation of the circuit, there are exceptional cases where it cannot be said that "A and B are indirectly connected." An example of such an exceptional case is when A and B are connected via an insulator. In other words, when A and B are connected via an insulator, it cannot be said that "A and B are indirectly connected." A specific example of a case where A and B are connected via an insulator is when a capacitive element is connected between A and B, as shown in FIG. 24A4. Another example of a case where A and B are connected via an insulator is when a gate insulating film of a transistor is interposed between A and B, as shown in FIG. 24A5. In this case, it cannot be said that "A (the gate of the transistor) and B (the source or drain of the transistor) are indirectly connected."

[0380] Another example of a case where it cannot be said that "A and B are indirectly connected" is a case where there is no timing when an electrical signal is exchanged or when potential interaction occurs between A and B. An example of this is when, as shown in Figures 24A6 and 24A7, multiple transistors are connected via their sources and drains to the path from A to B, and a constant potential V is supplied to a node between the transistors from a power supply, GND, or the like. In this case, it cannot be said that "A and B are indirectly connected," but it is possible to say that "A and V are indirectly connected" or "B and V are indirectly connected." In addition, in Figure 24A3, if A and C are connected via the source and drain of transistor TrP, and B and C are connected via the source and drain of transistor TrQ, and a constant potential V is supplied to C from a power supply or GND, etc., the connection relationship will be the same as in Figures 24A6 and 24A7, so it cannot be said that "A and B are indirectly connected," but it can be said that "A and C are indirectly connected," or "B and C are indirectly connected."

[0381] Although an example of "indirect connection" has been given above, as an example, the definition of "indirect connection" is included in the definition of "electrical connection," so if "A and B are indirectly connected," it can also be said that "A and B are electrically connected."

[0382] Next, specific examples of "direct connection" are shown. Examples of "A and B are directly connected" include cases where A and B are connected without any circuit element between them, as shown in FIGS. 24B1, 24B2, and 24B3. When A and B are connected to a power supply that supplies a constant potential V or to GND without any circuit element between them, as shown in FIGS. 24B4 and 24B5, it can be said that "A and B are directly connected," "A and V are directly connected," or "B and V are directly connected." It can also be said that "A and B are directly connected," even when A (or B) is connected to a constant potential V via the source and drain of a transistor, as shown in FIG. 24B6. Because A and V or B and V are connected via the source and drain of a transistor, they cannot be said to be directly connected, but rather that "A and V are indirectly connected" or "B and V are indirectly connected."

[0383] Although an example of "direct connection" has been given above, as an example, the definition of "direct connection" is included in the definition of "electrical connection," so when "A and B are directly connected," it can also be said that "A and B are electrically connected."

[0384] Note that even when independent components are shown connected to each other in a circuit diagram, one component may have the functions of multiple components. For example, if part of a wiring also functions as an electrode, one conductive film has the functions of both the wiring and the electrode. Therefore, in this specification, the term "connection" also includes such cases where one conductive film has the functions of multiple components.

[0385] Furthermore, in this specification, the term "resistive element" may refer to, for example, a circuit element or wiring having a resistance value higher than 0 Ω. Therefore, in this specification, the term "resistive element" includes, for example, wiring having a resistance value, a transistor in which current flows from drain to source, a diode, or a coil. Therefore, the term "resistive element" may be replaced with, for example, terms such as "resistance," "load," or "region having a resistance value." Conversely, the terms "resistance," "load," or "region having a resistance value" may be replaced with, for example, terms such as "resistive element." The resistance value may be, for example, preferably 1 mΩ or more and 10 Ω or less, more preferably 5 mΩ or more and 5 Ω or less, and even more preferably 10 mΩ or more and 1 Ω or less. Furthermore, for example, the resistance value may be, for example, 1 Ω or more and 1×10 ９ It may be set to Ω or less.

[0386] When a wiring is used as a resistor, the resistance value of the resistor may be determined by the length of the wiring. Alternatively, the resistor may use a conductor having a different resistivity from the conductor used as the wiring. Alternatively, when a semiconductor is used as a resistor, the resistance value of the resistor may be determined by doping impurities into the semiconductor.

[0387] Furthermore, in this specification, a "capacitive element" can refer to, for example, a circuit element having a capacitance value higher than 0 F, a region of wiring having a capacitance value higher than 0 F, a parasitic capacitance, or a gate capacitance of a transistor. Therefore, in this specification, a "capacitive element" is not limited to a circuit element including a pair of electrodes and a dielectric sandwiched between the electrodes. A "capacitive element" also includes, for example, a parasitic capacitance occurring between wirings, or a gate capacitance occurring between one of the source or drain of a transistor and the gate. Furthermore, terms such as "capacitive element," "parasitic capacitance," or "gate capacitance" can be replaced with terms such as "capacitance" or "capacitance." Conversely, terms such as "capacitance" or "capacitance" can be replaced with terms such as "capacitive element," "parasitic capacitance," or "gate capacitance." Furthermore, terms such as "pair of electrodes," "pair of wirings," "pair of terminals," "pair of conductive layers," "pair of conductors," "pair of conductive regions," and "pair of regions" of a "capacitive element" can sometimes be interchangeable. The capacitance value may be, for example, 0.05 fF to 10 pF, or may be, for example, 1 pF to 10 μF.

[0388] In this specification and the like, a transistor has three terminals called a gate (also referred to as a gate terminal, a gate region, or a gate electrode), a source (also referred to as a source terminal, a source region, or a source electrode), and a drain (also referred to as a drain terminal, a drain region, or a drain electrode). The transistor also has a region where a channel is formed between the drain and the source (also referred to as a channel formation region). A transistor can pass a current between the source and the drain through the channel formation region. That is, a transistor can transmit and receive an electric signal or generate a potential interaction between the source and the drain through the channel formation region. The channel formation region is a region through which a current mainly flows. The gate is a control terminal that controls the amount of current flowing in the channel formation region. The two terminals that function as a source and a drain are input / output terminals that input or output a current flowing in the channel formation region.

[0389] Note that one of the two input / output terminals functions as a source and the other as a drain depending on the conductivity type of the transistor (n-channel or p-channel) and the level of the potential applied to the three terminals of the transistor. Furthermore, for example, when the direction of current changes during circuit operation, the function as a source and the function as a drain may be interchanged. For this reason, in this specification, the terms "source" and "drain" are interchangeable. Furthermore, in this specification, when describing the connection relationship of a transistor, the terms "one of the source or drain" (or first electrode or first terminal) or "the other of the source or drain" (or second electrode or second terminal) are used.

[0390] Depending on the structure, a transistor may have a terminal called a back gate (also referred to as a back gate terminal, back gate region, or back gate electrode) in addition to the three terminals described above. In this case, in this specification and the like, one of the gate or the back gate of the transistor may be referred to as a first gate, and the other of the gate or the back gate of the transistor may be referred to as a second gate. Furthermore, for the same transistor, the terms "gate" and "back gate" may be interchangeable. Furthermore, when a transistor has three or more gates, in this specification and the like, each gate may be referred to as, for example, a first gate, a second gate, a third gate, or the like.

[0391] In this specification, a transistor having a multi-gate structure with two or more gate electrodes can be used. A multi-gate transistor has channel formation regions connected in series, resulting in a structure in which multiple transistors are connected in series. Therefore, a multi-gate transistor can reduce off-state current and improve the transistor's breakdown voltage (improved reliability). Furthermore, when a multi-gate transistor operates in the saturation region, even if the voltage between the drain and source changes, the current between the drain and source does not change significantly, resulting in a voltage-current characteristic with a flat slope. A transistor having a voltage-current characteristic with a flat slope can realize an ideal current source circuit or an active load with a very high resistance value. As a result, a transistor having a voltage-current characteristic with a flat slope can realize, for example, a differential circuit or a current mirror circuit with good characteristics.

[0392] Furthermore, in this specification, when a single circuit element is illustrated on a circuit diagram, the circuit element may include multiple circuit elements. For example, when a single resistor is illustrated on a circuit diagram, the resistor is considered to include two or more resistors connected in series. For example, when a single capacitor is illustrated on a circuit diagram, the capacitor is considered to include two or more capacitors connected in parallel. For example, when a single transistor is illustrated on a circuit diagram, the transistor is considered to include two or more transistors connected in series, with the gates of the respective transistors connected to each other. Similarly, when a single switch is illustrated on a circuit diagram, the switch is considered to include two or more transistors, with the two or more transistors connected in series or in parallel, and with the gates of the respective transistors connected to each other.

[0393] Furthermore, in this specification and the like, a "node" can be rephrased as a "terminal," "wiring," "electrode," "conductive layer," "conductor," or "impurity region," depending on, for example, the circuit configuration or the device structure. Furthermore, for example, a "terminal" or "wiring" can be rephrased as a "node."

[0394] Furthermore, in this specification, "voltage" and "potential" can be interchanged as appropriate. "Voltage" refers to the potential difference from a reference potential. For example, if the reference potential is the ground potential (earth potential), then "voltage" can be interchanged with "potential." Note that ground potential does not necessarily mean 0 V. Furthermore, potential is relative. In other words, a change in the reference potential will change, for example, the potential applied to wiring, the potential applied to a circuit, or the potential output from a circuit.

[0395] Furthermore, in this specification and the like, the terms "high-level potential (also referred to as "high-level potential," "H potential," or "H")" and "low-level potential (also referred to as "low-level potential," "L potential," or "L")" do not refer to any particular potential. For example, when two wirings are both described as "functioning as wirings that supply a high-level potential," the high-level potentials provided by both wirings do not have to be equal to each other. Similarly, when two wirings are both described as "functioning as wirings that supply a low-level potential," the low-level potentials provided by both wirings do not have to be equal to each other.

[0396] Furthermore, in this specification, "electric current" refers to the phenomenon of charge transfer (electrical conduction). For example, the statement "electrical conduction of positively charged bodies is occurring" can be rephrased as "electrical conduction of negatively charged bodies is occurring in the opposite direction." Therefore, in this specification, unless otherwise specified, "electric current" refers to the phenomenon of charge transfer (electrical conduction) associated with the movement of carriers. Examples of carriers include electrons, holes, anions, cations, and complex ions. Note that carriers vary depending on the system through which the current flows (e.g., semiconductor, metal, electrolyte, vacuum, etc.). Furthermore, the "direction of current" in, for example, wiring, is the direction in which positive carriers move and is expressed as a positive current amount. In other words, the direction in which negative carriers move is opposite to the direction of current and is expressed as a negative current amount. Therefore, in this specification and the like, unless otherwise specified, regarding the positive / negative (or current direction) of a current, for example, a statement such as "a current flows from element A to element B" can be rephrased as "a current flows from element B to element A" etc. Furthermore, for example, a statement such as "a current is input to element A" can be rephrased as "a current is output from element A" etc.

[0397] Furthermore, in this specification, the ordinal numbers "first," "second," and "third" are used to avoid confusion between components. Therefore, they do not limit the number of components. Furthermore, they do not limit the order of the components. For example, a component referred to as "first" in one embodiment of this specification may be referred to as "second" in another embodiment or in the claims. Furthermore, for example, a component referred to as "first" in one embodiment of this specification may be omitted in another embodiment or in the claims.

[0398] Furthermore, in this specification, terms indicating arrangement, such as "above," "below," "upward," or "belowward," may be used for convenience in describing the positional relationship between components with reference to drawings. Furthermore, the positional relationship between components changes as appropriate depending on the orientation in which each component is depicted. Therefore, terms indicating arrangement described in this specification are not limited to these terms and can be rephrased appropriately. For example, the expression "insulator located on the upper surface of a conductor" can be rephrased as "insulator located on the lower surface of a conductor" by rotating the orientation of the drawing by 180 degrees. Furthermore, the expression "insulator located on the upper surface of a conductor" can be rephrased as "insulator located on the left (or right) surface of a conductor" by rotating the orientation of the drawing by 90 degrees.

[0399] Furthermore, the terms "above" and "below" do not limit the positional relationship of components to being directly above or below and in direct contact with each other. For example, the expression "electrode B on insulating layer A" does not necessarily mean that electrode B is formed on insulating layer A in direct contact with it, and does not exclude the inclusion of other components between insulating layer A and electrode B. Thus, the term "above" may be replaced with terms such as "above," "upper side," or "upper layer," and the term "below" may be replaced with terms such as "below," "lower side," or "lower layer."

[0400] Furthermore, in this specification, terms such as "row" or "column" may be used to describe components arranged in a matrix and their positional relationships. Furthermore, the positional relationships between components change as appropriate depending on the direction in which each component is depicted. Therefore, terms such as "row" or "column" used in this specification are not limited to these terms and can be rephrased appropriately. For example, the expression "row direction" can be rephrased as "column direction" by rotating the orientation of the drawing by 90 degrees.

[0401] Furthermore, in this specification and the like, for example, terms such as "overlap" do not limit the state of the stacking order of components, etc. For example, the expression "electrode B overlapping insulating layer A" is not limited to the state in which electrode B is formed on insulating layer A. The expression "electrode B overlapping insulating layer A" does not exclude, for example, the state in which electrode B is formed under insulating layer A, or the state in which electrode B is formed on the right (or left) side of insulating layer A.

[0402] Furthermore, in this specification and the like, the terms "adjacent" or "close to" do not limit components to being in direct contact with each other. For example, the expression "electrode B adjacent to insulating layer A" does not necessarily mean that insulating layer A and electrode B are formed in direct contact with each other, and does not exclude the inclusion of other components between insulating layer A and electrode B.

[0403] Furthermore, in this specification and the like, terms such as "film" or "layer" may be interchangeable. For example, the term "conductive layer" may be interchangeable with the term "conductive film." For example, the term "insulating film" may be interchangeable with the term "insulating layer." Furthermore, terms such as "film" or "layer" may be interchangeable with other terms without using those terms. For example, the term "conductive layer" or "conductive film" may be interchangeable with the term "conductor." Furthermore, the term "conductor" may be interchangeable with the term "conductive layer" or "conductive film." For example, the term "insulating layer" or "insulating film" may be interchangeable with the term "insulator." Furthermore, the term "insulator" may be interchangeable with the term "insulating layer" or "insulating film."

[0404] Furthermore, in this specification and the like, terms such as "electrode," "wiring," or "terminal" do not functionally limit these components. For example, an "electrode" may be used as part of a "wiring," and vice versa. Furthermore, the terms "electrode" or "wiring" include, for example, cases where multiple "electrodes" or "wirings" are integrally formed. Furthermore, for example, a "terminal" may be used as part of a "wiring" or "electrode," and vice versa. Furthermore, the term "terminal" includes, for example, cases where multiple "electrodes," "wirings," or "terminals" are integrally formed. Therefore, for example, an "electrode" can be part of a "wiring" or "terminal." Furthermore, for example, a "terminal" can be part of a "wiring" or "electrode." Furthermore, for example, terms such as "electrode," "wiring," or "terminal" may be replaced with terms such as "region."

[0405] Furthermore, in this specification and the like, for example, terms such as "signal line" or "power line" may be changed to the term "wiring." Furthermore, for example, the term "potential" applied to wiring may be changed to the term "signal." The same is true in reverse, for example, terms such as "signal" may be changed to the term "potential."

[0406] In addition, in this specification, a "switch" refers to a circuit element that has multiple terminals and the ability to switch (select) between conduction and non-conduction between the terminals. In other words, a switch can be said to have the ability to control whether or not a current flows between the multiple terminals, or the ability to control whether or not an electrical signal or potential interaction occurs between the multiple terminals. For example, if a switch has two terminals and the two terminals are considered to be electrically short-circuited, the switch is said to be in a "conductive state" or "on state." Furthermore, if the two terminals are considered to be electrically disconnected, the switch is said to be in a "non-conductive state" or "off state." Note that switching the switch between a conductive state or a non-conductive state, or maintaining the switch in either a conductive state or a non-conductive state, may be referred to as "controlling the conduction state."

[0407] In other words, a switch is a device that has the function of controlling whether or not a current flows. Alternatively, a switch is a device that has the function of selecting and switching a path through which a current flows. For example, an electrical switch or a mechanical switch can be used as the switch. In other words, the switch is not limited to a specific type.

[0408] There are types of switches that are normally in a non-conductive state but can be made conductive by controlling the conductive state, and these switches are sometimes called "contact A." There are also types of switches that are normally in a conductive state but can be made non-conductive by controlling the conductive state, and these switches are sometimes called "contact B."

[0409] Examples of electrical switches include transistors (e.g., bipolar transistors or MOS transistors), diodes (e.g., PN diodes, PIN diodes, Schottky diodes, MIM (Metal Insulator Metal) diodes, MIS (Metal Insulator Semiconductor) diodes, or diode-connected transistors), and logic circuits that combine these. Note that when a transistor is operated simply as a switch, the polarity (conductivity type) of the transistor is not particularly limited.

[0410] An example of a mechanical switch is a switch that uses MEMS (microelectromechanical systems) technology. Such a switch has an electrode that can be mechanically moved, and the movement of the electrode selects a conductive state or a non-conductive state.

[0411] In this specification, the "channel length" of a transistor may refer to, for example, the distance between the source and drain in a region where the semiconductor (or the portion in the semiconductor through which current flows when the transistor is on) and the gate overlap, or the distance between the source and drain in a region where a channel is formed.

[0412] In addition, in this specification, the "channel width" of a transistor may refer to, for example, the length of the portion where the source and drain face each other in a region where the semiconductor (or the portion where current flows in the semiconductor when the transistor is on) and the gate overlap, or the length of the portion where the source and drain face each other in a region where a channel is formed.

[0413] In this specification and the like, terms such as "substrate," "wafer," or "die" do not limit the functionality of these components. For example, terms such as "substrate," "wafer," or "die" may be used interchangeably.

[0414] In this specification, "parallel" does not necessarily mean strictly parallel. Therefore, the term "parallel" can be appropriately interchanged with terms such as "approximately parallel," "generally parallel," or "substantially parallel." Unless otherwise specified, "parallel," "generally parallel," "generally parallel," or "substantially parallel" may include, for example, a state in which two lines or planes are arranged at an angle of -5° or more and 5° or less. Alternatively, they may include a state in which two lines or planes are arranged at an angle of -10° or more and 10° or less. Alternatively, they may include a state in which two lines or planes are arranged at an angle of -30° or more and 30° or less. Therefore, "parallel" can mean, for example, "parallel or roughly parallel." Furthermore, "perpendicular" does not necessarily mean strictly perpendicular. Therefore, the term "perpendicular" can be appropriately interchanged with terms such as "generally vertical," "generally vertical," or "substantially vertical." Unless otherwise specified, "vertical," "approximately vertical," "generally vertical," or "substantially vertical" may include, for example, a state in which two straight lines or planes are arranged at an angle of 85° or more and 95° or less. Alternatively, it may also include a state in which two straight lines or planes are arranged at an angle of 80° or more and 100° or less. Alternatively, it may also include a state in which two straight lines or planes are arranged at an angle of 60° or more and 120° or less. Therefore, "vertical" may mean, for example, "vertical or roughly vertical."

[0415] In this specification, "equal heights" refers to the same height from a reference surface (e.g., a flat surface such as a substrate surface) in a cross-sectional view. For example, in a semiconductor device manufacturing process, a planarization process may expose the surface of a single layer or multiple layers. In this case, the surfaces to be planarized have the same height from the reference surface. However, depending on the processing equipment, processing method, or material of the processed surface during the planarization process, the heights of multiple layers may not be strictly equal. In this specification, "equal heights" is also used. For example, when there are two layers (here, a first layer and a second layer) with different heights relative to a reference surface, the difference between the height of the top surface of the first layer and the height of the top surface of the second layer is 20 nm or less. Therefore, "equal heights" may mean, for example, "equal heights or approximately equal heights."

[0416] In this specification, "edges coincide" means that, when viewed from above, at least a portion of the contours of stacked layers overlap. For example, this includes cases in which, in a semiconductor device manufacturing process, upper and lower layers are processed using the same mask pattern or a portion of the same mask pattern. However, strictly speaking, the contours may not overlap, and the contour of the upper layer may be located inside the contour of the lower layer, or the contour of the upper layer may be located outside the contour of the lower layer. In this specification, this case is also referred to as "edges coincide." Therefore, "edges coincide" can mean, for example, "edges coincide or approximately coincide."

[0417] In this specification, for example, when referring to counting values ​​and measurement values, or to things, methods, and events that can be converted into counting values ​​or measurement values, terms such as "identical," "same," "equal," "simultaneous," "matching," or "uniform" (including synonyms thereof) are intended to include errors. Therefore, unless otherwise specified, these terms may include an error of plus or minus 10% or an error of plus or minus 20%. Thus, "identical" means "identical or approximately identical," "same" means "same or approximately the same," "equal" means "equal or approximately equal," "simultaneous" means "simultaneous or approximately simultaneous," "matching" means "matching or approximately matching," and "uniform" may mean "uniform or approximately uniform."

[0418] In this specification and the like, the term "impurity" in a semiconductor refers to, for example, a substance other than the main component constituting the semiconductor. For example, an element with a concentration of less than 0.1 atomic % is an impurity. The presence of impurities in a semiconductor may, for example, increase the defect state density of the semiconductor, decrease the carrier mobility, or decrease the crystallinity. When the semiconductor is an oxide semiconductor, examples of impurities that change the characteristics of the semiconductor include Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main component of the oxide semiconductor. In particular, examples of impurities include hydrogen (also contained in water), lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. For example, the inclusion of impurities in an oxide semiconductor may cause oxygen vacancies in the oxide semiconductor.

[0419] In this specification and the like, a metal oxide refers to an oxide of a metal in a broad sense. Metal oxides are classified into, for example, oxide insulators, oxide conductors (including transparent oxide conductors), and oxide semiconductors (also referred to as oxide semiconductors or simply as OSs). For example, when a metal oxide is used as a semiconductor including a channel formation region of a transistor, the metal oxide may be referred to as an oxide semiconductor. In other words, when a metal oxide is used as a material capable of forming a channel formation region of a transistor having at least one of an amplifying function, a rectifying function, and a switching function, the metal oxide can be referred to as a metal oxide semiconductor. Furthermore, the term "OS transistor" can be rephrased as a transistor including a metal oxide or an oxide semiconductor.

[0420] In this specification and the like, nitrogen-containing metal oxides may also be collectively referred to as metal oxides. Nitrogen-containing metal oxides may also be referred to as metal oxynitrides.

[0421] In addition, in drawings and the like relating to this specification, arrows indicating the X direction, Y direction, and Z direction may be used. In this specification, the "X direction" refers to the direction along the X axis, and unless otherwise specified, the forward direction and the reverse direction may not be distinguished. The same applies to the "Y direction" and the "Z direction." The X direction, Y direction, and Z direction are directions that intersect with each other. For example, the X direction, Y direction, and Z direction are directions that are perpendicular to each other. In this specification, one of the X direction, Y direction, and Z direction may be referred to as the "first direction" or "first direction." The other may be referred to as the "second direction" or "second direction." The remaining one may be referred to as the "third direction" or "third direction."

[0422] 100: semiconductor device, 101: pixel circuit, PD: light receiving element, M11: transistor, M12: transistor, M13: transistor, M14: transistor, C11: capacitance element, FD: node, SN: node, TX: wiring, RS: wiring, SE: wiring, WX: wiring, VL1: wiring, VL2: wiring, Lta: layer, Ltb: layer, Ltc: layer, Lpd: layer, Lop: layer, 200: transistor, 205: conductive layer, 205_1: conductive layer, 205_2: conductive layer, 208_a: conductive layer, 208_b: conductive layer, 212: insulating layer, 214: insulating layer, 216: insulating layer, 218 _a: conductive layer, 218_b: conductive layer, 221: insulating layer, 222: insulating layer, 224: insulating layer, 230: semiconductor layer, 230_1: semiconductor layer, 230_2: semiconductor layer, 230_a: semiconductor layer, 230_a1: semiconductor layer, 230_a2: semiconductor layer, 230_b: semiconductor layer, 230_b1: semiconductor layer, 230_b2: semiconductor layer, 241a: insulating layer, 241b: insulating layer, 242a: conductive layer, 242b: conductive layer, 243a: conductive layer, 243a1: conductive layer, 243a2: conductive layer, 243b: conductive layer, 243b1: conductive layer, 243b2: conductive layer, 246_a: conductive layer, 24 6_b: conductive layer, 248_a: conductive layer, 248_b: conductive layer, 250: insulating layer, 250_1: insulating layer, 250_2: insulating layer, 250_3: insulating layer, 250_4: insulating layer, 260: conductive layer, 260_1: conductive layer, 260_2: conductive layer, 275: insulating layer, 280: insulating layer, 282: insulating layer, 283: insulating layer, 285: insulating layer, 288: insulating layer, 289: opening, 292: insulating layer, 293: conductive layer, 294: conductive layer, 300: transistor, 310: transistor, 311: substrate, 313: semiconductor region, 314a: low resistance region, 314b: low resistance region, 315 : insulating layer, 316: conductive layer, 318: element isolation layer, 320: insulating layer, 322: insulating layer, 324: insulating layer, 326: insulating layer, 328: conductive layer, 328a: conductive layer, 328b: conductive layer, 330: conductive layer, 330a: conductive layer, 330b: conductive layer, 411: conductive layer, 412: functional layer, 413: photoelectric conversion layer, 414: functional layer, 415: conductive layer, 416: insulating layer, 417: insulating layer, 418: insulating layer, 419: insulating layer, 431: insulating layer, 432: conductive layer, 433: insulating layer, 434: conductive layer, 441: insulating layer, 442: insulating layer, 443: semiconductor region, 444: semiconductor region,445: insulating layer, 447: insulating layer, 450: optical filter, 451: light-shielding layer, 455: microlens array, 160: imaging device, 161: pixel, 162: pixel unit, 163: driving circuit, 164: readout circuit, 165: wiring, 166: wiring, 470: readout circuit, 471: current-voltage conversion circuit, 472: correlated double sampling circuit, 473: analog-to-digital conversion circuit, M41: transistor, M42: transistor, M43: transistor, C41: capacitance element, C42: capacitance element, DOL: wiring, VL41: wiring, VL42: wiring, VL43: wiring, NL41: wiring, NL42: wiring, NL43: wiring,

Claims

1. A semiconductor device comprising: a first transistor, a second transistor, and a light-receiving element; one terminal of the light-receiving element is electrically connected to a first terminal of the first transistor; a second terminal of the first transistor is electrically connected to a gate of the second transistor; the first transistor includes a first oxide semiconductor in a channel formation region; and the second transistor includes a second oxide semiconductor in a channel formation region.

2. A semiconductor device comprising: a first transistor, a second transistor, and a light-receiving element; one terminal of the light-receiving element is electrically connected to a first terminal of the first transistor; a second terminal of the first transistor is electrically connected to a gate of the second transistor; the first transistor includes a first oxide semiconductor in a channel formation region; the second transistor includes a second oxide semiconductor in a channel formation region; each of the first oxide semiconductor and the second oxide semiconductor includes indium; and the indium content of the second oxide semiconductor is higher than the indium content of the first oxide semiconductor.

3. A semiconductor device comprising: a first transistor, a second transistor, and a light-receiving element; one terminal of the light-receiving element is electrically connected to a first terminal of the first transistor; a second terminal of the first transistor is electrically connected to a gate of the second transistor; the first transistor includes a first oxide semiconductor in a channel formation region; the second transistor includes a second oxide semiconductor in a channel formation region; the first oxide semiconductor is indium gallium zinc oxide; and the second oxide semiconductor is indium oxide.

4. A semiconductor device according to any one of claims 1 to 3, comprising a third transistor and a fourth transistor, wherein a first terminal of the third transistor is electrically connected to a second terminal of the first transistor and a gate of the second transistor, a first terminal of the fourth transistor is electrically connected to a second terminal of the second transistor, a second terminal of the light receiving element is electrically connected to a first wiring, a first terminal of the second transistor is electrically connected to a second wiring, a second terminal of the third transistor is electrically connected to the second wiring, a gate of the first transistor is electrically connected to a third wiring, a gate of the third transistor is electrically connected to a fourth wiring, a gate of the fourth transistor is electrically connected to a fifth wiring, and a second terminal of the fourth transistor is electrically connected to a sixth wiring, the third transistor includes the first oxide semiconductor in a channel formation region, and the fourth transistor includes the second oxide semiconductor in a channel formation region.

5. A semiconductor device according to any one of claims 1 to 3, wherein the light receiving element is provided in a first layer, the first transistor is provided in a second layer above the first layer, and the second transistor is provided in a third layer above the second layer.

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