Semiconductor device and method for producing semiconductor device

Abstract

Provided is a semiconductor device having a high operating speed. The semiconductor device includes a transistor that uses indium oxide as a semiconductor layer, and an insulating layer. The source electrode and the drain electrode have an oxide that contains indium and a first metal element, and have a region in contact with an upper surface of the semiconductor layer. The film thickness of the source electrode and the drain electrode is thinner than the film thickness of the semiconductor layer. The insulating layer has a region in contact with an upper surface of the source electrode and the drain electrode. The insulating layer has a first opening between the source electrode and the drain electrode, and a gate insulating layer and a gate electrode are provided inside the first opening. The semiconductor layer has a recess that overlaps with the first opening. The source electrode and the insulating layer have a second opening, and the drain electrode and the insulating layer have a third opening. First and second plugs having a region in contact with the semiconductor layer, are respectively provided inside the second and third openings. The first and second plugs have a second metal element.

Description

Semiconductor device and method for manufacturing the same

[0001] 1. Field of the Invention One embodiment of the present invention relates to a semiconductor device, a memory device, and an electronic device. Another embodiment of the present invention relates to a manufacturing method of a semiconductor device.

[0002] One embodiment of the present invention is not limited to the above technical field, and examples of the technical field of one embodiment of the present invention include semiconductor devices, display devices, light-emitting devices, power storage devices, memory devices, electronic devices, lighting devices, input devices (e.g., touch sensors), input / output devices (e.g., touch panels), driving methods thereof, and manufacturing methods thereof.

[0003] In this specification and the like, a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (transistor, diode, photodiode, etc.), a device having such a circuit, etc. Also, it refers to any device that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip including an integrated circuit, and an electronic component in which a chip is housed in a package are examples of semiconductor devices. Furthermore, a memory device, a display device, a light-emitting device, a lighting device, and an electronic device may themselves be semiconductor devices and each may have a semiconductor device.

[0004] A technology for constructing transistors using semiconductor thin films formed on substrates with insulating surfaces has attracted attention. Such transistors are widely used in electronic devices such as integrated circuits (ICs) and display devices. While silicon-based semiconductor materials are widely known as semiconductor materials applicable to transistors, oxide semiconductors have also attracted attention as other materials.

[0005] Furthermore, it is known that a transistor using an oxide semiconductor has an extremely small leakage current in an off state. For example, Patent Document 1 discloses a low-power central processing unit (CPU) that utilizes the low leakage current characteristic of a transistor using an oxide semiconductor. Furthermore, Patent Document 2 discloses a memory device that can retain stored data for a long period of time by utilizing the low leakage current characteristic of a transistor using an oxide semiconductor.

[0006] Examples of oxide semiconductors that can be used in the active layer of a transistor include indium oxide and indium gallium zinc oxide. Non-Patent Document 1 discloses the use of indium oxide in thin film transistors. Non-Patent Document 2 discloses a thin film transistor that uses hydrogenated polycrystalline indium oxide formed by low-temperature solid phase crystallization as the active layer.

[0007] JP 2012-257187 A JP 2011-151383 A

[0008] Dhananjay and C. W. Chu, “Realization of In▲2▼O▲3▼ thin film transistors through reactive evaporation process” Appl. Phys. Lett. 91, 132111 (2007). Y. Magari et al. , "High-mobility hydrogenated polycrystalline In 2 O 3 (In 2 O 3 : H) thin-film transistors", Nature Communications, 13, 1078 (2022) Takashi Koida, "High-mobility transparent conductive film", National Institute of Advanced Industrial Science and Technology, AIST Photovoltaic Power Generation Research Results Report 2019, Internet <URL: https: / / unit.aist.go.jp / rpd-envene / PV / ja / results / 2019 / oral / T13.pdf>

[0009] An object of one embodiment of the present invention is to provide a semiconductor device or a storage device including a transistor with high on-state current.An object of one embodiment of the present invention is to provide a semiconductor device or a storage device including a transistor with favorable electrical characteristics.An object of one embodiment of the present invention is to provide a semiconductor device or a storage device with high operating speed.An object of one embodiment of the present invention is to provide a semiconductor device or a storage device with low manufacturing cost.An object of one embodiment of the present invention is to provide a highly reliable transistor, semiconductor device, or storage device.An object of one embodiment of the present invention is to provide a transistor, semiconductor device, or storage device that can be miniaturized or highly integrated.An object of one embodiment of the present invention is to provide a semiconductor device or a storage device with low power consumption.An object of one embodiment of the present invention is to provide a novel transistor, semiconductor device, or storage device.

[0010] An object of one embodiment of the present invention is to provide a method for manufacturing a semiconductor device or a memory device including a transistor with high on-state current.An object of one embodiment of the present invention is to provide a method for manufacturing a semiconductor device or a memory device including a transistor with favorable electrical characteristics.An object of one embodiment of the present invention is to provide a method for manufacturing a semiconductor device or a memory device with high operating speed.An object of one embodiment of the present invention is to provide a method for manufacturing a semiconductor device or a memory device with high yield.An object of one embodiment of the present invention is to provide a method for manufacturing a semiconductor device with high productivity.An object of one embodiment of the present invention is to provide a method for manufacturing a highly reliable transistor, semiconductor device, or memory device.An object of one embodiment of the present invention is to provide a method for manufacturing a transistor, semiconductor device, or memory device that can be miniaturized or highly integrated.An object of one embodiment of the present invention is to provide a method for manufacturing a semiconductor device or a memory device with low power consumption.An object of one embodiment of the present invention is to provide a method for manufacturing a novel transistor, semiconductor device, or memory device.

[0011] Note that the description of these problems does not preclude the existence of other problems. One embodiment of the present invention does not necessarily have to solve all of these problems. Problems other than these can be extracted from the description in the specification, drawings, and claims.

[0012] One embodiment of the present invention includes a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, a fifth conductive layer, a first insulating layer, and a second insulating layer, the first conductive layer and the second conductive layer being spaced apart from each other to have a region in contact with a top surface of the semiconductor layer, the first insulating layer having a region in contact with a top surface of the first conductive layer and a region in contact with a top surface of the second conductive layer, the first insulating layer having a first opening in a region between the first conductive layer and the second conductive layer in a plan view, the first conductive layer and the first insulating layer having a second opening having a region overlapping with the semiconductor layer, the second conductive layer and the first insulating layer having a third opening having a region overlapping with the semiconductor layer, the semiconductor layer having a first recess overlapping with the first opening, and the second insulating layer having a first recess in the first insulating layer. a third conductive layer is provided on the second insulating layer so as to have a region in contact with the semiconductor layer; a fourth conductive layer is provided on the second insulating layer so as to have a region in contact with the semiconductor layer; a fifth conductive layer is provided on the third opening so as to have a region in contact with the semiconductor layer; the first conductive layer has a thickness smaller than that of the semiconductor layer in a region overlapping with the first conductive layer; the second conductive layer has a thickness smaller than that of the semiconductor layer in a region overlapping with the second conductive layer; the semiconductor layer has indium oxide; the first conductive layer and the second conductive layer have an oxide containing indium and a first metal element; and the fourth conductive layer and the fifth conductive layer have a second metal element.

[0013] Alternatively, in the above aspect, the electrical resistivity in the first region of the semiconductor layer that contacts the fourth conductive layer and the second region of the semiconductor layer that contacts the fifth conductive layer may be lower than the electrical resistivity in the third region of the semiconductor layer that overlaps with the third conductive layer.

[0014] Alternatively, in the above embodiment, the second metal element may be titanium, tin, or zirconium.

[0015] Alternatively, in the above embodiment, the first metal element may be tin.

[0016] Alternatively, in the above aspect, the semiconductor device may have a sixth conductive layer and a seventh conductive layer, the sixth conductive layer being provided on the fourth conductive layer so as to fill the second opening, the seventh conductive layer being provided on the fifth conductive layer so as to fill the third opening, and the electrical conductivity of the sixth conductive layer being higher than the electrical conductivity of the fourth conductive layer, and the electrical conductivity of the seventh conductive layer being higher than the electrical conductivity of the fifth conductive layer.

[0017] Alternatively, in the above aspect, the semiconductor device may include a sixth conductive layer and a seventh conductive layer, the sixth conductive layer being provided on the fourth conductive layer so as to fill the second opening, and the seventh conductive layer being provided on the fifth conductive layer so as to fill the third opening, and the sixth conductive layer and the seventh conductive layer may each include tungsten, copper, aluminum, or molybdenum.

[0018] Alternatively, in the above aspect, the film thickness of the first conductive layer may be 1 / 5 or less of the film thickness of the semiconductor layer in a region overlapping with the first conductive layer, and the film thickness of the second conductive layer may be 1 / 5 or less of the film thickness of the semiconductor layer in a region overlapping with the second conductive layer.

[0019] Alternatively, in the above aspect, the semiconductor layer may have a second recess overlapping the second opening and a third recess overlapping the third opening, the fourth conductive layer may have a region in contact with an upper surface of the second recess of the semiconductor layer and a region in contact with a side surface of the second recess of the semiconductor layer, and the fifth conductive layer may have a region in contact with an upper surface of the third recess of the semiconductor layer and a region in contact with a side surface of the third recess of the semiconductor layer.

[0020] Alternatively, one embodiment of the present invention includes a first step of forming a semiconductor layer, a first conductive layer having a region in contact with a top surface of the semiconductor layer, and a first insulating layer having a region in contact with a top surface of the first conductive layer; a second step of processing the first insulating layer and the first conductive layer to form a first opening having a region overlapping with the semiconductor layer in the first insulating layer and to form a second conductive layer and a third conductive layer facing each other with the first opening between them; a third step of forming the second insulating layer and a fourth conductive layer over the second insulating layer so as to have a region located inside the first opening; a fourth step of processing the first insulating layer, the second conductive layer, and the third conductive layer to form a second opening reaching the semiconductor layer in the first insulating layer and the second conductive layer and to form a third opening reaching the semiconductor layer in the first insulating layer and the third conductive layer; a fifth step of forming a fifth conductive layer having a region located inside the third opening and a sixth conductive layer having a region located inside the third opening, so as to have a region in contact with the semiconductor layer; and a sixth step of performing heat treatment, wherein in the first step, the semiconductor layer is formed to contain indium oxide, and in the first step, the first conductive layer is formed to contain an oxide containing indium and a first metal element and to have a thickness thinner than that of the semiconductor layer, in the fifth step, the fifth conductive layer and the sixth conductive layer are formed to contain a second metal element, and in the sixth step, a first region and a second region containing the second metal element are formed in the semiconductor layer by heat treatment, and the first region is formed to have a region overlapping with the fifth conductive layer and the second region is formed to have a region overlapping with the sixth conductive layer.

[0021] Alternatively, in the above embodiment, the second metal element may be titanium, tin, or zirconium.

[0022] Alternatively, in the above embodiment, the first metal element may be tin.

[0023] Alternatively, in the above aspect, a seventh step of forming a seventh conductive layer on the fifth conductive layer and an eighth conductive layer on the sixth conductive layer may be performed after the fifth step and before the sixth step, and in the seventh step, the seventh conductive layer may be formed so as to fill the second opening, and the electrical conductivity of the seventh conductive layer may be higher than the electrical conductivity of the fifth conductive layer; and in the seventh step, the eighth conductive layer may be formed so as to fill the third opening, and the electrical conductivity of the eighth conductive layer may be higher than the electrical conductivity of the sixth conductive layer.

[0024] Alternatively, in the above aspect, a seventh step of forming a seventh conductive layer on the fifth conductive layer and an eighth conductive layer on the sixth conductive layer may be performed after the fifth step and before the sixth step, in which the seventh conductive layer is formed so as to fill the second opening, and in the seventh step the eighth conductive layer is formed so as to fill the third opening, and in the seventh step the seventh conductive layer and the eighth conductive layer may be formed so as to contain tungsten, copper, aluminum, or molybdenum, respectively.

[0025] Alternatively, in the above embodiment, in the first step, the first conductive layer may be formed so that its thickness is 1 / 5 or less of the thickness of the semiconductor layer.

[0026] According to one embodiment of the present invention, a semiconductor device or a storage device including a transistor with high on-state current can be provided. According to one embodiment of the present invention, a semiconductor device or a storage device including a transistor with favorable electrical characteristics can be provided. According to one embodiment of the present invention, a semiconductor device or a storage device with high operating speed can be provided. According to one embodiment of the present invention, a semiconductor device or a storage device with low manufacturing cost can be provided. According to one embodiment of the present invention, a highly reliable transistor, semiconductor device, or storage device can be provided. According to one embodiment of the present invention, a transistor, semiconductor device, or storage device that can be miniaturized or highly integrated can be provided. According to one embodiment of the present invention, a semiconductor device or a storage device with low power consumption can be provided. According to one embodiment of the present invention, a novel transistor, semiconductor device, or storage device can be provided.

[0027] According to one embodiment of the present invention, a method for manufacturing a semiconductor device or a memory device including a transistor with high on-state current can be provided. According to one embodiment of the present invention, a method for manufacturing a semiconductor device or a memory device including a transistor with favorable electrical characteristics can be provided. According to one embodiment of the present invention, a method for manufacturing a semiconductor device or a memory device with high operating speed can be provided. According to one embodiment of the present invention, a method for manufacturing a semiconductor device or a memory device with high yield can be provided. According to one embodiment of the present invention, a method for manufacturing a semiconductor device with high productivity can be provided. According to one embodiment of the present invention, a method for manufacturing a highly reliable transistor, semiconductor device, or memory device can be provided. According to one embodiment of the present invention, a method for manufacturing a transistor, semiconductor device, or memory device that can be miniaturized or highly integrated can be provided. According to one embodiment of the present invention, a method for manufacturing a semiconductor device or a memory device with low power consumption can be provided. According to one embodiment of the present invention, a method for manufacturing a novel transistor, semiconductor device, or memory device can be provided.

[0028] Note that the description of these effects does not preclude the existence of other effects. One embodiment of the present invention does not necessarily have all of these effects. Effects other than these can be extracted from the description in the specification, drawings, and claims.

[0029] FIG. 1A is a plan view showing a structural example of a semiconductor device. FIG. 1B is a cross-sectional view showing a structural example of a semiconductor device. FIGS. 2A and 2B are cross-sectional views showing a structural example of a semiconductor device. FIGS. 3A and 3B are cross-sectional views showing a structural example of a semiconductor device. FIG. 4A is a plan view showing a structural example of a semiconductor device. FIG. 4B is a cross-sectional view showing a structural example of a semiconductor device. FIG. 5A is a plan view showing a structural example of a semiconductor device. FIG. 5B is a cross-sectional view showing a structural example of a semiconductor device. FIG. 6A is a plan view showing a structural example of a semiconductor device. FIG. 6B is a cross-sectional view showing a structural example of a semiconductor device. FIG. 7A is a plan view showing a structural example of a semiconductor device. FIG. 7B is a cross-sectional view showing a structural example of a semiconductor device. FIG. 8A is a plan view showing an example of a method for manufacturing a semiconductor device. FIGS. 8B, 8C, and 8D are cross-sectional views showing an example of a method for manufacturing a semiconductor device. FIG. 9A is a plan view showing an example of a method for manufacturing a semiconductor device. FIGS. 9B, 9C, and 9D are cross-sectional views showing an example of a method for manufacturing a semiconductor device. FIG. 10A is a plan view showing an example of a method for manufacturing a semiconductor device. 10B, 10C, and 10D are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIG. 11A is a plan view illustrating an example of a method for manufacturing a semiconductor device. FIGS. 11B, 11C, and 11D are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIG. 12A is a plan view illustrating an example of a method for manufacturing a semiconductor device. FIGS. 12B, 12C, and 12D are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIG. 13A is a plan view illustrating an example of a method for manufacturing a semiconductor device. FIGS. 13B, 13C, and 13D are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIG. 14A is a plan view illustrating an example of a method for manufacturing a semiconductor device. FIGS. 14B, 14C, and 14D are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIG. 15A is a plan view illustrating an example of a method for manufacturing a semiconductor device. FIGS. 15B, 15C, and 15D are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIG. 16A is a plan view illustrating an example of a method for manufacturing a semiconductor device. 16B, 16C, and 16D are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. Fig. 17A is a plan view illustrating an example of a method for manufacturing a semiconductor device. Fig. 17B, 17C, and 17D are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. Fig. 18A and Fig. 18B are diagrams illustrating the carrier concentration dependence of Hall mobility.FIG. 18C is a cross-sectional view illustrating an indium oxide film. FIG. 19 is a block diagram illustrating a configuration example of a semiconductor device. FIGS. 20A, 20B, 20C, 20D, 20E, 20F, and 20G are diagrams illustrating an example of a circuit configuration of a memory cell. FIG. 21 is a cross-sectional view illustrating an example of a semiconductor device. FIGS. 22A and 22B are perspective views illustrating an example of a configuration of a semiconductor device. FIG. 23 is a cross-sectional view illustrating an example of a semiconductor device. FIG. 24 is a block diagram illustrating a CPU. FIGS. 25A and 25B are perspective views of a semiconductor device. FIGS. 26A and 26B are perspective views of a semiconductor device. FIG. 27 is a conceptual diagram illustrating the hierarchy of a memory device. FIGS. 28A and 28B are diagrams illustrating an example of electronic components. FIGS. 29A, 29B, and 29C are diagrams illustrating an example of a mainframe computer. FIG. 29D is a diagram illustrating an example of space equipment. FIG. 29E is a diagram illustrating an example of a storage system applicable to a data center.

[0030] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it will be readily understood by those skilled in the art that various changes can be made in form and detail without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments shown below.

[0031] In the configuration of the invention described below, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and repeated explanations thereof will be omitted. Furthermore, when referring to similar functions, the same hatching pattern may be used and no particular reference numeral may be assigned.

[0032] Furthermore, for ease of understanding, the position, size, range, etc. of each component shown in the drawings may not represent the actual position, size, range, etc. Therefore, the disclosed invention is not necessarily limited to the position, size, range, etc. disclosed in the drawings.

[0033] In this specification, ordinal numbers such as "first" and "second" are used to avoid confusion between components, and do not indicate any order or ranking, such as the order of processes, stacking order, or arrangement order. Furthermore, even if a term is not accompanied by an ordinal number in this specification, ordinal numbers may be accompanied in the claims to avoid confusion between components. Furthermore, even if a term is accompanied by an ordinal number in this specification, ordinal numbers may be accompanied by a different ordinal number in the claims. Furthermore, even if a term is accompanied by an ordinal number in this specification, ordinal numbers may be omitted in the claims.

[0034] A transistor is a type of semiconductor element that can perform functions such as amplifying current or voltage and performing a switching operation to control conduction or non-conduction. The term "transistor" as used herein includes an insulated gate field effect transistor (IGFET) and a thin film transistor (TFT).

[0035] In this specification and the like, a transistor using an oxide semiconductor or a metal oxide for a semiconductor layer and a transistor having an oxide semiconductor or a metal oxide for a channel formation region may be referred to as an OS (oxide semiconductor) transistor. A transistor having silicon for a channel formation region may be referred to as a Si transistor.

[0036] In this specification and the like, a transistor is an element having at least three terminals including a gate, a drain, and a source. A transistor has a region (also referred to as a channel formation region) where a channel is formed between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode), and current can flow between the source and the drain through the channel formation region. Note that in this specification and the like, the channel formation region refers to a region through which current mainly flows.

[0037] Furthermore, the functions of "source" and "drain" may be interchanged when transistors of different polarities are used, or when the direction of current flow changes during circuit operation, etc. Therefore, in this specification, the terms "source" and "drain" may be used interchangeably.

[0038] Note that impurities in a semiconductor refer to, for example, elements other than the main components constituting the semiconductor. For example, an element with a concentration of less than 0.1 atomic % can be considered an impurity. The presence of impurities may increase the density of defect states in the semiconductor or reduce the crystallinity, for example. When the semiconductor is an oxide semiconductor, impurities that change the characteristics of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components of the oxide semiconductor. Specific examples include hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. Note that water may also function as an impurity. For example, the inclusion of impurities may cause oxygen deficiency (V) in the oxide semiconductor. Ｏ (also called) may be formed.

[0039] In this specification and the like, an oxynitride refers to a material whose composition contains more oxygen than nitrogen. A nitride oxide refers to a material whose composition contains more nitrogen than oxygen. For example, silicon oxynitride refers to a material whose composition contains more oxygen than nitrogen, and silicon nitride oxide refers to a material whose composition contains more nitrogen than oxygen.

[0040] To analyze the content of elements such as hydrogen, oxygen, carbon, or nitrogen contained in a film, for example, secondary ion mass spectrometry (SIMS) or X-ray photoelectron spectroscopy (XPS) or electron spectroscopy for chemical analysis (ESCA) can be used. XPS is suitable when the content of the target element is high (e.g., 0.5 atomic% or more, or 1 atomic% or more). On the other hand, SIMS is suitable when the content of the target element is low (e.g., 0.5 atomic% or less, or 1 atomic% or less). When comparing the content of elements, it is more preferable to perform a combined analysis using both SIMS and XPS analytical methods.

[0041] In this specification and the like, the term "content" refers to the ratio of a component contained in a film. For example, when an oxide semiconductor layer contains a metal element X, a metal element Y, and a metal element Z, the number of atoms of each of the metal elements X, Y, and Z contained in the oxide semiconductor layer is expressed as A. Ｘ , A Ｙ , A Ｚ When the content of the metal element X is Ｘ / (A Ｘ +A Ｙ +A Ｚ In addition, the ratio of the number of atoms of the metal element X, the metal element Y, and the metal element Z in the oxide semiconductor layer (atomic ratio) can be expressed as follows: Ｘ : B Ｙ : B Ｚ When the content of the metal element X is expressed as B Ｘ / (B Ｘ +B Ｙ +B Ｚ ) can be shown as

[0042] It should be noted that the terms "film" and "layer" can be interchangeable depending on the circumstances. For example, the term "conductive layer" can be changed to the term "conductive film." Or, for example, the term "insulating film" can be changed to the term "insulating layer."

[0043] In this specification, space groups are expressed using short notation in international notation (or Hermann-Mauguin notation). Crystal planes and crystal orientations are expressed using Miller indices. In crystallography, space groups, crystal planes, and crystal orientations are expressed by adding a superscript bar to the numbers. However, in this specification, due to formatting restrictions, numbers may be expressed by adding a minus sign (-) before them instead of adding a bar above them. Individual orientations indicating directions within a crystal are expressed with [ ], collective orientations indicating all equivalent orientations are expressed with < >, individual planes indicating crystal planes are expressed with ( ), and collective planes with equivalent symmetry are expressed with {}.

[0044] Furthermore, in this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10 degrees or more and 10 degrees or less. Therefore, it also includes cases where the angle is -5 degrees or more and 5 degrees or less. Furthermore, "substantially parallel" refers to a state in which two straight lines are arranged at an angle of -20 degrees or more and 20 degrees or less. Furthermore, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, it also includes cases where the angle is 85 degrees or more and 95 degrees or less. Furthermore, "substantially perpendicular" refers to a state in which two straight lines are arranged at an angle of 70 degrees or more and 110 degrees or less.

[0045] In this specification and the like, the opening also includes, for example, a groove, a slit, and the like.

[0046] In this specification, "connection" includes, as an example, "electrical connection." Note that the term "electrical connection" is sometimes used to define the connection relationship between circuit elements as an object. Furthermore, "electrical connection" includes "direct connection" and "indirect connection." "A and B are directly connected" means that A and B are connected without the intervention of a circuit element (e.g., a transistor, a switch, etc.; wiring is not considered a circuit element). On the other hand, "A and B are indirectly connected" means that A and B are connected via one or more circuit elements.

[0047] For example, assuming that a circuit including A and B is operating, if there is a time during the operation of the circuit when an electrical signal is exchanged or an interaction of electrical potential occurs between A and B, then it can be defined that "A and B are indirectly connected" as objects. Note that even if there is a time during the operation of the circuit when no electrical signal is exchanged or an interaction of electrical potential occurs between A and B, it can still be defined that "A and B are indirectly connected" as long as there is a time during the operation of the circuit when an electrical signal is exchanged or an interaction of electrical potential occurs between A and B.

[0048] An example of a case where "A and B are indirectly connected" is when A and B are connected via the source and drain of one or more transistors. On the other hand, an example of a case where it cannot be said that "A and B are indirectly connected" is when an insulator is present in the path from A to B. Specifically, there are cases where a capacitive element is connected between A and B, and cases where a gate insulating film of a transistor is present between A and B. Therefore, it cannot be said that "the gate (A) of a transistor and the source or drain (B) of the transistor are indirectly connected."

[0049] Another example of a case where it cannot be said that "A and B are indirectly connected" is when multiple transistors are connected via their sources and drains to the path from A to B, and a constant potential V is supplied to a node between one transistor and another transistor from a power supply, GND, etc.

[0050] Unless otherwise specified, in this specification, the off-state current refers to a leakage current between the source and drain when a transistor is in an off state (also referred to as a non-conducting state or a cut-off state). Unless otherwise specified, the off-state refers to a state in which the gate-source voltage Vgs is lower than the threshold voltage Vth for an n-channel transistor (higher than Vth for a p-channel transistor).

[0051] In this specification and the like, a tapered shape refers to a shape in which at least a portion of the side surface of a structure is inclined with respect to the substrate surface or the surface to be formed. For example, it is preferable to have a region in which the angle (also called the taper angle) between the inclined side surface and the substrate surface or the surface to be formed is greater than 0 degrees and less than 90 degrees. Note that the side surface of the structure, the substrate surface, and the surface to be formed do not necessarily need to be completely flat, and may be approximately planar with a slight curvature or approximately planar with a slight unevenness.

[0052] In this specification, when it is stated that A is located on B, at least a portion of A is located on B. Therefore, for example, it can be rephrased as "A has a region located on B." Similarly, when it is stated that A contacts B or A overlaps B, at least a portion of A contacts B or overlaps B. Therefore, it can be rephrased as "A has a region contacting B" or "A has a region overlapping B," respectively. Similarly, in this specification, when it is stated that A covers B, at least a portion of A covers B. Therefore, for example, it can be rephrased as "A has a region covering B."

[0053] In this specification and the like, the term "island-like" refers to a state in which two or more layers made of the same material and formed in the same process are physically separated.

[0054] Embodiment 1 In this embodiment, a semiconductor device of one embodiment of the present invention will be described.

[0055] One embodiment of the present invention relates to a transistor having a semiconductor layer containing indium oxide and a semiconductor device including the transistor. When a metal oxide (also referred to as an oxide semiconductor) that functions as a semiconductor is used for the semiconductor layer, the higher the ratio of the number of indium atoms to the sum of the numbers of atoms of all metal elements contained in the metal oxide, the higher the field-effect mobility of the transistor. Therefore, by using indium oxide as the metal oxide in the semiconductor layer, the transistor can have a large on-state current and high frequency characteristics. Therefore, a semiconductor device with high operating speed can be realized.

[0056] In a transistor included in a semiconductor device according to one embodiment of the present invention, a source electrode and a drain electrode are spaced apart from each other so as to have a region in contact with a top surface of the semiconductor layer. When the source electrode and the drain electrode contain an element contained in the semiconductor layer, the band gaps of the source electrode and the drain electrode can be approximately equal to the band gap of the semiconductor layer. Specifically, when the main component of the source electrode and the drain electrode is the same as the main component of the semiconductor layer, the band gaps of the source electrode and the drain electrode can be approximately equal to the band gap of the semiconductor layer. This reduces the energy barrier between the source electrode and the drain electrode and the semiconductor layer. Therefore, the on-state current of the transistor can be increased, thereby realizing a semiconductor device with high operating speed. Specifically, an oxide containing indium and a first metal element can be used as the source electrode and the drain electrode. For example, tin can be used as the first metal element. When tin is used as the first metal element, an indium tin oxide (In—Sn oxide, also referred to as ITO) film is used as the source electrode and the drain electrode.

[0057] When the above-described oxide is used for the source electrode and the drain electrode, it is preferable not to provide a layer whose main component is different from that of the semiconductor layer on the layer containing the oxide (oxide layer). That is, it is preferable that the source electrode and the drain electrode have a single oxide layer structure rather than a stacked structure. This allows the semiconductor film that becomes the semiconductor layer and the conductive film that becomes the source electrode and the drain electrode to be processed under a single condition. Therefore, the number of manufacturing steps for the semiconductor device can be reduced compared to when the source electrode and the drain electrode have a stacked structure of, for example, two or more layers, and the productivity of the semiconductor device can be increased. Therefore, a semiconductor device with low manufacturing cost can be realized.

[0058] An insulating layer is provided on the source electrode and the drain electrode. The insulating layer can be provided so as to cover the source electrode, the drain electrode, and the semiconductor layer. The insulating layer has a region in contact with the top surface of the oxide layer in the source electrode and a region in contact with the top surface of the oxide layer in the drain electrode.

[0059] The insulating layer has a first opening in a region between the source electrode and the drain electrode in a plan view. The gate insulating layer and the gate electrode are provided so as to have a region located inside the first opening. After the first opening is formed, the source electrode and the drain electrode are formed by processing the conductive layer that will become the source electrode and the drain electrode using the same mask pattern as that used to form the first opening. Specifically, first, a semiconductor layer, a conductive layer that will become the source electrode and the drain electrode, and an insulating layer are formed. Next, a first opening is formed in the insulating layer. After that, the region of the conductive layer that overlaps with the first opening is removed. In this manner, the source electrode and the drain electrode are formed.

[0060] Here, when the conductive layer to be the source electrode and the drain electrode contains an element contained in the semiconductor layer, the etching selectivity between the conductive layer and the semiconductor layer decreases. Specifically, when the main component of the conductive layer to be the source electrode and the drain electrode is the same as the main component of the semiconductor layer, the etching selectivity between the conductive layer and the semiconductor layer decreases. Therefore, when the thickness of the conductive layer to be the source electrode and the drain electrode is thicker than the thickness of the semiconductor layer, the semiconductor layer may be divided by processing the conductive layer.

[0061] Therefore, it is preferable that the thickness of the conductive layer that will become the source and drain electrodes is thinner than the thickness of the semiconductor layer. This prevents the semiconductor layer from being divided by the formation of the source and drain electrodes. Therefore, a semiconductor device can be manufactured with a high yield, and a semiconductor device can be manufactured at low cost. Note that, since the etching selectivity between the semiconductor layer and the conductive layer that will become the source and drain electrodes is low, the semiconductor layer has a recess at a position that overlaps with the first opening.

[0062] The thickness of the source electrode and the drain electrode is set to be at least thinner than the thickness of the semiconductor layer, specifically, the thickness of the semiconductor layer in the region overlapping with the source electrode or the drain electrode. For example, the thickness of the source electrode is set to be ½ or less, preferably ⅕ or less, of the thickness of the semiconductor layer in the region overlapping with the source electrode. Similarly, the thickness of the drain electrode is set to be ½ or less, preferably ⅕ or less, of the thickness of the semiconductor layer in the region overlapping with the drain electrode. This is preferable because it can prevent the semiconductor layer from being divided.

[0063] The insulating layer has a second opening and a third opening. The second and third openings have an area overlapping with the semiconductor layer and are provided opposite each other with the first opening in between. A first plug is provided inside the second opening, and a second plug is provided inside the third opening. The first plug is connected to the source electrode, and the second plug is connected to the drain electrode.

[0064] As described above, the film thickness of the source electrode and the drain electrode is thin. Therefore, in one embodiment of the present invention, the second and third openings reach the semiconductor layer. In this case, the second opening is also formed in the source electrode, and the third opening is also formed in the drain electrode. Therefore, the first plug and the second plug have regions in contact with the semiconductor layer. Therefore, the material contained in the first plug and the material contained in the second plug can be diffused into the semiconductor layer. For example, after the first plug and the second plug are formed, heat treatment can be performed to diffuse the above-mentioned materials into the semiconductor layer. Therefore, the material contained in the first plug and the material contained in the second plug can be supplied to the semiconductor layer as impurity elements.

[0065] In a semiconductor device according to one embodiment of the present invention, the first plug and the second plug contain an element that forms a low-resistance region when contained in the semiconductor layer. This can reduce contact resistance between the first plug and the semiconductor layer and the second plug. Therefore, the on-state current of a transistor can be increased, and a semiconductor device with high operating speed can be realized.

[0066] A second metal element, such as titanium, tin, or zirconium, can be used for the first and second plugs. The first plug and the second plug can each have a stacked structure of two or more layers. In this case, the second metal element is used for the layer that contacts the semiconductor layer among the layers that make up the first plug. Similarly, the second metal element is used for the layer that contacts the semiconductor layer among the layers that make up the second plug.

[0067] <Structural Example 1 of Semiconductor Device> A structural example of a semiconductor device of one embodiment of the present invention will be described below.

[0068] 1A is a plan view of a semiconductor device including a transistor 200. Note that some elements are omitted from the plan view of FIG. 1A for clarity. Some elements may also be omitted from the subsequent plan views.

[0069] Fig. 1B is a cross-sectional view taken along dashed dotted line A1-A2 in Fig. 1A and is also a cross-sectional view in the channel length direction of transistor 200. Fig. 2A is a cross-sectional view taken along dashed dotted line A3-A4 in Fig. 1A and is also a cross-sectional view in the channel width direction of transistor 200. Fig. 2B is a cross-sectional view taken along dashed dotted line A5-A6 in Fig. 1A.

[0070] 1A to 2B includes an insulating layer 212 over a substrate (not shown), an insulating layer 214 over the insulating layer 212, a transistor 200, an insulating layer 216, a conductive layer 245a, a conductive layer 245b, a conductive layer 246a, and a conductive layer 246b over the insulating layer 214, an insulating layer 275 over the insulating layer 216, an insulating layer 280 over the insulating layer 275, an insulating layer 282 over the transistor 200 and the insulating layer 280, an insulating layer 283 over the insulating layer 282, and an insulating layer 285 over the insulating layer 283. The insulating layer 212, the insulating layer 214, the insulating layer 216, the insulating layer 280, the insulating layer 282, the insulating layer 283, and the insulating layer 285 function as interlayer insulating layers. Note that FIG. 2B shows a configuration example of a region including the conductive layer 245b and the conductive layer 246b.

[0071] The transistor 200 includes a conductive layer 205, an insulating layer 221 over the conductive layer 205, an insulating layer 222 over the insulating layer 221, an insulating layer 224 over the insulating layer 222, a semiconductor layer 230 over the insulating layer 224, an insulating layer 250, a conductive layer 242a, and a conductive layer 242b over the semiconductor layer 230, and a conductive layer 260 over the insulating layer 250. 1A to 2B show an example in which the insulating layer 224, the semiconductor layer 230, the conductive layer 242a, and the conductive layer 242b are processed into island shapes.

[0072] The semiconductor layer 230 includes a metal oxide (also referred to as an oxide semiconductor) that functions as a semiconductor. Here, a transistor including an oxide semiconductor is referred to as an OS transistor. Note that in this specification and the like, a semiconductor layer including an oxide semiconductor can be alternatively referred to as an oxide semiconductor layer. Furthermore, since the semiconductor layer 230 includes a metal oxide, the semiconductor layer 230 can be alternatively referred to as a metal oxide layer. In the semiconductor device of one embodiment of the present invention, indium oxide can be used as the semiconductor layer 230, for example.

[0073] When the semiconductor layer is a metal oxide layer, the higher the ratio of the number of indium atoms to the sum of the numbers of atoms of all metal elements contained in the metal oxide layer, the higher the field-effect mobility of the transistor. Therefore, by using indium oxide for the semiconductor layer 230, the transistor 200 can achieve a large on-state current and high frequency characteristics. Therefore, a semiconductor device with high operating speed can be realized. Details of indium oxide will be described in Embodiment 2.

[0074] The conductive layer 260 functions as a first gate electrode (also referred to as an upper gate electrode or a top gate electrode) of the transistor 200. The insulating layer 250 functions as a first gate insulating layer of the transistor 200. At least a part of a region of the semiconductor layer 230 that overlaps with the conductive layer 260 functions as a channel formation region 230i of the transistor 200.

[0075] The conductive layer 205 functions as a second gate electrode (also referred to as a lower gate electrode or a bottom gate electrode) of the transistor 200. The insulating layers 224, 222, and 221 each function as a second gate insulating layer of the transistor 200. The conductive layer 242a functions as one of the source and drain electrodes of the transistor 200. The conductive layer 242b functions as the other of the source and drain electrodes of the transistor 200.

[0076] The conductive layers 242a and 242b are spaced apart from each other so as to have a region in contact with the top surface of the semiconductor layer 230. When the conductive layers 242a and 242b contain an element contained in the semiconductor layer 230, the band gaps of the conductive layers 242a and 242b can be made substantially equal to the band gap of the semiconductor layer 230. Specifically, when the main component of the conductive layers 242a and 242b is the same as the main component of the semiconductor layer 230, the band gaps of the conductive layers 242a and 242b can be made substantially equal to the band gap of the semiconductor layer 230. This can reduce the energy barrier between the conductive layers 242a and 242b and the semiconductor layer 230. Therefore, the on-state current of the transistor 200 can be increased, and a semiconductor device with high operating speed can be realized. When indium oxide is used for the semiconductor layer 230, the conductive layers 242a and 242b can be formed using, for example, an oxide containing indium and a first metal element. For example, tin can be used as the first metal element. When tin is used as the first metal element, an ITO film can be used as the conductive layers 242a and 242b.

[0077] When the conductive layers 242a and 242b are made of the oxide, it is preferable that a layer containing a different main component from that of the semiconductor layer 230 is not provided on the layer containing the oxide (oxide layer). That is, the conductive layers 242a and 242b preferably have a single oxide layer structure rather than a stacked structure. As described above, the semiconductor film that will become the semiconductor layer 230 and the conductive film that will become the conductive layers 242a and 242b can be processed under a single condition, as will be described in detail later. Therefore, the number of manufacturing steps for the semiconductor device can be reduced compared to when the conductive layers 242a and 242b have a stacked structure of, for example, two or more layers, and the productivity of the semiconductor device can be increased. Therefore, a semiconductor device with low manufacturing cost can be realized. Furthermore, by forming the conductive layers 242a and 242b as a single oxide layer, absorption of oxygen contained in the oxide layer can be suppressed. Therefore, a decrease in the reliability of the semiconductor device can be suppressed in some cases.

[0078] The insulating layer 275 has a region in contact with the top surface of the conductive layer 242a and a region in contact with the top surface of the conductive layer 242b. Specifically, the insulating layer 275 has a region in contact with the top surface of the oxide layer. The insulating layer 275 can be provided to cover the conductive layer 242a, the conductive layer 242b, the semiconductor layer 230, and the insulating layer 224. As described above, the insulating layer 280 is provided over the insulating layer 275.

[0079] The insulating layer 280 is preferably made of an insulating material that releases oxygen when heat is applied. When heat is applied during the manufacturing process of the semiconductor device, the insulating layer 280 releases oxygen, and the oxygen can be supplied to the semiconductor layer 230 through the insulating layer 250. By supplying oxygen to the semiconductor layer 230, particularly the channel formation region 230i, oxygen vacancies or defects in which hydrogen has entered the oxygen vacancies (hereinafter referred to as V Ｏ H) can be reduced. Therefore, the transistor 200 can have favorable electrical characteristics and high reliability.

[0080] Since the insulating layer 280 functions as an interlayer insulating layer, it is preferable to use a material with a low dielectric constant. By using a material with a low dielectric constant for the interlayer insulating layer, it is possible to reduce the parasitic capacitance that occurs between wirings. In addition, it is preferable to reduce the concentration of impurities such as water and hydrogen in the insulating layer 280. This makes it possible to suppress the intrusion of impurities such as hydrogen or water into the channel formation region of the semiconductor layer 230. For example, silicon oxide or silicon oxynitride can be used as the insulating layer 280.

[0081] Insulating layer 275 and insulating layer 280 have an opening 289 in a region between conductive layer 242a and conductive layer 242b in a plan view. Insulating layer 250 and conductive layer 260 are provided so as to have a region located inside opening 289. Figures 1B and 2A show an example in which the top surface of insulating layer 280, the top edge of insulating layer 250, and the top surface of conductive layer 260 are flush or approximately flush with each other.

[0082] Although the details will be described later, the conductive layers 242a and 242b are formed by processing the conductive layers that will become the conductive layers 242a and 242b after the openings 289 are formed. Specifically, first, the semiconductor layer 230, the conductive layers that will become the conductive layers 242a and 242b, the insulating layers 275, and the insulating layers 280 are formed. Next, the openings 289 are formed in the insulating layers 280 and 275. After that, the regions of the conductive layers that will become the conductive layers 242a and 242b that overlap with the openings 289 are removed. In this manner, the conductive layers 242a and 242b are formed.

[0083] Here, when the conductive layers to become the conductive layers 242a and 242b contain an element contained in the semiconductor layer 230, the etching selectivity between the conductive layers to become the conductive layers 242a and 242b and the semiconductor layer 230 decreases. Specifically, when the main component of the conductive layers to become the conductive layers 242a and 242b is the same as the main component of the semiconductor layer 230, the etching selectivity between the conductive layers and the semiconductor layer 230 decreases. Therefore, when the thickness of the conductive layers to become the conductive layers 242a and 242b is thicker than the thickness of the semiconductor layer 230, processing the conductive layers to become the conductive layers 242a and 242b may cause the semiconductor layer 230 to be divided.

[0084] Therefore, it is preferable that the thickness of the conductive layer that will become the conductive layer 242a and the conductive layer 242b is thinner than the thickness of the semiconductor layer 230. This can prevent the semiconductor layer 230 from being divided by the formation of the conductive layer 242a and the conductive layer 242b. Therefore, a semiconductor device can be manufactured by a method with a high yield, and therefore a semiconductor device can be manufactured at low cost. Note that, since the etching selectivity between the semiconductor layer 230 and the conductive layer that will become the conductive layer 242a and the conductive layer 242b is low, the semiconductor layer 230 has a recess 287 at a position that overlaps with the opening 289.

[0085] The thicknesses of the conductive layers 242a and 242b are set to be at least thinner than the thickness of the semiconductor layer 230. Specifically, the thickness of the conductive layer 242a is set to be thinner than the thickness of the semiconductor layer 230 in a region overlapping with the conductive layer 242a. The thickness of the conductive layer 242b is set to be thinner than the thickness of the semiconductor layer 230 in a region overlapping with the conductive layer 242b. For example, the thickness of the conductive layer 242a is preferably ½ or less, more preferably ⅓ or less, and even more preferably ⅕ or less, of the thickness of the semiconductor layer 230 in a region overlapping with the conductive layer 242a. Similarly, for example, the thickness of the conductive layer 242b is preferably ½ or less, more preferably ⅓ or less, and even more preferably ⅕ or less, of the thickness of the semiconductor layer 230 in a region overlapping with the conductive layer 242b. As a result, the semiconductor layer 230 can be prevented from being divided. On the other hand, if the film thicknesses of the conductive layers 242a and 242b are too thin, the electrical resistance of the conductive layers 242a and 242b will be high. Therefore, the film thickness of the conductive layer 242a is preferably, for example, 1 / 20 or more, more preferably 1 / 15 or more, and even more preferably 1 / 10 or more of the film thickness of the semiconductor layer 230 in the region overlapping with the conductive layer 242a. Similarly, the film thickness of the conductive layer 242b is preferably, for example, 1 / 20 or more, more preferably 1 / 15 or more, and even more preferably 1 / 10 or more of the film thickness of the semiconductor layer 230 in the region overlapping with the conductive layer 242b.

[0086] From the above, the thickness of the conductive layer 242a is preferably from 1 / 20 to 1 / 2, more preferably from 1 / 15 to 1 / 3, and still more preferably from 1 / 10 to 1 / 5 of the thickness of the conductive layer 242a in the region overlapping with the conductive layer 242a of the semiconductor layer 230. Similarly, the thickness of the conductive layer 242b is preferably from 1 / 20 to 1 / 2, more preferably from 1 / 15 to 1 / 3, and still more preferably from 1 / 10 to 1 / 5 of the thickness of the conductive layer 242b in the region overlapping with the conductive layer 242b of the semiconductor layer 230.

[0087] The thickness of the conductive layer 242a and the conductive layer 242b is preferably from 0.1 nm to 5 nm, more preferably from 0.5 nm to 4 nm, and further preferably from 1 nm to 3 nm. The thickness of the semiconductor layer 230 in a region overlapping with the conductive layer 242a or the conductive layer 242b is preferably from 5 nm to 50 nm, more preferably from 5 nm to 30 nm, more preferably from 5 nm to 20 nm, and further preferably from 5 nm to 10 nm.

[0088] The insulating layer 250 is provided inside the opening 289 so as to have a region in contact with the upper surface of the recess 287 of the semiconductor layer 230. The insulating layer 250 can have a region in contact with the side surface of the recess 287 of the semiconductor layer 230, a region in contact with the side surface of the conductive layer 242a, a region in contact with the side surface of the conductive layer 242b, a region in contact with the side surface of the insulating layer 275 in the opening 289, a region in contact with the side surface of the insulating layer 280 in the opening 289, a region in contact with the side surface of the insulating layer 224, and a region in contact with the upper surface of the insulating layer 222.

[0089] In this specification, in a layer having a recess, the upper surface inside the recess can be referred to as the bottom surface of the recess. Also, in a layer having a recess, the side surface inside the recess can be referred to as the side wall of the recess. Furthermore, in a layer having an opening, the side surface inside the opening can be referred to as the side wall of the opening.

[0090] The insulating layer 250 can be made of an insulating material described in the section [Insulating Layer] below.

[0091] 1B and 2A show an example in which the insulating layer 250 has a single-layer structure. Note that the insulating layer 250 can have a stacked structure of two or more layers. In this case, the insulating layer 250 is preferably formed of two or more types of films. By forming the insulating layer 250 using two or more types of films, multiple functions can be imparted to the insulating layer 250. Examples of the functions of the insulating layer 250 include a function of extracting excess oxygen from the semiconductor layer 230, a function of extracting hydrogen from the semiconductor layer 230, and a function of suppressing diffusion of hydrogen into the semiconductor layer 230.

[0092] The insulating layer 250 is preferably a thin film. For example, by setting the thickness of the insulating layer 250 to 1 nm or more and 20 nm or less, preferably 3 nm or more and 10 nm or less, the subthreshold swing value (also referred to as S value) can be reduced. Note that the S value refers to the amount of change in gate voltage when the drain current is changed by one order of magnitude while the drain voltage is constant in the subthreshold region.

[0093] The insulating layer 250 can have, for example, a four-layer structure in which an aluminum oxide film, a hafnium oxide film, a silicon oxide film, and a silicon nitride film are stacked in this order from the semiconductor layer 230 side. The thicknesses of the aluminum oxide film, the hafnium oxide film, the silicon oxide film, and the silicon nitride film are 1 nm, 2 nm, 2 nm, and 1 nm, respectively. With this structure, excess oxygen in the semiconductor layer 230 can be discharged to the insulating layer 250, thereby reducing the amount of excess oxygen in the semiconductor layer 230. Furthermore, hydrogen in the semiconductor layer 230 can be captured or fixed. Therefore, the electrical characteristics and reliability of the transistor 200 can be improved.

[0094] In addition, in forming the insulating layer 250 having a stacked structure of multiple insulating films, it is preferable to use the atomic layer deposition (ALD) method two or more times. For example, it is preferable that two or more of the multiple insulating films included in the insulating layer 250 are formed using the ALD method. By forming at least two or more types of insulating films using the ALD method, it is possible to improve the coverage and film thickness uniformity of the insulating layer 250. Furthermore, for example, it is possible to increase productivity by successively forming two or more types of insulating films using the ALD method.

[0095] The conductive layer 260 is provided on the insulating layer 250 so as to have a region located inside the opening 289. In the examples shown in Figures 1A, 1B, and 2A, the conductive layer 260 is provided so as to fill the opening 289.

[0096] 1A and 2A, the conductive layer 260 is preferably provided to extend in the channel width direction of the transistor 200. With this structure, when a plurality of transistors 200 are provided in a semiconductor device, the conductive layer 260 functions as a wiring.

[0097] The conductive layer 260 can be formed using a conductive material described in the section "Conductive Layer" below. The conductive layer 260 is preferably formed using a conductive material containing, for example, tungsten, copper, or aluminum as a main component. The conductive layer 260 may also have a stacked structure. For example, the conductive layer 260 can have a stacked structure of a titanium nitride film and a tungsten film over the titanium nitride film.

[0098] Insulating layer 282 is located on insulating layer 280, insulating layer 250, and conductive layer 260. Also, insulating layer 283 is located on insulating layer 282, and insulating layer 285 is located on insulating layer 283, as described above.

[0099] The insulating layer 275, the insulating layer 280, the insulating layer 282, the insulating layer 283, and the insulating layer 285 have openings 243a and 243b. The openings 243a and 243b have regions overlapping with the semiconductor layer 230 and are provided opposite to each other with an opening 289 interposed therebetween. A conductive layer 245a and a conductive layer 246a over the conductive layer 245a are provided inside the opening 243a. A conductive layer 245b and a conductive layer 246b over the conductive layer 245b are provided inside the opening 243b.

[0100] 1A shows an example in which the shape of openings 243a and 243b in a plan view is circular. Note that in this specification, a circle is not limited to a perfect circle. Furthermore, the shape of openings 243a and 243b in a plan view does not have to be circular, and can be, for example, a substantially circular shape such as an ellipse, a polygonal shape such as a square, or a polygonal shape such as a square with rounded corners.

[0101] The conductive layer 245a and the conductive layer 246a function as plugs connected to the conductive layer 242a. The conductive layer 245b and the conductive layer 246b function as plugs connected to the conductive layer 242b. The conductive layer 242a, which functions as one of the source and drain electrodes of the transistor 200, can be connected to, for example, a wiring (not shown) over the insulating layer 285 through the conductive layer 245a and the conductive layer 246a. The conductive layer 242b, which functions as the other of the source and drain electrodes of the transistor 200, can be connected to, for example, a wiring (not shown) over the insulating layer 285 through the conductive layer 245b and the conductive layer 246b.

[0102] Hereinafter, the conductive layers having a region located inside the opening 243a may be collectively referred to as a first plug. That is, in the examples shown in FIGS. 1A and 1B, the conductive layers 245a and 246a are collectively referred to as a first plug. Similarly, the conductive layers having a region located inside the opening 243b may be collectively referred to as a second plug. That is, in the examples shown in FIGS. 1A, 1B, and 2B, the conductive layers 245b and 246b are collectively referred to as a second plug. Note that the first plug and the second plug may be included as components of the transistor 200. In this case, the first plug functions as one of the source electrode and drain electrode of the transistor 200. The second plug functions as the other of the source electrode and drain electrode of the transistor 200.

[0103] As described above, the conductive layers 242a and 242b are thin. Therefore, in one embodiment of the present invention, in the process of forming the openings 243a and 243b, part of the conductive layer 242a and part of the conductive layer 242b are removed, so that the openings 243a and 243b reach the semiconductor layer 230. In this case, the opening 243a is also formed in the conductive layer 242a, and the opening 243b is also formed in the conductive layer 242b. Therefore, the conductive layers 245a and 245b have regions in contact with the semiconductor layer 230. Therefore, the material contained in the conductive layer 245a and the material contained in the conductive layer 245b can be diffused into the semiconductor layer 230. For example, by performing heat treatment after the formation of the conductive layers 245a and 245b, the above-described materials can be diffused into the semiconductor layer. Therefore, the material contained in the conductive layer 245a and the material contained in the conductive layer 245b can be supplied to the semiconductor layer 230 as impurity elements. Note that the impurity element can also be supplied to the conductive layers 242a and 242b.

[0104] The conductive layer 245a and the conductive layer 245b contain an element that forms a low-resistance region when contained in the semiconductor layer 230. In FIG. 1B , the low-resistance region formed in the region of the semiconductor layer 230 that contacts the conductive layer 245a and in the region nearby is referred to as a low-resistance region 230na. In addition, in FIG. 1B and FIG. 2B , the low-resistance region formed in the region of the semiconductor layer 230 that contacts the conductive layer 245b and in the region nearby is referred to as a low-resistance region 230nb. Similar descriptions are used in the subsequent drawings.

[0105] The low-resistance region 230na functions as one of the source region and the drain region of the transistor 200. The low-resistance region 230nb functions as the other of the source region and the drain region of the transistor 200.

[0106] The concentration of the element contained in the conductive layer 245a in the low-resistance region 230na is higher than the concentration of the element contained in the conductive layer 245a in the channel formation region 230i. Similarly, the concentration of the element contained in the conductive layer 245b in the low-resistance region 230nb is higher than the concentration of the element contained in the conductive layer 245b in the channel formation region 230i.

[0107] By forming the low-resistance region 230na in the semiconductor layer 230, the contact resistance between the conductive layer 245a and the semiconductor layer 230 can be made smaller than when the low-resistance region 230na is not formed. Similarly, by forming the low-resistance region 230nb in the semiconductor layer 230, the contact resistance between the conductive layer 245b and the semiconductor layer 230 can be made smaller than when the low-resistance region 230nb is not formed. As a result, the on-current of the transistor 200 can be increased, thereby realizing a semiconductor device with high operating speed.

[0108] Furthermore, when the semiconductor layer 230 has a low-resistance region 230na, even if the conductive layer 245a does not contact the conductive layer 242a or the area of ​​the contact region is small, the conductive layer 242a and the conductive layer 245a can be connected via the low-resistance region 230na. Similarly, when the semiconductor layer 230 has a low-resistance region 230nb, even if the conductive layer 245b does not contact the conductive layer 242b or the area of ​​the contact region is small, the conductive layer 242b and the conductive layer 245b can be connected via the low-resistance region 230nb. For example, when the film thickness of the conductive layer 242a is thin, the contact area between the conductive layer 245a and the conductive layer 242a becomes small. Similarly, when the film thickness of the conductive layer 242b is thin, the contact area between the conductive layer 245b and the conductive layer 242b becomes small. Even in the above case, by forming the low resistance region 230na and the low resistance region 230nb in the semiconductor layer 230, the conductive layer 242a and the conductive layer 245a can be connected, and the conductive layer 242b and the conductive layer 245b can be connected.

[0109] The electrical resistivity of the low-resistance region 230na and the low-resistance region 230nb is lower than the electrical resistivity of at least the channel formation region 230i. The lower the electrical resistivity of the low-resistance region 230na and the low-resistance region 230nb, the more preferable. The electrical resistivity of the low-resistance region 230na and the low-resistance region 230nb is, for example, 1×10 −５ Ω・m or more 1×10 −３ It can be made Ω·m or less.

[0110] The conductive layer 245a and the conductive layer 245b can contain a second metal element, specifically, a metal element that generates carriers when supplied to the semiconductor layer 230. The low-resistance region 230na and the low-resistance region 230nb can be regions where the carriers are generated.

[0111] When titanium, tin, or zirconium, for example, is used for the conductive layer 245a and the conductive layer 245b, these metal elements can be supplied to the semiconductor layer 230 as impurity elements, and some of the elements contained in the semiconductor layer 230 can be replaced with the impurity elements. For example, when indium oxide is used for the semiconductor layer 230, some of the indium can be replaced with the impurity elements. Since the valence of the above-mentioned impurity elements is different from the valence of indium, for example, by replacing the indium contained in the semiconductor layer 230 with the above-mentioned impurity elements, a shallow donor level is easily formed. That is, the donor level is easily formed so that the difference between the energy of the conduction band minimum (CBM) and the donor level is small. For example, when titanium is added as an impurity element to the semiconductor layer 230, the energy gap between the CBM and the donor level can be set to 0.25 eV. This makes it possible to realize a transistor with high field-effect mobility.

[0112] The concentration of the metal element contained in at least one of the low resistance region 230na, the low resistance region 230nb, and the channel formation region 230i can be measured by, for example, inductively coupled plasma mass spectrometry (ICP-MS), XPS, SIMS, time-of-flight secondary ion mass spectrometry (ToF-SIMS), Auger electron spectroscopy (AES), energy dispersive X-ray spectroscopy (EDX), or the like. The evaluation can be performed using, for example, plasma atomic emission spectroscopy (ICP-AES), inductively coupled plasma atomic emission spectroscopy (ICP-AES), or the like.

[0113] Here, the boundary between the low-resistance region 230na and the conductive layer 242a, and the boundary between the low-resistance region 230nb and the conductive layer 242b may not be clearly visible in an electron microscope image, such as a scanning transmission electron microscope (STEM) image. In this case, the boundary between the low-resistance region 230na and the conductive layer 242a, and the boundary between the low-resistance region 230nb and the conductive layer 242b can be defined based on the content of the second metal element described above. Specifically, a region where the content of the second metal element is less than a predetermined value can be defined as the low-resistance region 230na or the low-resistance region 230nb, and a region where the content is equal to or greater than the predetermined value can be defined as the conductive layer 242a or the conductive layer 242b. For example, a region where the content of the second metal element measured using EDX is less than 3 atomic % can be designated as low resistance region 230na or low resistance region 230nb, and a region where the content is 3 atomic % or more can be designated as conductive layer 242a or conductive layer 242b. Here, the content of the second metal element in a predetermined region refers to the ratio of the number of atoms of the second metal element to the sum of the numbers of atoms of all metal elements contained in the predetermined region.

[0114] Note that the conductive layer 245a and the conductive layer 245b may contain a compound of a metal element that generates carriers when supplied to the semiconductor layer 230. For example, the conductive layer 245a and the conductive layer 245b may contain a nitride or an oxide of the metal element. For example, the conductive layer 245a and the conductive layer 245b may contain titanium nitride or titanium oxide. Furthermore, the conductive layer 245a and the conductive layer 245b may each have a stacked structure of two or more layers.

[0115] 1A and 1B show an example in which the conductive layer 245a is provided along the sidewall of the opening 243a. Also, FIGS. 1A, 1B, and 2B show an example in which the conductive layer 245b is provided along the sidewall of the opening 243b. In the above cases, the conductive layer 245a can have a region in contact with the side surface of the conductive layer 242a in the opening 243a, a region in contact with the side surface of the insulating layer 275 in the opening 243a, a region in contact with the side surface of the insulating layer 280 in the opening 243a, a region in contact with the side surface of the insulating layer 282 in the opening 243a, a region in contact with the side surface of the insulating layer 283 in the opening 243a, and a region in contact with the side surface of the insulating layer 285 in the opening 243a. Similarly, the conductive layer 245b can have a region in contact with the side surface of the conductive layer 242b in the opening 243b, a region in contact with the side surface of the insulating layer 275 in the opening 243b, a region in contact with the side surface of the insulating layer 280 in the opening 243b, a region in contact with the side surface of the insulating layer 282 in the opening 243b, a region in contact with the side surface of the insulating layer 283 in the opening 243b, and a region in contact with the side surface of the insulating layer 285 in the opening 243b. Furthermore, a configuration can be adopted in which the conductive layer 246a is not in contact with the side wall of the opening 243a, and the conductive layer 246b is not in contact with the side wall of the opening 243b.

[0116] As shown in FIG. 1B , the conductive layer 246a can be provided over the conductive layer 245a so as to fill the opening 243a. Furthermore, as shown in FIGS. 1B and 2B , the conductive layer 246b can be provided over the conductive layer 245b so as to fill the opening 243b. Note that FIG. 1B illustrates an example in which the top surface of the insulating layer 285, the top end of the conductive layer 245a, the top end of the conductive layer 245b, the top surface of the conductive layer 246a, and the top surface of the conductive layer 246b are aligned or substantially aligned. As will be described in detail later, after the openings 243a and 243b are formed, a first conductive film to be the conductive layers 245a and 245b and a second conductive film to be the conductive layers 246a and 246b are sequentially formed, and these conductive films are subjected to planarization treatment, thereby forming the conductive layers 245a, 245b, 246a, and 246b shown in FIG. 1B and the like.

[0117] Here, it is preferable to use a material for the conductive layer 246a that has a higher electrical conductivity than the conductive layer 245a. Similarly, it is preferable to use a material for the conductive layer 246b that has a higher electrical conductivity than the conductive layer 245b. This makes it possible to lower the electrical resistance of the first plug than when, for example, only the conductive layer 245a is used as the first plug. Similarly, it is possible to lower the electrical resistance of the second plug than when, for example, only the conductive layer 245b is used as the second plug. As a result, a semiconductor device with high operating speed can be realized.

[0118] The conductive layers 246a and 246b are preferably made of a conductive material containing tungsten, copper, aluminum, or molybdenum as a main component. The electrical conductivity of tungsten, copper, aluminum, and molybdenum is higher than that of, for example, titanium. Therefore, the electrical resistance of the first plug and the second plug can be lower than when, for example, the first plug and the second plug are made of titanium alone.

[0119] The thickness of the conductive layer 245a is preferably thinner than the thickness of the conductive layer 246a. Similarly, the thickness of the conductive layer 245b is preferably thinner than the thickness of the conductive layer 246b. For example, the thickness of the conductive layer 245a is preferably thinner than the thickness of the conductive layer 246a, and the thickness of the conductive layer 245b is preferably thinner than the thickness of the conductive layer 246b. This allows the electrical resistance of the first plug and the second plug to be reduced while forming the low-resistance regions 230na and 230nb in the semiconductor layer 230. The thicknesses of the conductive layers 245a and 245b are preferably 0.1 nm to 50 nm, more preferably 0.5 nm to 30 nm, and even more preferably 1 nm to 10 nm.

[0120] In this specification, the film thickness of a layer provided to fill an opening indicates the width of the layer. For example, the film thickness of the conductive layer 246a and the conductive layer 246b can be the length of the conductive layer 246a and the conductive layer 246b, respectively, in a direction parallel to the reference plane. For example, if the conductive layer 246a and the conductive layer 246b have a circular shape in a planar view, the diameter can be the film thickness of the conductive layer 246a and the conductive layer 246b. Note that if the sidewall of the opening 243a has a tapered shape, the width of the conductive layer 246a varies depending on the location. For example, the width of the bottom surface of the conductive layer 246a is different from the width of the top surface. In this case, for example, the maximum width value can be used as the width of the conductive layer 246a. Note that the minimum width value can be used as the width of the conductive layer 246a, or the average of the maximum and minimum values ​​can be used as the width of the conductive layer 246a. The same applies to the conductive layer 246b.

[0121] In this specification and the like, the reference surface can be, for example, the upper surface of a substrate or the upper surface of an interlayer insulating layer.

[0122] The thickness of the conductive layer 245a may be equal to or greater than the thickness of the conductive layer 246a. Similarly, the thickness of the conductive layer 245b may be equal to or greater than the thickness of the conductive layer 246b. For example, when the width of the opening 243a is small, the thickness of the conductive layer 245a may be equal to or greater than the thickness of the conductive layer 246a. Similarly, when the width of the opening 243b is small, the thickness of the conductive layer 245b may be equal to or greater than the thickness of the conductive layer 246b. By reducing the width of the opening 243a and the width of the opening 243b, the transistors 200 can be arranged at a high density. Therefore, a highly integrated semiconductor device can be realized.

[0123] As described above, the etching selectivity between the semiconductor layer 230 and the conductive layers 242a and 242b is low. Therefore, the semiconductor layer 230 may have a recess 244a overlapping the opening 243a and a recess 244b overlapping the opening 243b. In this case, the conductive layer 245a may have a region in contact with the upper surface of the semiconductor layer 230, specifically the upper surface of the recess 244a, as well as a region in contact with the side surface of the recess 244a. Similarly, the conductive layer 245b may have a region in contact with the upper surface of the semiconductor layer 230, specifically the upper surface of the recess 244b, as well as a region in contact with the side surface of the recess 244b. As a result, the contact area between the semiconductor layer 230 and the conductive layer 245a can be larger than when the semiconductor layer 230 does not have the recess 244a. Similarly, the contact area between the semiconductor layer 230 and the conductive layer 245b can be larger than when the semiconductor layer 230 does not have the recess 244b.

[0124] Therefore, the elements contained in the conductive layer 245a and the elements contained in the conductive layer 245b can be easily supplied to the semiconductor layer 230. This makes it easier to form the low-resistance region 230na and the low-resistance region 230nb. For example, the volumes of the low-resistance region 230na and the low-resistance region 230nb can be increased. Furthermore, by increasing the contact area between the conductive layer 245a and the semiconductor layer 230 and the contact area between the conductive layer 245b and the semiconductor layer 230, the contact resistance between the conductive layer 245a and the semiconductor layer 230 and the contact resistance between the conductive layer 245b and the semiconductor layer 230 can be reduced, respectively. As described above, when the semiconductor layer 230 has the recesses 244a and 244b, the operating speed of the semiconductor device can be increased compared to when the recesses 244a and 244b are not present.

[0125] The conductive layer 205 is provided so as to be embedded in an opening formed in the insulating layer 216. The conductive layer 205 is disposed so as to overlap with the semiconductor layer 230 and the conductive layer 260. As shown in FIGS. 1A and 2A , the conductive layer 205 is preferably provided so as to extend in the channel width direction of the transistor 200. With this structure, when a plurality of transistors 200 are provided in a semiconductor device, the conductive layer 205 functions as a wiring.

[0126] The threshold voltage (Vth) of the transistor 200 can be controlled by changing the potential applied to the conductive layer 205 independently of the potential applied to the conductive layer 260. In particular, applying a negative potential to the conductive layer 205 can increase the Vth of the transistor 200 and reduce the off-state current. Therefore, applying a negative potential to the conductive layer 205 can reduce the drain current when the potential applied to the conductive layer 260 is 0 V, compared to when no negative potential is applied.

[0127] The conductive layer 205 can be formed using a conductive material described in the section "Conductive Layer" below. The conductive layer 205 is preferably formed using a conductive material containing, for example, tungsten, copper, or aluminum as a main component. The conductive layer 205 may have a stacked structure. For example, the conductive layer 205 can have a stacked structure of a titanium nitride film in contact with the sidewall of the opening in the insulating layer 216 and a tungsten film on the titanium nitride film.

[0128] The insulating layer 224 is preferably made of an insulating material that releases oxygen when heat is applied. When heat is applied during the manufacturing process of the semiconductor device, the insulating layer 224 releases oxygen, and the oxygen can be supplied to the semiconductor layer 230. By supplying oxygen to the semiconductor layer 230, particularly to the channel formation region, oxygen vacancies or V Ｏ H can be reduced. Therefore, a transistor having good electrical characteristics and high reliability can be obtained. Note that the insulating layer 224 may have a stacked structure of two or more layers. In this case, the insulating layer 224 is not limited to a stacked structure made of the same material, and may have a stacked structure made of different materials.

[0129] Similarly to the semiconductor layer 230, the insulating layer 224 is preferably processed into an island shape. Thus, when a plurality of transistors 200 are provided, each transistor 200 has an insulating layer 224 of approximately the same size. This allows the amount of oxygen supplied from the insulating layer 224 to the semiconductor layer 230 in each transistor 200 to be approximately the same. Therefore, variation in the electrical characteristics of the transistors 200 within the substrate surface can be suppressed. Furthermore, by processing the insulating layer 224 into an island shape, at least a portion of the lower surface of the conductive layer 260 can be provided below the lower surface of the semiconductor layer 230 (see FIG. 2A ). This allows the conductive layer 260 to be provided facing the upper surface and side surface of the semiconductor layer 230, allowing the electric field of the conductive layer 260 to act on the upper surface and side surface of the semiconductor layer 230.

[0130] However, the insulating layer 224 does not necessarily have to be processed into an island shape. For example, the insulating layer 224 can have a convex portion at a position overlapping with the semiconductor layer 230. In this case, the thickness of the insulating layer 224 in a region not overlapping with the semiconductor layer 230 is thinner than the thickness of the region overlapping with the semiconductor layer 230. When multiple transistors are provided on the same substrate, forming the insulating layer 224 in this manner allows the semiconductor layer 230 of each transistor to be formed on the same insulating layer 224. This reduces variation in the amount of oxygen supplied from the insulating layer 224 to the semiconductor layer 230 of each transistor. Therefore, variation in the electrical characteristics of each transistor can be reduced. Note that the insulating layer 224 having a convex portion may have an opening in a region that does not overlap with the semiconductor layer 230 and overlaps with the insulating layer 250, or may not have such an opening.

[0131] At least one of the insulating layer 212, the insulating layer 214, the insulating layer 221, the insulating layer 222, the insulating layer 275, the insulating layer 282, and the insulating layer 283 preferably functions as a barrier insulating layer against hydrogen. At least one of the insulating layer 212, the insulating layer 214, the insulating layer 221, the insulating layer 222, the insulating layer 275, the insulating layer 282, and the insulating layer 283 preferably functions as a barrier insulating layer against impurities. At least one of the insulating layer 212, the insulating layer 214, the insulating layer 221, the insulating layer 222, the insulating layer 275, the insulating layer 282, and the insulating layer 283 preferably functions as a barrier insulating layer against oxygen. Note that all of the insulating layer 212, the insulating layer 214, the insulating layer 221, the insulating layer 222, the insulating layer 275, the insulating layer 282, and the insulating layer 283 do not necessarily need to be provided. As long as the insulating layer has sufficient barrier properties against hydrogen, impurities, oxygen, and the like, the insulating layer can be formed by appropriately selecting from the insulating layer 212, the insulating layer 214, the insulating layer 221, the insulating layer 222, the insulating layer 275, the insulating layer 282, and the insulating layer 283. For example, a structure can be used in which the insulating layer 216 and the conductive layer 205 are formed in contact with the upper surface of the insulating layer 212 without providing the insulating layer 214.

[0132] In this specification and the like, a barrier insulating layer refers to an insulating layer having barrier properties. The barrier properties are defined as a property that makes it difficult for a corresponding substance to diffuse (also referred to as a property that makes it difficult for a corresponding substance to permeate, a property that the permeability of a corresponding substance is low, or a function that suppresses the diffusion of a corresponding substance). Note that hydrogen when described as a corresponding substance includes, for example, a hydrogen atom, a hydrogen molecule, a water molecule, and OH. − Furthermore, unless otherwise specified, impurities when described as corresponding substances refer to impurities in the channel formation region or semiconductor layer, and include, for example, hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N ２ O, NO, and NO ２ The term "oxygen" when used in reference to a corresponding substance refers to at least one of an oxygen atom, an oxygen molecule, and the like.

[0133] An insulator having a function of suppressing diffusion of hydrogen is preferably used for the insulating layer 212, the insulating layer 221, the insulating layer 275, and the insulating layer 283. For example, silicon nitride, which has a higher hydrogen barrier property, is preferably used for the insulating layer 212, the insulating layer 221, the insulating layer 275, and the insulating layer 283.

[0134] The insulating layer 214, the insulating layer 222, and the insulating layer 282 preferably have a function of capturing or fixing hydrogen. For example, aluminum oxide can be used for the insulating layer 214 and the insulating layer 282. For example, hafnium oxide, which is a high-k material, is preferably used for the insulating layer 222 that functions as the second gate insulating layer.

[0135] By providing the insulating layer 212 having a function of suppressing hydrogen diffusion under the transistor 200, it is possible to suppress diffusion of hydrogen from layers below the transistor 200. Furthermore, by providing the insulating layer 214 having a function of capturing or fixing hydrogen, hydrogen contained in the insulating layer 216 or the like can be captured or fixed in the insulating layer 214. This makes it possible to reduce excess hydrogen in the semiconductor layer 230 and its vicinity.

[0136] Furthermore, by providing the insulating layer 221 having a function of suppressing hydrogen diffusion under the semiconductor layer 230, it is possible to suppress diffusion of hydrogen from a layer below the semiconductor layer 230. Furthermore, by providing the insulating layer 222 having a function of capturing or fixing hydrogen, hydrogen contained in the insulating layer 224 or the like can be captured or fixed in the insulating layer 222. This makes it possible to reduce excess hydrogen in the semiconductor layer 230 and its vicinity.

[0137] Furthermore, by providing an insulating layer 275 having the function of suppressing the diffusion of hydrogen so as to cover the semiconductor layer 230, the conductive layer 242a, the conductive layer 242b, etc., it is possible to suppress the diffusion of hydrogen from the insulating layer 280 to the semiconductor layer 230, the conductive layer 242a, the conductive layer 242b, etc.

[0138] Furthermore, by providing the insulating layer 283 having a function of suppressing hydrogen diffusion over the transistor 200, it is possible to suppress diffusion of hydrogen from above the transistor 200. Furthermore, by providing the insulating layer 282 having a function of capturing or fixing hydrogen, hydrogen contained in the insulating layer 280 or the like can be captured or fixed to the insulating layer 282. This makes it possible to reduce excess hydrogen in the semiconductor layer 230 and its vicinity.

[0139] In this manner, by using a structure in which the top and bottom of the transistor 200 are surrounded by barrier insulating layers against hydrogen, diffusion of hydrogen into the oxide semiconductor is suppressed, and the V Ｏ H can be reduced. As a result, the electrical characteristics and reliability of the transistor 200 can be improved.

[0140] 3A is a cross-sectional view taken along dashed dotted line A1-A2 in FIG. 1A, illustrating an example of a semiconductor device that does not include an insulating layer 275. For example, when the hydrogen concentration of the insulating layer 280 is low, the semiconductor device can have the structure shown in FIG. 3A. In this structure, the insulating layer 280 is in contact with the conductive layer 242a and the conductive layer 242b.

[0141] As described above, oxide can be used for the conductive layers 242 a and 242 b. Therefore, in the semiconductor device illustrated in FIG. 3A , even when oxygen is contained in the insulating layer 280, the conductivity of the conductive layers 242 a and 242 b can be maintained.

[0142] The insulating layer 282 is preferably formed by a sputtering method in an atmosphere containing oxygen gas, whereby oxygen can be added to the insulating layer 280.

[0143] The insulating layer 216, the insulating layer 280, and the insulating layer 285 each preferably have a lower dielectric constant than the insulating layer 222. By using a material with a low dielectric constant as an interlayer insulating layer, the parasitic capacitance generated between wirings can be reduced.

[0144] For example, the insulating layer 216, the insulating layer 280, and the insulating layer 285 can each be made of a material with a low dielectric constant, as described in the "Insulating Layer" section below. Silicon oxide and silicon oxynitride are particularly preferred because they are thermally stable. Materials such as silicon oxide, silicon oxynitride, and silicon oxide with vacancies are also preferred because they allow for the easy formation of a region containing excess oxygen.

[0145] 3B is a cross-sectional view taken along dashed line A1-A2 in FIG. 1A, illustrating an example of a semiconductor device including insulating layers 241a and 241b. Insulating layer 241a is provided inside opening 243a and is positioned between the sidewall of opening 243a and conductive layer 245a. Similarly, insulating layer 241b is provided inside opening 243b and is positioned between the sidewall of opening 243b and conductive layer 245b.

[0146] For example, silicon nitride can be used for the insulating layer 241a and the insulating layer 241b. This can prevent impurities such as water and hydrogen contained in the insulating layer 280 and the like from being mixed into the semiconductor layer 230 through the conductive layer 245a, the conductive layer 245b, and the like. Furthermore, oxygen contained in the insulating layer 280 and the like can be prevented from being absorbed by the conductive layer 245a, the conductive layer 245b, and the like.

[0147] Alternatively, the insulating layer 241 a and the insulating layer 241 b may have a stacked structure. In this case, the first insulating layer in contact with the sidewall of the opening 243 a or the sidewall of the opening 243 b and the second insulating layer therein are preferably formed by combining a barrier insulating layer against oxygen and a barrier insulating layer against hydrogen.

[0148] 1A, 1B, and the like of a semiconductor device according to one embodiment of the present invention will be described below. Note that differences from the description of the above-described <Structural Example 1 of Semiconductor Device> will be mainly described, and descriptions of overlapping parts will be omitted as appropriate.

[0149] FIG. 4A is a plan view showing an example of the configuration of a semiconductor device. FIG. 4B is a cross-sectional view taken along dashed line A1-A2 in FIG. 4A . In the semiconductor device shown in FIGS. 4A and 4B , the upper end of conductive layer 245a is located below the upper surface of conductive layer 246a. Similarly, the upper end of conductive layer 245b is located below the upper surface of conductive layer 246b. In other words, the height of the upper end of conductive layer 245a from the reference plane is lower than the height of the upper surface of conductive layer 246a from the reference plane. Similarly, the height of the upper end of conductive layer 245b from the reference plane is lower than the height of the upper surface of conductive layer 246b from the reference plane. In the example shown in FIGS. 4A and 4B , conductive layer 246a can contact at least a portion of the sidewall of opening 243a. Similarly, conductive layer 246b can contact at least a portion of the sidewall of opening 243b. 4A, the shape of the conductive layer 246a in a plan view can be the same as or approximately the same as the shape of the conductive layer 245a in a plan view. Similarly, the shape of the conductive layer 246b in a plan view can be the same as or approximately the same as the shape of the conductive layer 245b in a plan view.

[0150] When the conductive films that become the conductive layers 245a and 245b are formed using a method with low coverage, the conductive layers 245a and 245b may have the structures shown in Figures 4A and 4B. For example, when the conductive films that become the conductive layers 245a and 245b are formed using a sputtering method, which has lower coverage than the ALD method and the chemical vapor deposition (CVD) method, the conductive layers 245a and 245b may have the structures shown in Figures 4A and 4B. Even in such a case, if the conductive layer 245a has a region in contact with the semiconductor layer 230, a low-resistance region 230na is formed in the semiconductor layer 230. Similarly, if the conductive layer 245b has a region in contact with the semiconductor layer 230, a low-resistance region 230nb is formed in the semiconductor layer 230.

[0151] FIG. 5A is a plan view showing a configuration example of a semiconductor device. FIG. 5B is a cross-sectional view taken along dashed line A1-A2 in FIG. 5A . In the semiconductor device shown in FIGS. 5A and 5B , the conductive layer 246a includes a conductive layer 246a1 and a conductive layer 246a2 on the conductive layer 246a1. Similarly, the conductive layer 246b includes a conductive layer 246b1 and a conductive layer 246b2 on the conductive layer 246b1. In the example shown in FIGS. 5A and 5B , the conductive layer 246a1 is provided along the top and side surfaces of the conductive layer 245a inside the opening 243a. Similarly, the conductive layer 246b1 is provided along the top and side surfaces of the conductive layer 245b inside the opening 243b. Furthermore, the conductive layer 246a2 is provided to fill the opening 243a, and the conductive layer 246b2 is provided to fill the opening 243b.

[0152] The conductive layers 246a2 and 246b2 can be made of the same materials as those used for the conductive layers 246a and 246b shown in FIGS. 1A and 1B. The conductive layers 246a1 and 246b1 can be made of, for example, a conductive material that has a function of suppressing oxygen diffusion. The conductive layers 246a1 and 246b1 can be made of, for example, titanium nitride, tantalum, tantalum nitride, ruthenium, ruthenium oxide, or the like. This can prevent the conductive layers 246a and 246b from being oxidized by oxygen contained in the insulating layer 280 and the insulating layer 285, for example.

[0153] Fig. 6A is a plan view showing a configuration example of a semiconductor device. Fig. 6B is a cross-sectional view taken along dashed dotted line A1-A2 shown in Fig. 6A. In the semiconductor device shown in Fig. 6A and Fig. 6B, the conductive layer 245a and the conductive layer 245b have regions in contact with not only the top surface of the semiconductor layer 230 but also the side surface of the semiconductor layer 230. Note that Fig. 6B shows an example in which the conductive layer 245a and the conductive layer 245b have regions in contact with the side surface of the insulating layer 224 and the top surface of the insulating layer 222.

[0154] The semiconductor device shown in Figures 6A and 6B can increase the contact area between the conductive layer 245a and the conductive layer 245b and the semiconductor layer 230 compared to the semiconductor device shown in Figures 1A, 1B, etc. This can reduce the contact resistance between the conductive layer 245a and the conductive layer 245b and the semiconductor layer 230. Furthermore, the volumes of the low-resistance regions 230na and 230nb can be increased in some cases. As a result, a semiconductor device with high operating speed can be realized. On the other hand, the semiconductor device shown in Figures 1A, 1B, etc. can arrange the transistors 200 at a higher density compared to the semiconductor device shown in Figures 6A and 6B. Therefore, a highly integrated semiconductor device can be realized.

[0155] Fig. 7A is a plan view showing an example of the configuration of a semiconductor device. Fig. 7B is a cross-sectional view taken along dashed dotted line A1-A2 shown in Fig. 7A. The semiconductor device shown in Fig. 7A and Fig. 7B has an insulating layer 255. Inside opening 289, insulating layer 255 is provided so as to have a region located between insulating layer 280 and insulating layer 250, a region located between conductive layer 242a and insulating layer 250, and a region located between conductive layer 242b and insulating layer 250.

[0156] The insulating layer 255 has an opening 290 at a position overlapping the region between the conductive layer 242a and the conductive layer 242b. The opening 290 is located inside the opening 289. The side surface of the insulating layer 255 at the opening 289 has a region that coincides or nearly coincides with the side surface of the conductive layer 242a and a region that coincides or nearly coincides with the side surface of the conductive layer 242b.

[0157] 7A and 7B , inside opening 289 or opening 290, insulating layer 250 can have a region in contact with the upper surface of recess 287 of semiconductor layer 230, a region in contact with the side surface of recess 287 of semiconductor layer 230, a region in contact with the side surface of conductive layer 242a, a region in contact with the side surface of conductive layer 242b, a region in contact with the side surface of insulating layer 255, a region in contact with the side surface of insulating layer 224, and a region in contact with the upper surface of insulating layer 222. Fig. 7B shows an example in which the upper surface of insulating layer 280, the upper end of insulating layer 250, the upper end of insulating layer 255, and the upper surface of conductive layer 260 are aligned or approximately aligned.

[0158] 7A and 7B, the channel length of the transistor 200 can be shortened without making the width of the opening 289 smaller than that of the semiconductor device shown in FIGS. 1A, 1B, etc. Therefore, the on-state current of the transistor 200 can be increased, and a semiconductor device with high operating speed can be realized.

[0159] The insulating layer 255 can be formed using, for example, silicon nitride, hafnium oxide, or aluminum oxide. Silicon nitride has a barrier property against hydrogen and can therefore prevent excessive diffusion of hydrogen from the insulating layer 280 to the semiconductor layer 230 through the insulating layer 250. Hafnium oxide has a function of capturing or fixing hydrogen, so hydrogen contained in the insulating layer 250 or the like can be captured or fixed to the insulating layer 255. This can reduce excess hydrogen in and around the semiconductor layer 230. Aluminum oxide has a barrier property against oxygen and can therefore control the amount of oxygen supplied from the insulating layer 280 to the semiconductor layer 230 through the insulating layer 250. By adjusting the thickness of the insulating layer 255, an appropriate amount of oxygen can be supplied to the insulating layer 280. Therefore, a highly reliable transistor 200 can be realized. Note that the insulating layer 255 may have a stacked structure of two or more layers. For example, the insulating layer 255 can have a two-layer stacked structure including a layer using one of silicon nitride, hafnium oxide, and aluminum oxide and a layer using the other one. Alternatively, a three-layer stack structure can be formed of a layer using one of silicon nitride, hafnium oxide, and aluminum oxide, a layer using another one of the materials, and a layer using the remaining one of the materials.

[0160] 1A to 7B can be combined as appropriate. For example, the conductive layer 246a and the conductive layer 246b shown in FIG. 3A, 3B, 4B, 6B, or 7B can have a two-layer stacked structure as shown in FIG. 5B.

[0161] <Materials for Constituting Semiconductor Device> Materials that can be used for the semiconductor device will be described below. Each layer constituting the semiconductor device may have a single layer structure or a multilayer structure.

[0162] [Insulating Layer] It is preferable to use an inorganic insulating film for each of the insulating layers (insulating layer 212, insulating layer 214, insulating layer 216, insulating layer 221, insulating layer 222, insulating layer 224, insulating layer 241a, insulating layer 241b, insulating layer 250, insulating layer 255, insulating layer 275, insulating layer 280, insulating layer 282, insulating layer 283, insulating layer 285, etc.) included in the semiconductor device. Examples of inorganic insulating films include an oxide insulating film, a nitride insulating film, an oxynitride insulating film, and a nitride oxide insulating film. Examples of oxide insulating films include a silicon oxide film, an aluminum oxide film, a magnesium oxide film, a gallium oxide film, a germanium oxide film, an yttrium oxide film, a zirconium oxide film, a lanthanum oxide film, a neodymium oxide film, a hafnium oxide film, a tantalum oxide film, a cerium oxide film, a gallium zinc oxide film, and a hafnium aluminate film. Examples of nitride insulating films include a silicon nitride film and an aluminum nitride film. Examples of the oxynitride insulating film include a silicon oxynitride film, an aluminum oxynitride film, a gallium oxynitride film, an yttrium oxynitride film, and a hafnium oxynitride film. Examples of the nitride oxide insulating film include a silicon nitride oxide film and an aluminum nitride oxide film. An insulating layer included in a semiconductor device may be an organic insulating film.

[0163] For example, as transistors become more miniaturized and highly integrated, problems such as leakage current may occur due to thinner gate insulating layers. Using high-k materials for the gate insulating layer allows for lower voltages during transistor operation while maintaining the physical film thickness. It also allows for thinner equivalent oxide thickness (EOT) of the gate insulating layer. Meanwhile, using a material with a low dielectric constant for the insulating layer that functions as an interlayer insulating layer can reduce the parasitic capacitance that occurs between wiring. Therefore, it is preferable to select materials according to the function of the insulating layer. Note that materials with a low dielectric constant also have high dielectric strength.

[0164] Examples of high-k materials include aluminum oxide, gallium oxide, hafnium oxide, tantalum oxide, zirconium oxide, hafnium zirconium oxide, oxides having aluminum and hafnium, oxynitrides having aluminum and hafnium, oxides having silicon and hafnium, oxynitrides having silicon and hafnium, and nitrides having silicon and hafnium.

[0165] Examples of materials with a low relative dielectric constant include inorganic insulating materials such as silicon oxide, silicon oxynitride, and silicon nitride oxide, and resins such as polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, and acrylic resin. Other inorganic insulating materials with a low relative dielectric constant include silicon oxide containing fluorine, silicon oxide containing carbon, and silicon oxide containing carbon and nitrogen. Another example is silicon oxide having vacancies. These silicon oxides may contain nitrogen.

[0166] Furthermore, a material capable of exhibiting ferroelectricity may be used for the insulating layer of the semiconductor device. As the material capable of exhibiting ferroelectricity, an oxide containing one or both of hafnium and zirconium is preferably used. Examples of such oxides include metal oxides such as hafnium oxide, zirconium oxide, and hafnium zirconium oxide. Furthermore, as the material capable of exhibiting ferroelectricity, a material obtained by adding an element J1 (here, the element J1 is one or more selected from the other of hafnium and zirconium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) to a metal oxide containing one of hafnium and zirconium may be used.

[0167] Furthermore, adding a Group 3 element in the periodic table to an oxide containing one or both of hafnium and zirconium increases the oxygen vacancy concentration in the oxide, making it easier to form crystals with an orthorhombic crystal structure. This is preferable because it increases the proportion of crystals with an orthorhombic crystal structure and increases the remanent polarization. On the other hand, adding too much of the Group 3 element may reduce the crystallinity of the oxide and make it difficult to exhibit ferroelectricity. Therefore, the content of the Group 3 element in the oxide containing one or both of hafnium and zirconium is preferably 0.1 atomic% to 10 atomic%, more preferably 0.1 atomic% to 5 atomic%, and even more preferably 0.1 atomic% to 3 atomic%. Here, the content of the Group 3 element refers to the ratio of the number of atoms of the Group 3 element to the sum of the number of atoms of all metal elements contained in the layer. The Group 3 element is preferably one or more selected from scandium, lanthanum, and yttrium, and more preferably one or both of lanthanum and yttrium.

[0168] Furthermore, examples of materials that may have ferroelectricity include metal nitrides containing nitrogen and at least one of element M1 and element M2. Here, element M1 is one or more selected from aluminum, gallium, indium, etc. Furthermore, element M2 is one or more selected from boron, scandium, yttrium, lanthanum, cerium, neodymium, europium, titanium, zirconium, hafnium, vanadium, niobium, tantalum, chromium, etc. Furthermore, examples of materials that may have ferroelectricity include materials in which element M3 is added to the above metal nitrides. Furthermore, element M3 is one or more selected from magnesium, calcium, strontium, zinc, cadmium, etc.

[0169] Furthermore, materials that can have ferroelectricity include SrTaO ２ N and BaTaO ２ Perovskite-type oxynitrides such as N, GaFeO with κ-alumina structure ３ Furthermore, examples of materials that can have ferroelectricity include lead titanate (PbTiO ＸPiezoelectric ceramics having a perovskite structure, such as barium strontium titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), bismuth ferrite (BFO), or barium titanate, may also be used.

[0170] In the above description, metal oxides and metal nitrides are used as examples, but the present invention is not limited to these. For example, metal oxynitrides in which nitrogen is added to the aforementioned metal oxides, or metal oxynitrides in which oxygen is added to the aforementioned metal nitrides, may also be used.

[0171] Furthermore, as a material capable of exhibiting ferroelectricity, for example, a mixture or compound of a plurality of materials selected from the materials listed above can be used. However, since the crystal structure (characteristics) of the materials listed above may change depending not only on the film formation conditions but also on various processes, in this specification, a material that exhibits ferroelectricity is not only called a ferroelectric but also called a material capable of exhibiting ferroelectricity.

[0172] In this specification, a layer of a material that can have ferroelectricity may be referred to as a ferroelectric layer, a metal oxide film, or a metal nitride film. Also, in this specification, a device having such a ferroelectric layer, a metal oxide film, or a metal nitride film may be referred to as a ferroelectric device.

[0173] The ferroelectric layer preferably contains crystals having an orthorhombic crystal structure, since this allows ferroelectricity to be exhibited. The crystal structure of the crystals contained in the ferroelectric layer may be one or more selected from the group consisting of tetragonal, orthorhombic, monoclinic, and hexagonal. The ferroelectric layer may also have an amorphous structure. In this case, the ferroelectric layer may have a composite structure having an amorphous structure and a crystalline structure.

[0174] A metal oxide containing one or both of hafnium and zirconium is also an insulating material that has the function of capturing or fixing hydrogen. Therefore, by using a metal oxide containing one or both of hafnium and zirconium for at least a part of a gate insulating layer, hydrogen contained in the oxide semiconductor layer can be captured or fixed, and excess hydrogen in the oxide semiconductor layer can be reduced. Furthermore, a transistor having the gate insulating layer can function as a ferroelectric field effect transistor (FeFET).

[0175] Furthermore, a transistor using a metal oxide can have stable electrical characteristics by being surrounded by an insulating layer that has a function of suppressing the permeation of impurities and oxygen. The insulating layer that has a function of suppressing the permeation of impurities and oxygen can be, for example, a single-layer or stacked insulating layer containing one or more elements selected from boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum. Specifically, the insulating layer that has a function of suppressing the permeation of impurities and oxygen can be made of a metal oxide such as aluminum oxide, magnesium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide; a nitride such as aluminum nitride or silicon nitride; or a nitride oxide such as silicon nitride oxide.

[0176] Specifically, examples of materials for the insulating layer that have the function of suppressing the permeation of impurities such as water and hydrogen, and oxygen, include metal oxides such as aluminum oxide, magnesium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, and oxides containing aluminum and hafnium (hafnium aluminate). Examples of nitrides include aluminum nitride, aluminum titanium nitride, silicon nitride oxide, and silicon nitride. Examples of nitride oxides include silicon nitride oxide. Examples of materials for the insulating layer that have the function of suppressing the permeation of oxygen include gallium oxide.

[0177] An insulating layer such as a gate insulating layer that is in contact with or near an oxide semiconductor layer preferably has a region containing excess oxygen. For example, when an insulating layer having a region containing excess oxygen is in contact with or near an oxide semiconductor layer, oxygen vacancies in the oxide semiconductor layer can be reduced.

[0178] An insulating layer provided in contact with or near an oxide semiconductor layer is preferably a barrier insulating layer against hydrogen. When the insulating layer has a barrier property against hydrogen, diffusion of hydrogen into the oxide semiconductor layer can be suppressed. The barrier insulating layer against hydrogen can also be said to have a function of suppressing diffusion of hydrogen.

[0179] Examples of insulating materials having the function of capturing or fixing hydrogen include metal oxides such as oxides containing hafnium, oxides containing magnesium, oxides containing aluminum, oxides containing aluminum and hafnium (hafnium aluminate), hafnium silicate, etc. These metal oxides may further contain zirconium, and examples thereof include oxides containing hafnium and zirconium.

[0180] An insulating layer having the function of capturing or fixing hydrogen preferably has an amorphous structure. In a metal oxide having an amorphous structure, some oxygen atoms have dangling bonds, which enhances the ability to capture or fix hydrogen. Therefore, when the insulating layer has an amorphous structure, the function of capturing or fixing hydrogen can be enhanced.

[0181] By making the insulating layer an amorphous structure, it is possible to suppress the formation of crystal grain boundaries. By suppressing the formation of crystal grain boundaries, it is possible to improve the flatness of the insulating layer. This makes it possible to uniformize the film thickness distribution of the insulating layer and reduce areas with extremely thin film thickness, thereby improving the breakdown voltage of the insulating layer. It is also possible to uniformize the film thickness distribution of a film provided on the insulating layer. Furthermore, by suppressing the formation of crystal grain boundaries in the insulating layer, it is possible to reduce leakage current caused by defect levels at the crystal grain boundaries. Therefore, the insulating layer can function as an insulating film with low leakage current.

[0182] The ability to capture or fix a corresponding substance can also be said to have the property of making it difficult for the corresponding substance to diffuse. Therefore, the ability to capture or fix a corresponding substance can be rephrased as barrier properties.

[0183] Examples of materials for the barrier insulating layer against hydrogen include aluminum oxide, magnesium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium (hafnium aluminate), oxides containing hafnium and zirconium (hafnium zirconium oxide), silicon nitride, and silicon nitride oxide.

[0184] The inorganic insulating layers cited as insulating layers having the function of capturing or fixing hydrogen and insulating layers having the function of suppressing hydrogen diffusion also have barrier properties against oxygen. Examples of materials for oxygen barrier insulating layers include oxides containing one or both of aluminum and hafnium, magnesium oxide, gallium zinc oxide, silicon nitride, and silicon nitride oxide. Examples of oxides containing one or both of aluminum and hafnium include aluminum oxide, hafnium oxide, oxides containing aluminum and hafnium (hafnium aluminate), and hafnium silicate.

[0185] [Conductive Layer] The conductive layers (conductive layer 205, conductive layer 246a, conductive layer 246b, conductive layer 260, etc.) included in the semiconductor device preferably contain a metal element selected from aluminum, chromium, copper, silver, gold, platinum, zinc, tantalum, nickel, titanium, iron, cobalt, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, palladium, iridium, strontium, lanthanum, etc., or an alloy containing the above-mentioned metal element as a component, or an alloy combining the above-mentioned metal elements. As the alloy containing the above-mentioned metal element as a component, a nitride of the alloy or an oxide of the alloy may be used. For example, tantalum nitride, titanium nitride, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, oxide containing lanthanum and nickel, etc. are preferably used. Furthermore, semiconductors with high electrical conductivity, such as polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicide may also be used.

[0186] Nitrogen-containing conductive materials, such as nitrides containing tantalum, nitrides containing titanium, nitrides containing molybdenum, nitrides containing tungsten, nitrides containing ruthenium, nitrides containing tantalum and aluminum, or nitrides containing titanium and aluminum; oxygen-containing conductive materials, such as ruthenium oxide, oxides containing strontium and ruthenium, or oxides containing lanthanum and nickel; and materials containing metal elements, such as titanium, tantalum, or ruthenium, are preferred because they are conductive materials that are resistant to oxidation, have a function of suppressing oxygen diffusion, or maintain conductivity even after absorbing oxygen. Examples of oxygen-containing conductive materials include indium oxide containing tungsten oxide, In-Ti oxide, ITO, indium tin oxide containing titanium oxide, indium tin oxide containing silicon (also referred to as ITSO), indium zinc oxide (In-Zn oxide, also referred to as IZO (registered trademark)), and indium zinc oxide containing tungsten oxide. In this specification and the like, a conductive film formed using a conductive material containing oxygen may be referred to as an oxide conductive film.

[0187] Furthermore, a plurality of conductive layers formed from the above materials may be stacked. For example, a stacked structure may be formed by combining the above-described material containing a metal element and a conductive material containing oxygen. A stacked structure may be formed by combining the above-described material containing a metal element and a conductive material containing nitrogen. A stacked structure may be formed by combining the above-described material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen.

[0188] When a metal oxide is used for the channel formation region of a transistor, the conductive layer that functions as a gate electrode preferably has a stacked structure that combines a material containing the metal element and a conductive material containing oxygen. In this case, the conductive material containing oxygen is preferably provided on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen desorbed from the conductive material is easily supplied to the channel formation region.

[0189] [Substrate] Substrates on which transistors are formed can include, for example, insulating substrates, semiconductor substrates, or conductive substrates. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (e.g., yttria-stabilized zirconia substrates), and resin substrates. Examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, or compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. Examples of semiconductor substrates include those having an insulating region within the semiconductor substrate, such as an SOI (Silicon-On-Insulator) substrate. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Examples of substrates include substrates having a metal nitride or a metal oxide. Examples of substrates include substrates having a conductor or semiconductor provided on an insulating substrate, substrates having a conductor or insulator provided on a semiconductor substrate, and substrates having a semiconductor or insulator provided on a conductive substrate. Alternatively, a substrate provided with elements may be used, such as a capacitor element, a resistor element, a switch element, a light-emitting element, or a memory element.

[0190] The above is a description of materials that can be used in semiconductor devices.

[0191] 8A to 17D , an example of a method for manufacturing a semiconductor device according to one embodiment of the present invention will be described. Here, the case of manufacturing the semiconductor device illustrated in FIGS. 1A to 2B will be described as an example. Note that with regard to the materials and formation methods of each component, descriptions of parts similar to those described above may be omitted.

[0192] Thin films (insulating films, semiconductor films, conductive films, etc.) constituting a semiconductor device can be formed using a sputtering method, a CVD method, a molecular beam epitaxy (MBE) method, a vacuum evaporation method, a pulsed laser deposition (PLD) method, an ALD method, or the like.

[0193] RF sputtering is preferably used for film formation using an insulating target. DC sputtering is mainly used for film formation using a conductive target. In addition to forming conductive films, DC sputtering can also form insulating films by reactive sputtering using pulsed DC sputtering. Specifically, pulsed DC sputtering can be used for forming films of compounds such as oxides, nitrides, and carbides by reactive sputtering.

[0194] CVD methods can be further classified into plasma-enhanced CVD (PECVD) methods that utilize plasma, thermal CVD (TCVD) methods that utilize heat, and photo-CVD (photo-CVD) methods that utilize light. CVD methods can also be further classified into metal CVD (MCVD) methods and metal organic CVD (MOCVD) methods depending on the source gas used.

[0195] The plasma CVD method can produce high-quality films at relatively low temperatures. Furthermore, the thermal CVD method is a film formation method that can reduce plasma damage to the workpiece because it does not use plasma. For example, wiring, electrodes, elements (transistors, capacitors, etc.) included in a semiconductor device may become charged up by receiving electric charge from the plasma. In this case, the accumulated electric charge may destroy the wiring, electrodes, elements, etc. included in the semiconductor device. On the other hand, the thermal CVD method, which does not use plasma, does not cause such plasma damage, and therefore can increase the yield of semiconductor devices. Furthermore, the thermal CVD method does not cause plasma damage during film formation, so films with fewer defects can be obtained.

[0196] As the ALD method, a thermal ALD method in which a reaction between a precursor and a reactant is carried out using only thermal energy, a PEALD method in which a plasma-excited reactant is used, or the like can be used.

[0197] Note that some precursors used in the ALD method contain elements such as carbon or chlorine. Therefore, films formed by the ALD method may contain more elements such as carbon or chlorine than films formed by other film formation methods. The amounts of these elements can be quantified using XPS or SIMS. Note that the metal oxide film formation method of one embodiment of the present invention uses the ALD method, but employs one or both of the following conditions: a high substrate temperature during film formation and / or an impurity removal treatment. Therefore, the amount of carbon and chlorine contained in the film may be smaller than when the ALD method is used without these conditions.

[0198] Unlike film formation methods in which particles emitted from a target or the like are deposited, the ALD method is a film formation method in which a film is formed by a reaction on the surface of a workpiece. Therefore, it is a film formation method that is less affected by the shape of the workpiece and has good step coverage. In particular, the ALD method has excellent step coverage and excellent thickness uniformity, making it suitable for coating the surface of an opening with a high aspect ratio.

[0199] The CVD and ALD methods differ from sputtering methods in which particles emitted from a target or the like are deposited. Therefore, they are film formation methods that are less affected by the shape of the workpiece and have good step coverage. In particular, the ALD method has excellent step coverage and excellent thickness uniformity, making it suitable for coating the surface of an opening with a high aspect ratio. However, because the ALD method has a relatively slow film formation rate, it may be preferable to use it in combination with other film formation methods, such as the CVD method, which have a faster film formation rate.

[0200] Furthermore, the CVD method allows deposition of a film of any composition by adjusting the flow rate ratio of the source gases. For example, the CVD method allows deposition of a film with a continuously changing composition by changing the flow rate ratio of the source gases during deposition. When deposition is performed while changing the flow rate ratio of the source gases, the time required for deposition can be shortened compared to deposition using multiple deposition chambers because no time is required for transport or pressure adjustment. Therefore, the productivity of semiconductor devices can be improved in some cases.

[0201] In addition, in the ALD method, a film of any composition can be formed by simultaneously introducing multiple different precursors, or by controlling the number of cycles of each precursor when multiple different precursors are introduced.

[0202] There are two typical photolithography methods: one is to form a resist mask on the thin film to be processed, process the thin film by etching or the like, and then remove the resist mask; the other is to form a photosensitive thin film, and then process the thin film into the desired shape by exposure and development.

[0203] In photolithography, the light used for exposure may be, for example, i-line (wavelength 365 nm), g-line (wavelength 436 nm), h-line (wavelength 405 nm), or a mixture of these. Other light sources that can be used include ultraviolet light, KrF laser light, ArF laser light, etc. Exposure may also be performed by immersion exposure technology. Extreme ultraviolet (EUV) light or X-rays may also be used as the light used for exposure. An electron beam may also be used instead of the light used for exposure. Extreme ultraviolet light, X-rays, or an electron beam are preferred because they enable extremely fine processing. When exposure is performed by scanning a beam such as an electron beam, a photomask is not required.

[0204] For etching the thin film, dry etching, wet etching, sandblasting, or the like can be used.

[0205] 8 to 17A show plan views. 8 to 17B show cross-sectional views taken along dashed lines A1-A2 in (A) of the respective figures. 8 to 17C show cross-sectional views taken along dashed lines A3-A4 in (A) of the respective figures. 8 to 17D show cross-sectional views taken along dashed lines A5-A6 in (D) of the respective figures.

[0206] 8A to 8D , a substrate (not shown) is prepared, an insulating layer 212 is formed on the substrate, and an insulating layer 214 is formed on the insulating layer 212. In this embodiment, a silicon nitride film is formed by sputtering as the insulating layer 212, and an aluminum oxide film is formed by sputtering as the insulating layer 214. By using a sputtering method that does not require the use of molecules containing hydrogen in the film formation gas, the hydrogen concentrations in the insulating layers 212 and 214 can be reduced.

[0207] Furthermore, it is preferable to perform heat treatment to reduce water and hydrogen adsorbed to the substrate (including the circuit elements and the interlayer insulating layer formed over the substrate) before forming the insulating layer 212. In this embodiment mode, the temperature of the heat treatment is 400° C.

[0208] 8A to 8D , an insulating layer 216 is formed over the insulating layer 214. In this embodiment, a silicon oxide film is formed by a sputtering method as the insulating layer 216. By using the sputtering method, which does not require the use of molecules containing hydrogen in the film formation gas, the hydrogen concentration in the insulating layer 216 can be reduced.

[0209] The insulating layers 212, 214, and 216 are preferably formed in succession without exposure to the air. For example, a multi-chamber film formation apparatus is preferably used. This allows the insulating layers 212, 214, and 216 to be formed with reduced hydrogen content and further reduces hydrogen contamination between film formation steps.

[0210] Next, an opening reaching the insulating layer 214 is formed in the insulating layer 216. The opening is formed in a region where the conductive layer 205 is to be formed. The opening may be formed by wet etching, but dry etching is preferable for fine processing. For the insulating layer 214, an insulator that functions as an etching stopper film when the insulating layer 216 is etched is preferably selected. For example, when silicon oxide or silicon oxynitride is used for the insulating layer 216, silicon nitride, aluminum oxide, hafnium oxide, or the like may be used for the insulating layer 214.

[0211] After the opening is formed, a conductive film to be the conductive layer 205 is formed, and a chemical mechanical polishing (CMP) process is performed to remove a portion of the conductive film until the insulating layer 216 is exposed. As a result, the conductive layer 205 embedded in the insulating layer 216 can be formed as shown in FIGS. 8A to 8D . In this embodiment, the conductive film is a stacked film of a titanium nitride film formed by a CVD method and a tungsten film formed on the titanium nitride film by a CVD method.

[0212] 8A to 8D , an insulating layer 221 is formed on the insulating layer 216 and the conductive layer 205, and an insulating layer 222 is further formed on the insulating layer 221. In this embodiment, a silicon nitride film is formed as the insulating layer 221 by using a PEALD method, and a hafnium oxide film is formed as the insulating layer 222 by using a thermal ALD method.

[0213] 8A to 8D, an insulating film 224f that will become the insulating layer 224 is formed on the insulating layer 222. In this embodiment, a silicon oxide film is formed as the insulating film 224f by sputtering. By using a sputtering method that does not require the use of hydrogen-containing molecules in the film formation gas, the hydrogen concentration in the insulating film 224f can be reduced. Since the insulating film 224f will be in contact with a semiconductor film 230f that will be formed in a later step, it is preferable that the hydrogen concentration be reduced in this manner.

[0214] 8A to 8D, a semiconductor film 230f is formed on the insulating film 224f. In this embodiment, an indium oxide film is formed as the semiconductor layer 230 by sputtering or ALD.

[0215] Subsequently, heat treatment is preferably performed. For example, the heat treatment can be performed at 450° C. for 1 hour with a flow rate ratio of nitrogen gas to oxygen gas of 4:1. The heat treatment can improve the crystallinity of the semiconductor layer 230. This can improve the on-state current, S value, field-effect mobility, frequency characteristics, and the like of the transistor 200, thereby providing a semiconductor device with favorable electrical characteristics. Furthermore, a highly reliable semiconductor device can be provided.

[0216] The heat treatment is preferably performed in a nitrogen gas or inert gas atmosphere, or an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more. The heat treatment may be performed under reduced pressure. Alternatively, after the heat treatment in the nitrogen gas or inert gas atmosphere, the heat treatment may be performed in an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more to compensate for the desorbed oxygen.

[0217] Furthermore, the gas used in the heat treatment is preferably highly purified. For example, the amount of moisture contained in the gas used in the heat treatment is preferably 1 ppb or less, more preferably 0.1 ppb or less, and even more preferably 0.05 ppb or less. By performing the heat treatment using a highly purified gas, it is possible to prevent moisture and the like from being taken into the semiconductor film 230f and the like as much as possible. Note that highly purified gas can also be used for the heat treatment before this step and the heat treatment after this step.

[0218] Furthermore, the heat treatment using oxygen gas as described above can reduce impurities such as carbon, water, and hydrogen in the semiconductor film 230f. Reducing the impurities in the film in this manner can improve the crystallinity of the semiconductor film 230f, resulting in a denser, more compact structure. This increases the crystalline region in the semiconductor film 230f, reducing the in-plane variation of the crystalline region in the semiconductor film 230f. This reduces the in-plane variation of the electrical characteristics of the transistor 200.

[0219] Furthermore, by performing heat treatment, oxygen can be supplied to the semiconductor film 230f, and oxygen vacancies in the semiconductor film 230f can be reduced, thereby improving the reliability of the transistor 200.

[0220] Furthermore, by performing heat treatment, hydrogen in the insulating layer 216, the insulating film 224f, and the semiconductor film 230f moves to the insulating layer 222 and is absorbed into the insulating layer 222. In other words, hydrogen in the insulating layer 216, the insulating film 224f, and the semiconductor film 230f diffuses into the insulating layer 222. Therefore, the hydrogen concentration in the insulating layer 222 increases, but the hydrogen concentrations in the insulating layer 216, the insulating film 224f, and the semiconductor film 230f decrease. Note that by providing the insulating layer 221 in contact with the lower surface of the insulating layer 222, impurities such as moisture or hydrogen can be prevented from entering from below the insulating layer 221 during the heat treatment.

[0221] Next, as shown in FIGS. 8A to 8D , a conductive film 242f that becomes the conductive layers 242a and 242b is formed on the semiconductor film 230f. The conductive film 242f contains elements contained in the semiconductor film 230f. Specifically, the conductive film 242f includes an oxide containing indium and a first metal element. For example, tin can be used as the first metal element. In this embodiment, ITO is formed as the conductive film 242f by a sputtering method or an ALD method. Here, it is preferable not to form a film whose main component is different from that of the semiconductor film 230f on the film containing the oxide (oxide film). That is, the conductive film 242f preferably has a single-layer oxide film structure rather than a stacked structure. This allows the conductive film 242f to be easily processed in subsequent steps. Furthermore, since absorption of oxygen contained in the oxide film can be suppressed, a decrease in the reliability of the semiconductor device can be suppressed in some cases.

[0222] Note that heat treatment may be performed before the formation of the conductive film 242f. The heat treatment may be performed under reduced pressure, and the conductive film 242f may be formed successively without exposure to the air. By performing such treatment, moisture and hydrogen adsorbed on the surface of the semiconductor layer 230 can be removed, and excess hydrogen in the semiconductor layer 230 can be further reduced. The temperature of the heat treatment is preferably 100° C. or higher and 400° C. or lower.

[0223] Subsequently, the conductive film 242f, the semiconductor film 230f, and the insulating film 224f are processed into island shapes by lithography, thereby forming the conductive layer 242, the semiconductor layer 230, and the insulating layer 224 as shown in FIGS.

[0224] The conductive film 242f, the semiconductor film 230f, and the insulating film 224f can be processed by dry etching or wet etching. Dry etching is suitable for microfabrication. By forming the conductive film 242f as a single oxide film, the conductive film 242f and the semiconductor film 230f can be processed under a single set of conditions. Therefore, the number of manufacturing steps for the semiconductor device can be reduced compared to when the conductive film 242f has a stacked structure of, for example, two or more layers, thereby increasing the productivity of the semiconductor device. The insulating film 224f can be processed under the same conditions as those for processing the semiconductor film 230f, or under different conditions.

[0225] Here, the conductive film 242f, the semiconductor film 230f, and the insulating film 224f are preferably processed using the same mask pattern. At this time, it is preferable that the side edges of the conductive film 242f coincide or substantially coincide with the side edges of the semiconductor layer 230. Furthermore, it is preferable that the side edges of the insulating layer 224 coincide or substantially coincide with the side edges of the semiconductor layer 230. With such a structure, the number of manufacturing steps of the semiconductor device can be reduced, and the productivity of the semiconductor device can be increased.

[0226] Furthermore, the insulating layer 222 is exposed in a region that does not overlap with the insulating layer 224, the semiconductor layer 230, or the conductive layer 242. However, this is not limiting, and a structure in which the insulating layer 224 remains on the insulating layer 222 in a region that does not overlap with the semiconductor layer 230 may also be used.

[0227] 9B to 9D , the side surfaces of the insulating layer 224, the semiconductor layer 230, and the conductive layer 242 may be tapered. The taper angle of the side surfaces of the insulating layer 224, the semiconductor layer 230, and the conductive layer 242 can be, for example, 60° or more and less than 90°. By tapering the side surfaces in this manner, the coverage of the insulating layer 275 and the like can be improved in subsequent steps, and defects such as voids can be reduced.

[0228] Furthermore, without being limited to the above, the side surfaces of the insulating layer 224, the semiconductor layer 230, and the conductive layer 242 may be perpendicular or approximately perpendicular to the top surface of the insulating layer 222. With such a structure, a reduction in area and a high density can be achieved when providing a plurality of transistors.

[0229] In the lithography method, first, the resist is exposed through a mask. Next, the exposed region is removed or left using a developer to form a resist mask. Next, an etching process is performed through the resist mask, allowing a conductor, semiconductor, insulator, or the like to be processed into a desired shape. For example, a resist mask can be formed by exposing the resist using KrF excimer laser light, ArF excimer laser light, EUV (Extreme Ultraviolet) light, or the like. Alternatively, a liquid immersion technique may be used, in which a liquid (e.g., water) is filled between the substrate and the projection lens for exposure. Alternatively, an electron beam or an ion beam may be used instead of the light described above. When an electron beam or an ion beam is used, a mask may not be used in some cases.

[0230] The resist mask that is no longer needed after processing can be removed by performing a dry etching treatment such as ashing using oxygen plasma (hereinafter, sometimes referred to as oxygen plasma treatment), a wet etching treatment, a dry etching treatment followed by a wet etching treatment, or a wet etching treatment followed by a dry etching treatment.

[0231] Furthermore, a hard mask made of an insulating layer or a conductive layer may be used under the resist mask. When using a hard mask, an insulating or conductive film serving as the hard mask is formed on the conductive film 242f, a resist mask is formed thereon, and the hard mask is etched to a desired shape. For example, tungsten may be used as the hard mask. Etching of the conductive film 242f and the like may be performed after removing the resist mask or may be performed while leaving the resist mask. In the latter case, the resist mask may be lost during etching. The hard mask may be removed by etching after etching the insulating layer 275 and the like. On the other hand, if the material of the hard mask does not affect subsequent processes or can be used in subsequent processes, it is not necessarily necessary to remove the hard mask.

[0232] Alternatively, a spin-on-carbon (SOC) film and a spin-on-glass (SOG) film may be formed between the workpiece and the resist mask. Using the SOC film and the SOG film as a mask can improve adhesion with the resist mask and improve the durability of the mask pattern. For example, a lithography method can be performed by forming an SOC film, an SOG film, and a resist mask in this order on the workpiece.

[0233] As the etching gas for the dry etching process, an etching gas containing halogen can be used, and specifically, an etching gas containing one or more of fluorine, chlorine, and bromine can be used. ４ F ６ Gas, C ５ F ６ Gas, C ４ F ８ Gas, CF ４ Gas, SF ６ Gas, CHF ３ Gas, CH ２ F ２ Gas, Cl ２ Gas, BCl ３ Gas, SiCl ４ Gas, or BBr ３A gas such as a halogen gas or a fluorine gas can be used alone or in combination of two or more gases. Oxygen gas, carbon dioxide gas, nitrogen gas, helium gas, argon gas, hydrogen gas, or hydrocarbon gas can be added to the above-mentioned etching gas as appropriate. Depending on the object to be dry-etched, a gas containing no halogen gas but a hydrocarbon gas or hydrogen gas can be used as the etching gas. Examples of hydrocarbons used in the etching gas include methane (CH ４ ), ethane (C ２ H ６ ), propane (C ３ H ８ ), butane (C ４ H １０ ), ethylene (C ２ H ４ ), propylene (C ３ H ６ ), acetylene (C ２ H ２ ), and propyne (C ３ H ４ The etching conditions can be appropriately set depending on the target to be etched.

[0234] The dry etching apparatus may be a capacitively coupled plasma (CCP) etching apparatus having parallel-plate electrodes. The capacitively coupled plasma etching apparatus having parallel-plate electrodes may be configured to apply a high-frequency voltage to one of the parallel-plate electrodes. Alternatively, a high-frequency voltage of the same frequency may be applied to each of the parallel-plate electrodes. Alternatively, a plurality of different high-frequency voltages may be applied to the parallel-plate electrodes. Such a CCP etching apparatus is called a dual-frequency capacitively coupled plasma (DF-CCP) etching apparatus. The DF-CCP etching apparatus may be configured to apply high-frequency voltages of different frequencies to each of the parallel-plate electrodes. Alternatively, a plurality of different high-frequency voltages may be applied to one of the parallel-plate electrodes. Alternatively, a dry etching apparatus having a high-density plasma source can be used. The dry etching apparatus having a high-density plasma source can be, for example, an inductively coupled plasma (ICP) etching apparatus. The etching apparatus can be appropriately configured according to the object to be etched. In the above-mentioned dry etching apparatus, reactive ion etching can be performed by applying a high-frequency voltage to the electrode on the substrate side to generate a self-bias potential. In reactive ion etching, etching is performed by accelerating ion species in the plasma and causing them to collide with the workpiece, thereby enabling highly anisotropic etching.

[0235] 10A to 10D, an insulating layer 275 is formed to cover the insulating layer 224, the semiconductor layer 230, and the conductive layer 242, and an insulating layer 280 is further formed over the insulating layer 275. Note that after the insulating layer 280 is formed, it is preferable to perform CMP treatment to planarize the top surface of the insulating layer 280.

[0236] 8A to 10D , a semiconductor layer 230 containing indium oxide, a conductive layer 242 having a region in contact with the top surface of the semiconductor layer 230, and an insulating layer 275 having a region in contact with the top surface of the conductive layer 242 are formed. The conductive layer 242 is formed to contain an oxide containing indium and the first metal element. The conductive layer 242 is formed to have a single layer containing the oxide (oxide layer).

[0237] 11A to 11D , the insulating layer 280 and the insulating layer 275 are processed by lithography to form an opening 289 that reaches the conductive layer 242 and the insulating layer 222. The opening 289 has a region that overlaps with the semiconductor layer 230 and a region that overlaps with the conductive layer 205.

[0238] After the opening 289 is formed, the conductive layer 242 is processed using the same mask pattern as that used to form the opening 289, thereby forming the conductive layer 242a and the conductive layer 242b. Specifically, the conductive layer 242a and the conductive layer 242b are formed by removing a region of the conductive layer 242 that overlaps with the opening 289. The conductive layer 242a and the conductive layer 242b face each other across the opening 289. Here, by forming the conductive layer 242 with the above-described single oxide layer structure, the number of manufacturing steps of the semiconductor device can be reduced compared to, for example, when the conductive layer 242 has a stacked structure of two or more layers, thereby increasing the productivity of the semiconductor device. For example, the conductive layer 242 can be processed under the same conditions as those for forming the opening 289.

[0239] The conductive layer 242 contains an element contained in the semiconductor layer 230. Therefore, it is difficult to increase the etching selectivity between the conductive layer 242 and the semiconductor layer 230. Therefore, if the thickness of the conductive layer 242 is thicker than the thickness of the semiconductor layer 230, the semiconductor layer 230 may be divided by processing the conductive layer 242. Therefore, it is preferable to make the thickness of the conductive layer 242 thinner than the thickness of the semiconductor layer 230. Specifically, the thickness of the conductive layer 242 is set to be at least thinner than the thickness of the semiconductor layer 230, preferably ½ or less, more preferably ⅓ or less, and even more preferably ⅕ or less of the thickness of the semiconductor layer 230. This makes it possible to prevent the semiconductor layer 230 from being divided by the formation of the conductive layer 242a and the conductive layer 242b. Therefore, a semiconductor device can be manufactured by a method with a high yield. Since the etching selectivity between the semiconductor layer 230 and the conductive layer 242 is low, a recess 287 is formed in the semiconductor layer 230 at a position overlapping the opening 289, as shown in FIG. 11B.

[0240] The lithography method can be any of the above methods as appropriate. In order to finely process the opening 289, it is preferable to use a lithography method using short wavelength light such as EUV light or an electron beam.

[0241] 12A to 12D, an insulating film 250f that will become the insulating layer 250 is formed to cover the insulating layer 280 and the semiconductor layer 230.

[0242] Next, it is preferable to perform microwave treatment in an oxygen-containing atmosphere. Here, microwave treatment refers to treatment using, for example, a device having a power source that generates high-density plasma using microwaves. In addition, in this specification, microwaves refer to electromagnetic waves having a frequency of 300 MHz or more and 300 GHz or less.

[0243] In the microwave treatment, it is preferable to use a microwave treatment device having a power supply that generates high-density plasma using microwaves. Here, the frequency of the microwave treatment device is preferably 300 MHz to 300 GHz, more preferably 2.4 GHz to 2.5 GHz, for example, it can be 2.45 GHz. By using high-density plasma, high-density oxygen radicals can be generated. Furthermore, the power of the power supply that applies microwaves to the microwave treatment device is preferably 1000 W to 10,000 W, preferably 2000 W to 5,000 W. Furthermore, the microwave treatment device may have a power supply that applies RF to the substrate side. Furthermore, by applying RF to the substrate side, oxygen ions generated by high-density plasma can be efficiently introduced into the film.

[0244] The microwave treatment is preferably carried out under reduced pressure, and the pressure is preferably from 10 to 1000 Pa, and more preferably from 300 to 700 Pa. The treatment temperature is preferably from room temperature (25°C) to 750°C, more preferably from 300 to 500°C, and even more preferably from 400 to 450°C.

[0245] Alternatively, after the microwave treatment or plasma treatment, a heat treatment may be performed successively without exposure to the outside air. The temperature of the heat treatment is, for example, preferably 100° C. or higher and 750° C. or lower, more preferably 300° C. or higher and 500° C. or lower, and even more preferably 400° C. or higher and 450° C. or lower.

[0246] The microwave treatment can be carried out using, for example, oxygen gas and argon gas. Here, the oxygen flow rate ratio (O ２ / (O ２ +Ar)) is preferably greater than 0% and less than or equal to 100%, more preferably greater than 0% and less than or equal to 50%, even more preferably greater than or equal to 10% and less than or equal to 40%, and even more preferably greater than or equal to 10% and less than or equal to 30%.

[0247] When the insulating film 250f has a stacked structure, the microwave treatment is not necessarily performed after the insulating film 250f is formed. For example, when two or more layers are stacked as the insulating film 250f, the microwave treatment may be performed before forming a layer that will be in contact with the conductive layer 260 to be formed in a later step, or after forming a layer that will be in contact with the semiconductor layer 230, or after forming a layer that will be provided between them. The microwave treatment may be performed multiple times (at least two times or more).

[0248] 12A to 12D, a conductive film 260f, which will later become the conductive layer 260, is formed on the insulating film 250f. In this embodiment, the conductive film 260f is a stacked film of a titanium nitride film formed by an ALD method and a tungsten film formed on the titanium nitride film by a CVD method.

[0249] Next, the insulating film 250f and the conductive film 260f are polished by CMP treatment until the insulating layer 280 is exposed. That is, the portions of the insulating film 250f and the conductive film 260f exposed from the opening 289 are removed. As a result, the insulating layer 250 and the conductive layer 260 can be formed to have regions located inside the opening 289, as shown in FIGS. 13A to 13D . In this manner, the transistor 200 is manufactured.

[0250] 14A to 14D , an insulating layer 282 is formed over the insulating layer 250, the conductive layer 260, and the insulating layer 280, an insulating layer 283 is formed over the insulating layer 282, and an insulating layer 285 is formed over the insulating layer 283. In this embodiment, an aluminum oxide film is formed as the insulating layer 282 by a sputtering method, a silicon nitride film is formed as the insulating layer 283 by a sputtering method, and a silicon oxide film is formed as the insulating layer 285 by a sputtering method.

[0251] Next, the insulating layers 285, 283, 282, 280, and 275 are processed. As a result, as shown in FIGS. 15A to 15D , openings 243a and 243b are formed in the insulating layers 285, 283, 282, 280, and 275. The openings 243a and 243b have regions that overlap with the semiconductor layer 230 and are formed to face each other across the opening 289. The openings 243a and 243b can be formed using lithography. The openings 243a and 243b are preferably formed by processing the workpiece using dry etching. Dry etching is capable of anisotropic etching and is therefore suitable for forming openings with a high aspect ratio. When performing anisotropic etching, reactive ion etching, for example, is preferably used.

[0252] The conductive layers 242a and 242b are formed to have a smaller thickness than the semiconductor layer 230. Thus, in one embodiment of the present invention, when the openings 243a and 243b are formed, part of the conductive layer 242a and part of the conductive layer 242b are removed, so that the openings 243a and 243b reach the semiconductor layer 230. In this case, the openings 243a are also formed in the conductive layer 242a, and the openings 243b are also formed in the conductive layer 242b.

[0253] In the semiconductor device of one embodiment of the present invention, it is difficult to increase the etching selectivity between the semiconductor layer 230 and the conductive layers 242a and 242b. Therefore, a recess 244a overlapping with the opening 243a and a recess 244b overlapping with the opening 243b might be formed in the semiconductor layer 230.

[0254] 16A to 16D , a conductive film 245f to be the conductive layers 245a and 245b is formed so as to have a region located inside the opening 243a and a region located inside the opening 243b. The conductive film 245f is formed so as to have a region in contact with the semiconductor layer 230. In this embodiment, a film containing a second metal element is formed as the conductive film 245f by a sputtering method, a CVD method, or an ALD method. Examples of the second metal element include titanium, tin, and zirconium.

[0255] After the conductive film 245f is formed, a conductive film 246f to be the conductive layer 246a and the conductive layer 246b is formed so as to fill the openings 243a and 243b. The conductive film 246f is formed using a material having higher electrical conductivity than the conductive film 245f. In this embodiment, a tungsten film, a copper film, an aluminum film, or a molybdenum film is formed as the conductive film 246f by a sputtering method, a CVD method, or an ALD method.

[0256] Subsequently, CMP treatment is performed to remove a portion of the conductive film 246f and a portion of the conductive film 245f, thereby exposing the upper surface of the insulating layer 285. As a result, the conductive films 245f and 246f remain inside the openings 243a and 243b, respectively, thereby forming a conductive layer 245a having a region located inside the openings 243a, a conductive layer 245b having a region located inside the openings 243b, a conductive layer 246a having a region located inside the openings 243a, and a conductive layer 246b having a region located inside the openings 243b, as shown in FIGS. 17A to 17D . As a result, a first plug located inside the openings 243a and a second plug located inside the openings 243b are formed. Note that the above-described CMP treatment may remove a portion of the upper surface of the insulating layer 285.

[0257] The conductive layer 245a and the conductive layer 245b are formed to have regions in contact with the semiconductor layer 230. As described above, the semiconductor layer 230 may have recesses 244a and 244b formed therein. In this case, the conductive layer 245a can be formed to have a region in contact with the upper surface of the semiconductor layer 230, specifically the upper surface of the recess 244a, as well as a region in contact with the side surface of the recess 244a. Similarly, the conductive layer 245b can be formed to have a region in contact with the upper surface of the semiconductor layer 230, specifically the upper surface of the recess 244b, as well as a region in contact with the side surface of the recess 244b. As a result, the contact area between the semiconductor layer 230 and the conductive layer 245a can be made larger than when the recess 244a is not formed in the semiconductor layer 230. Similarly, the contact area between the semiconductor layer 230 and the conductive layer 245b can be made larger than when the recess 244b is not formed in the semiconductor layer 230.

[0258] The conductive layer 246a is formed on the conductive layer 245a so as to fill the opening 243a. Similarly, the conductive layer 246b is formed on the conductive layer 245b so as to fill the opening 243b. The conductive layer 246a is formed to have a higher electrical conductivity than the conductive layer 245a. Similarly, the conductive layer 246b is formed to have a higher electrical conductivity than the conductive layer 245b.

[0259] Subsequently, heat treatment is performed. As a result, the material contained in the conductive layer 245a and the material contained in the conductive layer 245b are diffused into the semiconductor layer 230. Therefore, the material contained in the conductive layer 245a and the material contained in the conductive layer 245b are supplied to the semiconductor layer 230 as impurity elements, and some of the elements contained in the semiconductor layer 230 can be replaced with the impurity elements. For example, when an indium oxide film is formed as the semiconductor layer 230, some of the indium can be replaced with the impurity elements. As a result, a low-resistance region 230na containing an element contained in the conductive layer 245a and a low-resistance region 230nb containing an element contained in the conductive layer 245b are formed. For example, when an indium oxide film is formed as the semiconductor layer 230, an element having a valence different from that of indium is contained in the conductive layer 245a and the conductive layer 245b, thereby forming the low-resistance region 230na and the low-resistance region 230nb, respectively.

[0260] The low-resistance region 230na is formed to have a region overlapping with the conductive layer 245a. Similarly, the low-resistance region 230nb is formed to have a region overlapping with the conductive layer 245b. Note that the impurity elements contained in the low-resistance region 230na can also be supplied to the conductive layer 242a. Similarly, the impurity elements contained in the low-resistance region 230nb can also be supplied to the conductive layer 242b.

[0261] The temperature of the heat treatment is preferably 200° C. or higher and 800° C. or lower, more preferably 300° C. or higher and 600° C. or lower. Note that the heat treatment is not necessary when the elements contained in the conductive layer 245a and the elements contained in the conductive layer 245b can be supplied to the semiconductor layer 230 without performing the heat treatment. For example, when one or both of the deposition temperatures of the conductive film 245f and the conductive film 246f are the temperatures of the heat treatment, the heat treatment is not necessary.

[0262] As described above, by forming the recesses 244a and 244b in the semiconductor layer 230, the contact area between the semiconductor layer 230 and the conductive layer 245a and the contact area between the semiconductor layer 230 and the conductive layer 245b can be increased compared to when the recesses 244a and 244b are not formed. This makes it easier to form the low-resistance regions 230na and 230nb. For example, the volumes of the low-resistance regions 230na and 230nb can be increased. As a result, a semiconductor device with high operating speed can be manufactured.

[0263] In this manner, the semiconductor device shown in FIGS. 1A to 2B can be manufactured.

[0264] When fabricating the semiconductor device shown in FIGS. 7A and 7B, first, the steps shown in FIGS. 8A to 10D are performed, and then, as shown in FIGS. 11A to 11D, openings 289 are formed in the insulating layer 280 and the insulating layer 275. Note that the conductive layer 242 is not processed. Subsequently, an insulating layer 255 is formed to cover the insulating layer 280 and the conductive layer 242. Subsequently, openings 290 overlapping with the openings 289 are formed in the insulating layer 255 by, for example, lithography. Subsequently, the conductive layer 242 is removed from the region overlapping with the openings 290, thereby forming the conductive layers 242a and 242b. Thereafter, the steps shown in FIGS. 12A to 17D are performed. In this manner, the semiconductor device shown in FIGS. 7A and 7B can be fabricated.

[0265] This embodiment mode can be combined with other embodiment modes as appropriate. In addition, in this specification, when a plurality of configuration examples are shown in one embodiment mode, the configuration examples can be combined as appropriate.

[0266] Embodiment 2 In this embodiment, an indium oxide film that can be used for a semiconductor layer of a transistor included in a semiconductor device of one embodiment of the present invention will be described.

[0267] In this specification and the like, indium oxide having at least a crystalline portion or a crystalline region in a film is referred to as crystalline indium oxide (crystal IO) or crystalline indium oxide (crystalline IO). Examples of crystalline IO or crystalline IO include single-crystalline indium oxide, polycrystalline indium oxide, and microcrystalline indium oxide.

[0268] Indium oxide is a semiconductor material having physical properties that are completely different from those of oxide semiconductors such as In—Ga—Zn oxide (hereinafter also referred to as IGZO) and zinc oxide.

[0269] The carrier concentration dependence of the Hall mobility of indium oxide, silicon, and IGZO will be explained. FIG. 18A shows the carrier concentration dependence of the Hall mobility of silicon (Si) and indium oxide (InO Ｘ ) and FIG. 18B is a schematic diagram showing the carrier concentration dependence of the hole mobility for IGZO.

[0270] First, IGZO tends to exhibit higher hole mobility as the carrier concentration increases, as shown by the arrows in Figure 18B. On the other hand, indium oxide tends to exhibit higher hole mobility as the carrier concentration decreases, as shown by the arrows in Figure 18A (see Non-Patent Document 3). This trend is similar to that of silicon; the lower the dopant (impurity) concentration in the material, the less impurity scattering there is and the higher the hole mobility. In other words, the higher the purity and intrinsic indium oxide, the higher the hole mobility. From these results, it can be said that indium oxide, unlike IGZO, is a material with physical properties similar to those of silicon. Note that the characteristics of indium oxide shown in Figure 18A are assumed to be single crystal. Therefore, when indium oxide is non-single crystal (e.g., polycrystalline), the characteristics may differ from those shown in Figure 18A.

[0271] 18A, the range R1 of low carrier concentration has extremely high hole mobility, and therefore can be said to be a range of carrier concentration suitable for, for example, a channel formation region of a transistor. For example, in the case of indium oxide, the range R1 is a range where the carrier concentration value is 1×10 １５ cm −３ The range includes, for example, 1×10 １４ cm −３ That's it, 1 x 10 １８ cm −３ By sufficiently reducing the carrier concentration, the Hall mobility value can be increased to 270 cm ２ It is expected that the resistance can be increased to about / (V·s).

[0272] In addition, in indium oxide, the region where the carrier concentration is in the range R1 may contain an element that lowers the carrier concentration. Examples of elements that lower the carrier concentration include magnesium, calcium, zinc, cadmium, and copper. By substituting these elements for indium, the carrier concentration can be lowered. Examples of elements that lower the carrier concentration include nitrogen, phosphorus, arsenic, and antimony. For example, by substituting nitrogen, phosphorus, arsenic, or antimony for oxygen, the carrier concentration can be lowered.

[0273] On the other hand, the range R2 with a high carrier concentration has a low electrical resistance, and can be said to be a range of carrier concentrations suitable for, for example, the source and drain regions of a transistor, a resistor, or a transparent conductive film. ２０ cm −３ The range includes, for example, 1×10 １９ cm −３ That's it, 1 x 10 ２２ cm −３ By increasing the carrier concentration sufficiently, the resistivity can be reduced to 1×10 −４ It is expected that the resistivity can be reduced to Ω·cm or less.

[0274] In addition, in indium oxide, the region where the carrier concentration is in the range R2 may contain an element that increases the carrier concentration. For example, it is preferable that the indium oxide contains an element that is common to the source electrode and drain electrode of the transistor. Examples of elements that increase the carrier concentration include titanium, zirconium, hafnium, tantalum, tungsten, molybdenum, tin, silicon, and boron. In particular, it is more preferable to use an element whose oxide has conductive or semiconducting properties. Note that, as a method for supplying an element that increases the carrier concentration, a method of forming a film containing the element and diffusing it, ion implantation, ion doping, plasma immersion ion implantation, or plasma treatment can be used. Note that, unless otherwise specified in this specification, the presence or absence of mass separation is not limited. For example, in this specification, a method of supplying ions after mass separation is referred to as an ion implantation method, and a method of supplying ions without mass separation is referred to as an ion doping method.

[0275] In this way, indium oxide uses a region with a low carrier concentration as the channel formation region of a transistor, and a region with a high carrier concentration as the source and drain regions of the transistor. In other words, indium oxide can be said to be an oxide capable of valence electron control. Note that IGZO may experience strain in the source and drain regions due to stress from electrodes in contact with the IGZO, resulting in the formation of n-type regions. On the other hand, unlike IGZO, indium oxide is capable of valence electron control, and therefore does not require strain to be formed in the film as with IGZO. Less strain in the film is expected to improve reliability. For example, by separately creating a region with a carrier concentration in the range R1 shown in FIG. 18A and a region with a carrier concentration in the range R2 in the indium oxide film, a so-called n-i-n junction (a junction between an n-type region, an i-type region, and an n-type region) can be created. Note that valence electron control in transistors using silicon is generally known. On the other hand, valence electron control in transistors using indium oxide is a novel technical concept that would not normally be conceived.

[0276] By using the above technical concept, the transistor having indium oxide in this specification and the like has two or more, preferably three or more, more preferably four or more, and most preferably five of the following characteristics (1) to (5): (1) high on-current (in other words, high mobility); (2) low off-current; (3) normally-off operation; (4) high reliability; and (5) high cutoff frequency (fT). For example, the transistor having indium oxide in this specification and the like has high mobility, low off-current, and is normally-off operation. The transistor has high mobility and is different from a normally-on transistor.

[0277] In addition, a semiconductor being i-type can be rephrased as having the same Fermi level (Ef) and intrinsic Fermi level (Ei) (Ef = Ei). As shown in FIG. 18B, in IGZO, the lower the carrier concentration, the smaller the hole mobility. Therefore, when Ef = Ei finally occurs, the carriers disappear (in other words, the physical properties become similar to those of an insulator), and there is a possibility that the transistor will no longer function. On the other hand, in indium oxide, as shown in FIG. 18A, the lower the carrier concentration, the higher the hole mobility. When Ef = Ei finally occurs, the hole mobility is maximized. In other words, a transistor containing indium oxide can achieve high field-effect mobility by setting Ef = Ei. Note that a transistor containing indium oxide is likely to be normally-off due to its low carrier concentration. Therefore, a transistor containing indium oxide can be normally-off and achieve high field-effect mobility.

[0278] Note that normally-off refers to a state in which no current flows through a transistor when no potential is applied to the gate or when the gate-source voltage is 0 V. Furthermore, normally-off can be evaluated by the threshold voltage (Vth) or shift value (Vsh) of the transistor. Unless otherwise specified, Vth is calculated by a constant current method. More specifically, Vth refers to a state in which the value of drain current (Id) × channel length (L) ÷ channel width (W) in the Id-Vg characteristics of a transistor is 1 nA (1 × 10 −９ A). Vsh is the gate voltage (Vg) when the drain current (Id) in the Id-Vg characteristic of the transistor is expressed logarithmically and the tangent of the maximum slope is Id = 1 pA (1 × 10 −１２ The gate voltage (Vg) is the intersection point between the line of Id = 1 pA and the line extrapolated from two points where the slope of Id is maximum when Id is expressed logarithmically in the Id-Vg characteristics of the transistor. For example, if either or both of Vth and Vsh are zero or a positive value, the transistor can be considered to be normally-off.

[0279] In addition, in a transistor containing indium oxide, in order to make the semiconductor i-type, that is, to achieve Ef = Ei, the film structure in contact with the indium oxide film is important. For example, in a transistor containing indium oxide, a film structure in which a silicon oxide film in contact with the indium oxide film, a hafnium oxide film, and a silicon nitride film are stacked is exemplified. By using this film structure, a semiconductor device with high reliability and Ef = Ei can be obtained.

[0280] In the above film configuration, a film containing oxygen, such as a silicon oxynitride film, a silicon nitride oxide film, an aluminum oxide film, or a gallium oxide film, can be used instead of the silicon oxide film. Also, in the above film configuration, a silicon nitride oxide film, a silicon oxynitride film, or the like can be used instead of the silicon nitride film. The hafnium oxide film, which is located closer to the indium oxide film than the silicon nitride film, functions as a gettering site for hydrogen.

[0281] The above film configuration can also be considered as a stacked structure of a film (e.g., a silicon oxide film) capable of supplying oxygen to the indium oxide film from the indium oxide film side, a film (e.g., a hafnium oxide film) capable of gettering hydrogen, and a film (e.g., a silicon nitride film) that suppresses the penetration of oxygen and hydrogen. With this configuration, oxygen vacancies in the indium oxide film are filled with oxygen in the silicon oxide film. Hydrogen in the indium oxide film is captured by the hafnium oxide film by heat treatment or the like. Furthermore, the provision of the silicon nitride film results in a film configuration that reduces the penetration of oxygen and hydrogen from the outside. That is, with the above film configuration, the indium oxide film can be made closer to i-type. Therefore, a transistor having the above-described indium oxide film has high field-effect mobility and high reliability.

[0282] Next, an indium oxide film applied to a transistor will be described. The indium oxide film preferably has crystallinity (i.e., has crystal grains). Examples of films having crystal grains include single-crystal films, polycrystalline films, and amorphous films containing crystal grains (also called microcrystalline films). In particular, the indium oxide film is preferably a polycrystalline film, and more preferably a single-crystal film. A single-crystal film does not have grain boundaries. Impurities (typically, insulating impurities, insulating oxides, etc.) that hinder carrier flow tend to segregate at grain boundaries. The use of a single-crystal film can suppress carrier scattering at grain boundaries, thereby realizing a transistor exhibiting high field-effect mobility. Furthermore, the use of a single-crystal film has the excellent effect of suppressing variations in transistor characteristics due to the grain boundaries.

[0283] Furthermore, polycrystalline films are preferable because they can reduce carrier scattering and exhibit high field-effect mobility compared to microcrystalline or amorphous films. When using a polycrystalline film, it is preferable to use a film with as large a crystal grain size as possible and with few crystal grain boundaries. Note that in a transistor using an indium oxide polycrystalline film, if there is no crystal grain boundary in the channel formation region or no crystal grain boundary is observed, the channel formation region is located within a single crystal region included in the polycrystalline film, and therefore the transistor can be considered to be using single-crystal indium oxide.

[0284] The crystallinity of indium oxide can be analyzed by, for example, X-ray diffraction (XRD), transmission electron microscope (TEM), or electron diffraction (ED). Alternatively, a combination of these methods may be used for analysis.

[0285] In this specification and the like, a semiconductor layer in which no crystal grain boundary is observed in the channel formation region, a semiconductor layer in which the channel formation region is included in one crystal grain, or a semiconductor layer in which the crystal axis direction is the same in at least two regions in the channel formation region can be called a single crystal film. Also, a semiconductor layer in which, in the channel formation region, within one crystal grain, the direction of another crystal axis continuously changes around a certain crystal axis or a certain crystal orientation as the axis of rotation can be called a single crystal film.

[0286] The channel formation region refers to a region of the semiconductor layer that overlaps (or faces) the gate electrode via the gate insulating layer, and is located between the region in contact with the source electrode and the region in contact with the drain electrode. The current path in the channel formation region is the shortest distance between the source electrode and the drain electrode. Therefore, the crystal grains, crystal grain boundaries, crystal axes, crystal orientation, etc. in the channel formation region can be confirmed by observing a cross section including the semiconductor layer, the source electrode, and the drain electrode.

[0287] The indium oxide film in the channel formation region preferably has a lower impurity concentration. Impurities in the indium oxide film in the channel formation region can be a scattering source of carriers, which can lead to a decrease in field-effect mobility. These impurities can also hinder the crystal growth of the indium oxide film. Examples of impurities in the indium oxide film include boron and silicon. The indium oxide film preferably contains these impurities at concentrations of 0.1% or less, and more preferably 0.01% (100 ppm) or less. Carbon, hydrogen, and other elements may be contained in the film-forming gas or precursor during film formation, and may remain in the indium oxide film in greater amounts than the above-mentioned impurities.

[0288] The indium oxide film in the channel formation region may contain an element that can become the same trivalent cation as indium, as long as the crystal maintains a cubic crystal structure (bixbyite type). Examples of such an element include Group 13 elements of the periodic table, such as gallium and aluminum, and Group 3 elements of the periodic table. These elements exist mainly as trivalent cations in oxides, and therefore the carrier concentration of indium oxide can be maintained low.

[0289] In addition, the indium oxide film in this specification and the like has a high film density. ２ O ３ The film densities of the films are shown in Table 1.

[0290]

[0291] As shown in Table 1, the film density of the indium oxide film was evaluated at six levels, Sample 1 to Sample 6. In Table 1, Condition 1 is the condition of the base of the indium oxide film, Samples 1 to 3 are glass, Sample 4 is a SiOx film formed by sputtering, and Samples 5 and 6 are yttria-stabilized zirconia (YSZ). Condition 2 is the film formation condition of the indium oxide film, Samples 1 to 3 are film formation by sputtering (SP), and Samples 4 to 6 are film formation by ALD. Condition 3 is the heat treatment condition after the formation of the indium oxide film, with Sample 1, Sample 4, and Sample 5 being no heat treatment (as-deposited), Sample 2 being baked at 350°C in a CDA atmosphere, Sample 3 being baked at 650°C in a CDA atmosphere, and Sample 6 being baked at 250°C in a vacuum atmosphere.

[0292] In Table 1, CDA stands for clean dry air. It is preferable that the atmosphere used in the heat treatment (condition 3) after the formation of the indium oxide film contains as little hydrogen and water as possible. It is preferable to use a high-purity gas with a dew point of −60° C. or lower, preferably −100° C. or lower, as the atmosphere.

[0293] As shown in Table 1, the indium oxide film tends to have a higher film density when subjected to heat treatment compared to when not subjected to heat treatment (Sample 1, Sample 4, or Sample 5). This is because the heat treatment removes impurity elements (e.g., carbon, nitrogen, hydrogen, argon, etc.) from the film, thereby increasing the purity of the indium oxide film. Furthermore, as shown in Samples 5 and 6, the indium oxide film on YSZ has a film density of 7.00 g / cm. ３ The theoretical film density of an indium oxide film is 7.18 g / cm ３ In this specification, the range of the film density of the indium oxide film is 6.70 g / cm ３ 7.18g / cm or more ３ Preferably, it is 6.90 g / cm or less.３ 7.18g / cm or more ３ More preferably, it is 7.00 g / cm or less. ３ 7.18g / cm or more ３ The following is the result.

[0294] The film density can be evaluated by, for example, Rutherford backscattering spectroscopy (RBS) or X-ray reflectometry (XRR). Differences in film density can sometimes be evaluated by cross-sectional transmission electron microscope (TEM) images. In TEM observation, a high film density results in a dense (dark) transmission electron (TE) image, whereas a low film density results in a faint (bright) transmission electron (TE) image.

[0295] By using such an indium oxide film in a transistor, the field effect mobility of the transistor can be increased to 50 cm ２ / (V·s) or more, preferably 100 cm ２ / (V·s) or more, more preferably 150 cm ２ / (V·s) or more, more preferably 200 cm ２ / (V·s) or more, more preferably 250 cm ２ / (V·s) or more.

[0296] One of the features of an indium oxide film is that it has higher oxygen permeability (diffusibility) than an IGZO film. As shown in FIG. 18C, an indium oxide film (InO Ｘ Oxygen (O) diffusing into the indium oxide film passes through the indium oxide film and becomes oxygen molecules (O ２ ) and is released as water molecules (H ２ O) may be released in the film. Ｏ In the case where an indium oxide film is present, oxygen atoms diffuse to compensate for the oxygen vacancies. Since oxygen diffuses easily in the indium oxide film, it can be said that oxygen vacancies are more easily compensated for in the indium oxide film than in the IGZO film.

[0297] As described above, an indium oxide film can more easily reduce oxygen vacancies in the film than an IGZO film. Therefore, by using such an indium oxide film in a transistor, a transistor exhibiting extremely high reliability can be realized.

[0298] Furthermore, as shown in FIG. 18C, the indium oxide film diffuses hydrogen. Hydrogen that diffuses into the indium oxide film from the outside passes through the indium oxide film and becomes hydrogen molecules (H ２ ) or reacts with oxygen contained in the film and is released as water molecules. The oxygen and hydrogen diffuse in the indium oxide film by heat treatment. The temperature of the heat treatment is 200° C. or higher and 700° C. or lower, preferably 350° C. or higher and 650° C. or lower, and more preferably 400° C. or higher and 500° C. or lower.

[0299] A transistor using an indium oxide film is an accumulation-type transistor that uses electrons as majority carriers. Assuming that the carrier relaxation time is constant, the smaller the effective mass of the electrons (carriers), the higher the electron mobility. In other words, by using indium oxide, which has a small effective mass of electrons, for a transistor, the on-state current or field-effect mobility of the transistor can be increased.

[0300] Table 2 shows the results of single crystal indium oxide (here, In ２ O ３ ) and single-crystal silicon (Si). As shown in Table 2, indium oxide is characterized by a small effective mass of electrons and a large effective mass of holes. Indium oxide also has the characteristic that the effective mass of electrons is almost independent of the crystal orientation. Therefore, by using crystalline indium oxide in a transistor, a transistor with high field-effect mobility and high frequency characteristics (also called f characteristics) can be realized. Furthermore, since the effective mass of holes is large, a transistor with extremely small off-current can be realized. For example, by applying an indium oxide film to a vertical transistor, the off-current per 1 μm of channel width can be reduced to 1 fA (1×10) in an environment of 125° C. −１５ A) or less, or 1aA (1 x 10 −１８ A) or less, and under room temperature (25°C) conditions, −１８ A) or less, or 1zA (1 x 10 −２１Furthermore, as shown in Table 2, indium oxide has a smaller effective mass of electrons and a larger effective mass of holes than silicon, and therefore may be able to realize a transistor with higher field-effect mobility and lower off-state current than a Si transistor.

[0301]

[0302] It is preferable to provide a seed layer so as to be in contact with at least a portion of the crystalline indium oxide film. The seed layer is preferably made of a material containing crystals with a small difference in lattice constant (also called lattice mismatch) with indium oxide. This can improve the crystallinity of the indium oxide film. Note that a substrate (e.g., a single-crystal substrate) may be used as one of the layers in contact with at least a portion of the crystalline indium oxide film.

[0303] One method for evaluating the degree of lattice mismatch is to use the value of the lattice mismatch shown below. The lattice mismatch Δa [%] of the crystals of the formed film (here, the indium oxide film) with respect to the crystals of the seed layer is expressed as Δa = ((L １ -L ２ ) / L ２ ) × 100, where L １ is the length or lattice constant of the unit lattice vector of the crystal of the formed film, and L ２ is the length of the unit cell vector or the lattice constant of the crystal of the seed layer.

[0304] The smaller the absolute value of the lattice mismatch Δa between the seed layer and the indium oxide film, the more preferable, and it is most preferably 0. For example, Δa can be set to −5% or more and 5% or less, preferably −4% or more and 4% or less, more preferably −3% or more and 3% or less, and even more preferably −2% or more and 2% or less.

[0305] Here, the indium oxide crystal has a cubic crystal structure (bixbyite type). For example, the crystal of yttria-stabilized zirconia (YSZ) can have a cubic crystal structure (fluorite type). The lattice mismatch of the indium oxide crystal with the cubic YSZ crystal is in the range of −2% to 2%, and a single crystal film of indium oxide can be epitaxially grown on the YSZ substrate.

[0306] It should be noted that the crystal structure of the seed layer and the crystal structure of the indium oxide film may not necessarily have the same crystal system or crystal orientation. For example, a film having crystals of a hexagonal or trigonal structure may be used under an indium oxide film having crystals of a cubic structure. For example, by setting the crystal orientation of the surface of the seed layer to

[001] and the crystal orientation of the underside of the indium oxide film to

[111] , the requirements related to the crystal orientation necessary for epitaxial growth can be satisfied. Examples of hexagonal or trigonal crystals include wurtzite structure, YbFe ２ O ４ Type structure, Yb ２ Fe ３ O ７ YbFeFe alloys have the following structures: ２ O ４ Type structure or Yb ２ Fe ３ O ７ An example of a crystal having a crystalline structure is IGZO. It should be noted that a single crystal film of indium oxide can be formed not only on a YSZ substrate but also on an insulating film. On the other hand, it is difficult to form a single crystal film of silicon on an insulating film. Silicon crystals have a diamond structure. As such, indium oxide and silicon have similar properties in terms of single crystal. However, when comparing indium oxide and silicon in terms of whether they can be formed as single crystals on an insulating film, they have different properties.

[0307] Here, a comparison is made among a transistor having a crystalline indium oxide film, a transistor having an IGZO (a compound oxide of In, Ga, and Zn) film, and a transistor having a silicon (Si) film. The comparison is shown in Table 3.

[0308]

[0309] In Table 3, transistors having a crystalline indium oxide film are intended for use in LSIs and are clearly indicated as crystalline IO (LSI). Hereinafter, this may be simply referred to as crystalline IO. Transistors having an IGZO film are intended for use in displays and are clearly indicated as IGZO (Display). Hereinafter, this may be simply referred to as IGZO. Transistors having a Si film are also clearly indicated as Si. In Table 3, ◎ represents +2 points, ○ represents +1 point, △ represents 0 points, and × represents −1 point, respectively. Total is the total value of the ◎, ○, △, and × points shown in Table 3. A higher score indicates better characteristics than a lower score.

[0310] In Table 3, the first comparison item is extremely small off-state current, with crystalline IO and IGZO being superior to Si. The second comparison item is on-state current (Ion) characteristics, with crystalline IO and Si being superior to IGZO. The third comparison item is reliability, with crystalline IO and Si being superior to IGZO. The fourth comparison item is miniaturization of channel length, with crystalline IO and IGZO being superior to Si. In the section on miniaturization of channel length, VFET represents a vertical transistor, UFET represents a transistor with a U-shape structure, and 3D structure represents a three-dimensional structure. The fifth comparison item is cutoff frequency, with the characteristics increasing in the order of crystalline IO, Si, and IGZO. The sixth comparison item is improvement in integration, with Si being superior to crystalline IO and IGZO. The seventh comparison item is threshold voltage controllability (Vth controllability), in which Si is superior to crystalline IO and IGZO. The eighth comparison item is radiation resistance, in which crystalline IO and IGZO are superior to Si. The ninth comparison item is 3D (multi-level) integrated structure, in which crystalline IO and IGZO are superior to Si. The tenth comparison item is the possibility of self-heating, in which crystalline IO and IGZO are superior to Si.

[0311] As shown in Table 3, the total score for crystalline IO (LSI) is 9 points, for IGZO (Display) is 4 points, and for Si is 3 points. As described above, the semiconductor device of one embodiment of the present invention, in particular the semiconductor device including a crystalline indium oxide film, has the potential to replace a semiconductor device using Si.

[0312] This embodiment mode can be combined with other embodiment modes as appropriate. In addition, in this specification, when a plurality of configuration examples are shown in one embodiment mode, the configuration examples can be combined as appropriate.

[0313] Embodiment 3 In this embodiment, a semiconductor device 900 according to one embodiment of the present invention will be described. The semiconductor device 900 can function as a memory device.

[0314] Fig. 19 is a block diagram showing a configuration example of a semiconductor device 900. The semiconductor device 900 shown in Fig. 19 has a driver circuit 910 and a memory array 920. The memory array 920 has one or more memory cells 950. Fig. 19 shows an example in which the memory array 920 has a plurality of memory cells 950 arranged in a matrix.

[0315] The transistor 200 described in Embodiment 1 can be applied to the memory cell 950. By using the transistor described in Embodiment 1, the operation speed of the memory device can be improved. Furthermore, miniaturization and high integration of the memory device can be achieved. Furthermore, the capacitance per area of ​​the memory device can be increased.

[0316] The drive circuit 910 includes a PSW 931 (power switch), a PSW 932, and a peripheral circuit 915. The peripheral circuit 915 includes a peripheral circuit 911, a control circuit 912, and a voltage generation circuit 928.

[0317] In the semiconductor device 900, each circuit, signal, and voltage can be appropriately selected or omitted as needed. Alternatively, other circuits or signals may be added. The signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are input signals from the outside, and the signal RDA is an output signal to the outside. The signal CLK is a clock signal.

[0318] Furthermore, signals BW, CE, and GW are control signals. Signal CE is a chip enable signal, signal GW is a global write enable signal, and signal BW is a byte write enable signal. Signal ADDR is an address signal. Signal WDA is a write data signal, and signal RDA is a read data signal. Signals PON1 and PON2 are power gating control signals. Note that signals PON1 and PON2 may be generated by the control circuit 912.

[0319] The control circuit 912 is a logic circuit having a function of controlling the overall operation of the semiconductor device 900. For example, the control circuit 912 performs a logical operation on the signals CE, GW, and BW to determine the operation mode (e.g., write operation, read operation) of the semiconductor device 900. Alternatively, the control circuit 912 generates a control signal for the peripheral circuit 911 so that this operation mode is executed.

[0320] The voltage generating circuit 928 has a function of generating a negative voltage. The signal WAKE has a function of controlling the input of the signal CLK to the voltage generating circuit 928. For example, when an H-level signal is given as the signal WAKE, the signal CLK is input to the voltage generating circuit 928, and the voltage generating circuit 928 generates a negative voltage.

[0321] The peripheral circuit 911 is a circuit for writing and reading data to and from the memory cells 950. The peripheral circuit 911 includes a row decoder 941, a column decoder 942, a row driver 923, a column driver 924, an input circuit 925, an output circuit 926, and a sense amplifier 927.

[0322] The row decoder 941 and the column decoder 942 have the function of decoding the signal ADDR. The row decoder 941 is a circuit for specifying a row to be accessed, and the column decoder 942 is a circuit for specifying a column to be accessed. The row driver 923 has the function of selecting the row specified by the row decoder 941. The column driver 924 has the function of writing data to the memory cells 950, reading data from the memory cells 950, and retaining the read data.

[0323] The input circuit 925 has a function of holding a signal WDA. The data held by the input circuit 925 is output to the column driver 924. The output data of the input circuit 925 is data (Din) to be written to the memory cell 950. The data (Dout) read from the memory cell 950 by the column driver 924 is output to the output circuit 926. The output circuit 926 has a function of holding Dout. In addition, the output circuit 926 has a function of outputting Dout to the outside of the semiconductor device 900. The data output from the output circuit 926 is a signal RDA.

[0324] The PSW 931 is a V ＤＤ The PSW 932 has the function of controlling the supply of V to the row driver 923. ＨＭ Here, the high power supply potential of the semiconductor device 900 is V ＤＤ and the low power supply potential is GND (ground potential). ＨＭ is the high power supply potential used to drive the word line high, and V ＤＤ 19, in the peripheral circuit 915, V ＤＤ Although the number of power domains to which power is supplied is set to one, it is also possible to set it to a plurality of power domains. In this case, a power switch is provided for each power domain.

[0325] 20A to 20G, examples of memory cell configurations that can be applied to the memory cell 950 will be described.

[0326] 20A shows an example of a circuit configuration of a memory cell of a dynamic random access memory (DRAM). In this specification and the like, a DRAM using an OS transistor is referred to as a dynamic oxide semiconductor random access memory (DOSRAM). The memory cell 951 includes a transistor M1 and a capacitor CA.

[0327] The transistor M1 may have a front gate (sometimes simply referred to as a gate) and a back gate. In this case, the back gate may be connected to a wiring to which a constant potential or a signal is applied, or the front gate and the back gate may be connected to each other.

[0328] One of the source and drain of the transistor M1 is connected to one electrode of the capacitor CA, the other of the source and drain of the transistor M1 is connected to a wiring BIL, and the gate of the transistor M1 is connected to a wiring WOL. The other electrode of the capacitor CA is connected to a wiring CAL.

[0329] The wiring BIL functions as a bit line, and the wiring WOL functions as a word line. The wiring CAL functions as a wiring for applying a predetermined potential to the other electrode of the capacitor CA. When writing and reading data, it is preferable to apply a low-level potential (sometimes referred to as a reference potential) to the wiring CAL.

[0330] Data is written and read by applying a high-level potential to the wiring WOL, turning on the transistor M1, and bringing the wiring BIL and one electrode of the capacitor CA into an electrically conductive state (a state in which current can flow).

[0331] Furthermore, the memory cell that can be used for the memory cell 950 is not limited to the memory cell 951, and the circuit configuration can be changed. For example, the memory cell 952 shown in FIG. 20B may be used. The memory cell 952 is an example in which the memory cell 952 does not include a capacitor CA and a wiring CAL. One of the source and drain of the transistor M1 is electrically floating.

[0332] In the memory cell 952, the potential written through the transistor M1 is held in a capacitance (also referred to as a parasitic capacitance) between the gate and one of the source and drain of the transistor M1. In Figure 20B, the parasitic capacitance is indicated by a dashed line. With this configuration, the configuration of the memory cell can be significantly simplified.

[0333] Note that an OS transistor is preferably used as the transistor M1. Use of an OS transistor can improve the operation speed of the memory device. Furthermore, an OS transistor has a characteristic of having an extremely low off-state current. By using an OS transistor as the transistor M1, the leakage current of the transistor M1 can be made extremely small. That is, written data can be held by the transistor M1 for a long time, which reduces the frequency of refreshing the memory cell. Alternatively, the refresh operation of the memory cell can be made unnecessary. Furthermore, since the leakage current is extremely small, multilevel data or analog data can be held in the memory cell 951 and the memory cell 952.

[0334] An example of the structure of a DOSRAM will now be described with reference to Fig. 21. In Fig. 21, the X direction is parallel to the channel width direction of the transistor, the Y direction is perpendicular to the X direction, and the Z direction is perpendicular to the X and Y directions.

[0335] 21 , the memory cell 951 includes a transistor M1 and a capacitor CA. The capacitor CA includes a conductive layer 410, an insulating layer 430 on the conductive layer 410, and a conductive layer 420 on the insulating layer 430. The conductive layer 410 functions as one electrode of the capacitor CA. The conductive layer 420 functions as the other electrode of the capacitor CA. The insulating layer 430 functions as a dielectric of the capacitor CA. The capacitor CA forms a metal-insulator-metal (MIM) capacitor.

[0336] 21 shows an example in which the shape of the capacitor CA is a planar type, but the memory device described in this embodiment is not limited to this. For example, the shape of the capacitor CA may be a cylindrical type.

[0337] The conductive layer 410 and the conductive layer 420 can be formed using, for example, a material that can be used for the conductive layer 260. The conductive layer 410 and the conductive layer 420 can be formed using, for example, tungsten. FIG. 21 shows an example in which the insulating layer 430 and the conductive layer 420 on the insulating layer 430 cover the top surface and side surfaces of the conductive layer 410. This allows the side surfaces of the conductive layer 410 to function as part of the capacitor CA. Therefore, the capacitance of the capacitor CA can be increased compared to when the insulating layer 430 and the conductive layer 420 do not cover the side surfaces of the conductive layer 410.

[0338] The insulating layer 430 is preferably formed using the high-k material described in Embodiment 1. This makes it possible to make the insulating layer 430 thick enough to suppress leakage current and to ensure sufficient capacitance of the capacitor CA. Furthermore, since the insulating layer 430 is formed to cover the conductive layer 410, it is preferably formed by a film formation method with good coverage, such as an ALD method or a CVD method.

[0339] The insulating layer 430 may also have a laminated structure. For example, it is preferable to have a laminated structure of a high-k material and a material having a higher dielectric strength than the high-k material. For materials with a high dielectric strength, see embodiment 1. Here, as shown in embodiment 1, a material with a high dielectric strength is also a material with a low relative dielectric constant. The insulating layer 430 may have a laminated structure of, for example, aluminum oxide, which is a high-k material, and silicon oxide on the aluminum oxide, which has a high dielectric strength.

[0340] Alternatively, the insulating layer 430 may be formed by stacking, for example, a zirconium oxide film, an aluminum oxide film, and a zirconium oxide film in this order. Alternatively, the insulating layer 430 may be formed by stacking, for example, a zirconium oxide film, an aluminum oxide film, a zirconium oxide film, and an aluminum oxide film in this order. Alternatively, the insulating layer 430 may be formed by stacking, for example, a hafnium zirconium oxide film, an aluminum oxide film, a hafnium zirconium oxide film, and an aluminum oxide film in this order. By stacking insulating films with a relatively high dielectric strength, such as an aluminum oxide film, the dielectric strength is improved, and electrostatic breakdown of the capacitor element CA can be suppressed.

[0341] Alternatively, the insulating layer 430 may be formed using the material having ferroelectricity described in Embodiment Mode 1.

[0342] An insulating layer 213 is provided under the insulating layer 212 provided under the transistor M1. The insulating layer 213 functions as an interlayer insulating layer. The insulating layer 213 can be made of the same material as the insulating layer 280.

[0343] A conductive layer 412 is provided on the conductive layer 245a, the conductive layer 246a, and the insulating layer 285. The conductive layer 412 can have, for example, a region in contact with the upper end of the conductive layer 245a and a region in contact with the upper surface of the conductive layer 246a. This allows the first plug and the conductive layer 412 to be connected. Since the first plug is connected to the conductive layer 242a, the conductive layer 242a and the conductive layer 412 are connected via the first plug. The conductive layer 412 functions as a wiring.

[0344] A conductive layer 410 is provided on the conductive layer 245b, the conductive layer 246b, and the insulating layer 285. The conductive layer 410 can have, for example, a region in contact with the upper end of the conductive layer 245b and a region in contact with the upper surface of the conductive layer 246b. This allows the second plug and the conductive layer 410 to be connected. Since the second plug is connected to the conductive layer 242b, the conductive layer 242b and the conductive layer 410 are connected via the second plug. Note that the conductive layer 410 has the same material as the conductive layer 412 and can be formed in the same process.

[0345] An insulating layer 487 is provided over the capacitor CA, the conductive layer 412, and the insulating layer 285. The insulating layer 487 is provided to cover the conductive layer 420 and the conductive layer 412. An insulating layer 488 is provided over the insulating layer 487.

[0346] The insulating layer 487 is preferably an insulating film that has a function of capturing or fixing hydrogen. For example, an aluminum oxide film is preferably used for the insulating layer 487. The insulating layer 488 is preferably an insulating film that has a function of suppressing hydrogen diffusion. For example, the insulating layer 488 is preferably a silicon nitride film that has a higher hydrogen barrier property.

[0347] Furthermore, the insulating layer 487 preferably has a stacked structure. For example, when the insulating layer 487 has a two-layer stacked structure, it is preferable to deposit the first layer (lower layer) by the ALD method and the second layer (upper layer) by the sputtering method. For example, the first layer of the insulating layer 487 can be an aluminum oxide film deposited by the thermal ALD method, and the second layer of the insulating layer 487 can be an aluminum oxide film deposited by the sputtering method. By depositing the second layer of the insulating layer 487 by the sputtering method after the first layer of the insulating layer 487 has been deposited, the capacitor element CA and the like can be protected from the impact of ion collisions caused by the sputtering deposition of the second layer of the insulating layer 487. Furthermore, by depositing the first layer of the insulating layer 487 by the ALD method, which has good step coverage, the first layer of the insulating layer 487 can be deposited without forming pinholes or discontinuities, even in steps of the capacitor element CA and the like.

[0348] Furthermore, the insulating layer 488 preferably has a stacked structure. For example, when the insulating layer 488 has a two-layer stacked structure, it is preferable that the first layer (lower layer) be formed by sputtering and the second layer (upper layer) be formed by ALD. For example, the first layer of the insulating layer 488 can be silicon oxide formed by sputtering, and the second layer of the insulating layer 488 can be silicon oxide formed by PEALD. Even if a pinhole or a step is formed in the first layer of the insulating layer 488 near a step of the capacitor element CA or the like, the barrier property against hydrogen can be maintained by covering it with the second layer of the insulating layer 488 formed by ALD, which has good step coverage.

[0349] In this way, by providing the insulating layer 488 on the capacitor CA, it is possible to suppress diffusion of hydrogen from the upper layer of the capacitor CA. Furthermore, by providing the insulating layer 487 below the insulating layer 488, it is possible to capture or fix hydrogen contained in the capacitor CA, the insulating layer 285, and the like in the insulating layer 487.

[0350] An insulating layer 450 is provided over the insulating layer 488. The insulating layer 450 functions as an interlayer insulating layer. The insulating layer 450 can be formed using the same material as the insulating layer 280.

[0351] The insulating layer 487, the insulating layer 488, and the insulating layer 450 have openings that reach the conductive layer 420. The conductive layer 440 is provided to have a region located inside the opening. The conductive layer 440 functions as a plug and is connected to the conductive layer 420. The conductive layer 440 can be in contact with, for example, the top surface of the conductive layer 420. The conductive layer 440 can be formed using the same material as can be used for the conductive layer 246a and the conductive layer 246b.

[0352] 21, the conductive layer 410, the conductive layer 412, the conductive layer 420, and the conductive layer 440 each have a single-layer structure, but are not limited to this structure and may have a stacked structure of two or more layers. For example, a stacked structure of a conductive film having a barrier property and a conductive film having high conductivity may be used. For example, a stacked structure of a titanium nitride film and a tungsten film over the titanium nitride film may be used.

[0353] A conductive layer 462 is provided over the conductive layer 440 and the insulating layer 450. The conductive layer 462 is connected to the conductive layer 440. The conductive layer 462 may have a region in contact with the top surface of the conductive layer 440, for example. The conductive layer 420 and the conductive layer 462 are connected to each other through the conductive layer 440. The conductive layer 462 functions as a wiring. The conductive layer 462 may be formed using, for example, a material that can be used for the conductive layer 260.

[0354] 21 shows the conductive layer 462 as having a single-layer structure, the present invention is not limited to this structure and may have a stacked structure of two or more layers. For example, a highly conductive metal material may be sandwiched between metal materials having high heat resistance. Examples of highly conductive metal materials include aluminum and copper. Examples of highly heat-resistant metal materials include molybdenum, titanium, tungsten, and nitrides of these metal materials.

[0355] For example, the conductive layer 462 can have a five-layer stacked structure. For example, aluminum, which has high conductivity, can be used for the third layer of the conductive layer 462, titanium, which has high heat resistance, can be used for the first layer (bottom layer) and fourth layer, and titanium nitride, which has high heat resistance, can be used for the second layer and fifth layer (top layer). With this structure, even if aluminum, which has low heat resistance, is used, the occurrence of defects such as hillocks, whiskers, and migration can be suppressed. Therefore, the conductive layer 462 can function as a highly conductive wiring.

[0356] An insulating layer 470 is provided over the conductive layer 462 and the insulating layer 450. The insulating layer 470 functions as an interlayer insulating layer. The insulating layer 470 can be formed using the same material as the insulating layer 280.

[0357] 20C shows an example circuit configuration of a gain cell type memory cell having two transistors and one capacitor. The memory cell 953 includes a transistor M2, a transistor M3, and a capacitor CB. In this specification and the like, a memory device having a gain cell type memory cell in which the transistor M2 is an OS transistor is referred to as a nonvolatile oxide semiconductor RAM (NOSRAM).

[0358] One of the source and drain of transistor M2 is connected to one electrode of capacitor CB, the other of the source and drain of transistor M2 is connected to wiring WBL, and the gate of transistor M2 is connected to wiring WOL. The other electrode of capacitor CB is connected to wiring CAL. One of the source and drain of transistor M3 is connected to wiring RBL, the other of the source and drain of transistor M3 is connected to wiring SL, and the gate of transistor M3 is connected to one electrode of capacitor CB.

[0359] The wiring WBL functions as a write bit line, the wiring RBL functions as a read bit line, and the wiring WOL functions as a word line. The wiring CAL functions as a wiring for applying a predetermined potential to the other electrode of the capacitance element CB. When writing data, while retaining data, and when reading data, it is preferable to apply a low-level potential (sometimes referred to as a reference potential) to the wiring CAL.

[0360] Data is written by applying a high-level potential to the wiring WOL, turning on the transistor M2, and establishing electrical continuity between the wiring WBL and one electrode of the capacitor CB. Specifically, when the transistor M2 is on, a potential corresponding to the information to be recorded is applied to the wiring WBL, and the potential is written to one electrode of the capacitor CB and the gate of the transistor M3. Then, a low-level potential is applied to the wiring WOL, turning off the transistor M2, thereby maintaining the potential of one electrode of the capacitor CB and the potential of the gate of the transistor M3.

[0361] Data is read by applying a predetermined potential to the wiring SL. The current flowing between the source and drain of the transistor M3 and the potential of one of the source and drain of the transistor M3 are determined by the potential of the gate of the transistor M3 and the potential of the other of the source and drain of the transistor M3. Therefore, the potential held in one electrode of the capacitor CB (or the gate of the transistor M3) can be read by reading the potential of the wiring RBL connected to one of the source and drain of the transistor M3. In other words, information written in this memory cell can be read from the potential held in one electrode of the capacitor CB (or the gate of the transistor M3).

[0362] Alternatively, for example, the wiring WBL and the wiring RBL may be combined into a single wiring BIL. An example circuit configuration of such a memory cell is shown in FIG. 20D . The memory cell 954 is configured such that the wiring WBL and the wiring RBL of the memory cell 953 are combined into a single wiring BIL, and the other of the source and drain of the transistor M2 and one of the source and drain of the transistor M3 are connected to the wiring BIL. In other words, the memory cell 954 is configured such that the write bit line and the read bit line operate as a single wiring BIL.

[0363] 20E is an example in which the capacitor element CB and the wiring CAL are omitted from the memory cell 953. Also, the memory cell 956 shown in Fig. 20F is an example in which the capacitor element CB and the wiring CAL are omitted from the memory cell 954. With such a configuration, the integration degree of the memory cells can be increased.

[0364] Note that it is preferable to use an OS transistor for at least the transistor M2. In particular, it is preferable to use OS transistors for the transistors M2 and M3. By using an OS transistor as the transistor M2, written data can be held by the transistor M2 for a long time, which reduces the frequency of refreshing the memory cell. Alternatively, the refresh operation of the memory cell can be eliminated. Furthermore, since the leakage current is extremely small, multilevel data or analog data can be held in the memory cells 953 to 956.

[0365] The memory cells 953 to 956 in which an OS transistor is used as the transistor M2 are one embodiment of NOSRAM.

[0366] Note that a Si transistor may be used as the transistor M3. The Si transistor can increase the field effect mobility and can also be used as a p-channel transistor, thereby increasing the degree of freedom in circuit design.

[0367] 20G shows a three-transistor, one-capacitor gain cell type memory cell 957. The memory cell 957 has transistors M4 to M6 and a capacitor CC.

[0368] One of the source and drain of transistor M4 is connected to one electrode of a capacitor CC, the other of the source and drain of transistor M4 is connected to wiring BIL, and the gate of transistor M4 is connected to wiring WOL. The other electrode of capacitor CC is connected to one of the source and drain of transistor M5 and wiring GNDL. The other of the source and drain of transistor M5 is connected to one of the source and drain of transistor M6, and the gate of transistor M5 is connected to one electrode of capacitor CC. The other of the source and drain of transistor M6 is connected to wiring BIL, and the gate of transistor M6 is connected to wiring RWL.

[0369] The wiring BIL functions as a bit line, the wiring WOL functions as a write word line, and the wiring RWL functions as a read word line. The wiring GNDL is a wiring that applies a low-level potential.

[0370] Data is written by applying a high-level potential to the wiring WOL, turning on the transistor M4, and establishing electrical continuity between the wiring BIL and one electrode of the capacitor CC. Specifically, when the transistor M4 is on, a potential corresponding to the information to be recorded is applied to the wiring BIL, and the potential is written to one electrode of the capacitor CC and the gate of the transistor M5. Then, a low-level potential is applied to the wiring WOL, turning off the transistor M4, thereby maintaining the potential of one electrode of the capacitor CC and the potential of the gate of the transistor M5.

[0371] Data is read by precharging the wiring BIL to a predetermined potential, then electrically floating the wiring BIL, and applying a high-level potential to the wiring RWL. Because the wiring RWL is at a high-level potential, the transistor M6 is turned on, and the wiring BIL and the other of the source and drain of the transistor M5 are electrically connected. At this time, the potential of the wiring BIL is applied to the other of the source and drain of the transistor M5. The potential of the wiring BIL changes depending on the potential held in one electrode of the capacitor CC (or the gate of the transistor M5). By reading the potential of the wiring BIL, the potential held in one electrode of the capacitor CC (or the gate of the transistor M5) can be read. In other words, information written in this memory cell can be read from the potential held in one electrode of the capacitor CC (or the gate of the transistor M5).

[0372] Note that at least the transistor M4 is preferably an OS transistor.

[0373] Note that Si transistors may be used as the transistors M5 and M6. As described above, Si transistors may have higher field-effect mobility than OS transistors depending on the crystalline state of silicon used in the semiconductor layer.

[0374] The driver circuit 910 and memory array 920 of the semiconductor device 900 may be provided on the same plane. Alternatively, as shown in FIG. 22A, the driver circuit 910 and memory array 920 may be provided overlapping each other. By providing the driver circuit 910 and memory array 920 overlapping each other, the signal propagation distance can be shortened. Alternatively, as shown in FIG. 22B, the memory array 920 may be provided in multiple layers on the driver circuit 910.

[0375] 23 is a cross-sectional view showing a configuration example of a semiconductor device 900 in which multiple memory arrays 920 are stacked. The semiconductor device 900 shown in FIG. 23 includes a driver circuit 910 that is a layer including a transistor 310 and the like, and memory arrays 920[1] to 920[m] (m is an integer of 2 or more. In the example shown in FIG. 23, m is an integer of 3 or more) on the driver circuit 910. Here, the layer provided in the first layer (bottom) is referred to as memory array 920[1], the layer provided in the second layer is referred to as memory array 920[2], and the layer provided in the mth layer (top) is referred to as memory array 920[m]. In other words, a memory device of one embodiment of the present invention may have a structure in which multiple layers including memory cells are stacked.

[0376] 23 illustrates a transistor 310 included in a driver circuit 910. The transistor 310 is provided over a substrate 311 and includes a conductive layer 316 functioning as a gate, an insulating layer 315 functioning as a gate insulating layer, a semiconductor region 313 including part of the substrate 311, and low-resistance regions 314a and 314b functioning as source and drain regions. An element isolation layer 318 is preferably provided between adjacent transistors 310. The transistor 310 may be either a p-channel transistor or an n-channel transistor. The substrate 311 may be, for example, a single crystal silicon substrate.

[0377] Here, in the transistor 310, a semiconductor region 313 (a part of the substrate 311) in which a channel is formed has a convex shape. A conductive layer 316 is provided to cover the side and top surfaces of the semiconductor region 313 with an insulating layer 315 interposed therebetween. Note that the conductive layer 316 may be made of a material that adjusts the work function. Such a transistor 310 is also called a FIN-type transistor because it utilizes the convex portions of the semiconductor substrate. Note that an insulating layer that is in contact with the top of the convex portions and functions as a mask for forming the convex portions may be provided. Here, the case where the convex portions are formed by processing a part of the semiconductor substrate is shown, but a semiconductor film having a convex shape may also be formed by processing an SOI substrate.

[0378] Note that the transistor 310 illustrated in FIG. 23 is just an example, and the structure is not limited thereto. An appropriate transistor can be used depending on the circuit configuration or driving method.

[0379] Between each structure, a wiring layer provided with an interlayer insulating layer, wiring, plugs, etc. may be provided. Furthermore, multiple wiring layers may be provided depending on the design. Here, for conductive layers that function as plugs or wiring, the same reference numeral may be used to refer to multiple structures. Furthermore, in this specification and the like, the wiring and the plug connecting to the wiring may be integrated. That is, there are cases where a part of the conductive layer functions as the wiring, and cases where a part of the conductive layer functions as the plug.

[0380] For example, an insulating layer 320, an insulating layer 322, an insulating layer 324, and an insulating layer 326 are stacked in this order as an interlayer insulating layer over the transistor 310. A conductive layer 328 and the like are embedded in the insulating layer 320 and the insulating layer 322. A conductive layer 330 and the like are embedded in the insulating layer 324 and the insulating layer 326. The conductive layer 328 and the conductive layer 330 function as plugs or wirings.

[0381] The insulating layer serving as an interlayer insulating layer may also function as a planarizing film that covers the underlying unevenness. For example, the top surface of the insulating layer 322 may be planarized by CMP treatment to enhance flatness.

[0382] Insulators that can be used as the interlayer insulating layer include oxides, nitrides, oxynitrides, nitride oxides, metal oxides, metal oxynitrides, and metal nitride oxides, which have insulating properties.

[0383] For example, by using a material with a low dielectric constant for an insulating layer that functions as an interlayer insulating layer, the parasitic capacitance that occurs between wirings can be reduced. Therefore, it is preferable to select a material depending on the function of the insulating layer.

[0384] An insulating layer 208 is provided over the driver circuit 910. The insulating layer 208 functions as an interlayer insulating layer. The insulating layer 208 can be formed using the same material as the insulating layer 216.

[0385] An opening is provided in the insulating layer 208, and a conductive layer 207 is provided so as to have a region located inside the opening. The conductive layer 207 functions as a plug and is connected to the driver circuit 910. The conductive layer 207 can be made of the same material as can be used for the conductive layer 440 shown in FIG.

[0386] A conductive layer 209 is provided over the conductive layer 207 and the insulating layer 208. The conductive layer 209 functions as a wiring and is connected to the conductive layer 207. For example, the conductive layer 209 can have a region in contact with the top surface of the conductive layer 207. The conductive layer 209 can be formed using the same material as that used for the conductive layer 462 shown in FIG.

[0387] An insulating layer 213 is provided over the conductive layer 209 and the insulating layer 208. Similar to the memory device shown in FIG. 21 , an insulating layer 212 and an insulating layer 214 are provided over the insulating layer 213. Openings reaching the conductive layer 209 are provided in the insulating layers 213, 212, and 214, and a conductive layer 211 is provided so as to have a region located inside the openings. The conductive layer 211 functions as a plug and is connected to the conductive layer 209. The conductive layer 211 can have a region in contact with the top surface of the conductive layer 209, for example. The conductive layer 211 can be formed using a material that can be used for the conductive layer 440 shown in FIG. 21 .

[0388] Each of the memory arrays 920[1] to 920[m] includes a plurality of memory cells 951. Each memory cell 951 includes a conductive layer 231, a conductive layer 232, a conductive layer 233, a conductive layer 234, a conductive layer 235, and a conductive layer 236 as a conductive layer that functions as a plug or a wiring. The conductive layer 245b and the conductive layer 246b included in each memory cell 951 are connected to the conductive layer 211 through the conductive layers 231 to 236. Therefore, the conductive layer 245b and the conductive layer 246b included in each memory cell 951 are connected to the driver circuit 910 through the conductive layer 207, the conductive layer 209, the conductive layer 211, and the conductive layers 231 to 236.

[0389] The conductive layer 231 is provided inside an opening included in the insulating layer 216. The conductive layer 232 is included in the insulating layers 221, 222, 275, 280, 282, 283, and 285, and is provided inside an opening that reaches the conductive layer 231. The conductive layer 233 is provided over the conductive layer 232, the conductive layer 245b, the conductive layer 246b, and the insulating layer 285. The conductive layer 234 is included in the insulating layers 487, 488, and 450, and is provided inside an opening that reaches the conductive layer 233. The conductive layer 235 is provided over the conductive layer 234 and the insulating layer 450. The conductive layer 236 is provided inside an opening that is included in the insulating layer 470 and the insulating layers 212 and 214 over the insulating layer 470 and reaches the conductive layer 235 .

[0390] The conductive layer 231 can be formed using the same material and process as the conductive layer 205. The conductive layer 232 and the conductive layer 236 can be formed using the same material as the conductive layer 211. The conductive layer 233 can be formed using the same material and process as the conductive layer 410. The conductive layer 234 can be formed using the same material and process as the conductive layer 440. The conductive layer 235 can be formed using the same material and process as the conductive layer 462.

[0391] 23 , the conductive layers 231 to 236 are shared by adjacent memory cells 951. In addition, in the adjacent memory cells 951, the configuration on the right side and the configuration on the left side are arranged symmetrically with respect to the conductive layers 232, 234, and 236.

[0392] In the above-described memory array 920, the memory arrays 920[1] to 920[m] can be stacked. The memory arrays 920[1] to 920[m] included in the memory array 920 can be arranged in a vertical direction to the surface of the substrate on which the driver circuit 910 is provided, thereby improving the memory density of the memory cells 951. Furthermore, the memory array 920 can be manufactured by repeatedly using the same manufacturing process in the vertical direction. The semiconductor device 900 can reduce the manufacturing cost of the memory array 920.

[0393] Next, an example of a processing unit that can include a semiconductor device such as the memory device will be described.

[0394] 24 shows a block diagram of the arithmetic device 960. The arithmetic device 960 shown in FIG. 24 can be applied to, for example, a CPU. The arithmetic device 960 can also be applied to processors such as a GPU (Graphics Processing Unit), a TPU (Tensor Processing Unit), and an NPU (Neural Processing Unit) that have a larger number (several tens to several hundreds) of processor cores capable of parallel processing than a CPU.

[0395] The arithmetic device 960 shown in FIG. 24 has an ALU 962 (ALU: Arithmetic logic unit, arithmetic circuit), an ALU controller 962c, an instruction decoder 963, an interrupt controller 964, a timing controller 965, a register 966, a register controller 967, a bus interface 968, a cache 969, and a cache interface 969i on a substrate 961. The substrate 961 may be a semiconductor substrate, an SOI substrate, a glass substrate, or the like. It may also have a rewritable ROM and a ROM interface. The cache 969 and the cache interface 969i may also be provided on separate chips.

[0396] The cache 969 is connected to a main memory provided on a separate chip via a cache interface 969i. The cache interface 969i has a function of supplying part of the data held in the main memory to the cache 969. The cache interface 969i also has a function of outputting part of the data held in the cache 969 to the ALU 962, register 966, etc. via the bus interface 968.

[0397] As will be described later, a memory array 920 can be provided stacked on the arithmetic unit 960. The memory array 920 can be used as a cache. In this case, the cache interface 969i may have a function of supplying data held in the memory array 920 to the cache 969. In this case, it is preferable that a drive circuit 910 be provided as part of the cache interface 969i.

[0398] It is also possible to use only the memory array 920 as a cache without providing the cache 969 .

[0399] The arithmetic device 960 shown in FIG. 24 is merely an example of a simplified configuration, and actual arithmetic devices 960 have a wide variety of configurations depending on their applications. For example, it is preferable to use a configuration including the arithmetic device 960 shown in FIG. 24 as one core, and to include multiple such cores, each of which operates in parallel, in a so-called multi-core configuration. The greater the number of cores, the higher the computational performance. The greater the number of cores, for example, two, preferably four, more preferably eight, even more preferably twelve, and even more preferably sixteen or more. Furthermore, when extremely high computational performance is required, such as for server applications, a multi-core configuration having 16 or more, preferably 32 or more, and even more preferably 64 or more cores is preferable. Furthermore, the number of bits that the arithmetic device 960 can handle in its internal computation circuit, data bus, etc. can be, for example, 8 bits, 16 bits, 32 bits, 64 bits, etc.

[0400] An instruction input to the arithmetic unit 960 via the bus interface 968 is input to the instruction decoder 963, decoded, and then input to the ALU controller 962c, the interrupt controller 964, the register controller 967, and the timing controller 965.

[0401] The ALU controller 962c, interrupt controller 964, register controller 967, and timing controller 965 perform various controls based on the decoded instructions. Specifically, the ALU controller 962c generates signals for controlling the operation of the ALU 962. Furthermore, the interrupt controller 964 determines and processes interrupt requests from external input / output devices, peripheral circuits, etc. based on their priority, mask status, etc. while the arithmetic unit 960 is executing a program. The register controller 967 generates an address for the register 966 and reads and writes data from and to the register 966 depending on the state of the arithmetic unit 960.

[0402] Furthermore, the timing controller 965 generates signals that control the timing of the operations of the ALU 962, the ALU controller 962c, the instruction decoder 963, the interrupt controller 964, and the register controller 967. For example, the timing controller 965 includes an internal clock generation unit that generates an internal clock signal based on a reference clock signal, and supplies the internal clock signal to the various circuits described above.

[0403] 24, the register controller 967 selects the holding operation in the register 966 in accordance with an instruction from the ALU 962. That is, it selects whether the memory cells in the register 966 will hold data using flip-flops or using capacitors. If holding data using flip-flops is selected, a power supply potential is supplied to the memory cells in the register 966. If holding data using capacitors is selected, the data is rewritten to the capacitors, and the supply of power supply potential to the memory cells in the register 966 can be stopped.

[0404] The memory array 920 and the arithmetic unit 960 can be provided overlapping each other. Perspective views of a semiconductor device 970A are shown in Figures 25A and 25B. The semiconductor device 970A has a layer 930 on which memory arrays are provided above the arithmetic unit 960. The layer 930 is provided with memory arrays 920L1, 920L2, and 920L3. The arithmetic unit 960 and each memory array have overlapping regions. To make the configuration of the semiconductor device 970A easier to understand, the arithmetic unit 960 and the layer 930 are shown separately in Figure 25B.

[0405] By stacking the layer 930 having the memory array and the arithmetic unit 960, the connection distance between them can be shortened, thereby increasing the communication speed between them. In addition, the short connection distance reduces power consumption.

[0406] As a method for stacking the layer 930 having a memory array and the arithmetic device 960, a method (also referred to as monolithic stacking) in which the layer 930 having a memory array is stacked directly on the arithmetic device 960 may be used, or a method in which the arithmetic device 960 and the layer 930 are formed on different substrates, and the two substrates are bonded together and connected using a through-via or conductive film bonding technology (Cu-Cu bonding, etc.) may be used. The former method does not require consideration of misalignment during bonding, and therefore can not only reduce the chip size but also reduce manufacturing costs.

[0407] Here, the arithmetic unit 960 does not have a cache 969, and the memory arrays 920L1, 920L2, and 920L3 provided in the layer 930 can each be used as a cache. In this case, for example, the memory array 920L1 can be used as an L1 cache (also referred to as a level 1 cache), the memory array 920L2 can be used as an L2 cache (also referred to as a level 2 cache), and the memory array 920L3 can be used as an L3 cache (also referred to as a level 3 cache). Of the three memory arrays, the memory array 920L3 has the largest capacity and the lowest access frequency. Furthermore, the memory array 920L1 has the smallest capacity and the highest access frequency.

[0408] When the cache 969 provided in the arithmetic unit 960 is used as an L1 cache, each memory array provided in the layer 930 can be used as a lower-level cache or a main memory. The main memory has a larger capacity than the cache and is accessed less frequently.

[0409] 25B, a driving circuit 910L1, a driving circuit 910L2, and a driving circuit 910L3 are provided. The driving circuit 910L1 is connected to the memory array 920L1 via a connection electrode 940L1. Similarly, the driving circuit 910L2 is connected to the memory array 920L2 via a connection electrode 940L2, and the driving circuit 910L3 is connected to the memory array 920L3 via a connection electrode 940L3.

[0410] Although the number of memory arrays functioning as caches is three in this example, the number may be one or two, or four or more.

[0411] When the memory array 920L1 is used as a cache, the driver 910L1 may function as part of the cache interface 969i, or may be configured to be connected to the cache interface 969i. Similarly, the driver circuits 910L2 and 910L3 may also function as part of the cache interface 969i, or may be configured to be connected thereto.

[0412] Whether the memory array 920 is made to function as a cache or as a main memory is determined by a control circuit 912 included in each drive circuit 910. The control circuit 912 can cause some of the memory cells 950 included in the semiconductor device 900 to function as RAM based on a signal supplied from the arithmetic device 960.

[0413] The semiconductor device 900 can cause some of the memory cells 950 to function as a cache and the other memory cells to function as a main memory. That is, the semiconductor device 900 can function as both a cache and a main memory. The semiconductor device 900 according to one embodiment of the present invention can function as, for example, a universal memory.

[0414] Furthermore, a layer 930 having one memory array 920 may be provided over the arithmetic device 960. Figure 26A shows a perspective view of a semiconductor device 970B.

[0415] In the semiconductor device 970B, one memory array 920 can be divided into multiple areas, each of which can be used for a different function. Fig. 26A shows an example in which area L1 is used as an L1 cache, area L2 is used as an L2 cache, and area L3 is used as an L3 cache.

[0416] Furthermore, in the semiconductor device 970B, the capacity of each of the areas L1 to L3 can be changed depending on the situation. For example, if it is desired to increase the capacity of the L1 cache, this can be achieved by increasing the area of ​​the area L1. This configuration can improve the efficiency of calculation processing and increase the processing speed.

[0417] Also, multiple memory arrays may be stacked. Figure 26B shows a perspective view of a semiconductor device 970C.

[0418] The semiconductor device 970C includes a layer 930L1 having a memory array 920L1, a layer 930L2 having a memory array 920L2 on top of that, and a layer 930L3 having a memory array 920L3 on top of that. The memory array 920L1, which is physically closest to the arithmetic unit 960, can be used as a higher-level cache, and the memory array 920L3, which is farthest, can be used as a lower-level cache or main memory. This configuration allows the capacity of each memory array to be increased, thereby further improving processing power.

[0419] This embodiment mode can be combined with other embodiment modes as appropriate. In addition, in this specification, when a plurality of configuration examples are shown in one embodiment mode, the configuration examples can be combined as appropriate.

[0420] 27 , a memory device according to one embodiment of the present invention includes a transistor including an oxide as a semiconductor (hereinafter also referred to as an OS transistor) and a capacitor. Since the off-state current of an OS transistor is extremely small, the memory device including the OS transistor has excellent storage characteristics and can function as a nonvolatile memory.

[0421] In semiconductor devices such as computers, various memory devices are used depending on the application. Figure 27 shows a conceptual diagram explaining the hierarchy of memory devices used in semiconductor devices. In Figure 27, the conceptual diagram explaining the hierarchy of memory devices is shown as a triangle, with memory devices located higher in the triangle being required to have a faster operating speed, and memory devices located lower in the triangle being required to have a larger memory capacity and a higher recording density.

[0422] In FIG. 27 , from the top layer of the triangle, memories integrated as registers in the CPU, GPU, and NPU arithmetic processing units, cache memories (sometimes simply referred to as caches, and typically L1, L2, and L3 caches), main memories such as DRAM, and storage memories such as 3D NAND and hard disks (also called HDDs: hard disk drives) are shown.

[0423] The memory embedded as a register in a processing unit such as a CPU, GPU, or NPU is used for temporary storage of calculation results, and is therefore frequently accessed by the processing unit. Therefore, a high operating speed is required rather than a large storage capacity. Registers also have the function of storing setting information for the processing unit.

[0424] Cache memory has the function of duplicating and storing a portion of the data stored in DRAM. By duplicating frequently used data and storing it in cache memory, the speed of accessing the data can be increased. The storage capacity required for cache memory is smaller than that of DRAM, but it is required to have a faster operating speed than DRAM. In addition, data rewritten in cache memory is duplicated and supplied to DRAM.

[0425] The memory device of one embodiment of the present invention can be used as a DRAM.

[0426] 27 illustrates only up to the L3 cache, but the cache memory is not limited to this. For example, the storage device of one embodiment of the present invention can be used as a last level cache (LLC) or a final level cache (FLC), which are located at the lowest level of the cache.

[0427] The DRAM has a function of holding programs, data, etc. read from the 3D NAND.

[0428] 3D NAND has the function of storing data that requires long-term storage, various programs used in computing devices (e.g., artificial neural network models), etc. Therefore, 3D NAND requires large storage capacity and high recording density rather than fast operating speed.

[0429] Hard disks have large capacity and are non-volatile. Instead of hard disks, solid state drives (SSDs) and the like can be used.

[0430] The memory device of one embodiment of the present invention can be monolithically structured with peripheral circuits by using OS transistors. Furthermore, the use of OS transistors allows monolithic stacking with peripheral circuits. Therefore, this has advantages in terms of data access with peripheral circuits. Furthermore, the degree of integration can be increased by stacking with peripheral circuits. Furthermore, the use of OS transistors enables the memory device of one embodiment of the present invention to retain data for a long period of time. Therefore, when used as a DRAM, the frequency of refresh can be reduced.

[0431] Furthermore, the storage device of one embodiment of the present invention can reduce leakage current by using an OS transistor. Therefore, for example, data can be sufficiently stored even if the capacitance value of a capacitor is small. Therefore, for example, by using the storage device of one embodiment of the present invention as a DRAM, the operation speed of the DRAM, for example, the speed of rewriting, can be increased in some cases.

[0432] Furthermore, since the memory device of one embodiment of the present invention includes a capacitor including a ferroelectric material, data can be retained for a long time. Therefore, when the memory device is used as a DRAM, the frequency of refresh can be reduced. Furthermore, the reliability of the memory device can be improved.

[0433] The storage device of one embodiment of the present invention can be used for the Target2 region and the Target1 region shown in Figure 27. In particular, the storage device can be suitably used for the Target1 region.

[0434] 27, Target1 includes a boundary area (Target1_1) between the DRAM and 3D NAND, and a boundary area (Target1_2) between the DRAM and cache (L1, L2, L3). Examples of Target1_2 include the LLC and FLC described above.

[0435] By replacing the storage device of one embodiment of the present invention with a DRAM, power consumption can be reduced. With this configuration, power consumption can be reduced to half or less, preferably one-tenth or less, more preferably one-hundredth, and even more preferably one-thousandth or less, compared to a configuration using a DRAM. Therefore, the storage device of one embodiment of the present invention can be suitably used for Target 1.

[0436] Furthermore, the storage device of one embodiment of the present invention can retain data for a long time and has advantages in terms of data access. Therefore, the storage device of one embodiment of the present invention can be suitably used for Target1_1, which is a region of Target1 that is rewritten relatively infrequently. By applying the storage device of one embodiment of the present invention to Target1_1, the reliability of the storage device can be improved. Furthermore, the integration degree of the storage device can be increased. Furthermore, the power consumption of the storage device can be reduced.

[0437] Furthermore, the storage device of one embodiment of the present invention has high operating speed and is advantageous in terms of data access, and therefore can be suitably used for Target1_2, which is rewritten more frequently than Target1. By applying the storage device of one embodiment of the present invention to Target1_2, the calculation efficiency of the storage device can be improved and power consumption can be reduced.

[0438] Another means for reducing power consumption is a configuration in which a storage device such as a DRAM or an FeRAM (including the semiconductor device of one embodiment of the present invention) is stacked on an arithmetic processing device such as a CPU, a GPU, or an NPU. A configuration in which an arithmetic processing device and a storage device are stacked is called a monolithic stack. By configuring the arithmetic processing device and the storage device as a monolithic stack, for example, the power consumption required for data access between the arithmetic processing device and the storage device can be significantly reduced. Therefore, by deploying information processing devices including supercomputers (also called high performance computers (HPCs)), computers, servers, etc. to which such a configuration is applied throughout the world, global warming can be suppressed.

[0439] As described above, the memory device including an oxide semiconductor according to one embodiment of the present invention can be applied to a wide range of memories, from memories integrated as registers in arithmetic processing units such as CPUs, GPUs, and NPUs to memories located in the boundary region between DRAMs and 3D NANDs.

[0440] This embodiment mode can be combined with other embodiment modes as appropriate. In addition, in this specification, when a plurality of configuration examples are shown in one embodiment mode, the configuration examples can be combined as appropriate.

[0441] Embodiment 5 In this embodiment, application examples of a semiconductor device of one embodiment of the present invention will be described with reference to FIGS. 28A to 29E.

[0442] The semiconductor device of one embodiment of the present invention can be used in, for example, electronic components, mainframes, space equipment, data centers (also referred to as DCs), and various electronic devices. By using the semiconductor device of one embodiment of the present invention, low power consumption and high performance can be achieved for the electronic components, mainframes, space equipment, data centers, and various electronic devices.

[0443] Examples of electronic devices include electronic devices with relatively large screens such as television sets, desktop or notebook computers, computer monitors, digital signage, large game machines such as pachinko machines, as well as digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, personal digital assistants, and sound playback devices.

[0444] The electronic device of this embodiment may have a sensor (including the function of detecting, detecting, or measuring force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared rays).

[0445] The electronic device of the present embodiment can have various functions, such as a function to display various information (still images, videos, text images, etc.) on a display unit, a touch panel function, a function to display a calendar, date, time, etc., a function to execute various software (programs), a wireless communication function, and a function to read out programs or data recorded on a recording medium.

[0446] [Electronic Component] FIG. 28A shows a perspective view of a substrate (mounting substrate 989) on which an electronic component 980 is mounted. The electronic component 980 shown in FIG. 28A has a semiconductor device 981 inside a mold 984. FIG. 28A omits some parts in order to show the interior of the electronic component 980. The electronic component 980 has lands 985 on the outside of the mold 984. The lands 985 are connected to electrode pads 986, and the electrode pads 986 are connected to the semiconductor device 981 via wires 987. The electronic component 980 is mounted on, for example, a printed circuit board 988. A plurality of such electronic components are combined and connected on the printed circuit board 988 to complete the mounting substrate 989.

[0447] The semiconductor device 981 also includes a drive circuit layer 982 and a memory layer 983. The memory layer 983 has a configuration in which multiple memory cell arrays are stacked. The stacked configuration of the drive circuit layer 982 and the memory layer 983 can be a monolithic stacked configuration. In a monolithic stacked configuration, the layers can be connected without using through-electrode technology such as TSV (Through Silicon Via) or bonding technology such as Cu-Cu direct bonding. By monolithically stacking the drive circuit layer 982 and the memory layer 983, for example, a so-called on-chip memory configuration can be achieved in which the memory is formed directly on the processor. The on-chip memory configuration enables the operation of the interface between the processor and the memory to be faster.

[0448] Furthermore, by configuring an on-chip memory, the size of the connection wiring can be reduced compared to technologies that use through electrodes such as TSVs, and the number of connection pins can be increased. Increasing the number of connection pins enables parallel operation, which makes it possible to improve the memory bandwidth (also called memory bandwidth).

[0449] Furthermore, it is preferable that the memory cell arrays included in the memory layer 983 are formed using OS transistors and the memory cell arrays are monolithically stacked. By forming the memory cell arrays in a monolithic stacked configuration, it is possible to improve one or both of the memory bandwidth and the memory access latency. Note that the bandwidth refers to the amount of data transferred per unit time, and the access latency refers to the time from access to the start of data exchange. Note that when Si transistors are used for the memory layer 983, it is more difficult to form a monolithic stacked configuration than OS transistors. Therefore, it can be said that OS transistors have a superior structure to Si transistors in a monolithic stacked configuration.

[0450] The semiconductor device 981 may also be referred to as a die. In this specification, a die refers to a chip piece obtained during the semiconductor chip manufacturing process by forming a circuit pattern on, for example, a disk-shaped substrate (also called a wafer) and dicing it into cubes. Semiconductor materials that can be used for the die include, for example, silicon (Si), silicon carbide (SiC), or gallium nitride (GaN). For example, a die obtained from a silicon substrate (also called a silicon wafer) may be called a silicon die.

[0451] 28B shows a perspective view of an electronic component 990. The electronic component 990 is an example of a SiP (System in Package) or an MCM (Multi-Chip Module). The electronic component 990 has an interposer 991 provided on a package substrate 992 (printed circuit board), and a semiconductor device 994 and a plurality of semiconductor devices 981 provided on the interposer 991.

[0452] The electronic component 990 shows an example in which the semiconductor device 981 is used as a high bandwidth memory (HBM). The semiconductor device 994 can be used in an integrated circuit such as a CPU, a GPU, or an FPGA (Field Programmable Gate Array).

[0453] For example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate can be used as the package substrate 992. For example, a silicon interposer or a resin interposer can be used as the interposer 991.

[0454] The interposer 991 has multiple wirings and functions to connect multiple integrated circuits with different terminal pitches. The multiple wirings are provided in a single layer or multiple layers. The interposer 991 also functions to connect the integrated circuits provided on the interposer 991 to electrodes provided on the package substrate 992. For these reasons, the interposer is sometimes called a "rewiring substrate" or "intermediate substrate." In some cases, through electrodes are provided in the interposer 991, and the integrated circuits and the package substrate 992 are connected using the through electrodes. In addition, in a silicon interposer, TSVs can also be used as through electrodes.

[0455] In an HBM, many wirings must be connected to achieve a wide memory bandwidth. Therefore, the interposer on which the HBM is mounted must have fine and high-density wiring. Therefore, it is preferable to use a silicon interposer for the interposer on which the HBM is mounted.

[0456] Furthermore, in SiPs, MCMs, and the like that use silicon interposers, a decrease in reliability due to differences in the coefficient of expansion between the integrated circuit and the interposer is unlikely to occur. Furthermore, because the silicon interposer has a highly flat surface, poor connection between the integrated circuit mounted on the silicon interposer and the silicon interposer is unlikely to occur. In particular, it is preferable to use silicon interposers in 2.5D packages (2.5-dimensional packaging) in which multiple integrated circuits are arranged horizontally on an interposer.

[0457] On the other hand, when connecting multiple integrated circuits with different terminal pitches using a silicon interposer, TSVs, or the like, a space is required to accommodate the width of the terminal pitch. Therefore, when attempting to reduce the size of the electronic component 990, the width of the terminal pitch becomes an issue, and it may be difficult to provide the many wirings required to achieve a wide memory bandwidth. Therefore, as described above, a monolithic stacked structure using OS transistors is preferable. A composite structure may be formed by combining a memory cell array stacked using TSVs with a monolithic stacked memory cell array.

[0458] A heat sink (heat dissipation plate) may be provided over the electronic component 990. When a heat sink is provided, it is preferable to align the height of an integrated circuit provided on the interposer 991. For example, in the electronic component 990 shown in this embodiment, it is preferable to align the height of the semiconductor device 981 and the height of the semiconductor device 994.

[0459] Electrodes 993 may be provided on the bottom of the package substrate 992 in order to mount the electronic component 990 on another substrate. FIG. 28B shows an example in which the electrodes 993 are formed of solder balls. By providing solder balls in a matrix on the bottom of the package substrate 992, BGA (Ball Grid Array) mounting can be achieved. The electrodes 993 may also be formed of conductive pins. By providing conductive pins in a matrix on the bottom of the package substrate 992, PGA (Pin Grid Array) mounting can be achieved.

[0460] The electronic component 990 can be mounted on other substrates using various mounting methods, not limited to BGA and PGA, such as a staggered pin grid array (SPGA), a land grid array (LGA), a quad flat package (QFP), a quad flat J-leaded package (QFJ), and a quad flat non-leaded package (QFN).

[0461] 29A shows a perspective view of a mainframe computer 5600. The mainframe computer 5600 shown in Fig. 29A has a rack 5610 housing a plurality of rack-mounted computers 5620. The mainframe computer 5600 may also be called a supercomputer.

[0462] The computer 5620 can have the configuration shown in the perspective view of Fig. 29B, for example. In Fig. 29B, the computer 5620 has a motherboard 5630, which has a plurality of slots 5631 and a plurality of connection terminals. A PC card 5621 is inserted into the slot 5631. In addition, the PC card 5621 has connection terminals 5623, 5624, and 5625, which are each connected to the motherboard 5630.

[0463] PC card 5621 shown in Figure 29C is an example of a processing board equipped with a CPU, a GPU, a storage device, etc. PC card 5621 has board 5622. Board 5622 also has connection terminals 5623, 5624, 5625, semiconductor devices 5626, 5627, 5628, and 5629. Note that Figure 29C illustrates semiconductor devices other than semiconductor devices 5626, 5627, and 5628, but for these semiconductor devices, the following descriptions of semiconductor devices 5626, 5627, and 5628 can be referenced.

[0464] The connection terminal 5629 has a shape that allows it to be inserted into a slot 5631 of the motherboard 5630, and the connection terminal 5629 functions as an interface for connecting the PC card 5621 and the motherboard 5630. An example of the standard for the connection terminal 5629 is PCIe.

[0465] The connection terminals 5623, 5624, and 5625 can be, for example, interfaces for supplying power to the PC card 5621, inputting signals, etc. Furthermore, they can be, for example, interfaces for outputting signals calculated by the PC card 5621. Examples of the standards for the connection terminals 5623, 5624, and 5625 include USB (Universal Serial Bus), SATA (Serial ATA), and SCSI (Small Computer System Interface). Furthermore, when a video signal is output from the connection terminals 5623, 5624, and 5625, examples of the standards for each include HDMI (registered trademark).

[0466] The semiconductor device 5626 has a terminal (not shown) for inputting and outputting signals, and the semiconductor device 5626 can be connected to the board 5622 by inserting the terminal into a socket (not shown) provided on the board 5622.

[0467] The semiconductor device 5627 has a plurality of terminals, and the semiconductor device 5627 can be connected to the board 5622 by, for example, reflow soldering the terminals to wiring provided on the board 5622. Examples of the semiconductor device 5627 include an FPGA, a GPU, and a CPU. For example, the electronic component 990 can be used as the semiconductor device 5627.

[0468] The semiconductor device 5628 has a plurality of terminals, and the semiconductor device 5628 can be connected to the board 5622 by, for example, reflow soldering the terminals to wiring provided on the board 5622. Examples of the semiconductor device 5628 include a memory device. For example, the electronic component 990 can be used as the semiconductor device 5628.

[0469] The mainframe computer 5600 can also function as a parallel computer. By using the mainframe computer 5600 as a parallel computer, it is possible to perform large-scale calculations required for, for example, learning and inference in artificial intelligence.

[0470] [Space Equipment] The semiconductor device of one embodiment of the present invention can be suitably used in space equipment.

[0471] A semiconductor device according to one embodiment of the present invention includes an OS transistor. Compared to a Si transistor, an OS transistor exhibits smaller variations in electrical characteristics due to radiation exposure. That is, the OS transistor has high radiation resistance and is therefore highly reliable and suitable for use in environments where radiation may be incident. For example, an OS transistor can be suitably used in outer space. Specifically, an OS transistor can be used as a transistor for a semiconductor device provided in a space shuttle, an artificial satellite, or a space probe. Examples of radiation include X-rays and neutrons. Note that outer space refers to an altitude of 100 km or higher, and the outer space described in this specification can include one or more of the thermosphere, the mesosphere, and the stratosphere.

[0472] Fig. 29D shows an artificial satellite 6800 as an example of space equipment. The artificial satellite 6800 has a body 6801, a solar panel 6802, an antenna 6803, a secondary battery 6805, and a control device 6807. Note that Fig. 29D illustrates a planet 6804 in space.

[0473] 29D , a battery management system (also referred to as a BMS) or a battery control circuit may be provided for the secondary battery 6805. The use of an OS transistor in the battery management system or the battery control circuit is preferable because it has low power consumption and high reliability even in space.

[0474] Furthermore, outer space is an environment with radiation levels 100 times higher than on Earth. Examples of radiation include electromagnetic waves (electromagnetic radiation) such as X-rays and gamma rays, and particle radiation such as alpha rays, beta rays, neutron rays, proton rays, heavy ion rays, and meson rays.

[0475] When sunlight is irradiated onto the solar panel 6802, the power required for the operation of the satellite 6800 is generated. However, for example, in a situation where sunlight is not irradiated onto the solar panel or where the amount of sunlight irradiating the solar panel is small, the generated power is small. Therefore, there is a possibility that the power required for the operation of the satellite 6800 will not be generated. In order to operate the satellite 6800 even in a situation where the generated power is small, it is preferable to provide a secondary battery 6805 in the satellite 6800. Note that the solar panel may be called a solar cell module.

[0476] The satellite 6800 can generate a signal. The signal is transmitted via an antenna 6803, and can be received by, for example, a receiver on the ground or another satellite. By receiving the signal transmitted by the satellite 6800, the position of the receiver that received the signal can be determined. As described above, the satellite 6800 can constitute a satellite positioning system.

[0477] The control device 6807 has a function of controlling the artificial satellite 6800. The control device 6807 is configured using, for example, one or more selected from a CPU, a GPU, and a storage device. Note that the control device 6807 is preferably a semiconductor device including an OS transistor which is one embodiment of the present invention.

[0478] The artificial satellite 6800 can also be configured to include a sensor. For example, by including a visible light sensor, the artificial satellite 6800 can have the function of detecting sunlight reflected from an object on the ground. Or, by including a thermal infrared sensor, the artificial satellite 6800 can have the function of detecting thermal infrared rays emitted from the earth's surface. As described above, the artificial satellite 6800 can function as, for example, an earth observation satellite.

[0479] Although an artificial satellite is described as an example of space equipment in this embodiment, the present invention is not limited thereto. For example, the semiconductor device of one embodiment of the present invention can be suitably used in space equipment such as a spaceship, a space capsule, or a space probe.

[0480] As described above, OS transistors have excellent advantages over Si transistors, such as the ability to achieve a wide memory bandwidth and high radiation resistance.

[0481] [Data Center] The semiconductor device of one embodiment of the present invention can be suitably used in a storage system applied to, for example, a data center. The data center is required to perform long-term management of data, such as ensuring data immutability. Managing long-term data requires the construction of a large-scale building, such as installing storage and servers for storing a huge amount of data, ensuring a stable power supply for data retention, or ensuring cooling equipment required for data retention.

[0482] By using the semiconductor device of one embodiment of the present invention in a storage system applied to a data center, it is possible to reduce the power required to store data and the size of the semiconductor device that stores data. Therefore, it is possible to reduce the size of the storage system, the size of the power supply for storing data, the scale of cooling equipment, etc. Therefore, it is possible to reduce the space required for the data center.

[0483] Furthermore, the semiconductor device of one embodiment of the present invention has low power consumption, which allows heat generation from the circuit to be reduced. Therefore, adverse effects of the heat generation on the circuit itself, peripheral circuits, and modules can be reduced. Furthermore, by using the semiconductor device of one embodiment of the present invention, a data center that operates stably even in a high-temperature environment can be realized. Therefore, the reliability of the data center can be improved.

[0484] Fig. 29E shows a storage system applicable to a data center. The storage system 7010 shown in Fig. 29E has a plurality of servers 7001sb as hosts 7001. It also has a plurality of storage devices 7003md as storage 7003. The host 7001 and storage 7003 are connected via a storage area network 7004 and a storage control circuit 7002.

[0485] The host 7001 corresponds to a computer that accesses data stored in the storage 7003. The hosts 7001 may be connected to each other via a network.

[0486] Although the storage 7003 uses flash memory to reduce the data access speed, i.e., the time required to store and output data, this time is significantly longer than the time required for DRAM, which can be used as cache memory within the storage. In order to solve the problem of the long access speed of the storage 7003, a storage system typically provides cache memory within the storage to reduce the time required to store and output data.

[0487] The cache memory described above is used in the storage control circuit 7002 and the storage 7003. Data exchanged between the host 7001 and the storage 7003 is stored in the cache memory in the storage control circuit 7002 and the storage 7003, and then output to the host 7001 or the storage 7003.

[0488] By using OS transistors as transistors for storing data in the cache memory and holding a potential corresponding to the data, the frequency of refresh operations can be reduced, and power consumption can be reduced.

[0489] Note that power consumption can be reduced by applying the semiconductor device of one embodiment of the present invention to any one or more selected from electronic components, mainframe computers, space equipment, data centers, and electronic devices. Therefore, while energy demand is expected to increase with the improvement in performance or high integration of semiconductor devices, the use of the semiconductor device of one embodiment of the present invention can reduce carbon dioxide (CO ２ Furthermore, the semiconductor device of one embodiment of the present invention is effective as a countermeasure against global warming because it consumes low power.

[0490] This embodiment mode can be combined with other embodiment modes as appropriate. In addition, in this specification, when a plurality of configuration examples are shown in one embodiment mode, the configuration examples can be combined as appropriate.

[0491] 200: transistor, 205: conductive layer, 207: conductive layer, 208: insulating layer, 209: conductive layer, 211: conductive layer, 212: insulating layer, 213: insulating layer, 214: insulating layer, 216: insulating layer, 221: insulating layer, 222: insulating layer, 224: insulating layer, 224f: insulating film, 230: semiconductor layer, 230f: semiconductor film, 230i: channel formation region, 230na: low resistance region, 230nb: low resistance region, 231: conductive layer, 232: conductive layer, 233: conductive layer, 234: conductive layer, 235: conductive layer, 236: conductive layer, 241a: insulating layer, 241b: insulating layer, 242: conductive layer, 2 42a: conductive layer, 242b: conductive layer, 242f: conductive film, 243a: opening, 243b: opening, 244a: recess, 244b: recess, 245a: conductive layer, 245b: conductive layer, 245f: conductive film, 246a: conductive layer, 246b: conductive layer, 246f: conductive film, 250: insulating layer, 250f: insulating film, 255: insulating layer, 260: conductive layer, 260f: conductive film, 275: insulating layer, 280: insulating layer, 282: insulating layer, 283: insulating layer, 285: insulating layer, 287: recess, 289: opening, 290: opening, 310: transistor, 311: substrate, 313: semiconductor region, 31 4a: low resistance region, 314b: low resistance region, 315: insulating layer, 316: conductive layer, 318: element isolation layer, 320: insulating layer, 322: insulating layer, 324: insulating layer, 326: insulating layer, 328: conductive layer, 330: conductive layer, 410: conductive layer, 412: conductive layer, 420: conductive layer, 430: insulating layer, 440: conductive layer, 450: insulating layer, 462: conductive layer, 470: insulating layer, 487: insulating layer, 488: insulating layer, 900: semiconductor device, 910: driver circuit, 911: peripheral circuit, 912: control circuit, 915: peripheral circuit, 920[1]: memory array, 920[2]: memory array Ray, 920[m]: memory array, 920: memory array, 923: row driver, 924: column driver, 925: input circuit, 926: output circuit, 927: sense amplifier, 928: voltage generation circuit, 930: layer, 931: PSW, 932: PSW, 941: row decoder, 942: column decoder, 950: memory cell, 951: memory cell, 952: memory cell, 953: memory cell, 954: memory cell, 955: memory cell, 956: memory cell, 957: memory cell, 960: arithmetic unit, 961: substrate, 962: ALU, 962c: ALU controller,963: instruction decoder, 964: interrupt controller, 965: timing controller, 966: register, 967: register controller, 968: bus interface, 969: cache, 969i: cache interface, 970A: semiconductor device, 970B: semiconductor device, 970C: semiconductor device, 980: electronic component, 981: semiconductor device, 982: drive circuit layer, 983: memory layer, 984: mold, 985: land, 986: electrode pad, 987: wire, 988: printed circuit board, 989: mounting board, 990: electronic component, 991: interposer, 992: package board, 993: electrode, 994: semiconductor device, 5600: large type computer, 5610: rack, 5620: computer, 5621: PC card, 5622: board, 5623: connection terminal, 5624: connection terminal, 5625: connection terminal, 5626: semiconductor device, 5627: semiconductor device, 5628: semiconductor device, 5629: connection terminal, 5630: motherboard, 5631: slot, 6800: artificial satellite, 6801: aircraft, 6802: solar panel, 6803: antenna, 6804: planet, 6805: secondary battery, 6807: control device, 7001: host, 7001sb: server, 7002: storage control circuit, 7003: storage, 7003md: storage device, 7004: storage area network, 7010: storage system,

Claims

a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, a fifth conductive layer, a first insulating layer, and a second insulating layer; the first conductive layer and the second conductive layer are spaced apart from each other so as to have a region in contact with an upper surface of the semiconductor layer; the first insulating layer has a region in contact with an upper surface of the first conductive layer and a region in contact with an upper surface of the second conductive layer; the first insulating layer has a first opening in a region between the first conductive layer and the second conductive layer in a plan view; the first conductive layer and the first insulating layer have a second opening having a region overlapping with the semiconductor layer; the second conductive layer and the first insulating layer have a third opening having a region overlapping with the semiconductor layer; the semiconductor layer has a first recess overlapping the first opening, the second insulating layer is provided inside the first opening so as to have a region in contact with an upper surface of the semiconductor layer in the first recess; the third conductive layer is provided on the second insulating layer so as to have a region located inside the first opening; the fourth conductive layer is provided inside the second opening so as to have a region in contact with the semiconductor layer; the fifth conductive layer is provided inside the third opening so as to have a region in contact with the semiconductor layer; a thickness of the first conductive layer is thinner than a thickness of the semiconductor layer in a region where the semiconductor layer overlaps the first conductive layer; a thickness of the second conductive layer is thinner than a thickness of the semiconductor layer in a region where the semiconductor layer overlaps with the second conductive layer; the semiconductor layer comprises indium oxide; the first conductive layer and the second conductive layer each contain an oxide containing indium and a first metal element; The fourth conductive layer and the fifth conductive layer contain a second metal element. 　 In claim 1, A semiconductor device, wherein the electrical resistivity in a first region of the semiconductor layer that contacts the fourth conductive layer and in a second region of the semiconductor layer that contacts the fifth conductive layer is lower than the electrical resistivity in a third region of the semiconductor layer that overlaps with the third conductive layer. 　 In claim 1 or claim 2, The semiconductor device, wherein the second metal element is titanium, tin, or zirconium. 　 In claim 1 or claim 2, The semiconductor device wherein the first metal element is tin. 　 In claim 1 or claim 2, a sixth conductive layer and a seventh conductive layer; the sixth conductive layer is provided on the fourth conductive layer so as to fill the second opening; the seventh conductive layer is provided on the fifth conductive layer so as to fill the third opening; the sixth conductive layer has a higher electrical conductivity than the fourth conductive layer; A semiconductor device in which the seventh conductive layer has a higher electrical conductivity than the fifth conductive layer. 　 In claim 3, a sixth conductive layer and a seventh conductive layer; the sixth conductive layer is provided on the fourth conductive layer so as to fill the second opening; the seventh conductive layer is provided on the fifth conductive layer so as to fill the third opening; The sixth conductive layer and the seventh conductive layer each include tungsten, copper, aluminum, or molybdenum. 　 In claim 1 or claim 2, a thickness of the first conductive layer is ⅕ or less of a thickness of the semiconductor layer in a region where the semiconductor layer overlaps the first conductive layer; A semiconductor device in which the thickness of the second conductive layer is 1 / 5 or less of the thickness of the semiconductor layer in a region where the second conductive layer overlaps the semiconductor layer. 　 In claim 1 or claim 2, the semiconductor layer has a second recess overlapping the second opening and a third recess overlapping the third opening; the fourth conductive layer has a region in contact with an upper surface of the semiconductor layer in the second recess and a region in contact with a side surface of the semiconductor layer in the second recess, The fifth conductive layer has a region in contact with an upper surface of the semiconductor layer in the third recess, and a region in contact with a side surface of the semiconductor layer in the third recess. 　 a first step of forming a semiconductor layer, a first conductive layer having a region in contact with an upper surface of the semiconductor layer, and a first insulating layer having a region in contact with an upper surface of the first conductive layer; a second step of processing the first insulating layer and the first conductive layer to form a first opening in the first insulating layer, the first opening having a region overlapping with the semiconductor layer, and forming a second conductive layer and a third conductive layer facing each other across the first opening; a third step of forming a second insulating layer and a fourth conductive layer on the second insulating layer, the fourth conductive layer having an area located within the first opening; a fourth step of processing the first insulating layer, the second conductive layer, and the third conductive layer to form second openings in the first insulating layer and the second conductive layer that reach the semiconductor layer, and to form third openings in the first insulating layer and the third conductive layer that reach the semiconductor layer; a fifth step of forming a fifth conductive layer having a region located inside the second opening and a sixth conductive layer having a region located inside the third opening, so as to have regions in contact with the semiconductor layer; a sixth step of performing a heat treatment; In the first step, the semiconductor layer is formed to have indium oxide; In the first step, the first conductive layer is formed to have an oxide containing indium and a first metal element and to have a thickness smaller than that of the semiconductor layer; In the fifth step, the fifth conductive layer and the sixth conductive layer are formed to contain a second metal element; In the sixth step, a first region containing the second metal element and a second region are formed in the semiconductor layer by the heat treatment; the first region is formed to have a region overlapping with the fifth conductive layer; A method for manufacturing a semiconductor device, wherein the second region is formed to have a region overlapping with the sixth conductive layer. 　 In claim 9, The method for manufacturing a semiconductor device, wherein the second metal element is titanium, tin, or zirconium. 　 In claim 9, The method for manufacturing a semiconductor device, wherein the first metal element is tin. 　 In claim 9, performing a seventh step after the fifth step and before the sixth step of forming a seventh conductive layer on the fifth conductive layer and an eighth conductive layer on the sixth conductive layer; In the seventh step, the seventh conductive layer is formed so as to fill the second opening; the seventh conductive layer has a higher electrical conductivity than the fifth conductive layer; In the seventh step, the eighth conductive layer is formed so as to fill the third opening; A method for manufacturing a semiconductor device, wherein the eighth conductive layer has a higher electrical conductivity than the sixth conductive layer. 　 In claim 10, performing a seventh step after the fifth step and before the sixth step of forming a seventh conductive layer on the fifth conductive layer and an eighth conductive layer on the sixth conductive layer; In the seventh step, the seventh conductive layer is formed so as to fill the second opening; In the seventh step, the eighth conductive layer is formed so as to fill the third opening; In the seventh step, the seventh conductive layer and the eighth conductive layer are formed to contain tungsten, copper, aluminum, or molybdenum. 　 In any one of claims 9 to 13, In the first step, the first conductive layer is formed to have a thickness equal to or smaller than 1 / 5 of the thickness of the semiconductor layer.

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