Transistor

Abstract

Provided is a highly reliable semiconductor device. This transistor has a first conductive layer, a second conductive layer, a first insulating layer, a first semiconductor layer, a second insulating layer, and a third conductive layer. The semiconductor layer has a crystalline oxide semiconductor layer that contains indium and oxygen. The oxide semiconductor layer has properties for transmitting oxygen at 2 × 1020 atoms / cm3 to 1 × 1021 atoms / cm3 in a heat treatment in which the heating temperature is 400°C and the treatment time is 8 hours. The oxide semiconductor layer also has properties such that a deuterium diffusion amount integral value thereof is 5 × 1012 atoms / cm2 to 1 × 1014 atoms / cm2 in a heat treatment in which the heating temperature is 200°C and the treatment time is 8 hours.

Description

transistor

[0001] 1. Field of the Invention One embodiment of the present invention relates to a transistor, a semiconductor device, and a method for manufacturing a semiconductor device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. Examples of the technical field of one embodiment of the present invention include large-scale integration (LSI) chips, central processing units (CPUs), graphics processing units (GPUs), memories (storage devices), input devices, input / output devices, sensors, imaging devices, display devices, light-emitting devices, power storage devices, electronic devices, and driving methods or manufacturing methods thereof. Note that in this specification and the like, a semiconductor device refers to a device that utilizes semiconductor characteristics, and includes a circuit including a transistor, a device having such a circuit, and the like. Furthermore, a semiconductor device generally refers to a device that can function by utilizing semiconductor characteristics.

[0003] Note that one aspect of the present invention is not limited to the above technical fields. One aspect of the invention disclosed in this specification relates to an object or a method. Alternatively, it relates to a method (process), a machine, a manufacture, or a composition of matter.

[0004] A technology for constructing transistors using semiconductor thin films formed on insulating surfaces has attracted attention. Such transistors are widely used in electronic devices such as integrated circuits (ICs) and display devices. While silicon-based semiconductor materials are widely known as semiconductor thin films applicable to transistors, metal oxides (oxide semiconductors) that exhibit semiconducting properties have also attracted attention.

[0005] Furthermore, it is known that a transistor including an oxide semiconductor has an extremely small leakage current in a non-conducting state. For example, Patent Document 1 discloses a low-power consumption CPU that utilizes the property of a small leakage current. Furthermore, Patent Document 2 discloses a memory device that can retain stored data for a long period of time.

[0006] Also, In ２ O３ It has been reported that the compound is used in thin film transistors (Non-Patent Document 1).

[0007] Examples of oxide semiconductors that can be used for the active layer of a transistor include indium oxide, indium gallium zinc oxide, etc. Non-Patent Document 2 discloses a thin-film transistor that uses hydrogenated polycrystalline indium oxide formed by low-temperature solid-phase crystallization for the active layer.

[0008] JP 2012-257187 A JP 2011-151383 A

[0009] Dhananjay and C. W. Chu, “Realization of In▲2▼O▲3▼ thin film transistors through reactive evaporation process” Appl. Phys. Lett. 91, 132111 (2007). Y. Magari et al. , "High-mobility hydrogenated polycrystalline In 2 O 3 (In 2 O 3 : H) thin-film transistors", Nature Communications, 13, 1078 (2022) Takashi Koida, "High-mobility transparent conductive film", National Institute of Advanced Industrial Science and Technology, AIST Photovoltaic Power Generation Research Results Report 2019, Internet <URL: https: / / unit.aist.go.jp / rpd-envene / PV / ja / results / 2019 / oral / T13.pdf>

[0010] An object of one embodiment of the present invention is to provide a transistor capable of passing a large current. Another object is to provide a transistor with favorable electrical characteristics. Another object is to provide a transistor that can be miniaturized. Another object is to provide a transistor that occupies a small area. Another object is to provide a transistor with high reliability. Another object of one embodiment of the present invention is to provide a semiconductor device in which transistors can be arranged at high density. Another object is to provide a semiconductor device with low power consumption.

[0011] An object of one embodiment of the present invention is to provide a semiconductor device having a novel structure, and to overcome at least one of the problems of the prior art.

[0012] Note that the description of these problems does not preclude the existence of other problems. Note that one embodiment of the present invention does not necessarily solve all of these problems. Note that problems other than these can be extracted from the description of the specification, drawings, claims, etc.

[0013] One embodiment of the present invention is a transistor including a first conductive layer, a first insulating layer, a second conductive layer, a semiconductor layer, a second insulating layer, and a third conductive layer. The first insulating layer is located over the first conductive layer. The second conductive layer is located over the first insulating layer. The first insulating layer and the second conductive layer have openings. The semiconductor layer has a portion located on a side surface of the opening. The second insulating layer is located over the semiconductor layer. The third conductive layer has a portion facing the semiconductor layer with the second insulating layer interposed therebetween. The semiconductor layer includes a crystalline oxide semiconductor layer containing indium and oxygen. The oxide semiconductor layer is subjected to heat treatment at a temperature of 400° C. for 8 hours, and oxygen is removed from the oxide semiconductor layer at a concentration of 2×10 ２０ atoms / cm ３ When a +GBT stress test was conducted in a dark room under stress conditions of a substrate temperature of 125°C, a gate-source voltage Vgs of +1.98 V, and a drain-source voltage Vds of 0 V, the absolute value of the change in Vsh, |ΔVsh|, calculated from Id-Vg measurements over 1000 hours was within 200 mV, and the difference between the subthreshold swing value at a measurement temperature of -20°C and the subthreshold swing value at a measurement temperature of 110°C was 30 mV / dec or less.

[0014] Another embodiment of the present invention includes a first conductive layer, a first insulating layer, a second conductive layer, a semiconductor layer, a second insulating layer, and a third conductive layer. The first insulating layer is located over the first conductive layer. The second conductive layer is located over the first insulating layer. The first insulating layer and the second conductive layer have an opening. The semiconductor layer has a portion located on a side surface of the opening. The second insulating layer is located over the semiconductor layer. The third conductive layer has a portion facing the semiconductor layer with the second insulating layer interposed therebetween. The semiconductor layer includes a crystalline oxide semiconductor layer containing indium and oxygen. The oxide semiconductor layer has a crystalline oxide semiconductor layer in which an integrated value of the amount of diffusion of hydrogen is 5×10 in a heat treatment performed at a heating temperature of 200° C. for 8 hours. １２ atoms / cm ２ When a +GBT stress test was conducted in a dark room under stress conditions of a substrate temperature of 125°C, a gate-source voltage Vgs of +1.98 V, and a drain-source voltage Vds of 0 V, the absolute value of the change in Vsh, |ΔVsh|, calculated from Id-Vg measurements over 1000 hours was within 200 mV, and the difference between the subthreshold swing value at a measurement temperature of -20°C and the subthreshold swing value at a measurement temperature of 110°C was 30 mV / dec or less.

[0015] Another embodiment of the present invention includes a first conductive layer, a first insulating layer, a second conductive layer, a semiconductor layer, a second insulating layer, and a third conductive layer. The first insulating layer is located over the first conductive layer. The second conductive layer is located over the first insulating layer. The first insulating layer and the second conductive layer have openings. The semiconductor layer has a portion located on a side surface of the opening. The second insulating layer is located over the semiconductor layer. The third conductive layer has a portion facing the first semiconductor layer with the second insulating layer interposed therebetween. The semiconductor layer includes a crystalline oxide semiconductor layer containing indium and oxygen. The oxide semiconductor layer is subjected to heat treatment at a temperature of 400° C. for 8 hours, and oxygen is reduced to 2×10 ２０ atoms / cm ３ 1x10 or more ２１ atoms / cm ３The oxide semiconductor layer has a property of permeating hydrogen at an integrated value of 5×10 １２ atoms / cm ２ When a +GBT stress test was conducted in a dark room under stress conditions of a substrate temperature of 125°C, a gate-source voltage Vgs of +1.98 V, and a drain-source voltage Vds of 0 V, the absolute value of the change in Vsh, |ΔVsh|, calculated from Id-Vg measurements over 1000 hours was within 200 mV, and the difference between the subthreshold swing value at a measurement temperature of -20°C and the subthreshold swing value at a measurement temperature of 110°C was 30 mV / dec or less.

[0016] The grain boundary in the oxide semiconductor layer preferably has an extension length of 0 nm to 1000 nm, and the extension length is an average value of values ​​calculated for two 90-nm square fields extracted from a planar TEM image at a total magnification of 2,000,000 times.

[0017] In the above transistor, it is preferable that the amount of change in Vsh with temperature is −0.3 V or less in the range of −20° C. or more and 110° C. or less.

[0018] In the above transistor, the aluminum concentration in the oxide semiconductor layer measured by secondary ion mass spectrometry is 3.0×10 １５ atoms / cm ３ It is preferable that:

[0019] In the above transistor, the gallium concentration in the oxide semiconductor layer measured by secondary ion mass spectrometry was 4.0×10 １５ atoms / cm ３ It is preferable that:

[0020] According to one embodiment of the present invention, a transistor capable of passing a large current can be provided. Alternatively, a transistor with favorable electrical characteristics can be provided. Alternatively, a transistor that can be miniaturized can be provided. Alternatively, a transistor that occupies a small area can be provided. Alternatively, a transistor with high reliability can be provided. One embodiment of the present invention can provide a semiconductor device in which transistors can be arranged at high density. Furthermore, a semiconductor device with low power consumption can be provided.

[0021] Advantageous Effects of Invention According to one aspect of the present invention, it is possible to provide a semiconductor device having a novel configuration, and to improve at least one of the problems of the prior art.

[0022] Note that the description of these effects does not preclude the existence of other effects. Note that one embodiment of the present invention does not necessarily have all of these effects. Note that effects other than these can be extracted from the description in the specification, drawings, claims, etc.

[0023] FIGS. 1A, 1B, 1C, and 1D are structural examples of semiconductor devices. FIGS. 2A and 2B are structural examples of semiconductor devices. FIGS. 3A, 3B, and 3C are diagrams illustrating a manufacturing method of a semiconductor device. FIGS. 4A, 4B, and 4C are diagrams illustrating a manufacturing method of a semiconductor device. FIGS. 5A, 5B, and 5C are diagrams illustrating a manufacturing method of a semiconductor device. FIGS. 6A, 6B, and 6C are diagrams illustrating a manufacturing method of a semiconductor device. FIGS. 7A, 7B, 7C, and 7D are structural examples of semiconductor devices. FIGS. 8A, 8B, 8C, and 8D are structural examples of semiconductor devices. FIGS. 9A, 9B, and 9C are structural examples of memory devices. FIG. 10 is a structural example of a memory device. FIGS. 11A, 11B, and 11C are structural examples of memory devices. FIG. 12 is a structural example of a memory device. FIG. 13 is a block diagram illustrating a structural example of a semiconductor device. 14A, 14B, 14C, 14D, 14E, 14F, and 14G are diagrams illustrating an example of a circuit configuration of a memory cell. FIGS. 15A and 15B are perspective views of a semiconductor device. FIGS. 16A and 16B are diagrams illustrating an example of an electronic component. FIGS. 17A, 17B, and 17C are diagrams illustrating an example of a mainframe computer. FIG. 17D is a diagram illustrating an example of space equipment. FIG. 17E is a diagram illustrating an example of a storage system applicable to a data center. FIGS. 18A and 18B are diagrams illustrating the carrier concentration dependence of Hall mobility. FIG. 18C is a cross-sectional view illustrating an indium oxide film. FIGS. 19A, 19B, 19C, 19D, and 19E are SIMS analysis results of samples according to the example. FIGS. 20A, 20B, 20C, 20D, and 20E are SIMS analysis results of samples according to the example. 21A, 21B, 21C, 21D, and 21E are SIMS analysis results of samples according to the example. 22A, 22B, 22C, 22D, and 22E are SIMS analysis results of samples according to the example. 23A1, 23A2, 23B1, 23B2, 23C1, and 23C2 are TEM images of samples according to the example. 24A1, 24A2, 24B1, and 24B2 are TEM images of samples according to the example. 25A and 25B are diagrams illustrating the stacked structure of the stacked film.26A, 26B, and 26C show the results of SIMS analysis of the fabricated samples. FIGS. 27A and 27B show the results of SIMS analysis of the fabricated samples. FIGS. 28A and 28B are diagrams illustrating the relationship between the extension length of grain boundaries and oxygen concentration. FIGS. 29A, 29B, and 29C show the results of SIMS analysis of the fabricated samples. FIGS. 30A and 30B show the results of SIMS analysis of the fabricated samples. FIG. 31 is a conceptual diagram of a method for calculating integral values. FIG. 32 is a diagram illustrating the relationship between the extension length of grain boundaries and the integral of the amount of deuterium diffusion. FIGS. 33A and 33B show the Id-Vg characteristics of transistors. FIGS. 34A and 34B show the Id-Vg characteristics of transistors. FIGS. 35A, 35B, 35C, and 35D show the amount of change in transistor characteristic values ​​with temperature. FIG. 36 shows the evaluation results of a reliability test of the transistor. 37A and 37B show the results of SIMS analysis of the fabricated sample. 38A and 38B show the results of SIMS analysis of the fabricated sample. 39A and 39B show density of states diagrams obtained by calculation.

[0024] The following description of the preferred embodiments will be made with reference to the accompanying drawings. However, the present invention is not limited to the following description, and it will be readily understood by those skilled in the art that various changes can be made in the form and details without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the preferred embodiments shown below.

[0025] In the configuration of the invention described below, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and repeated explanations thereof will be omitted. Furthermore, when referring to similar functions, the same hatching pattern may be used and no particular reference numeral may be assigned.

[0026] In the drawings described in this specification, the size of each component, the thickness of layers, the positional relationship, or the area may be exaggerated for clarity, and therefore, the drawings are not necessarily limited to the scale.

[0027] In this specification, the ordinal numbers "first" and "second" are used for convenience and do not limit the number of components or the order of the components (for example, the order of processes or stacking order). Furthermore, the ordinal numbers assigned to components in one part of this specification may not match the ordinal numbers assigned to the same components in other parts of this specification or in the claims.

[0028] A transistor is a type of semiconductor element that can perform functions such as amplifying current or voltage and performing switching operations to control conduction or non-conduction. The term "transistor" as used herein includes an insulated gate field effect transistor (IGFET) and a thin film transistor (TFT).

[0029] In this specification and the like, a transistor using an oxide semiconductor or a metal oxide for a semiconductor layer and a transistor having an oxide semiconductor or a metal oxide for a channel formation region may be referred to as an OS (oxide semiconductor) transistor. A transistor having silicon for a channel formation region may be referred to as a Si transistor.

[0030] In this specification and the like, a transistor is an element having at least three terminals including a gate, a drain, and a source. A transistor has a region (also referred to as a channel formation region) where a channel is formed between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode), and current can flow between the source and the drain through the channel formation region. Note that in this specification and the like, the channel formation region refers to a region through which current mainly flows.

[0031] Furthermore, the functions of "source" and "drain" may be interchangeable when transistors of different polarities are used, or when the direction of current flow changes during circuit operation, etc. For this reason, the terms "source" and "drain" may be used interchangeably in this specification.

[0032] In this specification, the channel length direction of a transistor refers to one of the directions parallel to the line connecting the source region and the drain region at the shortest distance. In other words, the channel length direction corresponds to one of the directions of current flowing through the semiconductor layer when the transistor is in an on-state. The channel width direction refers to a direction perpendicular to the channel length direction. Depending on the structure or shape of the transistor, the channel length direction and the channel width direction may not be defined as a single direction.

[0033] Unless otherwise specified, in this specification and the like, the off-state current refers to the drain current when a transistor is in an off state (also referred to as a non-conducting state or a cut-off state). Unless otherwise specified, the off-state refers to a state in which the gate-source voltage Vgs is lower than the threshold voltage Vth for an n-channel transistor (higher than Vth for a p-channel transistor).

[0034] In this specification and the like, unless otherwise specified, the on-state current refers to the drain current when a transistor is in an on state (also referred to as a "conducting state"). Unless otherwise specified, the on state refers to a state in which Vgs is equal to or higher than Vth for an n-channel transistor, and a state in which Vgs is equal to or lower than the threshold voltage for a p-channel transistor.

[0035] In this specification, "connection" includes, as an example, "electrical connection." Note that the term "electrical connection" is sometimes used to define the connection relationship between circuit elements as an object. Furthermore, "electrical connection" includes "direct connection" and "indirect connection." "A and B are directly connected" means that A and B are connected without the intervention of a circuit element (e.g., a transistor, a switch, etc.; note that wiring is not a circuit element). On the other hand, "A and B are indirectly connected" means that A and B are connected via one or more circuit elements. Note that A and B represent objects such as elements, circuits, wiring, electrodes, terminals, semiconductor layers, and conductive layers.

[0036] For example, assuming that a circuit including A and B is operating, if there is a time during the operation of the circuit when an electrical signal is exchanged or an interaction of electrical potential occurs between A and B, then it can be defined that "A and B are indirectly connected" as objects. Note that even if there is a time during the operation of the circuit when no electrical signal is exchanged or an interaction of electrical potential occurs between A and B, it can still be defined that "A and B are indirectly connected" as long as there is a time during the operation of the circuit when an electrical signal is exchanged or an interaction of electrical potential occurs between A and B.

[0037] An example of a case where "A and B are indirectly connected" is when A and B are connected via the source and drain of one or more transistors. On the other hand, an example of a case where it cannot be said that "A and B are indirectly connected" is when an insulator is present in the path from A to B. Specifically, there are cases where a capacitive element is connected between A and B, and cases where a gate insulating film of a transistor is present between A and B. Therefore, it cannot be said that "the gate (A) of a transistor and the source or drain (B) of the transistor are indirectly connected."

[0038] Another example of a case where it cannot be said that "A and B are indirectly connected" is when multiple transistors are connected via their sources and drains to the path from A to B, and a constant potential V is supplied to a node between one transistor and another transistor from a power supply, GND, etc.

[0039] In this specification and the like, a plan view refers to a view from the normal direction of the surface on which the component is formed or the surface of a support (for example, a substrate) on which the component is formed.

[0040] In the following, expressions indicating directions such as "up" and "down" will basically be used in accordance with the directions in the drawings. However, for purposes such as facilitating explanation, the directions indicated by "up" or "down" in the specification may not match those in the drawings. For example, when explaining the stacking order (or formation order) of a laminate, etc., even if the surface on which the laminate is provided (such as a forming surface, a support surface, an adhesive surface, or a flat surface) is located above the laminate in the drawings, the forming surface side may be expressed as "down" and the direction opposite to the forming surface as "up."

[0041] Furthermore, in this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10 degrees or more and 10 degrees or less. Therefore, it also includes cases in which the angle is -5 degrees or more and 5 degrees or less. Furthermore, "substantially parallel" refers to a state in which two straight lines are arranged at an angle of -20 degrees or more and 20 degrees or less. Furthermore, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, it also includes cases in which the angle is 85 degrees or more and 95 degrees or less. Furthermore, "substantially perpendicular" refers to a state in which two straight lines are arranged at an angle of 70 degrees or more and 110 degrees or less.

[0042] In the drawings and the like relating to this specification, arrows indicating the X direction, Y direction, and Z direction may be used. In this specification and the like, the "X direction" refers to the direction along the X axis, and there may be no distinction between the forward direction and the reverse direction unless explicitly stated. The same applies to the "Y direction" and the "Z direction." The X direction, Y direction, and Z direction are directions that intersect with each other. For example, the X direction, Y direction, and Z direction are directions that are perpendicular to each other.

[0043] In addition, in this specification and the like, the terms "film" and "layer" are interchangeable. For example, the term "insulating layer" may be interchangeable with the term "insulating film."

[0044] In this specification and the like, an oxynitride refers to a material whose composition contains more oxygen than nitrogen. A nitride oxide refers to a material whose composition contains more nitrogen than oxygen. For example, silicon oxynitride refers to a material whose composition contains more oxygen than nitrogen, and silicon nitride oxide refers to a material whose composition contains more nitrogen than oxygen.

[0045] In this specification, space groups are expressed using short notation in international notation (or Hermann-Mauguin notation). Crystal planes and crystal orientations are expressed using Miller indices. In crystallography, space groups, crystal planes, and crystal orientations are expressed by adding a superscript bar to the numbers. However, due to formatting restrictions, in this specification, instead of adding a bar above the numbers, they may be expressed by adding a minus sign (-) before the numbers. Furthermore, individual orientations indicating directions within a crystal are expressed with [ ], collective orientations indicating all equivalent orientations are expressed with < >, individual planes indicating crystal planes are expressed with ( ), and collective planes with equivalent symmetry are expressed with {}.

[0046] Embodiment 1 In this embodiment, a structural example of a semiconductor device according to one embodiment of the present invention and an example of a manufacturing method thereof will be described.

[0047] In this embodiment, a semiconductor device of one embodiment of the present invention and a manufacturing method of the semiconductor device will be described with reference to FIGS. 1A to 6C. Note that in the plan views and perspective views shown below, some components (such as an insulating layer) may be omitted.

[0048] [Configuration Example of Semiconductor Device] FIGS. 1A to 1D are diagrams showing an example of a semiconductor device. FIG. 1A is a plan view of a semiconductor device having a transistor 100A. FIG. 1B is a cross-sectional view taken along dashed-dotted line A1-A2 in FIG. 1A. FIG. 1C is a cross-sectional view taken along dashed-dotted line B1-B2 in FIG. 1A. FIG. 1D is a horizontal cross-sectional view taken along dashed-dotted line C1-C2 in FIG. 1B. FIGS. 2A and 2B are schematic perspective views of the semiconductor device shown in FIGS. 1A to 1D. Some insulating films are not shown in FIGS. 2A and 2B to make the structure easier to understand. FIG. 2B is a schematic perspective view showing a cutaway portion of FIG. 2A.

[0049] The transistor 100A includes at least a conductive layer 102, a conductive layer 107, a semiconductor layer 108, an insulating layer 109, and a conductive layer 110. Part or all of the conductive layer 102 functions as a source electrode or a drain electrode. Part or all of the conductive layer 107 functions as a source electrode or a drain electrode. Part or all of the insulating layer 109 functions as a gate insulating film. Part or all of the conductive layer 110 functions as a gate electrode.

[0050] In this specification, when describing matters common to components distinguished by numbers attached to the reference symbols (conductive layer 102_1, conductive layer 102_2, conductive layer 102_3, conductive layer 1030a, conductive layer 1030b, conductive layer 1030c, etc.), the description may be made using symbols (conductive layer 102, conductive layer 1030, etc.) in which the alphabet or number is omitted.

[0051] The insulating layer 101 is provided on a substrate (not shown). The conductive layers 102 (conductive layer 102_1, conductive layer 102_2, conductive layer 102_3) are provided on the insulating layer 101. Note that the conductive layer 102 may have an island shape, or may extend in the X direction, the Y direction, or both the X and Y directions. The conductive layer 102 is preferably formed of three layers, namely, the conductive layer 102_1, the conductive layer 102_2, and the conductive layer 102_3, but may also be formed as a single layer, two layers, or a stack of four or more layers.

[0052] The insulating layer 103 is provided on the conductive layer 102 so as to cover the conductive layer 102. The insulating layer 104 is provided on the insulating layer 103. It is desirable that the upper surface of the insulating layer 104 be flat. The insulating layer 105 is provided on the insulating layer 104. The insulating layer 106 is provided on the insulating layer 105.

[0053] The conductive layer 107 is provided over the insulating layer 106. The conductive layer 107 may extend in the X direction, the Y direction, or both the X and Y directions. The conductive layer 107 is preferably formed as two layers, a conductive layer 107_1 and a conductive layer 107_2, but may also be formed as a single layer or a stack of three or more layers.

[0054] The opening 190 is provided in the conductive layer 107, the insulating layer 106, the insulating layer 105, the insulating layer 104, and the insulating layer 103, and reaches the conductive layer 102. A portion of the conductive layer 102 overlapping with the opening 190 has a recess. While the opening 190 is illustrated as being circular in plan view, it may be elliptical or polygonal. Furthermore, the shape and size in plan view may differ depending on the conductive layer 107, the insulating layer 106, the insulating layer 105, the insulating layer 104, and the insulating layer 103. For example, the diameter of the opening 190 provided in the insulating layer 103 may be smaller than the diameter of the opening 190 provided in the insulating layer 106. At least a portion of the sidewall of the opening 190 may be tapered.

[0055] The width D of the opening 190 is set depending on the film thickness of each of the semiconductor layer 108, the insulating layer 109, and the conductive layer 110 provided in the opening 190. The width D of the opening 190 is preferably, for example, 5 nm to 100 nm, 10 nm to 60 nm, 20 nm to 50 nm, 20 nm to 40 nm, or 20 nm to 30 nm.

[0056] The semiconductor layer 108 is provided over the conductive layer 107 so as to cover the sidewalls and bottom of the opening 190. The semiconductor layer 108 has portions in contact with the conductive layer 107 and the conductive layer 102. In the opening 190, the semiconductor layer 108 has portions in contact with the side surfaces of the conductive layer 107, the insulating layer 106, the insulating layer 105, the insulating layer 104, and the insulating layer 103. In addition, the semiconductor layer 108 has portions in contact with the conductive layer 102 in recesses provided in the conductive layer 102.

[0057] The insulating layer 109 is provided on the semiconductor layer 108 so as to cover the semiconductor layer 108. The insulating layer 109 has a portion in contact with the semiconductor layer 108 and a portion located inside the opening 190.

[0058] The conductive layer 110 is provided over the insulating layer 109, and has a portion facing the semiconductor layer 108 with the insulating layer 109 interposed therebetween. The conductive layer 110 also has a portion located inside the opening 190. The conductive layer 110 is preferably formed of two layers, a conductive layer 110_1 and a conductive layer 110_2, but may also be formed as a single layer or a stack of three or more layers. The conductive layer 110 may extend in the X direction, the Y direction, or both the X direction and the Y direction.

[0059] The insulating layer 111 is provided over the conductive layer 110 so as to cover the conductive layer 110. The insulating layer 112 is provided over the insulating layer 111. In addition, the insulating layer 111 preferably has a flat top surface.

[0060] As shown in FIGS. 1A to 2B , the transistor 100A has a structure in which one of the source electrode and the drain electrode (the conductive layer 102 here) is located below and the other of the source electrode and the drain electrode (the conductive layer 107 here) is located above, and thus current flows vertically. A channel is formed along the side surface of the opening 190. Therefore, the area occupied by the transistor 100A can be reduced. Therefore, the semiconductor device can be highly integrated. Furthermore, when the semiconductor device of one embodiment of the present invention is used for a memory device, the memory capacity per unit area can be increased. Note that the transistor 100A can be said to have a channel length direction having a component in the height direction (vertical direction); therefore, the transistor 100A can be called a VFET (Vertical Field Effect Transistor), a vertical transistor, a vertical channel transistor, a vertical channel transistor, or the like.

[0061] The distance between one of the source electrode and the drain electrode (here, the conductive layer 102) and the other of the source electrode and the drain electrode (here, the conductive layer 107) of the transistor 100A can be set by the total film thickness of the insulating layers 103, 104, 105, and 106 that overlap with the conductive layer 102. The total film thickness can be, for example, 0.1 nm to 500 nm, 1 nm to 300 nm, 5 nm to 100 nm, 5 nm to 60 nm, 5 nm to 50 nm, 5 nm to 40 nm, 5 nm to 30 nm, 5 nm to 20 nm, or 5 nm to 10 nm.

[0062] Furthermore, a portion of the conductive layer 102 overlapping with the opening 190 has a recess. Therefore, the contact area between the conductive layer 102 and the semiconductor layer 108 can be increased compared to when there is no recess. Therefore, the contact resistance between the conductive layer 102 and the semiconductor layer 108 can be reduced.

[0063] The depth of the recess in the conductive layer 102 is preferably set to be equal to or deeper than the total film thickness of the semiconductor layer 108 and the insulating layer 109. The height of the bottom surface of the conductive layer 110 in the opening 190 is preferably set to be equal to or lower than the height of the top surface of the conductive layer 102 other than the recess. With this structure, the controllability of the electron density of the semiconductor layer 108 near one of the source electrode and the drain electrode (here, the conductive layer 102) can be improved by the gate electric field from the gate electrode (conductive layer 110) compared to a case where there is no recess.

[0064] The recess in the conductive layer 102 may have a curved portion as shown in FIGS. 1B and 1C. When the recess has a curved portion, the semiconductor layer 108, the insulating layer 109, and the conductive layer 110 provided on the recess near the recess may also have a curved portion. In other words, the portion may have a curved or concave surface in cross-sectional view. Furthermore, the portion may not have a corner (right angle or acute angle) in cross-sectional view. This reduces electric field concentration on the insulating layer 109 near the recess, improves the breakdown voltage of the transistor 100A, and suppresses electrostatic breakdown of the transistor 100A. Therefore, the reliability of the semiconductor device can be improved.

[0065] [Materials for Constituting the Semiconductor Device] Materials that can be used in the semiconductor device of this embodiment will be described below. Note that each layer constituting the semiconductor device of this embodiment may have a single-layer structure or a multilayer structure.

[0066] [Substrate] As a substrate of the semiconductor device described in this embodiment, any of the following substrates can be used as appropriate.

[0067] Substrates on which transistors are formed may be, for example, insulating substrates, semiconductor substrates, or conductive substrates. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (e.g., yttria-stabilized zirconia substrates), and resin substrates. Examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, or compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, gallium oxide, and gallium nitride. Examples of semiconductor substrates having an insulating region within the aforementioned semiconductor substrate include silicon-on-insulator (SOI) substrates. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Substrates containing metal nitrides and substrates containing metal oxides can also be used. Examples of substrates include an insulating substrate having a conductive layer or semiconductor layer provided thereon, a semiconductor substrate having a conductive layer or insulating layer provided thereon, and a conductive substrate having a semiconductor layer or insulating layer provided thereon. Alternatively, a substrate provided with elements may be used, such as a capacitor, a resistor, a switch (including a transistor), a light-emitting element, a memory element, or the like.

[0068] [Semiconductor Layer] The semiconductor layer 108 preferably contains a metal oxide (oxide semiconductor) that exhibits semiconductor properties.

[0069] The semiconductor layer 108 may have a stacked structure of two or more layers.

[0070] The crystallinity of the semiconductor material used for the semiconductor layer 108 is not particularly limited, and any of an amorphous semiconductor, a single crystal semiconductor, and a semiconductor having crystallinity other than single crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor having a crystalline region in part) may be used. Use of a single crystal semiconductor or a crystalline semiconductor is preferable because it can suppress deterioration of transistor characteristics.

[0071] An OS transistor has an oxygen vacancy (V Ｏ ) and impurities, the electrical characteristics are likely to fluctuate and reliability may be reduced. Ｏ H) and generate electrons that serve as carriers. Therefore, if the channel formation region in the metal oxide contains oxygen vacancies, the OS transistor is likely to be normally on. Therefore, it is preferable that the oxygen vacancies and impurities are reduced as much as possible in the channel formation region in the metal oxide. In other words, it is preferable that the carrier concentration in the channel formation region in the metal oxide is reduced and the channel formation region in the metal oxide is made i-type (intrinsic) or substantially i-type.

[0072] On the other hand, the source and drain regions of an OS transistor have more oxygen vacancies than the channel formation region. Ｏ The source and drain regions of an OS transistor are preferably n-type regions having a high carrier concentration and low resistance, as compared with a channel formation region, due to a high concentration of H or an impurity such as hydrogen, nitrogen, or a metal element.

[0073] The band gap of a metal oxide functioning as a semiconductor is preferably 2.0 eV or more, more preferably 2.5 eV or more. By using a metal oxide with a wide band gap for an oxide semiconductor layer, the off-state current of a transistor can be reduced. Because the off-state current of an OS transistor is small, the power consumption of a semiconductor device can be sufficiently reduced. Furthermore, because the frequency characteristics of an OS transistor are high, the semiconductor device can operate at high speed.

[0074] For example, indium oxide can be used for the semiconductor layer 108. For indium oxide used for the semiconductor layer 108, the description in Embodiment 5 can be referred to.

[0075] Examples of the metal oxide that can be used for the semiconductor layer of an OS transistor include oxides containing one or more elements selected from In, Sn, Zn, Ga, Al, and Ti. In these oxides, the content of each of the elements selected from In, Sn, Zn, Ga, Al, and Ti is preferably 1 atomic % or more, for example.

[0076] Examples of metal oxides that can be used for the semiconductor layer 108 include gallium oxide and zinc oxide. The metal oxide preferably contains at least In or Zn. The metal oxide preferably contains two or three elements selected from In, element M, and Zn. The element M is a metal element or semimetal element having a high bond energy with oxygen, such as a metal element or semimetal element having a bond energy with oxygen higher than that of indium. Specific examples of element M include Al, Ga, Sn, Y, Ti, V, Cr, Mn, Fe, Co, Ni, Zr, Mo, Hf, Ta, W, La, Ce, Nd, Mg, Ca, Sr, Ba, B, Si, Ge, and Sb. The element M contained in the metal oxide is preferably one or more of the above elements, and is particularly preferably one or more selected from Al, Ga, Y, and Sn, with Ga being more preferred. Hereinafter, a metal oxide having In, M, and Zn may be referred to as an In-M-Zn oxide. In this specification and the like, metal elements and metalloid elements may be collectively referred to as "metal elements," and the "metal elements" described in this specification and the like may include metalloid elements.

[0077] Examples of the metal oxide include zinc oxide, tin oxide, indium zinc oxide (In-Zn oxide), indium tin oxide (In-Sn oxide), indium titanium oxide (In-Ti oxide), indium gallium oxide (In-Ga oxide), indium gallium aluminum oxide (In-Ga-Al oxide), indium gallium tin oxide (In-Ga-Sn oxide), gallium zinc oxide (Ga-Zn oxide, also referred to as "GZO"), aluminum zinc oxide (Al-Zn oxide, also referred to as "AZO"), and indium aluminum oxide. Examples of usable materials include indium zinc oxide (In-Al-Zn oxide, also referred to as "IAZO"), indium tin zinc oxide (In-Sn-Zn oxide), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also referred to as "IGZO"), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also referred to as "IGZTO"), and indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also referred to as "IGAZO" or "IAGZO"). Alternatively, indium tungsten oxide (In-W oxide, also referred to as "IWO") can be used. Alternatively, silicon-containing indium tin oxide, gallium tin oxide (Ga-Sn oxide), aluminum tin oxide (Al-Sn oxide), and the like can be used.

[0078] Specifically, the composition of the In-Zn oxide can be In:Zn=1:1 (atomic ratio) or a composition close thereto, In:Zn=2:1 (atomic ratio) or a composition close thereto, or In:Zn=4:1 (atomic ratio) or a composition close thereto, where the term "nearby composition" includes a range of ±30% of the desired atomic ratio.

[0079] When the metal oxide is an In-M-Zn oxide, the atomic ratio of In in the In-M-Zn oxide is preferably equal to or greater than the atomic ratio of M. For example, the atomic ratios of metal elements in such an In-M-Zn oxide may be In:M:Zn = 1:1:1, In:M:Zn = 1:1:1.2, In:M:Zn = 2:1:3, In:M:Zn = 3:1:2, In:M:Zn = 4:2:3, In:M:Zn = 4:2:4.1, In:M:Zn = 5:1:3, In:M:Zn = 5:1:6, In:M:Zn = 5:1:7, In:M:Zn = 5:1:8, In:M:Zn = 6:1:6, In:M:Zn = 5:2:5, or compositions in the vicinity thereof. Note that the term "composition in the vicinity" refers to a range of ±30% of the desired atomic ratio. By increasing the atomic ratio of indium in the metal oxide, the on-state current, field-effect mobility, and the like of a transistor can be increased.

[0080] Furthermore, the atomic ratio of In in the In-M-Zn oxide may be less than the atomic ratio of M. For example, the atomic ratio of metal elements in such an In-M-Zn oxide may be In:M:Zn=1:3:2, In:M:Zn=1:3:3, In:M:Zn=1:3:4, or a composition close to these. By increasing the atomic ratio of M in the metal oxide, the generation of oxygen vacancies can be suppressed.

[0081] Note that the metal oxide may contain one or more metal elements with higher period numbers in the periodic table instead of or in addition to indium. The greater the overlap of the orbitals of metal elements, the greater the carrier conduction in the metal oxide tends to be. Therefore, including a metal element with a higher period number may improve the field-effect mobility of a transistor. Examples of metal elements with higher period numbers include metal elements belonging to the fifth period and the sixth period. Specific examples of such metal elements include Y, Zr, Ag, Cd, Sn, Sb, Ba, Pb, Bi, La, Ce, Pr, Nd, Pm, Sm, and Eu. Note that La, Ce, Pr, Nd, Pm, Sm, and Eu are called light rare earth elements.

[0082] The metal oxide may also contain one or more nonmetallic elements, which may increase the field-effect mobility of the transistor. Examples of nonmetallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.

[0083] The metal oxide can be preferably formed by sputtering or atomic layer deposition (ALD). In particular, it is preferable to form the metal oxide by the ALD method, which has excellent coating properties. When forming the metal oxide by sputtering, the composition of the metal oxide after film formation may differ from the composition of the target. In particular, the zinc content in the metal oxide after film formation may be reduced to about 50% compared to the target. Furthermore, the sputtering method and the ALD method can be combined as a method for forming the metal oxide. For example, a method in which a metal oxide is formed by sputtering and then formed by ALD, or a method in which a metal oxide is formed by ALD and then formed by sputtering, can be used.

[0084] The semiconductor layer 108 may have a stacked structure including two or more metal oxide layers. The two or more metal oxide layers included in the semiconductor layer 108 may have the same or substantially the same composition. By using a stacked structure of metal oxide layers with the same composition, for example, the same sputtering target can be used to form the semiconductor layer 108, thereby reducing manufacturing costs. Note that a stacked structure in which two or more oxide semiconductor layers with different compositions are stacked may also be used. Furthermore, by using the ALD method, a metal oxide layer whose composition continuously varies in the thickness direction can also be formed. This not only broadens the range of design options compared to using a film with a fixed composition, but also prevents the generation of interface states between two layers with different compositions, thereby improving electrical characteristics and reliability. Furthermore, a metal oxide layer having a stacked structure may be formed using both the sputtering method and the ALD method.

[0085] For example, when the semiconductor layer 108 has a three-layer structure, it is preferable to use a material for the second layer that has a higher mobility than the first and third layers. This allows the second layer to mainly serve as a current path, thereby suppressing scattering at the interface with the gate insulating layer and realizing a highly reliable transistor.

[0086] The difference in the mobility and conductivity described above can be expressed, for example, by the indium content. In addition, whether or not an element other than indium that contributes to improving conductivity is included, and the content of that element, also affect the mobility and conductivity. Examples of high-mobility materials include In:Ga:Zn = 4:2:3, In:Zn = 1:1, In:Zn = 2:1, In:Zn = 4:1, In:Sn:Zn = 40:X:10 (where X is 0.1 or more and 5 or less, typically X = 1), or materials with compositions similar to these. On the other hand, materials with lower mobility or conductivity than the above-mentioned materials include In:Ga:Zn = 1:3:2, In:Ga:Zn = 1:3:4, In:Ga:Zn = 2:2:1, In:Ga:Zn = 1:1:1, In:Ga:Zn = 1:1:2, or materials with compositions similar to these.

[0087] A crystalline metal oxide layer is preferably used for the semiconductor layer 108. For example, a metal oxide layer having a single crystal structure, a c-axis aligned crystalline (CAAC) structure, a polycrystalline structure, a nanocrystalline (nc) structure, or the like can be used. By using a crystalline metal oxide layer for the semiconductor layer 108, the density of defect states in the semiconductor layer 108 can be reduced, and a highly reliable semiconductor device can be realized.

[0088] When an IGZO (In—Ga—Zn—O-based oxide) film is used as the metal oxide layer applied to the semiconductor layer 108, the higher the crystallinity of the metal oxide layer, the more the density of defect states in the semiconductor layer 108 can be reduced. On the other hand, by using a metal oxide layer with low crystallinity, the carrier concentration can be increased, and a transistor capable of passing a large current can be realized in some cases.

[0089] In particular, it is preferable to use indium oxide for the semiconductor layer 108. In particular, it is preferable to use a single-crystal indium oxide film. Note that a crystalline film is preferably used for the semiconductor layer 108, and it is particularly preferable to use indium oxide having a single-crystal structure. However, indium oxide having a polycrystalline structure or a microcrystalline structure can also be used. By using indium oxide having a single-crystal structure, carrier scattering at crystal grain boundaries can be suppressed, and a transistor with high field-effect mobility can be realized. Furthermore, a highly reliable transistor can be realized. When indium oxide having a polycrystalline structure is used, it is preferable that crystal grain boundaries are not observed at least in the channel formation region (the region overlapping with the conductive layer 110). As a result, even indium oxide having a polycrystalline structure can achieve the same effects as indium oxide having a single-crystal structure.

[0090] When polycrystalline indium oxide is used for the semiconductor layer 108, it is preferable that the semiconductor layer 108 has oxygen atoms with dangling bonds at the grain boundaries or the interface with the insulating layer 109. In this case, it can be said that at least a portion of the indium atoms located at the grain boundaries or the interface with the insulating layer 109 are terminated by oxygen atoms. Examples of oxygen atoms with dangling bonds include oxygen atoms having 0 to 5 bonds with indium atoms (corresponding to oxygen atoms of non-bridging oxygen hole centers (NBOHCs)) and oxygen atoms bonded to NBOHCs (corresponding to oxygen atoms at the terminals of peroxy radicals (PORs)). Oxygen atoms with dangling bonds are more thermally stable than oxygen atoms located between the lattices of indium oxide. Furthermore, it is preferable that the indium atoms with dangling bonds located at the grain boundaries or the interface with the insulating layer 109 are terminated by hydrogen atoms (hydrogen termination). In addition, some of the oxygen atoms that are located at the grain boundary or the interface with the insulating layer 109 and have dangling bonds are preferably terminated with hydrogen atoms (hydrogen termination).

[0091] Here, the influence of oxygen atoms having dangling bonds and hydrogen termination will be explained using the results of calculations. A slab model of indium oxide in which In atoms are located on the outermost surface (referred to as the first model), a slab model in which the indium atoms located on the outermost surface of the first model are terminated with hydrogen atoms (referred to as the second model), a slab model of indium oxide in which oxygen atoms are located on the outermost surface (referred to as the third model), and a slab model in which the oxygen atoms located on the outermost surface of the second model are terminated with hydrogen atoms (referred to as the fourth model) were prepared, and the density of states (DOS) of each model was calculated using first-principles calculations. The results are shown in FIG. 39. In FIG. 39, the vertical axis represents DOS and the horizontal axis represents energy.

[0092] 39A , it is confirmed that an intra-gap level (a level near −1.5 eV) is formed in the DOS of the first model compared to the second model. The formation of the intra-gap level is presumed to be due to In atoms having dangling bonds on the outermost surface. Furthermore, it is confirmed that the intra-gap level is reduced in the DOS of the second model compared to the first model. The reduction in the intra-gap level is presumed to be due to hydrogen termination of In atoms having dangling bonds. Since the intra-gap level is a factor that increases the variation in transistor characteristics, it is preferable to reduce it. Therefore, it is suggested that terminating In atoms having dangling bonds with hydrogen atoms can reduce the variation in transistor characteristics.

[0093] 39B , it is confirmed that a level is formed near the valence band in the DOS of the third model compared to the fourth model. This level is presumed to be an acceptor level. Therefore, it is suggested that electrons are captured at this level, causing the threshold voltage to shift to the positive side. The formation of this level is presumed to be caused by oxygen atoms having dangling bonds. Furthermore, it is confirmed that the level near the valence band is reduced in the DOS of the fourth model compared to the third model. The reduction in this level is presumed to be caused by hydrogen termination of oxygen atoms having dangling bonds. Therefore, it is suggested that reliability can be improved by terminating oxygen atoms having dangling bonds with hydrogen atoms.

[0094] For the above reasons, oxygen atoms having dangling bonds are preferably present at the crystal grain boundaries or the interface with the insulating layer 109. Indium atoms having dangling bonds that are located at the crystal grain boundaries or the interface with the insulating layer 109 are preferably terminated with hydrogen atoms. Furthermore, some of the oxygen atoms having dangling bonds that are located at the crystal grain boundaries or the interface with the insulating layer 109 are preferably terminated with hydrogen atoms.

[0095] The thickness of the semiconductor layer 108 is preferably 1 nm to 50 nm, more preferably 1.5 nm to 40 nm, more preferably 2.5 nm to 30 nm, more preferably 2.5 nm to 20 nm, more preferably 5 nm to 20 nm, and even more preferably 5 nm to 10 nm. The thinner the semiconductor layer 108, the smaller the subthreshold value (S value) may be. Furthermore, the thinner the semiconductor layer 108, the more the threshold voltage may be shifted in the positive direction. Furthermore, by making the semiconductor layer 108 2 nm or more, the crystallinity of the semiconductor layer 108 can be improved. Note that if the semiconductor layer 108 is less than 2 nm, clear crystallinity may not be confirmed.

[0096] Among oxide semiconductors with high crystallinity, indium oxide is a film through which one or both of hydrogen and oxygen move more easily than, for example, an IGZO (In—Ga—Zn—O-based oxide) film. Therefore, indium oxide can be said to be a film through which one or both of hydrogen and oxygen are more easily supplied and discharged than, for example, an IGZO film. As a result, excess oxygen or excess hydrogen, which can become carriers or fixed charges, is less likely to accumulate in the semiconductor layer 108, and therefore a transistor with favorable electrical characteristics and reliability can be obtained.

[0097] The semiconductor layer 108 preferably has a reduced concentration of elements that reduce crystallinity. For example, the concentration of elements such as boron and aluminum is preferably 1 atomic % or less, more preferably 0.1 atomic % or less, and further preferably 0.01 atomic % (100 ppm) or less.

[0098] Furthermore, when indium oxide is used for the semiconductor layer 108, unintentionally mixed gallium has a tendency to easily bond with excess oxygen atoms, which may increase the amount of variation in threshold voltage in a PBTS (Positive Bias Temperature Stress) test. Therefore, when indium oxide is used for the semiconductor layer 108, the gallium concentration in the semiconductor layer 108 is preferably 1 atomic % or less, more preferably 0.1 atomic % or less, and even more preferably 0.01 atomic % (100 ppm) or less.

[0099] A transistor using an oxide semiconductor (hereinafter referred to as an OS transistor) has extremely high field-effect mobility compared to a transistor using amorphous silicon. Furthermore, an OS transistor has an extremely low off-state current and can hold charge accumulated in a capacitor connected in series with the transistor for a long period of time. Furthermore, the use of an OS transistor can reduce the power consumption of a semiconductor device.

[0100] The semiconductor device according to one embodiment of the present invention can be applied to, for example, a processor, a memory device, or various ICs. The transistor according to one embodiment of the present invention is capable of passing a large current and has an extremely low off-state current, and therefore, high-speed operation of a circuit and low power consumption can be achieved at the same time.

[0101] OS transistors exhibit smaller variations in electrical characteristics due to radiation exposure than Si transistors, i.e., have high radiation resistance, and therefore can be suitably used in environments where radiation may be incident. It can also be said that OS transistors have high reliability against radiation. For example, OS transistors can be suitably used in pixel circuits of X-ray flat panel detectors. Furthermore, OS transistors can be suitably used in semiconductor devices used in outer space. Examples of radiation include electromagnetic radiation (e.g., X-rays and gamma rays) and particle radiation (e.g., alpha rays, beta rays, proton rays, and neutron rays).

[0102] Examples of semiconductor materials that can be used for the semiconductor layer 108 include semiconductors made of single elements and compound semiconductors. Examples of semiconductors made of single elements include silicon (including single crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon) and germanium. Examples of compound semiconductors include gallium arsenide and silicon germanium. Examples of compound semiconductors include organic semiconductors, nitride semiconductors, and oxide semiconductors. Note that these semiconductor materials may contain impurities as dopants.

[0103] Alternatively, the semiconductor layer 108 may include a layered material that functions as a semiconductor. A layered material is a general term for a group of materials having a layered crystal structure. A layered crystal structure is a structure in which layers formed by covalent bonds or ionic bonds are stacked via bonds weaker than covalent bonds or ionic bonds, such as van der Waals bonds. A layered material has high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity. By using a material that functions as a semiconductor and has high two-dimensional electrical conductivity in the channel formation region, a transistor with a large on-state current can be provided.

[0104] Examples of the layered material include graphene, silicene, and chalcogenides. Chalcogenides are compounds containing chalcogen (an element belonging to Group 16). Examples of chalcogenides include transition metal chalcogenides and Group 13 chalcogenides. Specific examples of transition metal chalcogenides that can be used as semiconductor layers of transistors include molybdenum sulfide (typically MoS ２ ), molybdenum selenide (typically MoSe ２ ), molybdenum telluride (typically MoTe ２ ), tungsten sulfide (typically WS ２ ), tungsten selenide (typically WSe ２ ), tungsten tellurium (typically WTe ２ ), hafnium sulfide (typically HfS ２ ), hafnium selenide (typically HfSe ２ ), zirconium sulfide (typically ZrS ２ ), zirconium selenide (typically ZrSe ２ ) etc.

[0105] The semiconductor layer 108 may have, for example, a stacked structure of an IGZO film formed by ALD on gallium oxide formed by ALD, and an IGZO film formed by sputtering on the IGZO film. Alternatively, it may have a stacked structure of an indium oxide film formed by ALD, and an IGZO film formed by sputtering on the indium oxide film. Alternatively, it may have a stacked structure of an IGZO film formed by ALD on an IGZO film formed by sputtering.

[0106] [Conductive Layer] A low-resistance conductive material is preferably used for the conductive layers 102, 107, 110, and the like. For the conductive layers 102, 107, 110, and the like, a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, cobalt, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, and the like, or an alloy containing the metal element, is preferably used. Nitrides of the above metals or alloys, or oxides of the above metals or alloys may also be used. For example, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, and the like are preferably used. Alternatively, a semiconductor having high electrical conductivity, such as polycrystalline silicon containing an impurity element such as phosphorus, or a silicide such as nickel silicide may be used. Tantalum, tantalum nitride, or the like is preferably used as the conductive layer because it has a barrier property against hydrogen.

[0107] A conductive layer used for the conductive layer 102, the conductive layer 107, the conductive layer 110, or the like may have a portion in contact with the semiconductor layer 108. When an oxide semiconductor is used as the semiconductor layer 108, if a metal that is easily oxidized, such as aluminum, is used in the portion of the conductive layer in contact with the semiconductor layer 108, an insulating oxide (e.g., aluminum oxide) may be formed between the conductive layer and the semiconductor layer 108, which may hinder electrical conduction therebetween. Therefore, it is preferable to use a conductive material that is not easily oxidized, a conductive material that maintains low electrical resistance even when oxidized, or a conductive oxide in at least the portion of the conductive layer in contact with the semiconductor layer 108.

[0108] As the conductive layer used for the conductive layer 102, the conductive layer 107, the conductive layer 110, etc., it is preferable to use, for example, tantalum nitride, titanium nitride, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, etc. These are preferable because they are conductive materials that are difficult to oxidize or materials that maintain conductivity even when oxidized.

[0109] Alternatively, a conductive oxide can be used for a portion of a conductive layer used in the conductive layer 102, the conductive layer 107, the conductive layer 110, or the like that is in contact with the semiconductor layer 108. Examples of conductive oxides that can be used include indium oxide, indium tin oxide (In—Sn oxide, also referred to as ITO), indium tin oxide containing silicon (In—Sn—Si oxide, also referred to as ITSO), In—Zn oxide, In—W oxide, In—W—Zn oxide, In—Ti oxide, and In—Ti—Sn oxide. Conductive oxides containing indium are particularly preferable because of their high conductivity. Alternatively, an oxide semiconductor that can be used for the semiconductor layer 108 can also be used as a conductive layer by increasing the carrier concentration.

[0110] For example, as the conductive layers used for the conductive layer 102, the conductive layer 107, the conductive layer 110, and the like, a single-layer structure of the above-mentioned conductive oxide film, a two-layer structure in which a ruthenium film or a ruthenium oxide film is stacked on a tungsten film, a two-layer structure in which the above-mentioned conductive oxide film is stacked on a ruthenium film or a ruthenium oxide film, or a two-layer structure in which a conductive oxide film is stacked on a tungsten film can be used. Alternatively, a three-layer structure in which tungsten is stacked on titanium nitride and a conductive oxide is stacked on the tungsten can be used. Alternatively, a four-layer structure in which tantalum nitride, titanium nitride, tungsten, and a conductive oxide are stacked in this order from the bottom can be used.

[0111] [Gate Insulating Film] As transistors become smaller and more highly integrated, thinner gate insulating layers can cause problems such as leakage current. Using a high-k material for the gate insulating layer allows for lower voltage operation of the transistor while maintaining the physical film thickness. Furthermore, the equivalent oxide thickness (EOT) of the gate insulating layer can be reduced. On the other hand, using a material with a low dielectric constant for the insulating layer functioning as an interlayer film can reduce parasitic capacitance between wirings. Therefore, it is preferable to select a material depending on the function of the insulating layer. The insulating layer 109 functions as a gate insulating film of the transistor. When an oxide semiconductor is used for the semiconductor layer 108, it is preferable to use an oxide insulating film for at least the film of the insulating layer 109 that is in contact with the semiconductor layer 108. For example, one or more of silicon oxide, silicon oxynitride, aluminum oxide, aluminum oxynitride, hafnium oxide, hafnium oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, and Ga—Zn oxide can be used. Alternatively, a nitride insulating film such as silicon nitride, silicon nitride oxide, aluminum nitride, or aluminum nitride oxide can be used as the insulating layer 109. The insulating layer 109 may have a stacked structure, for example, a stacked structure including one or more oxide insulating films and one or more nitride insulating films.

[0112] The insulating layer 109 is preferably formed by stacking insulating materials made of high-k materials with a high dielectric constant, and preferably by stacking a high-k material and a material with a higher dielectric strength than the high-k material. For example, hafnium oxide, hafnium silicate, nitrogen-doped hafnium silicate, zirconium oxide, and aluminum oxide can be used as the insulating layer 109. Alternatively, an insulating film (also referred to as ZAZ) in which zirconium oxide, aluminum oxide, and zirconium oxide are stacked in this order can be used. Alternatively, an insulating film (also referred to as ZAZA) in which zirconium oxide, aluminum oxide, zirconium oxide, and aluminum oxide are stacked in this order can be used. Alternatively, an insulating film (also referred to as hafnium zirconium oxide, aluminum oxide, hafnium zirconium oxide, and aluminum oxide can be stacked in this order can be used. By stacking an insulator with a relatively high dielectric strength, such as aluminum oxide, the dielectric strength can be improved, and electrostatic breakdown can be suppressed.

[0113] Furthermore, a material exhibiting ferroelectricity may be used for the insulating layer 109. Examples of the material exhibiting ferroelectricity include metal oxides such as hafnium oxide, zirconium oxide, and hafnium zirconium oxide.

[0114] When the insulating layer 109 has a two-layer structure, it is preferable to use an insulating film having a function of capturing or fixing hydrogen as the film located on the semiconductor layer 108 side, and an insulating film having a barrier property against hydrogen as the film located on the conductive layer 110 side functioning as a gate electrode. This can suppress diffusion of hydrogen from the conductive layer 110 side to the semiconductor layer 108, thereby realizing a highly reliable transistor.

[0115] When the insulating layer 109 has a three-layer structure, it is preferable that an insulating film having one or both of a high dielectric strength and a leakage current suppression function is used as the film located on the semiconductor layer 108 side, an insulating film having a barrier property against hydrogen and oxygen is used as the film located on the conductive layer 110 side, and an insulating film having a function of capturing or fixing hydrogen is used as the film located between them. Silicon oxide or silicon oxynitride can be used as the insulating film having a high dielectric strength function. Silicon oxide or silicon oxynitride can also be said to be an insulating film having a leakage current suppression function. The film located on the conductive layer 110 side can prevent oxygen from diffusing toward the conductive layer 110 side and suppress oxidation of the conductive layer 110.

[0116] When the insulating layer 109 has a four-layer structure, it is preferable to use an insulating film having a barrier property against oxygen as the film located on the semiconductor layer 108 side, an insulating film having one or both of a high dielectric strength function and a leakage current suppression function as the film next closest to the semiconductor layer 108, an insulating film having a function of capturing or fixing hydrogen as the film next closest to the semiconductor layer 108, and an insulating film having a barrier property against hydrogen and oxygen as the film located closest to the conductive layer 110. That is, in addition to the above-described three-layer structure, a structure can be obtained in which a film is added to the semiconductor layer 108 side. By using an insulating film having a barrier property against oxygen as the film in contact with the semiconductor layer 108, oxygen can be prevented from being released from the semiconductor layer 108. In this case, an aluminum oxide film is preferably used as the film in contact with the semiconductor layer 108. Aluminum oxide not only has a barrier property against oxygen but also has a function of capturing or fixing hydrogen, thereby preventing hydrogen from diffusing into the semiconductor layer 108.

[0117] When the insulating layer 109 has a stacked structure, each insulating film is preferably a thin film. For example, when the total thickness of the insulating layer 109 is 1 nm to 20 nm, preferably 2 nm to 10 nm, the subthreshold swing value (also referred to as S value) of the transistor can be reduced. The thickness of each insulating film is preferably 0.1 nm to 10 nm, more preferably 0.1 nm to 5 nm, still more preferably 0.5 nm to 5 nm, still more preferably 1 nm to less than 5 nm, and still more preferably 1 nm to 3 nm.

[0118] As a specific example, it is preferable to use a four-layer structure in which an aluminum oxide film, a silicon oxide film, a hafnium oxide film, and a silicon nitride film are stacked in this order from the semiconductor layer 108 side, and the thicknesses of these films are 1 nm, 2 nm, 2 nm, and 1 nm from the semiconductor layer 108 side.

[0119] As another specific example, it is preferable to use a four-layer structure in which a hafnium oxide film, a silicon oxide film, a hafnium oxide film, and a silicon nitride film are stacked in this order from the semiconductor layer 108 side, and to set the thicknesses of these films to 1 nm, 2 nm, 2 nm, and 1 nm from the semiconductor layer 108 side.

[0120] As another specific example, a two-layer structure is used in which a silicon oxide film and a hafnium oxide film are stacked in this order from the semiconductor layer 108 side, and the thicknesses of these are preferably 1 nm and 1.5 nm from the semiconductor layer 17 side.

[0121] In this specification and the like, the barrier property refers to a property that makes it difficult for a corresponding substance to diffuse (also referred to as a property that makes it difficult for a corresponding substance to permeate, a property that makes the permeability of the corresponding substance low, or a function that suppresses the permeation of the corresponding substance). Note that when hydrogen is described as a corresponding substance, it can refer to, for example, a hydrogen atom, a hydrogen molecule, a water molecule, and OH. − Furthermore, unless otherwise specified, impurities when described as corresponding substances refer to impurities in the channel formation region or semiconductor layer, and include, for example, hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N ２ O, NO, NO ２The term "oxygen" refers to at least one of an oxygen atom, an oxygen molecule, etc., when described as a corresponding substance.

[0122] Here, a transistor using a metal oxide film can have stable electrical characteristics by being surrounded by an insulating film that has a function of suppressing the permeation of impurities such as water and hydrogen and oxygen. Examples of insulating films that have a function of suppressing the permeation of impurities such as water and hydrogen and oxygen include oxides such as aluminum oxide, magnesium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, and oxides containing aluminum and hafnium (hafnium aluminate). Nitrides such as aluminum nitride, silicon nitride oxide, and silicon nitride can also be used.

[0123] Examples of insulating film materials capable of capturing or adhering hydrogen include metal oxides such as oxides containing hafnium, oxides containing magnesium, oxides containing aluminum, and oxides containing aluminum and hafnium (hafnium aluminate). These metal oxides may further contain zirconium, such as oxides containing hafnium and zirconium (hafnium zirconium oxide). Metal oxides with an amorphous structure have dangling bonds in some oxygen atoms, which enhance their ability to capture or adhering hydrogen. Therefore, these metal oxides preferably have an amorphous structure. For example, an amorphous structure may be achieved by including silicon in these oxides. For example, it is preferable to use an oxide containing hafnium and silicon (hafnium silicate). Metal oxides may have crystalline regions and / or grain boundaries in some regions.

[0124] The ability to capture or fix a corresponding substance can also be said to have the property of making it difficult for the corresponding substance to diffuse. Therefore, the ability to capture or fix a corresponding substance can be rephrased as barrier properties.

[0125] Examples of materials for the insulating film having a barrier property against hydrogen include aluminum oxide, magnesium oxide, hafnium oxide, zirconium oxide, hafnium aluminate, hafnium zirconium oxide, silicon nitride, silicon nitride oxide, and gallium oxide films.

[0126] The inorganic insulating layers exemplified as insulating films having a function of capturing or fixing hydrogen and insulating layers having a function of suppressing hydrogen permeation also have oxygen barrier properties. Examples of materials for insulating layers having oxygen barrier properties include oxides containing one or both of aluminum and hafnium, magnesium oxide, gallium zinc oxide, silicon nitride, and silicon nitride oxide. Examples of oxides containing one or both of aluminum and hafnium include aluminum oxide, hafnium oxide, hafnium aluminate, and hafnium silicate.

[0127] [Insulating Layer] The insulating layers used for the insulating layer 101, the insulating layer 103, the insulating layer 104, the insulating layer 105, the insulating layer 106, the insulating layer 111, the insulating layer 112, and the like can be used as interlayer insulating films. For example, they are preferably formed by a film formation method such as an ALD method, a sputtering method, or a plasma CVD method. The ALD method is preferably used for forming a barrier film because it can form a film with good coverage on the surface to be formed. Furthermore, the sputtering method does not require the use of hydrogen gas as a film formation gas, and therefore can form a film with an extremely low hydrogen content. Therefore, the supply of hydrogen to the semiconductor layer 108 can be suppressed, and the electrical characteristics of the semiconductor device can be stabilized.

[0128] The insulating layers used for the insulating layers 101, 103, 104, 105, 106, 111, 112, and the like preferably have a low dielectric constant. By using a material with a low dielectric constant as an interlayer insulating film, the parasitic capacitance generated between wirings can be reduced. For example, it is preferable to use one or more of silicon oxide, silicon oxynitride, silicon oxide to which fluorine has been added, silicon oxide to which carbon has been added, silicon oxide to which carbon and nitrogen have been added, and silicon oxide having vacancies. Silicon oxide and silicon oxynitride are preferable because they are thermally stable.

[0129] The insulating layers used for the insulating layer 101, insulating layer 103, insulating layer 104, insulating layer 105, insulating layer 106, insulating layer 111, insulating layer 112, etc. function as interlayer insulating layers, and therefore, it is preferable to use a film formation method that allows film formation at a high film formation rate compared to other insulating layers. For example, the insulating layers used for the insulating layer 105, insulating layer 112, etc. are made of TEOS (Tetra-Ethyl-Ortho-Silicate, chemical formula: Si(OC ２ H ５ ) ４ Alternatively, a silicon oxide film formed by plasma CVD using a silicon dioxide film containing SiO 2 may be used. This can improve productivity.

[0130] For the insulating layers used in the insulating layer 101, the insulating layer 103, the insulating layer 104, the insulating layer 105, the insulating layer 106, the insulating layer 111, the insulating layer 112, and the like included in the semiconductor device, an insulating film having a function of suppressing permeation of impurities such as water and hydrogen and oxygen, an insulating film having a function of capturing or fixing hydrogen, an insulating film having a barrier property against hydrogen, or an insulating layer having a barrier property against oxygen is preferably used. By using these insulating layers, diffusion of hydrogen into the semiconductor layer 108 can be suppressed. Furthermore, oxidation of the conductive layer 102, the conductive layer 107, and the conductive layer 110 can be suppressed.

[0131] For example, one or both of silicon nitride oxide and silicon nitride may be used in insulating layers such as the insulating layer 101, the insulating layer 103, the insulating layer 104, the insulating layer 105, the insulating layer 106, the insulating layer 111, and the insulating layer 112 of the semiconductor device to surround the transistor 100A. This can suppress diffusion of hydrogen into the transistor 100A, thereby providing a highly reliable transistor.

[0132] 3A to 6C , an example of a manufacturing method of a semiconductor device according to one embodiment of the present invention will be described. In the drawings illustrating an example of a manufacturing method of a semiconductor device, A in each drawing is a plan view. B in each drawing is a cross-sectional view taken along dashed line A1-A2 in A in each drawing. C in each drawing is a cross-sectional view taken along dashed line B1-B2 in A in each drawing.

[0133] Thin films (insulating films, semiconductor films, conductive films, etc.) constituting semiconductor devices can be formed using sputtering, chemical vapor deposition (CVD), vacuum evaporation, pulsed laser deposition (PLD), atomic layer deposition (ALD), etc. Examples of CVD methods include plasma enhanced chemical vapor deposition (PECVD), thermal CVD, and photo CVD. Other methods include metal organic chemical vapor deposition (MOCVD) and metal chemical vapor deposition (metal CVD).

[0134] Furthermore, thin films (insulating films, semiconductor films, conductive films, etc.) constituting the semiconductor device can be formed by methods such as spin coating, dipping, spray coating, inkjet, dispensing, screen printing, offset printing, slit coating, roll coating, curtain coating, etc.

[0135] The thin film constituting the semiconductor device can be processed using a photolithography method or the like. Alternatively, the thin film may be processed using a nanoimprint method, a lift-off method or the like. Alternatively, the island-shaped thin film may be directly formed by a film formation method using a shielding mask such as a metal mask.

[0136] There are two typical photolithography methods: one is to form a resist mask on the thin film to be processed, process the thin film by etching or the like, and then remove the resist mask; the other is to form a photosensitive thin film, and then process the thin film into the desired shape by exposure and development.

[0137] For the etching, a dry etching method, a wet etching method, or the like can be used.

[0138] First, an insulating layer 101 is formed on a substrate (not shown) (FIGS. 3A to 3C). For example, an inorganic insulating film such as silicon oxide, silicon nitride, silicon oxynitride, or silicon nitride oxide can be used as the insulating layer 101. For example, a sputtering method, a CVD method, or an ALD method can be used to form the insulating layer 101. If the top surface of the insulating layer 101 is not flat, a planarization treatment may be performed after the insulating layer 101 is formed so that the top surface of the insulating layer 101 becomes flat. For example, a chemical mechanical polishing (CMP) method can be used as the planarization treatment.

[0139] Films to be the conductive layers 102 (conductive layer 102_1, conductive layer 102_2, and conductive layer 102_3) are deposited over the insulating layer 101. The conductive layers 102 are formed by processing the films to be the conductive layers 102. The conductive layers 102 can be formed by a sputtering method, a metal CVD method, an MOCVD method, an ALD method, or the like. For example, titanium nitride formed by a metal CVD method for the conductive layer 102_1, tungsten formed by a metal CVD method for the conductive layer 102_2, and a conductive oxide formed by a sputtering method for the conductive layer 102_3 can be used as the conductive layer 102. Alternatively, for example, titanium nitride formed by a sputtering method for the conductive layer 102_1, tungsten formed by a sputtering method for the conductive layer 102_2, and a conductive oxide film formed by a sputtering method for the conductive layer 102_3 can be used as the conductive layer 102. Note that ITO, ITSO, or the like can be used as the conductive oxide film. A dry etching method is preferably used to process the conductive layer 102. For example, a mask (not shown) is formed on a film that will become the conductive layer 102 in a region that will become the conductive layer 102, and the film that will become the conductive layer 102 in a region where the mask is not formed is removed by etching. Anisotropic dry etching is preferably used for this etching process. The mask is removed after the etching process. While FIGS. 3B and 3C show an example in which the side surface of the conductive layer 102 is perpendicular to the surface on which the conductive layer 102 is formed, the side surface of the conductive layer 102 may have a tapered shape that is inclined with respect to the surface on which the conductive layer 102 is formed, depending on the etching conditions.

[0140] The insulating layer 103 is formed over the conductive layer 102 so as to cover the conductive layer 102. The insulating layer 103 can be formed by a deposition method such as an ALD method, a sputtering method, or a CVD method. For the insulating layer 103, for example, silicon nitride formed by an ALD method can be used. For the insulating layer 103, it is preferable to use an insulating film having a function of capturing or fixing hydrogen, an insulating film having a function of suppressing permeation of impurities such as water and hydrogen and oxygen, an insulating film having a barrier property against hydrogen, or an insulating film having a barrier property against oxygen.

[0141] An insulating layer 104 is formed over the insulating layer 103. The insulating layer 104 can be formed by a deposition method such as a sputtering method, an ALD method, or a CVD method. For example, silicon nitride deposited by a sputtering method can be used for the insulating layer 104. For the insulating layer 104, an insulating film having a function of capturing or adhering hydrogen, an insulating film having a function of suppressing the permeation of impurities such as water and hydrogen and oxygen, an insulating film having a barrier property against hydrogen, or an insulating film having a barrier property against oxygen is preferably used. Furthermore, the insulating layer 104 is preferably subjected to planarization treatment. For example, a CMP method can be used as the planarization treatment.

[0142] The insulating layer 105 is formed over the insulating layer 104. The insulating layer 105 can be formed using silicon nitride, silicon oxide, silicon nitride oxide, silicon oxynitride, or the like by a sputtering method, a CVD method, or an ALD method. For example, silicon oxide formed by a sputtering method can be used for the insulating layer 105. The insulating layer 105 is preferably formed using a film formed by a sputtering method in which hydrogen is not contained in a deposition gas. Furthermore, it is preferable to perform heat treatment after the insulating layer 105 is formed to reduce hydrogen in the insulating layer 105.

[0143] The heat treatment is preferably performed at a temperature of 250° C. or higher and 650° C. or lower, preferably 300° C. or higher and 500° C. or lower, more preferably 320° C. or higher and 450° C. or lower. Note that the heat treatment is performed in a nitrogen gas or inert gas atmosphere, or an atmosphere containing an oxidizing gas at 10 ppm or higher, 1% or higher, or 10% or higher. For example, when the heat treatment is performed in a mixed atmosphere of nitrogen gas and oxygen gas, the oxygen gas concentration is preferably about 20%. The heat treatment may be performed under reduced pressure. Alternatively, the heat treatment may be performed in an atmosphere containing an oxidizing gas at 10 ppm or higher, 1% or higher, or 10% or higher to compensate for desorbed oxygen after the heat treatment in the nitrogen gas or inert gas atmosphere. By performing the above-described heat treatment, impurities such as water and hydrogen contained in the insulating layer 105 or the like can be reduced before the formation of the oxide semiconductor layer to be the semiconductor layer.

[0144] The gas used in the heat treatment is preferably highly purified. For example, the amount of moisture contained in the gas used in the heat treatment is set to 1 ppb or less, preferably 0.1 ppb or less, and more preferably 0.05 ppb or less. By performing the heat treatment using a highly purified gas, moisture and the like can be prevented from being introduced into the insulating layer 105 and the like as much as possible.

[0145] The apparatus used for the heat treatment is not particularly limited, and may be an apparatus that heats the workpiece by thermal conduction or thermal radiation from a heating element such as a resistance heating element. For example, an electric furnace or an RTA (Rapid Thermal Anneal) apparatus such as an LRTA (Lamp Rapid Thermal Anneal) apparatus or a GRTA (Gas Rapid Thermal Anneal) apparatus can be used. The LRTA apparatus heats the workpiece by radiation of light (electromagnetic waves) emitted from a lamp such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high-pressure sodium lamp, or a high-pressure mercury lamp. The GRTA apparatus is an apparatus that performs heat treatment using high-temperature gas.

[0146] Alternatively, treatment can be performed to supply oxygen to the insulating layer 105. When oxygen is supplied to the insulating layer 105, oxygen can be supplied from the insulating layer 105 to the semiconductor layer 108 by heat or the like applied after the semiconductor layer 108 is formed.

[0147] Examples of treatment for supplying oxygen include heat treatment in an oxygen-containing atmosphere and plasma treatment (including microwave plasma treatment) in an oxygen-containing atmosphere. Alternatively, oxygen may be supplied to the insulating layer 105 by depositing an oxide film (preferably a metal oxide film) by a sputtering method in an oxygen-containing atmosphere. The deposited oxide film is preferably removed immediately after deposition. Note that the oxygen-containing atmosphere may be oxygen gas (O ２ ) as well as ozone (O ３ ) or nitrous oxide (N ２ The atmosphere includes a gas containing a compound gas containing oxygen such as oxygen (O). The substrate temperature during the plasma treatment is set to be equal to or higher than room temperature (25° C.) and equal to or lower than 450° C.

[0148] An insulating layer 106 is formed over the insulating layer 105. The insulating layer 106 can be formed by a deposition method such as a sputtering method, an ALD method, or a CVD method. For example, silicon nitride formed by a sputtering method can be used for the insulating layer 106. For the insulating layer 106, an insulating film having a function of capturing or adhering hydrogen, an insulating film having a function of suppressing permeation of impurities such as water and hydrogen and oxygen, an insulating film having a barrier property against hydrogen, or an insulating film having a barrier property against oxygen is preferably used.

[0149] Films to be the conductive layers 107 (conductive layers 107_1 and 107_2) are deposited over the insulating layer 106. The conductive layers 107 can be formed by a sputtering method, a metal CVD method, an MOCVD method, an ALD method, or the like. For example, tungsten deposited by sputtering can be used as the conductive layer 107_1, and a conductive oxide deposited by sputtering can be used as the conductive layer 107_2. Note that the conductive oxide film can be made of ITO, ITSO, or the like.

[0150] An opening 190 is formed. A mask (not shown) is formed on the conductive layer 107 in a region other than the region that will become the opening 190, and the conductive layer 107, the insulating layer 106, the insulating layer 105, the insulating layer 104, the insulating layer 103, and a part of the conductive layer 102 in the region where the mask is not formed are removed by etching. Anisotropic dry etching is preferably used for this etching process. After the etching process, the mask is removed. A region of the conductive layer 102 that overlaps with the opening 190 is preferably formed into a recessed shape. Note that the side surface of the opening 190 is preferably processed so as to be perpendicular or approximately perpendicular to the surface on which the conductive layer 107 is to be formed. Note that, depending on the processing conditions, the side surface of the opening 190 may be processed so as to have a slope with respect to the direction perpendicular to the surface on which the conductive layer 107 is to be formed.

[0151] A semiconductor layer 108f that will become the semiconductor layer 108 is deposited (FIGS. 4A to 4C). The semiconductor layer 108f is deposited so as to cover at least a portion of the conductive layer 107 and at least a portion of the opening 190. Within the opening 190, the semiconductor layer 108f has a region in contact with a side surface of the insulating layer 103, a region in contact with a side surface of the insulating layer 104, a region in contact with a side surface of the insulating layer 105, a region in contact with a side surface of the insulating layer 106, a region in contact with a side surface of the conductive layer 107, and a region in contact with a recess in the conductive layer 102.

[0152] The semiconductor layer 108f can be formed using a metal oxide (oxide semiconductor) exhibiting semiconductor properties. The semiconductor layer 108f can be formed by a film formation method such as an ALD method or a sputtering method. When the semiconductor layer 108f has a stacked structure, different film formation methods can be used for each layer. Furthermore, metal oxides with different compositions can be used for each layer. The semiconductor layer 108f can have, for example, a stacked structure of an IGZO film formed by ALD on gallium oxide formed by ALD, and an IGZO film formed by sputtering on the IGZO film. Alternatively, the semiconductor layer 108f can have a stacked structure of an indium oxide film formed by ALD, and an IGZO film formed by sputtering on the indium oxide film. Alternatively, the semiconductor layer 108f can have a stacked structure of an IGZO film formed by ALD on an IGZO film formed by sputtering.

[0153] The indium oxide used in the semiconductor layer 108f has a grain boundary extension length of 0 nm, which will be described later, and oxygen is 2×10 ２０ atoms / cm ３ or more, or 3 x 10 ２０ atoms / cm ３ Indium oxide, which is suggested to have the property of transmitting 1×10 or more, can be used. In addition, in a heat treatment in which the extension length of the grain boundary described below is 1000 nm, the heating temperature is 400° C., and the treatment time is 8 hours, ２１ atoms / cm ３ or less, or 8 x 10 ２０ atoms / cm ３Indium oxide, which is suggested to have the following oxygen permeability properties, can be used.

[0154] Indium oxide used in the semiconductor layer 108f has a grain boundary extension length of 0 nm, which will be described later, and a deuterium diffusion integral of 5×10 in a heat treatment at a heating temperature of 200° C. for 8 hours. １２ atoms / cm ２ or more, or 1 x 10 １３ atoms / cm ２ Indium oxide, which is suggested to have the property of transmitting more than 1000 nm of grain boundary extension length described later, is used in a heat treatment at a heating temperature of 200° C. for 8 hours, and the integral value of the deuterium diffusion amount is 1×10 １４ atoms / cm ２ or less, or 8 x 10 １３ atoms / cm ２ Indium oxide, which is suggested to have the following hydrogen permeability properties, can be used.

[0155] Indium oxide used for the semiconductor layer 108f is preferably highly purified. Specifically, the Al concentration in the indium oxide film is 3.0×10 １５ atoms / cm ３ The Ga concentration in the indium oxide film is preferably 4.0×10 or less. １５ atoms / cm ３ It is preferable that:

[0156] The thickness of the semiconductor layer 108f is preferably 1 nm to 50 nm, more preferably 2.5 nm to 30 nm, still more preferably 2.5 nm to 20 nm, still more preferably 5 nm to 20 nm, and even more preferably 5 nm to 10 nm. Note that the semiconductor layer 108f may have a region with the above thickness in at least a portion thereof. For example, the channel formation region of the semiconductor layer 108f may have a region with the above thickness. Setting the thickness of the semiconductor layer 108f within the above range can improve the crystallinity of the semiconductor layer 108f. By improving the crystallinity of the semiconductor layer 108f, the semiconductor layer 108f may have crystal grains.

[0157] The extension length of the grain boundary in the indium oxide film is preferably 0 nm or more and 1500 nm or less, more preferably 0 nm or more and 1000 nm or less, and even more preferably 0 nm or more and 800 nm or less.

[0158] After the metal oxide film is formed, it is preferable to perform a treatment to enhance the crystallinity of the metal oxide film. Examples of treatments to enhance the crystallinity of the metal oxide film include heat treatment, plasma treatment, microwave (typically 2.45 GHz) treatment, microwave plasma treatment, and light (e.g., ultraviolet light) irradiation treatment. Note that a plurality of these treatments may be performed simultaneously or sequentially. For example, heat treatment and microwave plasma treatment may be performed simultaneously. Alternatively, microwave plasma treatment may be performed after heat treatment.

[0159] Furthermore, it is more preferable to perform the treatment for increasing the crystallinity of the metal oxide film multiple times. For example, when forming a metal oxide film by the ALD method, it is preferable to perform a microwave plasma treatment after each atomic layer is formed. Alternatively, it is preferable to perform a treatment for increasing the crystallinity after each metal oxide film having a thickness within a predetermined range is formed, which can improve productivity. Specifically, it is preferable to form a first metal oxide film having a thickness of 1 nm to 10 nm, perform the first microwave plasma treatment, and then form a second metal oxide film having a thickness of 1 nm to 10 nm, and perform the second microwave plasma treatment.

[0160] Furthermore, a treatment for increasing the crystallinity of a metal oxide film may be performed after the metal oxide film is formed. Specifically, the treatment may be performed directly on the formed metal oxide film, or may be performed through another film, such as an insulating film, formed on the metal oxide film. For example, a microwave plasma treatment may be performed after the metal oxide film is formed, or an insulating film (e.g., a silicon nitride film, a silicon oxide film, an aluminum oxide film, etc.) may be formed after the metal oxide film is formed, and then a heat treatment or a microwave plasma treatment may be performed on the metal oxide film through the insulating film.

[0161] The treatment for increasing the crystallinity of a metal oxide film can also serve as a treatment for removing impurities contained in the metal oxide film. For example, carbon, hydrogen, nitrogen, and the like contained in the metal oxide film can be preferably removed. Alternatively, by performing the treatment for increasing the crystallinity of a metal oxide film in an oxygen gas atmosphere, oxygen vacancies in the metal oxide film can be reduced.

[0162] By increasing the crystallinity of the metal oxide film, a highly reliable transistor can be realized.

[0163] The temperature of the heat treatment on the semiconductor layer 108f is preferably 100° C. to 950° C., more preferably 250° C. to 650° C., and further preferably 350° C. to 450° C. For details of the heat treatment, refer to the above description.

[0164] Furthermore, since the indium oxide film that can be used for the semiconductor layer 108f is a film through which one or both of hydrogen and oxygen can easily move, it can be said that by performing heat treatment, excess oxygen or excess hydrogen, which can become carriers or fixed charges, is less likely to accumulate in the semiconductor layer 108, and therefore, a transistor with favorable electrical characteristics and reliability can be obtained.

[0165] In addition, it is preferable that the gas used in the heat treatment be highly purified. By performing the heat treatment using a highly purified gas, it is possible to prevent moisture and the like from being taken into the semiconductor layer 108f as much as possible. Alternatively, it is possible to reduce impurities such as carbon and hydrogen from the semiconductor layer 108f and thereby to highly purify the semiconductor layer 108f.

[0166] The metal oxide film can be formed by, for example, a sputtering method using a metal oxide target.

[0167] The metal oxide film is preferably a dense film with as few defects as possible. Furthermore, the metal oxide film is preferably a high-purity film with as few impurities as possible, such as hydrogen and water, as reduced as possible. In particular, it is preferable to use a crystalline metal oxide film as the metal oxide film.

[0168] Furthermore, when forming a metal oxide film, oxygen gas may be mixed with an inert gas (e.g., helium gas, argon gas, xenon gas, etc.). Note that the higher the ratio of oxygen gas to the total deposition gas when forming the metal oxide film (hereinafter also referred to as the oxygen flow ratio), the higher the crystallinity of the metal oxide film can be, and a highly reliable transistor can be realized. On the other hand, the lower the oxygen flow ratio, the lower the crystallinity of the metal oxide film can be, and a transistor with a higher on-state current can be obtained.

[0169] When forming a metal oxide film, the higher the substrate temperature, the higher the crystallinity and density of the metal oxide film, whereas the lower the substrate temperature, the lower the crystallinity and electrical conductivity of the metal oxide film.

[0170] When the ALD method is used, it is preferable to use a film formation method such as a thermal ALD method or a PEALD method. The thermal ALD method is preferable because it exhibits extremely high step coverage. The PEALD method is also preferable because it exhibits high step coverage and allows low-temperature film formation.

[0171] In the ALD method, a film of any composition can be formed by using multiple different precursors. When multiple different precursors are introduced, a film of any composition can be formed by controlling the number of cycles of each precursor.

[0172] For example, when a metal oxide is used for the semiconductor layer 108f, the semiconductor layer 108f can be formed by an ALD method using a precursor containing a constituent metal element and an oxidizing agent.

[0173] For example, when forming an In—Ga—Zn oxide film, three precursors, i.e., a precursor containing indium, a precursor containing gallium, and a precursor containing zinc, and ozone, oxygen, water, etc., can be used as oxidizers. Alternatively, two precursors, i.e., a precursor containing indium and a precursor containing gallium and zinc, and ozone, oxygen, water, etc., can be used as oxidizers.

[0174] For example, when forming an indium oxide film, a precursor containing indium and ozone, oxygen, water, or the like can be used as an oxidizing agent.

[0175] Examples of precursors that can be used include triethylindium (TEI), tris(2,2,6,6-tetramethyl-3,5-heptanedionate)indium, cyclopentadienyl indium, indium(III) chloride, and (3-(dimethylamino)propyl)dimethyl indium.

[0176] Furthermore, examples of precursors that can be used that contain gallium include trimethylgallium, triethylgallium, tris(dimethylamido)gallium(III), gallium(III) acetylacetonate, tris(2,2,6,6-tetramethyl-3,5-heptanedionate)gallium, dimethylchlorogallium, diethylchlorogallium, and gallium(III) chloride.

[0177] Furthermore, as a precursor containing zinc, dimethyl zinc, diethyl zinc, zinc bis(2,2,6,6-tetramethyl-3,5-heptanedionate), zinc chloride, etc. can be used.

[0178] As the oxidizing agent, for example, ozone, oxygen, water, etc. can be used.

[0179] Methods for controlling the composition of the resulting film include adjusting the flow rate ratio of the source gases, the time for which the source gases are flowed, the order in which the source gases are flowed, etc. By adjusting these, it is also possible to form a film whose composition changes continuously. It is also possible to form two or more films with different compositions continuously.

[0180] For example, the indium oxide film used for the semiconductor layer 108f formed by the ALD method can be formed using triethylindium (TEI) as an indium-containing precursor and ozone and oxygen as oxidizing agents. In this case, it is preferable that the time for introducing the mixed gas of ozone and oxygen as the oxidizing agents in one cycle is 9 seconds.

[0181] After the metal oxide film is formed, heat treatment is preferably performed at a temperature of 250° C. to 650° C., preferably 400° C. to 600° C. Note that the heat treatment is performed in a nitrogen gas or inert gas atmosphere, or an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. For example, when the heat treatment is performed in a mixed atmosphere of nitrogen gas and oxygen gas, the oxygen gas concentration is preferably about 20%. The heat treatment may also be performed under reduced pressure. Alternatively, after the heat treatment in the nitrogen gas or inert gas atmosphere, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas to compensate for the desorbed oxygen.

[0182] The gas used in the heat treatment is preferably highly purified. For example, the amount of moisture contained in the gas used in the heat treatment is set to 1 ppb or less, preferably 0.1 ppb or less, and more preferably 0.05 ppb or less. By performing the heat treatment using a highly purified gas, it is possible to prevent moisture and the like from being incorporated into the metal oxide film as much as possible.

[0183] Although the semiconductor layer 108f is shown as a single layer in the drawings, it may have a stacked structure. For example, it may have a two-layer structure formed by the ALD method, a three-layer structure formed by the ALD method, a two-layer structure in which the first layer is formed by the ALD method and the second layer is formed by sputtering, or a three-layer structure in which the first layer is formed by the ALD method, the second layer is formed by sputtering, and the third layer is formed by either the ALD method or sputtering. Alternatively, it may have a three-layer structure in which the first and second layers are formed by the ALD method and the third layer is formed by sputtering. Forming the first layer by the ALD method is preferable because mixing can be suppressed, but it can also be formed by sputtering. For example, it may have a two-layer structure in which the first layer is formed by the sputtering method and the second layer is formed by the ALD method. The semiconductor layer 108f may have a stacked structure of four or more layers.

[0184] For indium oxide used for the semiconductor layer 108f, the description in Embodiment 5 can be referred to.

[0185] The semiconductor layer 108 and the conductive layer 107 are formed by removing portions of the film that will become the semiconductor layer 108f and the conductive layer 107 (FIGS. 5A to 5C). For example, a mask (not shown) is formed on the semiconductor layer 108f in regions that will become the semiconductor layer 108 and the conductive layer 107, and the semiconductor layer 108f and the film that will become the conductive layer 107 in regions where the mask is not formed are removed by etching. Anisotropic dry etching is preferably used for this etching process. The mask is removed after the etching process. Note that FIGS. 5A to 5C show an example in which the semiconductor layer 108 and the conductive layer 107 are etched using the same mask pattern. Forming the semiconductor layer 108 and the conductive layer 107 using the same mask pattern can reduce the number of exposures and improve productivity. On the other hand, the semiconductor layer 108 and the conductive layer 107 can also be etched using different mask patterns. In this case, the degree of freedom in layout design can be improved. 5B and 5C show an example in which the side surfaces of the semiconductor layer 108 and the conductive layer 107 are perpendicular to the surface on which they are formed; however, depending on the etching conditions, the side surfaces of the semiconductor layer 108 and the conductive layer 107 may have a tapered shape inclined with respect to the surface on which they are formed.

[0186] An insulating layer 109 is formed to cover the semiconductor layer 108 (FIGS. 6A to 6C). Typically, the insulating layer 109 is preferably formed by an ALD method, which has higher step coverage than other film formation methods.

[0187] A film to be the conductive layer 110 is formed over the insulating layer 109. The film to be the conductive layer 110 is preferably formed by, for example, a metal CVD method, an MOCVD method, an ALD method, a sputtering method, or the like. For example, titanium nitride formed by a metal CVD method as the conductive layer 110_1 and tungsten formed by a metal CVD method as the conductive layer 110_2 can be used as the conductive layer 110. A dry etching method is preferably used to process the conductive layer 110. For example, a mask (not shown) is formed on the film to be the conductive layer 110 in a region to be the conductive layer 110, and the film to be the conductive layer 110 in a region where the mask is not formed is removed by etching. Anisotropic dry etching is preferably used for the etching process. The mask is removed after the etching process.

[0188] The insulating layer 111 is formed over the insulating layer 109 and the conductive layer 110. The insulating layer 111 can be formed by a film formation method such as a sputtering method, an ALD method, or a CVD method. For the insulating layer 111, for example, silicon nitride formed by an ALD method can be used. For the insulating layer 111, it is preferable to use an insulating film having a function of capturing or adhering hydrogen, an insulating film having a function of suppressing permeation of impurities such as water and hydrogen and oxygen, an insulating film having a barrier property against hydrogen, or an insulating film having a barrier property against oxygen.

[0189] The insulating layer 112 is formed over the insulating layer 111. The insulating layer 112 can be formed using silicon nitride, silicon oxide, silicon nitride oxide, silicon oxynitride, or the like by a sputtering method, a CVD method, or an ALD method. The insulating layer 112 can be formed using, for example, silicon oxide by a sputtering method. The insulating layer 112 is preferably formed using a film formed by a sputtering method that does not contain hydrogen in the deposition gas. After the insulating layer 112 is formed, planarization treatment is performed to planarize the insulating layer 112. For example, CMP can be used as the planarization treatment.

[0190] 1A to 1D can be manufactured by the above steps. By using such a manufacturing method, a transistor that can be miniaturized can be provided. Alternatively, a transistor that occupies a small area can be provided. Alternatively, a transistor that has high reliability can be provided.

[0191] For example, when a +GBT stress test is performed in a dark room under stress conditions of a substrate temperature of 125° C., a gate-source voltage Vgs of +1.98 V, and a drain-source voltage Vds of 0 V, a transistor can be obtained in which the absolute value of the change in Vsh, |ΔVsh|, calculated from Id-Vg measurements before and after 1000 hours has elapsed is within 200 mV. Furthermore, a transistor can be obtained in which the change in subthreshold swing (S.S.) with respect to temperature is 30 mV / dec or less in the range of −20° C. to 110° C. Furthermore, a transistor can be obtained in which the change in Vsh with respect to temperature is −0.3 V or less in the range of −20° C. to 110° C.

[0192] 7A to 8D , examples of the structure of a transistor that is partially different from the structure of the transistor 100A will be described. Note that descriptions of parts that overlap with those described above will be omitted, and only differences will be described. Furthermore, even if components differ in position or shape, if their functions are the same, they may be denoted by the same reference numerals and descriptions thereof may be omitted. Note that the semiconductor device shown in FIGS. 7A to 8D can be manufactured using the method described in the above-described [Manufacturing Method Example].

[0193] 1A to 1D illustrate a transistor provided with an insulating layer 104, but the configurations shown in FIGS. 7A to 7D may also be used. FIGS. 7A to 7D illustrate an example of a semiconductor device including a transistor 100B. FIG. 7A is a plan view of a semiconductor device including the transistor 100B. FIG. 7B is a cross-sectional view taken along dash-dotted line A1-A2 in FIG. 7A . FIG. 7C is a cross-sectional view taken along dash-dotted line B1-B2 in FIG. 7A . FIG. 7D is a horizontal cross-sectional view taken along dash-dotted line C1-C2 in FIG. 7B . In the transistor 100B shown in FIG. 7 , an insulating layer 105 is provided over and in contact with the insulating layer 103. The insulating layer 105 preferably has a flat top surface. The top surface of the insulating layer 105 can be planarized by CMP treatment after the insulating layer 105 is formed. This can eliminate the need for a step of forming the insulating layer 104, thereby improving productivity.

[0194] 8A to 8D show an example of a semiconductor device including a transistor 100C. Fig. 8A is a plan view of the semiconductor device including the transistor 100C. Fig. 8B is a cross-sectional view taken along dashed dotted line A1-A2 in Fig. 8A. Fig. 8C is a cross-sectional view taken along dashed dotted line B1-B2 in Fig. 8A. Fig. 8D is a horizontal cross-sectional view taken along dashed dotted line C1-C2 in Fig. 8B.

[0195] The conductive layer 801 functions as a gate wiring. The conductive layer 801 can be formed using any of the materials described in the above section [Conductive Layer]. For example, a high-melting-point material such as tungsten or molybdenum, which has both heat resistance and conductivity, can be used for the conductive layer 801. Alternatively, a low-resistance conductive material such as aluminum or copper can be used. By using a low-resistance conductive material, the wiring resistance can be reduced.

[0196] 8B and 8C , insulating layer 111 is provided so as to be located on insulating layer 109. Insulating layer 112 is provided so as to be located on insulating layer 111. Opening 890 is provided in insulating layer 112. At least a portion of opening 890 is provided above opening 190 at a position overlapping opening 190. Insulating layer 111 is provided so as to be in contact with the side surface of opening 890.

[0197] The conductive layer 110 has a portion located inside the opening 190 and an opening 890. An example in which both the conductive layer 110_1 and the conductive layer 110_2 are provided in the opening 190 is shown in FIGS. 8A to 8D. Note that when the widths of the openings 190 and 890 are small, only the conductive layer 110_1 may be provided in the opening 190, and the conductive layer 110_1 and the conductive layer 110_2 may be provided in the opening 890. Alternatively, only the conductive layer 110_1 may be provided in the opening 890.

[0198] The portion of the conductive layer 801 that does not overlap with the opening 890 is mainly located on the insulating layer 112. Therefore, the conductive layer 801 mainly overlaps with the conductive layer 107 via the insulating layer 112 and the insulating layer 111. This allows the physical distance between the conductive layer 801 and the conductive layer 107 to be increased, and the parasitic capacitance generated between the conductive layer 801 and the conductive layer 107 to be reduced.

[0199] The transistor 100C has a structure in which parasitic capacitance generated between the other of the source electrode and the drain electrode and the gate wiring is reduced, thereby improving the frequency characteristics of a circuit including the transistor.

[0200] In this embodiment, an example in which the opening 890 is circular in plan view has been shown, but the present invention is not limited to this. Shapes that can be applied to the opening 890 are the same as the shapes that can be applied to the opening 190 described above.

[0201] This embodiment can be implemented by appropriately combining at least a part of it with other embodiments described in this specification. In addition, when multiple configuration examples are shown in one embodiment in this specification, the configuration examples can be appropriately combined.

[0202] (Embodiment 2) <Structure Example 1 of Memory Device> In this embodiment, a memory device of one embodiment of the present invention will be described with reference to FIGS. 9A to 10 . The memory device of one embodiment of the present invention includes a memory cell. The memory cell includes a transistor and a capacitor. The transistor described in Embodiment 1 can be used as the transistor. Since the description of the transistor in Embodiment 1 can be referred to, detailed description thereof will be omitted.

[0203] 9A to 9C, the configuration of a semiconductor device having a memory cell 999 will be described. Fig. 9A is a plan view of a recording device having a memory cell 999. Fig. 9B is a cross-sectional view taken along dashed line A1-A2 in Fig. 9A. Fig. 9C is a cross-sectional view taken along dashed line B1-B2 in Fig. 9A.

[0204] 9A to 9C includes a memory cell 999 on a substrate (not shown). The memory cell 999 includes at least a capacitor 900 and a transistor 100A.

[0205] 9A to 9C includes an insulating layer 901, an insulating layer 902, an insulating layer 903, a conductive layer 904_1, and a conductive layer 904_2 over a substrate (not shown), and a capacitor 900 over the conductive layer 904. The capacitor 900 includes a conductive layer 909, an insulating layer 910, and a conductive layer 102. The insulating layer 910 is provided between the conductive layer 909 and the conductive layer 102. At least a part of the conductive layer 909 functions as one of a pair of electrodes of the capacitor. At least a part of the conductive layer 102 functions as the other of the pair of electrodes of the capacitor. Note that at least a part of the conductive layer 102 functions as one of the source electrode and the drain electrode of the transistor 100A. At least a part of the insulating layer 910 functions as a dielectric of the capacitor.

[0206] The insulating layer 905, the insulating layer 906, and the insulating layer 907 are provided over the insulating layer 903. The opening 990 is provided in the insulating layer 905, the insulating layer 906, and the insulating layer 907 so as to reach the conductive layer 904. The insulating layer 908 is provided along the inside of the opening 990. The conductive layer 909 has a portion that is provided along the inside of the opening 990 and a portion that is in contact with the conductive layer 904 at the bottom of the opening. Parts of the conductive layer 909, the insulating layer 910, and the conductive layer 102 are provided so as to be located inside the opening 990. The conductive layer 102 is preferably provided so as to fill the opening 990.

[0207] At least a portion of the capacitor element 900 can be provided inside the opening 990, so that the capacitance per unit area in plan view can be increased.

[0208] By providing the capacitor 900 and the transistor 100A stacked one above the other, the area occupied by the memory cell 999 in a plan view can be reduced, and the degree of integration of the memory cell can be improved.

[0209] Furthermore, by configuring the capacitor 900 and the transistor 100A to be stacked vertically, one conductive layer of a pair of electrodes of the capacitor can also serve as one conductive layer of a source electrode or drain electrode of the transistor, thereby simplifying the manufacturing process and improving productivity and yield.

[0210] For insulating layers such as the insulating layer 901, the insulating layer 902, the insulating layer 903, the insulating layer 905, the insulating layer 906, the insulating layer 907, and the insulating layer 908, the materials described in the [Gate insulating film] and [Insulating layer] sections of Embodiment 1 can be used. In particular, for the insulating layers 901, 902, 905, 907, and 908, it is preferable to use an insulating film that has a function of suppressing the permeation of impurities such as water and hydrogen and oxygen, an insulating film that has a function of capturing or fixing hydrogen, an insulating film that has a barrier property against hydrogen, or an insulating film that also has a barrier property against oxygen. Use of these insulating layers can suppress diffusion of hydrogen into the semiconductor layer 108 of the transistor 100A arranged over the capacitor 900. Furthermore, the transistor 100A arranged over the capacitor 900 can have high reliability.

[0211] Conductive layers such as the conductive layer 904 and the conductive layer 909 can be formed as a single layer or a stacked layer using the materials described in the [Conductive Layer] section of Embodiment 1. For example, the conductive layer 904 can have a two-layer structure using titanium nitride for the conductive layer 904_1 and tungsten for the conductive layer 904_2. Since a highly conductive material such as tungsten can be used, the wiring resistance of the conductive layer 904 can be reduced. The conductive layer 904 can also have a three-layer structure including, from the bottom, tantalum nitride, titanium nitride, and tungsten. The conductive layer 909 is preferably formed using a conductive material that is not easily oxidized. The conductive layer 904 can also have a four-layer structure including, from the bottom, tantalum nitride, tantalum, titanium nitride, and tungsten. Alternatively, the conductive layer 904 can have a four-layer structure including, from the bottom, tantalum nitride, tantalum nitride, titanium nitride, and tungsten. For example, the conductive layer 909 is preferably formed using titanium nitride or a conductive oxide such as In—Sn oxide.

[0212] An insulating layer such as the insulating layer 910 can be formed as a single layer or a stacked layer using any of the materials described in the [Gate insulating film] section of Embodiment 1. A high-k material is preferably used for the insulating layer 910. For example, an insulating film (also referred to as ZAZA) in which zirconium oxide, aluminum oxide, zirconium oxide, and aluminum oxide are stacked in this order can be used. By using a high-k material for the insulating layer 910, the thickness of the insulating layer 910 can be increased to a degree that can suppress leakage current and the capacitance of the capacitor 900 can be sufficiently ensured.

[0213] Furthermore, a ferroelectric material may be used for an insulating layer such as the insulating layer 910. For example, a metal oxide containing one or both of hafnium and zirconium can be used as the ferroelectric material. By using a ferroelectric material for the dielectric of the capacitor 900, the memory device described in this embodiment can function as a ferroelectric memory.

[0214] FIG. 10 shows an example of a cross-sectional configuration of a memory device in which a layer having the memory cells 999 shown in FIGS. 9A to 9C is stacked over a layer in which a driver circuit including a sense amplifier is provided.

[0215] 10, a memory cell 999 (a transistor 100A and a capacitor 900) is provided above a Si transistor 1000. The Si transistor 1000 is one of the transistors included in a driver circuit including a sense amplifier.

[0216] The Si transistor 1000 will be described. The Si transistor 1000 is a Fin-type transistor. Fig. 10 shows a schematic cross-sectional view in the channel length direction.

[0217] The Si transistor 1000 is provided on a substrate 1011 and has a conductive layer 1018a that functions as a gate electrode, an insulating layer 1017 that functions as a gate insulating film, a semiconductor region 1013 that functions as a channel formation region, and a low-resistance region 1014 that functions as a source region or a drain region.

[0218] The substrate 1011 may be, for example, a silicon substrate or an SOI (Silicon On Insulator) substrate.

[0219] Next, the semiconductor device shown in FIG. 10 will be described. An element isolation layer 1012, an insulating layer 1015, and dummy gate electrodes 1018b and 1018c are provided on a substrate 1011. The insulating layer 1015 functions as a sidewall. Insulating layers 1016, 1019, 1020, 1021, 1023, and 1025 are also provided, and these insulating layers function as interlayer insulating films. Insulating layers 1019, 1021, and 1025 function as barrier films. Conductive layers 1022 and 1024 function as plugs, electrodes, or wirings.

[0220] One of the source or drain of the Si transistor 1000 (here, the low resistance region 1014) is connected to the memory cell 999 via a conductive layer.

[0221] The insulating layer 1028 , the insulating layer 1029 , and the insulating layer 1031 are provided over the memory cell 999 .

[0222] For insulating layers such as the insulating layer 1028, the insulating layer 1029, and the insulating layer 1031, the materials described in the [Gate insulating film] and [Insulating layer] sections of Embodiment 1 can be used. In particular, for insulating layers such as the insulating layer 1028 and the insulating layer 1031, it is preferable to use an insulating film that has a function of suppressing the permeation of impurities such as water and hydrogen and oxygen, an insulating film that has a function of capturing or fixing hydrogen, an insulating film that has a barrier property against hydrogen, or an insulating film that also has a barrier property against oxygen. By using these insulating films, diffusion of hydrogen into the semiconductor layer 108 of the transistor 100A can be suppressed. Furthermore, the transistor 100A can have high reliability.

[0223] The conductive layers 1030 a , 1030 b , and 1030 c are provided so as to be embedded in the insulating layers 1028 and 1029 .

[0224] Conductive layers such as the conductive layer 1030a, the conductive layer 1030b, and the conductive layer 1030c can be formed as a single layer or a stacked layer using the materials described in [Conductive Layer] in Embodiment 1. For example, the conductive layer 1030 can have a two-layer structure using tungsten over titanium nitride. Since a conductive material with high conductivity such as tungsten can be used, the wiring resistance of the conductive layer 1030 can be reduced. Alternatively, the conductive layer 1030 can have a three-layer structure using titanium nitride over tantalum nitride and tungsten over titanium nitride.

[0225] The conductive layer 1027a is provided to connect the conductive layer 1030a and the conductive layer 904a with the conductive layer 1026 interposed therebetween.

[0226] The conductive layer 1027b is provided to connect the conductive layer 1030b and the conductive layer 110a.

[0227] The conductive layer 1027c is provided to connect the conductive layer 1030c and the conductive layer 107. In addition, for example, when a conductive oxide is used for the conductive layer 107_2 and a material having lower resistance than that is used for the conductive layer 107_1, openings may be provided in the semiconductor layer 108 and the conductive layer 107_2 so that the conductive layer 1027c is in contact with the conductive layer 107_1. With such a structure, the conductive layer 1027c can be in good contact with the conductive layer 107_1.

[0228] The conductive layer 1030a, the conductive layer 1030b, the conductive layer 1030c, the conductive layer 1027a, the conductive layer 1027b, the conductive layer 1027c, and the conductive layer 1026 function as plugs or wirings.

[0229] The conductive layer 1030a, the conductive layer 1030b, and the conductive layer 1030c may be connected to each other. The conductive layer 110a and the conductive layer 110 may be connected to each other.

[0230] <Structure Example 2 of Memory Device> In this embodiment, a memory device of one embodiment of the present invention will be described with reference to FIGS. 11A to 12 . The memory device of one embodiment of the present invention includes a memory cell. The memory cell includes two transistors. The transistor described in Embodiment 1 can be used as the transistor. Since the description of the transistor in Embodiment 1 can be referred to, detailed description thereof will be omitted.

[0231] 11A to 11C, the configuration of a semiconductor device having a memory cell 1199 will be described. Fig. 11A is a plan view of a recording device having a memory cell 1199. Fig. 11B is a cross-sectional view taken along dashed line A1-A2 in Fig. 11A. Fig. 11C is a cross-sectional view taken along dashed line B1-B2 in Fig. 11A.

[0232] 11A to 11C includes a memory cell 1199 on a substrate (not shown). The memory cell 1199 includes at least a transistor 1100A and a transistor 100A over the transistor 1100A.

[0233] For the transistor 1100A, the description of the transistor 100A in Embodiment 1 can be referred to, and detailed description thereof will be omitted. For example, the conductive layer 102 can be read as the conductive layer 1102, the conductive layer 107 can be read as the conductive layer 1107, and the semiconductor layer 108 can be read as the semiconductor layer 1108, and the descriptions in FIGS. 1A to 6C can be referred to. The description of the transistor 100A can also be referred to. The descriptions of the insulating layer 101, the insulating layer 103, the insulating layer 104, the insulating layer 105, and the insulating layer 109 can also be referred to for the insulating layer 1101, the insulating layer 1103, the insulating layer 1104, the insulating layer 1105, the insulating layer 1106, and the insulating layer 1109.

[0234] As shown in FIGS. 11B and 11C , the transistor 100A is provided so as to overlap with the transistor 1100A. Furthermore, an opening 1190 in which part of the structure of the transistor 1100A is provided overlaps with the opening 190 in which part of the structure of the transistor 100A is provided. In particular, the conductive layer 102 functions as one of the source electrode and drain electrode of the transistor 100A and as the gate electrode of the transistor 1100A. Therefore, the transistors 100A and 1100A share part of their structures. This structure can reduce the number of processes and improve productivity. Furthermore, the transistors 1100A and 100A can be provided without significantly increasing the occupied area in a plan view. This reduces the occupied area of ​​the memory cell 1199, allowing the memory cells 1199 to be densely arranged and the storage capacity of the storage device to be increased. In other words, the storage device can be highly integrated.

[0235] The transistors included in the memory cell 1199 are not limited to the combination of the transistor 100A and the transistor 1100A, and one or more of the transistors described in Embodiment 1 can be used.

[0236] In the memory cell 1199 shown in FIGS. 11B and 11C, capacitance generated between the conductive layer 102 and the conductive layer 1107 can be used; therefore, data can be held without forming a separate capacitor.

[0237] FIG. 12 shows an example of a cross-sectional configuration of a memory device in which a layer having the memory cells 1199 shown in FIGS. 11A to 11C is stacked over a layer in which a driver circuit including a sense amplifier is provided.

[0238] 12, a memory cell 1199 (transistor 100A and transistor 1100A) is provided above the Si transistor 1000. The Si transistor 1000 is one of the transistors included in a driver circuit including a sense amplifier.

[0239] The insulating layer 1201 is provided over the insulating layer 1025. The conductive layer 1202 is provided to be embedded in the insulating layer 1201. The conductive layer 1202 has a region in contact with the conductive layer 1102a. The conductive layer 1202 can be formed as a single layer or a stacked layer using the materials described in the [Conductive Layer] section of Embodiment 1. For example, the conductive layer 1202 can have a two-layer structure using tungsten over titanium nitride. Since a highly conductive material such as tungsten can be used, the wiring resistance of the conductive layer 1202 can be reduced. The conductive layer 1202 can also have a three-layer structure including, from the bottom, tantalum nitride, titanium nitride, and tungsten. Alternatively, the conductive layer 1202 can have a four-layer structure including, from the bottom, tantalum nitride, tantalum, titanium nitride, and tungsten. Alternatively, the conductive layer 1202 can have a four-layer structure including, from the bottom, tantalum nitride, tantalum nitride, titanium nitride, and tungsten.

[0240] The insulating layer 1205 , the insulating layer 1206 , and the insulating layer 1208 are provided over the memory cell 1199 .

[0241] For insulating layers such as the insulating layer 1201, the insulating layer 1205, the insulating layer 1206, and the insulating layer 1208, the materials described in the [Gate insulating film] and [Insulating layer] sections of Embodiment 1 can be used. In particular, for insulating layers such as the insulating layer 1205 and the insulating layer 1208, it is preferable to use an insulating film that has a function of suppressing the permeation of impurities such as water and hydrogen and oxygen, an insulating film that has a function of capturing or fixing hydrogen, an insulating film that has a barrier property against hydrogen, or an insulating film that also has a barrier property against oxygen. By using these insulating films, diffusion of hydrogen into the semiconductor layer 108 of the transistor 100A and the semiconductor layer 1108 of the transistor 1100A can be suppressed. Furthermore, the transistor 100A and the transistor 1100A can have high reliability.

[0242] The conductive layers 1207 a , 1207 b , 1207 c , and 1207 d are provided so as to be embedded in the insulating layers 1206 and 1205 .

[0243] Conductive layers such as the conductive layer 1207a, the conductive layer 1207b, the conductive layer 1207c, and the conductive layer 1207d can be formed as a single layer or a stacked layer using the materials described in the [Conductive Layer] section of Embodiment 1. For example, the conductive layer 1207 can have a two-layer structure using tungsten over titanium nitride. Since a highly conductive material such as tungsten can be used, the wiring resistance of the conductive layer 1207 can be reduced. The conductive layer 1207 can also have a three-layer structure of tantalum nitride, titanium nitride, and tungsten from the bottom. The conductive layer 1207 can also have a four-layer structure of tantalum nitride, tantalum, titanium nitride, and tungsten from the bottom. Alternatively, the conductive layer 1207 can have a four-layer structure of tantalum nitride, tantalum nitride, titanium nitride, and tungsten from the bottom.

[0244] The conductive layer 1204a is provided so as to connect the conductive layer 1207a and the conductive layer 1102a through the conductive layer 1203. Furthermore, for example, when a conductive oxide is used for the conductive layer 1102a_3 and a material having lower resistance than that is used for the conductive layers 1102a_2 and 1102a_1, an opening may be provided in the conductive layer 1102a_3 so that the conductive layer 1203 is in contact with the conductive layer 1102a_2. With such a structure, the conductive layer 1203 can be in good contact with the conductive layer 1102a_2. Note that the conductive layer 1102 can be formed in the same process as the conductive layer 1102.

[0245] The conductive layer 1204b is provided to connect the conductive layer 1207b and the conductive layer 1107a. For example, when a conductive oxide is used for the conductive layer 1107a_2 and a material having lower resistance than that is used for the conductive layer 1107a_1, openings may be provided in the semiconductor layer 1108a and the conductive layer 1107a_2 so that the conductive layer 1204b is in contact with the conductive layer 1107a_1. With such a structure, the conductive layer 1204b can be in good contact with the conductive layer 1107a_1.

[0246] The conductive layer 1204c is provided to connect the conductive layer 1207c and the conductive layer 110a.

[0247] The conductive layer 1204d is provided to connect the conductive layer 1207d and the conductive layer 107. For example, when a conductive oxide is used for the conductive layer 107_2 and a material having lower resistance than that is used for the conductive layer 107_1, openings may be provided in the semiconductor layer 108 and the conductive layer 107_2 so that the conductive layer 1204d is in contact with the conductive layer 107_1. With such a structure, the conductive layer 1204d can be in good contact with the conductive layer 107_1.

[0248] The conductive layer 1207a, the conductive layer 1207b, the conductive layer 1207c, the conductive layer 1207d, the conductive layer 1204a, the conductive layer 1204b, the conductive layer 1204c, the conductive layer 1204d, and the conductive layer 1203 function as plugs or wirings.

[0249] The conductive layer 1207a, the conductive layer 1207b, the conductive layer 1207c, and the conductive layer 1207d may be connected to each other. The conductive layer 110a and the conductive layer 110 may be connected to each other.

[0250] This embodiment can be implemented by appropriately combining at least a part of it with other embodiments described in this specification. In addition, when multiple configuration examples are shown in one embodiment in this specification, the configuration examples can be appropriately combined.

[0251] Embodiment 3 In this embodiment, a semiconductor device 1300 according to one embodiment of the present invention will be described. The semiconductor device 1300 can function as a memory device.

[0252] Fig. 13 is a block diagram showing a configuration example of a semiconductor device 1300. The semiconductor device 1300 shown in Fig. 13 includes a driver circuit 1310 and a memory array 1320. The memory array 1320 includes one or more memory cells 1350. Fig. 13 shows an example in which the memory array 1320 includes a plurality of memory cells 1350 arranged in a matrix.

[0253] The memory cell 1350 can be the memory device described in Embodiment 2.

[0254] The driver circuit 1310 includes a PSW 1331 (power switch), a PSW 1332, and a peripheral circuit 1315. The peripheral circuit 1315 includes a peripheral circuit 1311, a control circuit 1312, and a voltage generating circuit 1328.

[0255] In the semiconductor device, each circuit, signal, and voltage can be appropriately selected or omitted as needed. Alternatively, other circuits or signals may be added. The signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are input signals from the outside, and the signal RDA is an output signal to the outside. The signal CLK is a clock signal.

[0256] Furthermore, signals BW, CE, and GW are control signals. Signal CE is a chip enable signal, signal GW is a global write enable signal, and signal BW is a byte write enable signal. Signal ADDR is an address signal. Signal WDA is a write data signal, and signal RDA is a read data signal. Signals PON1 and PON2 are power gating control signals. Note that signals PON1 and PON2 may be generated by the control circuit 1312.

[0257] The control circuit 1312 is a logic circuit having a function of controlling the overall operation of the semiconductor device 1300. For example, the control circuit 1312 performs a logical operation on the signals CE, GW, and BW to determine the operation mode (e.g., write operation, read operation) of the semiconductor device 1300. Alternatively, the control circuit 1312 generates a control signal for the peripheral circuit 1311 so that this operation mode is executed.

[0258] The voltage generating circuit 1328 has a function of generating a negative voltage. The signal WAKE has a function of controlling the input of the signal CLK to the voltage generating circuit 1328. For example, when an H-level signal is given as the signal WAKE, the signal CLK is input to the voltage generating circuit 1328, and the voltage generating circuit 1328 generates a negative voltage.

[0259] The peripheral circuit 1311 is a circuit for writing and reading data to and from the memory cell 1350. The peripheral circuit 1311 includes a row decoder 1341, a column decoder 1342, a row driver 1323, a column driver 1324, an input circuit 1325, an output circuit 1326, and a sense amplifier 1327.

[0260] The row decoder 1341 and the column decoder 1342 have the function of decoding the signal ADDR. The row decoder 1341 is a circuit for specifying a row to be accessed, and the column decoder 1342 is a circuit for specifying a column to be accessed. The row driver 1323 has the function of selecting the row specified by the row decoder 1341. The column driver 1324 has the function of writing data to the memory cell 1350, the function of reading data from the memory cell 1350, the function of holding the read data, etc.

[0261] The input circuit 1325 has a function of holding a signal WDA. The data held by the input circuit 1325 is output to the column driver 1324. The output data of the input circuit 1325 is data (Din) to be written to the memory cell 1350. The data (Dout) read from the memory cell 1350 by the column driver 1324 is output to the output circuit 1326. The output circuit 1326 has a function of holding Dout. In addition, the output circuit 1326 has a function of outputting Dout to the outside of the semiconductor device 1300. The data output from the output circuit 1326 is a signal RDA.

[0262] The PSW 1331 is a V ＤＤ The PSW 1332 has the function of controlling the supply of V to the row driver 1323. ＨＭ Here, the high power supply potential of the semiconductor device 1300 is V ＤＤ and the low power supply potential is GND (ground potential). ＨＭ is the high power supply potential used to drive the word line high, and V ＤＤ The signal PON1 controls the on / off of the PSW 1331, and the signal PON2 controls the on / off of the PSW 1332. In FIG. 13, in the peripheral circuit 1315, V ＤＤAlthough the number of power domains to which power is supplied is set to one, it is also possible to set it to a plurality of power domains. In this case, a power switch may be provided for each power domain.

[0263] 14A to 14G, examples of memory cell configurations that can be applied to the memory cell 1350 will be described.

[0264] 14A shows an example of a circuit configuration of a memory cell of a dynamic random access memory (DRAM). In this specification and the like, a DRAM using an OS transistor is referred to as a dynamic oxide semiconductor random access memory (DOSRAM). The memory cell 1351 includes a transistor M1 and a capacitor CA.

[0265] The transistor M1 may have a front gate (sometimes simply referred to as a gate) and a back gate. In this case, the back gate may be connected to a wiring to which a constant potential or a signal is applied, or the front gate and the back gate may be connected to each other.

[0266] A first terminal of the transistor M1 is connected to a first terminal of the capacitance element CA, a second terminal of the transistor M1 is connected to the wiring BIL, and a gate of the transistor M1 is connected to the wiring WOL. The second terminal of the capacitance element CA is connected to the wiring CAL.

[0267] The wiring BIL functions as a bit line, and the wiring WOL functions as a word line. The wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitance element CA. When writing and reading data, it is preferable to apply a low-level potential (sometimes referred to as a reference potential) to the wiring CAL.

[0268] Data is written and read by applying a high-level potential to the wiring WOL, turning on the transistor M1, and bringing the wiring BIL and the first terminal of the capacitor CA into a conductive state (a state in which current can flow).

[0269] Furthermore, the memory cell that can be used as the memory cell 1350 is not limited to the memory cell 1351, and the circuit configuration can be changed. For example, the memory cell 1351 does not need to include the capacitor CA and the wiring CAL, and the first terminal of the transistor M1 may be in an electrically floating state.

[0270] Note that an OS transistor is preferably used as the transistor M1. An OS transistor has a characteristic of having an extremely small off-state current. By using an OS transistor as the transistor M1, the leakage current of the transistor M1 can be made extremely small. That is, written data can be held by the transistor M1 for a long time, so that the frequency of refreshing the memory cell can be reduced. Alternatively, the refresh operation of the memory cell can be made unnecessary. Furthermore, since the leakage current is extremely small, multi-level data or analog data can be held in the memory cell 1351.

[0271] 14B, one wiring BIL can be provided in common for two or more DRAM memory cells. In FIG. 14B, a first memory cell having a transistor M1 and a capacitor CA1 and a second memory cell having a transistor M2 and a capacitor CA2 are connected to one wiring BIL. Note that the gate of the transistor M1 is connected to a wiring WOL1, and the gate of the transistor M2 is connected to a wiring WOL2. The description of the transistor M1 can be referred to for the transistor M2, the description of the capacitor CA can be referred to for the capacitors CA1 and CA2, and the description of the wiring WOL can be referred to for the wiring WOL1 and WOL2.

[0272] 14C shows an example circuit configuration of a gain cell type memory cell having two transistors and one capacitor. The memory cell 1353 includes a transistor M2, a transistor M3, and a capacitor CB. In this specification and the like, a memory device having a gain cell type memory cell in which the transistor M2 is an OS transistor is referred to as a nonvolatile oxide semiconductor RAM (NOSRAM).

[0273] The first terminal of transistor M2 is connected to the first terminal of capacitance element CB, the second terminal of transistor M2 is connected to wiring WBL, and the gate of transistor M2 is connected to wiring WOL. The second terminal of capacitance element CB is connected to wiring CAL. The first terminal of transistor M3 is connected to wiring RBL, the second terminal of transistor M3 is connected to wiring SL, and the gate of transistor M3 is connected to the first terminal of capacitance element CB.

[0274] The wiring WBL functions as a write bit line, the wiring RBL functions as a read bit line, and the wiring WOL functions as a word line. The wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitance element CB. When writing data, while retaining data, and when reading data, it is preferable to apply a low-level potential (sometimes referred to as a reference potential) to the wiring CAL.

[0275] Data is written by applying a high-level potential to the wiring WOL, turning on the transistor M2, and establishing electrical continuity between the wiring WBL and the first terminal of the capacitor CB. Specifically, when the transistor M2 is on, a potential corresponding to the information to be recorded is applied to the wiring WBL, and the potential is written to the first terminal of the capacitor CB and the gate of the transistor M3. Then, a low-level potential is applied to the wiring WOL, turning off the transistor M2, thereby maintaining the potential of the first terminal of the capacitor CB and the potential of the gate of the transistor M3.

[0276] Data is read by applying a predetermined potential to the wiring SL. The current flowing between the source and drain of the transistor M3 and the potential of the first terminal of the transistor M3 are determined by the potential of the gate of the transistor M3 and the potential of the second terminal of the transistor M3. Therefore, the potential held in the first terminal of the capacitor CB (or the gate of the transistor M3) can be read by reading the potential of the wiring RBL connected to the first terminal of the transistor M3. In other words, information written in this memory cell can be read from the potential held in the first terminal of the capacitor CB (or the gate of the transistor M3).

[0277] Alternatively, for example, the wiring WBL and the wiring RBL may be combined into a single wiring BIL. An example circuit configuration of such a memory cell is shown in FIG. 14D . The memory cell 1354 is configured such that the wiring WBL and the wiring RBL of the memory cell 1353 are combined into a single wiring BIL, and the second terminal of the transistor M2 and the first terminal of the transistor M3 are connected to the wiring BIL. In other words, the memory cell 1354 is configured to operate as a write bit line and a read bit line using a single wiring BIL.

[0278] 14E is an example in which the capacitor element CB and the wiring CAL are omitted from the memory cell 1353. Also, the memory cell 1356 shown in Fig. 14F is an example in which the capacitor element CB and the wiring CAL are omitted from the memory cell 1354. With such a configuration, the integration degree of the memory cells can be increased.

[0279] Note that it is preferable to use an OS transistor for at least the transistor M2. In particular, it is preferable to use OS transistors for the transistors M2 and M3. By using an OS transistor as the transistor M2, written data can be held by the transistor M2 for a long time, which reduces the frequency of refreshing the memory cell. Alternatively, the refresh operation of the memory cell can be eliminated. Furthermore, since the leakage current is extremely small, multi-level data or analog data can be held in the memory cells 1353 to 1356.

[0280] The memory cells 1353 to 1356 in which an OS transistor is used as the transistor M2 are one embodiment of an NOSRAM.

[0281] Note that a Si transistor may be used as the transistor M3. The Si transistor can increase the field effect mobility and can also be used as a p-channel transistor, thereby increasing the degree of freedom in circuit design.

[0282] 14G shows a three-transistor, one-capacitor gain cell type memory cell 1357. The memory cell 1357 includes transistors M4 to M6 and a capacitor CC.

[0283] The first terminal of transistor M4 is connected to the first terminal of capacitor CC, the second terminal of transistor M4 is connected to wiring BIL, and the gate of transistor M4 is connected to wiring WOL. The second terminal of capacitor CC is connected to the first terminal of transistor M5 and wiring GNDL. The second terminal of transistor M5 is connected to the first terminal of transistor M6, and the gate of transistor M5 is connected to the first terminal of capacitor CC. The second terminal of transistor M6 is connected to wiring BIL, and the gate of transistor M6 is connected to wiring RWL.

[0284] The wiring BIL functions as a bit line, the wiring WOL functions as a write word line, and the wiring RWL functions as a read word line. The wiring GNDL is a wiring that applies a low-level potential.

[0285] Data is written by applying a high-level potential to the wiring WOL, turning on the transistor M4, and establishing electrical continuity between the wiring BIL and the first terminal of the capacitor CC. Specifically, when the transistor M4 is on, a potential corresponding to the information to be recorded is applied to the wiring BIL, and the potential is written to the first terminal of the capacitor CC and the gate of the transistor M5. Then, a low-level potential is applied to the wiring WOL, turning off the transistor M4, thereby maintaining the potential of the first terminal of the capacitor CC and the potential of the gate of the transistor M5.

[0286] Data is read by precharging the wiring BIL to a predetermined potential, then electrically floating the wiring BIL, and applying a high-level potential to the wiring RWL. Because the wiring RWL is at a high-level potential, the transistor M6 is turned on, and the wiring BIL and the second terminal of the transistor M5 are electrically connected. At this time, the potential of the wiring BIL is applied to the second terminal of the transistor M5. The potential of the second terminal of the transistor M5 and the potential of the wiring BIL change depending on the potential held in the first terminal of the capacitor CC (or the gate of the transistor M5). By reading the potential of the wiring BIL, the potential held in the first terminal of the capacitor CC (or the gate of the transistor M5) can be read. In other words, information written in this memory cell can be read from the potential held in the first terminal of the capacitor CC (or the gate of the transistor M5).

[0287] Note that at least the transistors M4 to M6 are preferably OS transistors.

[0288] The transistors M5 and M6 may be Si transistors.

[0289] 15A and 15B show perspective views of a semiconductor device 1370A. The semiconductor device 1370A includes a layer 1330 on which a memory array is provided, on an arithmetic device 1360. The layer 1330 includes a memory array 1320L1, a memory array 1320L2, and a memory array 1320L3. The arithmetic device 1360 and each memory array overlap each other. To make the configuration of the semiconductor device 1370A easier to understand, the arithmetic device 1360 and the layer 1330 are shown separately in FIG. 15B. The arithmetic device 1360 may be, for example, a central processing unit (CPU), a graphics processing unit (GPU), or the like.

[0290] By stacking the layer 1330 having the memory array and the arithmetic unit 1360, the connection distance between them can be shortened, thereby increasing the communication speed between them. In addition, the short connection distance can reduce power consumption.

[0291] As a method for stacking the layer 1330 having a memory array and the computing device 1360, a method (also referred to as monolithic stacking) in which the layer 1330 having a memory array is stacked directly on the computing device 1360 may be used, or a method in which the computing device 1360 and the layer 1330 are formed on different substrates, the two substrates are bonded together, and connection is made using a through-via or conductive film bonding technology (such as Cu-Cu bonding) may be used. The former method does not require consideration of misalignment during bonding, and therefore can not only reduce the chip size but also reduce manufacturing costs.

[0292] Here, the arithmetic unit 1360 does not have a cache, and the memory arrays 1320L1, 1320L2, and 1320L3 provided in the layer 1330 can each be used as a cache. In this case, for example, the memory array 1320L1 can be used as an L1 cache (also called a level 1 cache), the memory array 1320L2 can be used as an L2 cache (also called a level 2 cache), and the memory array 1320L3 can be used as an L3 cache (also called a level 3 cache). Of the three memory arrays, the memory array 920L3 has the largest capacity and the lowest access frequency. Furthermore, the memory array 920L1 has the smallest capacity and the highest access frequency.

[0293] When the cache provided in the arithmetic unit 1360 is used as an L1 cache, each memory array provided in the layer 1330 can be used as a lower-level cache or a main memory. The main memory has a larger capacity than the cache and is accessed less frequently.

[0294] 15B, a driving circuit 1310L1, a driving circuit 1310L2, and a driving circuit 1310L3 are provided. The driving circuit 1310L1 is connected to the memory array 1320L1 via a connection electrode 1340L1. Similarly, the driving circuit 1310L2 is connected to the memory array 1320L2 via a connection electrode 1340L2, and the driving circuit 1310L3 is connected to the memory array 1320L3 via a connection electrode 1340L3.

[0295] Although the number of memory arrays functioning as caches is three in this example, the number may be one or two, or four or more.

[0296] When the memory array 1320L1 is used as a cache, the driver 1310L1 may function as part of the cache interface or may be configured to be connected to the cache interface. Similarly, the driver circuits 1310L2 and 1310L3 may also function as part of the cache interface or may be configured to be connected to it.

[0297] 15A and 15B show an example in which one layer 1330 having a memory array is provided on the arithmetic device 1360, but two or more layers 1330 having memory arrays may be provided.

[0298] This embodiment can be implemented by appropriately combining at least a part of it with other embodiments described in this specification. In addition, when multiple configuration examples are shown in one embodiment in this specification, the configuration examples can be appropriately combined.

[0299] In this embodiment, an application example of a semiconductor device according to one embodiment of the present invention will be described. The semiconductor device according to one embodiment of the present invention is suitable for, for example, electronic components, electronic devices, mainframes, space equipment, and data centers because it can provide a transistor with high on-state current and a small area.

[0300] [Electronic Component] FIG. 16A shows a perspective view of a substrate (mounting substrate 1389) on which electronic component 1380 is mounted. Electronic component 1380 shown in FIG. 16A has semiconductor device 1381 inside mold 1384. FIG. 16A omits some details to show the interior of electronic component 1380. Electronic component 1380 has lands 1385 on the outside of mold 1384. Lands 1385 are electrically connected to electrode pads 1386, and electrode pads 1386 are electrically connected to semiconductor device 1381 via wires 1387. Electronic component 1380 is mounted on, for example, a printed circuit board 1388. A plurality of such electronic components are combined and electrically connected on printed circuit board 1388 to complete mounting substrate 1389.

[0301] The semiconductor device 1381 also includes a drive circuit layer 1382 and a memory layer 1383. The memory layer 1383 has a configuration in which multiple memory cell arrays are stacked. The stacked configuration of the drive circuit layer 1382 and the memory layer 1383 can be a monolithic stacked configuration. In a monolithic stacked configuration, the layers can be connected without using through-electrode technology such as TSV (Through Silicon Via) or bonding technology such as Cu-Cu direct bonding. By monolithically stacking the drive circuit layer 1382 and the memory layer 1383, for example, a so-called on-chip memory configuration can be achieved in which the memory is formed directly on the processor. The on-chip memory configuration enables the operation of the interface between the processor and the memory to be faster.

[0302] Furthermore, by configuring an on-chip memory, the size of the connection wiring can be reduced compared to technologies that use through electrodes such as TSVs, and the number of connection pins can be increased. Increasing the number of connection pins enables parallel operation, which makes it possible to improve the memory bandwidth (also called memory bandwidth).

[0303] Furthermore, it is preferable that the memory cell arrays included in the memory layer 1383 are formed using OS transistors and the memory cell arrays are monolithically stacked. By forming the memory cell arrays in a monolithic stacked structure, one or both of the memory bandwidth and the memory access latency can be improved. Note that the bandwidth is the amount of data transferred per unit time, and the access latency is the time from access to the start of data exchange. Note that when Si transistors are used for the memory layer 1383, it is more difficult to form a monolithic stacked structure than OS transistors. Therefore, it can be said that OS transistors have a superior structure to Si transistors in a monolithic stacked structure.

[0304] The semiconductor device 1381 may also be referred to as a die. In this specification, a die refers to a chip piece obtained by forming a circuit pattern on, for example, a disk-shaped substrate (also called a wafer) and cutting it into dices during the semiconductor chip manufacturing process. Semiconductor materials that can be used for the die include, for example, silicon (Si), silicon carbide (SiC), and gallium nitride (GaN). For example, a die obtained from a silicon substrate (also called a silicon wafer) may be called a silicon die.

[0305] 16B shows a perspective view of electronic component 1390. Electronic component 1390 is an example of a SiP (System in Package) or MCM (Multi-Chip Module). Electronic component 1390 has an interposer 1391 provided on a package substrate 1392 (printed circuit board), and a semiconductor device 1394 and a plurality of semiconductor devices 1381 provided on interposer 1391.

[0306] The electronic component 1390 shows an example in which the semiconductor device 1381 is used as a high bandwidth memory (HBM). The semiconductor device 1394 can be used in an integrated circuit such as a CPU, a GPU, or an FPGA (Field Programmable Gate Array).

[0307] For example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate can be used for the package substrate 1392. For example, a silicon interposer or a resin interposer can be used for the interposer 1391.

[0308] The interposer 1391 has multiple wirings and functions to connect multiple integrated circuits with different terminal pitches. The multiple wirings are provided in a single layer or multiple layers. The interposer 1391 also functions to connect the integrated circuits provided on the interposer 1391 to electrodes provided on the package substrate 1392. For these reasons, the interposer is sometimes called a "rewiring substrate" or "intermediate substrate." In some cases, through electrodes are provided in the interposer 1391, and the integrated circuits and the package substrate 1392 are connected using the through electrodes. In addition, in a silicon interposer, TSVs can also be used as through electrodes.

[0309] In an HBM, many wirings must be connected to achieve a wide memory bandwidth. Therefore, the interposer on which the HBM is mounted must have fine and high-density wiring. Therefore, it is preferable to use a silicon interposer for the interposer on which the HBM is mounted.

[0310] Furthermore, in SiPs, MCMs, and the like that use silicon interposers, a decrease in reliability due to differences in the coefficient of expansion between the integrated circuit and the interposer is unlikely to occur. Furthermore, since the silicon interposer has a highly flat surface, poor connection between the integrated circuit mounted on the silicon interposer and the silicon interposer is unlikely to occur. In particular, it is preferable to use silicon interposers in 2.5D packages (2.5-dimensional packaging) in which multiple integrated circuits are arranged horizontally on an interposer.

[0311] On the other hand, when connecting multiple integrated circuits with different terminal pitches using a silicon interposer, a TSV, or the like, a space is required, such as the width of the terminal pitch. Therefore, when attempting to reduce the size of the electronic component 1390, the width of the terminal pitch becomes an issue, and it may be difficult to provide the many wirings necessary to achieve a wide memory bandwidth. Therefore, as described above, a monolithic stacked structure using OS transistors is preferable. A composite structure may be formed by combining a memory cell array stacked using TSVs and a monolithically stacked memory cell array.

[0312] A heat sink (heat dissipation plate) may be provided overlapping the electronic component 1390. When providing a heat sink, it is preferable to align the height of an integrated circuit provided on the interposer 1391. For example, in the electronic component 1390 shown in this embodiment, it is preferable to align the height of the semiconductor device 1381 and the height of the semiconductor device 1394.

[0313] Electrodes 1393 may be provided on the bottom of package substrate 1392 in order to mount electronic component 1390 on another substrate. FIG. 16B shows an example in which electrodes 1393 are formed of solder balls. By providing solder balls in a matrix on the bottom of package substrate 1392, BGA (Ball Grid Array) mounting can be achieved. Electrodes 1393 may also be formed of conductive pins. By providing conductive pins in a matrix on the bottom of package substrate 1392, PGA (Pin Grid Array) mounting can be achieved.

[0314] The electronic component 1390 can be mounted on other substrates using various mounting methods, including, but not limited to, BGA and PGA, such as a staggered pin grid array (SPGA), a land grid array (LGA), a quad flat package (QFP), a quad flat J-leaded package (QFJ), and a quad flat non-leaded package (QFN).

[0315] 17A shows a perspective view of a mainframe computer 5600. The mainframe computer 5600 shown in Fig. 17A has a rack 5610 housing a plurality of rack-mounted computers 5620. The mainframe computer 5600 may also be called a supercomputer.

[0316] The computer 5620 can have the configuration shown in the perspective view of Fig. 17B, for example. In Fig. 17B, the computer 5620 has a motherboard 5630, which has a plurality of slots 5631 and a plurality of connection terminals. A PC card 5621 is inserted into the slot 5631. In addition, the PC card 5621 has connection terminals 5623, 5624, and 5625, which are each connected to the motherboard 5630.

[0317] A PC card 5621 shown in Figure 17C is an example of a processing board equipped with a CPU, a GPU, a storage device, etc. The PC card 5621 has a board 5622. The board 5622 also has a connection terminal 5623, a connection terminal 5624, a connection terminal 5625, a semiconductor device 5626, a semiconductor device 5627, a semiconductor device 5628, and a connection terminal 5629. Note that Figure 17C illustrates semiconductor devices other than the semiconductor device 5626, the semiconductor device 5627, and the semiconductor device 5628, but for these semiconductor devices, the following descriptions of the semiconductor device 5626, the semiconductor device 5627, and the semiconductor device 5628 can be referred to.

[0318] The connection terminal 5629 has a shape that allows it to be inserted into a slot 5631 of the motherboard 5630 , and the connection terminal 5629 functions as an interface for connecting the PC card 5621 and the motherboard 5630 .

[0319] The semiconductor device 5626 has a terminal (not shown) for inputting and outputting signals, and the semiconductor device 5626 can be connected to the board 5622 by inserting the terminal into a socket (not shown) provided on the board 5622.

[0320] Examples of the semiconductor device 5627 include an FPGA, a GPU, and a CPU. The semiconductor device 5627 may be, for example, the electronic component 1390.

[0321] The semiconductor device 5628 can be, for example, a memory device. The electronic component 1390 can be used as the semiconductor device 5628.

[0322] The mainframe computer 5600 can also function as a parallel computer. By using the mainframe computer 5600 as a parallel computer, it is possible to perform large-scale calculations required for, for example, learning and inference in artificial intelligence.

[0323] [Space Equipment] The semiconductor device of one embodiment of the present invention can be suitably used in space equipment.

[0324] A semiconductor device according to one embodiment of the present invention includes an OS transistor. Compared to a Si transistor, an OS transistor exhibits smaller variations in electrical characteristics due to radiation exposure. That is, the OS transistor has high radiation resistance and is therefore highly reliable and suitable for use in environments where radiation may be incident. For example, an OS transistor can be suitably used in outer space. Specifically, an OS transistor can be used as a transistor for a semiconductor device provided in a space shuttle, an artificial satellite, or a space probe. Note that outer space refers to an altitude of 100 km or higher, for example. However, the outer space described in this specification can include one or more of the thermosphere, the mesosphere, and the stratosphere.

[0325] Furthermore, outer space is an environment with radiation levels 100 times higher than on Earth. Examples of radiation include electromagnetic waves (electromagnetic radiation) such as X-rays and gamma rays, and particle radiation such as alpha rays, beta rays, neutron rays, proton rays, heavy ion rays, and meson rays.

[0326] Fig. 17D shows an artificial satellite 6800 as an example of space equipment. The artificial satellite 6800 has a body 6801, a solar panel 6802, an antenna 6803, a secondary battery 6805, and a control device 6807. Note that Fig. 17D also shows a planet 6804 in space.

[0327] 17D , a battery management system (also referred to as a BMS) or a battery control circuit may be provided for the secondary battery 6805. The use of an OS transistor in the battery management system or the battery control circuit is preferable because it consumes low power and has high reliability even in space.

[0328] The control device 6807 has a function of controlling the artificial satellite 6800. The control device 6807 is configured using, for example, one or more selected from a CPU, a GPU, and a storage device. Note that the control device 6807 is preferably a semiconductor device including an OS transistor which is one embodiment of the present invention.

[0329] Although an artificial satellite is described as an example of space equipment in this embodiment, the present invention is not limited thereto. For example, the semiconductor device of one embodiment of the present invention can be suitably used in space equipment such as a spaceship, a space capsule, or a space probe.

[0330] As described above, OS transistors have excellent advantages over Si transistors, such as the ability to achieve a wide memory bandwidth and high radiation resistance.

[0331] [Data Center] The semiconductor device of one embodiment of the present invention can be suitably used in a storage system applied to, for example, a data center. The data center is required to perform long-term management of data, such as ensuring data immutability. To manage long-term data, the building must be large enough to accommodate the installation of storage and servers for storing a huge amount of data, a stable power source for storing the data, or cooling equipment required for storing the data.

[0332] By using the semiconductor device of one embodiment of the present invention in a storage system applied to a data center, it is possible to reduce the power required to store data and the size of the semiconductor device that stores data. Therefore, it is possible to reduce the size of the storage system, the size of the power supply for storing data, the scale of the cooling equipment, and the like. Therefore, it is possible to reduce the space required for the data center.

[0333] Furthermore, the semiconductor device of one embodiment of the present invention has low power consumption, which allows heat generation from the circuit to be reduced. Therefore, adverse effects of the heat generation on the circuit itself, peripheral circuits, and modules can be reduced. Furthermore, by using the semiconductor device of one embodiment of the present invention, a data center that operates stably even in a high-temperature environment can be realized. Therefore, the reliability of the data center can be improved.

[0334] Fig. 17E shows a storage system applicable to a data center. The storage system 7010 shown in Fig. 17E has a plurality of servers 7001sb as hosts 7001 (illustrated as Host Computers). It also has a plurality of storage devices 7003md as storage 7003 (illustrated as Storage). The host 7001 and storage 7003 are shown connected via a storage area network 7004 (illustrated as SAN: Storage Area Network) and a storage control circuit 7002 (illustrated as Storage Controller).

[0335] The host 7001 corresponds to a computer that accesses data stored in the storage 7003. The hosts 7001 may be connected to each other via a network.

[0336] Although the storage 7003 uses flash memory to reduce the data access speed, i.e., the time required to store and output data, this time is significantly longer than the time required for DRAM, which can be used as cache memory within the storage. In order to solve the problem of the long access speed of the storage 7003, a storage system typically provides cache memory within the storage to reduce the time required to store and output data.

[0337] The cache memory described above is used in the storage control circuit 7002 and the storage 7003. Data exchanged between the host 7001 and the storage 7003 is stored in the cache memory in the storage control circuit 7002 and the storage 7003, and then output to the host 7001 or the storage 7003.

[0338] By using OS transistors as transistors for storing data in the cache memory and holding a potential corresponding to the data, the frequency of refresh operations can be reduced, and power consumption can be reduced.

[0339] This embodiment can be implemented by appropriately combining at least a part of it with other embodiments described in this specification. In addition, when multiple configuration examples are shown in one embodiment in this specification, the configuration examples can be appropriately combined.

[0340] Embodiment 5 In this embodiment, an indium oxide film that can be used for a semiconductor layer of a transistor included in a semiconductor device of one embodiment of the present invention will be described.

[0341] In this specification and the like, indium oxide having at least a crystalline portion or a crystalline region in a film is referred to as crystalline indium oxide (crystal IO) or crystalline indium oxide (crystalline IO). Examples of crystalline IO or crystalline IO include single-crystalline indium oxide, polycrystalline indium oxide, and microcrystalline indium oxide.

[0342] Indium oxide is a semiconductor material having physical properties that are completely different from those of oxide semiconductors such as In—Ga—Zn oxide (hereinafter also referred to as IGZO) and zinc oxide.

[0343] The carrier concentration dependence of the Hall mobility of indium oxide, silicon, and IGZO will be explained. FIG. 18A shows the carrier concentration dependence of the Hall mobility of silicon (Si) and indium oxide (InO Ｘ ) and FIG. 18B is a schematic diagram showing the carrier concentration dependence of the hole mobility for IGZO.

[0344] First, IGZO tends to exhibit higher hole mobility as the carrier concentration increases, as shown by the arrows in Figure 18B. On the other hand, indium oxide tends to exhibit higher hole mobility as the carrier concentration decreases, as shown by the arrows in Figure 18A (see Non-Patent Document 3). This trend is similar to that of silicon; the lower the dopant (impurity) concentration in the material, the less impurity scattering there is and the higher the hole mobility. In other words, the higher the purity and intrinsic indium oxide, the higher the hole mobility. From these results, it can be said that indium oxide, unlike IGZO, is a material with physical properties similar to those of silicon. Note that the characteristics of indium oxide shown in Figure 18A are assumed to be single crystal. Therefore, when indium oxide is non-single crystal (e.g., polycrystalline), the characteristics may differ from those shown in Figure 18A.

[0345] 18A, the range R1 of low carrier concentration has extremely high hole mobility, and therefore can be said to be a range of carrier concentration suitable for, for example, a channel formation region of a transistor. For example, in the case of indium oxide, the range R1 is a range where the carrier concentration value is 1×10 １５ cm −３ The range includes, for example, 1×10 １４ cm −３ That's it, 1 x 10 １８ cm −３ By sufficiently reducing the carrier concentration, the Hall mobility value can be increased to 270 cm ２ It is expected that the resistance can be increased to about / (V·s).

[0346] In addition, in indium oxide, the region where the carrier concentration is in the range R1 may contain an element that lowers the carrier concentration. Examples of elements that lower the carrier concentration include magnesium, calcium, zinc, cadmium, and copper. By substituting these elements for indium, the carrier concentration can be lowered. Examples of elements that lower the carrier concentration include nitrogen, phosphorus, arsenic, and antimony. For example, by substituting nitrogen, phosphorus, arsenic, or antimony for oxygen, the carrier concentration can be lowered.

[0347] On the other hand, the range R2 with a high carrier concentration has a low electrical resistance, and can be said to be a range of carrier concentrations suitable for, for example, the source and drain regions of a transistor, a resistor, or a transparent conductive film. ２０ cm −３ The range includes, for example, 1×10 １９ cm −３ That's it, 1 x 10 ２２ cm −３ By increasing the carrier concentration sufficiently, the resistivity can be reduced to 1×10 −４ It is expected that the resistivity can be reduced to Ω·cm or less.

[0348] In addition, in indium oxide, the region where the carrier concentration is in the range R2 may contain an element that increases the carrier concentration. For example, it is preferable that the indium oxide contains an element that is common to the source electrode and drain electrode of the transistor. Examples of elements that increase the carrier concentration include titanium, zirconium, hafnium, tantalum, tungsten, molybdenum, tin, silicon, and boron. In particular, it is more preferable to use an element whose oxide has conductive or semiconducting properties. Note that, as a method for supplying an element that increases the carrier concentration, a method of forming a film containing the element and diffusing it, ion implantation, ion doping, plasma immersion ion implantation, or plasma treatment can be used. Note that, unless otherwise specified in this specification, the presence or absence of mass separation is not limited. For example, in this specification, a method of supplying ions after mass separation is referred to as an ion implantation method, and a method of supplying ions without mass separation is referred to as an ion doping method.

[0349] In this way, indium oxide uses a region with a low carrier concentration as the channel formation region of a transistor, and a region with a high carrier concentration as the source and drain regions of the transistor. In other words, indium oxide can be said to be an oxide capable of valence electron control. Note that IGZO may experience strain in the source and drain regions due to stress from electrodes in contact with the IGZO, resulting in the formation of n-type regions. On the other hand, unlike IGZO, indium oxide is capable of valence electron control, and therefore does not require strain to be formed in the film as with IGZO. Less strain in the film is expected to improve reliability. For example, by separately creating a region with a carrier concentration in the range R1 shown in FIG. 18A and a region with a carrier concentration in the range R2 in the indium oxide film, a so-called n-i-n junction (a junction between an n-type region, an i-type region, and an n-type region) can be created. Note that valence electron control in transistors using silicon is generally known. On the other hand, valence electron control in transistors using indium oxide is a novel technical concept that would not normally be conceived.

[0350] By using the above technical concept, the transistor having indium oxide in this specification and the like has two or more, preferably three or more, more preferably four or more, and most preferably five of the following characteristics (1) to (5): (1) high on-current (in other words, high mobility); (2) low off-current; (3) normally-off operation; (4) high reliability; and (5) high cutoff frequency (fT). For example, the transistor having indium oxide in this specification and the like has high mobility, low off-current, and is normally-off operation. The transistor has high mobility and is different from a normally-on transistor.

[0351] In addition, a semiconductor being i-type can be rephrased as having the same Fermi level (Ef) and intrinsic Fermi level (Ei) (Ef = Ei). As shown in FIG. 18B, in IGZO, the lower the carrier concentration, the smaller the hole mobility. Therefore, when Ef = Ei finally occurs, the carriers disappear (in other words, the physical properties become similar to those of an insulator), and there is a possibility that the transistor will no longer function. On the other hand, in indium oxide, as shown in FIG. 18A, the lower the carrier concentration, the higher the hole mobility. When Ef = Ei finally occurs, the hole mobility is maximized. In other words, a transistor containing indium oxide can achieve high field-effect mobility by setting Ef = Ei. Note that a transistor containing indium oxide is likely to be normally-off due to its low carrier concentration. Therefore, a transistor containing indium oxide can be normally-off and achieve high field-effect mobility.

[0352] Note that normally-off refers to a state in which no current flows through a transistor when no potential is applied to the gate or when the gate-source voltage is 0 V. Furthermore, normally-off can be evaluated by the threshold voltage (Vth) or shift value (Vsh) of the transistor. Unless otherwise specified, Vth is calculated by a constant current method. More specifically, Vth refers to a state in which the value of drain current (Id) × channel length (L) ÷ channel width (W) in the Id-Vg characteristics of a transistor is 1 nA (1 × 10 −９ A). Vsh is the gate voltage (Vg) when the drain current (Id) in the Id-Vg characteristic of the transistor is expressed logarithmically and the tangent of the maximum slope is Id = 1 pA (1 × 10 −１２ The gate voltage (Vg) is the intersection point between the line of Id = 1 pA and the line extrapolated from two points where the slope of Id is maximum when Id is expressed logarithmically in the Id-Vg characteristics of the transistor. For example, if either or both of Vth and Vsh are zero or a positive value, the transistor can be considered to be normally-off.

[0353] In addition, in a transistor containing indium oxide, in order to make the semiconductor i-type, that is, to achieve Ef = Ei, the film structure in contact with the indium oxide film is important. For example, in a transistor containing indium oxide, a film structure in which a silicon oxide film in contact with the indium oxide film, a hafnium oxide film, and a silicon nitride film are stacked is exemplified. By using this film structure, a semiconductor device with high reliability and Ef = Ei can be obtained.

[0354] In the above film configuration, a film containing oxygen, such as a silicon oxynitride film, a silicon nitride oxide film, an aluminum oxide film, or a gallium oxide film, can be used instead of the silicon oxide film. Also, in the above film configuration, a silicon nitride oxide film, a silicon oxynitride film, or the like can be used instead of the silicon nitride film. The hafnium oxide film, which is located closer to the indium oxide film than the silicon nitride film, functions as a gettering site for hydrogen.

[0355] The above film configuration can also be considered as a stacked structure of a film (e.g., a silicon oxide film) capable of supplying oxygen to the indium oxide film from the indium oxide film side, a film (e.g., a hafnium oxide film) capable of gettering hydrogen, and a film (e.g., a silicon nitride film) that suppresses the penetration of oxygen and hydrogen. With this configuration, oxygen vacancies in the indium oxide film are filled with oxygen in the silicon oxide film. Hydrogen in the indium oxide film is captured by the hafnium oxide film by heat treatment or the like. Furthermore, the provision of the silicon nitride film results in a film configuration that reduces the penetration of oxygen and hydrogen from the outside. That is, with the above film configuration, the indium oxide film can be made closer to i-type. Therefore, a transistor having the above-described indium oxide film has high field-effect mobility and high reliability.

[0356] Next, an indium oxide film applied to a transistor will be described. The indium oxide film preferably has crystallinity (i.e., has crystal grains). Examples of films having crystal grains include single-crystal films, polycrystalline films, and amorphous films containing crystal grains (also called microcrystalline films). In particular, the indium oxide film is preferably a polycrystalline film, and more preferably a single-crystal film. A single-crystal film does not have grain boundaries. Impurities (typically, insulating impurities, insulating oxides, etc.) that hinder carrier flow tend to segregate at grain boundaries. The use of a single-crystal film can suppress carrier scattering at grain boundaries, thereby realizing a transistor exhibiting high field-effect mobility. Furthermore, the use of a single-crystal film has the excellent effect of suppressing variations in transistor characteristics due to the grain boundaries.

[0357] Furthermore, polycrystalline films are preferable because they can reduce carrier scattering and exhibit high field-effect mobility compared to microcrystalline or amorphous films. When using a polycrystalline film, it is preferable to use a film with as large a crystal grain size as possible and with few crystal grain boundaries. Note that in a transistor using an indium oxide polycrystalline film, if there is no crystal grain boundary in the channel formation region or no crystal grain boundary is observed, the channel formation region is located within a single crystal region included in the polycrystalline film, and therefore the transistor can be considered to be using single-crystal indium oxide.

[0358] The crystallinity of indium oxide can be analyzed by, for example, X-ray diffraction (XRD), transmission electron microscope (TEM), or electron diffraction (ED). Alternatively, a combination of these methods may be used for analysis.

[0359] In this specification and the like, a semiconductor layer in which no crystal grain boundary is observed in the channel formation region, a semiconductor layer in which the channel formation region is included in one crystal grain, or a semiconductor layer in which the crystal axis direction is the same in at least two regions in the channel formation region can be called a single crystal film. Also, a semiconductor layer in which, in the channel formation region, within one crystal grain, the direction of another crystal axis continuously changes around a certain crystal axis or a certain crystal orientation as the axis of rotation can be called a single crystal film.

[0360] The channel formation region refers to a region of the semiconductor layer that overlaps (or faces) the gate electrode via the gate insulating layer, and is located between the region in contact with the source electrode and the region in contact with the drain electrode. The current path in the channel formation region is the shortest distance between the source electrode and the drain electrode. Therefore, the crystal grains, crystal grain boundaries, crystal axes, crystal orientation, etc. in the channel formation region can be confirmed by observing a cross section including the semiconductor layer, the source electrode, and the drain electrode.

[0361] The indium oxide film in the channel formation region preferably has a lower impurity concentration. Impurities in the indium oxide film in the channel formation region can be a scattering source of carriers, which can lead to a decrease in field-effect mobility. These impurities can also hinder the crystal growth of the indium oxide film. Examples of impurities in the indium oxide film include boron and silicon. The indium oxide film preferably contains these impurities at concentrations of 0.1% or less, and more preferably 0.01% (100 ppm) or less. Carbon, hydrogen, and other elements may be contained in the film-forming gas or precursor during film formation, and may remain in the indium oxide film in greater amounts than the above-mentioned impurities.

[0362] The indium oxide film in the channel formation region may contain an element that can become the same trivalent cation as indium, as long as the crystal maintains a cubic crystal structure (bixbyite type). Examples of such an element include Group 13 elements of the periodic table, such as gallium and aluminum, and Group 3 elements of the periodic table. These elements exist mainly as trivalent cations in oxides, and therefore the carrier concentration of indium oxide can be maintained low.

[0363] In addition, the indium oxide film in this specification and the like has a high film density. ２ O ３ The film densities of the films are shown in Table 1.

[0364]

[0365] As shown in Table 1, the film density of the indium oxide film was evaluated at six levels, Sample 1 to Sample 6. In Table 1, Condition 1 is the condition of the base of the indium oxide film, Samples 1 to 3 are glass, Sample 4 is a SiOx film formed by sputtering, and Samples 5 and 6 are yttria-stabilized zirconia (YSZ). Condition 2 is the film formation condition of the indium oxide film, Samples 1 to 3 are film formation by sputtering (SP), and Samples 4 to 6 are film formation by ALD. Condition 3 is the heat treatment condition after the formation of the indium oxide film, with Sample 1, Sample 4, and Sample 5 being no heat treatment (as-deposited), Sample 2 being baked at 350°C in a CDA atmosphere, Sample 3 being baked at 650°C in a CDA atmosphere, and Sample 6 being baked at 250°C in a vacuum atmosphere.

[0366] In Table 1, CDA stands for clean dry air. It is preferable that the atmosphere used in the heat treatment (condition 3) after the formation of the indium oxide film contains as little hydrogen and water as possible. It is preferable to use a high-purity gas with a dew point of −60° C. or lower, preferably −100° C. or lower, as the atmosphere.

[0367] As shown in Table 1, the indium oxide film tends to have a higher film density when subjected to heat treatment compared to when not subjected to heat treatment (Sample 1, Sample 4, or Sample 5). This is because the heat treatment removes impurity elements (e.g., carbon, nitrogen, hydrogen, argon, etc.) from the film, thereby increasing the purity of the indium oxide film. Furthermore, as shown in Samples 5 and 6, the indium oxide film on YSZ has a film density of 7.00 g / cm. ３ The theoretical film density of an indium oxide film is 7.18 g / cm ３ In this specification, the range of the film density of the indium oxide film is 6.70 g / cm ３ 7.18g / cm or more ３ Preferably, it is 6.90 g / cm or less. ３ 7.18g / cm or more ３ More preferably, it is 7.00 g / cm or less. ３ 7.18g / cm or more ３ The following is the result.

[0368] The film density can be evaluated by, for example, Rutherford backscattering spectroscopy (RBS) or X-ray reflectometry (XRR). Differences in film density can sometimes be evaluated by cross-sectional transmission electron microscope (TEM) images. In TEM observation, a high film density results in a dense (dark) transmission electron (TE) image, whereas a low film density results in a faint (bright) transmission electron (TE) image.

[0369] By using such an indium oxide film in a transistor, the field effect mobility of the transistor can be increased to 50 cm ２ / (V·s) or more, preferably 100 cm ２ / (V·s) or more, more preferably 150 cm ２ / (V·s) or more, more preferably 200 cm ２ / (V·s) or more, more preferably 250 cm ２ / (V·s) or more.

[0370] One of the features of an indium oxide film is that it has higher oxygen permeability (diffusibility) than an IGZO film. As shown in FIG. 18C, an indium oxide film (InO Ｘ Oxygen (O) diffusing into the indium oxide film passes through the indium oxide film and becomes oxygen molecules (O ２ ) and is released as water molecules (H ２ O) may be released in the film. Ｏ In the case where an indium oxide film is present, oxygen atoms diffuse to compensate for the oxygen vacancies. Since oxygen diffuses easily in the indium oxide film, it can be said that oxygen vacancies are more easily compensated for in the indium oxide film than in the IGZO film.

[0371] As described above, an indium oxide film can more easily reduce oxygen vacancies in the film than an IGZO film. Therefore, by using such an indium oxide film in a transistor, a transistor with extremely high reliability can be realized.

[0372] Furthermore, as shown in FIG. 18C, the indium oxide film diffuses hydrogen. Hydrogen that diffuses into the indium oxide film from the outside passes through the indium oxide film and becomes hydrogen molecules (H ２ ) or reacts with oxygen contained in the film and is released as water molecules. The oxygen and hydrogen diffuse in the indium oxide film by heat treatment. The temperature of the heat treatment is 200° C. or higher and 700° C. or lower, preferably 350° C. or higher and 650° C. or lower, and more preferably 400° C. or higher and 500° C. or lower.

[0373] A transistor using an indium oxide film is an accumulation-type transistor that uses electrons as majority carriers. Assuming that the carrier relaxation time is constant, the smaller the effective mass of the electrons (carriers), the higher the electron mobility. In other words, by using indium oxide, which has a small effective mass of electrons, for a transistor, the on-state current or field-effect mobility of the transistor can be increased.

[0374] Table 2 shows the results of single crystal indium oxide (here, In ２ O ３) and single-crystal silicon (Si). As shown in Table 2, indium oxide is characterized by a small effective mass of electrons and a large effective mass of holes. Indium oxide also has the characteristic that the effective mass of electrons is almost independent of the crystal orientation. Therefore, by using crystalline indium oxide in a transistor, a transistor with high field-effect mobility and high frequency characteristics (also called f characteristics) can be realized. Furthermore, since the effective mass of holes is large, a transistor with extremely small off-current can be realized. For example, by applying an indium oxide film to a vertical transistor, the off-current per 1 μm of channel width can be reduced to 1 fA (1×10) in an environment of 125° C. −１５ A) or less, or 1aA (1 x 10 −１８ A) or less, and under room temperature (25°C) conditions, −１８ A) or less, or 1zA (1 x 10 −２１ Furthermore, as shown in Table 2, indium oxide has a smaller effective mass of electrons and a larger effective mass of holes than silicon, and therefore may be able to realize a transistor with higher field-effect mobility and lower off-state current than a Si transistor.

[0375]

[0376] It is preferable to provide a seed layer so as to be in contact with at least a portion of the crystalline indium oxide film. The seed layer is preferably made of a material containing crystals with a small difference in lattice constant (also called lattice mismatch) with indium oxide. This can improve the crystallinity of the indium oxide film. Note that a substrate (e.g., a single-crystal substrate) may be used as one of the layers in contact with at least a portion of the crystalline indium oxide film.

[0377] One method for evaluating the degree of lattice mismatch is to use the value of the lattice mismatch shown below. The lattice mismatch Δa [%] of the crystals of the formed film (here, the indium oxide film) with respect to the crystals of the seed layer is expressed as Δa = ((L １ -L ２ ) / L ２) × 100, where L １ is the length or lattice constant of the unit lattice vector of the crystal of the formed film, and L ２ is the length of the unit cell vector or the lattice constant of the crystal of the seed layer.

[0378] The smaller the absolute value of the lattice mismatch Δa between the seed layer and the indium oxide film, the more preferable, and it is most preferably 0. For example, Δa can be set to −5% or more and 5% or less, preferably −4% or more and 4% or less, more preferably −3% or more and 3% or less, and even more preferably −2% or more and 2% or less.

[0379] Here, the indium oxide crystal has a cubic crystal structure (bixbyite type). For example, the crystal of yttria-stabilized zirconia (YSZ) can have a cubic crystal structure (fluorite type). The lattice mismatch of the indium oxide crystal with the cubic YSZ crystal is in the range of −2% to 2%, and a single crystal film of indium oxide can be epitaxially grown on the YSZ substrate.

[0380] It should be noted that the crystal structure of the seed layer and the crystal structure of the indium oxide film may not necessarily have the same crystal system or crystal orientation. For example, a film having crystals of a hexagonal or trigonal structure may be used under an indium oxide film having crystals of a cubic structure. For example, by setting the crystal orientation of the surface of the seed layer to

[001] and the crystal orientation of the underside of the indium oxide film to

[111] , the requirements related to the crystal orientation necessary for epitaxial growth can be satisfied. Examples of hexagonal or trigonal crystals include wurtzite structure, YbFe ２ O ４ Type structure, Yb ２ Fe ３ O ７ YbFeFe alloys have the following structures: ２ O ４ Type structure or Yb ２ Fe ３ O ７An example of a crystal having a crystalline structure is IGZO. It should be noted that a single crystal film of indium oxide can be formed not only on a YSZ substrate but also on an insulating film. On the other hand, it is difficult to form a single crystal film of silicon on an insulating film. Silicon crystals have a diamond structure. As such, indium oxide and silicon have similar properties in terms of single crystal. However, when comparing indium oxide and silicon in terms of whether they can be formed as single crystals on an insulating film, they have different properties.

[0381] Here, a comparison is made among a transistor having a crystalline indium oxide film, a transistor having an IGZO (a compound oxide of In, Ga, and Zn) film, and a transistor having a silicon (Si) film. The comparison is shown in Table 3.

[0382]

[0383] In Table 3, transistors having a crystalline indium oxide film are intended for use in LSIs and are clearly indicated as crystalline IO (LSI). Hereinafter, this may be simply referred to as crystalline IO. Transistors having an IGZO film are intended for use in displays and are clearly indicated as IGZO (Display). Hereinafter, this may be simply referred to as IGZO. Transistors having a Si film are also clearly indicated as Si. In Table 3, ◎ represents +2 points, ○ represents +1 point, △ represents 0 points, and × represents −1 point, respectively. Total is the total value of the ◎, ○, △, and × points shown in Table 3. A higher score indicates better characteristics than a lower score.

[0384] In Table 3, the first comparison item is extremely small off-state current, with crystalline IO and IGZO being superior to Si. The second comparison item is on-state current (Ion) characteristics, with crystalline IO and Si being superior to IGZO. The third comparison item is reliability, with crystalline IO and Si being superior to IGZO. The fourth comparison item is miniaturization of channel length, with crystalline IO and IGZO being superior to Si. In the section on miniaturization of channel length, VFET represents a vertical transistor, UFET represents a transistor with a U-shape structure, and 3D structure represents a three-dimensional structure. The fifth comparison item is cutoff frequency, with the characteristics increasing in the order of crystalline IO, Si, and IGZO. The sixth comparison item is improvement in integration, with Si being superior to crystalline IO and IGZO. The seventh comparison item is threshold voltage controllability (Vth controllability), in which Si is superior to crystalline IO and IGZO. The eighth comparison item is radiation resistance, in which crystalline IO and IGZO are superior to Si. The ninth comparison item is 3D (multi-level) integrated structure, in which crystalline IO and IGZO are superior to Si. The tenth comparison item is the possibility of self-heating, in which crystalline IO and IGZO are superior to Si.

[0385] As shown in Table 3, the total score for crystalline IO (LSI) is 9 points, for IGZO (Display) is 4 points, and for Si is 3 points. As described above, the semiconductor device of one embodiment of the present invention, in particular the semiconductor device including a crystalline indium oxide film, has the potential to replace a semiconductor device using Si.

[0386] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0387] In this example, the impurity concentration, crystallinity, and oxygen permeability of indium oxide films were evaluated. Specifically, five samples (Samples 2A to 2E) containing indium oxide films were fabricated, and secondary ion mass spectrometry (SIMS) and TEM images were taken. Ten samples (Samples 5A to 5J) containing indium oxide films were fabricated, and the oxygen permeability of the indium oxide films was evaluated by SIMS analysis.

[0388] Methods for manufacturing Samples 2A to 2E will be described.

[0389] In common with Samples 2A to 2E, a silicon substrate was first prepared, followed by forming a silicon oxide film with a thickness of 100 nm on the silicon substrate by thermal oxidation treatment.

[0390] Subsequently, an indium oxide film was formed on the silicon oxide film by ALD.

[0391] The indium oxide films were formed using triethylindium (TEI) as a precursor. Sample 2A used TEI with an aluminum content of 820 ppm, while Samples 2B to 2E used TEI with an aluminum content of less than 0.1 ppm.

[0392] In addition, in the formation of the indium oxide film, ozone (O ３ ) and oxygen (O ２ The time for introducing the oxidizing agent during one cycle was 30 seconds for Sample 2A and Sample 2D, 9 seconds for Sample 2B, 15 seconds for Sample 2C, and 60 seconds for Sample 2E. The time for introducing the oxidizing agent during one cycle may be simply referred to as the oxidation time.

[0393] In Sample 2A, an indium oxide film was formed to a target thickness of 40 nm, and in Samples 2B to 2E, an indium oxide film was formed to a target thickness of 20 nm.

[0394] In this manner, Samples 2A to 2E were fabricated.

[0395] [Evaluation of Hydrogen Concentration and Carbon Concentration] SIMS analysis was performed on Samples 2A to 2E. The analysis direction of the SIMS analysis was from the surface side of the sample toward the substrate. Depth profiles of the hydrogen concentration and carbon concentration were obtained by the SIMS analysis. The SIMS analysis was performed using a quadrupole secondary ion mass spectrometer (PHI-ADEPT1010) manufactured by ULVAC-PHI, Inc., and cesium primary ions (Cs ＋ Hereinafter, the hydrogen concentration depth profile may be referred to as an H profile, and the carbon concentration depth profile may be referred to as a C profile.

[0396] 19A to 19E show the results of the H profiles of Samples 2A to 2E. In FIGS. 19A to 19E, the horizontal axis represents the depth [nm] from the sample surface, and the position at the left end, 0 nm in depth, corresponds to the sample surface (the surface of the indium oxide film). The vertical axis represents the H concentration [atoms / cm ３ In addition, the background level (B.G.) of hydrogen in the SIMS analysis is 1.0×10 １９ atoms / cm ３ 19A is the H profile of sample 2A, FIG. 19B is the H profile of sample 2B, FIG. 19C is the H profile of sample 2C, FIG. 19D is the H profile of sample 2D, and FIG. 19E is the H profile of sample 2E. HCl-SiOx in FIGS. 19A to 19E indicates the silicon oxide film, and InOx indicates the indium oxide film. The same applies to the following FIGS. 20A to 22E.

[0397] 20A to 20E show the results of the C profiles for Samples 2A to 2E. In FIGS. 20A to 20E, the horizontal axis represents the depth [nm] from the sample surface, and the position at the left end, at a depth of 0 nm, corresponds to the sample surface (the surface of the indium oxide film). The vertical axis represents the C concentration [atoms / cm ３ In addition, the background level (B.G.) of carbon in the SIMS analysis was 2.0×10 １８ atoms / cm ３20A is a C profile of sample 2A, FIG. 20B is a C profile of sample 2B, FIG. 20C is a C profile of sample 2C, FIG. 20D is a C profile of sample 2D, and FIG. 20E is a C profile of sample 2E.

[0398] 19A to 19E, the hydrogen concentration in the indium oxide film increased with increasing oxidation time, and FIG. 20A to 20E, the carbon concentration in the indium oxide film decreased with increasing oxidation time.

[0399] [Evaluation of Aluminum Concentration and Gallium Concentration] SIMS analysis was performed on Samples 2A to 2E. The analysis direction of the SIMS analysis was from the surface side of the sample toward the substrate. Depth profiles of aluminum (Al) concentration and gallium (Ga) concentration were obtained by the SIMS analysis. The SIMS analysis was performed using a magnetic field secondary ion mass spectrometer (IMS-7f-Auto) manufactured by CAMECA, and O was used as the primary ion species. ２ ＋ Hereinafter, the depth profile of Al concentration may be referred to as an Al profile, and the depth profile of Ga concentration may be referred to as a Ga profile.

[0400] 21A to 21E show the results of the Al profiles for Samples 2A to 2E. In FIGS. 21A to 21E, the horizontal axis represents the depth [nm] from the sample surface, and the position at the left end, 0 nm in depth, corresponds to the sample surface (the surface of the indium oxide film). The vertical axis represents the Al concentration [atoms / cm ３ In addition, the background level (B.G.) of Al in the SIMS analysis was 3.0×10 １５ atoms / cm ３ 21A is the Al profile of sample 2A, FIG. 21B is the Al profile of sample 2B, FIG. 21C is the Al profile of sample 2C, FIG. 21D is the Al profile of sample 2D, and FIG. 21E is the Al profile of sample 2E.

[0401] 22A to 22E show the results of the Ga profiles for Samples 2A to 2E. In FIGS. 22A to 22E, the horizontal axis represents the depth [nm] from the sample surface, and the position at the left end, 0 nm in depth, corresponds to the sample surface (the surface of the indium oxide film). The vertical axis represents the Ga concentration [atoms / cm ３ In addition, the background level (B.G.) of Ga in the SIMS analysis was 4.0 × 10 １５ atoms / cm ３ 22A is the Ga profile of sample 2A, FIG. 22B is the Ga profile of sample 2B, FIG. 22C is the Ga profile of sample 2C, FIG. 22D is the Ga profile of sample 2D, and FIG. 22E is the Ga profile of sample 2E.

[0402] 21B to 21E and 22B to 22E, the Al concentration and Ga concentration in the indium oxide film formed using a precursor with a low Al content were found to be below the background level. In other words, by using a precursor with a low Al content, the Al concentration in the indium oxide film was reduced to 3.0×10 １５ atoms / cm ３ It was found that the Ga concentration in the indium oxide film can be reduced to 4.0×10 or less. １５ atoms / cm ３ I found that I could do the following:

[0403] The concentration of each element was calculated from the depth profile of the concentration of each element shown in Figures 19A to 22E. The results are shown in Table 4. In Table 4, the unit of the concentration of each element is [atoms / cm ３ ] to [ppm]. The unit conversion is ２ O ３ The density of ２２ atoms / cm ３ This was done under the assumption that:

[0404]

[0405] [Crystalline Properties] Cross-sectional and planar TEM images were taken for Samples 2A to 2E. To take the TEM images, the prepared samples were thinned by ion milling. A spherical aberration corrector function was used to observe the TEM images.

[0406] The TEM images were taken using an atomic resolution analytical electron microscope JEM-ARM200F manufactured by JEOL Ltd. at an acceleration voltage of 200 kV.

[0407] 23A1 and 23A2 show cross-sectional TEM images and planar TEM images of sample 2A, respectively. 23B1 and 23B2 show cross-sectional TEM images and planar TEM images of sample 2B, respectively. 23C1 and 23C2 show cross-sectional TEM images and planar TEM images of sample 2C, respectively. 24A1 and 24A2 show cross-sectional TEM images and planar TEM images of sample 2D, respectively. 24B1 and 24B2 show cross-sectional TEM images and planar TEM images of sample 2E, respectively. The total magnification of the planar TEM image of sample 2A was 4,000,000 times, and FIG. 23A2 shows a region of approximately 10 nm × 13 nm (also referred to as a field of view) cut out from a planar TEM image acquired in a 45 nm square. The total magnification of the planar TEM images of each of Samples 2B to 2E was 500,000 times, and Figures 23B2, 23C2, 24A2, and 24B2 show an area of ​​approximately 100 nm x 125 nm cut out from a planar TEM image acquired at a 360 nm square.

[0408] 23A1 and 23A2, it was observed that the crystallinity of the indium oxide film of Sample 2A was low. Furthermore, as shown in FIGS. 23B1 to 24B2, polycrystallization was observed in the indium oxide films of Samples 2B to 2E. This indicates that the crystallinity of an indium oxide film can be improved by using a precursor with a low Al content.

[0409] 23B1 to 24B2, the average grain size of the 10 crystal grains was 37 nm for sample 2B, 28 nm for sample 2C, 14 nm for sample 2D, and 13 nm for sample 2E. Therefore, it was observed that the longer the oxidation time, the smaller the average grain size of the crystal grains. In other words, it was observed that the longer the oxidation time, the finer the crystal grains.

[0410] Next, the extension length of the grain boundary was calculated based on the observation results of the obtained planar TEM image. Specifically, in the planar TEM image, the location where the connection of lattice fringes is interrupted is considered to be a grain boundary region, and a line is drawn at that location. Next, the center line of the drawn grain boundary region is approximated by a broken line, and the sum of the lengths of the broken lines is taken as the extension length of the grain boundary. In other words, the longer the extension length of the grain boundary, the more grain boundary components there are. Note that the extension length of the grain boundary may be calculated for each field of view, and the average value thereof may be used.

[0411] The grain boundary extension length calculated from the planar TEM image shown in Figure 23B2 was 518 nm, the grain boundary extension length calculated from the planar TEM image shown in Figure 23C2 was 850 nm, the grain boundary extension length calculated from the planar TEM image shown in Figure 24A2 was 1170 nm, and the grain boundary extension length calculated from the planar TEM image shown in Figure 24B2 was 1380 nm. Note that the grain boundary extension length shown here is the average value of the values ​​calculated for each of two 90 nm square fields extracted from a planar TEM image with a total magnification of 2 million times.

[0412] Table 5 shows the results of calculating the concentration of each element from the calculated extension length of the grain boundary and the depth profile of the concentration of each element shown in FIGS. 19B to 19E and 20B to 20E.

[0413]

[0414] [Oxygen Permeability] To evaluate the oxygen permeability of the indium oxide film, ten samples (Samples 5A to 5J) were prepared.

[0415] 25A and 25B show the structure of the laminated film included in each sample.

[0416] As shown in FIG. 25A, the stacked film of each of samples 5A and 5B includes a layer 701, a layer 702 on layer 701, a layer 703 on layer 702, a layer 704 on layer 703, a layer 705 on layer 704, and a layer 706 on layer 705.

[0417] 25B , the stacked film included in each of Samples 5C to 5J includes a layer 701, a layer 702 over the layer 701, a layer 703 over the layer 702, a layer 707 over the layer 703, a layer 704 over the layer 707, a layer 705 over the layer 704, and a layer 706 over the layer 705. Note that the film used as the layer 707 corresponds to an indium oxide film.

[0418] A silicon substrate was prepared as the layer 701. A silicon oxide film having a thickness of 100 nm formed by thermal oxidation was used as the layer 702. A silicon oxynitride film having a thickness of 100 nm formed by PECVD was used as the layer 703.

[0419] In all of Samples 5C to 5J, an indium oxide film with a target thickness of 10 nm, deposited by an ALD method, was used as the layer 707. The indium oxide films were deposited under the same conditions as the indium oxide film contained in Sample 2B for Samples 5C and 5D, under the same conditions as the indium oxide film contained in Sample 2C for Samples 5E and 5F, under the same conditions as the indium oxide film contained in Sample 2D for Samples 5G and 5H, and under the same conditions as the indium oxide film contained in Sample 2E for Samples 5I and 5J.

[0420] The layer 704 was a silicon oxynitride film formed by a PECVD method to a thickness of 50 nm. The layer 705 was a silicon oxynitride film formed by a sputtering method to a thickness of 50 nm. １８ A silicon oxide film containing O was used. Here, the silicon oxide film was formed using a silicon oxide target as a target and the following gas as a film formation gas: １８ O ２ The layer 706 was a silicon nitride film formed by sputtering to a thickness of 20 nm.

[0421] Subsequently, Samples 5B, 5D, 5F, 5H, and 5J were subjected to a heat treatment at 400° C. for 8 hours in a nitrogen atmosphere, while Samples 5A, 5C, 5E, 5G, and 5I were not subjected to the heat treatment.

[0422] In this manner, Samples 5A to 5J were fabricated.

[0423] The oxygen ( １８ By comparing the oxygen concentration distributions, the oxygen permeability of the indium oxide film used in the layer 707 (the extent to which oxygen permeates the layer 707 due to thermal diffusion, or the extent to which the layer 707 suppresses the thermal diffusion of oxygen) can be evaluated.

[0424] SIMS analysis was performed on Samples 5A to 5J. The analysis direction of the SIMS analysis was from the layer 701 side toward the layer 706. １８ The depth profile of the oxygen (O) concentration was obtained. For the SIMS analysis, a quadrupole mass spectrometer (ADEPT1010) manufactured by ULVAC-PHI, Inc. was used. １８ O) The concentration depth profile １８ This is sometimes referred to as the O profile.

[0425] 26A to 27B show the results of the measurements of Samples 5A to 5J. １８ 26A to 27B, the horizontal axis indicates the depth [nm] from the sample surface, and the position at the left end, 0 nm in depth, corresponds to the sample surface (surface of layer 706). １８ O concentration [atoms / cm ３ The dashed line in FIG. 26A indicates the sample 5A. １８ The solid line in FIG. 26A is the O profile of sample 5B. １８ The dashed line in FIG. 26B is the O profile of sample 5C. １８ The solid line in FIG. 26B is the O profile of sample 5D. １８ The dashed line in FIG. 26C is the O profile of sample 5E. １８ The solid line in FIG. 26C is the O profile of sample 5F. １８The dashed line in FIG. 27A is the O profile of sample 5G. １８ The solid line in FIG. 27A is the O profile of sample 5H. １８ The dashed line in Figure 27B is the O profile of sample 5I. １８ The solid line in FIG. 27B is the O profile of sample 5J. １８ This is the O profile.

[0426] Samples 5A to 5J １８ From the O profile, layer 705 is characterized by oxygen ( １８ O) concentration is 1 × 10 ２２ atoms / cm ３ Furthermore, the layer 703 before the heat treatment (the layer 703 of Samples 5A, 5C, 5E, 5G, and 5I) has a region where the oxygen ( １８ O) concentration is 1 × 10 ２０ atoms / cm ３ Therefore, before the heat treatment, the oxygen ( １８ It was confirmed that the oxygen (O) did not diffuse into the layer 703.

[0427] 26A to 27B, in Sample 5B, Sample 5D, Sample 5F, Sample 5H, and Sample 5J, which were subjected to the heat treatment, the oxygen ( １８ It was confirmed that the oxygen (O) contained in the layer 705 was diffused into the layer 703. １８ It was found that indium oxide (O) permeates the indium oxide film by thermal diffusion.

[0428] Also, near the center of the layer 703 ( １８ O profile depth of approximately 150 nm) １８ The O concentration was 6.0 × 10 for sample 5D. ２０ atoms / cm ３ (see FIG. 26B), and for sample 5F it was 7.0 × 10 ２０ atoms / cm ３ (see FIG. 26C), and for sample 5H it was 7.8×10 ２０ atoms / cm ３ (see FIG. 27A), and for sample 5J it was 9.2 × 10 ２０ atoms / cm３ That is, when the layer 707 (indium oxide film) was disposed between the layer 705 and the layer 703, oxygen contained in the layer 705 was transferred to the layer 703 through the layer 707 at a rate of 2×10 ２０ atoms / cm ３ More specifically, 5 x 10 ２０ atoms / cm ３ It was confirmed that it spread further.

[0429] The horizontal axis represents the extension length of the grain boundary, and the vertical axis represents the length of the grain boundary near the center of the layer 703. １８ The plot of O concentration is shown in Figure 28A. The dashed line in Figure 28A is the regression line for the plot, and the equation of the regression line is y = 4 × 10 １７ x + 4 x 10 ２０ and the coefficient of determination R ２ The value of was 0.9564. The dashed line in FIG. 28A indicates the thickness of the layer 703 that existed before the heat treatment. １８ O concentration is shown.

[0430] From the regression line equation, it can be seen that an indium oxide film with an extension length of the grain boundary of 0 nm has a grain boundary of 2×10 ２０ atoms / cm ３ or more, or 3 x 10 ２０ atoms / cm ３ Furthermore, it was suggested that an indium oxide film having a grain boundary extension length of 1000 nm has a permeability of 1×10 or more when subjected to a heat treatment at a heating temperature of 400° C. for a treatment time of 8 hours. ２１ atoms / cm ３ or less, or 8 x 10 ２０ atoms / cm ３ It was suggested that the following oxygen permeability properties were present.

[0431] As can be seen from FIG. 28A, the longer the extension length of the grain boundary, the １８It was confirmed that the O concentration tends to be higher in indium oxide films. In other words, it was confirmed that the more grain boundaries per unit volume an indium oxide film has, the more oxygen permeates through it. This suggests that oxygen diffuses through the crystal grain boundaries in the indium oxide film. It was also suggested that grain boundary diffusion of oxygen occurs in indium oxide films.

[0432] On the other hand, the intercept of the regression line is 4 x 10 ２０ atoms / cm ３ This is because the layer 703 was present before the heat treatment. １８ Here, if an indium oxide film with a grain boundary extension length of 0 nm is considered to be a single-crystal indium oxide film, it has been suggested that oxygen diffuses within the crystal grains (in the bulk) even if the indium oxide film is single-crystal. For example, within the crystal grains contained in the indium oxide film, oxygen ２０ atoms / cm ３ or more or 3 x 10 ２０ atoms / cm ３ It was suggested that the above oxygen was diffused by the heat treatment at a heating temperature of 400° C. for a treatment time of 8 hours.

[0433] These results suggest that oxygen can penetrate indium oxide films, and that oxygen diffuses not only through the grain boundaries but also within the bulk of the crystal grains.

[0434] In addition, to evaluate the permeation of oxygen through the indium oxide film, the oxygen diffused into the layer 703 was １８ The amount of O per unit area was integrated. １８ From the amount of O per unit area, the amount of O in layer 703 in the sample that was not subjected to heat treatment was １８ The integral of the amount of O per unit area is １８ The integral of the amount of O diffusion was used.

[0435] The horizontal axis represents the extension length of the grain boundary, and the vertical axis represents the length of the grain boundary diffused into the layer 703. １８ O diffusion amount integral value [atoms / cm ２28B shows a plot of the above. The dashed line in FIG. 28B is a regression line for the plot, and the equation of the regression line is y=4×10 １２ x + 3 x 10 １５ and the coefficient of determination R ２ The value was 0.9826.

[0436] From the regression line equation, it can be seen that an indium oxide film with an extension length of the grain boundary of 0 nm has a grain boundary of 1×10 １５ atoms / cm ２ or more, or 2 x 10 １５ atoms / cm ２ Furthermore, it was suggested that an indium oxide film having a grain boundary extension length of 1000 nm has a permeability of 1×10 or more when subjected to a heat treatment at a heating temperature of 400° C. for a treatment time of 8 hours. １６ atoms / cm ２ or less, or 8 x 10 １５ atoms / cm ２ It was suggested that the following oxygen permeability properties were present.

[0437] [Hydrogen Permeability] To evaluate the hydrogen permeability of the indium oxide film, ten samples (Samples 7A to 7J) were prepared.

[0438] 25A and 25B show the structure of the laminated film included in each sample.

[0439] As shown in Figure 25A, the stacked film of each of sample 7A and sample 7B includes a layer 701, a layer 702 on layer 701, a layer 703 on layer 702, a layer 704 on layer 703, a layer 705 on layer 704, and a layer 706 on layer 705.

[0440] 25B , the stacked film included in each of Samples 7C to 7J includes a layer 701, a layer 702 over the layer 701, a layer 703 over the layer 702, a layer 707 over the layer 703, a layer 704 over the layer 707, a layer 705 over the layer 704, and a layer 706 over the layer 705. Note that the film used as the layer 707 corresponds to an indium oxide film.

[0441] A silicon substrate was prepared as the layer 701. A silicon oxide film having a thickness of 100 nm formed by thermal oxidation was used as the layer 702. A silicon oxynitride film having a thickness of 100 nm formed by PECVD was used as the layer 703.

[0442] In Samples 7C to 7J, an indium oxide film with a target thickness of 10 nm formed by an ALD method was used as the layer 707. The indium oxide films were formed under the same conditions as the indium oxide film contained in Sample 2B for Samples 7C and 7D, under the same conditions as the indium oxide film contained in Sample 2C for Samples 7E and 7F, under the same conditions as the indium oxide film contained in Sample 2D for Samples 7G and 7H, and under the same conditions as the indium oxide film contained in Sample 2E for Samples 7I and 7J.

[0443] The layer 704 was a silicon oxynitride film with a thickness of 50 nm formed by a PECVD method. The layer 705 was a silicon oxynitride film with a thickness of 50 nm containing deuterium formed by a PECVD method. The silicon oxynitride film was formed using a 5% deuterium (D) gas diluted with Ar. ２ ) gas, SiH ４ gas, and N ２ O gas was used. Furthermore, a silicon nitride film having a thickness of 20 nm and formed by sputtering was used as the layer 706.

[0444] Subsequently, Samples 7B, 7D, 7F, 7H, and 7J were subjected to a heat treatment at 200° C. for 8 hours in a nitrogen atmosphere, while Samples 7A, 7C, 7E, 7G, and 7I were not subjected to the heat treatment.

[0445] In this manner, Samples 7A to 7J were fabricated.

[0446] Deuterium (D( ２ By comparing the hydrogen concentration distributions of the indium oxide film used for the layer 707, the hydrogen permeability of the indium oxide film used for the layer 707 (the degree to which hydrogen permeates the layer 707 due to thermal diffusion, or the degree to which the layer 707 suppresses the thermal diffusion of hydrogen) can be evaluated.

[0447] SIMS analysis was performed on Samples 7A to 7J. The analysis direction of the SIMS analysis was from the layer 701 side toward the layer 706. The SIMS analysis revealed that deuterium (D( ２ A depth profile of deuterium (D(H)) concentration was obtained. For the SIMS analysis, a quadrupole mass spectrometer (ADEPT1010) manufactured by ULVAC-PHI, Inc. was used. In the following, deuterium (D( ２ The depth profile of H) concentration may be referred to as a D concentration profile or a D profile.

[0448] 29A to 30B show the results of the D profiles for samples 7A to 7J. In FIGS. 29A to 30B, the horizontal axis represents the depth [nm] from the sample surface, and the position at the left end, 0 nm in depth, corresponds to the sample surface (surface of layer 706). The vertical axis represents the D concentration [atoms / cm ３ ]. The dashed line shown in FIG. 29A is the D profile of sample 7A, and the solid line shown in FIG. 29A is the D profile of sample 7B. The dashed line shown in FIG. 29B is the D profile of sample 7C, and the solid line shown in FIG. 29B is the D profile of sample 7D. The dashed line shown in FIG. 29C is the D profile of sample 7E, and the solid line shown in FIG. 29C is the D profile of sample 7F. The dashed line shown in FIG. 30A is the D profile of sample 7G, and the solid line shown in FIG. 30A is the D profile of sample 7H. The dashed line shown in FIG. 30B is the D profile of sample 7I, and the solid line shown in FIG. 30B is the D profile of sample 7J. The background level of D in this SIMS analysis was 1.6×10 １６ atoms / cm ３ It was.

[0449] From the D profiles of Samples 7A to 7J, the layer 705 has a deuterium concentration of 1×10 ２０ atoms / cm ３ Furthermore, the layer 703 before the heat treatment (the layer 703 of Samples 7A, 7C, 7E, 7G, and 7I) has a region where the deuterium concentration by SIMS is 1×10 １８ atoms / cm ３Therefore, it was confirmed that the deuterium contained in the layer 705 had not diffused into the layer 703 before the heat treatment.

[0450] 29A to 30B , it was confirmed that in Sample 7B, Sample 7D, Sample 7F, Sample 7H, and Sample 7J, which were subjected to the heat treatment, deuterium contained in the layer 705 diffused into the layer 703. This indicates that deuterium contained in the layer 705 permeates the indium oxide film by thermal diffusion.

[0451] The concentration profile of D diffused into layer 703 via layer 707 by heat treatment at a heating temperature of 200° C. for 8 hours has a distribution in layer 703. Therefore, the permeation of deuterium through the indium oxide film was evaluated by integrating the amount of deuterium diffused per unit area into layer 703. A conceptual diagram of a method for calculating the integral is shown in FIG. 31 . Specifically, the integral of the value obtained by subtracting the amount of deuterium per unit area in layer 703 without heat treatment from the amount of deuterium per unit area in layer 703 after heat treatment at a heating temperature of 200° C. for 8 hours (region X in FIG. 31 ) was used as the integral of the amount of deuterium diffused.

[0452] The integral value of the amount of deuterium diffused into the layer 703 was 4.19×10 for sample 7D. １３ atoms / cm ２ and for sample 7F, it was 5.23 × 10 １３ atoms / cm ２ and for sample 7H, it was 6.93 × 10 １３ atoms / cm ２ and for sample 7J, it is 7.86 × 10 １３ atoms / cm ２ That is, when the layer 707 (indium oxide film) was disposed between the layer 705 and the layer 703, the integral value of the amount of deuterium diffused from the layer 705 to the layer 703 via the layer 707 by heat treatment at a heating temperature of 200° C. for 8 hours was 2×10 １３ atoms / cm ２ More specifically, 4 x 10 １３ atoms / cm ２ It was confirmed that this was the case.

[0453] The horizontal axis represents the extension length of the grain boundary, and the vertical axis represents the integral value of the amount of deuterium diffused into the layer 703 [atoms / cm ２ 32 shows a plot of the above. The dashed line in FIG. 32 is a regression line for the plot, and the equation of the regression line is y=4×10 １０ x + 2 x 10 １３ and the coefficient of determination R ２ The value was 0.9886.

[0454] From the equation of the regression line, in an indium oxide film having an extension length of the grain boundary of 0 nm, the integral value of the amount of deuterium diffused into the layer 703 in a heat treatment at a heating temperature of 200° C. for 8 hours is 5×10 １２ atoms / cm ２ or more, or 1 x 10 １３ atoms / cm ２ Furthermore, in an indium oxide film having a grain boundary extension length of 1000 nm, the integral value of the amount of deuterium diffused into the layer 703 during heat treatment at a heating temperature of 200° C. for 8 hours was 1×10 １４ atoms / cm ２ or less, or 8 x 10 １３ atoms / cm ２ It was suggested that the following deuterium permeability properties were present.

[0455] 32, it was confirmed that the longer the extension length of the grain boundaries, the higher the deuterium concentration of the integral value of the amount of deuterium diffused into the layer 703 tends to be. In other words, it was confirmed that the more grain boundaries there are per unit volume of an indium oxide film, the more deuterium permeates through it. This suggests that hydrogen diffuses through the crystal grain boundaries in the indium oxide film. It also suggests the existence of grain boundary diffusion of hydrogen in the indium oxide film.

[0456] On the other hand, the intercept of the regression line is 2 x 10 １３ atoms / cm ２Here, if an indium oxide film with an extension length of the grain boundary of 0 nm is considered to be a single-crystal indium oxide film, it was suggested that deuterium diffuses within the crystal grains (in the bulk) even if the indium oxide film is single-crystal. For example, within the crystal grains contained in the indium oxide film, １２ atoms / cm ２ or more, or 1 x 10 １３ atoms / cm ２ It was suggested that the above deuterium was diffused by the heat treatment at a heating temperature of 200° C. for 8 hours.

[0457] Since the indium oxide film contains hydrogen, in this example, the hydrogen permeability of the indium oxide film was evaluated using deuterium. Note that, since deuterium is an isotope of hydrogen, the permeability of deuterium and the permeability of hydrogen are presumed to be equivalent. Therefore, the permeability of deuterium, the diffusion of deuterium, and the integral of the diffusion amount of deuterium can be rephrased as the permeability of hydrogen, the diffusion amount of deuterium, and the integral of the diffusion amount of hydrogen, respectively.

[0458] These results suggest that hydrogen can permeate indium oxide films. In addition to the grain boundary diffusion mentioned above, hydrogen also diffuses within the crystal grains (in the bulk).

[0459] The configurations, structures, or methods described in this embodiment can be used in appropriate combination with the configurations, structures, or methods described in other embodiment modes.

[0460] Below, a transistor of one embodiment of the present invention was fabricated and its electrical characteristics were evaluated. The results are described.

[0461] In this example, a transistor A and a transistor B1 were fabricated and their electrical characteristics were evaluated.

[0462] The transistor A was manufactured to have the structure of the transistor 100A described in Embodiment 1. The conductive layer 102_1 was formed using titanium nitride with a thickness of approximately 5 nm by a metal CVD method. The conductive layer 102_2 was formed using tungsten with a thickness of approximately 40 nm by a metal CVD method. The conductive layer 102_3 was formed using In—Sn—Si oxide with a thickness of approximately 20 nm by a sputtering method. The insulating layer 103 was formed using silicon nitride with a thickness of approximately 5 nm by an ALD method. The insulating layer 104 was formed using silicon nitride with a thickness of approximately 10 nm on the conductive layer 102 by a sputtering method. The insulating layer 105 was formed using silicon oxide with a thickness of approximately 80 nm by a sputtering method. The insulating layer 106 was formed using silicon nitride with a thickness of approximately 10 nm by a sputtering method. The conductive layer 107_1 was formed using tungsten with a thickness of approximately 15 nm by a sputtering method. The conductive layer 107_2 was formed using an In—Sn—Si oxide film with a thickness of approximately 10 nm and formed by a sputtering method. The diameter of the opening 190 was approximately 60 nm. The semiconductor layer 108 was formed using indium oxide with a thickness of approximately 5 nm and an In—Ga—Zn oxide film with a thickness of approximately 5 nm formed on the indium oxide by a sputtering method using an oxide target with an In:Ga:Zn=1:1:1.2 atomic ratio. The indium oxide was formed by the ALD method using triethylindium (TEI) as an indium precursor and ozone and oxygen as oxidants, with the introduction time of the mixed gas of ozone and oxygen as oxidants set to 9 seconds per cycle. The indium oxide used had low impurities such as aluminum and gallium and was permeable (diffusible) to oxygen and hydrogen. The insulating layer 109 had a four-layer structure in which, from the semiconductor layer 108 side, an aluminum oxide film with a thickness of about 1 nm formed by ALD, a silicon oxide film with a thickness of about 2 nm formed by ALD, a hafnium oxide film with a thickness of about 2 nm formed by ALD, and a silicon nitride film with a thickness of about 1 nm formed by ALD were stacked in this order. The conductive layer 110_1 was made of titanium nitride with a thickness of about 5 nm formed by metal CVD. The conductive layer 110_2 was made of tungsten with a thickness of about 20 nm formed by metal CVD.The insulating layer 111 was made of silicon nitride having a thickness of about 5 nm and formed by the ALD method.

[0463] The transistor B1 was manufactured to have the same structure as the transistor 100B described in Embodiment 1. The conductive layer 102_1 was formed using titanium nitride with a thickness of approximately 5 nm by a sputtering method. The conductive layer 102_2 was formed using tungsten with a thickness of approximately 20 nm by a sputtering method. The conductive layer 102_3 was formed using In—Sn—Si oxide with a thickness of approximately 20 nm by a sputtering method. The insulating layer 103 was formed using silicon nitride with a thickness of approximately 5 nm by an ALD method. The insulating layer 105 was formed using silicon oxide with a thickness of approximately 80 nm above the conductive layer 102 by a sputtering method. The insulating layer 106 was formed using silicon nitride with a thickness of approximately 10 nm by a sputtering method. The conductive layer 107_1 was formed using tungsten with a thickness of approximately 15 nm by a sputtering method. The conductive layer 107_2 was made of In—Sn—Si oxide with a thickness of approximately 10 nm formed by a sputtering method. The diameter of the opening 190 was approximately 60 nm. The semiconductor layer 108 was made of gallium oxide with a thickness of approximately 0.5 nm formed by an ALD method, an In—Ga—Zn oxide with a thickness of approximately 5 nm formed on the gallium oxide by the ALD method with an atomic ratio of In:Ga:Zn = 1:1:1, and an In—Ga—Zn oxide with a thickness of approximately 5 nm formed on the In—Ga—Zn oxide by a sputtering method using an oxide target with an atomic ratio of In:Ga:Zn = 1:1:1.2. The insulating layer 109 had a four-layer structure in which, from the semiconductor layer 108 side, an aluminum oxide film with a thickness of approximately 1 nm formed by ALD, a silicon oxide film with a thickness of approximately 2 nm formed by ALD, a hafnium oxide film with a thickness of approximately 2 nm formed by ALD, and a silicon nitride film with a thickness of approximately 1 nm formed by ALD were stacked in this order. The conductive layer 110_1 was made of titanium nitride with a thickness of approximately 5 nm formed by metal CVD. The conductive layer 110_2 was made of tungsten with a thickness of approximately 20 nm formed by metal CVD. The insulating layer 111 was made of silicon nitride with a thickness of approximately 5 nm formed by ALD.

[0464] 33A and 33B show the Id-Vg characteristics of the temperature-dependent evaluation of transistor A. The vertical axis represents the drain current (Id) on a logarithmic scale, and the horizontal axis represents the gate-source voltage (Vgs). Fig. 33B is an enlarged view of Fig. 33A over the range of gate-source voltage (Vgs) from -1 V to 3 V.

[0465] 34A and 34B show the Id-Vg characteristics of the transistor B1 in a temperature-dependent evaluation. The vertical axis represents the drain current (Id) on a logarithmic scale, and the horizontal axis represents the gate-source voltage (Vgs). Fig. 34B is an enlarged view of Fig. 34A over the range of gate-source voltage (Vgs) from -1 V to 3 V.

[0466] The measurement conditions for the Id-Vg characteristics were five substrate temperatures: condition A -20°C, condition B 25°C, condition C 60°C, condition D 85°C, and condition E 110°C; gate-source voltage (Vgs) = -4V to +4V in 0.1V steps; drain-source voltage (Vds) = +0.1V; and source voltage (Vs) = 0V.

[0467] It was confirmed that in both the transistor A and the transistor B1, Vsh tends to shift negatively and the subthreshold swing value (also referred to as the S value) tends to increase as the temperature increases from low to high. Note that in Examples 2 and 3, Vsh is a value of 1 pA (1×10 −１２ The gate voltage (Vg) was used as the value at which the axis of (A) intersects with the line (tangent) extrapolated from the two points where the slope of log(Id) is maximum. In this specification, the subthreshold swing value is defined as the amount of change in gate voltage when the drain current is changed by one order of magnitude while the drain voltage is kept constant in the subthreshold region.

[0468] 35A shows the subthreshold swing (S.S.) values ​​of transistors A and B1 at various temperatures. The vertical axis represents the subthreshold swing (S.S.), and the horizontal axis represents the temperature (Temp) at the time of measurement. The subthreshold swing (S.S.) values ​​of transistor A were 76.0 mV / dec when the measurement temperature was −20° C., 82.7 mV / dec when the measurement temperature was 25° C., 89.8 mV / dec when the measurement temperature was 60° C., 96.5 mV / dec when the measurement temperature was 85° C., and 102.3 mV / dec when the measurement temperature was 110° C. The subthreshold swing value (S.S.) of transistor B was 77.6 mV / dec when the measurement temperature was −20° C., 83.7 mV / dec when the measurement temperature was 25° C., 89.1 mV / dec when the measurement temperature was 60° C., 92.4 mV / dec when the measurement temperature was 85° C., and 103.3 mV / dec when the measurement temperature was 110° C.

[0469] 35B shows the change in subthreshold swing (S.S.) at each temperature for transistor A and transistor B1 shown in FIG. 35A. The vertical axis shows the difference (change) in subthreshold swing (S.S.), and the horizontal axis shows the temperature (Temp) at the time of measurement. The change in subthreshold swing (S.S.) for transistor A was 6.7 mV / dec from −20° C. to 25° C., 13.8 mV / dec from −20° C. to 60° C., 20.5 mV / dec from −20° C. to 85° C., and 26.3 mV / dec from −20° C. to 110° C. The rate of change in the subthreshold swing (S.S.) of transistor B1 was 6.1 mV / dec from −20° C. to 25° C., 11.5 mV / dec from −20° C. to 60° C., 14.8 mV / dec from −20° C. to 85° C., and 25.7 mV / dec from −20° C. to 110° C. That is, the rate of change in the subthreshold swing (S.S.) of transistor A was 50 mV / dec or less or 30 mV / dec or less from −20° C. to 110° C. Furthermore, the rate of change in the subthreshold swing (S.S.) of transistor B1 was 50 mV / dec or less or 30 mV / dec or less from −20° C. to 110° C.

[0470] 35C shows Vsh at each temperature for transistors A and B1. The vertical axis represents Vsh, and the horizontal axis represents the temperature (Temp) at the time of measurement. The Vsh of transistor A was −0.46 V when the measurement temperature was −20° C., −0.56 V when the measurement temperature was 25° C., −0.62 V when the measurement temperature was 60° C., −0.67 V when the measurement temperature was 85° C., and −0.72 V when the measurement temperature was 110° C. The Vsh of transistor B1 was 0.63 V when the measurement temperature was −0° C., 0.54 V when the measurement temperature was 25° C., 0.48 V when the measurement temperature was 60° C., 0.43 V when the measurement temperature was 85° C., and 0.35 V when the measurement temperature was 110° C.

[0471] Figure 35D shows the difference (change) in Vsh at each temperature between transistor A and transistor B1 shown in Figure 35C. The vertical axis represents the change in Vsh, and the horizontal axis represents the temperature (Temp) at the time of measurement. The change in Vsh for transistor A was -0.10 V from -20°C to 25°C, -0.16 V from -20°C to 60°C, -0.21 V from -20°C to 85°C, and -0.26 V from -20°C to 110°C. The change in Vsh for transistor B1 was -0.09 V from -20°C to 25°C, -0.15 V from -20°C to 60°C, -0.20 V from -20°C to 85°C, and -0.28 V from -20°C to 110°C. That is, the Vsh change amount of the transistor A was −0.5 V or less or −0.3 V or less at temperatures from −20° C. to 110° C. The Vsh change amount of the transistor B1 was −0.5 V or less or −0.3 V or less at temperatures from −20° C. to 110° C.

[0472] According to this example, it was confirmed that the transistor of one embodiment of the present invention exhibited small temperature-dependent changes in initial characteristics and favorable electrical characteristics.

[0473] A transistor according to one embodiment of the present invention is manufactured, and the results of a reliability test thereof are described below.

[0474] In this example, a transistor A and a transistor B2 were fabricated and evaluated in a +GBT (Gate Bias-Temperature) stress test (PBTS (Positive Bias Temperature Stress)).

[0475] The transistor A was fabricated to have the structure shown in Example 2.

[0476] The transistor B2 was manufactured to have the same structure as the transistor 100B described in Embodiment 1. The conductive layer 102_1 was formed using titanium nitride with a thickness of approximately 5 nm by a sputtering method. The conductive layer 102_2 was formed using tungsten with a thickness of approximately 20 nm by a sputtering method. The conductive layer 102_3 was formed using In—Sn—Si oxide with a thickness of approximately 20 nm by a sputtering method. The insulating layer 103 was formed using silicon nitride with a thickness of approximately 5 nm by an ALD method. The insulating layer 105 was formed using silicon oxide with a thickness of approximately 80 nm above the conductive layer 102 by a sputtering method. The insulating layer 106 was formed using silicon nitride with a thickness of approximately 10 nm by a sputtering method. The conductive layer 107_1 was formed using tungsten with a thickness of approximately 15 nm by a sputtering method. The conductive layer 107_2 was made of In—Sn—Si oxide with a thickness of approximately 10 nm and formed by a sputtering method. The diameter of the opening 190 was approximately 60 nm. The semiconductor layer 108 was made of In—Ga—Zn oxide with a thickness of approximately 5 nm, formed by a sputtering method using an oxide target with an In:Ga:Zn=1:1:1.2 atomic ratio, and an In—Ga—Zn oxide with a thickness of approximately 5 nm, formed on the In—Ga—Zn oxide by an ALD method with an atomic ratio of In:Ga:Zn=1:1:1. The insulating layer 109 had a four-layer structure including, from the semiconductor layer 108 side, an aluminum oxide film with a thickness of approximately 1 nm and formed by an ALD method, a silicon oxide film with a thickness of approximately 2 nm and formed by an ALD method, a hafnium oxide film with a thickness of approximately 2 nm and formed by an ALD method, and a silicon nitride film with a thickness of approximately 1 nm and formed by an ALD method. The conductive layer 110_1 was made of titanium nitride with a thickness of about 5 nm and formed by a metal CVD method. The conductive layer 110_2 was made of tungsten with a thickness of about 20 nm and formed by a metal CVD method. The insulating layer 111 was made of silicon nitride with a thickness of about 5 nm and formed by an ALD method.

[0477] 36 shows the results of the +GBT stress test for transistor A (n=2) and transistor B2 (n=2). The vertical axis represents the amount of change in Vsh (ΔVsh [mV]) from the start of the test, and the horizontal axis represents the stress time (Time) [hr].

[0478] The +GBT stress test was conducted in a dark room under the following stress conditions: substrate temperature 125°C, gate-source voltage (Vgs) = 1.98V, and drain-source voltage (Vds) = 0V. Furthermore, during the +GBT stress test, the Id-Vg characteristics were measured at regular intervals. The Id-Vg characteristics were measured under the following conditions: gate-source voltage (Vgs) = -1.8V to +1.8V in 0.1V steps, drain-source voltage (Vds) = +1.2V, source voltage (Vs) = 0V, and substrate temperature = 125°C.

[0479] In the case of transistor A, even after 1000 hours of the +GBT stress test, the absolute value |ΔVsh| of the amount of change in Vsh remained within 200 mV.

[0480] According to this example, it was confirmed that the transistor of one embodiment of the present invention has high reliability.

[0481] In this example, the oxygen in the indium oxide film ( １８ The concentrations of indium oxide (O) and hydrogen (deuterium: D) were evaluated. Specifically, six samples (Sample 1A, Sample 1B, Sample 1C, Sample 1D, Sample 1E, and Sample 1F) including indium oxide films were fabricated and subjected to SIMS analysis.

[0482] Methods for manufacturing Samples 1A to 1F will be described.

[0483] For each of Samples 1A to 1F, an yttria-stabilized zirconia (YSZ) substrate was prepared.

[0484] Subsequently, indium oxide (InO Ｘ ) film was formed.

[0485] The indium oxide film was formed by ALD. Triethylindium (TEI) was used as a precursor. Ozone (O ３) and oxygen (O ２ The time for introducing the oxidizing agent during one cycle was set to 9 seconds. The target thickness of the indium oxide film was 20 nm.

[0486] Subsequently, a silicon oxynitride (SiON) film having a thickness of 50 nm was formed on the indium oxide film by using a PECVD method.

[0487] Subsequently, for Sample 1A, Sample 1B, and Sample 1C, a silicon oxynitride film was formed by a sputtering method using a gas containing HCl as a deposition gas. １８ O ２ A silicon oxide (SiOx) film with a thickness of 50 nm was formed using gas. １８ O)) A film was formed.

[0488] For Sample 1D, Sample 1E, and Sample 1F, a silicon oxynitride (SiON(D)) film containing deuterium and having a thickness of 50 nm was formed on the silicon oxynitride film by a PECVD method. The silicon oxynitride film was formed using a 5% deuterium (SiON(D)) diluted with Ar as a deposition gas. ２ ) gas, SiH ４ gas, and N ２ O gas was used.

[0489] Subsequently, a silicon nitride (SiNx) film having a thickness of 20 nm was formed on the silicon oxide film or the silicon oxynitride film by sputtering.

[0490] Subsequently, Samples 1B and 1E were subjected to a heat treatment in a nitrogen atmosphere at 400° C. for 1 hour. Samples 1C and 1F were subjected to a heat treatment in a nitrogen atmosphere at 400° C. for 8 hours. Samples 1A and 1D were not subjected to a heat treatment.

[0491] In this manner, Samples 1A to 1F were fabricated.

[0492] SIMS analysis was performed on each of Samples 1A to 1F. The measurement direction of the SIMS analysis was the direction from the surface side of the sample toward the substrate. １８The depth profile of the concentration of deuterium (O) and the depth profile of the concentration of deuterium (D) were obtained. For the SIMS analysis, a quadrupole secondary ion mass spectrometer (PHI-ADEPT1010) manufactured by ULVAC-PHI, Inc. was used, and the primary ion species was Cs ＋ Hereafter, the depth profile of oxygen concentration is calculated as follows: １８ The depth profile of deuterium concentration is sometimes referred to as an O profile. The depth profile of deuterium concentration is sometimes referred to as a D profile.

[0493] FIG. 37A shows the results of the measurements of Sample 1A, Sample 1B, and Sample 1C. １８ 37A shows the results of the O profile. In FIG. 37A, the horizontal axis indicates the depth [nm] from the sample surface, and the position of 0 nm depth on the left end corresponds to the sample surface (surface of the SiNx film). The left vertical axis indicates １８ O concentration (atoms / cm ３ The right vertical axis indicates the secondary ion intensity [counts / sec.] of Si and In+O. In FIG. 37A, the thin dotted line indicates the sample without heat treatment (sample 1A). １８ The thick dotted line is the O profile of the sample (sample 1B) that was heat treated at 400°C for 1 hour in a nitrogen atmosphere. １８ The solid line shows the O profile of the sample (sample 1C) that was heat-treated at 400°C for 8 hours in a nitrogen atmosphere. １８ The thin solid line indicates the secondary ion intensity of In+O, and the thin dashed dotted line indicates the secondary ion intensity of Si.

[0494] Figure 37B shows the results of the D profile for Sample 1D, Sample 1E, and Sample 1F. In Figure 37B, the horizontal axis indicates the depth (nm) from the sample surface, and the position at the left end, 0 nm in depth, corresponds to the sample surface (surface of the SiNx film). The left vertical axis indicates the D concentration (atoms / cm ３]. The right vertical axis shows the secondary ion intensity [counts / sec.] of Si and In + O. In Figure 37B, the thin dotted line is the D profile of a sample without heat treatment (Sample 1D), the thick dotted line is the D profile of a sample (Sample 1E) that was heat treated at 400 °C for 1 hour in a nitrogen atmosphere, and the solid line is the D profile of a sample (Sample 1F) that was heat treated at 400 °C for 8 hours in a nitrogen atmosphere. The thin solid line shows the secondary ion intensity of In + O, and the thin dash-dot line shows the secondary ion intensity of Si.

[0495] 37A and 37B, segregation of deuterium (also called pile up) is confirmed at the interface between the YSZ substrate and the indium oxide film. On the other hand, oxygen ( １８ O) segregation is not clearly observed.

[0496] FIG. 38A shows the １８ 38B shows the O profile extracted from FIG. 37B. Also, FIG. 38B shows the D profile extracted from FIG.

[0497] FIG. 38A shows the results of the measurements of Sample 1A, Sample 1B, and Sample 1C. １８ 38A shows the results of the O profile. In FIG. 38A, the horizontal axis indicates the depth (nm) from the sample surface, and the position of 0 nm depth on the left edge corresponds to the sample surface (surface of the SiNx film). １８ O concentration (atoms / cm ３ In FIG. 38A, the thin dotted line indicates the sample without heat treatment (sample 1A). １８ The thick dotted line is the O profile of the sample (sample 1B) that was heat treated at 400°C for 1 hour in a nitrogen atmosphere. １８ The solid line shows the O profile of the sample (sample 1C) that was heat-treated at 400°C for 8 hours in a nitrogen atmosphere. １８ This is the O profile.

[0498] From FIG. 38A, it can be seen that the oxygen ( １８It was found that O) diffuses in the indium oxide film. Note that, since the lattice mismatch between YSZ crystal and indium oxide crystal is small, the indium oxide film on the YSZ substrate can grow epitaxially to become a single crystal film.

[0499] Oxygen in the indium oxide film ( １８ The oxygen (O) concentration in the indium oxide film after the heat treatment tended to be higher in the region closer to the interface with the upper SiON film, and there were also regions where the concentration changed by more than 10 times before and after the heat treatment. １８ It was found that the O) concentration increased slightly when the heat treatment was carried out for 8 hours (Sample 1C) compared to when the heat treatment was carried out for 1 hour (Sample 1B).

[0500] From the above, even if the indium oxide film has crystallinity (polycrystalline or single crystal), the film is free from oxygen ( １８ The results suggest that oxygen in the indium oxide film can be diffused relatively easily by heat treatment at 400°C. ２ O ３ The oxygen migration barrier in the film was 0.85 eV.

[0501] Figure 38B shows the results of the D profile for Sample 1D, Sample 1E, and Sample 1F. In Figure 38B, the horizontal axis indicates the depth (nm) from the sample surface, and the position at a depth of 0 nm on the left edge corresponds to the sample surface (surface of the SiNx film). The vertical axis indicates the D concentration (atoms / cm ３ In Fig. 38B, the thin dotted line is the D profile of the sample without heat treatment (sample 1D), the thick dotted line is the D profile of the sample that was heat treated at 400°C for 1 hour in a nitrogen atmosphere (sample 1E), and the solid line is the D profile of the sample that was heat treated at 400°C for 8 hours in a nitrogen atmosphere (sample 1F).

[0502] 38B shows that deuterium diffuses into the indium oxide film by heat treatment at 400° C. Since there is a small lattice mismatch between YSZ crystals and indium oxide crystals, the indium oxide film on the YSZ substrate can grow epitaxially to become a single crystal film.

[0503] The D concentration in the indium oxide film tends to be higher in regions closer to the interface with the upper SiON film, and there were also regions where the concentration changed by 10 times or more before and after the heat treatment.

[0504] In this example, deuterium was used to evaluate the movement of hydrogen in the sample. Since deuterium is an isotope of hydrogen, it is assumed that its movement in the sample is similar. From the above, results were obtained suggesting that an indium oxide film has the property of easily diffusing hydrogen in the film, even if it has its crystallinity (polycrystalline or single crystal). Furthermore, results were obtained suggesting that hydrogen present in an indium oxide film can be diffused relatively easily by performing a heat treatment at 400°C. Furthermore, the In calculated using Quantum ESPRESSO, a first-principles electronic structure calculation package, ２ O ３The hydrogen migration barrier in the semiconductor layer was 0.34 eV. [Explanation of symbols] 100A: transistor, 100B: transistor, 100C: transistor, 101: insulating layer, 102: conductive layer, 102_1: conductive layer, 102_2: conductive layer, 102_3: conductive layer, 103: insulating layer, 104: insulating layer, 105: insulating layer, 106: insulating layer, 107: conductive layer, 107_1: conductive layer, 107_2: conductive layer, 108: semiconductor layer, 108f: semiconductor layer, 109: insulating layer, 110: conductive layer, 110_1: conductive layer, 110_2: conductive layer, 110a: conductive layer, 111: insulating layer, 112: insulating layer, 190: opening, 701: layer, 702: layer, 703: layer, 704: layer, 705: layer, 706: layer, 707: layer, 801: conductive layer, 890: opening, 900: capacitor element, 901: insulating layer, 902: insulating layer, 903: insulating layer, 904: conductive layer, 904_1: conductive layer, 904_2: conductive layer, 904a: conductive layer, 905: insulating layer, 906: insulating layer, 907: insulating layer, 908: insulating layer, 909: conductive layer, 910: insulating layer, 990: opening, 999: memory cell, 1011: substrate, 1012: element isolation layer, 1013: semiconductor region, 1014: low resistance region, 1015: insulating layer, 1016: insulating layer, 10 17: insulating layer, 1018a: conductive layer, 1018b: dummy gate electrode, 1018c: dummy gate electrode, 1019: insulating layer, 1020: insulating layer, 1021: insulating layer, 1022: conductive layer, 1023: insulating layer, 1024: conductive layer, 1025: insulating layer, 1026: conductive layer, 1027a: conductive layer, 1027b: conductive layer, 1027c: conductive layer, 1028: insulating layer, 1029: insulating layer, 1030: conductive layer, 1030a: conductive layer, 1030b: conductive layer, 1030c: conductive layer, 1031: insulating layer, 1000: Si transistor, 1100A: transistor, 1102: conductive layer, 1102a: conductive layer, 1102a_1: conductive layer, 1102a_2: conductive layer, 1102a_3: conductive layer, 1107: conductive layer, 1107a: conductive layer, 1107a_1: conductive layer, 1107a_2: conductive layer, 1108: semiconductor layer, 1108a: semiconductor layer, 1190: opening, 1199: memory cell, 1201: insulating layer, 1202: conductive layer, 1203: conductive layer, 1204a: conductive layer, 1204b: conductive layer, 1204c: conductive layer, 1204d: conductive layer, 1205: insulating layer, 1206: insulating layer, 1207: conductive layer, 1207a: conductive layer,1207b: conductive layer, 1207c: conductive layer, 1207d: conductive layer, 1208: insulating layer, 1300: semiconductor device, 1310: driver circuit, 1311: peripheral circuit, 1312: control circuit, 1315: peripheral circuit, 1320: memory array, 1323: row driver, 1324: column driver, 1325: input circuit, 1326: output circuit, 1327: sense amplifier, 1328: voltage generation circuit, 1330: layer, 1331: PSW, 13 32: PSW, 1341: row decoder, 1342: column decoder, 1350: memory cell, 1351: memory cell, 1353: memory cell, 1354: memory cell, 1355: memory cell, 1356: memory cell, 1357: memory cell, 1360: arithmetic unit, 1370A: semiconductor device, 1380: electronic component, 1381: semiconductor device, 1382: driver circuit layer, 1383: memory layer, 1384: mold, 1385: land, 13 86: electrode pad, 1387: wire, 1388: printed circuit board, 1389: mounting board, 1390: electronic component, 1391: interposer, 1392: package board, 1393: electrode, 1394: semiconductor device, 5600: mainframe computer, 5610: rack, 5620: computer, 5621: PC card, 5622: board, 5623: connection terminal, 5624: connection terminal, 5625: connection terminal, 5626: semiconductor device, 5627: Semiconductor device, 5628: semiconductor device, 5629: connection terminal, 5630: motherboard, 5631: slot, 6800: artificial satellite, 6801: aircraft, 6802: solar panel, 6803: antenna, 6804: planet, 6805: secondary battery, 6807: control device, 7001: host, 7001sb: server, 7002: storage control circuit, 7003: storage, 7003md: storage device, 7010: storage system,

Claims

a transistor having a first conductive layer, a first insulating layer, a second conductive layer, a semiconductor layer, a second insulating layer, and a third conductive layer; at least a portion of the first conductive layer functions as one of a source electrode or a drain electrode; at least a portion of the second conductive layer functions as the other of the source electrode and the drain electrode; at least a portion of the third conductive layer functions as a gate electrode; the first insulating layer is located on the first conductive layer; the second conductive layer is located on the first insulating layer; the first insulating layer and the second conductive layer have openings that reach the first conductive layer; the semiconductor layer has a portion in contact with the first conductive layer, a portion in contact with a side surface of the opening of the first insulating layer, and a portion in contact with the second conductive layer; the second insulating layer is located on the semiconductor layer; the third conductive layer has a portion facing the semiconductor layer with the second insulating layer interposed therebetween; The semiconductor layer has a crystalline oxide semiconductor layer containing indium and oxygen. The oxide semiconductor layer is heated at 400° C. for 8 hours to remove oxygen from 2×10 ２０ atoms / cm ３ It has the property of transmitting more than When a +GBT stress test was carried out in a dark room, the absolute value |ΔVsh| of the change in Vsh calculated from Id-Vg measurement for 1000 hours under stress conditions of a substrate temperature of 125° C., a gate-source voltage Vgs of +1.98 V, and a drain-source voltage Vds of 0 V was within 200 mV, A transistor in which the difference between the subthreshold swing value at a measurement temperature of -20°C and the subthreshold swing value at a measurement temperature of 110°C is 30 mV / dec or less. 　 a transistor having a first conductive layer, a first insulating layer, a second conductive layer, a semiconductor layer, a second insulating layer, and a third conductive layer; at least a portion of the first conductive layer functions as one of a source electrode or a drain electrode; at least a portion of the second conductive layer functions as the other of the source electrode and the drain electrode; at least a portion of the third conductive layer functions as a gate electrode; the first insulating layer is located on the first conductive layer; the second conductive layer is located on the first insulating layer; the first insulating layer and the second conductive layer have openings that reach the first conductive layer; the semiconductor layer has a portion in contact with the first conductive layer, a portion in contact with a side surface of the opening of the first insulating layer, and a portion in contact with the second conductive layer; the second insulating layer is located on the semiconductor layer; the third conductive layer has a portion facing the semiconductor layer with the second insulating layer interposed therebetween; The semiconductor layer has a crystalline oxide semiconductor layer containing indium and oxygen. The oxide semiconductor layer has a hydrogen diffusion integral of 5×10 １２ atoms / cm ２ and When a +GBT stress test was carried out in a dark room, the absolute value |ΔVsh| of the change in Vsh calculated from Id-Vg measurement for 1000 hours under stress conditions of a substrate temperature of 125° C., a gate-source voltage Vgs of +1.98 V, and a drain-source voltage Vds of 0 V was within 200 mV, A transistor in which the difference between the subthreshold swing value at a measurement temperature of -20°C and the subthreshold swing value at a measurement temperature of 110°C is 30 mV / dec or less. 　 a transistor having a first conductive layer, a first insulating layer, a second conductive layer, a semiconductor layer, a second insulating layer, and a third conductive layer; at least a portion of the first conductive layer functions as one of a source electrode or a drain electrode; at least a portion of the second conductive layer functions as the other of the source electrode and the drain electrode; at least a portion of the third conductive layer functions as a gate electrode; the first insulating layer is located on the first conductive layer; the second conductive layer is located on the first insulating layer; the first insulating layer and the second conductive layer have openings that reach the first conductive layer; the semiconductor layer has a portion in contact with the first conductive layer, a portion in contact with a side surface of the opening of the first insulating layer, and a portion in contact with the second conductive layer; the second insulating layer is located on the semiconductor layer; the third conductive layer has a portion facing the semiconductor layer with the second insulating layer interposed therebetween; The semiconductor layer has a crystalline oxide semiconductor layer containing indium and oxygen. The oxide semiconductor layer is heated at 400° C. for 8 hours to remove oxygen from 2×10 ２０ atoms / cm ３ It has the property of transmitting more than The oxide semiconductor layer has a hydrogen diffusion integral of 5×10 １２ atoms / cm ２ and When a +GBT stress test was carried out in a dark room, the absolute value |ΔVsh| of the change in Vsh calculated from Id-Vg measurement for 1000 hours under stress conditions of a substrate temperature of 125° C., a gate-source voltage Vgs of +1.98 V, and a drain-source voltage Vds of 0 V was within 200 mV, A transistor in which the difference between the subthreshold swing value at a measurement temperature of -20°C and the subthreshold swing value at a measurement temperature of 110°C is 30 mV / dec or less. 　 In any one of claims 1 to 3, The transistor, wherein the extension length of the grain boundary in the oxide semiconductor layer is 0 nm or more and 1000 nm or less.

4. The transistor according to claim 1, wherein a change in Vsh with respect to temperature is -0.3 V or less in a temperature range of -20° C. to 110° C.

4. The oxide semiconductor layer according to claim 1, wherein the aluminum concentration in the oxide semiconductor layer obtained by secondary ion mass spectrometry is 3.0×10 １５ atoms / cm ３ Below is a transistor.

4. The oxide semiconductor layer according to claim 1, wherein the gallium concentration in the oxide semiconductor layer obtained by secondary ion mass spectrometry is 4.0×10 １５ atoms / cm ３ Below is a transistor.

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