Method for forming metal oxide layer

Abstract

Provided is a metal oxide layer having high carrier mobility. A metal oxide layer, having indium and oxygen and having crystal grains, is formed. This method has: a first step for forming a crystal part on a base film; and a second step for forming a metal oxide layer covering the crystal part. In the second step, crystal grains are formed in the metal oxide layer by the first crystal growth and the second crystal growth. The first crystal growth occurs in a first direction. The second crystal growth occurs in a second direction perpendicular or substantially perpendicular to the first direction. The speed of the first crystal growth is higher than the speed of the second crystal growth.

Description

Method for forming a metal oxide layer

[0001] 1. Field of the Invention One embodiment of the present invention relates to a metal oxide layer, a transistor, a semiconductor device, a memory device, and an electronic device. Another embodiment of the present invention relates to a method for forming a metal oxide layer, and a method for manufacturing a transistor and a semiconductor device.

[0002] One embodiment of the present invention is not limited to the above technical field, and examples of the technical field of one embodiment of the present invention include semiconductor devices, display devices, light-emitting devices, power storage devices, memory devices, electronic devices, lighting devices, input devices (e.g., touch sensors), input / output devices (e.g., touch panels), driving methods thereof, and manufacturing methods thereof.

[0003] In this specification and the like, a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (transistor, diode, photodiode, etc.), a device having such a circuit, etc. Also, it refers to any device that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip including an integrated circuit, and an electronic component in which a chip is housed in a package are examples of semiconductor devices. Furthermore, a memory device, a display device, a light-emitting device, a lighting device, and an electronic device may themselves be semiconductor devices and each may have a semiconductor device.

[0004] A technology for constructing transistors using semiconductor thin films formed on substrates with insulating surfaces has attracted attention. Such transistors are widely used in electronic devices such as integrated circuits (ICs) and display devices. While silicon-based semiconductor materials are widely known as semiconductor materials applicable to transistors, oxide semiconductors have also attracted attention as other materials.

[0005] Furthermore, it is known that a transistor using an oxide semiconductor has an extremely small leakage current in an off state. For example, Patent Document 1 discloses a low-power central processing unit (CPU) that utilizes the low leakage current characteristic of a transistor using an oxide semiconductor. Furthermore, Patent Document 2 discloses a memory device that can retain stored data for a long period of time by utilizing the low leakage current characteristic of a transistor using an oxide semiconductor.

[0006] Examples of oxide semiconductors that can be used in the active layer of a transistor include indium oxide and indium gallium zinc oxide. ２ O ３ Non-Patent Document 2 discloses a thin film transistor using hydrogenated polycrystalline indium oxide formed by low-temperature solid phase crystallization as an active layer.

[0007] JP 2012-257187 A JP 2011-151383 A

[0008] Dhananjay and C. W. Chu, “Realization of In▲2▼O▲3▼ thin film transistors through reactive evaporation process.” Appl. Phys. Lett. 91, 132111 (2007). Y. Magari et al. , “High-mobility hydrogenated polycrystalline In▲2▼O▲3▼(In▲2▼O▲3▼:H) thin-film transistors”, nature COMMUNICATIONS, 13, 1078 (2022) C. Chen, S. P. Ong, "A universal graph deep learning interatomic potential for the periodic table," Nat. Comput. Sci. , 2, 2022, pp. 718-728; Takashi Koida, "High mobility transparent conductive film," National Research and Development Agency, National Institute of Advanced Industrial Science and Technology, AIST Photovoltaic Power Generation Research Results Report 2019, Internet <URL: https: / / unit.aist.go.jp / rpd-envene / PV / ja / results / 2019 / oral / T13. pdf>IEEE IRDS, 2022 Edition, More Moore, Internet <URL: https: / / irds.ieee.org / editions / 2022 / more-moore>

[0009] An object of one embodiment of the present invention is to provide a metal oxide layer having high carrier mobility.An object of one embodiment of the present invention is to provide a novel metal oxide layer.An object of one embodiment of the present invention is to provide a transistor, a semiconductor device, or a memory device to which the metal oxide layer is applied.

[0010] An object of one embodiment of the present invention is to provide a transistor with favorable electrical characteristics.An object of one embodiment of the present invention is to provide a transistor with large on-state current.An object of one embodiment of the present invention is to provide a transistor with small parasitic capacitance.An object of one embodiment of the present invention is to provide a highly reliable transistor, semiconductor device, or memory device.An object of one embodiment of the present invention is to provide a transistor, semiconductor device, or memory device that can be miniaturized or highly integrated.An object of one embodiment of the present invention is to provide a semiconductor device or memory device with low power consumption.An object of one embodiment of the present invention is to provide a memory device with high operating speed.

[0011] Note that the description of these problems does not preclude the existence of other problems. One embodiment of the present invention does not necessarily have to solve all of these problems. Problems other than these can be extracted from the description in the specification, drawings, and claims.

[0012] One aspect of the present invention is a method for forming a metal oxide layer containing indium and oxygen and having crystal grains. The method includes a first step of forming crystal portions on an underlayer and a second step of forming a metal oxide layer covering the crystal portions. In the second step, crystal grains are formed in the metal oxide layer by first crystal growth and second crystal growth. The first crystal growth occurs in a first direction. The second crystal growth occurs in a second direction perpendicular or substantially perpendicular to the first direction. The rate of the first crystal growth is faster than the rate of the second crystal growth.

[0013] In the above-described method for forming a metal oxide layer, the second direction is preferably perpendicular or approximately perpendicular to the surface of the base film on which the crystal portions are disposed.

[0014] In the above method for forming a metal oxide layer, the crystal grains preferably have a grain size of 10 nm or more and 100 nm or less.

[0015] In the above method for forming a metal oxide layer, the metal oxide layer is preferably formed by atomic layer deposition (ALD).

[0016] In the above-described method for forming a metal oxide layer, it is preferable to form crystal grains by forming a metal oxide layer having an amorphous structure by sputtering and then performing heat treatment.

[0017] In the above method for forming a metal oxide layer, it is preferable to use a gas containing hydrogen as the sputtering gas.

[0018] In the above method for forming a metal oxide layer, it is preferable that the crystal grains have a cubic crystal structure, and the second direction is parallel to the <111> orientation of the crystal grains.

[0019] In the above method for forming a metal oxide layer, it is preferable that the crystal structure of the crystal portion is a cubic system, and the <111> orientation of the crystal portion is parallel or approximately parallel to the second direction.

[0020] In the above method for forming a metal oxide layer, the crystal portion preferably contains indium and oxygen.

[0021] In the above method for forming a metal oxide layer, the crystal portion preferably contains indium, tin, and oxygen.

[0022] In the above method for forming a metal oxide layer, it is preferable that the crystal structure of the crystal portion is hexagonal or trigonal, and the c-axis direction of the crystal portion is parallel or approximately parallel to the second direction.

[0023] In the above method for forming a metal oxide layer, the crystalline portion preferably contains indium, gallium, zinc, and oxygen.

[0024] In the above-described method for forming a metal oxide layer, the crystalline portion preferably has a composition of In:Ga:Zn=1:1:1 [atomic ratio] or a composition therearound, or a composition of In:Ga:Zn=1:3:2 [atomic ratio] or a composition therearound.

[0025] According to one embodiment of the present invention, a metal oxide layer having high carrier mobility can be provided. According to one embodiment of the present invention, a novel metal oxide layer can be provided. According to one embodiment of the present invention, a transistor, a semiconductor device, or a memory device to which the metal oxide layer is applied can be provided.

[0026] According to one embodiment of the present invention, a transistor with favorable electrical characteristics can be provided. According to one embodiment of the present invention, a transistor with large on-state current can be provided. According to one embodiment of the present invention, a transistor with small parasitic capacitance can be provided. According to one embodiment of the present invention, a highly reliable transistor, semiconductor device, or memory device can be provided. According to one embodiment of the present invention, a transistor, semiconductor device, or memory device that can be miniaturized or highly integrated can be provided. According to one embodiment of the present invention, a semiconductor device or memory device with low power consumption can be provided. According to one embodiment of the present invention, a memory device with high operating speed can be provided.

[0027] Note that the description of these effects does not preclude the existence of other effects. One embodiment of the present invention does not necessarily have all of these effects. Effects other than these can be extracted from the description in the specification, drawings, and claims.

[0028] FIGS. 1A, 1B, 1C, 1D, and 1E show examples of methods for forming a metal oxide layer. FIGS. 2A, 2B, 2C, 2D, 2E, and 2F show examples of methods for forming a metal oxide layer. FIGS. 3A, 3B, 3C, and 3D are diagrams illustrating examples of the configuration of a semiconductor device. FIGS. 4A, 4B, and 4C are diagrams illustrating examples of the configuration of a semiconductor device. FIGS. 5A, 5B, and 5C are diagrams illustrating examples of the configuration of a semiconductor device. FIGS. 6A, 6B, 6C, and 6D are diagrams illustrating examples of the configuration of a semiconductor device. FIGS. 7A, 7B, and 7C are diagrams illustrating examples of the configuration of a semiconductor device. FIGS. 8A and 8B are diagrams illustrating the carrier concentration dependence of Hall mobility. FIG. 8C is a cross-sectional view illustrating an indium oxide film. FIG. 9A is a diagram illustrating the crystal structure of indium oxide. FIG. 9B is a diagram illustrating the effect of lattice distortion on the effective mass. FIG. 10A is a diagram showing levels formed by hydrogen, oxygen vacancies, and oxygen in indium oxide crystal. FIG. 10B is a diagram showing the charges of each element in indium oxide. FIG. 11 is a block diagram illustrating an example configuration of a semiconductor device. FIGS. 12A, 12B, 12C, 12D, 12E, 12F, 12G, and 12H are diagrams illustrating an example circuit configuration of a memory cell. FIG. 13 is a cross-sectional view showing an example of a semiconductor device. FIGS. 14A and 14B are perspective views illustrating an example configuration of a semiconductor device. FIG. 15 is a cross-sectional view showing an example of a semiconductor device. FIG. 16 is a block diagram illustrating a CPU. FIGS. 17A and 17B are perspective views of a semiconductor device. FIGS. 18A and 18B are perspective views of a semiconductor device. FIG. 19A is an equivalent circuit diagram of a logic circuit. FIG. 19B is a circuit symbol for the logic circuit. FIG. 19C is a timing chart illustrating the operation of the logic circuit. FIGS. 20A and 20D are equivalent circuit diagrams of the logic circuit. Figures 20B, 20C, 20E, and 20F are circuit symbols for logic circuits. Figure 21A is an equivalent circuit diagram of a DFF circuit. Figure 21B is a circuit symbol for a DFF circuit. Figure 22A is a diagram explaining an example of the configuration of a shift register circuit. Figure 22B is a timing chart explaining the operation of the shift register circuit. Figures 23A and 23B are diagrams showing an example of electronic components. Figures 24A, 24B, and 24C are diagrams showing an example of a mainframe computer.FIG. 24D is a diagram showing an example of space equipment. FIG. 24E is a diagram showing an example of a storage system applicable to a data center. FIG. 25 is a cross-sectional STEM image of a transistor according to an example. FIGS. 26A, 26B, and 26C are diagrams showing Id-Vg characteristics of a transistor according to an example. FIGS. 27A, 27B, and 27C are diagrams showing measurement results of cutoff frequencies of transistors according to an example. FIGS. 28A and 28B are diagrams showing calculation results of cutoff frequencies of transistors according to an example. FIG. 29 is a diagram showing a calculation model of a transistor according to an example. FIG. 30 is a diagram showing calculation results of Id-Vg characteristics of a transistor according to an example. FIG. 31 is a diagram showing calculation results of cutoff frequencies of a transistor according to an example. FIG. 32 is a circuit diagram showing an off-current measurement system for a transistor according to an example. FIG. 33 is a diagram showing an Arrhenius plot of the off-current of a transistor according to an example.

[0029] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it will be readily understood by those skilled in the art that various changes can be made in form and detail without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments shown below.

[0030] In the configuration of the invention described below, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and repeated explanations thereof will be omitted. Furthermore, when referring to similar functions, the same hatching pattern may be used and no particular reference numeral may be assigned.

[0031] Furthermore, for ease of understanding, the position, size, range, etc. of each component shown in the drawings may not represent the actual position, size, range, etc. Therefore, the disclosed invention is not necessarily limited to the position, size, range, etc. disclosed in the drawings.

[0032] In this specification, the ordinal numbers "first" and "second" are used for convenience and do not limit the number of components or the order of the components (for example, the order of processes or stacking order). Furthermore, the ordinal numbers assigned to components in one part of this specification may not match the ordinal numbers assigned to the same components in other parts of this specification or in the claims.

[0033] A transistor is a type of semiconductor element that can amplify current or voltage, and perform a switching operation to control conduction or non-conduction. The term "transistor" used in this specification includes an insulated gate field effect transistor (IGFET) and a thin film transistor (TFT).

[0034] In this specification and the like, a transistor using an oxide semiconductor or a metal oxide for a semiconductor layer and a transistor having an oxide semiconductor or a metal oxide for a channel formation region may be referred to as an OS (oxide semiconductor) transistor. A transistor having silicon for a channel formation region may be referred to as a Si transistor.

[0035] Furthermore, the functions of "source" and "drain" may be interchanged when transistors of different polarities are used, or when the direction of current flow changes during circuit operation, etc. For this reason, the terms "source" and "drain" may be used interchangeably in this specification.

[0036] In this specification and the like, an oxynitride is a material containing oxygen and nitrogen, and the nitrogen and oxygen contents in the composition are not limited. That is, the oxynitride includes a material whose composition contains more oxygen than nitrogen, and a material whose composition contains more nitrogen than oxygen.

[0037] In this specification and the like, the words "film" and "layer" can be interchangeable in some cases or depending on the situation. For example, the term "conductive layer" can be changed to the term "conductive film." Or, for example, the term "insulating film" can be changed to the term "insulating layer."

[0038] Furthermore, in this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10 degrees or more and 10 degrees or less. Therefore, it also includes cases where the angle is -5 degrees or more and 5 degrees or less. Furthermore, "substantially parallel" refers to a state in which two straight lines are arranged at an angle of -20 degrees or more and 20 degrees or less. Furthermore, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, it also includes cases where the angle is 85 degrees or more and 95 degrees or less. Furthermore, "substantially perpendicular" refers to a state in which two straight lines are arranged at an angle of 70 degrees or more and 110 degrees or less.

[0039] In this specification, "connection" includes, as an example, "electrical connection." Note that the term "electrical connection" is sometimes used to define the connection relationship between circuit elements as an object. Furthermore, "electrical connection" includes "direct connection" and "indirect connection." "A and B are directly connected" means that A and B are connected without the intervention of a circuit element (e.g., a transistor, a switch, etc.; note that wiring is not a circuit element). On the other hand, "A and B are indirectly connected" means that A and B are connected via one or more circuit elements. Note that A and B represent objects such as elements, circuits, wiring, electrodes, terminals, semiconductor layers, and conductive layers.

[0040] For example, assuming that a circuit including A and B is operating, if there is a time during the operation of the circuit when an electrical signal is exchanged or an interaction of electrical potential occurs between A and B, then it can be defined that "A and B are indirectly connected" as objects. Note that even if there is a time during the operation of the circuit when no electrical signal is exchanged or an interaction of electrical potential occurs between A and B, it can still be defined that "A and B are indirectly connected" as long as there is a time during the operation of the circuit when an electrical signal is exchanged or an interaction of electrical potential occurs between A and B.

[0041] An example of a case where "A and B are indirectly connected" is when A and B are connected via the source and drain of one or more transistors. On the other hand, an example of a case where it cannot be said that "A and B are indirectly connected" is when an insulator is present in the path from A to B. Specifically, there are cases where a capacitive element is connected between A and B, and cases where a gate insulating film of a transistor is present between A and B. Therefore, it cannot be said that "the gate (A) of a transistor and the source or drain (B) of the transistor are indirectly connected."

[0042] Another example of a case where it cannot be said that "A and B are indirectly connected" is when multiple transistors are connected via their sources and drains to the path from A to B, and a constant potential V is supplied to a node between one transistor and another transistor from a power supply, GND, etc.

[0043] In this specification, a tapered shape refers to a shape in which at least a portion of the side surface of a structure is inclined relative to the substrate surface or the surface to be formed. For example, it is preferable to have a region in which the angle (also called the taper angle) between the inclined side surface and the substrate surface or the surface to be formed is greater than 0 degrees and less than 90 degrees. Note that the side surface of the structure, the substrate surface, and the surface to be formed do not necessarily need to be completely flat, and may be approximately planar with a slight curvature or approximately planar with a slight unevenness.

[0044] In the drawings and the like relating to this specification, arrows indicating the X direction, Y direction, and Z direction may be used. Note that in this specification, the "X direction" refers to the direction along the X axis, and there may be no distinction between the forward direction and the reverse direction unless explicitly stated. The same applies to the "Y direction" and the "Z direction." Furthermore, the X direction, Y direction, and Z direction are directions that intersect with each other. For example, the X direction, Y direction, and Z direction are directions that are perpendicular to each other.

[0045] In this specification and the like, a cubic crystal structure may be referred to as a cubic crystal, a cubic crystal structure, etc. The same applies to other crystal systems (hexagonal, trigonal, tetragonal, orthorhombic, monoclinic, and triclinic).

[0046] In this specification and the like, a high power supply potential VDD (hereinafter simply referred to as "VDD") refers to a power supply potential that is higher than a low power supply potential VSS (hereinafter simply referred to as "VSS"). Also, the low power supply potential VSS refers to a power supply potential that is lower than the high power supply potential VDD.

[0047] The potential H is a potential that turns on an n-channel field effect transistor (also called an "n-type transistor") and turns off a p-channel field effect transistor (also called a "p-type transistor"). The potential L is a potential that turns off an n-type transistor and turns on a p-type transistor. Therefore, the potential H is higher than the potential L. The potential H may be equal to VDD, and the potential L may be equal to VSS.

[0048] In this specification, space groups are expressed using short notation in international notation (or Hermann-Mauguin notation). Crystal planes and crystal orientations are expressed using Miller indices. In crystallography, space groups, crystal planes, and crystal orientations are expressed by adding a superscript bar to the numbers. However, due to formatting restrictions, in this specification, instead of adding a bar above the numbers, they may be expressed by adding a minus sign (-) before the numbers. Furthermore, individual orientations indicating directions within a crystal are expressed with [ ], collective orientations indicating all equivalent orientations are expressed with < >, individual planes indicating crystal planes are expressed with ( ), and collective planes with equivalent symmetry are expressed with {}.

[0049] Embodiment 1 In this embodiment, a metal oxide of one embodiment of the present invention and a method for forming a layer including the metal oxide (also referred to as a metal oxide layer) will be described with reference to FIGS. 1A to 2F.

[0050] The metal oxide of one embodiment of the present invention can be used for, for example, a semiconductor layer of a transistor. In this case, the metal oxide functions as a semiconductor, and therefore can be referred to as an oxide semiconductor. Note that the metal oxide of one embodiment of the present invention can also be used as any of a conductive material, a semiconductor material, and an insulating material depending on the type, combination, composition, and the like of elements constituting the metal oxide.

[0051] The metal oxide layer preferably has crystallinity. For example, the metal oxide layer preferably has crystal grains. The grain size of the crystal grains in the metal oxide layer is preferably, for example, 10 nm to 1 μm, 10 nm to 0.5 μm, or 10 nm to 100 nm. Furthermore, for example, the grain size is preferably 50 nm to 1 μm, 50 nm to 0.5 μm, or 50 nm to 100 nm. By forming the semiconductor layer of the transistor using a crystalline metal oxide layer, fluctuations in the electrical characteristics of the transistor can be suppressed, and reliability can be improved.

[0052] The grain size of a crystal grain can be calculated, for example, by calculating the cross-sectional area of ​​the crystal grain and assuming a perfect circle corresponding to the calculated area. The diameter in this case is sometimes called the area-equivalent circle diameter.

[0053] Films having crystal grains include single-crystal films, polycrystalline films, and amorphous films containing crystal grains. A polycrystalline film is composed of two or more crystal grains, whereas a single-crystal film can be considered to be composed of a single crystal grain. While grain boundaries are observed in polycrystalline films, they are not observed in single-crystal films.

[0054] In this specification and the like, a semiconductor layer in which no crystal grain boundary is observed in the channel formation region, a semiconductor layer in which the channel formation region is included in one crystal grain, or a semiconductor layer in which the crystal axis direction is the same in at least two regions in the channel formation region can be called a single crystal film. Alternatively, a semiconductor layer in which at least one crystal orientation is oriented in one direction in the channel formation region can be called a single crystal film.

[0055] The channel formation region refers to a region of the semiconductor layer that overlaps (or faces) the gate electrode via the gate insulating layer and is located between the region in contact with the source electrode and the region in contact with the drain electrode. A semiconductor layer in which no crystal grain boundaries are observed in the region in contact with the source electrode and the region in contact with the drain electrode, a semiconductor layer in which the region in contact with the source electrode and the region in contact with the drain electrode is included in a single crystal grain, or a semiconductor layer in which the crystal axis direction is the same in at least two regions located between the region in contact with the source electrode and the region in contact with the drain electrode can also be called a single-crystalline film. Alternatively, a semiconductor layer in which at least one crystal orientation is oriented in one direction in the region in contact with the source electrode and the region in contact with the drain electrode can also be called a single-crystalline film.

[0056] The current path in the channel formation region is the shortest distance between the source electrode and the drain electrode, so the crystal grains, crystal grain boundaries, crystal axes, crystal orientations, etc. in the channel formation region can be confirmed by observing a cross section including the semiconductor layer, the source electrode, and the drain electrode.

[0057] The crystallinity of the metal oxide layer can be analyzed by, for example, X-ray diffraction (XRD), transmission electron microscope (TEM), or electron diffraction (ED), or a combination of these methods may be used.

[0058] Crystal grains can be confirmed, for example, by a high-resolution TEM image. Furthermore, crystal grain boundaries can sometimes be confirmed, for example, by a high-resolution TEM image. That is, crystal grains and crystal grain boundaries can sometimes be observed in a high-resolution TEM image of a crystalline film. The total magnification when acquiring a TEM image is preferably 2,000,000 times or more, and more preferably 4,000,000 times or more.

[0059] The presence or absence of grain boundaries can be confirmed in a TEM image acquired at a total magnification at which the grain boundaries can be observed. For example, if no grain boundaries are observed in a TEM image of a film acquired at a total magnification at which the grain boundaries can be observed, the film can be said to be a single crystal film or a film in which no grain boundaries are observed.

[0060] The metal oxide of one embodiment of the present invention contains at least indium and oxygen. The higher the indium content in the metal oxide, the higher the field-effect mobility of the transistor. Therefore, the transistor can have a large on-state current and high frequency characteristics.

[0061] The crystal grains of the metal oxide layer contain indium and oxygen. By increasing the indium content in the crystal grains, the crystal structure of the crystal grains becomes a cubic system, specifically, a bixbite type. In order for the metal oxide layer to have crystal grains with a cubic crystal structure, the indium content in the crystal grains is set to 70% to 100%, preferably 80% to 100%, more preferably 90% to 100%, and even more preferably 95% to 100%.

[0062] In this specification, the content of a metal element in a metal oxide refers to the ratio of the number of atoms of that element to the total number of atoms of the metal element contained in the metal oxide. For example, if a metal oxide contains metal elements X, Y, and Z, and the number of atoms of each of metal elements X, Y, and Z contained in the metal oxide is A, then Ｘ , A Ｙ , A Ｚ When the content of the metal element X is Ｘ / (A Ｘ +A Ｙ +A Ｚ) In addition, the ratio of the number of atoms of the metal element X, the metal element Y, and the metal element Z in the metal oxide (atomic number ratio) can be expressed as follows: Ｘ : B Ｙ : B Ｚ When the content of the metal element X is expressed as B Ｘ / (B Ｘ +B Ｙ +B Ｚ ) can be shown as

[0063] The metal oxide layer may contain other elements as long as the crystal structure of the crystal grains maintains a cubic crystal system. For example, the metal oxide layer may contain an element Mx in addition to indium and oxygen. Examples of the element Mx include one or more elements selected from tin, zinc, antimony, copper, cobalt, and gallium. The content of the element Mx in the crystal grains is preferably 0.1% or more and less than 30%, more preferably 0.1% or more and less than 20%, more preferably 0.1% or more and less than 10%, and even more preferably 0.1% or more and less than 5%. When the elements Mx1 and Mx2 are selected as the element Mx, the content of the element Mx in the crystal grains can be calculated as the sum of the content of the element Mx1 and the content of the element Mx2 in the crystal grains. For example, by adding atoms that can become tetravalent or higher cations (tin, antimony, and cobalt) to indium oxide, the atoms can be substituted for indium atoms, resulting in one or more extra electrons, thereby forming an n-type. Furthermore, for example, by adding atoms that can become divalent or lower cations (e.g., zinc and copper) to indium oxide, the atoms replace indium atoms, resulting in a deficiency of one or more electrons, thereby forming a p-type material and reducing the carrier concentration of the metal oxide layer.

[0064] In one embodiment of the present invention, in order to form a crystalline metal oxide layer, a crystal portion is provided in contact with a base film on which the metal oxide layer is provided. By forming a metal oxide layer to cover the crystal portion, the crystal portion can be used to enhance the crystallinity of the metal oxide layer. Furthermore, a metal oxide layer having crystal grains can be formed. The crystal portion functions as a seed or nucleus for enhancing the crystallinity of the metal oxide layer, and therefore can be referred to as a seed layer, seed crystal, crystal nucleus, or the like.

[0065] A method for forming a metal oxide layer using the crystalline portion will be described.

[0066] First, a method for forming a metal oxide layer in the case where the crystal structure of the crystal portion is a cubic system, which is the same as the crystal structure of the crystal grains of the metal oxide layer, will be described with reference to FIGS. 1A to 1E. FIG.

[0067] An underlayer 11 is prepared. FIG. 1A illustrates an underlayer 11 having a flat surface. The underlayer 11 may be an insulating substrate, a semiconductor substrate, or a conductive substrate. The underlayer 11 may also be an insulating film, a semiconductor film, or a conductive film provided on a substrate.

[0068] The underlayer film 11 is preferably made of a material having a thermal expansion coefficient smaller than that of the metal oxide of one embodiment of the present invention. For example, the underlayer film 11 can be made of a material having a thermal expansion coefficient smaller than that of indium oxide. Specifically, the thermal expansion coefficient of the underlayer film 11 is 0.01×10 −６ K −１ 5.5 x 10 −６ K −１ Preferably, 0.01 x 10 or less −６ K −１ Above 5.0 x 10 −６ K −１ Preferably, 0.01 x 10 or less −６ K −１ Above 3.0 x 10 −６ K −１ More preferably, 0.01 x 10 or less −６ K −１ Above 1.0 x 10 −６ K −１ The following is even more preferable. When a metal oxide layer containing indium oxide is in contact with or located near an underlayer 11 having a small thermal expansion coefficient, tensile stress is applied to the indium oxide when the temperature is lowered, making the indium oxide energetically unstable. As a result, the indium oxide becomes a cubic crystal, which is more energetically stable. This promotes crystal growth, allowing the formation of large cubic crystal grains. Silicon oxide is suitable for the underlayer 11 because it has a smaller thermal expansion coefficient than indium oxide.

[0069] Next, a crystalline portion 12 having a cubic crystal structure is formed on the base film 11 (see FIG. 1A ). Examples of the crystalline portion 12 having a cubic crystal structure include oxides containing indium (typically indium oxide), oxides containing one or both of yttrium and zirconium, erbium oxide, gallium zinc oxide (Ga-Zn oxide, also referred to as GZO), and aluminum zinc oxide (Al-Zn oxide, also referred to as AZO). Examples of oxides containing one or both of yttrium and zirconium include yttrium oxide, zirconium oxide, and oxides containing yttrium and zirconium. Examples of the crystalline portion 12 having a cubic crystal structure include the aforementioned metal oxides containing indium, element Mx, and oxygen. Examples of such metal oxides include indium tin oxide (In-Sn oxide, also referred to as ITO).

[0070] 1A shows an example in which island-shaped crystal portions 12 are provided. In plan view, the crystal portions 12 may be, for example, approximately circular, such as elliptical, triangular, quadrangular (including rectangular, rhombic, and square), pentagonal, or polygonal, such as a star-shaped polygon, or these polygons with rounded corners. Furthermore, when sputtered particles are used as the crystal portions 12, the crystal portions 12 in plan view may be triangular or hexagonal.

[0071] In this specification and the like, a plan view refers to a view from the normal direction of the surface on which a certain component is formed or the surface of a support (for example, a substrate) on which the component is formed.

[0072] The crystal portion 12 may have a tapered shape. By making the crystal portion 12 have a tapered shape, the coverage of the metal oxide layer 13 can be improved, and defects such as voids can be reduced. Furthermore, crystal growth in the metal oxide layer 13 can be promoted.

[0073] The crystal portions 12 may be provided so as to extend along the surface of the base film 11. The crystal portions 12 may also be striped in plan view. The number of crystal portions 12 provided on the base film 11 may be one or more.

[0074] The crystal portions 12 may be provided so as to be embedded in the base film 11. This allows the surface on which the metal oxide layer 13 is to be formed to be flat, and the crystallinity of the metal oxide layer 13 can be improved.

[0075] The crystalline portion 12 may be provided so as to cover the upper surface of the base film 11. This reduces the steps on the surface on which the metal oxide layer 13 is formed, and the crystallinity of the metal oxide layer 13 can be improved.

[0076] The thickness of the crystal portion 12 is preferably thin. The crystal portion 12 preferably has a region where the thickness is, for example, 0.1 nm or more and less than 3 nm, and more preferably has a region where the thickness is 0.5 nm or more and less than 3 nm. By thinning the thickness of the crystal portion 12, the step that occurs between the crystal portion 12 and the base film 11 is reduced. This improves the coverage of the metal oxide layer that will be formed later, and reduces defects such as voids. It also promotes crystal growth of the metal oxide layer.

[0077] Subsequently, a metal oxide layer 13 is formed on the underlayer 11 to cover the crystal portion 12 (see FIG. 1B).

[0078] The metal oxide layer 13 is preferably formed using the ALD method. By using the ALD method, which deposits atoms during film formation rather than the sputtering method, which bombards particles onto the surface to be formed, the generation of crystal nuclei in the film can be suppressed. For example, a precursor and an oxidizing agent can be used to form the metal oxide layer 13. The precursor preferably contains indium. In this case, a film containing indium and oxygen is formed as the metal oxide layer 13. Note that when the precursor contains indium, a thermal ALD method can be used as the ALD method.

[0079] Examples of precursors that can be used that contain indium include trimethylindium, triethylindium, ethyldimethylindium, tris(1-methylethyl)indium, tris(2,2,6,6-tetramethyl-3,5-heptanedionate)indium, cyclopentadienylindium, indium(III) acetylacetonate, (3-(dimethylamino)propyl)dimethylindium, (diethylphosphino)dimethylindium, chlorodimethylindium, bromodimethylindium, and dimethyl(2-propanolato)indium.

[0080] Alternatively, an inorganic precursor containing no hydrocarbon may be used as the indium-containing precursor. Examples of the inorganic precursor containing indium include halogen-based indium compounds such as trifluoroindium (indium(III) fluoride), indium trichloride (indium(III) chloride), indium tribromide (indium(III) bromide), and indium triiodide (indium(III) iodide). Indium trichloride has a decomposition temperature of approximately 500°C to 700°C. Therefore, by using indium trichloride, film formation can be performed by the ALD method while heating the substrate at approximately 400°C to 600°C, for example, at 500°C.

[0081] It is preferable to use a precursor having a low impurity concentration, i.e., a high purity, in the method for forming the metal oxide layer 13. For example, by using a precursor having a purity of 3N (99.9%) or higher, preferably 4N (99.99%) or higher, more preferably 5N (99.999%) or higher, and even more preferably 6N (99.9999%) or higher, the impurities in the metal oxide layer 13 can be reduced.

[0082] The gallium content and aluminum content of the indium-containing precursor are each preferably 1000 ppm or less, more preferably 500 ppm or less, even more preferably 100 ppm or less, still more preferably 50 ppm or less, still more preferably 10 ppm or less, and still more preferably 1 ppm or less. By using a precursor with a low gallium content, the gallium concentration in the metal oxide layer 13 can be reduced, thereby improving the reliability of the transistor. Furthermore, by using a precursor with a low aluminum content, the aluminum concentration in the metal oxide layer 13 can be reduced, thereby improving the crystallinity of the metal oxide layer 13.

[0083] Furthermore, as the precursor used in this embodiment, it is preferable to use a precursor purified by performing distillation (also referred to as rectification or precision distillation) two or more times. Using such a precursor facilitates the formation of a metal oxide film with few impurities, which is preferable. Performing distillation multiple times can further suppress impurities originating from the starting materials used in the precursor production from remaining in the precursor, which is preferable. Note that the present invention is not limited to the above, and a precursor purified by a single distillation, i.e., simple distillation, may also be used. Simple distillation can reduce production costs, which is preferable. By performing distillation one or more times, the aluminum content of the indium-containing precursor can be reduced to 100 ppm or less, 1 ppm or less, or 1 ppb (0.001 ppm) or less.

[0084] As an oxidizing agent, ozone (O ３ ), oxygen (O ２ ), water (H ２ O), hydrogen peroxide (H ２ O ２ The oxidizing agent preferably contains at least one of ozone and oxygen. By using ozone, oxygen, or the like that does not contain hydrogen as the oxidizing agent, the amount of hydrogen mixed into the metal oxide layer 13 can be reduced.

[0085] In this specification and the like, unless otherwise specified, when ozone, oxygen, or water is used as an oxidizing agent, it is not limited to the gas or molecular state, but also includes the plasma state, radical state, or ion state.

[0086] The substrate heating temperature when introducing the precursor into the reaction chamber is preferably set to a temperature corresponding to the decomposition temperature of the precursor. Here, in the case of a thermal ALD method using triethylindium as the precursor containing indium, for example, the substrate heating temperature can be 100°C or higher and 350°C or lower, preferably 150°C or higher and 300°C or lower. Note that, when the crystal portion 12 is provided, the substrate heating temperature can be room temperature (25°C) or higher and 300°C or lower, preferably room temperature or higher and 200°C or lower, more preferably room temperature or higher and 150°C or lower.

[0087] By forming the metal oxide layer 13 by the ALD method, it is possible to form a crystalline metal oxide layer 13 by utilizing the crystalline portions 12 during the process of forming the metal oxide layer 13, particularly during the temperature drop process. The crystal growth in the metal oxide layer 13 will be described in detail below.

[0088] First, the crystal growth mechanism of indium oxide according to one embodiment of the present invention will be described using interfacial energy. The interfacial energy refers to the energy loss due to the formation of an interface between a crystalline structure and an amorphous structure, and can be calculated using the following formula:

[0089]

[0090] Here, E ｉｎｔｅｒｆａｃｅ is the interfacial energy, and E ａｍｏ is the total energy of the amorphous structure model, and E ｃｒｙ is the total energy of the single crystal structure model, and E ａ／ｃ is the total energy of the model in which the amorphous structure and the single crystal structure are bonded. S is the bond cross-sectional area, which is the contact area between the amorphous structure and the single crystal structure in the model in which the amorphous structure and the single crystal structure are bonded.

[0091] The smaller the interfacial energy, the smaller the energy loss due to crystallization. Therefore, crystals grow to maximize the surface area of ​​the crystal plane with low interfacial energy. In other words, the rate of crystal growth is fast in the direction along the crystal plane with low interfacial energy, and slow in the direction perpendicular to the crystal plane with low interfacial energy.

[0092] As a model in which an amorphous structure and a single crystal structure are bonded, first, a model including a single crystal structure is prepared. Next, a molecular dynamics calculation is performed using an NVT ensemble, and half of the model is melted at 5000 K. Next, a molecular dynamics calculation is performed, and the structure of the half-melted model is optimized. From the above, a model in which an amorphous structure and a single crystal structure are bonded can be created. Next, a molecular dynamics calculation is performed using an NVT ensemble, and the created model is rapidly cooled to 200 K, and the energy in the equilibrium state is calculated. The calculated energy is used as the total energy of the model in which an amorphous structure and a single crystal structure are bonded.

[0093] The molecular dynamics calculation can be performed using LAMMPS, which is open source software. In this embodiment, M3GNet (see Non-Patent Document 3) is used as the molecular force field.

[0094] Table 1 shows the interfacial energies of the (100), (110), (1-10), and (111) planes of an indium oxide crystal.

[0095]

[0096] From Table 1, it can be seen that indium oxide has the smallest interfacial energy in the (111) plane, the next smallest in the (110) plane, the next smallest in the (1-10) plane, and the largest in the (100) plane. Since the (111) plane has the smallest interfacial energy in indium oxide, it is presumed that indium oxide crystals grow while maximizing the surface area of ​​the (111) plane. In other words, it is presumed that indium oxide has a preferred orientation in the (111) plane. Since indium oxide is a cubic crystal, it can also be said that it has a preferred orientation in the {111} plane.

[0097] The above is a description of the mechanism of crystal growth of indium oxide. In one embodiment of the present invention, this mechanism is utilized to form a crystalline metal oxide layer 13.

[0098] Because the metal oxide layer 13 is a thin film, the length of the metal oxide layer 13 in the direction along the surface of the underlayer 11 is greater than the film thickness of the metal oxide layer 13. To increase the grain size of the crystals, it is preferable that the rate of crystal growth in the direction along the surface of the underlayer 11 is faster than the rate of crystal growth in the film thickness direction of the metal oxide layer 13. Here, the direction along the surface of the underlayer 11 is defined as a first direction, and the film thickness direction of the metal oxide layer 13 is defined as a second direction. Note that, because the film thickness direction of the metal oxide layer 13 is perpendicular to the surface of the underlayer 11, the second direction is perpendicular to the first direction.

[0099] As described above, since the crystal growth of indium oxide is anisotropic with respect to the crystal plane, it is necessary to control the crystal plane or crystal orientation of the crystal grains. Therefore, in one embodiment of the present invention, by providing the crystal portion 12, crystal growth in a first direction and crystal growth in a second direction are caused, thereby forming crystal grains. In this specification and the like, crystal growth in the first direction may be referred to as first crystal growth, and crystal growth in the second direction may be referred to as second crystal growth. In other words, crystal grains are formed in the metal oxide layer by the first crystal growth and the second crystal growth.

[0100] From the above-mentioned mechanism, it is presumed that the crystal growth rate in the direction along the {111} plane is faster than the crystal growth rate in the direction perpendicular to the {111} plane. Therefore, it is preferable that the first direction is parallel to the direction along the {111} plane and the second direction is parallel to the direction perpendicular to the {111} plane. This makes it possible to make the crystal growth rate in the first direction faster than the crystal growth rate in the second direction, thereby enabling the crystal grain size to be increased.

[0101] Note that the direction perpendicular to the {111} plane is the direction belonging to <111> (individual <111> direction), and the direction along the {111} plane is the direction perpendicular to the direction belonging to <111>. Examples of the direction belonging to <111> include the

[111] direction, the [-111] direction, the [1-11] direction, and the [11-1] direction. Examples of the direction perpendicular to the

[111] direction include the [-1-12] direction and the [5-1-4] direction. Examples of the direction perpendicular to the [-111] direction include the

[110] direction and the

[101] direction. In this specification and the like, the direction belonging to <111> may be simply referred to as the <111> direction.

[0102] To enhance the crystallinity of the metal oxide layer 13 by utilizing the crystalline portions 12, it is preferable that the crystalline structures of the crystalline portions 12 and the crystal grains are cubic. This facilitates epitaxial growth (homoepitaxial growth or heteroepitaxial growth) or axial growth using the crystalline portions 12 as seeds or nuclei. Furthermore, it is preferable that the crystalline portions 12 are provided so that the <111> orientation is parallel to the direction perpendicular to the surface of the underlayer 11. This allows the second direction to be parallel to the <111> orientation. Therefore, providing the crystalline portions 12 allows first and second crystal growth to occur in the metal oxide layer 13. In FIG. 1B , the first direction is indicated by a dashed arrow, and the second direction is indicated by a solid arrow. The same applies to the dashed arrows and solid arrows shown in FIGS. 1C , 2C , and 2D .

[0103] With the above configuration, the rate of the first crystal growth is faster than the rate of the second crystal growth, and the crystal grains 13c grow along the surface of the base film 11. When the crystal grains 13c grow in the first direction, they also grow slightly in the second direction (see FIG. 1B ). Furthermore, the regions 13a of the metal oxide layer 13 other than the crystal grains 13c are regions with low crystallinity, for example, regions with an amorphous structure.

[0104] By increasing the rate of the first crystal growth, the area of ​​the crystal grains 13c in plan view can be increased before the formation of crystal nuclei in the region 13a, thereby promoting the enlargement of the crystal grain size and enabling the formation of crystal grains 13c having a grain size in the aforementioned range.

[0105] After the crystal grains 13c have grown sufficiently in the first direction, they grow in the second direction (see FIG. 1C). As a result, a crystalline metal oxide layer 13 can be formed. Note that when indium oxide is used as the crystal portion 12, it may be difficult to clearly detect the boundary between the crystal portion 12 and the metal oxide layer 13.

[0106] Note that crystal growth in the metal oxide layer 13 is not limited to the process of forming the metal oxide layer 13, but may occur due to a process involving heating the substrate (such as a film formation process) or heat treatment after the formation of the metal oxide layer 13.

[0107] The metal oxide layer 13 can also be formed by sputtering, chemical vapor deposition (CVD), molecular beam epitaxy (MBE), or pulsed laser deposition (PLD). For example, when the metal oxide layer 13 is formed by sputtering, the sputtering gas may be hydrogen (H ２ ) is preferably contained. By introducing hydrogen when forming the metal oxide layer 13 by sputtering, it is possible to form a metal oxide layer 13 with low crystallinity. Furthermore, when forming the metal oxide layer 13, it is possible to suppress the generation of crystal nuclei or to promote the disappearance of crystal nuclei. Note that, as the sputtering gas, a single gas of a noble gas (typically argon) or oxygen, or a mixed gas of a noble gas and oxygen, etc. can also be used.

[0108] Furthermore, when the metal oxide layer 13 is formed by sputtering, the substrate temperature during deposition of the metal oxide layer 13 is preferably from room temperature (25°C) to 250°C, more preferably from room temperature to 200°C, and even more preferably from room temperature to 140°C. For example, a substrate temperature of from room temperature to 140°C is preferred because it increases productivity. It is also preferred because it can suppress the generation of crystal nuclei. Alternatively, the metal oxide layer can be deposited at room temperature or without heating the substrate.

[0109] After forming the metal oxide layer 13 with low crystallinity by sputtering, it is preferable to perform heat treatment. The heat treatment can be performed, for example, at a temperature of 250°C or higher and 650°C or lower, preferably 300°C or higher and 500°C or lower, and more preferably 320°C or higher and 450°C or lower. The heat treatment can promote crystal growth from the crystal portion 12 and increase the size of the crystal grains in the metal oxide layer 13. As described above, the metal oxide layer 13 with crystallinity can be formed. Furthermore, the heat treatment can reduce excess hydrogen in the metal oxide layer 13.

[0110] The heat treatment is performed in a nitrogen gas or inert gas atmosphere, or in an atmosphere containing 10 ppm (0.001%) or more, 1% or more, or 10% or more of an oxidizing gas. For example, when the heat treatment is performed in a mixed atmosphere of nitrogen gas and oxygen gas, the oxygen gas concentration is preferably about 20%. The heat treatment may also be performed under reduced pressure. Alternatively, after the heat treatment in a nitrogen gas or inert gas atmosphere, the heat treatment can be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas to compensate for the desorbed oxygen.

[0111] The gas used in the heat treatment is preferably highly purified. For example, the amount of moisture contained in the gas used in the heat treatment is 1 ppb (1×10 −３ ppm) or less, and 0.1 ppb (1 x 10 −４ ppm) or less, and 0.05 ppb (5 × 10 −５By performing the heat treatment using a highly purified gas, it is possible to prevent moisture and the like from being taken into the metal oxide layer 13 as much as possible.

[0112] The heating device used for the heat treatment is not particularly limited, and may be a device that heats the workpiece by thermal conduction or thermal radiation from a heating element such as a resistance heating element. For example, an electric furnace or an RTA (Rapid Thermal Anneal) device such as an LRTA (Lamp Rapid Thermal Anneal) device or a GRTA (Gas Rapid Thermal Anneal) device can be used. The LRTA device is a device that heats the workpiece by radiation of light (electromagnetic waves) emitted from a lamp such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high-pressure sodium lamp, or a high-pressure mercury lamp. The GRTA device is a device that performs heat treatment using high-temperature gas.

[0113] After forming the metal oxide layer 13, the metal oxide layer 13 may be processed. Fig. 1D shows a configuration in which a part of the metal oxide layer 13 in a region that does not overlap with the crystal portion 12 is removed, leaving the crystal portion 12. Fig. 1E shows a configuration in which the crystal portion 12 is removed when the metal oxide layer 13 including the region that overlaps with the crystal portion 12 is removed.

[0114] The above is a description of the method for forming a metal oxide layer using the crystalline portion.

[0115] Although the method for forming a metal oxide layer using a crystalline portion having a cubic crystal structure has been described above, the present invention is not limited to this. A metal oxide layer can also be formed using a crystalline portion having a crystal structure other than a cubic crystal structure.

[0116] A method for forming a metal oxide layer when the crystal structure of the crystal portion is hexagonal or trigonal will be described with reference to FIGS. 2A to 2F. FIG.

[0117] An undercoat film 11 is prepared. Fig. 2A illustrates an undercoat film 11 having a flat surface. For the undercoat film 11, the above description can be referred to.

[0118] Next, a crystalline portion 12 having a hexagonal or trigonal crystal structure is formed on the underlayer 11 (see FIG. 2A ). Examples of the crystalline portion 12 having a hexagonal or trigonal crystal structure include zinc oxide, indium gallium oxide (In—Ga oxide), indium gallium zinc oxide (In—Ga—Zn oxide, also referred to as IGZO), indium aluminum zinc oxide (In—Al—Zn oxide, also referred to as IAZO), and indium tin zinc oxide (In—Sn—Zn oxide, also referred to as ITZO (registered trademark)). In—Ga—Zn oxide is preferably used as the crystalline portion 12. In this case, the crystalline portion 12 contains indium, gallium, zinc, and oxygen. Specifically, the crystalline portion 12 preferably has a composition of In:Ga:Zn=1:1:1 (atomic ratio) or a composition therearound, or a composition of In:Ga:Zn=1:3:2 (atomic ratio) or a composition therearound.

[0119] In—Ga—Zn oxide, In—Sn—Zn oxide, and the like tend to have a CAAC structure. When an oxide having a CAAC structure is used for the crystal portion 12, the c-axis direction of the crystal portion 12 is perpendicular or approximately perpendicular to the surface of the base film 11. Therefore, by using an oxide that tends to have a CAAC structure for the crystal portion 12, it is possible to improve the controllability of the crystal plane of the crystal grains of the metal oxide layer 13.

[0120] Subsequently, a metal oxide layer 13 is formed on the underlayer 11 so as to cover the crystal portion 12 (see FIG. 2B). The method for forming the metal oxide layer 13 can be referred to as described above.

[0121] By providing the crystal portion 12 so that the c-axis direction of the crystal portion 12 is perpendicular or approximately perpendicular to the surface of the base film 11, it is possible to form crystal grains 13c whose <111> orientation is perpendicular or approximately perpendicular to the surface of the base film 11 (see Figure 2B).

[0122] Subsequently, first and second crystal growths occur in the metal oxide layer 13. As described above, the second direction is parallel to the <111> orientation, so the rate of the first crystal growth is faster than the rate of the second crystal growth, and the crystal grains 13c grow along the surface of the underlayer 11. When the crystal grains 13c grow in the first direction, they also grow slightly in the second direction (see FIG. 2C ).

[0123] After the crystal grains 13c have grown sufficiently in the first direction, they grow in the second direction (see FIG. 2D). As a result, the metal oxide layer 13 having crystallinity can be formed.

[0124] After forming the metal oxide layer 13, the metal oxide layer 13 may be processed. FIG. 2E shows a configuration in which a portion of the metal oxide layer 13 not overlapping with the crystal portion 12 is removed, leaving the crystal portion 12. FIG. 2F shows a configuration in which the crystal portion 12 is removed when removing the metal oxide layer 13 including the portion overlapping with the crystal portion 12. When processing the metal oxide layer 13 to form one or more metal oxide layers, it is preferable to provide one crystal portion 12 for one or more metal oxide layers. This reduces variations in the crystallinity of the multiple metal oxide layers, suppresses variations in transistor characteristics, and improves transistor reliability. Note that two or more crystal portions 12 may be provided for one metal oxide layer.

[0125] Although the above describes a method for forming a metal oxide layer on a base film having a flat surface, the present invention is not limited to this. A crystalline metal oxide layer can be formed even when the base film has, for example, grooves, depressions, openings, trenches, slits, etc. Furthermore, a crystalline metal oxide layer can be formed even when the base film has, for example, protrusions, projections, etc.

[0126] This embodiment mode can be combined with other embodiment modes as appropriate. In addition, in this specification, when a plurality of configuration examples are shown in one embodiment mode, the configuration examples can be combined as appropriate.

[0127] Embodiment 2 In this embodiment, a semiconductor device according to one embodiment of the present invention will be described. The semiconductor device according to one embodiment of the present invention includes a transistor. For example, a semiconductor layer including a channel formation region of the transistor can be formed using the metal oxide layer according to one embodiment of the present invention.

[0128] <Configuration Example of Semiconductor Device> A configuration example of a semiconductor device according to one embodiment of the present invention will be described with reference to FIGS. 3A to 3D . FIG. 3A is a plan view of a semiconductor device including a transistor 50A. FIG. 3B is a cross-sectional view of a portion indicated by a dashed-dotted line A1-A2 in FIG. 3A , which is also a cross-sectional view of the transistor 50A in the channel length direction. FIG. 3C is a cross-sectional view of a portion indicated by a dashed-dotted line B1-B2 in FIG. 3A , which is also a cross-sectional view of the transistor 50A in the channel width direction. FIG. 3D is a cross-sectional view of a portion indicated by a dashed-dotted line B3-B4 in FIG. 3A . Note that some elements are omitted in the plan view of FIG. 3A for clarity. Some elements may also be omitted in the subsequent plan views. FIGS. 4A to 5C each show an enlarged cross-sectional view of the transistor 50A in the channel length direction.

[0129] The transistor 50A has a conductive layer 71, an insulating layer 72 on the conductive layer 71, an insulating layer 73 on the insulating layer 72, an insulating layer 74 on the insulating layer 73, a semiconductor layer 51 on the insulating layer 74, conductive layers 54a and 54b on the semiconductor layer 51, an insulating layer 52 on the semiconductor layer 51, and a conductive layer 53 on the insulating layer 52.

[0130] In the transistor 50A, the conductive layer 53 functions as a first gate electrode (also referred to as a top gate electrode), and the insulating layer 52 functions as a first gate insulating layer. The conductive layer 71 functions as a second gate electrode (also referred to as a bottom gate electrode), and the insulating layers 74, 73, and 72 each function as a second gate insulating layer. The conductive layer 54a functions as one of a source electrode and a drain electrode, and the conductive layer 54b functions as the other of the source electrode and the drain electrode.

[0131] The semiconductor layer 51 of the transistor 50A has a channel formation region and a source region and a drain region sandwiching the channel formation region. At least a portion of the channel formation region overlaps with the conductive layer 53. The source region overlaps with the conductive layer 54a, and the drain region overlaps with the conductive layer 54b. The source region and the drain region can be interchanged. The source region and the drain region are n-type regions (low-resistance regions) with a higher carrier concentration than the channel formation region.

[0132] The metal oxide of one embodiment of the present invention can be used for the semiconductor layer 51. In this case, the transistor 50A can be an OS transistor. The semiconductor layer 51 can be formed using the metal oxide layer 13 described in the above embodiment.

[0133] An OS transistor has an oxygen vacancy (V Ｏ If there are impurities and oxygen vacancies, the electrical characteristics may be easily changed and reliability may be reduced. Ｏ H) may generate electrons that serve as carriers. Therefore, if oxygen vacancies are present in the channel formation region of the oxide semiconductor, the OS transistor is likely to have normally-on characteristics. Therefore, it is preferable that oxygen vacancies and impurities are reduced as much as possible in the channel formation region of the oxide semiconductor. In other words, it is preferable that the carrier concentration of the channel formation region of the oxide semiconductor is reduced and the channel formation region of the oxide semiconductor is made i-type (intrinsic) or substantially i-type.

[0134] On the other hand, the source and drain regions of an OS transistor have more oxygen vacancies than the channel formation region. Ｏ The source and drain regions of an OS transistor are preferably n-type regions having a high carrier concentration and low resistance compared to a channel formation region, and the source and drain regions of the OS transistor preferably have a high carrier concentration and low resistance due to a high concentration of H or an impurity such as hydrogen, nitrogen, or a metal element.

[0135] 3C , in a cross-sectional view of the transistor 50A in the channel width direction, a curved surface may be formed between the side surface of the semiconductor layer 51 and the top surface of the semiconductor layer 51. That is, the end of the side surface and the end of the top surface may be curved. By adopting such a shape, it is possible to suppress the concentration of an electric field between the side surface and the top surface, thereby suppressing fluctuations in the transistor characteristics.

[0136] 3B and the like show an example in which the semiconductor layer 51 has a single-layer structure. Note that the semiconductor layer 51 can have a stacked structure of two or more layers. FIG. 4A shows a configuration in which the semiconductor layer 51 has a three-layer structure including a semiconductor layer 51_1, a semiconductor layer 51_2 on the semiconductor layer 51_1, and a semiconductor layer 51_3 on the semiconductor layer 51_2. Note that the semiconductor layer 51 may have a configuration in which one of the semiconductor layer 51_1 and the semiconductor layer 51_3 is not provided.

[0137] The semiconductor layer 51_2 is formed using a metal oxide (typically indium oxide) that can be used for the semiconductor layer 51. The semiconductor layer 51_2 corresponds to the metal oxide layer 13 described in Embodiment 1.

[0138] The semiconductor layer 51_3 is preferably made of a metal oxide whose conduction band minimum is located closer to the vacuum level than the conduction band minimum of the semiconductor layer 51_2. In this case, the semiconductor layer 51_2 can mainly function as a current path (channel). That is, the semiconductor layer 51_2 has a channel formation region on the surface on the semiconductor layer 51_3 side and in the vicinity thereof.

[0139] The above-described structure can reduce carriers trapped at the interface of the semiconductor layer 51_2 and in the vicinity thereof. In addition, the channel can be located away from the surface of the insulating layer 52, thereby reducing the influence of surface scattering. This can increase the field-effect mobility of the transistor.

[0140] Examples of metal oxides that can be used for the semiconductor layer 51_3 include In—Ga oxide, indium zinc oxide (In—Zn oxide, also referred to as IZO (registered trademark)), In—Sn oxide, indium titanium oxide (In—Ti oxide), In—Al—Zn oxide, In—Ga—Zn oxide, In—Sn—Zn oxide, indium titanium zinc oxide (In—Ti—Zn oxide), and indium tin oxide containing silicon oxide (also referred to as ITSO). Alternatively, zinc oxide, aluminum zinc oxide (Al—Zn oxide, also referred to as AZO), and aluminum tin oxide (Al—Sn oxide) can be used.

[0141] Specifically, the In—Zn oxide used in the semiconductor layer 51_3 can have a composition of In:Zn=1:1 (atomic ratio) or a composition thereabout, an In:Zn=2:1 (atomic ratio) or a composition thereabout, or an In:Zn=4:1 (atomic ratio) or a composition thereabout. Specifically, the IGZO used in the semiconductor layer 51_3 can have a composition of In:Ga:Zn=1:1:1 (atomic ratio) or a composition thereabout, an In:Ga:Zn=1:3:2 (atomic ratio) or a composition thereabout, or an In:Ga:Zn=1:3:4 (atomic ratio) or a composition thereabout. Note that a composition thereabout includes a range of ±30% of the desired atomic ratio.

[0142] The crystallinity of the metal oxide included in the semiconductor layer 51_3 is not particularly limited. For example, the semiconductor layer 51_3 may include one or more of an amorphous semiconductor (a semiconductor having an amorphous structure), a single-crystal semiconductor (a semiconductor having a single-crystal structure), or a semiconductor having crystallinity other than single crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor having a crystalline region in part).

[0143] The semiconductor layer 51_1 is preferably made of a metal oxide applicable to the semiconductor layer 51_3. This can suppress diffusion of impurities from structures formed below the semiconductor layer 51_1 to the semiconductor layer 51_2. Furthermore, the semiconductor layer 51_1 can serve as a seed or nucleus to enhance the crystallinity of the semiconductor layer 51_2. The semiconductor layer 51_1 corresponds to the base film 11 or the crystalline portion 12 described in the first embodiment.

[0144] An insulating layer 61 is provided on the conductive layer 54a and the conductive layer 54b, and an insulating layer 62 is provided on the insulating layer 61. The upper surface of the insulating layer 62 may be planarized. An opening 63 is formed in the insulating layer 62 and the insulating layer 61, reaching the insulating layer 73 and the semiconductor layer 51, and the opening 63 overlaps the region between the conductive layer 54a and the conductive layer 54b. In a plan view, the side surface of the opening 63 in the conductive layer 54a is aligned or approximately aligned with the side surface of the opening 63 in the insulating layer 62. Similarly, the side surface of the opening 63 in the conductive layer 54b is aligned or approximately aligned with the side surface of the opening 63 in the insulating layer 62.

[0145] The sidewalls of the openings 63 may be perpendicular or approximately perpendicular to the upper surface of the insulating layer 73, or may be tapered. Tapering the sidewalls of the openings 63 improves the coverage of the insulating layer 52 and the like provided in the openings 63, and reduces defects such as voids.

[0146] The thickness of the semiconductor layer 51 in the region overlapping with the opening 63 may be reduced (see FIG. 4B). Similarly, when the semiconductor layer 51 has a stacked structure, the thickness of the semiconductor layer 51_2 in the region overlapping with the opening 63 may be reduced. In this case, the semiconductor layer 51_3 is separated by the opening 63 (see FIG. 4C). The reduction in the thickness of the semiconductor layer 51 in the region overlapping with the opening 63 increases the effective channel length. Therefore, the short channel effect can be reduced, and a semiconductor device with good electrical characteristics can be provided.

[0147] The insulating layer 52 and the conductive layer 53 are disposed in the opening 63. In the opening 63, the insulating layer 52 contacts the top surface of the insulating layer 73, the side surface of the insulating layer 74, the side surface and top surface of the semiconductor layer 51, the side surface of the conductive layer 54a, the side surface of the conductive layer 54b, the side surface of the insulating layer 61, and the side surface of the insulating layer 62. The conductive layer 53 covers the side surface of the insulating layer 74 and the side surface and top surface of the semiconductor layer 51 via the insulating layer 52. The height of the top surface of the conductive layer 53 is equal to or approximately equal to the height of the upper end of the insulating layer 52 and the height of the top surface of the insulating layer 62, respectively.

[0148] In this specification, "having the same or substantially the same height" refers to a configuration in which the heights from a reference surface (e.g., a flat surface such as a substrate surface) are the same or substantially the same in cross-sectional view. For example, in the case of having two layers (here, layer A and layer B) with different heights relative to the reference surface, the difference in height between the top surface of layer A and the top surface of layer B is 10 nm or less, and this is also referred to as "having the same or substantially the same height."

[0149] The insulating layer 52 can be made of an insulating material described in the section [Insulating Layer] below.

[0150] 3B and 3C show an example in which the insulating layer 52 has a single layer structure. The insulating layer 52 can have a stacked structure of two or more layers. In this case, the insulating layer 52 is preferably formed of two or more types of films. By forming the insulating layer 52 into two or more types of films, multiple functions can be imparted to the insulating layer 52. Examples of the functions of the insulating layer 52 include a function of extracting excess oxygen from the semiconductor layer 51, a function of extracting hydrogen from the semiconductor layer 51, and a function of suppressing diffusion of hydrogen into the semiconductor layer 51.

[0151] The insulating layer 52 is preferably a thin film. For example, by setting the thickness of the insulating layer 52 to be 1 nm or more and 20 nm or less, preferably 3 nm or more and 10 nm or less, the subthreshold swing value (also referred to as the S value) can be reduced. The S value refers to the amount of change in gate voltage when the drain current is changed by one order of magnitude while the drain voltage is kept constant in the subthreshold region.

[0152] The insulating layer 52 can have, for example, a four-layer structure in which an aluminum oxide film, a hafnium oxide film, a silicon oxide film, and a silicon nitride film are stacked in this order from the semiconductor layer 51 side. The thicknesses of the aluminum oxide film, the hafnium oxide film, the silicon oxide film, and the silicon nitride film are 1 nm, 2 nm, 2 nm, and 1 nm, respectively. Alternatively, the insulating layer 52 can have, for example, a four-layer structure in which an aluminum oxide film, a silicon oxide film, a hafnium oxide film, and a silicon nitride film are stacked in this order from the semiconductor layer 51 side. The thicknesses of the aluminum oxide film, the silicon oxide film, the hafnium oxide film, and the silicon nitride film are 1 nm, 2 nm, 2 nm, and 1 nm, respectively. With this structure, excess oxygen in the semiconductor layer 51 can be discharged to the insulating layer 52, thereby reducing the amount of excess oxygen in the semiconductor layer 51. Furthermore, hydrogen in the semiconductor layer 51 can be captured or fixed. Therefore, the electrical characteristics and reliability of the transistor 50A can be improved.

[0153] It is preferable to use the ALD process two or more times in forming the insulating layer 52 having a stacked structure of multiple insulating films. For example, it is preferable that two or more of the multiple insulating films included in the insulating layer 52 are formed using the ALD process. By forming at least two or more types of insulating films using the ALD process, it is possible to improve the coverage and film thickness uniformity of the insulating layer 52. Furthermore, it is possible to increase productivity by successively forming, for example, two or more types of insulating films using the ALD process.

[0154] 3A and 3C, the conductive layer 53 is preferably provided to extend in the channel width direction. With this configuration, when a plurality of transistors are provided, the conductive layer 53 functions as wiring.

[0155] The conductive layer 53 can be formed using a conductive material described in the section "Conductive Layer" below. The conductive layer 53 is preferably formed using a conductive material containing, for example, tungsten, copper, or aluminum as a main component. The conductive layer 53 may also have a stacked structure. For example, the conductive layer 53 can have a stacked structure of a titanium nitride film and a tungsten film on the titanium nitride film.

[0156] An insulating layer 83 is provided in contact with the lower surface of the insulating layer 72. The upper surface of the insulating layer 83 may be planarized. The insulating layer 83 functions as an interlayer film.

[0157] The conductive layer 71 is provided so as to be embedded in an opening formed in the insulating layer 83. The conductive layer 71 is disposed so as to overlap the semiconductor layer 51 and the conductive layer 53. As shown in Figures 3A and 3C, the conductive layer 71 is preferably provided so as to extend in the channel width direction. With this configuration, when a plurality of transistors are provided, the conductive layer 71 functions as wiring.

[0158] The threshold voltage (Vth) of the transistor 50A can be controlled by changing the potential applied to the conductive layer 71 independently of the potential applied to the conductive layer 53. In particular, applying a negative potential or a potential lower than the source potential to the conductive layer 71 can increase the Vth of the transistor 50A and reduce its off-state current. Therefore, applying a negative potential or a potential lower than the source potential to the conductive layer 71 can reduce the drain current when the potential applied to the conductive layer 53 is 0 V, compared to not applying a negative potential or a potential lower than the source potential to the conductive layer 71.

[0159] The conductive layer 71 can be formed using a conductive material described later in the section [Conductive Layer]. The conductive layer 71 is preferably formed using a conductive material containing, for example, tungsten, copper, or aluminum as a main component. The conductive layer 71 may also have a stacked structure. For example, the conductive layer 71 can have a stacked structure of a titanium nitride film in contact with the sidewall of the opening in the insulating layer 83 and a tungsten film on the titanium nitride film.

[0160] The insulating layer 74 is preferably made of an insulating material that releases oxygen when heat is applied. When heat is applied during the manufacturing process of the semiconductor device, the insulating layer 74 releases oxygen, and the oxygen can be supplied to the semiconductor layer 51. By supplying oxygen to the semiconductor layer 51, particularly to the channel formation region, oxygen vacancies or V Ｏ H can be reduced. Therefore, a highly reliable transistor can be obtained that exhibits favorable electrical characteristics.

[0161] The insulating layer 74 is preferably processed into an island shape, similar to the semiconductor layer 51. As a result, when multiple transistors 50A are provided, each transistor 50A has an insulating layer 74 of approximately the same size. As a result, the amount of oxygen supplied from the insulating layer 74 to the semiconductor layer 51 in each transistor 50A is approximately the same. Therefore, variation in the electrical characteristics of the transistors 50A within the substrate surface can be suppressed. Furthermore, by processing the insulating layer 74 into an island shape, at least a portion of the lower surface of the conductive layer 53 can be located below the lower surface of the semiconductor layer 51 (see FIG. 3C ). This allows the conductive layer 53 to be provided facing the upper and side surfaces of the semiconductor layer 51, allowing the electric field of the conductive layer 53 to act on the upper and side surfaces of the semiconductor layer 51.

[0162] The insulating film that becomes the insulating layer 74 corresponds to the base film 11 described in embodiment 1. The crystal portion 12 described in embodiment 1 may be located between the insulating layer 74 and the semiconductor layer 51. Furthermore, the crystal portion 12 described in embodiment 1 may be removed when the metal oxide layer 13 is processed to form the semiconductor layer 51.

[0163] The conductive layers 54a and 54b can be formed using the conductive materials described in the section "Conductive Layer" below. In particular, it is preferable to use a conductive material that is resistant to oxidation, a material that maintains conductivity even when absorbing oxygen, or a conductive material that has a function of suppressing oxygen diffusion for the conductive layers 54a and 54b. Examples of such a conductive material include a conductive material containing nitrogen and a conductive material containing oxygen (also referred to as an oxide conductor). This can suppress a decrease in the conductivity of the conductive layers 54a and 54b.

[0164] It is particularly preferable to use an oxide conductor for the conductive layer 54a and the conductive layer 54b. For example, it is particularly preferable to use In—Sn oxide, silicon-containing ITO (In—Sn—Si oxide, also referred to as ITSO), In—Zn oxide, In—Ti oxide, or the like. These materials are preferable because they are more likely to maintain conductivity even after absorbing oxygen than materials composed of metal elements (also referred to as metal materials). In addition, these materials are preferable because they can reduce the contact resistance between the conductive layer 54a and the semiconductor layer 51 and the contact resistance between the conductive layer 54b and the semiconductor layer 51.

[0165] Furthermore, when an oxide conductor is used for the conductive layers 54a and 54b, the conductive layer 54a may function as one of the source and drain regions, and the conductive layer 54b may function as the other of the source and drain regions. This allows the semiconductor layer 51 to be i-type (intrinsic) or substantially i-type. In other words, it is not necessary to separately form an i-type (intrinsic) or substantially i-type region and a low-resistance n-type region in the semiconductor layer 51. Therefore, even when the distance between the conductive layer 54a and the conductive layer 54b is short, a channel formation region can be provided, and a transistor exhibiting good electrical characteristics can be obtained. Therefore, miniaturization or high integration of a semiconductor device can be achieved.

[0166] The conductive layers 54a and 54b may be formed using a metal nitride, such as tantalum nitride or titanium nitride.

[0167] Alternatively, the conductive layers 54a and 54b may each have a stacked structure. FIG. 5A shows an example in which the conductive layer 54a has a two-layer structure including a conductive layer 54a1 in contact with the semiconductor layer 51 and a conductive layer 54a2 on the conductive layer 54a1, and the conductive layer 54b has a two-layer structure including a conductive layer 54b1 in contact with the semiconductor layer 51 and a conductive layer 54b2 on the conductive layer 54b1. The conductive layers 54a1 and 54b1 may be made of the above-mentioned conductive materials, and the conductive layers 54a2 and 54b2 may be made of a conductive material with higher conductivity. For example, ITO or ITSO may be used for the conductive layers 54a1 and 54b1, and tungsten may be used for the conductive layers 54a2 and 54b2. Alternatively, tantalum nitride or titanium nitride may be used for the conductive layers 54a1 and 54b1, and tungsten may be used for the conductive layers 54a2 and 54b2. This can increase the conductivity of the conductive layers 54a and 54b.

[0168] The insulating layer 62 is preferably made of an insulating material that releases oxygen when heat is applied. When heat is applied during the manufacturing process of the semiconductor device, the insulating layer 62 releases oxygen, and the oxygen can be supplied to the semiconductor layer 51 through the insulating layer 52. By supplying oxygen to the semiconductor layer 51, particularly to the channel formation region, oxygen vacancies or V Ｏ H can be reduced. Therefore, a highly reliable transistor can be obtained that exhibits favorable electrical characteristics.

[0169] Since the insulating layer 62 functions as an interlayer film, it is preferable to use a material with a low dielectric constant. By using a material with a low dielectric constant for the interlayer film, it is possible to reduce the parasitic capacitance that occurs between wirings. It is also preferable to reduce the concentration of impurities such as water and hydrogen in the insulating layer 62. This makes it possible to suppress the intrusion of impurities such as hydrogen or water into the channel formation region of the semiconductor layer 51. For example, silicon oxide or silicon oxynitride can be used as the insulating layer 62.

[0170] An insulating layer 84 is provided in contact with the upper surface of insulating layer 62, the upper end of insulating layer 52, and the upper surface of conductive layer 53, an insulating layer 85 is provided on insulating layer 84, and an insulating layer 86 is provided on insulating layer 85. An insulating layer 82 is provided below insulating layer 83 and conductive layer 71, and an insulating layer 81 is provided below insulating layer 82. Insulating layer 81 is provided on a substrate (not shown). Insulating layers 81, 82, 84, 85, and 86 function as interlayer films.

[0171] At least one of the insulating layer 81, the insulating layer 82, the insulating layer 72, the insulating layer 73, the insulating layer 61, the insulating layer 84, and the insulating layer 85 preferably functions as a barrier insulating layer against hydrogen. At least one of the insulating layer 81, the insulating layer 82, the insulating layer 72, the insulating layer 73, the insulating layer 61, the insulating layer 84, and the insulating layer 85 preferably functions as a barrier insulating layer against impurities. At least one of the insulating layer 81, the insulating layer 82, the insulating layer 72, the insulating layer 73, the insulating layer 61, the insulating layer 84, and the insulating layer 85 preferably functions as a barrier insulating layer against oxygen. Note that it is not necessarily necessary to provide all of the insulating layer 81, the insulating layer 82, the insulating layer 72, the insulating layer 73, the insulating layer 61, the insulating layer 84, and the insulating layer 85. As long as the insulating layer has sufficient barrier properties against hydrogen, impurities, oxygen, and the like, it can be formed by appropriately selecting from the insulating layer 81, the insulating layer 82, the insulating layer 72, the insulating layer 73, the insulating layer 61, the insulating layer 84, and the insulating layer 85. For example, it is also possible to form the insulating layer 83 and the conductive layer 71 in contact with the upper surface of the insulating layer 81 without providing the insulating layer 82.

[0172] It is preferable that the insulating layer 81, the insulating layer 72, the insulating layer 61, and the insulating layer 85 have a function of suppressing hydrogen diffusion. For example, it is preferable that the insulating layer 81, the insulating layer 72, the insulating layer 61, and the insulating layer 85 be made of silicon nitride, which has a higher hydrogen barrier property.

[0173] The insulating layer 82, the insulating layer 73, and the insulating layer 84 preferably have a function of capturing or fixing hydrogen. For example, aluminum oxide may be used for the insulating layer 82 and the insulating layer 84. Furthermore, for example, hafnium oxide, which is a material with a high relative dielectric constant (high-k), is preferably used for the insulating layer 73 that functions as the second gate insulating layer.

[0174] By providing the insulating layer 81 having the function of suppressing hydrogen diffusion under the transistor 50A, it is possible to suppress diffusion of hydrogen from layers below the transistor 50A. Furthermore, by providing the insulating layer 82 having the function of capturing or fixing hydrogen, it is possible to capture or fix hydrogen contained in the insulating layer 83 or the like in the insulating layer 82. This makes it possible to reduce excess hydrogen in the semiconductor layer 51 and its vicinity.

[0175] Furthermore, by providing the insulating layer 72 having the function of suppressing hydrogen diffusion under the semiconductor layer 51, it is possible to suppress diffusion of hydrogen from below the semiconductor layer 51. Furthermore, by providing the insulating layer 73 having the function of capturing or fixing hydrogen, hydrogen contained in the insulating layer 74 or the like can be captured or fixed by the insulating layer 73. This makes it possible to reduce excess hydrogen in the semiconductor layer 51 and its vicinity.

[0176] Furthermore, by providing an insulating layer 61 having the function of suppressing the diffusion of hydrogen so as to cover the semiconductor layer 51, the conductive layer 54a, the conductive layer 54b, etc., it is possible to suppress the diffusion of hydrogen from the insulating layer 62 to the semiconductor layer 51, the conductive layer 54a, the conductive layer 54b, etc.

[0177] Furthermore, by providing the insulating layer 85 having the function of suppressing hydrogen diffusion over the transistor 50A, it is possible to suppress diffusion of hydrogen from above the transistor 50A. Furthermore, by providing the insulating layer 84 having the function of capturing or fixing hydrogen, hydrogen contained in the insulating layer 62 or the like can be captured or fixed in the insulating layer 84. This makes it possible to reduce excess hydrogen in the semiconductor layer 51 and its vicinity.

[0178] In this way, by using a structure in which the transistor 50A is surrounded by barrier insulating layers against hydrogen from above and below, it is possible to suppress diffusion of hydrogen into the oxide semiconductor, and to reduce the V Ｏ H can be reduced, thereby improving the electrical characteristics and reliability of the transistor 50A.

[0179] Note that when the hydrogen concentration in the insulating layer 62 is low, a structure without the insulating layer 61 can be used. In this structure, the insulating layer 62 is in contact with the conductive layers 54a and 54b. Note that by using an oxide conductor for the conductive layers 54a and 54b, the conductive layers 54a and 54b can maintain conductivity even when they are in contact with the insulating layer 62 containing oxygen and absorb oxygen.

[0180] The insulating layer 84 is preferably formed by sputtering in an atmosphere containing oxygen gas, which allows oxygen to be added to the insulating layer 62.

[0181] The insulating layers 83, 62, and 86 each preferably have a lower dielectric constant than the insulating layer 73. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance generated between wirings can be reduced. For example, the insulating layers 83, 62, and 86 can each be made of a material with a low dielectric constant as described in the "Insulating Layer" section below. Silicon oxide and silicon oxynitride are particularly preferred because they are thermally stable. Materials such as silicon oxide, silicon oxynitride, and silicon oxide with vacancies are also preferred because they allow for the easy formation of regions containing excess oxygen.

[0182] Openings reaching the conductive layer 54a are provided in the insulating layers 86, 85, 84, 62, and 61, and the conductive layer 76a is provided in the openings. Openings reaching the conductive layer 54b are provided in the insulating layers 86, 85, 84, 62, and 61, and the conductive layer 76b is provided in the openings. The conductive layer 76a contacts the conductive layer 54a, and the conductive layer 76b contacts the conductive layer 54b. The height of the upper surfaces of the conductive layers 76a and 76b is the same or approximately the same as the height of the upper surface of the insulating layer 86. The lower portion of the conductive layer 76a may be formed so as to be embedded in the conductive layer 54a. Similarly, the lower portion of the conductive layer 76b may be formed so as to be embedded in the conductive layer 54b.

[0183] The conductive layers 76a and 76b function as vias that connect a wiring or the like provided over the transistor 50A to the source or drain of the transistor 50A. The conductive layers 76a and 76b can be formed using a conductive material described later in [Conductive Layer]. For the conductive layers 76a and 76b, a conductive material containing tungsten, copper, or aluminum as a main component is preferably used, for example.

[0184] The conductive layer 76a and the conductive layer 76b may each have a stacked structure. Figure 5B shows an example in which the conductive layer 76b has a two-layer structure consisting of a conductive layer 76b1 in contact with the sidewalls and bottom of the opening 64 provided in the insulating layer 62, the insulating layer 61, etc., and a conductive layer 76b2 on the conductive layer 76b1. Figure 5C shows an example in which the conductive layer 76b has a two-layer structure consisting of a conductive layer 76b1 provided on the bottom of the opening 64 provided in the insulating layer 62, the insulating layer 61, etc., and a conductive layer 76b2 on the conductive layer 76b1. For example, titanium or titanium nitride can be used as the conductive layer 76b1, and tungsten, copper, or aluminum can be used as the conductive layer 76b2. The structure of the conductive layer 76a can be referenced for the structure of the conductive layer 76b.

[0185] An insulating layer can be provided between the sidewall of the opening of the insulating layer 62 or the like and the conductive layer 76a. A barrier insulating layer applicable to the insulating layer 61 or the like can be used as the insulating layer. For example, silicon nitride can be used as the insulating layer. This can prevent impurities such as water and hydrogen contained in the insulating layer 62 or the like from being mixed into the semiconductor layer 51 through the conductive layer 76a. Also, oxygen contained in the insulating layer 62 can be prevented from being absorbed by the conductive layer 76a. Note that the insulating layer can be provided between the sidewall of the opening of the insulating layer 62 or the like and the conductive layer 76b.

[0186] 3A to 3D show a configuration in which the insulating layer 52 is provided in contact with the sidewall of the opening 63, but the present invention is not limited to this. For example, an insulating layer may be provided between the sidewall of the opening 63 and the insulating layer 52.

[0187] Modifications of the semiconductor device described in <Configuration Example of Semiconductor Device> will be described with reference to Figures 6A to 7C. Figure 6A is a plan view of a semiconductor device including a transistor 50A, and corresponds to the plan view shown in Figure 3A. Figures 6B to 6D are cross-sectional views of the semiconductor device, and correspond to the cross-sectional views shown in Figures 3B to 3D, respectively. Figures 7A to 7C are enlarged cross-sectional views of the transistor 50A in the channel length direction.

[0188] 6A to 6D differs from the transistor 50A shown in Figures 1A to 1D mainly in that the semiconductor device has a sidewall-shaped insulating layer 58. Hereinafter, differences from the description of the above-mentioned <Configuration Example of Semiconductor Device> will be mainly described, and overlapping portions will be referred to and may not be described again.

[0189] In the transistor 50A shown in FIGS. 6A to 6D , in a plan view, the side surface of the insulating layer 58 facing the conductive layer 53 is aligned or substantially aligned with the side surface of the conductive layer 54a facing the conductive layer 53. Also, the side surface of the conductive layer 54b facing the conductive layer 53 is aligned or substantially aligned with the side surface of the conductive layer 54a facing the conductive layer 53 (see FIG. 7A ). The sidewall-shaped insulating layer 58 can be formed on the conductive layer that will become the conductive layer 54a and the conductive layer 54b by anisotropic etching. Furthermore, the conductive layer can be divided using the insulating layer 58 as a mask to form the conductive layer 54a and the conductive layer 54b. That is, the insulating layer 58 that functions as a mask can be formed in a self-aligned manner. This reduces the number of masks and steps in the manufacturing process of the semiconductor device. Therefore, productivity of the semiconductor device can be improved. Furthermore, the distance between the source and the drain can be shortened, thereby shortening the channel length. Therefore, the frequency characteristics of the transistor 50A can be improved. In this way, miniaturization of the semiconductor device can provide a semiconductor device with improved operating speed.

[0190] 7A shows an example in which the conductive layers 54a and 54b have a single-layer structure. Note that each of the conductive layers 54a and 54b may have a stacked structure.

[0191] In FIG. 7B , the conductive layer 54a has a two-layer structure consisting of a conductive layer 54a1 and a conductive layer 54a2. In a plan view, the side surface of the conductive layer 54a2 facing the conductive layer 53 is aligned or substantially aligned with the sidewall of the opening 63. The conductive layer 54a1 has a portion in contact with the insulating layer 52 and a portion in contact with the insulating layer 58. The sidewall-shaped insulating layer 58 can be formed on the conductive layer that will become the conductive layer 54a1 and the conductive layer 54b1 by removing the portions of the conductive layer that will become the conductive layer 54a2 and the conductive layer 54b2 that overlap with the opening 63, followed by forming an insulating film that will become the insulating layer 58, and then anisotropically etching the insulating layer 58. Furthermore, the conductive layer can be divided using the insulating layer 58 to form the conductive layer 54a1 and the conductive layer 54b1. Using a material that functions as a barrier insulating layer against oxygen for the insulating layer 58 can prevent the side surface of the conductive layer 54a2 from being oxidized. The configuration of the conductive layer 54b can be referred to the configuration of the conductive layer 54a.

[0192] In the structure shown in FIG. 7B , an insulating layer can be further provided between the sidewall of the opening 63 and the insulating layer 58. FIG. 7C illustrates a structure in which an insulating layer 59 is provided between the sidewall of the opening 63 and the insulating layer 58. In a plan view, the side surface of the conductive layer 54a2 facing the conductive layer 53 is aligned or substantially aligned with the side surface of the insulating layer 59 facing the conductive layer 53. The top surface of the conductive layer 54a2 has a portion in contact with the insulating layer 59. The sidewall-shaped insulating layer 59 can be formed on the conductive layer that will become the conductive layer 54a2 and the conductive layer 54b2 by anisotropic etching. Furthermore, the conductive layer can be divided using the insulating layer 59 as a mask to form the conductive layer 54a2 and the conductive layer 54b2. This further shortens the distance between the source and drain, thereby shortening the channel length. This improves the frequency characteristics of the transistor 50A. By miniaturizing the semiconductor device in this way, a semiconductor device with improved operating speed can be provided.

[0193] The transistor included in the semiconductor device of one embodiment of the present invention is not limited to the transistor 50A. For example, a transistor having a planar structure or a GAA (Gate All Around) structure (including a GAA nanosheet structure) may also be included.

[0194] <Constituent Materials of Semiconductor Device> Materials that can be used in the semiconductor device of this embodiment will be described below. Note that each layer constituting the semiconductor device of this embodiment may have a single-layer structure or a multilayer structure.

[0195] [Insulating Layer] It is preferable to use an inorganic insulating film for each of the insulating layers (insulating layer 52, insulating layer 58, insulating layer 59, insulating layer 61, insulating layer 62, insulating layer 72, insulating layer 73, insulating layer 74, insulating layer 81, insulating layer 82, insulating layer 83, insulating layer 84, insulating layer 85, insulating layer 86, etc.) included in the semiconductor device. Examples of inorganic insulating films include an oxide insulating film, a nitride insulating film, and an oxynitride insulating film. Examples of oxide insulating films include a silicon oxide film, an aluminum oxide film, a magnesium oxide film, a gallium oxide film, a germanium oxide film, a yttrium oxide film, a zirconium oxide film, a lanthanum oxide film, a neodymium oxide film, a hafnium oxide film, a tantalum oxide film, a cerium oxide film, a gallium zinc oxide film, and an oxide film containing aluminum and hafnium. Examples of nitride insulating films include a silicon nitride film and an aluminum nitride film. Examples of the oxynitride insulating film include a silicon oxynitride film, an aluminum oxynitride film, a gallium oxynitride film, an yttrium oxynitride film, and a hafnium oxynitride film. An organic insulating film may also be used for an insulating layer included in a semiconductor device.

[0196] For example, as transistors become more miniaturized and highly integrated, problems such as leakage current may occur due to thinner gate insulating layers. Using a high-k material for the gate insulating layer enables lower voltages during transistor operation while maintaining the physical film thickness. Furthermore, it also enables thinner equivalent oxide thickness (EOT) of the gate insulating layer. On the other hand, using a material with a low dielectric constant for the insulating layer that functions as an interlayer film can reduce the parasitic capacitance that occurs between wirings. Therefore, it is preferable to select materials according to the function of the insulating layer. Note that materials with a low dielectric constant also have high dielectric strength.

[0197] Examples of materials with a high relative dielectric constant include aluminum oxide, gallium oxide, hafnium oxide, tantalum oxide, zirconium oxide, oxides containing hafnium and zirconium, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.

[0198] Examples of materials with a low dielectric constant include inorganic insulating materials such as silicon oxide and silicon oxynitride, and resins such as polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, and acrylic resin. Other inorganic insulating materials with a low dielectric constant include silicon oxide containing fluorine, silicon oxide containing carbon, and silicon oxide containing carbon and nitrogen. Another example is silicon oxide having vacancies. These silicon oxides may contain nitrogen.

[0199] Furthermore, a material capable of exhibiting ferroelectricity may be used for an insulating layer of a semiconductor device. As the material capable of exhibiting ferroelectricity, an oxide containing one or both of hafnium and zirconium is preferably used. Examples of such oxides include metal oxides such as hafnium oxide, zirconium oxide, and hafnium zirconium oxide. Furthermore, as the material capable of exhibiting ferroelectricity, a material obtained by adding an element J1 (here, the element J1 is one or more selected from the other of hafnium and zirconium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) to a metal oxide containing one of hafnium and zirconium may be used.

[0200] Furthermore, adding a Group 3 element in the periodic table to an oxide containing one or both of hafnium and zirconium increases the oxygen vacancy concentration in the oxide, making it easier to form crystals with an orthorhombic crystal structure. This is preferable because it increases the proportion of crystals with an orthorhombic crystal structure and increases remanent polarization. On the other hand, adding too much of the Group 3 element may reduce the crystallinity of the oxide, making it difficult to exhibit ferroelectricity. Therefore, the content of the Group 3 element in the oxide containing one or both of hafnium and zirconium is preferably 0.1% to 10%, more preferably 0.1% to 5%, and even more preferably 0.1% to 3%. Here, the content of the Group 3 element refers to the ratio of the number of atoms of the Group 3 element to the sum of the number of atoms of all metal elements contained in the layer. The Group 3 element is preferably one or more selected from scandium, lanthanum, and yttrium, and more preferably one or both of lanthanum and yttrium.

[0201] Furthermore, examples of materials that may have ferroelectricity include metal nitrides containing nitrogen and at least one of element M1 and element M2. Here, element M1 is one or more selected from aluminum, gallium, indium, etc. Furthermore, element M2 is one or more selected from boron, scandium, yttrium, lanthanum, cerium, neodymium, europium, titanium, zirconium, hafnium, vanadium, niobium, tantalum, chromium, etc. Furthermore, examples of materials that may have ferroelectricity include materials in which element M3 is added to the above metal nitrides. Furthermore, element M3 is one or more selected from magnesium, calcium, strontium, zinc, cadmium, etc.

[0202] Furthermore, materials that can have ferroelectricity include SrTaO ２ N and BaTaO ２ Perovskite-type oxynitrides such as N, GaFeO with κ-alumina structure ３ Furthermore, examples of materials that can have ferroelectricity include lead titanate (PbTiO ＸPiezoelectric ceramics having a perovskite structure, such as barium strontium titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), bismuth ferrite (BFO), or barium titanate, may also be used.

[0203] In the above description, metal oxides and metal nitrides are used as examples, but the present invention is not limited to these. For example, a material in which nitrogen is added to the above-mentioned metal oxides, or a material in which oxygen is added to the above-mentioned metal nitrides, may also be used.

[0204] Furthermore, as a material capable of exhibiting ferroelectricity, for example, a mixture or compound of a plurality of materials selected from the materials listed above can be used. However, since the crystal structure (characteristics) of the materials listed above may change depending not only on the film formation conditions but also on various processes, in this specification and the like, a material that exhibits ferroelectricity is not only called a ferroelectric but also called a material capable of exhibiting ferroelectricity.

[0205] In this specification, a layer of a material that may have ferroelectricity may be referred to as a ferroelectric layer, a metal oxide layer, or a metal nitride film. Also, in this specification, a device having such a ferroelectric layer, a metal oxide layer, or a metal nitride film may be referred to as a ferroelectric device.

[0206] The ferroelectric layer preferably contains crystals having an orthorhombic crystal structure, since this allows ferroelectricity to be exhibited. The crystal structure of the crystals contained in the ferroelectric layer may be one or more selected from the group consisting of tetragonal, orthorhombic, monoclinic, and hexagonal. The ferroelectric layer may also have an amorphous structure. In this case, the ferroelectric layer may have a composite structure having an amorphous structure and a crystalline structure.

[0207] A metal oxide containing one or both of hafnium and zirconium is also an insulating material that has a function of capturing or fixing hydrogen. Therefore, by using a metal oxide containing one or both of hafnium and zirconium for at least a part of a gate insulating layer, hydrogen contained in the oxide semiconductor layer can be captured or fixed, thereby reducing the hydrogen concentration in the oxide semiconductor layer. Furthermore, a transistor including the gate insulating layer can function as a ferroelectric field effect transistor (FeFET).

[0208] Furthermore, a transistor using a metal oxide can have stable electrical characteristics by being surrounded by an insulating layer that has a function of suppressing the permeation of impurities and oxygen. The insulating layer that has a function of suppressing the permeation of impurities and oxygen can be, for example, a single-layer or stacked insulating layer containing one or more elements selected from boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum. Specifically, the insulating layer that has a function of suppressing the permeation of impurities and oxygen can be made of a metal oxide such as aluminum oxide, magnesium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide; a nitride such as aluminum nitride or silicon nitride; or an oxynitride such as silicon oxynitride.

[0209] Specifically, examples of materials for the insulating layer that have the function of suppressing the permeation of impurities such as water and hydrogen, and oxygen, include metal oxides such as aluminum oxide, magnesium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, and oxides containing aluminum and hafnium. Examples of nitrides include aluminum nitride, aluminum titanium nitride, and silicon nitride. Examples of oxynitrides include silicon oxynitride. Examples of materials for the insulating layer that have the function of suppressing the permeation of oxygen include gallium oxide.

[0210] An insulating layer such as a gate insulating layer that is in contact with or near an oxide semiconductor layer preferably has a region containing excess oxygen. For example, when an insulating layer having a region containing excess oxygen is in contact with or near an oxide semiconductor layer, oxygen vacancies in the oxide semiconductor layer can be reduced.

[0211] An insulating layer provided in contact with or near an oxide semiconductor layer is preferably a barrier insulating layer against hydrogen. When the insulating layer has a barrier property against hydrogen, diffusion of hydrogen into the oxide semiconductor layer can be suppressed. The barrier insulating layer against hydrogen can also be said to have a function of suppressing diffusion of hydrogen.

[0212] Examples of insulating materials having the function of capturing or fixing hydrogen include metal oxides such as oxides containing hafnium, oxides containing magnesium, oxides containing aluminum, oxides containing aluminum and hafnium, oxides containing hafnium and silicon, etc. These metal oxides may further contain zirconium, such as oxides containing hafnium and zirconium.

[0213] An insulating layer having the function of capturing or fixing hydrogen preferably has an amorphous structure. In a metal oxide having an amorphous structure, some oxygen atoms have dangling bonds, which enhances the ability to capture or fix hydrogen. Therefore, when the insulating layer has an amorphous structure, the function of capturing or fixing hydrogen can be enhanced.

[0214] By making the insulating layer an amorphous structure, it is possible to suppress the formation of crystal grain boundaries. By suppressing the formation of crystal grain boundaries, it is possible to improve the flatness of the insulating layer. This makes it possible to uniformize the film thickness distribution of the insulating layer and reduce areas with extremely thin film thickness, thereby improving the breakdown voltage of the insulating layer. It is also possible to uniformize the film thickness distribution of a film provided on the insulating layer. Furthermore, by suppressing the formation of crystal grain boundaries in the insulating layer, it is possible to reduce leakage current caused by defect levels at the crystal grain boundaries. Therefore, the insulating layer can function as an insulating film with low leakage current.

[0215] The ability to capture or fix a corresponding substance can also be said to have the property of making it difficult for the corresponding substance to diffuse. Therefore, the ability to capture or fix a corresponding substance can be rephrased as barrier properties.

[0216] In this specification and the like, a barrier insulating layer refers to an insulating layer having barrier properties. The barrier properties refer to a property that makes it difficult for a corresponding substance to diffuse (also referred to as a property that makes it difficult for a corresponding substance to permeate, a property that the permeability of a corresponding substance is low, or a function that suppresses the diffusion of a corresponding substance). Note that hydrogen when described as a corresponding substance refers to at least one of, for example, a hydrogen atom, a hydrogen molecule, and a substance bonded to hydrogen such as a water molecule or OH − . Furthermore, unless otherwise specified, impurities when described as a corresponding substance refer to impurities in a channel formation region or a semiconductor layer, and include, for example, hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N ２ O, NO, NO ２ The term "oxygen" refers to at least one of an oxygen atom, an oxygen molecule, etc., when described as a corresponding substance.

[0217] Examples of materials for the barrier insulating layer against hydrogen include aluminum oxide, magnesium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxides containing hafnium and zirconium, silicon nitride, and silicon oxynitride.

[0218] The inorganic insulating layers cited as insulating layers having the function of capturing or fixing hydrogen and insulating layers having the function of suppressing hydrogen diffusion also have barrier properties against oxygen. Examples of materials for the oxygen barrier insulating layer include oxides containing one or both of aluminum and hafnium, magnesium oxide, gallium zinc oxide, silicon nitride, and silicon oxynitride. Examples of oxides containing one or both of aluminum and hafnium include aluminum oxide, hafnium oxide, oxides containing aluminum and hafnium, and oxides containing hafnium and silicon.

[0219] [Conductive Layer] The conductive layers (conductive layer 53, conductive layer 54a, conductive layer 54a1, conductive layer 54a2, conductive layer 54b, conductive layer 54b1, conductive layer 54b2, conductive layer 71, conductive layer 76a, conductive layer 76b, conductive layer 76b1, conductive layer 76b2, etc.) included in the semiconductor device preferably contain a metal element selected from aluminum, chromium, copper, silver, gold, platinum, zinc, tantalum, nickel, titanium, iron, cobalt, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, palladium, iridium, strontium, lanthanum, etc., or an alloy containing any of the above metal elements, or an alloy combining any of the above metal elements. The alloy containing any of the above metal elements may be a nitride of the alloy or an oxide of the alloy. For example, it is preferable to use tantalum nitride, titanium nitride, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, oxide containing lanthanum and nickel, etc. Furthermore, semiconductors with high electrical conductivity, typified by polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicide may also be used.

[0220] Nitrogen-containing conductive materials, such as nitrides containing tantalum, nitrides containing titanium, nitrides containing molybdenum, nitrides containing tungsten, nitrides containing ruthenium, nitrides containing tantalum and aluminum, or nitrides containing titanium and aluminum; oxygen-containing conductive materials, such as ruthenium oxide, oxides containing strontium and ruthenium, or oxides containing lanthanum and nickel; and materials containing metal elements, such as titanium, tantalum, or ruthenium, are preferred because they are conductive materials that are resistant to oxidation, have a function of suppressing oxygen diffusion, or maintain conductivity even after absorbing oxygen. Examples of oxygen-containing conductive materials include indium oxide containing tungsten oxide, indium oxide containing titanium oxide, ITO, indium tin oxide containing titanium oxide, ITSO, In—Zn oxide, and indium zinc oxide containing tungsten oxide. In this specification and the like, a conductive film formed using a conductive material containing oxygen may be referred to as an oxide conductive film.

[0221] Furthermore, a plurality of conductive layers formed from the above materials may be stacked. For example, a stacked structure may be formed by combining the above-described material containing a metal element and a conductive material containing oxygen. A stacked structure may be formed by combining the above-described material containing a metal element and a conductive material containing nitrogen. A stacked structure may be formed by combining the above-described material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen.

[0222] When a metal oxide is used for the channel formation region of a transistor, the conductive layer that functions as a gate electrode preferably has a stacked structure that combines a material containing the metal element and a conductive material containing oxygen. In this case, the conductive material containing oxygen is preferably provided on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen desorbed from the conductive material is easily supplied to the channel formation region.

[0223] [Substrate] Substrates on which transistors are formed can include, for example, insulating substrates, semiconductor substrates, or conductive substrates. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (such as yttria-stabilized zirconia substrates), and resin substrates. Examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, or compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. Examples of semiconductor substrates include those having an insulating region within the semiconductor substrate, such as an SOI (Silicon-On-Insulator) substrate. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Examples of substrates include substrates having a metal nitride or a metal oxide. Examples of substrates include a substrate having a conductor or semiconductor provided on an insulating substrate, a substrate having a conductor or insulator provided on a semiconductor substrate, and a substrate having a semiconductor or insulator provided on a conductive substrate. Alternatively, a substrate provided with elements may be used. The elements provided on the substrate include a capacitor element, a resistor element, a switch element, a light-emitting element, a memory element, and the like.

[0224] The above is the description of the materials that can be used for the semiconductor device of this embodiment mode.

[0225] This embodiment mode can be combined with other embodiment modes as appropriate. In addition, in this specification, when a plurality of configuration examples are shown in one embodiment mode, the configuration examples can be combined as appropriate.

[0226] Embodiment 3 In this embodiment, an indium oxide film that can be used for a metal oxide layer of one embodiment of the present invention and a semiconductor layer of a transistor of one embodiment of the present invention will be described.

[0227] In this specification and the like, indium oxide having at least a crystalline portion or a crystalline region in a film is referred to as crystalline indium oxide (crystal IO) or crystalline indium oxide (crystalline IO). Examples of crystalline IO or crystalline IO include single-crystalline indium oxide, polycrystalline indium oxide, and microcrystalline indium oxide.

[0228] Indium oxide is a semiconductor material having physical properties that are completely different from those of oxide semiconductors such as In—Ga—Zn oxide (hereinafter also referred to as IGZO) and zinc oxide.

[0229] The carrier concentration dependence of the Hall mobility of indium oxide, silicon, and IGZO will be explained. FIG. 8A shows the carrier concentration dependence of the Hall mobility of silicon (Si) and indium oxide (InO Ｘ ) and FIG. 8B is a schematic diagram showing the carrier concentration dependence of the hole mobility for IGZO.

[0230] First, IGZO tends to exhibit higher hole mobility as the carrier concentration increases, as shown by the arrows in Figure 8B. On the other hand, indium oxide tends to exhibit higher hole mobility as the carrier concentration decreases, as shown by the arrows in Figure 8A (see Non-Patent Document 4). This trend is similar to that of silicon; the lower the dopant (impurity) concentration in the material, the less impurity scattering there is and the higher the hole mobility. In other words, the higher the purity and intrinsic indium oxide, the higher the hole mobility. From these results, it can be said that indium oxide, unlike IGZO, is a material with physical properties similar to those of silicon. Note that the characteristics of indium oxide shown in Figure 8A are assumed to be single crystal. Therefore, when indium oxide is non-single crystal (e.g., polycrystalline), the characteristics may differ from those shown in Figure 8A.

[0231] 8A, the range R1 of low carrier concentration has extremely high hole mobility, and therefore can be said to be a range of carrier concentration suitable for, for example, a channel formation region of a transistor. For example, in the case of indium oxide, the range R1 is a range where the carrier concentration value is 1×10 １５ cm −３ The range includes, for example, 1×10 １４ cm−３ That's it, 1 x 10 １８ cm −３ By sufficiently reducing the carrier concentration, the Hall mobility value can be increased to 270 cm ２ It is expected that the resistance can be increased to about / (V·s).

[0232] In addition, in indium oxide, the region where the carrier concentration is in the range R1 may contain an element that lowers the carrier concentration. Examples of elements that lower the carrier concentration include magnesium, calcium, zinc, cadmium, and copper. By substituting these elements for indium, the carrier concentration can be lowered. Examples of elements that lower the carrier concentration include nitrogen, phosphorus, arsenic, and antimony. For example, by substituting nitrogen, phosphorus, arsenic, or antimony for oxygen, the carrier concentration can be lowered.

[0233] On the other hand, the range R2 with a high carrier concentration has a low electrical resistance, and can be said to be a range of carrier concentrations suitable for, for example, the source and drain regions of a transistor, a resistor, or a transparent conductive film. ２０ cm −３ The range includes, for example, 1×10 １９ cm −３ That's it, 1 x 10 ２２ cm −３ By increasing the carrier concentration sufficiently, the resistivity can be reduced to 1×10 −４ It is expected that the resistivity can be reduced to Ω·cm or less.

[0234] In addition, in indium oxide, the region where the carrier concentration is in the range R2 may contain an element that increases the carrier concentration. For example, it is preferable that the indium oxide contains an element that is common to the source electrode and drain electrode of the transistor. Examples of elements that increase the carrier concentration include titanium, zirconium, hafnium, tantalum, tungsten, molybdenum, tin, silicon, and boron. In particular, it is more preferable to use an element whose oxide has conductive or semiconducting properties. Note that, as a method for supplying an element that increases the carrier concentration, a method of forming a film containing the element and diffusing it, ion implantation, ion doping, plasma immersion ion implantation, or plasma treatment can be used. Note that, unless otherwise specified in this specification, the presence or absence of mass separation is not limited. For example, in this specification, a method of supplying ions after mass separation is referred to as an ion implantation method, and a method of supplying ions without mass separation is referred to as an ion doping method.

[0235] In this way, indium oxide uses a region with a low carrier concentration as the channel formation region of a transistor, and a region with a high carrier concentration as the source and drain regions of the transistor. In other words, indium oxide can be said to be an oxide capable of valence electron control. Note that IGZO may experience strain in the source and drain regions due to stress from electrodes in contact with the IGZO, resulting in the formation of n-type regions. On the other hand, unlike IGZO, indium oxide is capable of valence electron control, and therefore does not require strain to be formed in the film as with IGZO. Less strain in the film is expected to improve reliability. For example, by separately creating a region with a carrier concentration in the range R1 shown in FIG. 8A and a region with a carrier concentration in the range R2 in the indium oxide film, a so-called n-i-n junction (a junction between an n-type region, an i-type region, and an n-type region) can be created. Note that valence electron control in transistors using silicon is generally known. On the other hand, valence electron control in transistors using indium oxide is a novel technical concept that would not normally be conceived.

[0236] By using the above technical concept, the transistor having indium oxide in this specification and the like has two or more, preferably three or more, more preferably four or more, and most preferably five of the following characteristics (1) to (5): (1) high on-current (in other words, high mobility); (2) low off-current; (3) normally-off operation; (4) high reliability; and (5) high cutoff frequency (fT). For example, the transistor having indium oxide in this specification and the like has high mobility, low off-current, and is normally-off operation. The transistor has high mobility and is different from a normally-on transistor.

[0237] In addition, a semiconductor being i-type can be rephrased as having the same Fermi level (Ef) and intrinsic Fermi level (Ei) (Ef = Ei). As shown in FIG. 8B, in IGZO, the lower the carrier concentration, the smaller the hole mobility. Therefore, when Ef = Ei is finally achieved, the carriers disappear (in other words, the physical properties become similar to those of an insulator), and the transistor may no longer function. On the other hand, in indium oxide, as shown in FIG. 8A, the lower the carrier concentration, the larger the hole mobility. When Ef = Ei is finally achieved, the hole mobility is maximized. In other words, a transistor containing indium oxide can achieve high field-effect mobility by setting Ef = Ei. Note that a transistor containing indium oxide is likely to be normally-off due to its low carrier concentration. Therefore, a transistor containing indium oxide can be normally-off and achieve high field-effect mobility.

[0238] Note that normally-off refers to a state in which no current flows through a transistor when no potential is applied to the gate or when the gate-source voltage is 0 V. Furthermore, normally-off can be evaluated by the threshold voltage (Vth) or shift value (Vsh) of the transistor. Unless otherwise specified, Vth is calculated by a constant current method. More specifically, Vth refers to a state in which the value of drain current (Id) × channel length (L) ÷ channel width (W) in the Id-Vg characteristics of a transistor is 1 nA (1 × 10 −９ A). Vsh is the gate voltage (Vg) when the drain current (Id) in the Id-Vg characteristic of the transistor is expressed logarithmically and the tangent of the maximum slope is Id = 1 pA (1 × 10 −１２ The gate voltage (Vg) is the intersection point between the line of Id = 1 pA and the line extrapolated from two points where the slope of Id is maximum when Id is expressed logarithmically in the Id-Vg characteristics of the transistor. For example, if either or both of Vth and Vsh are zero or a positive value, the transistor can be considered to be normally-off.

[0239] In addition, in a transistor containing indium oxide, in order to make the semiconductor i-type, that is, to achieve Ef = Ei, the film structure in contact with the indium oxide film is important. For example, in a transistor containing indium oxide, a film structure in which a silicon oxide film in contact with the indium oxide film, a hafnium oxide film, and a silicon nitride film are stacked is exemplified. By using this film structure, a semiconductor device with high reliability and Ef = Ei can be obtained.

[0240] In the above film configuration, a film containing oxygen, such as a silicon oxynitride film, an aluminum oxide film, or a gallium oxide film, can be used instead of the silicon oxide film. Also, in the above film configuration, a silicon oxynitride film or the like can be used instead of the silicon nitride film. The hafnium oxide film, which is located closer to the indium oxide film than the silicon nitride film, functions as a gettering site for hydrogen.

[0241] The above film configuration can also be considered as a stacked structure of a film (e.g., a silicon oxide film) capable of supplying oxygen to the indium oxide film from the indium oxide film side, a film (e.g., a hafnium oxide film) capable of gettering hydrogen, and a film (e.g., a silicon nitride film) that suppresses the penetration of oxygen and hydrogen. With this configuration, oxygen vacancies in the indium oxide film are filled with oxygen in the silicon oxide film. Hydrogen in the indium oxide film is captured by the hafnium oxide film by heat treatment or the like. Furthermore, the provision of the silicon nitride film results in a film configuration that reduces the penetration of oxygen and hydrogen from the outside. That is, with the above film configuration, the indium oxide film can be made closer to i-type. Therefore, a transistor having the above-described indium oxide film has high field-effect mobility and high reliability.

[0242] Next, an indium oxide film applied to a transistor will be described. The indium oxide film preferably has crystallinity (i.e., has crystal grains). Examples of films having crystal grains include single-crystal films, polycrystalline films, and amorphous films containing crystal grains (also called microcrystalline films). In particular, the indium oxide film is preferably a polycrystalline film, and more preferably a single-crystal film. A single-crystal film does not have grain boundaries. Impurities (typically, insulating impurities, insulating oxides, etc.) that hinder carrier flow tend to segregate at grain boundaries. The use of a single-crystal film can suppress carrier scattering at grain boundaries, thereby realizing a transistor exhibiting high field-effect mobility. Furthermore, the use of a single-crystal film has the excellent effect of suppressing variations in transistor characteristics due to the grain boundaries.

[0243] Furthermore, polycrystalline films are preferable because they can reduce carrier scattering and exhibit high field-effect mobility compared to microcrystalline or amorphous films. When using a polycrystalline film, it is preferable to use a film with as large a crystal grain size as possible and with few crystal grain boundaries. Note that in a transistor using an indium oxide polycrystalline film, if there is no crystal grain boundary in the channel formation region or no crystal grain boundary is observed, the channel formation region is located within a single crystal region included in the polycrystalline film, and therefore the transistor can be considered to be using single-crystal indium oxide.

[0244] The crystallinity of indium oxide can be analyzed by, for example, XRD, TEM, or electron diffraction. Alternatively, the analysis may be performed by a combination of these methods.

[0245] In this specification and the like, a semiconductor layer in which no crystal grain boundary is observed in the channel formation region, a semiconductor layer in which the channel formation region is included in one crystal grain, or a semiconductor layer in which the crystal axis direction is the same in at least two regions in the channel formation region can be called a single crystal film. Also, a semiconductor layer in which, in the channel formation region, within one crystal grain, the direction of another crystal axis continuously changes around a certain crystal axis or a certain crystal orientation as the axis of rotation can be called a single crystal film.

[0246] The channel formation region refers to a region of the semiconductor layer that overlaps (or faces) the gate electrode via the gate insulating layer, and is located between the region in contact with the source electrode and the region in contact with the drain electrode. The current path in the channel formation region is the shortest distance between the source electrode and the drain electrode. Therefore, the crystal grains, crystal grain boundaries, crystal axes, crystal orientation, etc. in the channel formation region can be confirmed by observing a cross section including the semiconductor layer, the source electrode, and the drain electrode.

[0247] The indium oxide film in the channel formation region preferably has a lower impurity concentration. Impurities in the indium oxide film in the channel formation region can be a scattering source of carriers, which can lead to a decrease in field-effect mobility. These impurities can also hinder the crystal growth of the indium oxide film. Examples of impurities in the indium oxide film include boron and silicon. The indium oxide film preferably contains these impurities at concentrations of 0.1% or less, and more preferably 0.01% (100 ppm) or less. Carbon, hydrogen, and other elements may be contained in the film-forming gas or precursor during film formation, and may remain in the indium oxide film in greater amounts than the above-mentioned impurities.

[0248] The indium oxide film in the channel formation region may contain an element that can become the same trivalent cation as indium, as long as the crystal maintains a cubic crystal structure (bixbyite type). Examples of such an element include Group 13 elements of the periodic table, such as gallium and aluminum, and Group 3 elements of the periodic table. These elements exist mainly as trivalent cations in oxides, and therefore the carrier concentration of indium oxide can be maintained low.

[0249] In addition, the indium oxide film in this specification and the like has a high film density. ２ O ３ The film densities of the films are shown in Table 2.

[0250]

[0251] As shown in Table 2, the film density of the indium oxide film was evaluated at six levels, Sample 1 to Sample 6. In Table 2, Condition 1 is the condition of the base of the indium oxide film, Samples 1 to 3 are glass, Sample 4 is a SiOx film formed by sputtering, and Samples 5 and 6 are yttria-stabilized zirconia (YSZ). Condition 2 is the film formation condition of the indium oxide film, Samples 1 to 3 are film formation by sputtering (SP), and Samples 4 to 6 are film formation by ALD. Condition 3 is the heat treatment condition after the formation of the indium oxide film, with Sample 1, Sample 4, and Sample 5 being no heat treatment (as-deposited), Sample 2 being baked at 350°C in a CDA atmosphere, Sample 3 being baked at 650°C in a CDA atmosphere, and Sample 6 being baked at 250°C in a vacuum atmosphere.

[0252] In Table 2, CDA stands for clean dry air. It is preferable that the atmosphere used in the heat treatment (condition 3) after the formation of the indium oxide film contains as little hydrogen and water as possible. It is preferable to use a high-purity gas with a dew point of −60° C. or lower, preferably −100° C. or lower, as the atmosphere.

[0253] As shown in Table 2, the indium oxide film tends to have a higher film density when subjected to heat treatment compared to when not subjected to heat treatment (Sample 1, Sample 4, or Sample 5). This is because the heat treatment removes impurity elements (e.g., carbon, nitrogen, hydrogen, argon, etc.) from the film, thereby increasing the purity of the indium oxide film. Furthermore, as shown in Samples 5 and 6, the indium oxide film on YSZ has a film density of 7.00 g / cm. ３ The theoretical film density of an indium oxide film is 7.18 g / cm ３ In this specification, the range of the film density of the indium oxide film is 6.70 g / cm ３ 7.18g / cm or more ３ Preferably, it is 6.90 g / cm or less.３ 7.18g / cm or more ３ More preferably, it is 7.00 g / cm or less. ３ 7.18g / cm or more ３ The following is the result.

[0254] The film density can be evaluated by, for example, Rutherford backscattering spectroscopy (RBS) or X-ray reflectometry (XRR). Differences in film density can sometimes be evaluated by cross-sectional transmission electron microscope (TEM) images. In TEM observation, a high film density results in a dense (dark) transmission electron (TE) image, whereas a low film density results in a faint (bright) transmission electron (TE) image.

[0255] By using such an indium oxide film in a transistor, the field effect mobility of the transistor can be increased to 50 cm ２ / (V·s) or more, preferably 100 cm ２ / (V·s) or more, more preferably 150 cm ２ / (V·s) or more, more preferably 200 cm ２ / (V·s) or more, more preferably 250 cm ２ / (V·s) or more.

[0256] One of the features of an indium oxide film is that it has higher oxygen permeability (diffusibility) than an IGZO film. As shown in FIG. 8C, an indium oxide film (InO Ｘ Oxygen (O) diffusing into the indium oxide film passes through the indium oxide film and becomes oxygen molecules (O ２ ) and is released as water molecules (H ２ O) may be released in the film. Ｏ In the case where an indium oxide film is present, oxygen atoms diffuse to compensate for the oxygen vacancies. Since oxygen diffuses easily in the indium oxide film, it can be said that oxygen vacancies are more easily compensated for in the indium oxide film than in the IGZO film.

[0257] As described above, an indium oxide film can more easily reduce oxygen vacancies in the film than an IGZO film. Therefore, by using such an indium oxide film in a transistor, a transistor exhibiting extremely high reliability can be realized.

[0258] Furthermore, as shown in FIG. 8C, the indium oxide film diffuses hydrogen. Hydrogen that diffuses into the indium oxide film from the outside passes through the indium oxide film and becomes hydrogen molecules (H ２ ) or reacts with oxygen contained in the film and is released as water molecules. The oxygen and hydrogen diffuse in the indium oxide film by heat treatment. The temperature of the heat treatment is 200° C. or higher and 700° C. or lower, preferably 350° C. or higher and 650° C. or lower, and more preferably 400° C. or higher and 500° C. or lower.

[0259] A transistor using an indium oxide film is an accumulation-type transistor that uses electrons as majority carriers. Assuming that the carrier relaxation time is constant, the smaller the effective mass of the electrons (carriers), the higher the electron mobility. In other words, by using indium oxide, which has a small effective mass of electrons, for a transistor, the on-state current or field-effect mobility of the transistor can be increased.

[0260] Table 3 shows the results of single crystal indium oxide (here, In ２ O ３ ) and single-crystal silicon (Si). As shown in Table 3, indium oxide is characterized by a small effective mass of electrons and a large effective mass of holes. Indium oxide also has the characteristic that the effective mass of electrons is almost independent of the crystal orientation. Therefore, by using crystalline indium oxide in a transistor, a transistor with high field-effect mobility and high frequency characteristics (also called f characteristics) can be realized. Furthermore, since the effective mass of holes is large, a transistor with extremely small off-current can be realized. For example, by applying an indium oxide film to a vertical transistor, the off-current per 1 μm of channel width can be reduced to 1 fA (1×10) in an environment of 125° C. −１５ A) or less, or 1aA (1 x 10 −１８A) or less, and under room temperature (25°C) conditions, −１８ A) or less, or 1zA (1 x 10 −２１ Furthermore, as shown in Table 3, indium oxide has a smaller effective mass of electrons and a larger effective mass of holes than silicon, and therefore may be able to realize a transistor with higher field-effect mobility and lower off-state current than a Si transistor.

[0261]

[0262] It is preferable to provide a seed layer so as to be in contact with at least a portion of the crystalline indium oxide film. The seed layer is preferably made of a material containing crystals with a small difference in lattice constant (also called lattice mismatch) with indium oxide. This can improve the crystallinity of the indium oxide film. Note that a substrate (e.g., a single-crystal substrate) may be used as one of the layers in contact with at least a portion of the crystalline indium oxide film.

[0263] Here, the influence of lattice distortion on the effective mass of indium oxide will be explained using FIG. 9. FIG. 9A is a diagram showing the crystal structure of indium oxide, and FIG. 9B is a diagram explaining the influence of lattice distortion on the effective mass of indium oxide. FIG. 9B shows the results of calculating the change in effective mass when the lattice lengths of the a-axis and b-axis of the crystal structure of indium oxide are expanded or contracted (the c-axis length has an opposite tendency). From FIG. 9B, it is clear that the effective mass (m ｅ ＊ ), no significant change or anisotropy due to the direction or magnitude of the strain is observed. On the other hand, the effective mass of the hole (m ｈ ＊ ) shows a tendency for the strain to significantly lighten the charge carriers. This is presumably due to the shorter distance between oxygen atoms constituting the valence band, resulting in greater overlap of p-orbitals. Therefore, to reduce the off-current, it is desirable to minimize the introduction of lattice strain.

[0264] Here, the band gap, the effective mass of electrons, the effective mass of holes, V ＯThe amount of H, the migration barrier (O, H), the structural stability, and the mobility are shown in Table 4. The semiconductor material shown in Table 4 is indium oxide (hereinafter referred to as In ２ O ３ The semiconductor materials are In—Ga—Zn oxide (hereinafter may be referred to as IGZO), In—Ga—Zn oxide (hereinafter may be referred to as IGZO), and In—Zn oxide (hereinafter may be referred to as IZO). IGZO has a composition of In:Ga:Zn=1:1:1 [atomic ratio], for example, and IZO has a composition of In:Zn=2:1 [atomic ratio], for example. The symbol ○ in parentheses in Table 4 indicates that the semiconductor material is advantageous when used in a transistor, and the symbol △ indicates that there are concerns when using the semiconductor material in a transistor.

[0265]

[0266] From Table 4, in terms of band gap and effective mass of holes, IGZO, In ２ O ３ It is estimated that the off-state current is smaller in the order of In, IZO. Note that this is a comparison among the semiconductor materials shown in Table 4, and these semiconductor materials have a sufficiently small off-state current compared to silicon. ２ O ３ The barriers to oxygen and hydrogen transport are low in the order of In, IZO, and IGZO. ２ O ３ IGZO and IZO are superior to IZO in terms of structural stability. ２ O ３ It is presumed that In is more likely to release excess oxygen and hydrogen than other semiconductor materials, and is therefore superior in terms of normally-off transistors and reliability. ２ O ３ Higher mobility is expected in IZO compared to IGZO.

[0267] Here, hydrogen bonded to oxygen in indium oxide (hereinafter sometimes referred to as In—OH), V Ｏ H, V Ｏ , and oxygen located at stable sites (hereinafter sometimes referred to as exO) will be explained with reference to FIG. 10. FIG. 10A shows In—OH, V in an indium oxide crystal. Ｏ H, VＯ , and exO respectively, and FIG. 10B shows the charge of each element of In-OH. The results shown in FIGS. 10A and 10B are obtained by first-principles calculations. In FIG. 10A, Ec is the energy at the bottom of the conduction band, Ev is the energy at the top of the valence band, and Eg is the band gap. The band gap of indium oxide is set to 2.94 eV. The charge of each element shown in FIG. 10B is calculated by Bader charge analysis.

[0268] The first-principles electronic state calculations are performed using Quantum ESPRESSO, a first-principles electronic state calculation package. This package is based on density functional theory (DFT) using a plane wave basis and pseudopotentials. The Heyd-Scuseria-Ernzerhof (HSE) hybrid functional (HSE06) is used as the exchange-correlation functional. A norm-conserving pseudopotential is used. The cutoff energy of the wave function is set to 100 Ry, and the cutoff energy of the electron density is set to 400 Ry. Spin polarization is assumed to exist.

[0269] As shown in FIG. 10A, In—OH and V in indium oxide Ｏ It is suggested that both H and In form a shallow level near the bottom of the conduction band and become carriers. Specifically, the difference between Ec and the level is 0.25 eV for In—OH, and V Ｏ In the case of In—OH and V, the Fermi level is 0.12 eV. Ｏ H tends to have a valence of +1, and when the Fermi level is located between Ec and the level, In—OH and V Ｏ H tends to be neutral (zero valence). Therefore, In—OH and V in indium oxide Ｏ It is presumed that both In and H act as carrier sources. Furthermore, Fig. 10B suggests that hydrogen in In-OH exists as a cation.

[0270] In particular, VoH forms a shallower level than In—OH, suggesting that it becomes a more carrier-forming element. Ｏ is 0.42 eV, and V Ｏ forms a deep level, so VＯ This suggests that exO contained in single-crystal indium oxide does not form a level in the gap.

[0271] From the above, in order to reduce the carrier concentration in indium oxide having a single crystal structure, it is desirable to reduce the hydrogen concentration.

[0272] One method for evaluating the degree of lattice mismatch is to use the value of the lattice mismatch shown below. The lattice mismatch Δa [%] of the crystals of the formed film (here, the indium oxide film) with respect to the crystals of the seed layer is expressed as Δa = ((L １ -L ２ ) / L ２ ) × 100, where L １ is the length or lattice constant of the unit lattice vector of the crystal of the formed film, and L ２ is the length of the unit cell vector or the lattice constant of the crystal of the seed layer.

[0273] The smaller the absolute value of the lattice mismatch Δa between the seed layer and the indium oxide film, the more preferable, and it is most preferably 0. For example, Δa can be set to −5% or more and 5% or less, preferably −4% or more and 4% or less, more preferably −3% or more and 3% or less, and even more preferably −2% or more and 2% or less.

[0274] Here, the indium oxide crystal has a cubic crystal structure (bixbyite type). For example, the crystal of yttria-stabilized zirconia (YSZ) can have a cubic crystal structure (fluorite type). The lattice mismatch of the indium oxide crystal with the cubic YSZ crystal is in the range of −2% to 2%, and a single crystal film of indium oxide can be epitaxially grown on the YSZ substrate.

[0275] It should be noted that the crystal structure of the seed layer and the crystal structure of the indium oxide film may not necessarily have the same crystal system or crystal orientation. For example, a film having crystals of a hexagonal or trigonal structure may be used under an indium oxide film having crystals of a cubic structure. For example, by setting the crystal orientation of the surface of the seed layer to

[001] and the crystal orientation of the underside of the indium oxide film to

[111] , the requirements related to the crystal orientation necessary for epitaxial growth can be satisfied. Examples of hexagonal or trigonal crystals include wurtzite structure, YbFe ２ O ４ Type structure, Yb ２ Fe ３ O ７ YbFeFe alloys have the following structures: ２ O ４ Type structure or Yb ２ Fe ３ O ７ An example of a crystal having a crystalline structure is IGZO. It should be noted that a single crystal film of indium oxide can be formed not only on a YSZ substrate but also on an insulating film. On the other hand, it is difficult to form a single crystal film of silicon on an insulating film. Silicon crystals have a diamond structure. As such, indium oxide and silicon have similar properties in terms of single crystal. However, when comparing indium oxide and silicon in terms of whether they can be formed as single crystals on an insulating film, they have different properties.

[0276] Here, a comparison is made among a transistor having a crystalline indium oxide film, a transistor having an IGZO (a compound oxide of In, Ga, and Zn) film, and a transistor having a silicon (Si) film. The comparison is shown in Table 5.

[0277]

[0278] In Table 5, transistors having a crystalline indium oxide film are intended for use in LSIs and are clearly indicated as crystalline IO (LSI). Hereinafter, this may be simply referred to as crystalline IO. Transistors having an IGZO film are intended for use in displays and are clearly indicated as IGZO (Display). Hereinafter, this may be simply referred to as IGZO. Transistors having a Si film are also clearly indicated as Si. In Table 5, ◎ represents +2 points, ○ represents +1 point, △ represents 0 points, and × represents −1 point, respectively. Total is the total value of the ◎, ○, △, and × points shown in Table 5. A higher score indicates better characteristics than a lower score.

[0279] In Table 5, the first comparison item is extremely small off-state current, with crystalline IO and IGZO being superior to Si. The second comparison item is on-state current (Ion) characteristics, with crystalline IO and Si being superior to IGZO. The third comparison item is reliability, with crystalline IO and Si being superior to IGZO. The fourth comparison item is miniaturization of channel length, with crystalline IO and IGZO being superior to Si. In the section on miniaturization of channel length, VFET represents a vertical transistor, UFET represents a transistor with a U-shape structure, and 3D structure represents a three-dimensional structure. The fifth comparison item is cutoff frequency, with the characteristics increasing in the order of crystalline IO, Si, and IGZO. The sixth comparison item is improvement in integration, with Si being superior to crystalline IO and IGZO. The seventh comparison item is threshold voltage controllability (Vth controllability), in which Si is superior to crystalline IO and IGZO. The eighth comparison item is radiation resistance, in which crystalline IO and IGZO are superior to Si. The ninth comparison item is 3D (multi-level) integrated structure, in which crystalline IO and IGZO are superior to Si. The tenth comparison item is the possibility of self-heating, in which crystalline IO and IGZO are superior to Si.

[0280] As shown in Table 5, the total score for crystalline IO (LSI) is 9 points, for IGZO (Display) is 4 points, and for Si is 3 points. As described above, the semiconductor device of one embodiment of the present invention, in particular the semiconductor device including a crystalline indium oxide film, has the potential to replace a semiconductor device using Si.

[0281] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0282] Embodiment 4 In this embodiment, a semiconductor device 900 according to one embodiment of the present invention will be described. The semiconductor device 900 can function as a memory device.

[0283] Fig. 11 is a block diagram showing a configuration example of a semiconductor device 900. The semiconductor device 900 shown in Fig. 11 includes a driver circuit 910 and a memory array 920. The memory array 920 includes one or more memory cells 950. Fig. 11 shows an example in which the memory array 920 includes a plurality of memory cells 950 arranged in a matrix.

[0284] The drive circuit 910 includes a PSW 931 (power switch), a PSW 932, and a peripheral circuit 915. The peripheral circuit 915 includes a peripheral circuit 911, a control circuit 912, and a voltage generation circuit 928.

[0285] In the semiconductor device 900, each circuit, signal, and voltage can be appropriately selected or omitted as needed. Alternatively, other circuits or signals may be added. The signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are input signals from the outside, and the signal RDA is an output signal to the outside. The signal CLK is a clock signal.

[0286] Furthermore, signals BW, CE, and GW are control signals. Signal CE is a chip enable signal, signal GW is a global write enable signal, and signal BW is a byte write enable signal. Signal ADDR is an address signal. Signal WDA is a write data signal, and signal RDA is a read data signal. Signals PON1 and PON2 are power gating control signals. Note that signals PON1 and PON2 may be generated by the control circuit 912.

[0287] The control circuit 912 is a logic circuit having a function of controlling the overall operation of the semiconductor device 900. For example, the control circuit 912 performs a logical operation on the signals CE, GW, and BW to determine the operation mode (e.g., write operation, read operation) of the semiconductor device 900. Alternatively, the control circuit 912 generates a control signal for the peripheral circuit 911 so that this operation mode is executed.

[0288] The voltage generating circuit 928 has a function of generating a negative voltage. The signal WAKE has a function of controlling the input of the signal CLK to the voltage generating circuit 928. For example, when an H-level signal is given as the signal WAKE, the signal CLK is input to the voltage generating circuit 928, and the voltage generating circuit 928 generates a negative voltage.

[0289] The peripheral circuit 911 is a circuit for writing and reading data to and from the memory cells 950. The peripheral circuit 911 includes a row decoder 941, a column decoder 942, a row driver 923, a column driver 924, an input circuit 925, an output circuit 926, and a sense amplifier 927.

[0290] The row decoder 941 and the column decoder 942 have the function of decoding the signal ADDR. The row decoder 941 is a circuit for specifying a row to be accessed, and the column decoder 942 is a circuit for specifying a column to be accessed. The row driver 923 has the function of selecting the row specified by the row decoder 941. The column driver 924 has the function of writing data to the memory cells 950, reading data from the memory cells 950, and retaining the read data.

[0291] The input circuit 925 has a function of holding a signal WDA. The data held by the input circuit 925 is output to the column driver 924. The output data of the input circuit 925 is data (Din) to be written to the memory cell 950. The data (Dout) read from the memory cell 950 by the column driver 924 is output to the output circuit 926. The output circuit 926 has a function of holding Dout. In addition, the output circuit 926 has a function of outputting Dout to the outside of the semiconductor device 900. The data output from the output circuit 926 is a signal RDA.

[0292] The PSW 931 is a V ＤＤ The PSW 932 has the function of controlling the supply of V to the row driver 923. ＨＭ Here, the high power supply potential of the semiconductor device 900 is V ＤＤ and the low power supply potential is GND (ground potential). ＨＭ is the high power supply potential used to drive the word line high, and V ＤＤ The signal PON1 controls the on / off of the PSW 931, and the signal PON2 controls the on / off of the PSW 932. In FIG. 11, in the peripheral circuit 915, V ＤＤ Although the number of power domains to which power is supplied is set to one, it is also possible to set it to a plurality of power domains. In this case, a power switch may be provided for each power domain.

[0293] 12A to 12H, other examples of memory cell configurations that can be applied to the memory cell 950 will be described.

[0294] 12A shows an example of a circuit configuration of a memory cell of a dynamic random access memory (DRAM). In this specification and the like, a DRAM using an OS transistor is referred to as a dynamic oxide semiconductor random access memory (DOSRAM). The memory cell 951 includes a transistor M1 and a capacitor CA.

[0295] The transistor M1 may have a front gate (sometimes simply referred to as a gate) and a back gate. In this case, the back gate may be connected to a wiring that supplies a constant potential or a signal, or the front gate and the back gate may be connected to each other.

[0296] A first terminal of the transistor M1 is connected to a first terminal of the capacitance element CA, a second terminal of the transistor M1 is connected to the wiring BIL, and a gate of the transistor M1 is connected to the wiring WOL. The second terminal of the capacitance element CA is connected to the wiring CAL.

[0297] The wiring BIL functions as a bit line, and the wiring WOL functions as a word line. The wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitance element CA. When writing and reading data, it is preferable to apply a low-level potential (sometimes referred to as a reference potential) to the wiring CAL.

[0298] Data is written and read by applying a high-level potential to the wiring WOL, turning on the transistor M1, and bringing the wiring BIL and the first terminal of the capacitor CA into a conductive state (a state in which current can flow).

[0299] Furthermore, the memory cell that can be used for the memory cell 950 is not limited to the memory cell 951, and the circuit configuration can be changed. For example, a configuration in which one wiring BIL is provided in common for two or more memory cells may be used. Alternatively, for example, the configuration of the memory cell 952 shown in FIG. 12B may be used. The memory cell 952 is an example in which the memory cell 952 does not include the capacitor CA and the wiring CAL. The first terminal of the transistor M1 is in an electrically floating state.

[0300] In the memory cell 952, the potential written through the transistor M1 is held in a capacitance (also referred to as a parasitic capacitance) between the first terminal and the gate, which is indicated by a dashed line. With this configuration, the configuration of the memory cell can be significantly simplified.

[0301] Note that an OS transistor is preferably used as the transistor M1. An OS transistor has a characteristic of having an extremely small off-state current. By using an OS transistor as the transistor M1, the leakage current of the transistor M1 can be made extremely small. That is, written data can be held by the transistor M1 for a long time, so that the frequency of refreshing the memory cell can be reduced. Alternatively, the refresh operation of the memory cell can be made unnecessary. Furthermore, because the leakage current is extremely small, multilevel data or analog data can be held in the memory cell 951 and the memory cell 952.

[0302] An example of the structure of a DOSRAM will now be described with reference to Fig. 13. In Fig. 13, the X direction is parallel to the channel width direction of the transistor, the Y direction is perpendicular to the X direction, and the Z direction is perpendicular to the X and Y directions.

[0303] As shown in FIG. 13 , the memory cell 951 includes a transistor M1 and a capacitor CA. An insulating layer 284 is provided over the transistor M1. The insulating layer 284 can be an insulating layer applicable to the insulating layer 83. The transistor M1 has a similar structure to that of the transistor 50A described in Embodiment 2, and the same components are denoted by the same reference numerals. For details of the transistor 50A, refer to Embodiment 2. A conductive layer 240 is provided in contact with one of the source electrode and drain electrode (conductive layer 54b) of the transistor M1. The conductive layer 240 extends in the Z direction and functions as a wiring BIL. The gate electrode (conductive layer 53) of the transistor M1 extends in the X direction and functions as a wiring WOL.

[0304] The capacitor CA has a conductive layer 453 on the conductive layer 54 a, an insulating layer 454 on the conductive layer 453 , and a conductive layer 460 on the insulating layer 454 .

[0305] In the capacitor CA, the conductive layer 453 functions as one electrode (lower electrode), the insulating layer 454 functions as a dielectric, and the conductive layer 460 functions as the other electrode (upper electrode). The upper part of the conductive layer 460 can be extended to function as a wiring CAL. The capacitor CA forms a MIM (Metal-Insulator-Metal) capacitor.

[0306] At least a portion of the conductive layer 453, the insulating layer 454, and the conductive layer 460 is disposed in openings provided in the insulating layer 86, the insulating layer 85, the insulating layer 84, the insulating layer 62, and the insulating layer 61, respectively. The upper end of the conductive layer 453 coincides or substantially coincides with the upper surface of the insulating layer 86. The end of the insulating layer 454 and the end of the conductive layer 460 are each located on the insulating layer 86. The insulating layer 454 is provided so as to cover the end of the conductive layer 453. This allows the conductive layer 453 and the conductive layer 460 to be insulated from each other.

[0307] The deeper the opening (i.e., the thicker the film thickness of one or more of the insulating layers 86, 85, 84, 62, and 61), the greater the capacitance of the capacitor CA. Increasing the capacitance per unit area of ​​the capacitor CA allows for miniaturization or high integration of memory devices. For example, the capacitance of the capacitor CA can be set by adjusting the film thickness of the insulating layer 86. Specifically, the film thickness of the insulating layer 86 can be set in the range of 50 nm to 250 nm, and the depth of the opening can be set to approximately 150 nm to 350 nm. Forming the capacitor CA within such a range allows the capacitor CA to have sufficient capacitance, and prevents the height of one layer from becoming excessively high in a semiconductor device having multiple stacked memory cell layers. Note that the capacitance of the capacitors provided in each memory cell in each of the multiple memory cell layers may be different. In this configuration, for example, the thickness of the insulating layer 86 provided in each memory cell layer may be made different.

[0308] The conductive layer 54a also functions as an electrode that connects to the lower electrode of the capacitance element CA.

[0309] The conductive layer 453 and the conductive layer 460 can be formed using a conductive layer applicable to the conductive layer 53 or the conductive layer 71. The conductive layer 453 and the conductive layer 460 are preferably formed by a film formation method with good coverage, such as an ALD method or a CVD method. For example, the conductive layer 453 can be a titanium nitride film or a tantalum nitride film formed by an ALD method or a CVD method.

[0310] The top surface of the conductive layer 54a is in contact with the bottom surface of the conductive layer 453. Here, by using a conductive material with good conductivity for the conductive layer 54a, contact resistance between the conductive layer 453 and the conductive layer 54a can be reduced.

[0311] Alternatively, the conductive layer 460 can be formed using a stacked film of a titanium nitride film formed by an ALD method or a CVD method and a tungsten film formed by a CVD method over the titanium nitride film. Note that if the adhesion of the tungsten film to the insulating layer 454 is sufficiently high, the conductive layer 460 may have a single-layer structure of a tungsten film formed by a CVD method.

[0312] The high-k material described in the above embodiment is preferably used for the insulating layer 454 of the capacitor CA. By using the high-k material, the insulating layer 454 can be thick enough to suppress leakage current and ensure sufficient capacitance of the capacitor CA. In addition, the insulating layer 454 is preferably formed by a film formation method with good coverage, such as an ALD method or a CVD method.

[0313] In addition, it is preferable to use a stack of insulating layers made of the above materials, and it is preferable to use a stack structure of a high-k material and a material having a higher dielectric strength than the high-k material. For example, the insulating layer 454 can be an insulating film stacked in this order: a zirconium oxide film, an aluminum oxide film, and a zirconium oxide film. Alternatively, it can be an insulating film stacked in this order: a zirconium oxide film, an aluminum oxide film, a zirconium oxide film, and an aluminum oxide film. Alternatively, it can be an insulating film stacked in this order: a hafnium zirconium oxide film, an aluminum oxide film, a hafnium zirconium oxide film, and an aluminum oxide film. By stacking an insulator with a relatively high dielectric strength, such as aluminum oxide, the dielectric strength can be improved, and electrostatic breakdown of the capacitor element CA can be suppressed.

[0314] The insulating layer 454 may be formed using the material that can have ferroelectricity described in the [Insulating Layer] section of Embodiment Mode 2.

[0315] A ferroelectric material is an insulator that generates polarization internally when an external electric field is applied, and the polarization remains even when the electric field is removed. Therefore, a nonvolatile memory element can be formed using a capacitance element (hereinafter sometimes referred to as a ferroelectric capacitor) that uses this material as a dielectric. A nonvolatile memory element using a ferroelectric capacitor is sometimes called a Ferroelectric Random Access Memory (FeRAM), a ferroelectric memory, or the like. For example, a ferroelectric memory has a transistor and a ferroelectric capacitor, and one of the source and drain of the transistor is connected to one terminal of the ferroelectric capacitor. Therefore, when a ferroelectric capacitor is used as the capacitance element CA, the memory device described in this embodiment functions as a ferroelectric memory.

[0316] Note that the sidewall of the opening in which the capacitor element CA is disposed may be perpendicular or approximately perpendicular to the top surface of the insulating layer 73, or may be tapered. By tapering the sidewall of the opening, coverage of the conductive layer 453 or the like provided in the opening can be improved, and defects such as voids can be reduced.

[0317] The conductive layer 54b functions as a wiring that connects to the conductive layer 240. For example, in FIG.

[0318] By having the conductive layer 240 directly contact at least one of the upper surface and side edge of the conductive layer 54b, there is no need to provide a separate connection electrode, thereby reducing the area occupied by the memory array. Furthermore, the integration density of memory cells is improved, allowing for an increase in the memory capacity of the memory device. It is preferable that the conductive layer 240 contact a portion of the upper surface and side edge of the conductive layer 54b. By having the conductive layer 240 contact multiple surfaces of the conductive layer 54b, the contact resistance between the conductive layer 240 and the conductive layer 54b can be reduced.

[0319] The conductive layer 240 is provided in openings formed in the insulating layer 81, the insulating layer 82, the insulating layer 83, the insulating layer 72, the insulating layer 73, the insulating layer 61, the insulating layer 62, the insulating layer 84, the insulating layer 85, the insulating layer 86, and the insulating layer 284.

[0320] 13, an insulating layer 241 is preferably provided in contact with the side surface of the conductive layer 240. Specifically, the insulating layer 241 is provided in contact with the inner wall of the opening. The insulating layer 241 is also formed on the side surface of the semiconductor layer 51, which is formed to protrude into the opening. Here, at least a portion of the conductive layer 54b is exposed from the insulating layer 241 and is in contact with the conductive layer 240. In other words, the conductive layer 240 is provided so as to fill the opening via the insulating layer 241.

[0321] 13, the uppermost portion of the insulating layer 241 formed below the conductive layer 54b is preferably located below the upper surface of the conductive layer 54b. This configuration allows the conductive layer 240 to be in contact with at least a portion of the side edge of the conductive layer 54b. The insulating layer 241 formed below the conductive layer 54b preferably has a region in contact with the side surface of the semiconductor layer 51. This configuration can prevent impurities such as water and hydrogen contained in the insulating layer 62, etc. from being mixed into the semiconductor layer 51 through the conductive layer 240.

[0322] Furthermore, in the opening where the conductive layer 240 and the insulating layer 241 are disposed, the sidewall of the opening may be perpendicular or approximately perpendicular to the top surface of the insulating layer 73, or may have a tapered shape. By making the sidewall tapered, coverage of the insulating layer 241 and the like provided in the opening is improved.

[0323] 12C shows an example circuit configuration of a gain cell type memory cell having two transistors and one capacitor. The memory cell 953 includes a transistor M2, a transistor M3, and a capacitor CB. In this specification and the like, a storage device having a gain cell type memory cell in which the transistor M2 is an OS transistor is referred to as a nonvolatile oxide semiconductor RAM (NOSRAM).

[0324] The first terminal of transistor M2 is connected to the first terminal of capacitance element CB, the second terminal of transistor M2 is connected to wiring WBL, and the gate of transistor M2 is connected to wiring WOL. The second terminal of capacitance element CB is connected to wiring CAL. The first terminal of transistor M3 is connected to wiring RBL, the second terminal of transistor M3 is connected to wiring SL, and the gate of transistor M3 is connected to the first terminal of capacitance element CB.

[0325] The wiring WBL functions as a write bit line, the wiring RBL functions as a read bit line, and the wiring WOL functions as a word line. The wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitance element CB. When writing data, while retaining data, and when reading data, it is preferable to apply a low-level potential (sometimes referred to as a reference potential) to the wiring CAL.

[0326] Data is written by applying a high-level potential to the wiring WOL, turning on the transistor M2, and establishing electrical continuity between the wiring WBL and the first terminal of the capacitor CB. Specifically, when the transistor M2 is on, a potential corresponding to the information to be recorded is applied to the wiring WBL, and the potential is written to the first terminal of the capacitor CB and the gate of the transistor M3. Then, a low-level potential is applied to the wiring WOL, turning off the transistor M2, thereby maintaining the potential of the first terminal of the capacitor CB and the potential of the gate of the transistor M3.

[0327] Data is read by applying a predetermined potential to the wiring SL. The current flowing between the source and drain of the transistor M3 and the potential of the first terminal of the transistor M3 are determined by the potential of the gate of the transistor M3 and the potential of the second terminal of the transistor M3. Therefore, the potential held in the first terminal of the capacitor CB (or the gate of the transistor M3) can be read by reading the potential of the wiring RBL connected to the first terminal of the transistor M3. In other words, information written in this memory cell can be read from the potential held in the first terminal of the capacitor CB (or the gate of the transistor M3).

[0328] Alternatively, for example, the wiring WBL and the wiring RBL may be combined into a single wiring BIL. An example circuit configuration of such a memory cell is shown in FIG. 12D. The memory cell 954 is configured such that the wiring WBL and the wiring RBL of the memory cell 953 are combined into a single wiring BIL, and the second terminal of the transistor M2 and the first terminal of the transistor M3 are connected to the wiring BIL. In other words, the memory cell 954 is configured to operate as a write bit line and a read bit line using a single wiring BIL.

[0329] 12E is an example in which the capacitor CB and the wiring CAL in the memory cell 953 are omitted. Also, a memory cell 956 in Fig. 12F is an example in which the capacitor CB and the wiring CAL in the memory cell 954 are omitted. With such a configuration, the integration degree of the memory cells can be increased.

[0330] Note that it is preferable to use an OS transistor for at least the transistor M2. In particular, it is preferable to use OS transistors for the transistors M2 and M3. By using an OS transistor as the transistor M2, written data can be held by the transistor M2 for a long time, which reduces the frequency of refreshing the memory cell. Alternatively, the refresh operation of the memory cell can be eliminated. Furthermore, since the leakage current is extremely small, multilevel data or analog data can be held in the memory cells 953 to 956.

[0331] The memory cells 953 to 956 in which an OS transistor is used as the transistor M2 are one embodiment of NOSRAM.

[0332] Note that a Si transistor may be used as the transistor M3. The Si transistor can increase the field effect mobility and can also be used as a p-channel transistor, thereby increasing the degree of freedom in circuit design.

[0333] 12G shows a three-transistor, one-capacitor gain cell type memory cell 957. The memory cell 957 includes transistors M4 to M6 and a capacitor CC.

[0334] The first terminal of transistor M4 is connected to the first terminal of capacitor CC, the second terminal of transistor M4 is connected to wiring BIL, and the gate of transistor M4 is connected to wiring WOL. The second terminal of capacitor CC is connected to the first terminal of transistor M5 and wiring GNDL. The second terminal of transistor M5 is connected to the first terminal of transistor M6, and the gate of transistor M5 is connected to the first terminal of capacitor CC. The second terminal of transistor M6 is connected to wiring BIL, and the gate of transistor M6 is connected to wiring RWL.

[0335] The wiring BIL functions as a bit line, the wiring WOL functions as a write word line, and the wiring RWL functions as a read word line. The wiring GNDL is a wiring that applies a low-level potential.

[0336] Data is written by applying a high-level potential to the wiring WOL, turning on the transistor M4, and establishing electrical continuity between the wiring BIL and the first terminal of the capacitor CC. Specifically, when the transistor M4 is on, a potential corresponding to the information to be recorded is applied to the wiring BIL, and the potential is written to the first terminal of the capacitor CC and the gate of the transistor M5. Then, a low-level potential is applied to the wiring WOL, turning off the transistor M4, thereby maintaining the potential of the first terminal of the capacitor CC and the potential of the gate of the transistor M5.

[0337] Data is read by precharging the wiring BIL to a predetermined potential, then electrically floating the wiring BIL, and applying a high-level potential to the wiring RWL. Because the wiring RWL is at a high-level potential, the transistor M6 is turned on, and the wiring BIL and the second terminal of the transistor M5 are electrically connected. At this time, the potential of the wiring BIL is applied to the second terminal of the transistor M5. The potential of the second terminal of the transistor M5 and the potential of the wiring BIL change depending on the potential held in the first terminal of the capacitor CC (or the gate of the transistor M5). By reading the potential of the wiring BIL, the potential held in the first terminal of the capacitor CC (or the gate of the transistor M5) can be read. In other words, information written in this memory cell can be read from the potential held in the first terminal of the capacitor CC (or the gate of the transistor M5).

[0338] Note that at least the transistor M4 is preferably an OS transistor.

[0339] Note that Si transistors may be used as the transistors M5 and M6. As described above, Si transistors may have higher field-effect mobility than OS transistors depending on the crystalline state of silicon used in the semiconductor layer.

[0340] 12H shows an example of an SRAM (Static Random Access Memory) using an OS transistor. In this specification and the like, an SRAM using an OS transistor is referred to as an OS-SRAM (Oxide Semiconductor-SRAM). Note that a memory cell 958 shown in FIG. 12H is a memory cell of an SRAM capable of backing up data.

[0341] The memory cell 958 includes transistors M7 to M10, transistors MS1 to MS4, and capacitors CD1 and CD2. Note that the transistors MS1 and MS2 are p-channel transistors, and the transistors MS3 and MS4 are n-channel transistors.

[0342] A first terminal of transistor M7 is connected to wiring BIL, and a second terminal of transistor M7 is connected to a first terminal of transistor MS1, a first terminal of transistor MS3, the gate of transistor MS2, the gate of transistor MS4, and a first terminal of transistor M10. The gate of transistor M7 is connected to wiring WOL. A first terminal of transistor M8 is connected to wiring BILB, and a second terminal of transistor M8 is connected to a first terminal of transistor MS2, the first terminal of transistor MS4, the gate of transistor MS1, the gate of transistor MS3, and a first terminal of transistor M9. The gate of transistor M8 is connected to wiring WOL.

[0343] A second terminal of the transistor MS1 is connected to the wiring VDL. A second terminal of the transistor MS2 is connected to the wiring VDL. A second terminal of the transistor MS3 is connected to the wiring GNDL. A second terminal of the transistor MS4 is connected to the wiring GNDL.

[0344] A second terminal of the transistor M9 is connected to a first terminal of the capacitor CD1, and a gate of the transistor M9 is connected to the wiring BRL. A second terminal of the transistor M10 is connected to a first terminal of the capacitor CD2, and a gate of the transistor M10 is connected to the wiring BRL.

[0345] A second terminal of the capacitance element CD1 is connected to the wiring GNDL, and a second terminal of the capacitance element CD2 is connected to the wiring GNDL.

[0346] The wirings BIL and BILB function as bit lines, the wiring WOL functions as a word line, and the wiring BRL is a wiring that controls the on / off states of the transistors M9 and M10.

[0347] The wiring VDL is a wiring that applies a high-level potential, and the wiring GNDL is a wiring that applies a low-level potential.

[0348] Data is written by applying a high-level potential to the wiring WOL and a high-level potential to the wiring BRL. Specifically, when the transistor M10 is on, a potential corresponding to information to be written is applied to the wiring BIL, and the potential is written to the second terminal of the transistor M10.

[0349] Since the memory cell 958 includes an inverter loop formed by the transistors MS1 and MS2, an inverted signal of the data signal corresponding to the potential is input to the second terminal of the transistor M8. Because the transistor M8 is on, the potential applied to the wiring BIL, i.e., the inverted signal of the signal input to the wiring BIL, is output to the wiring BILB. Because the transistors M9 and M10 are on, the potentials of the second terminals of the transistors M7 and M8 are held in the first terminals of the capacitors CD2 and CD1, respectively. Then, a low-level potential is applied to the wiring WOL and a low-level potential is applied to the wiring BRL to turn off the transistors M7 to M10, thereby holding the potentials of the first terminals of the capacitors CD1 and CD2.

[0350] Data is read by precharging the wirings BIL and BILB to a predetermined potential in advance, and then applying a high-level potential to the wiring WOL and a high-level potential to the wiring BRL, so that the potential of the first terminal of the capacitor CD1 is refreshed by the inverter loop of the memory cell 958 and output to the wiring BILB. Also, the potential of the first terminal of the capacitor CD2 is refreshed by the inverter loop of the memory cell 958 and output to the wiring BIL. In the wirings BIL and BILB, the potentials of the first terminal of the capacitor CD2 and the first terminal of the capacitor CD1 change from the precharged potentials, respectively, so that the potential held in the memory cell can be read from the potential of the wiring BIL or the wiring BILB.

[0351] Note that OS transistors are preferably used as the transistors M7 to M10. This allows written data to be held by the transistors M7 to M10 for a long time, which reduces the frequency of refreshing the memory cells. Alternatively, refreshing the memory cells can be eliminated.

[0352] Note that Si transistors may be used as the transistors MS1 to MS4.

[0353] The driver circuit 910 and memory array 920 of the semiconductor device 900 may be provided on the same plane. Alternatively, as shown in FIG. 14A, the driver circuit 910 and memory array 920 may be provided overlapping each other. By providing the driver circuit 910 and memory array 920 overlapping each other, the signal propagation distance can be shortened. Alternatively, as shown in FIG. 14B, the memory array 920 may be provided in multiple layers on the driver circuit 910.

[0354] Here, a configuration example of a semiconductor device 900 in which memory arrays 920 are stacked in multiple layers will be described with reference to FIG.

[0355] 15 includes a driver circuit 910, which is a layer including a transistor 310 and the like, and memory arrays 920[1] to 920[m] (m is an integer of 3 or more) over the driver circuit 910. Here, the layer provided in the first layer (bottom) is referred to as memory array 920[1], the layer provided in the second layer is referred to as memory array 920[2], and the layer provided in the m-th layer (top) is referred to as memory array 920[m]. In other words, the memory device of one embodiment of the present invention may have a structure in which multiple layers including memory cells are stacked.

[0356] 15 illustrates a transistor 310 included in a driver circuit 910. The transistor 310 is provided over a substrate 311 and includes a conductive layer 316 functioning as a gate, an insulating layer 315 functioning as a gate insulating layer, a semiconductor region 313 including part of the substrate 311, and low-resistance regions 314a and 314b functioning as source and drain regions. An element isolation layer 318 is preferably provided between adjacent transistors 310. The transistor 310 may be either a p-channel type or an n-channel type. The substrate 311 can be, for example, a single-crystal silicon substrate.

[0357] Here, in the transistor 310, a semiconductor region 313 (a part of the substrate 311) in which a channel is formed has a convex shape. A conductive layer 316 is provided to cover the side and top surfaces of the semiconductor region 313 with an insulating layer 315 interposed therebetween. Note that the conductive layer 316 may be made of a material that adjusts the work function. Such a transistor 310 is also called a FIN-type transistor because it utilizes the convex portions of the semiconductor substrate. Note that an insulating layer that is in contact with the top of the convex portions and functions as a mask for forming the convex portions may be provided. Here, the case where the convex portions are formed by processing a part of the semiconductor substrate is shown, but a semiconductor film having a convex shape may also be formed by processing an SOI substrate.

[0358] Note that the transistor 310 illustrated in FIG. 15 is just an example, and the structure is not limited thereto. An appropriate transistor can be used depending on the circuit configuration or the driving method.

[0359] Between each structure, a wiring layer provided with an interlayer film, wiring, plugs, etc. may be provided. Furthermore, multiple wiring layers may be provided depending on the design. Here, for a conductive layer having the function of a plug or wiring, the same reference numeral may be used to refer to multiple structures. Furthermore, in this specification and the like, the wiring and the plug connected to the wiring may be integrated. That is, there are cases where a part of the conductive layer functions as the wiring, and cases where a part of the conductive layer functions as the plug.

[0360] For example, an insulating layer 320, an insulating layer 322, an insulating layer 324, and an insulating layer 326 are stacked in this order as an interlayer film over the transistor 310. A conductive layer 328 or the like is embedded in the insulating layer 320 and the insulating layer 322. A conductive layer 330 or the like is embedded in the insulating layer 324 and the insulating layer 326. The conductive layer 328 and the conductive layer 330 function as contact plugs or wirings.

[0361] The insulating layer serving as an interlayer film may also function as a planarizing film that covers the underlying unevenness. For example, the top surface of the insulating layer 322 may be planarized by CMP treatment to improve the planarity.

[0362] Insulating layers that can be used as interlayer films include oxides, nitrides, oxynitrides, metal oxides, and metal oxynitrides, which have insulating properties. For example, by using a material with a low dielectric constant for an insulating layer that functions as an interlayer film, the parasitic capacitance that occurs between wirings can be reduced. Therefore, it is preferable to select a material depending on the function of the insulating layer.

[0363] An insulating layer 208 is provided on the driver circuit 910, and a conductive layer 207 is provided in an opening formed in the insulating layer 208. Furthermore, an insulating layer 210 is provided on the insulating layer 208, and a conductive layer 209 is provided in an opening formed in the insulating layer 210. Furthermore, an insulating layer 81 and an insulating layer 82 are provided in this order on the insulating layer 210. A part of the conductive layer 240 provided in the memory array 920[1] is buried in the openings formed in the insulating layer 81 and the insulating layer 82. Here, the insulating layer 208 and the insulating layer 210 can be an insulating layer applicable to the insulating layer 83.

[0364] The conductive layer 207 functions as a wiring connected to the driver circuit 910. The top surface of the conductive layer 207 is in contact with the bottom surface of the conductive layer 209. The top surface of the conductive layer 209 is in contact with the bottom surface of the conductive layer 240 provided in the memory array 920[1]. With this structure, the conductive layer 240 corresponding to the wiring BIL can be connected to the driver circuit 910.

[0365] Each of the memory arrays 920[1] to 920[m] includes a plurality of memory cells 951. The conductive layer 240 of each memory cell 951 is connected to the conductive layer 240 in the upper layer and the conductive layer 240 in the lower layer.

[0366] 15, the conductive layer 240 is shared by adjacent memory cells 951. In addition, in the adjacent memory cells 951, the configuration on the right side and the configuration on the left side are arranged symmetrically with respect to the conductive layer 240.

[0367] In the above-described memory array 920, the memory arrays 920[1] to 920[m] can be stacked. The memory arrays 920[1] to 920[m] included in the memory array 920 can be arranged in the vertical direction of the substrate surface on which the driver circuit 910 is provided, thereby improving the memory density of the memory cells 951. Furthermore, the memory array 920 can be manufactured by repeatedly using the same manufacturing process in the vertical direction. The semiconductor device 900 can reduce the manufacturing cost of the memory array 920.

[0368] Next, an example of a processing unit that can include a semiconductor device such as the memory device will be described.

[0369] 16 shows a block diagram of the arithmetic device 960. The arithmetic device 960 shown in FIG. 16 can be applied to, for example, a CPU. The arithmetic device 960 can also be applied to processors such as a GPU (Graphics Processing Unit), a TPU (Tensor Processing Unit), and an NPU (Neural Processing Unit) that have a larger number (several tens to several hundreds) of processor cores capable of parallel processing than a CPU.

[0370] The arithmetic device 960 shown in FIG. 16 has an ALU 962 (ALU: Arithmetic logic unit, arithmetic circuit), an ALU controller 962c, an instruction decoder 963, an interrupt controller 964, a timing controller 965, a register 966, a register controller 967, a bus interface 968, a cache 969, and a cache interface 969i on a substrate 961. The substrate 961 may be a semiconductor substrate, an SOI substrate, a glass substrate, or the like. It may also have a rewritable ROM and a ROM interface. The cache 969 and the cache interface 969i may also be provided on separate chips.

[0371] The cache 969 is connected to a main memory provided on a separate chip via a cache interface 969i. The cache interface 969i has a function of supplying part of the data held in the main memory to the cache 969. The cache interface 969i also has a function of outputting part of the data held in the cache 969 to the ALU 962, register 966, etc. via the bus interface 968.

[0372] As will be described later, a memory array 920 can be provided stacked on the arithmetic unit 960. The memory array 920 can be used as a cache. In this case, the cache interface 969i may have a function of supplying data held in the memory array 920 to the cache 969. In this case, it is preferable that a drive circuit 910 be provided as part of the cache interface 969i.

[0373] It is also possible to use only the memory array 920 as a cache without providing the cache 969 .

[0374] The arithmetic device 960 shown in FIG. 16 is merely an example of a simplified configuration, and actual arithmetic devices 960 have a wide variety of configurations depending on their applications. For example, it is preferable to use a configuration including the arithmetic device 960 shown in FIG. 16 as one core, and to include multiple such cores, each of which operates in parallel, in a so-called multi-core configuration. The greater the number of cores, the higher the computational performance. The greater the number of cores, for example, two, preferably four, more preferably eight, even more preferably twelve, and even more preferably sixteen or more. Furthermore, when extremely high computational performance is required, such as for server applications, a multi-core configuration having 16 or more, preferably 32 or more, and even more preferably 64 or more cores is preferable. Furthermore, the number of bits that the arithmetic device 960 can handle via its internal computation circuit, data bus, etc. can be, for example, 8 bits, 16 bits, 32 bits, 64 bits, etc.

[0375] An instruction input to the arithmetic unit 960 via the bus interface 968 is input to the instruction decoder 963, decoded, and then input to the ALU controller 962c, the interrupt controller 964, the register controller 967, and the timing controller 965.

[0376] The ALU controller 962c, interrupt controller 964, register controller 967, and timing controller 965 perform various controls based on the decoded instructions. Specifically, the ALU controller 962c generates signals for controlling the operation of the ALU 962. Furthermore, the interrupt controller 964 determines and processes interrupt requests from external input / output devices, peripheral circuits, etc. based on their priority, mask status, etc. while the arithmetic unit 960 is executing a program. The register controller 967 generates an address for the register 966 and reads and writes data from and to the register 966 depending on the state of the arithmetic unit 960.

[0377] Furthermore, the timing controller 965 generates signals that control the timing of the operations of the ALU 962, the ALU controller 962c, the instruction decoder 963, the interrupt controller 964, and the register controller 967. For example, the timing controller 965 includes an internal clock generation unit that generates an internal clock signal based on a reference clock signal, and supplies the internal clock signal to the various circuits described above.

[0378] 16 , a register controller 967 selects a holding operation in a register 966 in accordance with an instruction from an ALU 962. That is, the register controller 967 selects whether data is to be held by a flip-flop or by a capacitor in the memory cell of the register 966. When holding data by a flip-flop is selected, a power supply potential is supplied to the memory cell in the register 966. When holding data in a capacitor is selected, data is rewritten to the capacitor, and the supply of power supply potential to the memory cell in the register 966 can be stopped.

[0379] The memory array 920 and the arithmetic unit 960 can be provided overlapping each other. Perspective views of a semiconductor device 970A are shown in Figures 17A and 17B. The semiconductor device 970A has a layer 930 on which memory arrays are provided above the arithmetic unit 960. The layer 930 is provided with memory arrays 920L1, 920L2, and 920L3. The arithmetic unit 960 and each memory array have overlapping regions. To make the configuration of the semiconductor device 970A easier to understand, the arithmetic unit 960 and the layer 930 are shown separately in Figure 17B.

[0380] By stacking the layer 930 having the memory array and the arithmetic unit 960, the connection distance between them can be shortened, thereby increasing the communication speed between them. In addition, the short connection distance reduces power consumption.

[0381] As a method for stacking the layer 930 having a memory array and the arithmetic device 960, a method (also called monolithic stacking) in which the layer 930 having a memory array is stacked directly on the arithmetic device 960 may be used, or a method in which the arithmetic device 960 and the layer 930 are formed on different substrates, and the two substrates are bonded together and connected using a through-via or conductive film bonding technology (such as Cu-Cu bonding) may be used. The former method does not require consideration of misalignment during bonding, and therefore can not only reduce the chip size but also reduce manufacturing costs.

[0382] Here, the arithmetic unit 960 does not have a cache 969, and the memory arrays 920L1, 920L2, and 920L3 provided in the layer 930 can each be used as a cache. In this case, for example, the memory array 920L1 can be used as an L1 cache (also referred to as a level 1 cache), the memory array 920L2 can be used as an L2 cache (also referred to as a level 2 cache), and the memory array 920L3 can be used as an L3 cache (also referred to as a level 3 cache). Of the three memory arrays, the memory array 920L3 has the largest capacity and the lowest access frequency. Furthermore, the memory array 920L1 has the smallest capacity and the highest access frequency.

[0383] When the cache 969 provided in the arithmetic unit 960 is used as an L1 cache, each memory array provided in the layer 930 can be used as a lower-level cache or a main memory. The main memory has a larger capacity than the cache and is accessed less frequently.

[0384] 17B, ​​a driving circuit 910L1, a driving circuit 910L2, and a driving circuit 910L3 are provided. The driving circuit 910L1 is connected to the memory array 920L1 via a connection electrode 940L1. Similarly, the driving circuit 910L2 is connected to the memory array 920L2 via a connection electrode 940L2, and the driving circuit 910L3 is connected to the memory array 920L3 via a connection electrode 940L3.

[0385] Although the number of memory arrays functioning as caches is three in this example, the number may be one or two, or four or more.

[0386] When the memory array 920L1 is used as a cache, the driver 910L1 may function as part of the cache interface 969i, or may be configured to be connected to the cache interface 969i. Similarly, the driver circuits 910L2 and 910L3 may also function as part of the cache interface 969i, or may be configured to be connected thereto.

[0387] Whether the memory array 920 is made to function as a cache or as a main memory is determined by a control circuit 912 included in each drive circuit 910. The control circuit 912 can cause some of the memory cells 950 included in the semiconductor device 900 to function as RAM based on a signal supplied from the arithmetic device 960.

[0388] The semiconductor device 900 can cause some of the memory cells 950 to function as a cache and the other memory cells to function as a main memory. That is, the semiconductor device 900 can function as both a cache and a main memory. The semiconductor device 900 according to one embodiment of the present invention can function as, for example, a universal memory.

[0389] Furthermore, a layer 930 having one memory array 920 may be provided over the arithmetic device 960. Figure 18A shows a perspective view of a semiconductor device 970B.

[0390] In the semiconductor device 970B, one memory array 920 can be divided into multiple areas, each of which can be used for a different function. Fig. 18A shows an example in which area L1 is used as an L1 cache, area L2 is used as an L2 cache, and area L3 is used as an L3 cache.

[0391] Furthermore, in the semiconductor device 970B, the capacity of each of the areas L1 to L3 can be changed depending on the situation. For example, if it is desired to increase the capacity of the L1 cache, this can be achieved by increasing the area of ​​the area L1. This configuration can improve the efficiency of calculation processing and increase the processing speed.

[0392] Also, multiple memory arrays may be stacked. Figure 18B shows a perspective view of a semiconductor device 970C.

[0393] The semiconductor device 970C includes a layer 930L1 having a memory array 920L1, a layer 930L2 having a memory array 920L2 on top of that, and a layer 930L3 having a memory array 920L3 on top of that. The memory array 920L1, which is physically closest to the arithmetic unit 960, can be used as a higher-level cache, and the memory array 920L3, which is farthest, can be used as a lower-level cache or main memory. This configuration allows the capacity of each memory array to be increased, thereby further improving processing power.

[0394] This embodiment mode can be combined with other embodiment modes as appropriate. In addition, in this specification, when a plurality of configuration examples are shown in one embodiment mode, the configuration examples can be combined as appropriate.

[0395] Embodiment 5 In this embodiment, an example of a CMOS circuit configuration using a Si transistor and an OS transistor according to one embodiment of the present invention will be described.

[0396] Si transistors have higher field-effect mobility and faster operation speed than OS transistors. Furthermore, OS transistors have significantly lower off-state current than Si transistors. In particular, OS transistors that use indium oxide for the semiconductor layer in which a channel is formed have significantly lower off-state current and higher field-effect mobility comparable to that of Si transistors. By using an OS transistor and a Si transistor in combination, a CMOS circuit that consumes less power and operates at high speed can be realized.

[0397] In this embodiment, examples of circuits using Si transistors and OS transistors will be described, including a NOT circuit, a NOR circuit, and a NAND circuit, which are logic circuits. Also, examples of delay flip-flop (DFF) circuits and a shift register circuit using the DFF circuits will be described.

[0398] [NOT Circuit] Fig. 19A is a circuit diagram showing an example of the configuration of a NOT circuit (NOT). A NOT circuit is also called an inversion circuit, an inverter circuit, etc. Fig. 19B shows the circuit symbol of a NOT circuit. Fig. 19C is a timing chart explaining the operation of the NOT circuit.

[0399] The NOT circuit shown in FIG. 19A includes transistors Tr11 and Tr12. The transistor Tr11 is a Si transistor functioning as a p-type transistor, and the transistor Tr12 is an OS transistor functioning as an n-type transistor. A potential H (e.g., a high power supply potential VDD) is supplied to one of the source and the drain of the transistor Tr11. The other of the source and the drain of the transistor Tr11 is connected to one of the source and the drain of the transistor Tr12 and to a terminal Y. A potential L (e.g., a low power supply potential VSS) is supplied to the other of the source and the drain of the transistor Tr12. The gates of the transistors Tr11 and Tr12 are connected to a terminal A.

[0400] 19A, the terminal A functions as an input terminal, and the terminal Y functions as an output terminal. When a potential H is input to the terminal A of the NOT circuit, the terminal Y outputs a potential L, and when a potential L is input to the terminal A, the terminal Y outputs a potential H (see FIG. 19C).

[0401] 19C, the NOT circuit has a function of correcting an input signal distorted by wiring resistance, parasitic capacitance, noise, etc., to a signal that is distorted or has reduced distortion, and outputting the corrected signal. The NOT circuit also has a function of amplifying the voltage amplitude of the input signal, and the output of the NOT circuit is supplied to a load such as a capacitance element Cx and a transistor Trx.

[0402] [NOR Circuit] Fig. 20A is a circuit diagram showing an example of the configuration of a two-input, one-output NOR circuit (NOR). Fig. 20B shows a circuit symbol for the NOR circuit. The NOR circuit shown in Fig. 20A includes transistors Tr21, Tr22, Tr23, and Tr24. Si transistors functioning as p-channel transistors are used as the transistors Tr21 and Tr22, and OS transistors functioning as n-channel transistors are used as the transistors Tr23 and Tr24.

[0403] 20A , a potential H is supplied to one of the source or drain of transistor Tr21. The other of the source or drain of transistor Tr21 is connected to one of the source or drain of transistor Tr22. The other of the source or drain of transistor Tr22 is connected to one of the source or drain of transistor Tr23, one of the source or drain of transistor Tr24, and terminal Y. A potential L is supplied to the other of the source or drain of transistor Tr23 and the other of the source or drain of transistor Tr24.

[0404] The gate of the transistor Tr21 is connected to the gate of the transistor Tr23 and the terminal A. The gate of the transistor Tr22 is connected to the gate of the transistor Tr24 and the terminal B.

[0405] 20A and 20B has a function of outputting a potential H from a terminal Y when a potential L is input to both a terminal A and a terminal B. In addition, the NOR circuit has a function of outputting a potential L from a terminal Y when a potential H is input to one or both of the terminals A and B.

[0406] Furthermore, as shown in FIG. 20C, an OR circuit can be realized by connecting the input of a NOT circuit to the output of a NOR circuit.

[0407] [NAND Circuit] Fig. 20D is a circuit diagram showing a configuration example of a two-input, one-output NAND circuit (NAND). Fig. 20E shows a circuit symbol of the NAND circuit. The NAND circuit shown in Fig. 20D includes transistors Tr31, Tr32, Tr33, and Tr34. Si transistors functioning as p-channel transistors are used as the transistors Tr31 and Tr32, and OS transistors functioning as n-channel transistors are used as the transistors Tr33 and Tr34.

[0408] 20D , a potential H is supplied to one of the source or drain of transistor Tr31 and one of the source or drain of transistor Tr32. The other of the source or drain of transistor Tr31 and the other of the source or drain of transistor Tr32 are connected to one of the source or drain of transistor Tr33 and terminal Y. The other of the source or drain of transistor Tr33 is connected to one of the source or drain of transistor Tr34. A potential L is supplied to the other of the source or drain of transistor Tr34.

[0409] The gate of the transistor Tr31 is connected to the gate of the transistor Tr34 and the terminal B. The gate of the transistor Tr32 is connected to the gate of the transistor Tr33 and the terminal A.

[0410] 20D and 20E has a function of outputting a potential L from a terminal Y when a potential H is input to both the terminal A and the terminal B. In addition, the NAND circuit has a function of outputting a potential H from a terminal Y when a potential L is input to one or both of the terminal A and the terminal B.

[0411] Furthermore, as shown in FIG. 20F, an AND circuit can be realized by combining a NAND circuit with a NOT circuit.

[0412] [DFF Circuit] Fig. 21A is a circuit diagram showing an example of the configuration of a D flip-flop circuit (DFF). Fig. 21B shows the circuit symbol of the D flip-flop circuit. The DFF has a clock signal input terminal CK, an input terminal D, and an output terminal Q.

[0413] 21A includes transistors Tr41 to Tr49, transistors Tr51 to Tr59, transistor Tr61, transistor Tr62, transistor Tr71, and transistor Tr72. Si transistors functioning as p-channel transistors are used as the transistors Tr41 to Tr49, transistor Tr61, and transistor Tr62, and OS transistors functioning as n-channel transistors are used as the transistors Tr51 to Tr59, transistor Tr71, and transistor Tr72.

[0414] A potential H is supplied to one of the source or drain of transistor Tr41, one of the source or drain of transistor Tr42, one of the source or drain of transistor Tr44, one of the source or drain of transistor Tr46, one of the source or drain of transistor Tr48, one of the source or drain of transistor Tr61, and one of the source or drain of transistor Tr62.

[0415] The other of the source or drain of transistor Tr41 is connected to one of the source or drain of transistor Tr51, the gate of transistor Tr44, the gate of transistor Tr46, the gate of transistor Tr53, and the gate of transistor Tr59. The gate of transistor Tr41 is connected to clock signal input terminal CK, the gate of transistor Tr51, the gate of transistor Tr42, the gate of transistor Tr48, the gate of transistor Tr55, and the gate of transistor Tr57.

[0416] The other of the source or drain of transistor Tr42 is connected to one of the source or drain of transistor Tr43. The other of the source or drain of transistor Tr44 is connected to one of the source or drain of transistor Tr45. The other of the source or drain of transistor Tr43 is connected to the other of the source or drain of transistor Tr45, one of the source or drain of transistor Tr52, one of the source or drain of transistor Tr54, the gate of transistor Tr61, and the gate of transistor Tr71. The gate of transistor Tr43 is connected to the gate of transistor Tr52 and input terminal D.

[0417] The other of the source or drain of transistor Tr52 is connected to one of the source or drain of transistor Tr53. The other of the source or drain of transistor Tr54 is connected to one of the source or drain of transistor Tr55. The gate of transistor Tr45 is connected to the gate of transistor Tr54, the other of the source or drain of transistor Tr61, one of the source or drain of transistor Tr71, the gate of transistor Tr47, and the gate of transistor Tr56. The other of the source or drain of transistor Tr46 is connected to one of the source or drain of transistor Tr47. The other of the source or drain of transistor Tr48 is connected to one of the source or drain of transistor Tr49.

[0418] The other of the source or drain of transistor Tr47 is connected to one of the source or drain of transistor Tr56, the other of the source or drain of transistor Tr49, one of the source or drain of transistor Tr58, the gate of transistor Tr62, and the gate of transistor Tr72. The other of the source or drain of transistor Tr62 is connected to one of the source or drain of transistor Tr72, the gate of transistor Tr49, the gate of transistor Tr58, and output terminal Q.

[0419] The other of the source or the drain of transistor Tr56 is connected to one of the source or the drain of transistor Tr57. The other of the source or the drain of transistor Tr58 is connected to one of the source or the drain of transistor Tr59. A potential L is supplied to the other of the source or the drain of transistor Tr51, the other of the source or the drain of transistor Tr53, the other of the source or the drain of transistor Tr55, the other of the source or the drain of transistor Tr71, the other of the source or the drain of transistor Tr57, the other of the source or the drain of transistor Tr59, and the other of the source or the drain of transistor Tr72.

[0420] 21A and 21B has a function in which, while a potential H is being input to the clock signal input terminal CK, information (potential) supplied to the input terminal D is written to the DFF, and when the signal input to the clock signal input terminal CK changes from potential H to potential L, the information is held until the next time potential H is input to the clock signal input terminal CK. In addition, a signal (potential H or potential L) based on the information held by the DFF is always output from the output terminal Q.

[0421] FIG. 22A is a block diagram showing an example configuration of a shift register circuit (SR). The SR includes multiple DFFs. In this specification and elsewhere, the first-stage (first) DFF is referred to as "DFF[1]," and the potential (data) output from the output terminal Q of DFF[1] is referred to as "DATA OUT[1]." FIG. 22A shows a block diagram of an SR including four stages (four) of DFFs (DFF[1] to DFF[4]). In FIG. 22A, the data output from the output terminals Q of DFF[1] to DFF[4] are referred to as DATA OUT[1] to DATA OUT[4].

[0422] 22B is a timing chart illustrating the operation of the SR. The clock signal CLK is input to the clock signal input terminal CK of the odd-numbered DFF. The inverted signal of the clock signal CLK is input to the clock signal input terminal CK of the even-numbered DFF.

[0423] A pulse signal SPL is input to the input terminal D of DFF[1]. DFF[1] holds a signal corresponding to the input signal SPL in synchronization with the signal CLK and outputs it as data OUT[1]. Note that data OUT[1] has a value corresponding to the data held by DFF[1].

[0424] Furthermore, data OUT[1] is input to input terminal D of DFF[2]. DFF[2] holds a signal corresponding to the input data OUT[1] in synchronization with signal CLK and outputs it as data OUT[2]. Similarly, data OUT[2] is input to input terminal D of DFF[3], and data OUT[3] is input to input terminal D of DFF[4].

[0425] In this way, the SR has a function of sequentially transferring the input signal SPL to the subsequent DFF in synchronization with the signal CLK, and also has a function of sequentially switching the potentials of the data OUT[1] to OUT[4] output from the multiple DFFs in synchronization with the signal CLK.

[0426] Furthermore, it is preferable to provide an overlapping structure between a Si transistor and an OS transistor. By providing an overlapping structure between a Si transistor and an OS transistor, a circuit with a small occupancy area can be realized. Furthermore, an OS transistor operates stably even in a high-temperature environment and exhibits little fluctuation in characteristics. Therefore, the OS transistor is less susceptible to the heat generated by the Si transistor and can operate stably. Furthermore, by providing an overlapping structure between a Si transistor and an OS transistor, the connection distance between them can be made extremely short. As a result, wiring resistance and parasitic capacitance are reduced, enabling the circuit to operate at high speed. Furthermore, the power consumption of the circuit is reduced.

[0427] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0428] Embodiment 6 In this embodiment, application examples of a semiconductor device of one embodiment of the present invention will be described with reference to FIGS. 23A to 24E.

[0429] The semiconductor device of one embodiment of the present invention can be used in, for example, electronic components, mainframes, space equipment, data centers (also referred to as DCs), and various electronic devices. By using the semiconductor device of one embodiment of the present invention, low power consumption and high performance can be achieved for the electronic components, mainframes, space equipment, data centers, and various electronic devices.

[0430] Furthermore, a display device including the semiconductor device of one embodiment of the present invention can be used as a display portion of various electronic devices. A display device including the semiconductor device of one embodiment of the present invention can easily achieve high definition and high resolution.

[0431] Examples of electronic devices include electronic devices with relatively large screens such as television sets, desktop or notebook computers, computer monitors, digital signage, large game machines such as pachinko machines, as well as digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, personal digital assistants, and sound reproduction devices.

[0432] In particular, the display device according to one embodiment of the present invention is suitable for electronic devices having a relatively small display unit because it can increase the resolution. Examples of such electronic devices include wristwatch-type and bracelet-type information terminals (wearable devices), as well as head-mounted wearable devices such as VR devices such as head-mounted displays, AR glasses-type devices, and mixed reality (MR) devices.

[0433] The display device of one embodiment of the present invention preferably has extremely high resolution, such as HD (1280 × 720 pixels), FHD (1920 × 1080 pixels), WQHD (2560 × 1440 pixels), WQXGA (2560 × 1600 pixels), 4K (3840 × 2160 pixels), or 8K (7680 × 4320 pixels). A resolution of 4K, 8K, or higher is particularly preferable. Furthermore, the pixel density (resolution) of the display device of one embodiment of the present invention is preferably 100 ppi or more, 300 ppi or more, 500 ppi or more, 1000 ppi or more, 2000 ppi or more, 3000 ppi or more, 5000 ppi or more, or 7000 ppi or more. By using a display device having such high resolution and / or high resolution, it is possible to further enhance the sense of realism and depth. The display device of one embodiment of the present invention is not particularly limited in terms of the screen ratio (aspect ratio). For example, the display device can support various screen ratios such as 1:1 (square), 4:3, 16:9, or 16:10.

[0434] The electronic device of this embodiment may have a sensor (including the function of detecting, detecting, or measuring force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared rays).

[0435] The electronic device of the present embodiment can have various functions, such as a function to display various information (still images, videos, text images, etc.) on a display unit, a touch panel function, a function to display a calendar, date, time, etc., a function to execute various software (programs), a wireless communication function, and a function to read out programs or data recorded on a recording medium.

[0436] [Electronic Component] FIG. 23A shows a perspective view of a substrate (mounting substrate 819) on which electronic component 810 is mounted. Electronic component 810 shown in FIG. 23A has a semiconductor device 811 inside a mold 814. FIG. 23A omits some parts in order to show the interior of electronic component 810. Electronic component 810 has lands 815 on the outside of mold 814. Lands 815 are connected to electrode pads 816, and electrode pads 816 are connected to semiconductor device 811 via wires 817. Electronic component 810 is mounted on, for example, a printed circuit board 818. A plurality of such electronic components are combined and connected on printed circuit board 818 to complete mounting substrate 819.

[0437] The semiconductor device 811 also includes a drive circuit layer 812 and a memory layer 813. The memory layer 813 has a configuration in which multiple memory cell arrays are stacked. The stacked configuration of the drive circuit layer 812 and the memory layer 813 can be a monolithic stacked configuration. In a monolithic stacked configuration, the layers can be connected without using through-electrode technology such as TSV (Through Silicon Via) or bonding technology such as Cu-Cu direct bonding. By monolithically stacking the drive circuit layer 812 and the memory layer 813, for example, a so-called on-chip memory configuration can be achieved in which the memory is formed directly on the processor. The on-chip memory configuration enables the operation of the interface between the processor and the memory to be faster.

[0438] Furthermore, by configuring an on-chip memory, the size of the connection wiring can be reduced compared to technologies that use through electrodes such as TSVs, and the number of connection pins can be increased. Increasing the number of connection pins enables parallel operation, which makes it possible to improve the memory bandwidth (also called memory bandwidth).

[0439] It is also preferable that the memory cell arrays included in the memory layer 813 are formed using OS transistors and the memory cell arrays are monolithically stacked. By forming the memory cell arrays in a monolithic stacked structure, one or both of the memory bandwidth and the memory access latency can be improved. Note that the bandwidth is the amount of data transferred per unit time, and the access latency is the time from access to the start of data exchange. Note that when Si transistors are used for the memory layer 813, it is more difficult to form a monolithic stacked structure than when OS transistors are used. Therefore, it can be said that OS transistors have a superior structure to Si transistors in a monolithic stacked structure.

[0440] The semiconductor device 811 may also be referred to as a die. In this specification, a die refers to a chip piece obtained by forming a circuit pattern on, for example, a disk-shaped substrate (also called a wafer) and cutting it into dices during the semiconductor chip manufacturing process. Semiconductor materials that can be used for the die include, for example, silicon (Si), silicon carbide (SiC), and gallium nitride (GaN). For example, a die obtained from a silicon substrate (also called a silicon wafer) may be called a silicon die.

[0441] 23B shows a perspective view of an electronic component 820. The electronic component 820 is an example of a SiP (System in Package) or an MCM (Multi-Chip Module). The electronic component 820 has an interposer 821 provided on a package substrate 822 (printed circuit board), and a semiconductor device 824 and a plurality of semiconductor devices 811 provided on the interposer 821.

[0442] The electronic component 820 shows an example in which the semiconductor device 811 is used as a high bandwidth memory (HBM). The semiconductor device 824 can be used in an integrated circuit such as a CPU, a GPU, or an FPGA (Field Programmable Gate Array).

[0443] For example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate can be used as the package substrate 822. For example, a silicon interposer or a resin interposer can be used as the interposer 821.

[0444] The interposer 821 has a plurality of wirings and functions to connect a plurality of integrated circuits with different terminal pitches. The plurality of wirings are provided in a single layer or in multiple layers. The interposer 821 also functions to connect the integrated circuits provided on the interposer 821 to electrodes provided on the package substrate 822. For these reasons, the interposer may be called a "rewiring substrate" or "intermediate substrate." In some cases, through electrodes are provided in the interposer 821, and the integrated circuits and the package substrate 822 are connected using the through electrodes. In addition, in a silicon interposer, TSVs may also be used as through electrodes.

[0445] In an HBM, many wirings must be connected to achieve a wide memory bandwidth. Therefore, the interposer on which the HBM is mounted must have fine and high-density wiring. Therefore, it is preferable to use a silicon interposer for the interposer on which the HBM is mounted.

[0446] Furthermore, in SiPs, MCMs, and the like that use silicon interposers, a decrease in reliability due to differences in the coefficient of expansion between the integrated circuit and the interposer is unlikely to occur. Furthermore, because the silicon interposer has a highly flat surface, poor connection between the integrated circuit mounted on the silicon interposer and the silicon interposer is unlikely to occur. In particular, it is preferable to use silicon interposers in 2.5D packages (2.5-dimensional packaging) in which multiple integrated circuits are arranged horizontally on an interposer.

[0447] On the other hand, when connecting multiple integrated circuits with different terminal pitches using a silicon interposer, a TSV, or the like, a space is required, such as the width of the terminal pitch. Therefore, when attempting to reduce the size of the electronic component 820, the width of the terminal pitch becomes an issue, and it may be difficult to provide the many wirings necessary to achieve a wide memory bandwidth. Therefore, as described above, a monolithic stacked structure using OS transistors is preferable. A composite structure may be formed by combining a memory cell array stacked using TSVs and a monolithically stacked memory cell array.

[0448] A heat sink (heat dissipation plate) may be provided so as to overlap the electronic component 820. When a heat sink is provided, it is preferable to align the height of an integrated circuit provided on the interposer 821. For example, in the electronic component 820 shown in this embodiment, it is preferable to align the height of the semiconductor device 811 and the height of the semiconductor device 824.

[0449] Electrodes 823 may be provided on the bottom of the package substrate 822 in order to mount the electronic component 820 on another substrate. FIG. 23B shows an example in which the electrodes 823 are formed of solder balls. By providing solder balls in a matrix on the bottom of the package substrate 822, BGA (Ball Grid Array) mounting can be achieved. The electrodes 823 may also be formed of conductive pins. By providing conductive pins in a matrix on the bottom of the package substrate 822, PGA (Pin Grid Array) mounting can be achieved.

[0450] The electronic component 820 can be mounted on other substrates using various mounting methods, not limited to BGA and PGA, such as a staggered pin grid array (SPGA), a land grid array (LGA), a quad flat package (QFP), a quad flat J-leaded package (QFJ), and a quad flat non-leaded package (QFN).

[0451] 24A shows a perspective view of a mainframe computer 830. The mainframe computer 830 shown in Fig. 24A has a rack 831 housing a plurality of rack-mounted computers 832. The mainframe computer 830 may also be called a supercomputer.

[0452] The computer 832 can have the configuration shown in the perspective view of Fig. 24B, for example. In Fig. 24B, the computer 832 has a motherboard 842, which has a plurality of slots 843 and a plurality of connection terminals. A PC card 833 is inserted into the slot 843. In addition, the PC card 833 has connection terminals 835, 836, and 837, which are each connected to the motherboard 842.

[0453] A PC card 833 shown in Figure 24C is an example of a processing board equipped with a CPU, a GPU, a storage device, etc. The PC card 833 has a board 834. The board 834 also has a connection terminal 835, a connection terminal 836, a connection terminal 837, a semiconductor device 838, a semiconductor device 839, a semiconductor device 840, and a connection terminal 841. Note that Figure 24C illustrates semiconductor devices other than the semiconductor device 838, the semiconductor device 839, and the semiconductor device 840, but for these semiconductor devices, the following descriptions of the semiconductor device 838, the semiconductor device 839, and the semiconductor device 840 can be referred to.

[0454] The connection terminal 841 has a shape that allows it to be inserted into a slot 843 of the motherboard 842, and functions as an interface for connecting the PC card 833 and the motherboard 842. An example of the standard for the connection terminal 841 is PCIe.

[0455] The connection terminals 835, 836, and 837 can be, for example, interfaces for supplying power to the PC card 833, inputting signals, and the like. They can also be, for example, interfaces for outputting signals calculated by the PC card 833. Examples of standards for the connection terminals 835, 836, and 837 include USB (Universal Serial Bus), SATA (Serial ATA), and SCSI (Small Computer System Interface). In addition, when a video signal is output from the connection terminals 835, 836, and 837, examples of standards for the respective terminals include HDMI (registered trademark).

[0456] The semiconductor device 838 has a terminal (not shown) for inputting and outputting signals, and the semiconductor device 838 can be connected to the board 834 by inserting the terminal into a socket (not shown) provided on the board 834.

[0457] The semiconductor device 839 has a plurality of terminals, and the semiconductor device 839 can be connected to the board 834 by, for example, reflow soldering the terminals to wiring provided on the board 834. Examples of the semiconductor device 839 include an FPGA, a GPU, and a CPU. For example, the electronic component 820 can be used as the semiconductor device 839.

[0458] The semiconductor device 840 has a plurality of terminals, and the semiconductor device 840 can be connected to the board 834 by, for example, soldering the terminals to wiring provided on the board 834 using a reflow method. An example of the semiconductor device 840 is a memory device. For example, the electronic component 820 can be used as the semiconductor device 840.

[0459] The mainframe computer 830 can also function as a parallel computer. By using the mainframe computer 830 as a parallel computer, it is possible to perform large-scale calculations necessary for, for example, learning and inference in artificial intelligence.

[0460] [Space Equipment] The semiconductor device according to one embodiment of the present invention is suitable for space equipment.

[0461] A semiconductor device according to one embodiment of the present invention includes an OS transistor. Compared to a Si transistor, an OS transistor exhibits smaller variations in electrical characteristics due to radiation exposure. That is, an OS transistor has high radiation resistance and is therefore highly reliable and suitable for use in an environment where radiation may be incident. For example, an OS transistor is suitable for use in outer space. Specifically, an OS transistor can be used as a transistor for a semiconductor device provided in a space shuttle, an artificial satellite, or a space probe. Examples of radiation include X-rays and neutron rays. Note that outer space refers to an altitude of 100 km or higher, and the outer space described in this specification can include one or more of the thermosphere, the mesosphere, and the stratosphere.

[0462] Fig. 24D shows an artificial satellite 850 as an example of space equipment. The artificial satellite 850 has a body 851, a solar panel 852, an antenna 853, a secondary battery 855, and a control device 856. Note that Fig. 24D also shows a planet 854 in space.

[0463] 24D , a battery management system (also referred to as a BMS) or a battery control circuit may be provided for the secondary battery 855. The use of an OS transistor in the battery management system or the battery control circuit is preferable because it consumes low power and has high reliability even in space.

[0464] Furthermore, outer space is an environment with radiation levels 100 times higher than on Earth. Examples of radiation include electromagnetic waves (electromagnetic radiation) such as X-rays and gamma rays, and particle radiation such as alpha rays, beta rays, neutron rays, proton rays, heavy ion rays, and meson rays.

[0465] When sunlight is irradiated onto the solar panel 852, the power required for the operation of the satellite 850 is generated. However, for example, in a situation where sunlight is not irradiated onto the solar panel or where the amount of sunlight irradiating the solar panel is small, the generated power is small. Therefore, there is a possibility that the power required for the operation of the satellite 850 will not be generated. In order to operate the satellite 850 even in a situation where the generated power is small, it is advisable to provide a secondary battery 855 on the satellite 850. The solar panel may also be called a solar cell module.

[0466] The artificial satellite 850 can generate a signal. The signal is transmitted via an antenna 853, and can be received by, for example, a receiver installed on the ground or another artificial satellite. By receiving the signal transmitted by the artificial satellite 850, the position of the receiver that received the signal can be determined. As described above, the artificial satellite 850 can constitute a satellite positioning system.

[0467] The control device 856 has a function of controlling the artificial satellite 850. The control device 856 is configured using, for example, one or more selected from a CPU, a GPU, and a storage device. Note that the control device 856 is preferably a semiconductor device including an OS transistor which is one embodiment of the present invention.

[0468] The artificial satellite 850 can also be configured to include a sensor. For example, by including a visible light sensor, the artificial satellite 850 can have the function of detecting sunlight reflected from an object on the ground. Alternatively, by including a thermal infrared sensor, the artificial satellite 850 can have the function of detecting thermal infrared rays emitted from the earth's surface. As described above, the artificial satellite 850 can function as, for example, an earth observation satellite.

[0469] Although an artificial satellite is given as an example of space equipment in this embodiment, the invention is not limited thereto. For example, the semiconductor device of one embodiment of the present invention is suitable for space equipment such as a spaceship, a space capsule, and a space probe.

[0470] As described above, OS transistors have excellent advantages over Si transistors, such as the ability to achieve a wide memory bandwidth and high radiation resistance.

[0471] [Data Center] The semiconductor device according to one embodiment of the present invention is suitable for a storage system applied to, for example, a data center. Data centers are required to perform long-term management of data, such as ensuring the immutability of data. Managing long-term data requires larger buildings, such as installing storage and servers for storing huge amounts of data, ensuring a stable power supply for maintaining the data, or ensuring cooling equipment required for maintaining the data.

[0472] By using the semiconductor device of one embodiment of the present invention in a storage system applied to a data center, it is possible to reduce the power required to store data and the size of the semiconductor device that stores data. Therefore, it is possible to reduce the size of the storage system, the size of the power supply for storing data, the scale of the cooling equipment, and the like. Therefore, it is possible to reduce the space required for the data center.

[0473] Furthermore, the semiconductor device of one embodiment of the present invention has low power consumption, which allows heat generation from the circuit to be reduced. Therefore, adverse effects of the heat generation on the circuit itself, peripheral circuits, and modules can be reduced. Furthermore, by using the semiconductor device of one embodiment of the present invention, a data center that operates stably even in a high-temperature environment can be realized. Therefore, the reliability of the data center can be improved.

[0474] Fig. 24E shows a storage system applicable to a data center. The storage system 860 shown in Fig. 24E has a plurality of servers 861sb as hosts 861. It also has a plurality of storage devices 863md as storage 863. The host 861 and storage 863 are shown connected via a storage area network 864 and a storage control circuit 862.

[0475] The host 861 corresponds to a computer that accesses data stored in the storage 863. The hosts 861 may be connected to each other via a network.

[0476] Although the storage 863 uses flash memory to reduce the data access speed, i.e., the time required to store and output data, this time is significantly longer than the time required for DRAM, which can be used as cache memory within the storage. In order to solve the problem of the long access speed of the storage 863, a storage system typically provides cache memory within the storage to reduce the time required to store and output data.

[0477] The cache memory described above is used in the storage control circuit 862 and the storage 863. Data exchanged between the host 861 and the storage 863 is stored in the cache memory in the storage control circuit 862 and the storage 863, and then output to the host 861 or the storage 863.

[0478] By using OS transistors as transistors for storing data in the cache memory and holding a potential corresponding to the data, the frequency of refresh operations can be reduced, and power consumption can be reduced.

[0479] Note that the semiconductor device of one embodiment of the present invention can reduce power consumption by applying it to any one or more of electronic components, mainframe computers, space equipment, data centers, and electronic devices. Therefore, while energy demand is expected to increase with the improvement in performance or high integration of semiconductor devices, the use of the semiconductor device of one embodiment of the present invention can reduce carbon dioxide (CO ２ Furthermore, the semiconductor device of one embodiment of the present invention is effective as a countermeasure against global warming because it consumes low power.

[0480] This embodiment mode can be combined with other embodiment modes as appropriate. In addition, in this specification, when a plurality of configuration examples are shown in one embodiment mode, the configuration examples can be combined as appropriate.

[0481] In this example, transistors having a structure similar to that of the transistor 50A shown in FIGS. 6A to 6D are fabricated using three types of samples (sample A, sample B, and sample C) that are fabricated under different conditions. The results of observing cross-sectional STEM images and evaluating electrical characteristics are described.

[0482] <Structure and Fabrication of Samples> For some of the structures of the transistors included in Samples A to C, the structures illustrated in FIGS. 6A to 6D can be referred to.

[0483] The semiconductor layer 51 is a stacked film of a semiconductor layer 51_1, a semiconductor layer 51_2, and a semiconductor layer 51_3 (see FIG. 4A).

[0484] The samples A to C were fabricated by the same method except for the conditions of heat treatment after deposition of the film to be the semiconductor layer 51_2. The conditions of deposition of the film to be the semiconductor layer 51_2 were different between the samples A and B and the sample C.

[0485] The insulating layer 81 is a silicon nitride film with a thickness of 60 nm formed by sputtering. The insulating layer 82 is an aluminum oxide film with a thickness of 40 nm formed by sputtering. The insulating layer 83 is a silicon oxide film with a thickness of 40 nm formed by sputtering.

[0486] The conductive layer 71 is a laminated film of a titanium nitride film formed by CVD and a tungsten film formed on the titanium nitride film by CVD.

[0487] The insulating layer 72 is a silicon nitride film with a thickness of 5 nm formed by PEALD (Plasma Enhanced ALD), the insulating layer 73 is a hafnium oxide film with a thickness of 15 nm formed by thermal ALD, and the insulating layer 74 is a silicon oxide film with a thickness of 20 nm formed by sputtering.

[0488] The semiconductor layer 51_1 is an indium gallium zinc oxide film having a thickness of 10 nm and formed by a sputtering method using an oxide target having an atomic ratio of In:Ga:Zn=1:3:2.

[0489] In each of Sample A and Sample B, the semiconductor layer 51_2 is an indium oxide film with a thickness of 5 nm formed by an ALD method. In Sample C, the semiconductor layer 51_2 is an indium oxide film with a thickness of 5 nm formed by a sputtering method. ２ O ３ Using the target, H ２ The film was formed in an atmosphere containing 5% of the gas.

[0490] For Sample B and Sample C, heat treatment was performed after the film that becomes the semiconductor layer 51_2 was formed. For Sample B, microwave treatment was performed at a treatment temperature of 400° C. for 600 seconds. Here, microwave treatment refers to treatment using, for example, an apparatus having a power source that generates high-density plasma using microwaves. In this specification, microwaves refer to electromagnetic waves having a frequency of 300 MHz or more and 300 GHz or less. For Sample C, N ２ Gas flow rate 4 slm, O ２ The heat treatment was carried out in a mixed atmosphere with a gas flow rate of 1 slm at 250° C. for 1 hour. Note that the heat treatment was not carried out for Sample A.

[0491] The semiconductor layer 51_3 is a 5-nm-thick indium gallium zinc oxide film formed by a sputtering method using an oxide target having an atomic ratio of In:Ga:Zn=1:1:1.2.

[0492] After the film to be the semiconductor layer 51_3 was formed, a heat treatment was performed. ２ Gas flow rate 4 slm, O ２ Heat treatment was carried out at 450° C. for 1 hour in a mixed atmosphere with a gas flow rate of 1 slm.

[0493] Each of the conductive layers 54a and 54b is a stack of a tantalum nitride film having a thickness of 5 nm and a tungsten film having a thickness of 15 nm, both of which are formed by sputtering. The tantalum nitride film is a conductive film that will become the conductive layers 54a1 and 54b1, and the tungsten film is a conductive film that will become the conductive layers 54a2 and 54b2 (see FIG. 7B ).

[0494] The transistors included in Samples A to C each include a first insulating layer between the conductive layer 54a and the insulating layer 61 and between the conductive layer 54b and the insulating layer 61. The first insulating layer is a stacked film including a silicon nitride film with a thickness of 5 nm formed by a sputtering method and a silicon oxide film with a thickness of 10 nm formed over the silicon nitride film by a sputtering method.

[0495] The insulating layer 61 is a silicon nitride film having a thickness of 5 nm and formed by the PEALD method, and the insulating layer 62 is a silicon oxide film formed by the sputtering method.

[0496] Openings 63 were formed in the insulating layers 62 and 61. Subsequently, portions of the conductive film that would become the conductive layers 54a2 and 54b2, overlapping with the openings 63, were removed to separate the conductive film, thereby forming the conductive layers 54a2 and 54b2. Subsequently, an insulating film that would become the insulating layer 58 was formed. The insulating film was a silicon nitride film with a thickness of 4.6 nm formed by the PEALD method. Subsequently, the insulating film was subjected to dry etching to form the sidewall-shaped insulating layer 58 that contacts the sidewall of the opening 63. Subsequently, the conductive layer that would become the conductive layer 54a1 and the conductive layer 54b1 was separated using the insulating layer 62 and the insulating layer 58 as masks, thereby forming the conductive layer 54a1 and the conductive layer 54b1. After the formation of the conductive layer 54a and the conductive layer 54b, Samples A to C were washed with carbonated water. Subsequently, Samples A to C were subjected to heat treatment. The heat treatment was performed using N ２ Gas flow rate 4 slm, O ２ The heat treatment was carried out at atmospheric pressure at 350° C. for 1 hour in a mixed atmosphere with a gas flow rate of 1 slm.

[0497] The insulating layer 52 is a laminated film including a first hafnium oxide film having a thickness of 1 nm formed by thermal ALD, a silicon oxide film having a thickness of 2 nm formed on the first hafnium oxide film by PEALD, a second hafnium oxide film having a thickness of 2 nm formed on the silicon oxide film by thermal ALD, and a silicon nitride film having a thickness of 1 nm formed on the second hafnium oxide film by PEALD.

[0498] After the formation of the silicon oxide film and the second hafnium oxide film, microwave treatment was performed using argon gas (150 sccm) and oxygen gas (50 sccm) as treatment gases, with a power of 4000 W, a pressure of 400 Pa, a treatment temperature of 250° C., and a treatment time of 600 seconds.

[0499] The conductive layer 53 is a laminated film of a titanium nitride film formed by CVD and a tungsten film formed on the titanium nitride film by CVD.

[0500] The insulating layer 84 is an aluminum oxide film with a thickness of 10 nm formed by sputtering. The insulating layer 85 is a silicon nitride film with a thickness of 20 nm formed by sputtering. The insulating layer 86 is a silicon oxide film with a thickness of 50 nm formed by sputtering.

[0501] Each of the conductive layers 76a and 76b is a laminated film of a titanium nitride film formed by CVD and a tungsten film formed on the titanium nitride film by CVD.

[0502] The transistors included in Samples A to C each have a second insulating layer between the conductive layer 76 a and a sidewall of an opening where the conductive layer 76 a is provided and between the conductive layer 76 a and a sidewall of an opening where the conductive layer 76 b is provided and the conductive layer 76 b. The second insulating layer is a stacked film of an aluminum oxide film formed by a thermal ALD method and a silicon nitride film formed over the silicon oxide film by a PEALD method.

[0503] In this manner, samples A to C were prepared.

[0504] <Cross-Section Observation> First, a cross-sectional STEM image of the transistor was taken for Sample C. The cross-sectional STEM image was taken for a transistor in Sample C having a channel length (design value) of 30 nm and a channel width (design value) of 20 nm.

[0505] 25 shows a cross-sectional STEM image of the transistor in Sample C. Here, FIG. 25 is a bright-field STEM image of a cross section in the channel width direction of the transistor in Sample C. It was confirmed that a transistor similar to the schematic diagrams shown in FIG. 6C and the like was formed.

[0506] <Id-Vg Characteristics> The electrical characteristics of the transistors of Samples A to C fabricated above were evaluated. Specifically, the Id-Vg characteristics of the transistors were measured. The Id-Vg characteristics were measured by sweeping the top gate potential Vg from −4.0 V to 4.0 V in 0.1 V increments, with the drain potential Vd set to 0.1 V or 1.2 V, the source potential Vs set to 0 V, and the bottom gate potential Vbg set to 0 V.

[0507] The measurement was performed on a transistor having a channel length (design value) of 30 nm and a channel width (design value) of 30 nm, with the number of measurements being 9 within the substrate surface.

[0508] 26A to 26C show the measurement results of the Id-Vg characteristics of the transistors in Samples A to C, respectively. FIG. 26A shows the measurement results of the transistors in Sample A, FIG. 26B shows the measurement results of the transistors in Sample B, and FIG. 26C shows the measurement results of the transistors in Sample C. In each of FIGS. 26A to 26C, the horizontal axis represents the top gate potential Vg [V], the left vertical axis (first vertical axis) represents the drain current Id [A], and the right vertical axis (second vertical axis) represents the field-effect mobility μFE [cm ２ 26A to 26C each show the Id-Vg characteristics of nine transistors in an overlapping manner.

[0509] 26A to 26C, the shift value Vsh of the transistor in each sample was calculated. Furthermore, the median (Vsh_m) and the variation (standard deviation, Vsh_σ) of the shift values ​​of the nine transistors in each sample were calculated.

[0510] Comparing Samples A to C, Sample C had a Vsh_m of 0.02 V, making it the only sample among the three to exhibit normally-off electrical characteristics. Sample C also had the smallest Vsh_σ (88 mV). Therefore, it can be said that Sample C exhibited the best results in terms of the shift value Vsh. The on-state current Ion, S value, Vsh, and Vth values ​​for Sample C are shown in Table 6. In Table 6, Vth_m refers to the median value of the threshold voltage Vth, and Vth_σ refers to the variation (standard deviation) of the threshold voltage Vth. The difference between Samples A to C is the heat treatment conditions after deposition of the film that becomes the semiconductor layer 51_2. Therefore, the difference in the heat treatment may have caused differences in the way oxygen was supplied to the semiconductor layer 51, which may have contributed to the differences in transistor characteristics between the samples.

[0511]

[0512] On the other hand, the field-effect mobility also differed between the samples. The highest field-effect mobility was obtained for sample C, and the median value of the field-effect mobility μFE of the nine transistors shown in FIG. 26C was 9.1 cm when Vd = 0.1 V. ２ / (V·s), and when Vd = 1.2 V, it is 10.2 cm ２ / (V·s).

[0513] Of the three samples fabricated this time, even sample C, which gave the best results, had a field effect mobility of 10.0 cm ２ / (V·s), and the 50 cm ２ / (V·s) or more was not obtained. This is presumably because the contact resistance between the semiconductor layer 51 and the conductive layer 54a and the contact resistance between the semiconductor layer 51 and the conductive layer 54b are larger than the channel resistance due to the material of the semiconductor layer 51, and this limits the field effect mobility. Therefore, by reducing the external resistance other than these channel resistances, it is possible to achieve a value of 50 cm as described in the third embodiment. ２ / (V·s) or more, even 100 cm ２It is expected that a field effect mobility of 1 / (V·s) or more can be realized.

[0514] <Cutoff Frequency> Measurement of the cutoff frequency of the transistor was performed for Sample C fabricated above. The measurement was performed on a transistor (Transistor X) having a channel length (design value) of 16 nm and a channel width (design value) of 20 nm, a transistor (Transistor Y) having a channel length (design value) of 20 nm and a channel width (design value) of 20 nm, and a transistor (Transistor Z) having a channel length (design value) of 30 nm and a channel width (design value) of 20 nm.

[0515] 27A to 27C show the measurement results of the cutoff frequency of each transistor. FIG. 27A shows the measurement results for transistor X, FIG. 27B shows the measurement results for transistor Y, and FIG. 27C shows the measurement results for transistor Z. In each figure, dB(|H21|) on the vertical axis represents the logarithm (common logarithm) of the transistor's current gain (the ratio of the top gate current to the drain current), and the horizontal axis represents the input voltage frequency [GHz]. The solid lines in each figure represent the measured values ​​of the transistor's current gain, and the dashed lines in each figure represent extrapolated lines fitted based on the measured values. In each figure, the frequency at which the current gain is 1 (i.e., dB(|H21|) = 0) is the cutoff frequency (fT). In FIGS. 27A to 27C, the points where the extrapolated line intersects with the line where dB(|H21|) = 0 are indicated by arrows, and the frequency value corresponding to these points is shown in each figure as the cutoff frequency.

[0516] The input voltages during measurement for the transistor X were a drain potential (Vd) of 2.5 V, a source potential (Vs) of 0 V, a bottom gate potential (Vbg) of 0 V, and a top gate potential (Vg) of 1.60 V. For the transistors Y and Z, the input voltages were a drain potential (Vd) of 2.5 V, a source potential (Vs) of 0 V, a bottom gate potential (Vbg) of 0 V, and a top gate potential (Vg) of 1.65 V, respectively.

[0517] The cutoff frequency of each transistor can be estimated from the frequency at which dB(|H21|) = 0 on the extrapolated lines shown in each of Figures 27A to 27C. There is a tendency for the cutoff frequency to increase as the channel length of the transistor decreases. In this example, the cutoff frequency of transistor X was estimated to be 54.5 GHz (Figure 27A), the cutoff frequency of transistor Y was estimated to be 29.3 GHz (Figure 27B), and the cutoff frequency of transistor Z was estimated to be 18.4 GHz (Figure 27C). A higher cutoff frequency is preferable because it increases the operating speed of the transistor.

[0518] In this example, the cutoff frequency of the transistor of one embodiment of the present invention was also verified by device simulation using "Sentaurus Device" manufactured by Synopsys, Inc.

[0519] In the device simulation, a transistor having a structure similar to that of the transistors in Samples A to C was assumed, and the cutoff frequency estimated when the size (channel length, channel width, etc.) and field-effect mobility of the transistor were set as conditions was calculated.

[0520] Table 7 shows a list of transistor size conditions used in this device simulation. In Table 7, L represents the channel length of the transistor, Lg represents the gate length of the transistor, and W represents the channel width of the transistor. In the case of the transistor 50A shown in FIGS. 3A to 3D, the channel length L corresponds to the distance between the opposing ends of the conductive layers 54a and 54b in the cross-sectional view shown in FIG. 3B. The gate length Lg corresponds to the width of the conductive layer 53 in the cross-sectional view shown in FIG. 3B. The channel width W corresponds to the width of the semiconductor layer 51 in the cross-sectional view shown in FIG. 3C.

[0521]

[0522] Table 8 shows a list of calculation conditions used in this device simulation. In this example, it is assumed that the semiconductor layer 51 has a two-layer structure of semiconductor layers 51_1 and 51_2, and that indium gallium zinc oxide is used for the semiconductor layer 51_1, and indium oxide is used for the semiconductor layer 51_2. The electron mobility of the semiconductor layer 51_2, which is listed as "condition" in Table 8, corresponds to the field-effect mobility of the transistor.

[0523] In this example, it was assumed that insulating layers 72, 73, and 74 were made of silicon nitride with a thickness of 5 nm, hafnium oxide with a thickness of 15 nm, and silicon oxide with a thickness of 20 nm, respectively. It was also assumed that the first insulating layers provided between conductive layer 54a and insulating layer 61, and between conductive layer 54b and insulating layer 61, respectively, were made of a stacked structure of silicon nitride with a thickness of 5 nm and silicon oxide with a thickness of 10 nm. It was also assumed that insulating layer 61 was made of silicon nitride with a thickness of 5 nm. It was also assumed that insulating layer 62 was made of silicon oxide with a thickness of 35 nm in the portions overlapping conductive layers 54a and 54b. It was also assumed that insulating layer 52 was made of a stacked structure of first hafnium oxide with a thickness of 1 nm, silicon oxide with a thickness of 2 nm, second hafnium oxide with a thickness of 2 nm, and silicon nitride with a thickness of 1 nm. It was also assumed that conductive layer 53 was made of tungsten. Also, a case was assumed in which aluminum oxide with a film thickness of 10 nm was used as the insulating layer 84 .

[0524] Note that the "external resistance" shown in Table 8 refers to all resistance components other than the channel resistance of the transistor, such as the contact resistance between the semiconductor layer 51 and the conductive layer 54a, the contact resistance between the semiconductor layer 51 and the conductive layer 54b, etc. Also, in Table 8, AlOx represents aluminum oxide, HfOx represents hafnium oxide, SiOx represents silicon oxide, and SiNx represents silicon nitride.

[0525]

[0526] The cutoff frequency of the transistor was calculated based on the various conditions shown in Tables 7 and 8. The results are shown in Figures 28A and 28B. Figure 28A is a graph showing the gate length (Lg) dependency of the cutoff frequency (fT) of the transistor, and Figure 28B is a graph showing the Lg dependency and field-effect mobility (μFE) dependency of fT.

[0527] 28A, the horizontal axis represents gate length Lg [nm], and the vertical axis represents cutoff frequency fT [GHz]. Also, FIG. 28A shows calculation results for three transistors (transistor IO(A), transistor IO(B), and transistor IO(C)) with different field-effect mobilities. For transistor IO(A), transistor IO(B), and transistor IO(C), μFE (when the drain potential Vd of the transistor is 1.2 V) when Lg is 48 nm (L is 60 nm) is 100 cm ２ / (V・s), 80cm ２ / (V·s), and 40 cm ２ 28A, the square plots are the results for the transistor IO(A), the black triangle plots are the results for the transistor IO(B), and the white triangle plots are the results for the transistor IO(C).

[0528] 28A shows that for all transistors, the shorter the gate length (Lg), the higher the cutoff frequency (fT). It can also be seen that the higher the field-effect mobility (μFE) of a transistor, the higher the cutoff frequency. It can also be seen from FIG. 28B that the shorter the gate length of a transistor and the higher the field-effect mobility, the higher the cutoff frequency that can be achieved.

[0529] In the graph of Figure 28A, a straight line corresponding to a cutoff frequency of 261 GHz is drawn. This is the value indicated in the roadmap for Si transistors (gate length 16 nm) announced in 2022 (see Non-Patent Document 5). The calculation results shown in Figure 28A reveal that if a transistor with a gate length of less than 15 nm having the field-effect mobility assumed in transistor IO(A) or transistor IO(B) can be realized, it may be possible to realize a cutoff frequency equal to or higher than the value of the Si transistor indicated in the roadmap.

[0530] As miniaturization progresses, it becomes necessary to consider ballistic conduction. In ballistic conduction, carriers are conducted between the source and drain electrodes without scattering, which dissipates energy. In this example, to consider ballistic conduction, the electrical conduction was calculated using the non-equilibrium Green's function (NEGF) method.

[0531] The model used for the calculation is shown in Figure 29. Indium oxide was placed as the channel, with the carrier (electron) conduction direction set to the X direction. The indium oxide was placed so that the

[110] direction of the indium oxide crystal was parallel to the X direction and the

[001] direction of the indium oxide crystal was parallel to the Z direction. A dielectric with a film thickness of 1 nm and a relative dielectric constant of 20 was placed to mimic a gate insulating film. It was assumed that the interface between the dielectric and the channel was terminated to eliminate the level near the conduction band, so that conduction was not affected. In this model, a periodic boundary condition was imposed in the Y direction and a Neumann boundary condition in the Z direction.

[0532] The calculation conditions are shown in Table 9.

[0533]

[0534] The Id-Vg characteristics obtained by the above calculation are shown in Figure 30. In Figure 30, the horizontal axis represents the top gate potential Vg [V], and the vertical axis represents the drain current Id [A / μm] per 1 μm of channel width. The transconductance gm calculated from the Id-Vg characteristics shown in Figure 30 was 15 mS.

[0535] 29, when the capacitance C of the gate insulating film is calculated as a parallel plate, the capacitance C is 1.06 fF. In addition, the cutoff frequency (fT) estimated using the following formula (2) is about 2.2 THz.

[0536]

[0537] FIG. 31 is obtained by plotting the above results on the results shown in FIG. 28A. It can be seen from FIG. 31 that the above values ​​are significantly larger than the values ​​shown in Non-Patent Document 5. Note that the graph in FIG. 31 also includes a line corresponding to a cutoff frequency of 261 GHz, a line corresponding to a cutoff frequency of 308 GHz, and a line corresponding to a cutoff frequency of 358 GHz. These values ​​are shown in Non-Patent Document 5.

[0538] Incidentally, when parasitic capacitance is taken into consideration, the capacitance C increases as the thickness of the gate insulating film increases. In the above calculation model, the capacitance C roughly saturated when the gate insulating film thickness was about 10 nm. The capacitance C at saturation was about 1.87 fF. The fT at this time was estimated to be about 1.27 THz. In other words, even when parasitic capacitance is included, this value is found to be significantly larger than the value shown in Non-Patent Document 5.

[0539] <Off-State Current> The off-state current of the transistors fabricated above, such as Sample C, was measured. Note that the off-state current of an OS transistor is much smaller than that of a Si transistor (for example, 1×10 −１２ (Less than A). Therefore, it is difficult to directly detect the off-state current from the measurement results of the Id-Vg characteristics described above. Therefore, in this example, an attempt was made to indirectly estimate the off-state current of the transistors in Sample C and the like using a measurement system configured with the circuit diagram shown in FIG.

[0540] 32 includes transistors 101, 102, 103, and 104. The gate of the transistor 101 is connected to the input terminal IN_1, one of the source or the drain of the transistor 101 is connected to the input terminal IN_2, the gate of the transistor 102 is connected to the input terminal IN_3, one of the source or the drain of the transistor 102 is connected to the input terminal IN_4, the gate of the transistor 103 is connected to the other of the source or the drain of the transistor 101 and the other of the source or the drain of the transistor 102, one of the source or the drain of the transistor 103 is connected to one of the source or the drain of the transistor 104 and the output terminal OUT, the gate of the transistor 104 is connected to the input terminal IN_5, the other of the source or the drain of the transistor 104 is connected to the input terminal IN_6, and the other of the source or the drain of the transistor 103 is connected to the input terminal IN_7. A node connected to the gate of the transistor 103 (i.e., a node connected to the gate of the transistor 103, the other of the source or the drain of the transistor 101, and the other of the source or the drain of the transistor 102) is shown as a node FN. Note that the transistor under test (the transistor whose off-state current is measured) here is the transistor 102.

[0541] To measure minute currents, it is necessary to increase the current to a level where it is possible to detect the charge that moves due to the small current. Therefore, in order to increase the measurement current per unit channel width, 20,000 transistors connected in parallel were used as the transistors 102 to be measured.

[0542] 32 , the transistor 101 functions as a transistor that writes a potential to the node FN (also referred to as a writing transistor), and the transistors 103 and 104 function as transistors that read the potential held in the node FN (also referred to as reading transistors).

[0543] The off-state current of the transistor 102 was indirectly estimated by measuring the change in the amount of charge at the node FN over a long period of time using the measurement system having the above configuration.

[0544] The measurement method will be explained.

[0545] First, a potential difference is generated between the input terminals IN_1 and IN_2 to turn on the transistor 101, and the potential of the input terminal IN_2 is written to the node FN. At this time, the input terminals IN_3 and IN_4 are controlled so that the transistor 102 is turned off. After that, the input terminals IN_1 and IN_2 are controlled so that the transistor 101 is turned off, and the potential V ＦＮ After that, the measurement period starts. During the measurement period, the potentials of the input terminals IN_3 and IN_4 are fixed so that the transistor 102 is not conductive. On the other hand, the potential V ＦＮ As a result, charge flows due to the off-state current (which may be referred to as leakage current) of the transistor 102, and the potential V ＦＮ That is, as the amount of charge held in the node FN changes, the potential V ＦＮ As a result, the potential V of the output terminal OUT changes. ＯＵＴ also fluctuates.

[0546] Therefore, the potential V of the output terminal OUT ＯＵＴ By measuring the fluctuation of the potential V ＦＮ The amount of fluctuation can be detected.

[0547] Here, the capacitance of node FN is C ＦＮ , the measurement period is Δt, and the potential V ＦＮ The amount of change in ΔV ＦＮ Then, the off-state current I of the transistor 102 is ｏｆｆ can be expressed by the following equation (3).

[0548]

[0549] In formula (3), C ＦＮare values ​​(known values) determined by the material, thickness, etc. of the wiring that actually constitutes the measurement system, so the measured values ​​Δt and ΔV ＦＮ By substituting each of these into Equation (3), the off-state current I of the transistor 102 is ｏｆｆ In this example, the off-state current I can be calculated using the transistor 102 including a Si transistor, the transistor 102 including the OS transistor 1, the transistor 102 including the OS transistor 2, and the transistor 102 including the OS transistor 3. ｏｆｆ was calculated.

[0550] FIG. 33 shows the off-current I of various transistors estimated by the above-mentioned method. ｏｆｆ In FIG. 33, the vertical axis represents the off-state current I per 1 μm of channel width. ｏｆｆ 33 shows the calculated values ​​for four transistors, namely, a Si transistor, an OS transistor 1, an OS transistor 2, and an OS transistor 3. The horizontal axis represents the reciprocal of the measurement temperature (T), 1000 / T [1 / K].

[0551] The off-state current of the Si transistor is calculated using a transistor with a channel length (design value) of 60 nm and a channel width (design value) of 120 nm. Note that the measurement was performed when the top gate-source potential (Vgs) of the transistor 102 was 0.0 V and the potential of the node FN (V ＦＮ ) was fixed at 1.2 V, and the substrate temperatures were 27°C, 85°C, and 150°C.

[0552] The OS transistor 1 is a transistor included in Sample C, and the off-state current is calculated using a transistor with a channel length (design value) of 30 nm and a channel width (design value) of 30 nm. The channel width of the transistor 102 is 0.6 mm (design value). The measurements were performed with the top gate-source potential (Vgs) of the transistor 102 set to −2.0 V, the bottom gate potential (Vbg) set to −3.0 V, and the potential of the node FN (V ＦＮ) was fixed at 1.2 V, and the substrate temperature was set at 85°C and 100°C.

[0553] The OS transistor 2 is a transistor included in Sample C, and the off-state current is calculated using a transistor with a channel length (design value) of 60 nm and a channel width (design value) of 60 nm. The channel width of the transistor 102 is 1.2 mm (design value). The measurements were performed with the top gate-source potential (Vgs) of the transistor 102 set to −1.5 V, the bottom gate potential (Vbg) set to −3.0 V, and the potential of the node FN (V ＦＮ ) was fixed at 1.2 V, and the substrate temperatures were 85°C, 100°C, and 125°C.

[0554] The off-state current of the OS transistor 3 is calculated using a transistor with a channel length (design value) of 30 nm and a channel width (design value) of 30 nm, and the transistor 3 is a transistor using indium gallium zinc oxide for a semiconductor layer functioning as a channel formation region. Note that the measurement was performed when the top gate-source potential (Vgs) of the transistor 102 was −1.0 V, the bottom gate potential (Vbg) was −12 V, and the potential of the node FN (V ＦＮ ) was fixed at 1.2 V, and the test was carried out under conditions of substrate temperatures of 85°C, 125°C, and 150°C.

[0555] 33, it was confirmed that the off-state current of the OS transistor is smaller than that of a Si transistor by 10 orders of magnitude or more. Furthermore, when comparing OS transistors, it was confirmed that the off-state current of the transistor using indium gallium zinc oxide for the semiconductor layer 51_2 (OS transistor 3) is smaller than that of the transistors using indium oxide for the semiconductor layer 51_2 (OS transistor 1 and OS transistor 2) regardless of the measurement temperature.

[0556] The off-state current I at room temperature (substrate temperature 27° C.) calculated from the extrapolated line of the Arrhenius plot of each transistor shown in FIG. ｏｆｆ The current dissipation was 0.23 nA / μm for the Si transistor, 4.68 zA / μm for the OS transistor 1, 0.96 zA / μm for the OS transistor 2, and 11.1 yA / μm for the OS transistor 3. Note that 1 yA is 1×10−２４ More specifically, the off-state current per μm of channel width of OS transistor 2 was 117 zA / μm at 85° C. and 957 yA / μm at room temperature (substrate temperature 27° C.) calculated from the extrapolated line of the Arrhenius plot.

[0557] From the above, results suggesting that by configuring a semiconductor device using an OS transistor with indium oxide for the semiconductor layer 51_2, for example, by applying the semiconductor device to a memory device, a memory device with extremely excellent retention characteristics can be realized.

[0558] At least a part of the configurations, methods, and the like shown in this embodiment can be implemented in appropriate combination with other embodiment modes described in this specification.

[0559] 11: Undercoat film, 12: Crystal portion, 13: Metal oxide layer, 13a: Region, 13c: Crystal grain, 50A: Transistor, 51: Semiconductor layer, 51_1: Semiconductor layer, 51_2: Semiconductor layer, 51_3: Semiconductor layer, 52: Insulating layer, 53: Conductive layer, 54a: Conductive layer, 54a1: Conductive layer, 54a2: Conductive layer, 54b: Conductive layer, 54b1: Conductive layer, 54b2: Conductive layer, 58: Insulating layer, 59: Insulating layer, 61: Insulating layer, 62: Insulating layer, 63: Opening, 64: Opening, 71: Conductive layer, 72: Insulating layer, 73: Insulating layer, 74: Insulating layer, 76a: Conductive layer, 76b: Conductive layer, 76b1: Conductive layer, 76b2: conductive layer, 81: insulating layer, 82: insulating layer, 83: insulating layer, 84: insulating layer, 85: insulating layer, 86: insulating layer, 101: transistor, 102: transistor, 103: transistor, 104: transistor, 207: conductive layer, 208: insulating layer, 209: conductive layer, 210: insulating layer, 240: conductive layer, 241: insulating layer, 284: insulating layer, 310: transistor, 311: substrate, 313: semiconductor region, 314a: low resistance region, 314b: low resistance region, 315: insulating layer, 316: conductive layer, 318: element isolation layer, 320: insulating layer, 322: insulating layer, 324: insulating layer, 326: insulating layer, 328: conductive layer, 330: conductive layer, 453: conductive layer, 454: insulating layer, 460: conductive layer, 810: electronic component, 811: semiconductor device, 812: drive circuit layer, 813: memory layer, 814: mold, 815: land, 816: electrode pad, 817: wire, 818: printed circuit board, 819: mounting board, 820: electronic component, 821: interposer, 822: package board, 823: electrode, 824: semiconductor device, 830: mainframe computer, 831: rack, 832: computer, 833: PC card, 834: board, 835: connection terminal, 836: Connection terminal, 837: connection terminal, 838: semiconductor device, 839: semiconductor device, 840: semiconductor device, 841: connection terminal, 842: motherboard, 843: slot, 850: artificial satellite, 851: aircraft, 852: solar panel, 853: antenna, 854: planet, 855: secondary battery, 856: control device, 860: storage system, 861: host, 861sb: server, 862: storage control circuit, 863: storage, 863md: storage device, 864: storage area network, 900: semiconductor device, 910: drive circuit, 911: peripheral circuit,912: Control circuit, 915: Peripheral circuit, 920[1]: Memory array, 920[2]: Memory array, 920[m]: Memory array, 920: Memory array, 923: Row driver, 924: Column driver, 925: Input circuit, 926: Output circuit, 927: Sense amplifier, 928: Voltage generation circuit, 930: Layer, 931: PSW, 932: PSW, 941: Row decoder, 942: Column decoder, 950: Memory cell, 951: Memory cell, 952: Memory cell, 953: Memory cell, 954: Memory cell, 95 5: memory cell, 956: memory cell, 957: memory cell, 958: memory cell, 960: arithmetic unit, 961: substrate, 962: ALU, 962c: ALU controller, 963: instruction decoder, 964: interrupt controller, 965: timing controller, 966: register, 967: register controller, 968: bus interface, 969: cache, 969i: cache interface, 970A: semiconductor device, 970B: semiconductor device, 970C: semiconductor device,

Claims

A method for forming a metal oxide layer containing indium and oxygen and having crystal grains, comprising: a first step of forming a crystal portion on an underlayer; a second step of forming the metal oxide layer to cover the crystal portion, In the second step, the crystal grains are formed in the metal oxide layer by first crystal growth and second crystal growth; the first crystal growth occurs in a first direction; the second crystal growth occurs in a second direction perpendicular or substantially perpendicular to the first direction; A method for forming a metal oxide layer, wherein the first crystal growth rate is faster than the second crystal growth rate. 　 In claim 1, The method for forming a metal oxide layer, wherein the second direction is perpendicular or approximately perpendicular to the surface of the base film on which the crystal portion is disposed. 　 In claim 1, The method for forming a metal oxide layer, wherein the crystal grains have a grain size of 10 nm or more and 100 nm or less. 　 In claim 1, The method for forming a metal oxide layer comprises forming the metal oxide layer using atomic layer deposition. 　 In claim 1, A method for forming a metal oxide layer, comprising forming the metal oxide layer having an amorphous structure by a sputtering method, and then performing a heat treatment to form the crystal grains. 　 In claim 5, A method for forming a metal oxide layer, using a gas containing hydrogen as a sputtering gas. 　 In claim 1, The crystal structure of the crystal grains is a cubic system, The method for forming a metal oxide layer, wherein the second direction is parallel to the <111> orientation of the crystal grains. 　 In claim 7, the crystal structure of the crystalline portion is a cubic system, The method for forming a metal oxide layer, wherein the <111> orientation of the crystal portion is parallel or approximately parallel to the second direction. 　 In claim 8, The method for forming a metal oxide layer, wherein the crystalline portion contains indium and oxygen. 　 In claim 8, The method for forming a metal oxide layer, wherein the crystalline portion contains indium, tin, and oxygen. 　 In claim 7, the crystal structure of the crystalline portion is hexagonal or trigonal, The method for forming a metal oxide layer, wherein the c-axis direction of the crystal portion is parallel or approximately parallel to the second direction. 　 In claim 11, The method for forming a metal oxide layer, wherein the crystalline portion contains indium, gallium, zinc, and oxygen. 　 In claim 12, the crystalline portion has a composition of In:Ga:Zn=1:1:1 [atomic ratio] or a composition therearound, or a composition of In:Ga:Zn=1:3:2 [atomic ratio] or a composition therearound.

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