Semiconductor device and method for producing semiconductor device

Abstract

The present invention provides a transistor having favorable electrical characteristics. A semiconductor device according to the present invention includes first through third conductive layers, a semiconductor layer, and first and second insulating layers. The first insulating layer is located on the first conductive layer and has an opening that extends to the first conductive layer. The second conductive layer is located on the first insulating layer. The semiconductor layer includes: a portion in contact with the upper surface and side surface of the second conductive layer; a portion in contact with the side surface of the first insulating layer within the opening; and a portion in contact with the upper surface of the first conductive layer within the opening. The second insulating layer covers the semiconductor layer within the opening. The third conductive layer covers the second insulating layer within the opening. Furthermore, the first conductive layer and the second conductive layer contain indium. In addition, the semiconductor layer contains indium oxide, no grain boundaries are observed in the portion in contact with the first insulating layer in a cross section parallel to the height direction of the opening, and the crystal orientations of two or more portions in contact with the first insulating layer coincide.

Description

Semiconductor device and method for manufacturing the same

[0001] 1. Field of the Invention One embodiment of the present invention relates to a semiconductor device, a transistor, or a memory device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. Examples of the technical field of one embodiment of the present invention disclosed in this specification and the like include semiconductor devices, display devices, light-emitting devices, power storage devices, memory devices, electronic devices, lighting devices, input devices, input / output devices, driving methods thereof, and manufacturing methods thereof. A semiconductor device refers to any device that can function by utilizing semiconductor characteristics.

[0003] In recent years, semiconductor devices have been developed, and LSIs such as CPUs (Central Processing Units), memories, and other large-scale integrated circuits (LSIs) are mainly used in semiconductor devices. A CPU is an assembly of semiconductor elements that have been processed from a semiconductor wafer and have semiconductor integrated circuits (at least transistors and memories) formed into chips, and on which electrodes serving as connection terminals are formed.

[0004] 2. Description of the Related Art A CPU, a memory, or other LSI semiconductor circuit (IC chip) is mounted on a circuit board, such as a printed wiring board, and is used as one of the components of various electronic devices.

[0005] Furthermore, a technique for constructing a transistor using a semiconductor thin film formed on a substrate having an insulating surface has attracted attention. Such transistors are widely applied to electronic devices such as integrated circuits and image display devices (also simply referred to as display devices). While silicon-based semiconductor materials are widely known as semiconductor thin films applicable to transistors, oxide semiconductors have also attracted attention as other materials.

[0006] Furthermore, it is known that a transistor including an oxide semiconductor has an extremely small leakage current in a non-conducting state. For example, Patent Document 1 discloses a low-power consumption CPU that utilizes the property of a small leakage current. Furthermore, Patent Document 2 discloses a memory device that can retain stored data for a long period of time.

[0007] JP 2012-257187 A JP 2011-151383 A

[0008] Takashi Koida, "High Mobility Transparent Conductive Film," National Institute of Advanced Industrial Science and Technology, AIST Photovoltaic Power Generation Research Results Report 2019, Internet <URL: https: / / unit.aist.go.jp / rpd-envene / PV / ja / results / 2019 / oral / T13.pdf>

[0009] An object of one embodiment of the present invention is to provide a transistor capable of passing a large current. Another object is to provide a transistor with favorable electrical characteristics. Another object is to provide a transistor that can be miniaturized. Another object is to provide a transistor that occupies a small area. Another object is to provide a transistor that combines miniaturization with high reliability. Another object is to provide a memory device in which transistors can be arranged at high density.

[0010] An object of one embodiment of the present invention is to provide a semiconductor device, a memory device, or an electronic device having a novel structure. An object of one embodiment of the present invention is to alleviate at least one of the problems of the prior art.

[0011] Note that the description of these problems does not preclude the existence of other problems. Note that one embodiment of the present invention does not necessarily solve all of these problems. Note that problems other than these can be extracted from the description of the specification, drawings, claims, etc.

[0012] One embodiment of the present invention is a semiconductor device including a first conductive layer, a second conductive layer, a third conductive layer, a semiconductor layer, a first insulating layer, and a second insulating layer. The first insulating layer has a portion located on the first conductive layer and has an opening reaching the first conductive layer. The second conductive layer has a portion located on the first insulating layer. The semiconductor layer has a portion in contact with a top surface and a side surface of the second conductive layer, a portion in contact with a side surface of the first insulating layer in the opening, and a portion in contact with a top surface of the first conductive layer in the opening. The second insulating layer covers the semiconductor layer in the opening. The third conductive layer covers the second insulating layer in the opening. The portion of the first conductive layer in contact with the semiconductor layer and the portion of the second conductive layer in contact with the semiconductor layer each contain an oxide containing indium. In addition, the semiconductor layer contains indium oxide, and no grain boundaries are observed in the portion in contact with the first insulating layer in a cross section parallel to the height direction of the opening, and the crystal orientations of two or more portions in contact with the first insulating layer are the same.

[0013] Another embodiment of the present invention is a semiconductor device including a first conductive layer, a second conductive layer, a third conductive layer, a semiconductor layer, a first insulating layer, and a second insulating layer. The first insulating layer has a portion located on the first conductive layer and has an opening reaching the first conductive layer. The second conductive layer has a portion located on the first insulating layer. The semiconductor layer has a portion in contact with a top surface and a side surface of the second conductive layer, a portion in contact with a side surface of the first insulating layer in the opening, and a portion in contact with a top surface of the first conductive layer in the opening. The second insulating layer covers the semiconductor layer in the opening. The third conductive layer covers the second insulating layer in the opening. The portion of the first conductive layer in contact with the semiconductor layer and the portion of the second conductive layer in contact with the semiconductor layer each contain an oxide containing indium. The semiconductor layer contains indium oxide, and in a cross section parallel to the height direction of the opening, no grain boundaries are observed in the portion in contact with the first insulating layer, and the portion in contact with the first insulating layer has a region in which the crystal is twisted around a specific crystal orientation without any grain boundaries.

[0014] In any of the above, the semiconductor layer preferably has an annular shape in a cross section perpendicular to the height direction of the opening, and more preferably, the crystal orientations of two or more portions in the cross section are the same.

[0015] In any of the above, the first conductive layer and the second conductive layer each preferably have a first layer and a second layer on the first layer. In this case, the second layer preferably has an upper surface in contact with the semiconductor layer. Furthermore, the second layer preferably contains indium and tin and has a polycrystalline structure or a single crystalline structure.

[0016] In any of the above, the first conductive layer preferably has crystallinity, and the semiconductor layer preferably has a region whose crystal orientation coincides with that of the crystalline region of the first conductive layer.

[0017] Another embodiment of the present invention is a method for manufacturing a semiconductor device, including: forming a first insulating layer over a first conductive layer; forming a second conductive layer over the first insulating layer; forming an opening in the first insulating layer that reaches the first conductive layer; performing heat treatment; and forming a semiconductor film in contact with a top surface of the second conductive layer, a side surface of the first insulating layer in the opening, and a top surface of the first conductive layer in the opening. Further, the first conductive layer and the second conductive layer contain metal oxide containing indium, and the semiconductor film contains indium oxide.

[0018] In the above, the heat treatment is preferably carried out at a temperature of 100° C. or higher and 400° C. or lower in a reduced pressure atmosphere.

[0019] In the above, it is preferable that the first conductive layer and the second conductive layer each contain indium and tin and have a polycrystalline structure or a single crystalline structure after heat treatment.

[0020] According to one embodiment of the present invention, a transistor capable of passing a large current can be provided. Alternatively, a transistor with favorable electrical characteristics can be provided. Alternatively, a transistor that can be miniaturized can be provided. Alternatively, a transistor that occupies a small area can be provided. Alternatively, a transistor that can be miniaturized and has high reliability can be provided. Alternatively, a memory device in which transistors can be arranged at high density can be provided.

[0021] According to one aspect of the present invention, it is possible to provide a semiconductor device, a memory device, or an electronic device having a novel configuration. According to one aspect of the present invention, it is possible to at least alleviate at least one of the problems of the prior art.

[0022] Note that the description of these effects does not preclude the existence of other effects. Note that one embodiment of the present invention does not necessarily have all of these effects. Note that effects other than these can be extracted from the description in the specification, drawings, claims, etc.

[0023] FIGS. 1A and 1B are structural examples of a semiconductor device. FIGS. 2A and 2B are structural examples of a semiconductor device. FIGS. 3A and 3B are structural examples of a semiconductor device. FIGS. 4A and 4B are structural examples of a semiconductor device. FIGS. 5A and 5B are structural examples of a semiconductor device. FIGS. 6A and 6B are structural examples of a semiconductor device. FIGS. 7A, 7B, 7C, and 7D are diagrams illustrating an example of a method for manufacturing a semiconductor device. FIGS. 8A, 8B, and 8C are diagrams illustrating an example of a method for manufacturing a semiconductor device. FIG. 9 is a diagram illustrating an example of a method for manufacturing a semiconductor device. FIGS. 10A and 10B are diagrams illustrating an example of a method for manufacturing a semiconductor device. FIGS. 11A, 11B, and 11C are structural examples of memory devices. FIGS. 12A, 12B, and 12C are structural examples of memory devices. FIGS. 13A and 13B are structural examples of memory devices. FIGS. 14A and 14B are structural examples of memory devices. 15A and 15B are configuration examples of a memory device. FIG. 16 is a configuration example of a memory device. FIG. 17 is a configuration example of a memory device. FIGS. 18A and 18B are configuration examples of a memory device. FIGS. 19A and 19B are configuration examples of a memory device. FIGS. 20A and 20B are diagrams illustrating the carrier concentration dependence of Hall mobility. FIG. 20C is a cross-sectional view illustrating an indium oxide film. FIG. 21 is a block diagram illustrating a configuration example of a semiconductor device. FIGS. 22A, 22B, 22C, 22D, 22E, 22F, 22G, and 22H are diagrams illustrating circuit configuration examples of memory cells. FIGS. 23A and 23B are perspective views illustrating a configuration example of a semiconductor device. FIG. 24 is a block diagram illustrating a CPU. FIGS. 25A and 25B are perspective views of a semiconductor device. FIGS. 26A and 26B are perspective views of a semiconductor device. FIGS. 27A and 27B are configuration examples of electronic components. 28A, 28B, and 28C are configuration examples of a mainframe computer. FIG. 29A is a configuration example of space equipment. FIG. 29B is a configuration example of a storage system. FIG. 30 is an evaluation result of sheet resistance according to Example 1. FIG. 31 is a cross-sectional observation image according to Example 2. FIG. 32 is a cross-sectional observation image according to Example 2. FIG. 33 is a cross-sectional observation image according to Example 2. FIGS. 34A, 34B, and 34C are measurement results of electrical characteristics according to Example 2.35A, 35B, and 35C show reliability evaluation results for Example 2. FIG. 36 is a cross-sectional observation image for Example 3. FIGS. 37A and 37B show electrical characteristic measurement results for Example 3. FIGS. 38A, 38B, and 38C show reliability evaluation results for Example 3.

[0024] Hereinafter, embodiments will be described with reference to the drawings. However, it will be readily understood by those skilled in the art that the embodiments can be implemented in many different ways and that various changes in form and details can be made without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the following description of the embodiments.

[0025] In the configuration of the invention described below, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and repeated explanations thereof will be omitted. Furthermore, when referring to similar functions, the same hatching pattern may be used and no particular reference numeral may be assigned.

[0026] In the drawings described in this specification, the size of each component, the thickness of a layer, or an area may be exaggerated for clarity, and therefore, the drawings are not necessarily limited to the scale.

[0027] In this specification, ordinal numbers such as "first" and "second" are used to avoid confusion of components and do not limit the number.

[0028] A transistor is a type of semiconductor element that can perform functions such as amplifying current or voltage and performing switching operations to control conduction or non-conduction. The term "transistor" as used herein includes an insulated gate field effect transistor (IGFET) and a thin film transistor (TFT).

[0029] Furthermore, the functions of "source" and "drain" may be interchangeable when transistors of different polarities are used, or when the direction of current flow changes during circuit operation, etc. For this reason, the terms "source" and "drain" may be used interchangeably in this specification.

[0030] In this specification and the like, either the source or the drain of a transistor may be referred to as a “first electrode,” and the other of the source or the drain may be referred to as a “second electrode.” The gate may also be referred to as a “gate” or a “gate electrode.”

[0031] In this specification, "connection" includes "electrical connection." "A and B are electrically connected" means that, among the cases where A and B are connected without an insulator (where A and B are connected via a conductor or semiconductor, or where A and B are in contact), there is a time when an exchange of electrical signals or an interaction of potentials occurs between A and B during circuit operation. In other words, even if there is a time during circuit operation when an exchange of electrical signals or an interaction of potentials does not occur between A and B, it can be said that "A and B are electrically connected" as long as there is a time when an exchange of electrical signals or an interaction of potentials occurs between A and B.

[0032] An "electrical connection" includes a connection (direct connection) that does not involve a circuit element (for example, a transistor, but excluding wiring), and a connection (indirect connection) that involves one or more circuit elements.

[0033] In this specification, the phrase "top surface shapes generally match" refers to the overlap of at least a portion of the contours between stacked layers. For example, this includes cases where the upper and lower layers are processed using the same mask pattern or a portion of the same mask pattern. However, strictly speaking, the contours may not overlap, and the upper layer may be located inside the lower layer, or outside the lower layer. In these cases, the phrase "top surface shapes generally match" may also be used.

[0034] In this specification, the top surface shape of a certain component refers to the contour shape of the component in a plan view. The plan view refers to a view from the normal direction of the surface on which the component is formed or the surface of a support (e.g., a substrate) on which the component is formed.

[0035] In the following, expressions indicating directions such as "up" and "down" will basically be used in accordance with the directions in the drawings. However, for purposes such as facilitating explanation, the directions indicated by "up" or "down" in the specification may not match those in the drawings. For example, when explaining the stacking order (or formation order) of a laminate, etc., even if the surface on which the laminate is provided (such as a forming surface, a support surface, an adhesive surface, or a flat surface) is located above the laminate in the drawings, the forming surface side may be expressed as "down" and the direction opposite to the forming surface as "up."

[0036] In this specification, the channel length direction of a transistor refers to one of the directions parallel to the line connecting the source region and the drain region at the shortest distance. In other words, the channel length direction corresponds to one of the directions of current flowing through the semiconductor layer when the transistor is in an on-state. The channel width direction refers to a direction perpendicular to the channel length direction. Depending on the structure or shape of the transistor, the channel length direction and the channel width direction may not be defined as a single direction.

[0037] In addition, in this specification and the like, the terms "film" and "layer" are interchangeable. For example, the term "insulating layer" may be interchangeable with the term "insulating film."

[0038] Unless otherwise specified, in this specification and the like, the off-state current refers to the drain current when a transistor is in an off state (also referred to as a non-conducting state or a cut-off state). Unless otherwise specified, the off-state refers to a state in which the gate-source voltage Vgs is lower than the threshold voltage Vth for an n-channel transistor (higher than Vth for a p-channel transistor).

[0039] In this specification, space groups are expressed using short notation in international notation (or Hermann-Mauguin notation). Crystal planes and crystal orientations are expressed using Miller indices. In crystallography, space groups, crystal planes, and crystal orientations are expressed by adding a superscript bar to the numbers. However, due to formatting restrictions, in this specification, instead of adding a bar above the numbers, they may be expressed by adding a minus sign (-) before the numbers. Furthermore, individual orientations indicating directions within a crystal are expressed with [ ], collective orientations indicating all equivalent orientations are expressed with < >, individual planes indicating crystal planes are expressed with ( ), and collective planes with equivalent symmetry are expressed with {}.

[0040] In this specification, "two lines parallel" refers to a state in which the two lines are arranged at an angle of -10 degrees or more and 10 degrees or less. "Two lines approximately parallel" refers to a state in which the two lines are arranged at an angle of -30 degrees or more and 30 degrees or less (including parallel). "Two lines perpendicular" refers to a state in which the two lines are arranged at an angle of 80 degrees or more and 100 degrees or less. "Two lines approximately perpendicular" refers to a state in which the two lines are arranged at an angle of 60 degrees or more and 120 degrees or less (including perpendicular).

[0041] In this specification, "two surfaces are parallel" refers to a state in which their interior angle is between -10 degrees and 10 degrees. "Two surfaces are approximately parallel" refers to a state in which their interior angle is between -30 degrees and 30 degrees (including parallel). "Two surfaces are perpendicular" refers to a state in which their interior angle is between 80 degrees and 100 degrees (including perpendicular). "Two surfaces are approximately perpendicular" refers to a state in which their interior angle is between 60 degrees and 120 degrees (including perpendicular).

[0042] Embodiment 1 In this embodiment, a structure example of a transistor according to one embodiment of the present invention and an example of a method for manufacturing the transistor will be described.

[0043] In a transistor according to one embodiment of the present invention, a source electrode and a drain electrode are located at different heights, and a current flows in a semiconductor layer in the height direction. That is, it can be said that the channel length direction has a component in the height direction (vertical direction). Therefore, one embodiment of the present invention can be called a VFET (Vertical Field Effect Transistor), a vertical transistor, a vertical channel transistor, a vertical channel transistor, or the like.

[0044] More specifically, a first insulating layer functioning as a first spacer is provided to cover a lower electrode, which is one of the source and drain electrodes of a transistor, and an upper electrode, which is the other of the source and drain electrodes, is provided on the first insulating layer. A semiconductor layer is provided inside an opening provided in the first insulating layer, in contact with the lower electrode and in which a channel is formed along a side surface of the first insulating layer. The semiconductor layer is also in contact with an upper electrode located on the first insulating layer. Furthermore, a gate insulating layer is provided inside the opening in the first insulating layer along the semiconductor layer, and a gate electrode is provided so as to overlap the semiconductor layer via the gate insulating layer. Note that the opening may also be referred to as an opening.

[0045] An oxide semiconductor is preferably used for the semiconductor layer. For example, silicon, which is a typical semiconductor material, needs to be doped with impurities that function as donors or acceptors to form source and drain regions. However, in the vertical transistor of one embodiment of the present invention, it may be difficult to dope impurities into the semiconductor layer with high precision because the source and drain are at different heights and the channel formation region is located vertically relative to the substrate surface. On the other hand, an oxide semiconductor can be well connected to source and drain electrodes without doping with such impurities. Therefore, a transistor having a three-dimensional structure as in one embodiment of the present invention can be manufactured with high yield.

[0046] Furthermore, it is preferable to use an oxide conductor for at least the portion of the upper electrode and the lower electrode that is in contact with the semiconductor layer. In particular, it is preferable to use an oxide conductor containing the same metal element as the semiconductor layer, because this reduces the contact resistance between the upper electrode or the lower electrode and the semiconductor layer. For example, it is preferable to use an oxide containing one or more of In, Sn, Zn, Ga, and Ti for each of the semiconductor layer, the upper electrode, and the lower electrode, and it is particularly preferable to use an oxide containing In.

[0047] Furthermore, it is preferable to use a crystalline metal oxide film for the upper electrode and the lower electrode. This allows the metal oxide film to have a crystalline structure that reflects the crystalline structure of the upper electrode and the lower electrode when forming the metal oxide film that will become the semiconductor layer in contact with the upper electrode and the lower electrode, or by subsequent heat treatment. In particular, the metal oxide film can be formed so that a portion of the metal oxide film provided along the sidewall of the opening in the first insulating layer (the side surface of the first insulating layer located within the opening) has a single-crystalline region with a uniform crystal orientation. This allows for the realization of a transistor whose channel formation region has a substantially single-crystalline structure. This allows for the realization of a high-performance transistor that combines high field-effect mobility, high on-current, extremely low off-current, and high reliability.

[0048] In addition, in the manufacturing process of a transistor, it is preferable to perform heat treatment after forming an opening in the first insulating layer that reaches the lower electrode and before forming a metal oxide film that will become a semiconductor layer, which can reduce the electrical resistance of the exposed upper electrode and lower electrode, thereby achieving a higher on-state current and a higher field-effect mobility.

[0049] A more specific example will be described below with reference to the drawings.

[0050] [Configuration Example 1] Figures 1A and 1B each show a perspective view of a transistor 10. In each figure, arrows indicate the X, Y, and Z directions. Figure 1B is a perspective view with a portion cut away from Figure 1A. Note that in Figures 1A and 1B, only the outlines of insulating layers 41 and 42, which function as interlayer insulating layers, are shown by dashed lines.

[0051] 2A and 2B show cross-sectional views of the transistor 10. Fig. 2A shows a cross section cut along a plane perpendicular to the X direction, and Fig. 2B shows a cross section cut along a plane perpendicular to the Y direction.

[0052] The transistor 10 is provided over an insulating layer 11 provided over a substrate (not shown). The insulating layer 11 functions as a base insulating layer. The transistor 10 includes a semiconductor layer 21, an insulating layer 22 functioning as a gate insulating layer, a conductive layer 23 functioning as a gate electrode, a conductive layer 24 functioning as one of a source electrode and a drain electrode, and a conductive layer 25 functioning as the other electrode. Here, an example is shown in which the conductive layer 23 includes a conductive layer 23a and a conductive layer 23b, the conductive layer 24 includes a conductive layer 24a and a conductive layer 24b, and the conductive layer 25 includes a conductive layer 25a and a conductive layer 25b.

[0053] An insulating layer 45 may be provided between the insulating layer 11 and the conductive layer 24. The insulating layer 45 functions as a protective insulating layer. The insulating layer 45 has a function (barrier property) of preventing impurities such as hydrogen from diffusing into the semiconductor layer 21 from the insulating layer 11 or from below the insulating layer 11. For example, a film through which hydrogen is less likely to diffuse than a silicon oxide film (having barrier property against hydrogen) such as a silicon nitride film, a silicon nitride oxide film, an aluminum oxide film, a magnesium oxide film, a hafnium oxide film, or a gallium oxide film can be used. In particular, it is preferable to use a silicon nitride film or a silicon nitride oxide film.

[0054] In this specification and elsewhere, an oxynitride refers to a material whose composition contains more oxygen than nitrogen, and a nitride oxide refers to a material whose composition contains more nitrogen than oxygen. For example, silicon oxynitride refers to a material whose composition contains more oxygen than nitrogen, and silicon nitride oxide refers to a material whose composition contains more nitrogen than oxygen.

[0055] Furthermore, the conductive layer 23 is connected to the conductive layer 31 which functions as a gate wiring. Furthermore, the conductive layers 24 and 25 each function as wiring. Here, an example is shown in which the conductive layers 31 and 24 extend in the X direction, and the conductive layer 25 extends in the Y direction. However, the extension direction of each conductive layer is not limited to this, and the conductive layers may extend in a direction other than the X direction or the Y direction.

[0056] An insulating layer 41 that covers the conductive layer 24 and functions as a spacer is provided, and a conductive layer 25 is provided on the insulating layer 41. Here, an example is shown in which the insulating layer 41 includes insulating layers 41a, 41b, and 41c. The insulating layer 41 has an opening 20a that reaches the conductive layer 24. Here, an example is shown in which the conductive layer 25 also has an opening that overlaps with the opening 20a.

[0057] The semiconductor layer 21 has a portion in contact with the upper surface of the conductive layer 25, a portion in contact with the side surface of the conductive layer 25, a portion in contact with the side surface of the insulating layer 41 inside the opening 20a, and a portion in contact with the upper surface of the conductive layer 24 at the bottom of the opening 20a. Here, an example is shown in which the conductive layer 24 has a recess that overlaps with the opening 20a, and the semiconductor layer 21 is provided along the surface of the recess. This increases the contact area between the semiconductor layer 21 and the conductive layer 24, and reduces the contact resistance therebetween.

[0058] The insulating layer 22 is provided to cover the insulating layer 41, the conductive layer 25, and the semiconductor layer 21. The insulating layer 22 is provided along the surface of the semiconductor layer 21 inside the opening 20a.

[0059] An insulating layer 42 is provided on the insulating layer 22. The insulating layer 42 functions as an interlayer insulating layer. The insulating layer 42 has an opening 20b that overlaps with the opening 20a.

[0060] The conductive layer 23 is provided so as to fill the openings 20a and 20b. The conductive layer 23 is also provided so as to cover the insulating layer 22 within the opening 20a. Here, the upper surface of the conductive layer 23 is flattened so that the height of the upper surface is approximately the same as the upper surface of the insulating layer 42. The conductive layer 31 is also provided on the insulating layer 42, and the conductive layer 31 is in contact with the upper surface of the conductive layer 23. The conductive layer 31 functions as a gate wiring.

[0061] By providing the insulating layer 42, which functions as an interlayer insulating layer, between the conductive layer 31, which functions as a gate wiring, and the conductive layer 25 and the semiconductor layer 21 on the conductive layer 25, it is possible to reduce the parasitic capacitance therebetween. This makes it possible to realize a transistor 10 that can operate at even higher speeds. Furthermore, by providing the insulating layer 42, it is possible to significantly reduce the parasitic capacitance between the conductive layer 24 and the conductive layer 31. Therefore, it is possible to make the conductive layer 24 and the conductive layer 31 extend in the same direction, thereby increasing the degree of freedom in circuit design.

[0062] An insulating layer 43 is provided between the conductive layer 23 and the insulating layer 42, and between the insulating layer 22 and the insulating layer 42. As with the insulating layer 45, an insulating film having barrier properties can be used for the insulating layer 43. By providing the insulating layer 43, for example, it is possible to prevent oxygen contained in the insulating layer 42 from diffusing into the conductive layer 23 and oxidizing the conductive layer 23. It is also possible to prevent hydrogen contained in the insulating layer 42 from diffusing into the semiconductor layer 21 via the conductive layer 23 or the insulating layer 22.

[0063] In the transistor 10, the source electrode and the drain electrode are located at different heights, and therefore, a current flows in the height direction through the semiconductor. That is, it can be said that the channel length direction has a component in the height direction (vertical direction). Therefore, the transistor of one embodiment of the present invention can also be called a VFET, a vertical transistor, a vertical channel transistor, or the like. Since the transistor 10 can have two or more of the source electrode, the semiconductor, and the drain electrode stacked, the occupied area can be significantly reduced compared to a so-called planar transistor (which can also be called a lateral transistor, LFET (lateral FET), or the like) in which the semiconductor is arranged on a plane.

[0064] Furthermore, the channel length of the transistor 10 can be precisely controlled by the thickness of the insulating layer 41, which functions as a spacer. This significantly reduces the variation in channel length compared to planar transistors. Furthermore, by thinning the insulating layer 41, transistors with extremely short channel lengths can be fabricated. For example, transistors with channel lengths of 2 μm or less, 1 μm or less, 500 nm or less, 300 nm or less, 200 nm or less, 100 nm or less, 50 nm or less, 30 nm or less, or 20 nm or less, and 5 nm or more, 7 nm or more, or 10 nm or more, can be fabricated. Therefore, transistors with extremely short channel lengths that could not be achieved using mass-production exposure equipment can be realized. Furthermore, transistors with channel lengths of less than 10 nm can be fabricated without using the extremely expensive exposure equipment used in cutting-edge LSI technology.

[0065] Although various semiconductor materials can be used for the semiconductor layer 21, it is particularly preferable to use an oxide semiconductor containing a metal oxide. By using an oxide semiconductor formed under appropriate conditions, a transistor having both a high on-state current and an extremely low off-state current can be realized at low cost. Unless otherwise specified, the following describes a preferred configuration example in which an oxide semiconductor is used for the semiconductor layer 21.

[0066] In particular, it is preferable to use indium oxide for the semiconductor layer 21. By using single-crystal or polycrystalline indium oxide, a high-performance transistor can be realized that combines high field-effect mobility, high on-current, extremely low off-current, and high reliability. In this case, since there are no grain boundaries across the current path between the source electrode and the drain electrode in the channel formation region, an even higher on-current can be realized.

[0067] Here, the conductive layer 24 and the conductive layer 25 each have a stacked structure. The conductive layer 24b and the conductive layer 25b are configured to be in contact with the semiconductor layer 21. Therefore, if an oxide semiconductor is used for the semiconductor layer 21, the surfaces of the conductive layer 24b and the conductive layer 25b may be oxidized due to the influence of heat applied during or after the film formation process of the semiconductor film that becomes the semiconductor layer 21, forming an insulating oxide film between the conductive layer 24b and the semiconductor layer 21, which may increase the contact resistance. Therefore, it is preferable to use an oxide conductor containing a conductive oxide for the conductive layer 24b and the conductive layer 25b. This can prevent an increase in contact resistance due to oxidation of the surfaces of the conductive layer 24b and the conductive layer 25b. The conductive layer 24b and the conductive layer 25b may also be called an oxide layer, a metal oxide layer, an oxide conductor layer, or the like.

[0068] In particular, it is preferable that the conductive layer 24b and the conductive layer 25b each use a metal oxide containing the same metal element as the semiconductor layer 21. In particular, it is preferable that the semiconductor layer 21, the conductive layer 24b, and the conductive layer 25b each contain one or more of In, Sn, Zn, Ga, and Ti, and it is particularly preferable that they contain In.

[0069] In particular, it is preferable to use a metal oxide having a polycrystalline structure or a single-crystalline structure for the conductive layer 24b and the conductive layer 25b. In particular, it is preferable to use an In—Sn oxide having a polycrystalline structure or a single-crystalline structure. This can improve the crystallinity of the semiconductor film when forming the semiconductor film that contacts the conductive layer 24b and the conductive layer 25b and becomes the semiconductor layer 21. Therefore, it is possible to realize a transistor that combines high field-effect mobility and high reliability.

[0070] The conductive layer 24a is preferably made of a conductive material having a lower resistance than the conductive layer 24b, and particularly preferably contains a metal material. Similarly, the conductive layer 25a is preferably made of a conductive material having a lower resistance than the conductive layer 25b.

[0071] In this example, the conductive layer 23 has a stacked structure of conductive layers 23a and 23b. Since the conductive layer 23 is in contact with the insulating layer 22, the insulating layer 42, and the like, if an insulating film that diffuses oxygen, such as silicon oxide, is used for these layers, the conductive layer 23 may be oxidized due to the influence of heat during processing, resulting in a decrease in conductivity. Therefore, the conductive layer 23a in contact with the insulating layer 22 and the insulating layer 42 is preferably made of a conductive material that is less susceptible to oxidation than the conductive layer 23b. For example, a metal nitride film such as tantalum nitride or titanium nitride is preferably used for the conductive layer 23a. On the other hand, the conductive layer 23b can be made of a conductive material containing a low-resistance metal or alloy. This can improve the reliability of the transistor 10.

[0072] The insulating layer 41 functions as an interlayer insulating layer (spacer) that insulates the conductive layer 24 from the conductive layer 25. Here, the insulating layer 41 is shown to be a stacked film of insulating layers 41a, 41b, and 41c.

[0073] The semiconductor layer 21 is provided in contact with the inner wall of the opening 20a of the insulating layer 41b. It is preferable to use an oxide insulating film for the insulating layer 41b. In particular, it is preferable to use an oxide insulating film that releases oxygen when heated. It is also preferable to have a structure in which the insulating layer 41b is sandwiched between insulating layers 41a and 41c that have a barrier property against oxygen. This makes it possible to confine oxygen contained in the insulating layer 41b in a region surrounded by the insulating layers 41a, 41c, and the semiconductor layer 21. Furthermore, it is possible to prevent oxygen from being released and reduced in the insulating layer 41b during the process. This allows oxygen to be supplied to the semiconductor layer 21 more efficiently.

[0074] For example, the insulating layer 41a and the insulating layer 41c can be made of an insulating film that can be used for the insulating layer 45.

[0075] The portion of the semiconductor layer 21 that is in contact with the insulating layer 41b is a region in which oxygen vacancies are reduced and can be said to be an i-type region. On the other hand, the portion that is not in contact with the insulating layer 41b is preferably an n-type region containing many carriers. That is, the portion of the semiconductor layer 21 that is in contact with the insulating layer 41b can be called a channel formation region, and the region outside that can be called a low-resistance region (also called a source region or a drain region).

[0076] The insulating layer 41b is preferably a film containing as little hydrogen as possible because it is in contact with the semiconductor layer 21. Carriers are generated when oxygen vacancies in the semiconductor layer 21 combine with hydrogen, which may affect the threshold voltage of the transistor 10, for example. Therefore, an insulating film other than an oxide insulating film through which hydrogen is less likely to diffuse may be used as the insulating layer 41b. For example, a single layer of an insulating film having a barrier property against hydrogen and oxygen may be used as the insulating layer 41.

[0077] Because the semiconductor layer 21 and the insulating layer 22 are formed along the inner wall of the opening 20a in the insulating layer 41b, the thickness of this portion may be thin depending on the film formation method. For example, with film formation methods such as sputtering or plasma CVD, films formed on surfaces inclined or perpendicular to the substrate surface tend to be thinner than films formed on surfaces parallel to the substrate surface. On the other hand, with film formation methods such as atomic layer deposition (ALD) or thermal CVD, films of uniform thickness can be formed regardless of the angle of the surface on which they are formed. For example, when the angle of the sidewall of the opening 20a in the insulating layer 41b is 75 degrees or more, 80 degrees or more, or 85 degrees or more, it is preferable to form the semiconductor layer 21 and the insulating layer 22 using the ALD method.

[0078] [Configuration Example 2] The following describes a configuration example in which some components are different from those in Configuration Example 1. Note that the same reference numerals are used for parts that overlap with those in Configuration Example 1, and descriptions thereof may be omitted.

[0079] 3A and 3B are schematic cross-sectional views of a transistor 10a. The transistor 10a differs from the transistor 10a in that it does not have the insulating layer 42, the insulating layer 43, or the conductive layer 31.

[0080] The conductive layer 23 has a portion located over the conductive layer 25 with the insulating layer 22 and the semiconductor layer 21 interposed therebetween, and a portion located over the insulating layer 41 with the insulating layer 22 interposed therebetween. A part of the conductive layer 23 can function as a gate wiring. This structure is preferable because it can simplify the manufacturing process of the transistor and reduce manufacturing costs compared to Structure Example 1.

[0081] 4A is an example of a transistor 10b in which the sidewalls of the opening 20a are tapered. In the transistor 10b, the diameter of the opening 20a at its upper end (opening diameter) is larger than the diameter of the opening at its lower end (opening diameter).

[0082] In this specification and the like, the term "tapered shape" refers to a shape in which at least a part of the side surface of a structure is inclined with respect to the substrate surface or the surface on which the structure is to be formed. For example, it is preferable to have a region in which the angle between the inclined side surface and the surface on which the structure is to be formed (also referred to as the taper angle) is less than 90 degrees.

[0083] By tapering the sidewalls of the opening 20a, the coverage of the semiconductor layer 21, the insulating layer 22, etc. is improved, and the generation of defects such as low-density regions in the film can be suppressed even when a film formation method such as a sputtering method is used. For example, the taper angle can be 45 degrees or more and 90 degrees or less, or 60 degrees or more and less than 90 degrees, or 70 degrees or more and less than 90 degrees. Note that when a film formation method with extremely high coverage such as an ALD method is used, the taper angle may be greater than 90 degrees.

[0084] When the sidewall of opening 20a is tapered, the diameter of opening 20a, which corresponds to the channel width of transistor 10b, increases from the conductive layer 24 side toward conductive layer 25 side. In this case, the magnitude of the current flowing through transistor 10b is limited to the smallest diameter portion. Therefore, the channel width of transistor 10b can be regarded as the perimeter of the smallest diameter portion of opening 20a. Note that the channel width of transistor 10b may also be calculated using the largest diameter portion of opening 20a, the average value of the largest and smallest diameter portions, or the portion of opening 20a where the depth is halfway.

[0085] While Fig. 4A shows an example in which the conductive layer 23b is provided so as to fill the opening 20a, as shown in Fig. 4B, the conductive layer 23b does not have to fill the opening 20a. For example, if the thickness of the conductive layer 23b is sufficiently thinner than the diameter of the opening 20a, the shape shown in Fig. 4B may be obtained. More specifically, if the conductive layer 23b is thinner than the radius of the opening 20a minus the thicknesses of the semiconductor layer 21, the insulating layer 22, and the conductive layer 23a, the configuration shown in Fig. 4B may be obtained.

[0086] [Crystal Structure of Semiconductor Layer] A preferred crystal structure of the semiconductor layer 21 will be described below.

[0087] The semiconductor layer 21 is preferably single-crystalline, polycrystalline, or substantially single-crystalline. Substantially single-crystalline means that there are no grain boundaries across the current path at least in the channel formation region.

[0088] 5A shows an enlarged cross-sectional view of the transistor 10. In the semiconductor layer 21, the channel formation region can be considered to be the region between the upper end of the conductive layer 24 and the lower end of the conductive layer 25. Specifically, the region between the upper end of the conductive layer 24b and the lower end of the conductive layer 25a can be considered to be the channel formation region. Note that, when an insulating oxide is provided between the conductive layer 25a and the semiconductor layer 21, the portion between the upper end of the conductive layer 24b and the lower end of the conductive layer 25b may also be considered to be the channel formation region.

[0089] As an example, it is assumed that the crystal structure of the metal oxide film of the semiconductor layer 21 is a cubic system, which corresponds to the case where an indium oxide film is used.

[0090] 5A, the right side of the figure shows a schematic representation of the crystal orientations of five locations located in the channel formation region of the semiconductor layer 21. Inside the dashed dotted lines, the directions of the crystal axes (a-axis, b-axis, c-axis) and the crystal orientation

[111] in each region are indicated by arrows, and the orientation of the unit cell is shown to the right of the arrows.

[0091] The left side of Fig. 5B shows a cross section perpendicular to the Z direction of a region including a channel formation region. As shown in Fig. 5B, conductive layer 23a, insulating layer 22, and semiconductor layer 21 are provided concentrically around conductive layer 23b. The right side of Fig. 5B also shows schematic crystal orientations at three locations in the semiconductor layer.

[0092] As shown in FIG. 5A , in a cross-sectional view parallel to the Z direction, it is preferable that no crystal grain boundaries are observed in the channel formation region of the semiconductor layer 21, and that the crystal orientation at any position in the channel formation region of the semiconductor layer 21 is consistent. This allows the semiconductor layer 21 to be considered substantially single crystalline. Furthermore, as shown in FIG. 5B , it is preferable that no crystal grain boundaries are observed in the semiconductor layer 21, and that the crystal orientation at any position is consistent. This allows the semiconductor layer 21 to be considered to have a single crystalline structure. The fact that no crystal grain boundaries are observed in the channel formation region in a cross-sectional view can be rephrased as meaning that one crystal grain is observed in the region of the semiconductor layer 21 that contacts the insulating layer 41. Alternatively, it can be rephrased as meaning that the region of the semiconductor layer 21 that contacts the insulating layer 41 has a crystalline structure, and that two or more crystal grains are not observed in that region.

[0093] Furthermore, when indium oxide is used for the semiconductor layer 21, it is preferable that the crystal orientation

[111] or an equivalent crystal orientation be oriented parallel or approximately parallel to a direction perpendicular to the substrate surface or the surface on which it is formed (a direction parallel to the Z direction).

[0094] Furthermore, when a conductive material exhibiting a cubic crystal structure similar to indium oxide is used for the conductive layer 24b, it is preferable that the crystal orientation of the conductive layer 24b in contact with the semiconductor layer 21 coincide with that of the semiconductor layer 21. For example, the crystal of the semiconductor layer 21 can be epitaxially grown from the interface with the conductive layer 24b, thereby aligning the crystal orientations. This may reduce the contact resistance between the semiconductor layer 21 and the conductive layer 24b. For example, when indium oxide is used for the semiconductor layer 21 and an In—Sn oxide having a cubic crystal structure is used for the conductive layer 24b, the crystal of the semiconductor layer 21 can be epitaxially grown, thereby achieving a configuration in which the crystal orientations of the conductive layer 24b and the semiconductor layer 21 coincide. Note that while the conductive layer 24b has been described here, it is also preferable that the crystal orientations coincide in the vicinity of the interface between the conductive layer 24b and the semiconductor layer 21 as well.

[0095] Cross-sectional observation of the transistor 10 and identification of the crystal orientation of any part of the semiconductor layer 21 can be confirmed by cross-sectional images and diffraction images obtained using a scanning transmission electron microscope (STEM). Note that, because STEM analysis requires thinning the sample, only a cross section in one direction can be obtained for one sample. Therefore, when the semiconductor layer 21 has a three-dimensional structure, as in the transistor 10, it is extremely difficult to identify the crystal orientation of all parts of the semiconductor layer 21. Therefore, by analyzing multiple samples fabricated under the same conditions, the accuracy of the analysis can be improved, and it can be confirmed that the semiconductor layer 21 has a single crystal structure or can be considered to have a single crystal structure.

[0096] 5A and 5B, electron beam diffraction images using an STEM device can be used to identify the crystal orientations of multiple regions. In this case, if the same location is irradiated with an electron beam multiple times, it may affect the crystal structure. Therefore, when measuring multiple locations, it is preferable to separate two measurement locations by, for example, 10 nm or more so that the measurement locations do not overlap.

[0097] 6A and 6B show examples having crystallinity different from that described above.

[0098] FIG. 6A shows an example in which no grain boundaries are observed in a cross-sectional view in the Z direction, as described above. On the other hand, when the crystal orientations at multiple positions in the channel formation region are examined, the crystals are oriented so as to be twisted around the Z direction. More specifically, in the channel formation region, the crystals are continuously oriented from the conductive layer 24b side to the conductive layer 25b side without any grain boundaries, with the crystal axes rotating clockwise or counterclockwise when viewed from the Z direction. In this case, specific crystal orientations (here, the

[111] crystal orientation or an equivalent crystal orientation) are consistent. Thus, even in a distorted crystal structure, there are no grain boundaries across the current path (channel length direction), and the crystals are continuous, achieving high field-effect mobility. It is believed that such crystal twists (distortion) are caused by lattice distortion due to lattice defects (atomic defects), stress, etc., propagating in the crystal growth direction during crystal growth.

[0099] Although an example in which the crystal twists in one direction from the conductive layer 24b side to the conductive layer 25b side has been shown here, it is sufficient that the crystal is continuously oriented, and for example, there may be a mixture of portions in which the crystal axis twists clockwise and portions in which it twists counterclockwise. Also, although the case in which the rotation axis coincides with the Z direction has been shown here, it is sufficient that the crystal rotates (twists) around a specific crystal orientation, and the rotation axis of the crystal does not necessarily have to coincide with the Z direction (height direction).

[0100] Furthermore, as shown in FIG. 6B, in a cross section perpendicular to the Z direction, similar to FIG. 5B, it is preferable that no grain boundaries are observed and that the crystal orientations at any position are consistent.

[0101] [Regarding Components] <Substrate> The substrate on which a transistor is formed may be, for example, an insulating substrate, a semiconductor substrate, or a conductive substrate. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (e.g., yttria-stabilized zirconia substrates), and resin substrates. Examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, or compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, gallium oxide, and gallium nitride. Examples of semiconductor substrates include those having an insulating region within the aforementioned semiconductor substrate, such as an SOI (Silicon-On-Insulator) substrate. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Alternatively, substrates containing metal nitrides or metal oxides may also be used. Further, there are substrates in which a conductive layer or a semiconductor layer is provided on an insulating substrate, substrates in which a conductive layer or an insulating layer is provided on a semiconductor substrate, and substrates in which a semiconductor layer or an insulating layer is provided on a conductive substrate. Alternatively, any of these substrates may be provided with elements. The elements provided on the substrate include capacitor elements, resistor elements, switch elements (including transistors), light-emitting elements, memory elements, and the like.

[0102] <Semiconductor Layer> The semiconductor layer 21 preferably contains a metal oxide (oxide semiconductor).

[0103] The semiconductor layer 21 is preferably made of indium oxide.

[0104] Examples of metal oxides that can be used for the semiconductor layer 21 include Ga oxide and Zn oxide. The metal oxide preferably contains at least In or Zn. The metal oxide preferably contains two or three elements selected from In, element M, and Zn. The element M is a metal element or semimetal element with a high bond energy with oxygen, such as a metal element or semimetal element with a bond energy with oxygen higher than that of indium. Specific examples of the element M include Al, Ga, Sn, Y, Ti, V, Cr, Mn, Fe, Co, Ni, Zr, Mo, Hf, Ta, W, La, Ce, Nd, Mg, Ca, Sr, Ba, B, Si, Ge, and Sb. The element M contained in the metal oxide is preferably one or more of the above elements, and is particularly preferably one or more selected from Al, Ga, Y, and Sn, with Ga being more preferred. Hereinafter, a metal oxide having In, M, and Zn may be referred to as an In-M-Zn oxide. In this specification and the like, metal elements and metalloid elements may be collectively referred to as "metal elements," and the "metal elements" described in this specification and the like may include metalloid elements.

[0105] When the metal oxide is an In-M-Zn oxide, the atomic ratio of In in the In-M-Zn oxide is preferably equal to or greater than the atomic ratio of M. For example, the atomic ratios of metal elements in such an In-M-Zn oxide may be In:M:Zn = 1:1:1, In:M:Zn = 1:1:1.2, In:M:Zn = 2:1:3, In:M:Zn = 3:1:2, In:M:Zn = 4:2:3, In:M:Zn = 4:2:4.1, In:M:Zn = 5:1:3, In:M:Zn = 5:1:6, In:M:Zn = 5:1:7, In:M:Zn = 5:1:8, In:M:Zn = 6:1:6, In:M:Zn = 5:2:5, or compositions in the vicinity thereof. Note that the term "composition in the vicinity" refers to a range of ±30% of the desired atomic ratio. By increasing the atomic ratio of indium in the metal oxide, the on-state current, field-effect mobility, and the like of a transistor can be increased.

[0106] Furthermore, the atomic ratio of In in the In-M-Zn oxide may be less than the atomic ratio of M. For example, the atomic ratio of metal elements in such an In-M-Zn oxide may be In:M:Zn=1:3:2, In:M:Zn=1:3:3, In:M:Zn=1:3:4, or a composition close to these. By increasing the atomic ratio of M in the metal oxide, the generation of oxygen vacancies can be suppressed.

[0107] The semiconductor layer 21 can be made of, for example, In—Zn oxide, In—Ga oxide, In—Sn oxide, In—Ti oxide, In—Ga—Al oxide, In—Ga—Sn oxide, In—Ga—Zn oxide, In—Sn—Zn oxide, In—Al—Zn oxide, In—Ti—Zn oxide, In—Ga—Sn—Zn oxide, or In—Ga—Al—Zn oxide. Ga—Zn oxide may also be used. On the other hand, a material containing Zn is preferred because it is easy to increase crystallinity.

[0108] Note that the metal oxide may contain one or more metal elements with higher period numbers in the periodic table instead of or in addition to indium. The greater the overlap of the orbitals of metal elements, the greater the carrier conduction in the metal oxide tends to be. Therefore, including a metal element with a higher period number may improve the field-effect mobility of a transistor. Examples of metal elements with higher period numbers include metal elements belonging to the fifth period and the sixth period. Specific examples of such metal elements include Y, Zr, Ag, Cd, Sn, Sb, Ba, Pb, Bi, La, Ce, Pr, Nd, Pm, Sm, and Eu. Note that La, Ce, Pr, Nd, Pm, Sm, and Eu are called light rare earth elements.

[0109] The metal oxide may also contain one or more nonmetallic elements, which may increase the field-effect mobility of the transistor. Examples of nonmetallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.

[0110] The metal oxide can be preferably formed by sputtering or atomic layer deposition (ALD). In particular, it is preferable to form the metal oxide film by the ALD method, which has excellent coating properties. When forming the metal oxide by the sputtering method, the composition of the metal oxide film may differ from that of the target. In particular, the zinc content in the metal oxide film may decrease to about 50% of that of the target.

[0111] In this specification, the content of a metal element in a metal oxide refers to the ratio of the number of atoms of that element to the total number of atoms of the metal element contained in the metal oxide. For example, if a metal oxide contains metal elements X, Y, and Z, and the number of atoms of each of metal elements X, Y, and Z contained in the metal oxide is A, then Ｘ , A Ｙ , A Ｚ When the content of the metal element X is Ｘ / (A Ｘ +A Ｙ +A Ｚ ) In addition, the ratio of the number of atoms of the metal element X, the metal element Y, and the metal element Z in the metal oxide (atomic number ratio) can be expressed as follows: Ｘ : B Ｙ : B Ｚ When the content of the metal element X is expressed as B Ｘ / (B Ｘ +B Ｙ +B Ｚ ) can be shown as

[0112] For example, in the case of a metal oxide containing In, a transistor with a large on-current can be realized by increasing the In content.

[0113] By using a metal oxide that does not contain Ga or has a low Ga content in the semiconductor layer 21, a transistor with high reliability against positive bias application can be obtained. That is, a transistor with a small amount of threshold voltage fluctuation in a PBTS (Positive Bias Temperature Stress) test can be obtained. Furthermore, when using a metal oxide that contains Ga, it is preferable to make the Ga content lower than the In content. This makes it possible to realize a transistor with high mobility and high reliability.

[0114] On the other hand, by increasing the Ga content, a transistor with high reliability against light can be obtained. That is, a transistor with a small amount of variation in threshold voltage in a Negative Bias Temperature Illumination Stress (NBTIS) test can be obtained. Specifically, a metal oxide in which the atomic ratio of Ga is equal to or greater than the atomic ratio of In has a larger band gap, and the amount of variation in threshold voltage of the transistor in the NBTIS test can be reduced.

[0115] Furthermore, by increasing the zinc content, the metal oxide becomes highly crystalline, which can suppress the diffusion of impurities in the metal oxide, thereby suppressing fluctuations in the electrical characteristics of the transistor and improving its reliability.

[0116] The semiconductor layer 21 may have a stacked structure including two or more metal oxide layers. The two or more metal oxide layers included in the semiconductor layer 21 may have the same or substantially the same composition. By using a stacked structure of metal oxide layers with the same composition, for example, the same sputtering target can be used for formation, thereby reducing manufacturing costs. A stacked structure in which two or more oxide semiconductor layers with different compositions are stacked may also be used. Furthermore, by using the ALD method, it is possible to form a metal oxide layer whose composition varies continuously in the thickness direction. This not only broadens the range of design options compared to using a film with a fixed composition, but also prevents the generation of interface states between two layers with different compositions, thereby improving electrical characteristics and reliability. Furthermore, a metal oxide layer having a stacked structure may be formed using both the sputtering method and the ALD method.

[0117] When the semiconductor layer 21 has a two-layer structure, it is preferable to use a material with higher mobility (higher conductivity) in the second layer, i.e., the side closer to the gate electrode, than in the first layer. This allows for a normally-off transistor with a large on-current. This makes it possible to achieve both low power consumption and high performance. Alternatively, a material with higher mobility than in the second layer may be used in the first layer, i.e., the side in contact with the source electrode and drain electrode. This reduces the contact resistance between the semiconductor layer 21 and the source electrode or drain electrode, thereby reducing parasitic resistance and enabling a transistor with a large on-current.

[0118] Furthermore, when the semiconductor layer 21 has a three-layer structure, it is preferable to use a material for the second layer that has a higher mobility than the first and third layers, thereby realizing a transistor with a high on-current and high reliability.

[0119] The difference in the mobility and conductivity described above can be expressed, for example, by the indium content. In addition, whether or not an element other than indium that contributes to improving conductivity is included, and the content of that element, also affect the mobility and conductivity. Examples of high-mobility materials include In:Ga:Zn = 4:2:3, In:Zn = 1:1, In:Zn = 2:1, In:Zn = 4:1, In:Sn:Zn = 40:X:10 (where X is 0.1 or more and 5 or less, typically X = 1), or materials with compositions similar to these. On the other hand, materials with lower mobility or conductivity than the above-mentioned materials include In:Ga:Zn = 1:3:2, In:Ga:Zn = 1:3:4, In:Ga:Zn = 2:2:1, In:Ga:Zn = 1:1:1, In:Ga:Zn = 1:1:2, or materials with compositions similar to these.

[0120] It is preferable to use a crystalline metal oxide layer for the semiconductor layer 21. For example, a metal oxide layer having a single crystal structure, a CAAC structure, a polycrystalline structure, a nano-crystalline (nc) structure, or the like can be used. By using a crystalline metal oxide layer for the semiconductor layer 21, the density of defect states in the semiconductor layer 21 can be reduced, and a highly reliable semiconductor device can be realized.

[0121] The higher the crystallinity of the metal oxide layer used in the semiconductor layer 21, the more the density of defect states in the semiconductor layer 21 can be reduced. On the other hand, by using a metal oxide layer with low crystallinity, a transistor capable of passing a large current can be realized.

[0122] In particular, it is preferable to use indium oxide for the semiconductor layer 21. In particular, it is preferable to use a single-crystal indium oxide film. Note that it is preferable to use a crystalline film for the semiconductor layer 21, and it is particularly preferable to use indium oxide with a single-crystal structure. However, indium oxide with a polycrystalline structure or a microcrystalline structure can also be used. By using indium oxide with a single-crystal structure, carrier scattering at crystal grain boundaries can be suppressed, and a transistor with high field-effect mobility can be realized. Furthermore, a highly reliable transistor can be realized. When indium oxide with a polycrystalline structure is used, it is preferable that crystal grain boundaries are not observed at least in the channel formation region (the region overlapping with the conductive layer 23). As a result, even indium oxide with a polycrystalline structure can achieve the same effects as indium oxide with a single-crystal structure.

[0123] The thickness of the semiconductor layer 21 is preferably 2 nm to 50 nm, more preferably 2.5 nm to 30 nm, more preferably 2.5 nm to 20 nm, more preferably 5 nm to 20 nm, and even more preferably 5 nm to 10 nm. By setting the thickness of the semiconductor layer 21 within the above range, the crystallinity of the semiconductor layer 21 can be improved.

[0124] Among oxide semiconductors with high crystallinity, indium oxide is a film through which one or both of hydrogen and oxygen move more easily than, for example, an IGZO (In—Ga—Zn—O-based oxide) film. Therefore, indium oxide is a film through which one or both of hydrogen and oxygen are more easily supplied and discharged than, for example, an IGZO film. This means that excess oxygen or excess hydrogen, which can become carriers or fixed charges, is less likely to accumulate in the semiconductor layer 21, thereby making it possible to provide a transistor with good electrical characteristics and reliability.

[0125] The semiconductor layer 21 preferably has a reduced concentration of elements that reduce crystallinity. For example, the concentration of elements such as boron and aluminum is preferably 1 atomic % or less, more preferably 0.1 atomic % or less, and even more preferably 0.01 atomic % (100 ppm) or less.

[0126] Furthermore, when indium oxide is used for the semiconductor layer 21, unintentionally mixed gallium has a tendency to easily bond with excess oxygen atoms, which may result in a large amount of fluctuation in threshold voltage in a PBTS (Positive Bias Temperature Stress) test. Therefore, when indium oxide is used for the semiconductor layer 21, the gallium concentration in the semiconductor layer 21 is preferably 1 atomic % or less, more preferably 0.1 atomic % or less, and even more preferably 0.01 atomic % (100 ppm) or less.

[0127] A transistor using an oxide semiconductor (hereinafter referred to as an OS transistor) has significantly higher field-effect mobility than a transistor using amorphous silicon. Furthermore, an OS transistor has significantly lower source-drain leakage current in an off state (hereinafter also referred to as an off-state current) and can hold charge accumulated in a capacitor connected in series with the transistor for a long period of time. Furthermore, the use of an OS transistor can reduce the power consumption of a semiconductor device.

[0128] The semiconductor device according to one embodiment of the present invention can be applied to, for example, a processor, a memory device, or various ICs. The transistor according to one embodiment of the present invention is capable of passing a large current and has an extremely low off-state current, and therefore, high-speed operation of a circuit and low power consumption can be achieved at the same time.

[0129] A semiconductor device according to one embodiment of the present invention can also be applied to a display device, for example. To increase the emission luminance of a light-emitting device included in a pixel circuit of a display device, it is necessary to increase the amount of current flowing through the light-emitting device. To achieve this, it is necessary to increase the source-drain voltage of a driving transistor included in the pixel circuit. Since an OS transistor has a higher withstand voltage between the source and drain than a transistor using silicon (hereinafter referred to as a Si transistor), a high voltage can be applied between the source and drain of the OS transistor. Therefore, by using an OS transistor as the driving transistor included in the pixel circuit, it is possible to increase the amount of current flowing through the light-emitting device and increase the emission luminance of the light-emitting device.

[0130] When a transistor operates in the saturation region, an OS transistor can reduce the change in source-drain current with respect to a change in gate-source voltage compared to a Si transistor. Therefore, by using an OS transistor as a driving transistor included in a pixel circuit, the amount of current flowing through the light-emitting device can be precisely controlled. This allows for a larger number of gray levels in the pixel circuit. Furthermore, even if the electrical characteristics (e.g., resistance) of the light-emitting device fluctuate or vary, a stable current can flow.

[0131] As described above, by using an OS transistor for a driving transistor included in a pixel circuit, it is possible to achieve "suppression of black floating," "increase in light emission luminance," "multiple gradations," "suppression of the influence of manufacturing variations in light-emitting devices," and the like.

[0132] OS transistors exhibit smaller variations in electrical characteristics due to radiation exposure than Si transistors, i.e., have high radiation resistance, and therefore can be suitably used in environments where radiation may be incident. It can also be said that OS transistors have high reliability against radiation. For example, OS transistors can be suitably used in pixel circuits of X-ray flat panel detectors. Furthermore, OS transistors can be suitably used in semiconductor devices used in outer space. Examples of radiation include electromagnetic radiation (e.g., X-rays and gamma rays) and particle radiation (e.g., alpha rays, beta rays, proton rays, and neutron rays).

[0133] The semiconductor material that can be used for the semiconductor layer 21 is not limited to oxide semiconductors. For example, semiconductors made of simple elements or compound semiconductors can be used. Examples of semiconductors made of simple elements include silicon (including single crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon) and germanium. Examples of compound semiconductors include gallium arsenide and silicon germanium. Examples of compound semiconductors include organic semiconductors, nitride semiconductors, and oxide semiconductors. These semiconductor materials may contain impurities as dopants.

[0134] Alternatively, the semiconductor layer 21 may have a layered material that functions as a semiconductor. A layered material is a general term for a group of materials that have a layered crystal structure. A layered crystal structure is a structure in which layers formed by covalent or ionic bonds are stacked via bonds weaker than covalent or ionic bonds, such as van der Waals bonds. A layered material has high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity. By using a material that functions as a semiconductor and has high two-dimensional electrical conductivity in the channel formation region, a transistor with a large on-current can be provided.

[0135] Examples of the layered material include graphene, silicene, and chalcogenides. Chalcogenides are compounds containing chalcogen (an element belonging to Group 16). Examples of chalcogenides include transition metal chalcogenides and Group 13 chalcogenides. Specific examples of transition metal chalcogenides that can be used as semiconductor layers of transistors include molybdenum sulfide (typically MoS ２ ), molybdenum selenide (typically MoSe ２ ), molybdenum telluride (typically MoTe ２ ), tungsten sulfide (typically WS ２ ), tungsten selenide (typically WSe ２ ), tungsten tellurium (typically WTe ２ ), hafnium sulfide (typically HfS ２ ), hafnium selenide (typically HfSe ２ ), zirconium sulfide (typically ZrS ２ ), zirconium selenide (typically ZrSe ２ ) etc.

[0136] The crystallinity of the semiconductor material used for the semiconductor layer 21 is not particularly limited, and any of an amorphous semiconductor, a single-crystal semiconductor, and a semiconductor having crystallinity other than single crystal (a polycrystalline semiconductor, a microcrystalline semiconductor, or a semiconductor having a crystalline region in part) may be used. Use of a crystalline semiconductor is preferable because it can suppress deterioration of transistor characteristics.

[0137] <Gate Insulating Layer> The insulating layer 22 functions as a gate insulating layer of a transistor. When an oxide semiconductor is used for the semiconductor layer 21, it is preferable to use an oxide insulating film for at least the film of the insulating layer 22 that is in contact with the semiconductor layer 21. For example, one or more of silicon oxide, silicon oxynitride, aluminum oxide, aluminum oxynitride, hafnium oxide, hafnium oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, and Ga—Zn oxide can be used. Alternatively, a nitride insulating film such as silicon nitride, silicon nitride oxide, aluminum nitride, or aluminum nitride oxide can also be used for the insulating layer 22. Furthermore, the insulating layer 22 may have a stacked structure, for example, a stacked structure including one or more oxide insulating films and one or more nitride insulating films.

[0138] Furthermore, the insulating layer 22 is preferably formed by laminating insulating materials having a high dielectric constant (high-k material), and preferably by using a laminate structure of a high-k material and a material having a higher dielectric strength than the high-k material. For example, the insulating layer 22 can be formed by laminating an insulating film (also referred to as ZAZ) in which zirconium oxide, aluminum oxide, and zirconium oxide are stacked in this order. Alternatively, the insulating layer 22 can be formed by laminating an insulating film (also referred to as ZAZA) in which zirconium oxide, aluminum oxide, zirconium oxide, and aluminum oxide are stacked in this order. Alternatively, the insulating film can be formed by laminating hafnium zirconium oxide, aluminum oxide, hafnium zirconium oxide, and aluminum oxide in this order. By using a laminate of an insulator with a relatively high dielectric strength, such as aluminum oxide, the dielectric strength is improved and electrostatic breakdown can be suppressed.

[0139] Furthermore, a material exhibiting ferroelectricity may be used for the insulating layer 22. Examples of the material exhibiting ferroelectricity include hafnium oxide, zirconium oxide, and HfZrO. Ｘ (X is a real number greater than 0).

[0140] When the insulating layer 22 has a two-layer structure, it is preferable to use an insulating film having a function of capturing or fixing hydrogen as the film in contact with the semiconductor layer 21, and to use an insulating film having a barrier property against hydrogen as the film located on the conductive layer 23 side that functions as the gate electrode. This makes it possible to suppress diffusion of hydrogen from the conductive layer 23 side to the semiconductor layer 21, thereby realizing a highly reliable transistor.

[0141] As an insulating film that captures or fixes hydrogen, it is preferable to use a hafnium oxide film, a hafnium silicate film, an aluminum oxide film, etc. Furthermore, as an insulating film having a barrier property against hydrogen, it is preferable to use a silicon nitride film, a silicon nitride oxide film, an aluminum oxide film, a magnesium oxide film, a hafnium oxide film, a gallium oxide film, etc.

[0142] Alternatively, an insulating film that releases oxygen when heated may be used as a film in contact with the semiconductor layer 21, and an insulating film having a barrier property against hydrogen may be used as a film located on the conductive layer 23 side. Alternatively, an insulating film that releases oxygen when heated may be used as a film in contact with the semiconductor layer 21, and an insulating film that has a function of capturing or fixing hydrogen may be used as a film located on the conductive layer 23 side.

[0143] When the insulating layer 22 has a three-layer structure, it is preferable to use an insulating film made of a material through which oxygen easily diffuses as the film in contact with the semiconductor layer 21, an insulating film having barrier properties against hydrogen and oxygen as the film located on the conductive layer 23 side, and an insulating film having the function of capturing or fixing hydrogen as the film located between them. Silicon oxide or silicon oxynitride can be used as the material through which oxygen easily diffuses. With this structure, oxygen can be supplied to the semiconductor layer 21 from the film in contact with the semiconductor layer 21. Furthermore, the film located on the conductive layer 23 side prevents oxygen from diffusing toward the conductive layer 23, thereby suppressing oxidation of the conductive layer 23.

[0144] As the insulating film having a barrier property against oxygen, it is preferable to use an aluminum oxide film, a silicon nitride film, a hafnium oxide film, a hafnium silicate film, etc. As the insulating film having a barrier property against oxygen and hydrogen, it is preferable to use an aluminum oxide film, a silicon nitride film, a hafnium oxide film, etc.

[0145] When the insulating layer 22 has a four-layer structure, it is preferable to use an insulating film having a barrier property against oxygen as the film in contact with the semiconductor layer 21, followed by an insulating film made of a material into which oxygen easily diffuses, an insulating film having a function of capturing or fixing hydrogen, and an insulating film having a barrier property against hydrogen and oxygen, in order from the side closer to the semiconductor layer 21. That is, in addition to the above-mentioned three-layer structure, a configuration can be obtained in which a film in contact with the semiconductor layer 21 is added. By using an insulating film having a barrier property against oxygen as the film in contact with the semiconductor layer 21, oxygen can be prevented from being desorbed from the semiconductor layer 21. In this case, it is preferable to use an aluminum oxide film as the film in contact with the semiconductor layer 21. Aluminum oxide not only has a barrier property against oxygen but also has a function of capturing or fixing hydrogen, and therefore has the effect of preventing hydrogen from diffusing into the semiconductor layer 21.

[0146] When the insulating layer 22 has a stacked structure, each insulating film is preferably a thin film. For example, the thickness of the insulating layer 22 is 1 nm to 20 nm, preferably 3 nm to 10 nm, to reduce the subthreshold swing (also referred to as the S value) of the transistor. The thickness of each insulating film is preferably 0.1 nm to 10 nm, more preferably 0.1 nm to 5 nm, more preferably 0.5 nm to 5 nm, still more preferably 1 nm to less than 5 nm, and even more preferably 1 nm to 3 nm.

[0147] As a specific example, it is preferable to use a four-layer structure in which an aluminum oxide film, a silicon oxide film, a hafnium oxide film, and a silicon nitride film are stacked in this order from the semiconductor layer 21 side, and to set the thicknesses of these films to 1 nm, 2 nm, 2 nm, and 1 nm from the semiconductor layer 21 side.

[0148] <Conductive Layer> The conductive layer 24 and the conductive layer 25 are in contact with the semiconductor layer 21. When an oxide semiconductor is used as the semiconductor layer 21, if an easily oxidized metal such as aluminum is used in the portion of the conductive layer 24 or the conductive layer 25 in contact with the semiconductor layer 21, an insulating oxide (e.g., aluminum oxide) may be formed between the conductive layer 24 or the conductive layer 25 and the semiconductor layer 21, preventing electrical conduction therebetween. Therefore, it is preferable to use a conductive material that is resistant to oxidation, a conductive material that maintains low electrical resistance even when oxidized, or a conductive oxide material for at least the portion of the conductive layer 24 and the conductive layer 25 in contact with the semiconductor layer 21.

[0149] For the conductive layer 24 and the conductive layer 25 in contact with the semiconductor layer 21, it is preferable to use, for example, titanium, tantalum nitride, titanium nitride, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, etc. These are preferable because they are conductive materials that are difficult to oxidize or materials that maintain conductivity even when oxidized.

[0150] Alternatively, conductive oxides such as indium oxide, zinc oxide, In—Sn oxide, In—Zn oxide, In—W oxide, In—W—Zn oxide, In—Ti oxide, In—Ti—Sn oxide, In—Sn—Si oxide, and Ga—Zn oxide can be used. Conductive oxides containing indium are particularly preferred because of their high conductivity. Alternatively, oxide materials such as In—Ga—Zn oxide that can be used for the semiconductor layer 21 can also be used as a conductive layer by increasing the carrier concentration.

[0151] Furthermore, a low-resistance conductive material that can be used for the conductive layer 23 described later may be used for the conductive layer 24 and the conductive layer 25. In particular, the conductive layer 24 and the conductive layer 25 preferably have a stacked structure of a layer containing the above-mentioned conductive material that is resistant to oxidation, a conductive material that maintains low electrical resistance even when oxidized, or an oxide conductive material, and a layer containing a low-resistance conductive material.

[0152] A low-resistance conductive material is preferably used for the conductive layer 23 and the conductive layer 31. For example, a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, cobalt, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing such a metal element is preferably used. Nitrides of the above metals or alloys, or oxides of the above metals or alloys may also be used. For example, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc., are preferably used. Semiconductors with high electrical conductivity, such as polycrystalline silicon containing impurity elements such as phosphorus, or silicides such as nickel silicide may also be used.

[0153] The conductive layers 23 and 31 may be made of the same nitrides and oxides as those used for the conductive layer 24 .

[0154] <Insulating Layer> The insulating layer 41 and the insulating layer 42 can be used as an interlayer insulating film. For example, they are preferably formed by a film formation method such as a sputtering method or a plasma CVD method. In particular, when a sputtering method is used, hydrogen gas is not used as a film formation gas, and therefore a film with an extremely low hydrogen content can be obtained. Therefore, the supply of hydrogen to the semiconductor layer 21 can be suppressed, and the electrical characteristics of the transistor 10 can be stabilized.

[0155] The insulating layers 41 and 42 preferably have a low dielectric constant. By using a material with a low dielectric constant as the interlayer insulating film, the parasitic capacitance generated between wirings can be reduced. For example, it is preferable to have one or more of silicon oxide, silicon oxynitride, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, and silicon oxide having vacancies. Silicon oxide and silicon oxynitride are preferable because they are thermally stable.

[0156] Since the insulating layer 41 and the insulating layer 43 function as interlayer insulating layers, it is preferable to use a film formation method that allows film formation at a high film formation rate compared to other insulating layers. For example, the insulating layer 41 or the insulating layer 42 may be formed using TEOS (Tetra-Ethyl-Ortho-Silicate, chemical formula: Si(OC ２ H ５ ) ４ Alternatively, a silicon oxide film formed by plasma CVD using a silicon dioxide film containing SiO 2 may be used. This can improve productivity.

[0157] The insulating layer 11, which functions as a base insulating layer, also functions as an interlayer insulating layer. The insulating layer 11 can be made of the same insulating material as can be used for the insulating layer 41 or the like.

[0158] This concludes the description of the components.

[0159] [Manufacturing Method Example] An example of a manufacturing method of a transistor of one embodiment of the present invention will be described below, taking the transistor 10a described in Structure Example 2 as an example.

[0160] Thin films (insulating films, semiconductor films, conductive films, etc.) constituting a semiconductor device can be formed by a sputtering method, a chemical vapor deposition method, a vacuum evaporation method, a pulsed laser deposition (PLD) method, an ALD method, or the like.

[0161] Furthermore, thin films (insulating films, semiconductor films, conductive films, etc.) constituting the semiconductor device can be formed by methods such as spin coating, dipping, spray coating, inkjet, dispensing, screen printing, offset printing, doctor knife, slit coating, roll coating, curtain coating, and knife coating.

[0162] Sputtering methods include RF sputtering, which uses a high-frequency power supply as the sputtering power source, DC sputtering, which uses a direct current power supply, and pulsed DC sputtering, which changes the voltage applied to the electrode in a pulsed manner. RF sputtering is mainly used to deposit insulating films, while DC sputtering is mainly used to deposit metal conductive films. Pulsed DC sputtering is mainly used to deposit films of compounds such as oxides, nitrides, and carbides using reactive sputtering.

[0163] CVD methods can be classified into plasma-enhanced chemical vapor deposition (PECVD), which uses plasma, thermal CVD (TCVD), which uses heat, and photo-CVD (photo-CVD), which uses light. CVD methods can also be further classified into metal CVD (MCVD) and metal organic CVD (MOCVD), depending on the source gas used.

[0164] The plasma CVD method can produce high-quality films at relatively low temperatures. Furthermore, since the thermal CVD method does not use plasma, it is possible to reduce plasma damage to the workpiece. Furthermore, since the thermal CVD method does not cause plasma damage during film formation, it can produce films with fewer defects.

[0165] As the ALD method, a thermal ALD method in which a reaction between a precursor and a reactant is carried out using only thermal energy, a PEALD method in which a plasma-excited reactant is used, or the like can be used.

[0166] Unlike sputtering, CVD and ALD are film formation methods that are less affected by the shape of the workpiece and have good step coverage. In particular, ALD has excellent step coverage and excellent thickness uniformity, making it suitable for coating the surface of an opening with a high aspect ratio. However, because ALD has a relatively slow film formation rate, it may be preferable to use it in combination with other film formation methods, such as CVD, which have a faster film formation rate.

[0167] In the CVD method, a film of any composition can be formed by adjusting the flow rate ratio of the source gases. For example, in the CVD method, a film with a continuously changing composition can be formed by changing the flow rate ratio of the source gases while forming the film. When forming a film while changing the flow rate ratio of the source gases, the time required for film formation can be shortened compared to when forming a film using multiple film formation chambers because no time is required for transportation or pressure adjustment. Therefore, the productivity of semiconductor devices can be increased in some cases.

[0168] In the ALD method, a film of any composition can be formed by simultaneously introducing multiple different precursors. Alternatively, when multiple different precursors are introduced, a film of any composition can be formed by controlling the number of cycles of each precursor. Furthermore, as with the CVD method, a film with a continuously changing composition can be formed.

[0169] The thin film constituting the semiconductor device can be processed using a photolithography method or the like. Alternatively, the thin film may be processed using a nanoimprint method, a sandblasting method, a lift-off method or the like. Alternatively, the island-shaped thin film may be directly formed by a film formation method using a shielding mask such as a metal mask.

[0170] There are two typical photolithography methods: one is to form a resist mask on the thin film to be processed, process the thin film by etching or the like, and then remove the resist mask; the other is to form a photosensitive thin film, and then process the thin film into the desired shape by exposure and development.

[0171] In photolithography, the light used for exposure can be, for example, i-line (wavelength 365 nm), g-line (wavelength 436 nm), h-line (wavelength 405 nm), or a mixture of these. Other light sources that can be used include ultraviolet light, KrF laser light, ArF laser light, etc. Exposure can also be performed by immersion exposure technology. Extreme ultraviolet (EUV) light or X-rays can also be used as the light used for exposure. An electron beam can also be used instead of light used for exposure. Extreme ultraviolet light, X-rays, or an electron beam are preferred because they enable extremely fine processing. When exposure is performed by scanning a beam such as an electron beam, a photomask is not required.

[0172] Thin film etching can be performed using methods such as dry etching, wet etching, and sandblasting. Dry etching can be performed isotropically or anisotropically by controlling the etching conditions. Wet etching can be performed isotropically.

[0173] 7A to 10B are schematic cross-sectional views corresponding to the steps in the example of the fabrication method described below.

[0174] First, a substrate (not shown) is prepared, and an insulating layer 11 is formed on the substrate.

[0175] The substrate may be a substrate having heat resistance sufficient to withstand at least a subsequent heat treatment. When an insulating substrate is used, a glass substrate, a quartz substrate, a sapphire substrate, a ceramic substrate, an organic resin substrate, or the like may be used. Alternatively, a semiconductor substrate such as a single-crystal semiconductor substrate made of silicon or silicon carbide, a polycrystalline semiconductor substrate, a compound semiconductor substrate such as silicon germanium or gallium nitride, or an SOI substrate may be used.

[0176] An inorganic insulating film such as a silicon oxide film or a silicon oxynitride film can be used as the insulating layer 11. The insulating layer 11 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. If the surface on which the insulating layer 11 is to be formed is not flat, a planarization process may be performed after the insulating layer 11 is formed so that the upper surface of the insulating layer 11 becomes flat.

[0177] Subsequently, an insulating layer 45 is formed on the insulating layer 11. The insulating layer 45 can be formed by a film formation method such as a sputtering method, an ALD method, or a CVD method.

[0178] Next, a laminated film of a conductive film that will become conductive layer 24a and a conductive film that will become conductive layer 24b is formed on insulating layer 45, and then unnecessary portions of the laminated film are removed by etching to form conductive layer 24a and conductive layer 24b (Figure 7B).

[0179] The conductive films used for the conductive layers 24a and 24b can be formed independently by a film formation method such as a sputtering method, an ALD method, or a CVD method.

[0180] Next, insulating layers 41a and 41b are stacked to cover the insulating layer 45, the conductive layers 24a, and the conductive layers 24b. The top surface of the insulating layer 41b is then planarized. For the planarization process, methods such as CMP (Chemical Mechanical Polishing) and dry etching can be used. Then, an insulating layer 41c is stacked on the insulating layer 41b ( FIG. 7C ).

[0181] The insulating layers 41a, 41b, and 41c can be formed by a film formation method such as sputtering, CVD, MBE, PLD, or ALD. It is preferable that the insulating layers 41a, 41c, and 41b be made of insulating films having different compositions or constituent elements. Furthermore, because the thicknesses of the insulating layers 41a, 41b, and 41c affect the channel length of the transistor, it is important to prevent variations in the thicknesses of the insulating layers 41a, 41b, and 41c.

[0182] After the insulating layer 41b is formed or after planarization treatment, treatment for supplying oxygen to the insulating layer 41b may be performed. This can increase the amount of oxygen in the insulating layer 41b that can be supplied to the semiconductor layer 21. Furthermore, after the treatment for supplying oxygen, the top surface of the insulating layer 41b can be covered with an insulating layer 41c that has a barrier property against oxygen, thereby preventing desorption of the supplied oxygen.

[0183] Examples of the treatment for supplying oxygen include heat treatment in an oxygen-containing atmosphere and plasma treatment (including microwave plasma) in an oxygen-containing atmosphere. Alternatively, oxygen may be supplied to the insulating layer by forming an oxide film (preferably a metal oxide film) in an oxygen-containing atmosphere by sputtering. The formed oxide film may be removed immediately or may be left as it is. Note that the oxygen-containing atmosphere may be oxygen gas (O ２ ) as well as ozone (O ３ ), nitrous oxide (N ２ The atmosphere may include a gas containing an oxygen-containing compound such as oxygen (O).

[0184] The insulating layer 41b is preferably an oxide film containing a large amount of oxygen to such an extent that oxygen is released by heating and containing a small amount of hydrogen. The insulating layer 41b can be formed by a film formation method such as a PECVD method, a sputtering method, or an ALD method. In particular, the sputtering method does not require the use of a gas containing hydrogen in the film formation gas and can form the insulating layer 41b using a gas containing oxygen. Therefore, the insulating layer 41b can be formed with an extremely small amount of hydrogen and containing excess oxygen.

[0185] Next, a conductive film 25af that will become the conductive layer 25a and a conductive film 25bf that will become the conductive layer 25b are formed in this order on the insulating layer 41c (FIG. 7D). The conductive films 25af and 25bf can be formed independently by a film formation method such as a sputtering method, an ALD method, or a CVD method.

[0186] Subsequently, a resist mask is formed on the conductive film 25bf, and then an opening 20a reaching the conductive layer 24b is formed by etching in the conductive film 25bf, the conductive film 25af, the insulating layer 41c, the insulating layer 41b, and the insulating layer 41a (FIG. 8A).

[0187] At this time, by removing a portion of the conductive layer 24b by etching, a recess that overlaps with the opening 20a can be formed in the conductive layer 24b as shown in FIG. 8A.

[0188] The conductive film 25bf, the conductive film 25af, the insulating layer 41c, the insulating layer 41b, and the insulating layer 41a can be etched by dry etching to form the fine openings 20a. However, this is not limiting, and wet etching and dry etching may be combined, or processing may be performed by wet etching. Furthermore, after dry etching, dry cleaning using plasma or wet cleaning using a chemical solution (including acid or alkali) or water (including carbonated water) may be performed.

[0189] When forming the opening 20a, the conductive film 25bf may be used as a hard mask. At this time, the opening is first formed in the conductive film 25bf using a resist mask. Then, the insulating layer 41c, the insulating layer 41b, and the insulating layer 41a are sequentially etched using the conductive film 25bf as a mask, thereby forming the opening 20a. Note that the resist mask may be removed after etching the conductive film 25bf, or may be removed during etching of the insulating layer 41c, the insulating layer 41b, and the insulating layer 41a, or may be removed after forming the opening 20a.

[0190] Furthermore, when forming the opening 20a, the end of the conductive film 25bf may be tapered. This is not limited to the conductive film 25bf, but the conductive film 25af, the insulating layer 41c, the insulating layer 41b, and the like may also be tapered. Furthermore, due to the influence of etching in the horizontal direction relative to the substrate (also referred to as side etching), the upper film may have a shape that protrudes more than the lower film (an overhang shape). For example, the side surface of the insulating layer 41b located in the opening 20a may be processed so as to be positioned outward relative to the side surface of the insulating layer 41c.

[0191] The sidewalls of the opening 20a are preferably nearly perpendicular to the top surface of the conductive layer 24, since this reduces the area of ​​the opening 20a. This configuration allows a transistor with a small occupation area to be fabricated. Alternatively, the sidewalls of the opening 20a may be tapered. The tapered shape improves the coverage of a film formed inside the opening 20a.

[0192] The maximum width of the opening 20a (maximum diameter when the opening 20a is circular in plan view) is preferably as small as possible. For example, the maximum width of the opening 20a is 2 μm or less, 1 μm or less, 500 nm or less, 300 nm or less, 150 nm or less, 100 nm or less, 60 nm or less, 50 nm or less, 40 nm or less, 30 nm or less, or 20 nm or less, and is preferably 5 nm or more. In particular, to process the opening 20a extremely finely, it is preferable to use a lithography method using short-wavelength light such as EUV light or an electron beam.

[0193] Next, it is preferable to perform a heat treatment (FIG. 8B). The heat treatment is preferably performed in a reduced pressure atmosphere or an inert gas (nitrogen gas or noble gas) atmosphere. The heat treatment is performed at a temperature of 100° C. or higher and 400° C. or lower, preferably 100° C. or higher and 350° C. or lower, more preferably 150° C. or higher and 300° C. or lower, and even more preferably 200° C. or higher and 300° C. or lower. When the heat treatment is performed in a reduced pressure atmosphere, the pressure in the treatment chamber may be lower than atmospheric pressure, for example, 1×10 −７ Pa or more and 1 Pa or less, preferably 1×10 −６ Pa or more 1×10 −２ The heat treatment can be carried out at a pressure of 100 Pa or less.

[0194] At this time, with the upper surface of the conductive layer 24b and the upper surface of the conductive film 25bf exposed, oxygen (oxygen (O ２ ), ozone (O ３By performing the heat treatment in an atmosphere containing as few metal oxides as possible (including metal oxides such as In—Sn oxide and In—Zn oxide), the resistance of the conductive layer 24b and the conductive film 25bf can be reduced. In particular, when a metal oxide film such as an In—Sn oxide or an In—Zn oxide is used for the conductive layer 24b and the conductive film 25bf, the heat treatment partially eliminates oxygen, forming oxygen vacancies (Vo) in the film, thereby reducing the electrical resistance. Note that if the heat treatment is performed in an atmosphere containing oxygen, oxygen may be supplied to the conductive layer 24b and the conductive film 25bf, resulting in a high resistance.

[0195] Furthermore, by performing heat treatment on the conductive layer 24b and the conductive film 25bf, the crystallinity of the conductive layer 24b and the conductive film 25bf can be improved, thereby reducing the electrical resistance. For example, even if the conductive film that becomes the conductive layer 24b and the conductive film 25bf are formed under conditions that make them amorphous, they can be crystallized by heat treatment to become the conductive layer 24b and the conductive layer 25b having a polycrystalline or single-crystalline structure. Furthermore, for example, when a conductive material containing a dopant in indium oxide, such as In—Sn oxide, is used for the conductive layer 24 and the conductive film 25bf, the activation rate of the dopant can be improved by heat treatment, thereby reducing the electrical resistance.

[0196] Furthermore, since the heat treatment is performed in a state where the insulating layer 41b is exposed, hydrogen can be desorbed from the insulating layer 41b, and the hydrogen concentration at the contact surface with the semiconductor layer 21 and its vicinity can be reduced, thereby improving reliability. Note that it is important not to set the heating temperature too high, as there is a risk that oxygen in the insulating layer 41b may also be desorbed by the heat treatment. By setting the heating temperature within the above range, it is possible to minimize the amount of oxygen desorbed. Furthermore, it is preferable to supply an excess amount of oxygen to the insulating layer 41b in advance, taking into account the oxygen that will be desorbed during the heat treatment.

[0197] Subsequently, a semiconductor film 21f that will become the semiconductor layer 21 is formed to cover the conductive film 25bf, the opening 20a, the conductive layer 24b, etc. (FIG. 8C).

[0198] The semiconductor film 21f may be a metal oxide (oxide semiconductor) film having semiconductor properties, which may be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0199] The metal oxide film preferably has crystallinity. In particular, the metal oxide film according to one embodiment of the present invention preferably has a metal oxide having a single crystal structure, a polycrystalline structure, or a CAAC structure.

[0200] In particular, it is preferable to use an indium oxide film as the semiconductor film 21 f. For example, by forming the indium oxide film by the ALD method, which has high step coverage, a film of an appropriate thickness can be formed on the sidewall of the opening 20 a, and a transistor with good electrical characteristics can be realized.

[0201] Alternatively, the semiconductor film 21f may be a laminated film of an indium oxide film and a metal oxide film containing indium and other metal elements. The metal oxide film may be formed by sputtering, not by ALD. For example, a laminated film of an indium oxide film and an In—Ga—Zn oxide (IGZO) film is preferable.

[0202] When the ALD method is used, it is preferable to use a film formation method such as thermal ALD (Atomic Layer Deposition) or PEALD (Plasma Enhanced ALD). The thermal ALD method is preferable because it exhibits extremely high step coverage. The PEALD method is also preferable because it exhibits high step coverage and allows low-temperature film formation.

[0203] For example, when a metal oxide is used for the semiconductor film, the film can be formed by an ALD method using a precursor containing the constituent metal element and an oxidizing agent.

[0204] For example, when forming an indium oxide film, a precursor containing indium can be used.

[0205] For example, when forming an In—Ga—Zn oxide film, three precursors, i.e., a precursor containing indium, a precursor containing gallium, and a precursor containing zinc, can be used, or two precursors, i.e., a precursor containing indium and a precursor containing gallium and zinc, can be used.

[0206] Examples of precursors that can be used that contain indium include triethylindium, trimethylindium, tris(2,2,6,6-tetramethyl-3,5-heptanedionate)indium, cyclopentadienylindium, indium(III) chloride, and (3-(dimethylamino)propyl)dimethylindium.

[0207] Furthermore, examples of precursors that can be used that contain gallium include trimethylgallium, triethylgallium, tris(dimethylamido)gallium(III), gallium(III) acetylacetonate, tris(2,2,6,6-tetramethyl-3,5-heptanedionate)gallium, dimethylchlorogallium, diethylchlorogallium, and gallium(III) chloride.

[0208] Furthermore, as a precursor containing zinc, dimethyl zinc, diethyl zinc, zinc bis(2,2,6,6-tetramethyl-3,5-heptanedionate), zinc chloride, etc. can be used.

[0209] Examples of oxidizing agents include ozone (O ３ ), oxygen (O ２ ), water (H ２ O), nitrogen dioxide (NO ２ ), nitrous oxide (N ２ O), hydrogen peroxide (H ２ O ２ ) or the like can be used, and two or more of these may be used.

[0210] In order to reduce the hydrogen and nitrogen concentrations in the film, O is used as an oxidizing agent. ２ or O ３ It is preferable to use O ３On the other hand, when forming a single crystal or a polycrystal with a large grain size, it is preferable to use an oxidizing agent containing hydrogen in order to suppress the generation of crystal nuclei in the initial stage of film formation. For example, H ２ O or H ２ O ２ After forming a film with few crystal nuclei, crystal growth can be caused by heat applied during film formation or by heat treatment after film formation, thereby forming a single crystal film or a polycrystalline film with a large grain size.

[0211] Methods for controlling the composition of the resulting film include adjusting the flow rate ratio of the source gases, the time for which the source gases are flowed, the order in which the source gases are flowed, etc. By adjusting these, it is also possible to form a film whose composition changes continuously. It is also possible to form two or more films with different compositions continuously.

[0212] The metal oxide film can be formed by, for example, a sputtering method using a metal oxide target.

[0213] The metal oxide film is preferably a dense film with as few defects as possible. Furthermore, the metal oxide film is preferably a high-purity film with as few impurities as possible, such as hydrogen and water, as reduced as possible. In particular, it is preferable to use a crystalline metal oxide film as the metal oxide film.

[0214] Furthermore, when forming a metal oxide film by sputtering, oxygen gas may be mixed with an inert gas (e.g., helium gas, argon gas, xenon gas, etc.). Note that the higher the ratio of oxygen gas to the total deposition gas when forming the metal oxide film (hereinafter also referred to as the oxygen flow ratio), the higher the crystallinity of the metal oxide film, resulting in a highly reliable transistor. On the other hand, the lower the oxygen flow ratio, the lower the crystallinity of the metal oxide film, resulting in a transistor with a higher on-state current.

[0215] When a metal oxide film is formed by a sputtering method, a higher substrate temperature can result in a denser metal oxide film with higher crystallinity, whereas a lower substrate temperature can result in a lower crystallinity and higher electrical conductivity.

[0216] The deposition conditions for the metal oxide film are such that the substrate temperature is from room temperature to 250° C., preferably from room temperature to 200° C., and more preferably from room temperature to 140° C. For example, a substrate temperature of from room temperature to less than 140° C. is preferred because productivity is increased. Furthermore, by depositing the metal oxide film at room temperature or without intentionally heating the substrate, the crystallinity can be reduced.

[0217] It is preferable to perform a treatment to enhance the crystallinity of the metal oxide film during or after the formation of the metal oxide film. Examples of treatments to enhance the crystallinity of the metal oxide film include heat treatment, plasma treatment, microwave (typically 2.45 GHz) treatment, microwave plasma treatment, and light (e.g., ultraviolet light) irradiation treatment. A plurality of these treatments may be performed simultaneously or sequentially. For example, heat treatment and microwave plasma treatment may be performed simultaneously. Alternatively, microwave plasma treatment may be performed after heat treatment.

[0218] Furthermore, it is more preferable to perform the treatment for increasing the crystallinity of the metal oxide film multiple times during the formation of the metal oxide film. For example, when forming a metal oxide film by the ALD method, it is preferable to perform a microwave plasma treatment every time an atomic layer is formed. Alternatively, it is preferable to perform a treatment for increasing the crystallinity every time a metal oxide film having a thickness within a predetermined range is formed, which can improve productivity. Specifically, it is preferable to form a first metal oxide film having a thickness of 1 nm to 10 nm, perform the first microwave plasma treatment, and then form a second metal oxide film having a thickness of 1 nm to 10 nm, and perform the second microwave plasma treatment.

[0219] The deposition method for the first metal oxide film and the second metal oxide film is not particularly limited, and ALD or sputtering may be used for each. In particular, depositing the first metal oxide film by ALD is preferable because it can prevent elements from the layer constituting the surface to be formed from being mixed into the first metal oxide film and the second metal oxide film (also known as mixing). This is particularly suitable when the elements contained in the layer constituting the surface to be formed inhibit the crystallization of the metal oxide (e.g., when the layer contains silicon, carbon, or the like). The first metal oxide film and the second metal oxide film may have different compositions. Although a stacked structure of the first metal oxide film and the second metal oxide film is illustrated here, the present invention is not limited thereto. Similar processes can be applied to a single-layer or a stacked structure of three or more layers of metal oxide films.

[0220] Furthermore, a treatment for increasing the crystallinity of a metal oxide film may be performed after the metal oxide film is formed. Specifically, the treatment may be performed directly on the formed metal oxide film, or may be performed through another film, such as an insulating film, formed on the metal oxide film. For example, a microwave plasma treatment may be performed after the metal oxide film is formed, or an insulating film (e.g., a silicon nitride film, a silicon oxide film, an aluminum oxide film, etc.) may be formed after the metal oxide film is formed, and then a heat treatment or a microwave plasma treatment may be performed on the metal oxide film through the insulating film.

[0221] The above-described treatment for increasing the crystallinity of a metal oxide film can also serve as a treatment for removing impurities contained in the metal oxide film. For example, carbon, hydrogen, nitrogen, and the like contained in the metal oxide film can be preferably removed. Alternatively, by performing the treatment for increasing the crystallinity of a metal oxide film in an oxygen gas atmosphere, oxygen vacancies in the metal oxide film can be reduced.

[0222] When performing a treatment to increase the crystallinity of a metal oxide film, it is preferable to set the temperature of the heat treatment (or the temperature of the substrate) to room temperature (e.g., 25°C) or higher and 700°C or lower, 100°C or higher and 600°C or lower, or 300°C or higher and 450°C or lower.

[0223] By increasing the crystallinity of the metal oxide film, a highly reliable transistor can be realized.

[0224] In the following drawings, the semiconductor layer is shown as a single layer, but it may also have a laminated structure. For example, it may have a two-layer structure formed by the ALD method, a three-layer structure formed by the ALD method, a two-layer structure in which the first layer is formed by the ALD method and the second layer is formed by the sputtering method, or a three-layer structure in which the first layer is formed by the ALD method, the second layer is formed by the sputtering method, and the third layer is formed by the ALD method or the sputtering method. Forming the first layer by the ALD method is preferable because it can suppress mixing, but it is also possible to form the first layer by the sputtering method and the second layer by the ALD method. The semiconductor layer may also have a laminated structure of four or more layers.

[0225] When a film that easily crystallizes, such as an indium oxide film, is used for the semiconductor film 21f, a single-crystal or polycrystalline film can be obtained by heat treatment during or after the formation of the semiconductor film 21f. In this case, it is preferable that the conductive layer 24b and the conductive film 25bf in contact with the semiconductor film 21f have crystallinity. As a result, a crystalline region reflecting the crystallinity of the conductive layer 24b or the conductive film 25bf is generated in the region of the semiconductor film 21f in contact with the conductive layer 24b or the conductive film 25bf. Crystallization proceeds from the crystalline region, resulting in a polycrystalline film with large crystal grains or a film that is substantially single-crystal.

[0226] The conductive layer 24b and the conductive film 25bf are preferably made of an oxide conductive material containing indium, which can reduce the contact resistance with the semiconductor layer 21. In particular, the use of an In—Sn oxide having a polycrystalline structure is more preferable, as it can reduce not only the contact resistance but also the electrical resistance of the conductive layer 24b and the conductive layer 25b themselves.

[0227] 9 shows a schematic diagram of the crystal growth during the deposition of semiconductor film 21f. Crystal regions are generated in semiconductor film 21f in the portions in contact with conductive layer 24b and conductive film 25bf, and crystal growth occurs from these portions, with crystallization progressing toward insulating layer 41b in opening 20a, as indicated by the dashed arrows in FIG.

[0228] At this time, if the conductive film 25af is made of a conductive material that is easily oxidized, such as tungsten, molybdenum, or aluminum, the conductive film 25af may be oxidized during the formation of the semiconductor film 21f, and an oxide 25o may be formed on the exposed portion of the conductive film 25af. For example, the surface of the conductive film 25af may be oxidized by an oxidizing agent used in the ALD method or oxygen in the film formation gas in the sputtering method, and the oxide 25o may be formed.

[0229] When oxide 25o is formed on the surface of conductive film 25af, as crystallization progresses from the region of semiconductor film 21f that contacts the upper surface of conductive film 25bf toward the interior of opening 20a, the progress of crystallization may stop at the portion that contacts oxide 25o, forming region 21x with unclear crystallinity in that region. Meanwhile, crystallization progresses from the conductive layer 24b toward insulating layer 41a, insulating layer 41b, and insulating layer 41c, and stops upon reaching region 21x. Therefore, a single crystal grain may be formed in semiconductor film 21f across conductive layer 24b, insulating layer 41a, insulating layer 41b, and insulating layer 41c. In other words, a structure without grain boundaries that straddle the current path can be realized in the channel formation region of semiconductor layer 21.

[0230] In addition, since region 21x of semiconductor film 21f has lower crystallinity than other regions and can be made into an n-type region, it is presumed that this does not cause a decrease in on-current. In this case, the effective channel length of the transistor is the length of the portion of semiconductor layer 21 that contacts insulating layer 41b or the portion that contacts insulating layers 41a, 41b, and 41c.

[0231] Next, a resist mask is formed on the semiconductor film 21f so as to cover at least the opening 20a, and the regions of the semiconductor film 21f, the conductive film 25bf, and the conductive film 25af that are not covered by the resist mask are etched to form the semiconductor layer 21, the conductive layer 25b, and the conductive layer 25a.

[0232] Although the example in which the conductive layers 25 a and 25 b and the semiconductor layer 21 are processed using the same resist mask has been shown here, they may be processed separately using different resist masks. For example, the conductive layers 25 a and 25 b may be formed before the opening 20 a is formed, and then heat treatment may be performed after the opening 20 a is formed, and then the semiconductor film 21 f may be formed and the semiconductor film 21 f may be processed to form the semiconductor layer 21.

[0233] Next, an insulating layer 22 is formed to cover the insulating layer 41c, the conductive layer 25a, the conductive layer 25b, and the semiconductor layer 21 ( FIG. 10A ). The insulating layer 22 can be formed by a film formation method such as sputtering, ALD, or CVD. It is preferable that the insulating layer 22 be provided with as uniform a thickness as possible on the surface of the vertical portion of the semiconductor layer 21. Therefore, it is preferable to form the insulating layer 22 by the ALD method, which is a film formation method with extremely excellent coverage. Note that if the side surface of the opening 20a in the insulating layer 41 is tapered, the insulating layer 22 can be formed by sputtering, CVD, or the like.

[0234] Next, a conductive film that will later become conductive layer 23a and a conductive film that will later become conductive layer 23b are formed to cover insulating layer 22. These conductive films are preferably formed by a film formation method that provides high coverage. In particular, the conductive film that will become conductive layer 23b is preferably formed by a film formation method that provides high embedding. For example, the two conductive films can be formed consecutively by CVD. Alternatively, the conductive film that will become conductive layer 23a may be formed by ALD, and then the conductive film that will become conductive layer 23b may be formed by CVD.

[0235] Subsequently, unnecessary portions of the two conductive films are removed by etching to form conductive layers 23a and 23b (FIG. 10B).

[0236] Through the above steps, the transistor 10 can be formed.

[0237] This completes the description of the example of the method for manufacturing a transistor.

[0238] Embodiment 2 A structure of a memory device including a transistor and a capacitor according to one embodiment of the present invention will be described below.

[0239] 11A shows a circuit diagram of a memory cell 30. The memory cell 30 includes one transistor Tr1 and one capacitor C, and can also be represented as 1Tr1C. The transistor Tr1 has a gate connected to a wiring WL, one of a source and a drain connected to a wiring BL, and the other connected to one electrode of the capacitor C. The other electrode of the capacitor C is connected to a wiring PL.

[0240] The memory cell 30 can store data by holding, in the capacitor C, a data potential input from the wiring BL via the transistor Tr1. Furthermore, data can be held by turning the transistor Tr1 off. Furthermore, by turning the transistor Tr1 on, a potential corresponding to the held data is output to the wiring BL, allowing the data to be read. A signal that controls the conduction and non-conduction of the transistor Tr1 is applied to the wiring WL. Furthermore, a predetermined potential (e.g., a fixed potential) is applied to the wiring PL.

[0241] 11B and 11C show cross-sectional views of the memory cell 30. Fig. 11B is a cross-sectional view taken along the extension direction of the conductive layer 25, and Fig. 11C is a cross-sectional view taken along the extension direction of the conductive layer 31. The memory cell 30 has a configuration in which a transistor 10 is stacked on a capacitance element 50. The transistor 10 corresponds to the transistor Tr1, and the capacitance element 50 corresponds to the capacitance element C.

[0242] The configuration of the transistor 10 will not be described here because the description in Embodiment 1 can be referred to. Note that although an example using the transistor 10 is shown here, the transistor is not limited to the transistor 10 and can be replaced with various transistors described in Embodiment 1.

[0243] The capacitance element 50 includes a conductive layer 51, a conductive layer 52, and an insulating layer 53 sandwiched therebetween. The capacitance element 50 constitutes a so-called MIM (Metal-Insulator-Metal) capacitor.

[0244] The capacitance element 50 is provided on the insulating layer 11. A conductive layer 34 is provided on the insulating layer 11, and an insulating layer 55 is provided on the conductive layer 34. An opening 20d is provided in the insulating layer 55, reaching the conductive layer 34. A conductive layer 51 is provided inside the opening 20d, in contact with the side surface of the insulating layer 55 and the upper surface of the conductive layer 34. An insulating layer 53 is provided covering the insulating layer 55 and the conductive layer 51. An insulating layer 56 is provided on the insulating layer 53. The conductive layer 52 is provided so as to be embedded in the insulating layer 56 and the opening 20d.

[0245] The conductive layer 52 and the insulating layer 56 have flattened upper surfaces, and are at approximately the same height.

[0246] 11B and 11C, the conductive layer 25b corresponds to the wiring BL, the conductive layer 23 corresponds to the wiring WL, and the conductive layer 34 corresponds to the wiring PL.

[0247] A low-resistance conductive material can be used for the conductive layer 34, the conductive layer 51, and the conductive layer 52. For example, the material that can be used for the conductive layer 23b can be used.

[0248] The insulating layer 53 functions as a dielectric layer of the capacitance element 50. The thinner the insulating layer 53 is and the higher the relative dielectric constant thereof is, the larger the capacitance of the capacitance element 50 can be. For example, it is preferable to use a material that can be used for the insulating layer 22.

[0249] 12A shows a circuit diagram of a memory cell 30a. The memory cell 30a has a configuration in which the capacitor C of the memory cell 30 is replaced with a transistor Tr2. The gate of the transistor Tr2 is connected to the other of the source and drain of the transistor Tr1, one of the source and drain is connected to a wiring SL, and the other is connected to a wiring RL.

[0250] The memory cell 30a can store data by holding a data potential input from the wiring BL via the transistor Tr1 at a node connected to the gate of the transistor Tr2. Furthermore, data can be held by turning off the transistor Tr1. Furthermore, the conduction state between the wiring SL and the wiring RL of the transistor Tr2 changes depending on the potential held at the gate. For example, data can be read by applying a signal to one of the wirings SL and RL and determining the magnitude of the potential or current output to the other. Therefore, the memory cell 30a can be used as a memory capable of nondestructive readout.

[0251] 12A may include a capacitance element C. More specifically, one electrode of the capacitance element C may be connected to a node where the other of the source and drain of the transistor Tr1 and the gate of the transistor Tr2 are connected. In this case, the wiring PL may be connected to the other electrode of the capacitance element C. The capacitance element C may have the same configuration as the capacitance element 50 described above, or various MIM capacitors such as a parallel plate type, a cylinder type, or a pillar type may be used.

[0252] 12B and 12C are cross-sectional views of the memory cell 30a. The memory cell 30a has a structure in which a transistor 10 is stacked on a transistor 70. The structure of the transistor 10 is similar to that of the memory cell 30 described above.

[0253] The transistor 70 includes a conductive layer 74 a, a conductive layer 74 b, a semiconductor layer 71, an insulating layer 72, a conductive layer 73, a conductive layer 75 a, and a conductive layer 75 b. The transistor 70 is a vertical transistor provided in a region overlapping with an opening 20 e provided in the conductive layer 75 b, the conductive layer 75 a, the insulating layer 55 a, the insulating layer 55 b, and the insulating layer 55 c. For the transistor 70, the description of the transistor 10 can be referred to.

[0254] A conductive layer 74a is provided on the insulating layer 11, a conductive layer 74b is provided on the conductive layer 74a, and insulating layers 55a, 55b, and 55c are stacked on the conductive layer 74b. A conductive layer 75a and a conductive layer 75b are provided on the insulating layer 55c. A semiconductor layer 71 and an insulating layer 72 are provided along the inner walls of an opening 20e provided in the conductive layer 75a, the conductive layer 75b, the insulating layer 55a, the insulating layer 55b, and the insulating layer 55c. The semiconductor layer 71 is provided in contact with the top and side surfaces of the conductive layer 75b, the side surfaces of the conductive layer 75a, the insulating layer 55a, the insulating layer 55b, and the insulating layer 55c, and the top and side surfaces of the conductive layer 74b. The conductive layer 73 is provided to fill the opening in the insulating layer 56 and the opening 20e.

[0255] 12B and 12C, the conductive layer 73 corresponds to the gate of the transistor Tr2, the conductive layers 75a and 75b correspond to one of the wirings SL and RL, and the conductive layers 74a and 74b correspond to the other of the wirings SL and RL.

[0256] 13A and 13B show an example of a memory device in which two memory cells 30 are connected to a common wiring. Fig. 13A is a schematic top view of the memory device, and Fig. 13B is a schematic cross-sectional view taken along line A3-A4 in Fig. 13A.

[0257] The conductive layer 31 functioning as the wiring WL is provided for each of the two memory cells 30. The conductive layer 25a functioning as the wiring BL is provided in common to the two memory cells 30.

[0258] The conductive layer 25a functioning as the wiring BL is embedded in each interlayer insulating layer and is electrically connected to the conductive layer 61 and the conductive layer 62 functioning as plugs (also referred to as connection electrodes). The conductive layer 61 may be electrically connected to a sense amplifier (not shown) provided below the insulating layer 11. The conductive layer 61 may also be electrically connected to the conductive layer 25a of a memory cell stacked above the insulating layer 65.

[0259] The insulating layer 65 functions as a barrier layer and has a function of preventing impurities such as water and hydrogen from diffusing into the memory device from the outside.

[0260] Furthermore, a memory cell array can be configured by arranging the memory cells 30 in a three-dimensional matrix. As an example of a memory cell array, Figures 14A and 14B show an example of a memory device in which 4 x 2 x 4 memory cells 30 are arranged in the X, Y, and Z directions. Figure 14A is a plan view of the memory device, and Figure 14B is a cross-sectional view taken along the cutting line A3-A4 in Figure 14A.

[0261] A group of four memory cells 30 can be called a memory unit 60. 14A and 14B show eight memory units (memory unit 60[1,1] to memory unit 60[2,4]). In memory unit 60[a,b] (a and b are positive integers), a indicates an address in the Y direction, and b indicates an address in the Z direction.

[0262] In the memory unit 60, two memory cells 30 are arranged symmetrically around the conductive layer 61 or the conductive layer 62. The conductive layers 32 of the memory units 60 stacked in the Z direction are electrically connected to each other by the conductive layer 62. By stacking a plurality of memory units 60 in this way, it is possible to increase the storage capacity per unit area, and to provide a memory device that can be miniaturized or highly integrated.

[0263] 15A and 15B show an example in which the connection portion is arranged at the end of the memory unit. FIG. 15A is a plan view of the memory device, and FIG. 15B is a cross-sectional view. Here, as an example of a memory cell array, an example of a memory device in which 3 x 3 x m (m is an integer of 2 or more) memory cells 30 are arranged is shown. Of the layers having memory cells 30, the first layer is denoted as layer 80[1], and the mth layer (top) is denoted as layer 80[m].

[0264] The conductive layer 63 is provided outside the memory unit. The conductive layer 63 may be connected to wiring in a layer above the layer 80 including the conductive layer 63. For example, the conductive layer 63 provided in the layer 80[1] is electrically connected to wiring in the layer 80[2]. However, this is not limiting, and the conductive layer 63 may be configured to be electrically connected to wiring in the layer 80 located below the layer 80 including the conductive layer 63.

[0265] FIG. 16 shows an example of a cross-sectional configuration of a memory device in which a layer having memory cells 30 is stacked on a layer in which a driver circuit including a sense amplifier is provided.

[0266] 16 shows an example in which a capacitor 50 is stacked above a transistor 90, and the transistor 10 is stacked thereon. The transistor 90 is one of the transistors included in the sense amplifier.

[0267] By configuring the sense amplifier so that it overlaps with the memory cell 30, the bit line can be shortened. This reduces the load on the bit line, improving the read sensitivity of the sense amplifier. This allows the memory device to be driven at high speed.

[0268] The transistor 90 is provided over a substrate 91 and includes a conductive layer 94 functioning as a gate, an insulating layer 93 functioning as a gate insulating layer, a semiconductor region 92 formed of part of the substrate 91, and low-resistance regions 95 a and 95 b functioning as source and drain regions. The transistor 90 may be either a p-channel type or an n-channel type.

[0269] 16, a semiconductor region 92 (part of a substrate 91) where a channel is formed has a convex shape. A conductive layer 94 is provided to cover the side and top surfaces of the semiconductor region 92 with an insulating layer 93 interposed therebetween. Such a transistor 90 is also called a FIN transistor because it utilizes the convex portion of the semiconductor substrate.

[0270] It is preferable that a structure in which interlayer insulating layers and wiring layers are alternately stacked (also referred to as a multilayer wiring layer) be provided between a layer in which the transistor 90 is provided and a layer in which the memory cell 30 is provided. In the example shown in Figure 16, the low-resistance region 95b of the transistor 90 is electrically connected to the conductive layer 25 functioning as a bit line of the memory cell 30 via a wiring and a plug.

[0271] [Configuration Example 2] Hereinafter, an example in which a plurality of transistors are provided in a slit-shaped opening will be described.

[0272] 17 is a perspective schematic view of a configuration in which a capacitor 50 and a transistor 10d are stacked. For the transistor 10d, refer to the above-mentioned Configuration Example 1.

[0273] The transistor 10d has a semiconductor layer 21 inside a slit 20 provided in an insulating layer 41. The slit 20 is provided to extend in the Y direction. The semiconductor layer 21 is provided along the inner wall of the slit 20. The semiconductor layer 21 is in contact with a conductive layer 24 located at the bottom of the slit 20 and a conductive layer 25 provided on the insulating layer 41. The semiconductor layers 21 are arranged at equal intervals in the Y direction. An insulating layer 22 is provided to cover the semiconductor layer 21 and the insulating layer 41. The conductive layer 23 is embedded inside the slit 20 and extends in the Y direction. The conductive layer 23 also functions as wiring.

[0274] An insulating layer 44 is provided to cover the insulating layer 22, and a conductive layer 26 that functions as a wiring extending in the X direction is provided on the insulating layer 44. The insulating layer 44 functions as an interlayer insulating layer. An opening that reaches the conductive layer 25a is provided in the insulating layer 44, the insulating layer 22, the semiconductor layer 21, and the conductive layer 25b, and a plug 27 is provided to fill the opening. The conductive layer 26 and the conductive layer 25a are connected via the plug 27.

[0275] Here, an example is shown in which plug 27 is provided so as to penetrate conductive layer 25b and contact conductive layer 25a. This configuration in which low-resistance conductive layer 25a and plug 27 are in contact with each other is preferable because it reduces the contact resistance between them and reduces the wiring load. Note that the bottom surface of plug 27 may also be configured to contact conductive layer 25b or semiconductor layer 21.

[0276] 18A and 18B are different from the above-described example configuration mainly in that the extension directions of the word lines and bit lines are reversed. Fig. 18A shows a schematic cross-sectional view perpendicular to the Y direction, and Fig. 18B shows a schematic perspective view.

[0277] The conductive layer 23 is processed into an island shape and is connected to a conductive layer 29 located above it, which functions as a word line. The conductive layer 29 extends in the X direction. On the other hand, the conductive layer 25 extends in the same direction as the slit 20, i.e., the Y direction. The conductive layer 25 functions as a bit line.

[0278] An insulating layer 44 is provided on the insulating layer 41, and a portion of the conductive layer 23 is provided so as to be embedded in the insulating layer 44. The upper surface of the conductive layer 23 is flattened, and its height from the substrate surface is approximately the same as that of the upper surface of the insulating layer 44. The conductive layer 29 is provided on the conductive layer 23 and the insulating layer 44.

[0279] Furthermore, the insulating layer 22 and the semiconductor layer 21 each have a top surface shape that is approximately the same as that of the conductive layer 23. For example, the insulating layer 22 and the semiconductor layer 21 can be configured to be processed using the same etching mask as that used for the conductive layer 23.

[0280] Furthermore, an insulating layer 43 is provided between the insulating layer 44 and each of the semiconductor layer 21, the insulating layer 22, the conductive layer 23, the conductive layer 25, and the insulating layer 41. The insulating layer 43 can prevent impurities such as hydrogen from diffusing from the insulating layer 44 to the semiconductor layer 21.

[0281] The configuration shown in FIGS. 19A and 19B differs from the configuration shown in FIG. 17 mainly in that two transistors (transistor 10e) are provided in one slit 20.

[0282] The semiconductor layer 21, the insulating layer 22, the conductive layer 23, and the conductive layer 24 are divided into two parts within the slit 20 along the extension direction of the slit 20. The semiconductor layer 21 and the insulating layer 22 are provided along one of a pair of side surfaces of the insulating layer 41 within the slit 20.

[0283] A capacitance element 50 is provided in each of the pair of divided conductive layers 24. This allows one slit 20 to be shared by two memory cells 15. In this case, two slits 40 are provided for one slit 20. The slits 40 are provided at positions shifted in the X direction from the center of the slit 20.

[0284] Furthermore, an insulating layer 48 is provided along the side surfaces of the conductive layer 23, the insulating layer 22, the semiconductor layer 21, and the conductive layer 24, and along the top surface of the insulating layer 53. A recess is formed in the top surface of the insulating layer 48, and the insulating layer 44 is provided on the insulating layer 48 so as to fill the recess. Similar to the insulating layer 43, the insulating layer 48 preferably functions as a barrier film against impurities. This makes it possible to prevent impurities such as hydrogen contained in the insulating layer 44 from diffusing into the semiconductor layer 21.

[0285] By configuring the memory device exemplified in this embodiment, a highly integrated memory device can be realized.

[0286] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0287] Embodiment 3 In this embodiment, an indium oxide film that can be used for a semiconductor layer of a transistor according to one embodiment of the present invention will be described.

[0288] In this specification and the like, indium oxide having at least a crystalline portion or a crystalline region in a film is referred to as crystalline indium oxide (crystal IO) or crystalline indium oxide (crystalline IO). Examples of crystalline IO or crystalline IO include single-crystalline indium oxide, polycrystalline indium oxide, and microcrystalline indium oxide.

[0289] Indium oxide is a semiconductor material having physical properties that are completely different from those of oxide semiconductors such as In—Ga—Zn oxide (hereinafter also referred to as IGZO) and zinc oxide.

[0290] The carrier concentration dependence of the Hall mobility of indium oxide, silicon, and IGZO will be explained. Figure 20A shows the carrier concentration dependence of the Hall mobility of silicon (Si) and indium oxide (InO Ｘ ) and FIG. 20B is a schematic diagram showing the carrier concentration dependence of the hole mobility for IGZO.

[0291] First, IGZO tends to exhibit higher hole mobility as the carrier concentration increases, as shown by the arrows in Figure 20B. On the other hand, indium oxide tends to exhibit higher hole mobility as the carrier concentration decreases, as shown by the arrows in Figure 20A (see Non-Patent Document 1). This trend is similar to that of silicon; the lower the dopant (impurity) concentration in the material, the less impurity scattering there is and the higher the hole mobility. In other words, the higher the purity and intrinsic indium oxide, the higher the hole mobility. From these results, it can be said that indium oxide, unlike IGZO, is a material with physical properties similar to those of silicon. Note that the characteristics of indium oxide shown in Figure 20A are assumed to be single crystal. Therefore, when indium oxide is non-single crystal (e.g., polycrystalline), the characteristics may differ from those shown in Figure 20A.

[0292] 20A, the range R1 of low carrier concentration has extremely high hole mobility, and therefore can be said to be a range of carrier concentration suitable for, for example, a channel formation region of a transistor. For example, in the case of indium oxide, the range R1 is a range where the carrier concentration value is 1×10 １５ cm −３ The range includes, for example, 1×10 １４ cm −３ That's it, 1 x 10 １８ cm −３ By sufficiently reducing the carrier concentration, the Hall mobility value can be increased to 270 cm ２ It is expected that the resistance can be increased to about / (V·s).

[0293] In addition, in indium oxide, the region where the carrier concentration is in the range R1 may contain an element that lowers the carrier concentration. Examples of elements that lower the carrier concentration include magnesium, calcium, zinc, cadmium, and copper. By substituting these elements for indium, the carrier concentration can be lowered. Examples of elements that lower the carrier concentration include nitrogen, phosphorus, arsenic, and antimony. For example, by substituting nitrogen, phosphorus, arsenic, or antimony for oxygen, the carrier concentration can be lowered.

[0294] On the other hand, the range R2 with a high carrier concentration has a low electrical resistance, and can be said to be a range of carrier concentrations suitable for, for example, the source and drain regions of a transistor, a resistor, or a transparent conductive film. ２０ cm −３ The range includes, for example, 1×10 １９ cm −３ That's it, 1 x 10 ２２ cm −３ By increasing the carrier concentration sufficiently, the resistivity can be reduced to 1×10 −４ It is expected that the resistivity can be reduced to Ω·cm or less.

[0295] In the indium oxide, the region having a carrier concentration in the range R2 may contain an element that increases the carrier concentration. For example, it is preferable that the indium oxide contains an element that is common to the source electrode and the drain electrode of the transistor. Examples of elements that increase the carrier concentration include titanium, zirconium, hafnium, tantalum, tungsten, molybdenum, tin, silicon, and boron. In particular, it is more preferable to use an element whose oxide has conductive or semiconductive properties.

[0296] In this way, indium oxide uses a region with a low carrier concentration as the channel formation region of a transistor, and a region with a high carrier concentration as the source and drain regions of the transistor. In other words, indium oxide can be said to be an oxide capable of valence electron control. Note that IGZO may experience strain in the source and drain regions due to stress from electrodes in contact with the IGZO, resulting in the formation of n-type regions. On the other hand, unlike IGZO, indium oxide is capable of valence electron control, and therefore does not require strain to be formed in the film as with IGZO. Less strain in the film is expected to improve reliability. For example, by separately creating a region with a carrier concentration in the range R1 shown in FIG. 20A and a region with a carrier concentration in the range R2 in the indium oxide film, a so-called n-i-n junction (a junction between an n-type region, an i-type region, and an n-type region) can be created. Note that valence electron control in transistors using silicon is generally known. On the other hand, valence electron control in transistors using indium oxide is a novel technical concept that would not normally be conceived.

[0297] By using the above technical concept, the transistor having indium oxide in this specification and the like has two or more, preferably three or more, more preferably four or more, and most preferably five of the following characteristics (1) to (5): (1) high on-current (in other words, high mobility); (2) low off-current; (3) normally-off operation; (4) high reliability; and (5) high cutoff frequency (fT). For example, the transistor having indium oxide in this specification and the like has high mobility, low off-current, and is normally-off operation. The transistor has high mobility and is different from a normally-on transistor.

[0298] Next, an indium oxide film applied to a transistor will be described. The indium oxide film preferably has crystallinity (i.e., has crystal grains). Examples of films having crystal grains include single-crystal films, polycrystalline films, and amorphous films containing crystal grains (also called microcrystalline films). In particular, the indium oxide film is preferably a polycrystalline film, and more preferably a single-crystal film. A single-crystal film does not have grain boundaries. Impurities (typically, insulating impurities, insulating oxides, etc.) that hinder carrier flow tend to segregate at grain boundaries. The use of a single-crystal film can suppress carrier scattering at grain boundaries, thereby realizing a transistor exhibiting high field-effect mobility. Furthermore, the use of a single-crystal film has the excellent effect of suppressing variations in transistor characteristics due to the grain boundaries.

[0299] Furthermore, polycrystalline films are preferable because they can reduce carrier scattering and exhibit high field-effect mobility compared to microcrystalline or amorphous films. When using a polycrystalline film, it is preferable to use a film with as large a crystal grain size as possible and with few crystal grain boundaries. Note that in a transistor using an indium oxide polycrystalline film, if there is no crystal grain boundary in the channel formation region or no crystal grain boundary is observed, the channel formation region is located within a single crystal region included in the polycrystalline film, and therefore the transistor can be considered to be using single-crystal indium oxide.

[0300] The crystallinity of indium oxide can be analyzed by, for example, X-ray diffraction (XRD), transmission electron microscope (TEM), or electron diffraction (ED). Alternatively, a combination of these methods may be used for analysis.

[0301] In this specification and the like, a semiconductor layer in which no crystal grain boundary is observed in the channel formation region, a semiconductor layer in which the channel formation region is included in one crystal grain, or a semiconductor layer in which the crystal axis direction is the same in at least two regions in the channel formation region can be called a single crystal film. Also, a semiconductor layer in which, in the channel formation region, within one crystal grain, the direction of another crystal axis continuously changes around a certain crystal axis or a certain crystal orientation as the axis of rotation can be called a single crystal film.

[0302] The channel formation region refers to a region of the semiconductor layer that overlaps (or faces) the gate electrode via the gate insulating layer, and is located between the region in contact with the source electrode and the region in contact with the drain electrode. The current path in the channel formation region is the shortest distance between the source electrode and the drain electrode. Therefore, the crystal grains, crystal grain boundaries, crystal axes, crystal orientation, etc. in the channel formation region can be confirmed by observing a cross section including the semiconductor layer, the source electrode, and the drain electrode.

[0303] The indium oxide film in the channel formation region preferably has a lower impurity concentration. Impurities in the indium oxide film in the channel formation region can be a scattering source of carriers, which can lead to a decrease in field-effect mobility. These impurities can also hinder the crystal growth of the indium oxide film. Examples of impurities in the indium oxide film include boron and silicon. The indium oxide film preferably contains these impurities at concentrations of 0.1% or less, and more preferably 0.01% (100 ppm) or less. Carbon, hydrogen, and other elements may be contained in the film-forming gas or precursor during film formation, and may remain in the indium oxide film in greater amounts than the above-mentioned impurities.

[0304] The indium oxide film in the channel formation region may contain an element that can become the same trivalent cation as indium, as long as the crystal maintains a cubic crystal structure (bixbyite type). Examples of such an element include Group 13 elements of the periodic table, such as gallium and aluminum, and Group 3 elements of the periodic table. These elements exist mainly as trivalent cations in oxides, and therefore the carrier concentration of indium oxide can be maintained low.

[0305] By using such an indium oxide film in a transistor, the field effect mobility of the transistor can be increased to 50 cm ２ / (V·s) or more, preferably 100 cm ２ / (V·s) or more, more preferably 150 cm ２ / (V·s) or more, more preferably 200 cm ２ / (V·s) or more, more preferably 250 cm ２ / (V·s) or more.

[0306] One of the features of an indium oxide film is that it has higher oxygen permeability (diffusibility) than an IGZO film. As shown in FIG. 20C, Ｘ Oxygen (O) diffusing into the indium oxide film passes through the indium oxide film and becomes oxygen molecules (O ２ ) and is released as water molecules (H ２ O) may be released in the film. Ｏ In the case where an indium oxide film is present, oxygen atoms diffuse to compensate for the oxygen vacancies. Since oxygen diffuses easily in the indium oxide film, it can be said that oxygen vacancies are more easily compensated for in the indium oxide film than in the IGZO film.

[0307] As described above, an indium oxide film can more easily reduce oxygen vacancies in the film than an IGZO film. Therefore, by using such an indium oxide film in a transistor, a transistor exhibiting extremely high reliability can be realized.

[0308] Furthermore, as shown in FIG. 20C, the indium oxide film diffuses hydrogen. Hydrogen that diffuses into the indium oxide film from the outside passes through the indium oxide film and becomes hydrogen molecules (H ２ ) or reacts with oxygen contained in the membrane and is released as water molecules.

[0309] A transistor using an indium oxide film is an accumulation-type transistor that uses electrons as majority carriers. Assuming that the carrier relaxation time is constant, the smaller the effective mass of the electrons (carriers), the higher the electron mobility. In other words, by using indium oxide, which has a small effective mass of electrons, for a transistor, the on-state current or field-effect mobility of the transistor can be increased.

[0310] Table 1 shows the results of single crystal indium oxide (here, In ２ O ３ ) and single-crystal silicon (Si). As shown in Table 1, indium oxide is characterized by a small effective mass of electrons and a large effective mass of holes. Indium oxide also has the characteristic that the effective mass of electrons is almost independent of the crystal orientation. Therefore, by using crystalline indium oxide in a transistor, a transistor with high field-effect mobility and high frequency characteristics (also called f characteristics) can be realized. Furthermore, since the effective mass of holes is large, a transistor with extremely small off-current can be realized. For example, by applying an indium oxide film to a vertical transistor, the off-current per 1 μm of channel width can be reduced to 1 fA (1×10) in an environment of 125° C. −１５ A) or less, or 1aA (1 x 10 −１８ A) or less, and under room temperature (25°C) conditions, −１８ A) or less, or 1zA (1 x 10 −２１ Furthermore, as shown in Table 1, indium oxide has a smaller effective mass of electrons and a larger effective mass of holes than silicon, and therefore may be able to realize a transistor with higher field-effect mobility and lower off-state current than a Si transistor.

[0311]

[0312] It is preferable to provide a seed layer so as to be in contact with at least a portion of the crystalline indium oxide film. The seed layer is preferably made of a material containing crystals with a small difference in lattice constant (also called lattice mismatch) with indium oxide. This can improve the crystallinity of the indium oxide film. Note that a substrate (e.g., a single-crystal substrate) may be used as one of the layers in contact with at least a portion of the crystalline indium oxide film.

[0313] One method for evaluating the degree of lattice mismatch is to use the value of the lattice mismatch shown below. The lattice mismatch Δa [%] of the crystals of the formed film (here, the indium oxide film) with respect to the crystals of the seed layer is expressed as Δa = ((L １ -L ２ ) / L ２ ) × 100, where L １ is the length or lattice constant of the unit lattice vector of the crystal of the formed film, and L ２ is the length of the unit cell vector or the lattice constant of the crystal of the seed layer.

[0314] The smaller the absolute value of the lattice mismatch Δa between the seed layer and the indium oxide film, the more preferable, and it is most preferably 0. For example, Δa can be set to −5% or more and 5% or less, preferably −4% or more and 4% or less, more preferably −3% or more and 3% or less, and even more preferably −2% or more and 2% or less.

[0315] Here, the indium oxide crystal has a cubic crystal structure (bixbyite type). For example, the crystal of yttria-stabilized zirconia (YSZ) can have a cubic crystal structure (fluorite type). The lattice mismatch of the indium oxide crystal with the cubic YSZ crystal is in the range of −2% to 2%, and a single crystal film of indium oxide can be epitaxially grown on the YSZ substrate.

[0316] It should be noted that the crystal structure of the seed layer and the crystal structure of the indium oxide film may not necessarily have the same crystal system or crystal orientation. For example, a film having crystals of a hexagonal or trigonal structure may be used under an indium oxide film having crystals of a cubic structure. For example, by setting the crystal orientation of the surface of the seed layer to

[001] and the crystal orientation of the underside of the indium oxide film to

[111] , the requirements related to the crystal orientation necessary for epitaxial growth can be satisfied. Examples of hexagonal or trigonal crystals include wurtzite structure, YbFe ２ O ４ Type structure, Yb ２ Fe ３ O ７ YbFeFe alloys have the following structures: ２ O ４ Type structure or Yb ２ Fe ３ O ７ An example of a crystal having a ZnO-type structure is IGZO.

[0317] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0318] Embodiment 4 In this embodiment, a semiconductor device 900 according to one embodiment of the present invention, which is different from the above embodiment, will be described. The semiconductor device 900 can function as a memory device.

[0319] Fig. 21 is a block diagram showing a configuration example of a semiconductor device 900. The semiconductor device 900 shown in Fig. 21 has a driver circuit 910 and a memory array 920. The memory array 920 has one or more memory cells 950. Fig. 21 shows an example in which the memory array 920 has a plurality of memory cells 950 arranged in a matrix.

[0320] The memory cell 950 can be any of the memory devices exemplified in the above embodiments.

[0321] The drive circuit 910 includes a PSW 931 (power switch), a PSW 932, and a peripheral circuit 915. The peripheral circuit 915 includes a peripheral circuit 911, a control circuit 912, and a voltage generation circuit 928.

[0322] In the semiconductor device 900, each circuit, signal, and voltage can be appropriately selected or omitted as needed. Alternatively, other circuits or signals may be added. The signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are input signals from the outside, and the signal RDA is an output signal to the outside. The signal CLK is a clock signal.

[0323] Furthermore, signals BW, CE, and GW are control signals. Signal CE is a chip enable signal, signal GW is a global write enable signal, and signal BW is a byte write enable signal. Signal ADDR is an address signal. Signal WDA is a write data signal, and signal RDA is a read data signal. Signals PON1 and PON2 are power gating control signals. Note that signals PON1 and PON2 may be generated by the control circuit 912.

[0324] The control circuit 912 is a logic circuit having a function of controlling the overall operation of the semiconductor device 900. For example, the control circuit 912 performs a logical operation on the signals CE, GW, and BW to determine the operation mode (e.g., write operation, read operation) of the semiconductor device 900. Alternatively, the control circuit 912 generates a control signal for the peripheral circuit 911 so that this operation mode is executed.

[0325] The voltage generating circuit 928 has a function of generating a negative voltage. The signal WAKE has a function of controlling the input of the signal CLK to the voltage generating circuit 928. For example, when an H-level signal is given as the signal WAKE, the signal CLK is input to the voltage generating circuit 928, and the voltage generating circuit 928 generates a negative voltage.

[0326] The peripheral circuit 911 is a circuit for writing and reading data to and from the memory cells 950. The peripheral circuit 911 includes a row decoder 941, a column decoder 942, a row driver 923, a column driver 924, an input circuit 925, an output circuit 926, and a sense amplifier 927.

[0327] The row decoder 941 and the column decoder 942 have the function of decoding the signal ADDR. The row decoder 941 is a circuit for specifying a row to be accessed, and the column decoder 942 is a circuit for specifying a column to be accessed. The row driver 923 has the function of selecting the row specified by the row decoder 941. The column driver 924 has the function of writing data to the memory cells 950, reading data from the memory cells 950, and retaining the read data.

[0328] The input circuit 925 has a function of holding a signal WDA. The data held by the input circuit 925 is output to the column driver 924. The output data of the input circuit 925 is data (Din) to be written to the memory cell 950. The data (Dout) read from the memory cell 950 by the column driver 924 is output to the output circuit 926. The output circuit 926 has a function of holding Dout. In addition, the output circuit 926 has a function of outputting Dout to the outside of the semiconductor device 900. The data output from the output circuit 926 is a signal RDA.

[0329] The PSW 931 has a function of controlling the supply of VDD to the peripheral circuit 915. The PSW 932 has a function of controlling the supply of VHM to the row driver 923. In this example, the high power supply voltage of the semiconductor device 900 is VDD, and the low power supply voltage is GND (ground potential). VHM is a high power supply voltage used to set the word line to a high level and is higher than VDD. The on / off of the PSW 931 is controlled by a signal PON1, and the on / off of the PSW 932 is controlled by a signal PON2. In FIG. 21 , the number of power domains to which VDD is supplied in the peripheral circuit 915 is one, but multiple domains may also be used. In this case, a power switch may be provided for each power domain.

[0330] 22A to 22H, other examples of memory cell configurations that can be applied to the memory cell 950 will be described.

[0331] In the following, when two components are described as being connected, this includes being electrically connected via a circuit element (such as a transistor, a switch, a diode, or a resistor). Electrical connection means that a current can flow between the two components. Note that when two components are connected via a switch or a transistor, this is also included in the term "electrical connection," because a current can flow when these are in the on state.

[0332] 22A shows an example of a circuit configuration of a DRAM memory cell. In this specification and the like, a DRAM using an OS transistor is referred to as a DOSRAM (Dynamic Oxide Semiconductor Random Access Memory). The memory cell 951 includes a transistor M1 and a capacitor CA.

[0333] The transistor M1 may have a front gate (sometimes simply referred to as a gate) and a back gate. In this case, the back gate may be connected to a wiring that supplies a constant potential or a signal, or the front gate and the back gate may be connected to each other.

[0334] A first terminal of the transistor M1 is connected to a first terminal of the capacitance element CA, a second terminal of the transistor M1 is connected to the wiring BIL, and a gate of the transistor M1 is connected to the wiring WOL. The second terminal of the capacitance element CA is connected to the wiring CAL.

[0335] The wiring BIL functions as a bit line, and the wiring WOL functions as a word line. The wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitance element CA. When writing and reading data, it is preferable to apply a low-level potential (sometimes referred to as a reference potential) to the wiring CAL.

[0336] Data is written and read by applying a high-level potential to the wiring WOL, turning on the transistor M1, and bringing the wiring BIL and the first terminal of the capacitor CA into a conductive state (a state in which current can flow).

[0337] Furthermore, the memory cell that can be used for the memory cell 950 is not limited to the memory cell 951, and the circuit configuration can be changed. For example, the memory cell 952 shown in FIG. 22B may have a configuration. The memory cell 952 is an example in which the memory cell 952 does not include a capacitor CA and a wiring CAL. The first terminal of the transistor M1 is in an electrically floating state.

[0338] In the memory cell 952, the potential written through the transistor M1 is held in a capacitance (also referred to as a parasitic capacitance) between the first terminal and the gate, which is indicated by a dashed line. With this configuration, the configuration of the memory cell can be significantly simplified.

[0339] Note that an OS transistor is preferably used as the transistor M1. An OS transistor has a characteristic of extremely low off-state current. By using an OS transistor as the transistor M1, the leakage current of the transistor M1 can be significantly reduced. That is, written data can be held by the transistor M1 for a long time, so that the frequency of refreshing the memory cell can be reduced. Alternatively, the refresh operation of the memory cell can be eliminated. Furthermore, because the leakage current is extremely low, multilevel data or analog data can be held in the memory cell 951 and the memory cell 952.

[0340] 22C shows an example circuit configuration of a gain cell type memory cell having two transistors and one capacitor. The memory cell 953 includes a transistor M2, a transistor M3, and a capacitor CB. In this specification and the like, a storage device having a gain cell type memory cell in which the transistor M2 is an OS transistor is referred to as a nonvolatile oxide semiconductor RAM (NOSRAM).

[0341] The first terminal of transistor M2 is connected to the first terminal of capacitance element CB, the second terminal of transistor M2 is connected to wiring WBL, and the gate of transistor M2 is connected to wiring WOL. The second terminal of capacitance element CB is connected to wiring CAL. The first terminal of transistor M3 is connected to wiring RBL, the second terminal of transistor M3 is connected to wiring SL, and the gate of transistor M3 is connected to the first terminal of capacitance element CB.

[0342] The wiring WBL functions as a write bit line, the wiring RBL functions as a read bit line, and the wiring WOL functions as a word line. The wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitance element CB. When writing data, while retaining data, and when reading data, it is preferable to apply a low-level potential (sometimes referred to as a reference potential) to the wiring CAL.

[0343] Data is written by applying a high-level potential to the wiring WOL, turning on the transistor M2, and establishing electrical continuity between the wiring WBL and the first terminal of the capacitor CB. Specifically, when the transistor M2 is on, a potential corresponding to the information to be recorded is applied to the wiring WBL, and the potential is written to the first terminal of the capacitor CB and the gate of the transistor M3. Then, a low-level potential is applied to the wiring WOL, turning off the transistor M2, thereby maintaining the potential of the first terminal of the capacitor CB and the potential of the gate of the transistor M3.

[0344] Data is read by applying a predetermined potential to the wiring SL. The current flowing between the source and drain of the transistor M3 and the potential of the first terminal of the transistor M3 are determined by the potential of the gate of the transistor M3 and the potential of the second terminal of the transistor M3. Therefore, the potential held in the first terminal of the capacitor CB (or the gate of the transistor M3) can be read by reading the potential of the wiring RBL connected to the first terminal of the transistor M3. In other words, information written in this memory cell can be read from the potential held in the first terminal of the capacitor CB (or the gate of the transistor M3).

[0345] Alternatively, for example, the wiring WBL and the wiring RBL may be combined into a single wiring BIL. An example circuit configuration of such a memory cell is shown in FIG. 22D. The memory cell 954 is configured such that the wiring WBL and the wiring RBL of the memory cell 953 are combined into a single wiring BIL, and the second terminal of the transistor M2 and the first terminal of the transistor M3 are connected to the wiring BIL. In other words, the memory cell 954 is configured to operate as a write bit line and a read bit line using a single wiring BIL.

[0346] 22E is an example in which the capacitor element CB and the wiring CAL in the memory cell 953 are omitted. Also, the memory cell 956 in Fig. 22F is an example in which the capacitor element CB and the wiring CAL in the memory cell 954 are omitted. With such a configuration, the integration degree of the memory cells can be increased.

[0347] Note that it is preferable to use an OS transistor for at least the transistor M2, and particularly for the transistors M2 and M3.

[0348] Since the OS transistor has an extremely low off-state current, written data can be held by the transistor M2 for a long time, which reduces the frequency of refreshing the memory cell. Alternatively, the refresh operation of the memory cell can be eliminated. Furthermore, since the leakage current is extremely low, multilevel data or analog data can be held in the memory cell 953, the memory cell 954, the memory cell 955, and the memory cell 956.

[0349] The memory cell 953, the memory cell 954, the memory cell 955, and the memory cell 956, in which an OS transistor is used as the transistor M2, are one embodiment of an NOSRAM.

[0350] Note that a Si transistor may be used as the transistor M3. The Si transistor can increase the field effect mobility and can also be used as a p-channel transistor, thereby increasing the degree of freedom in circuit design.

[0351] When an OS transistor is used as the transistor M3, the memory cell can be configured using only n-channel transistors.

[0352] 22G shows a three-transistor, one-capacitor gain cell type memory cell 957. The memory cell 957 has transistors M4 to M6 and a capacitor CC.

[0353] The first terminal of transistor M4 is connected to the first terminal of capacitor CC, the second terminal of transistor M4 is connected to wiring BIL, and the gate of transistor M4 is connected to wiring WOL. The second terminal of capacitor CC is connected to the first terminal of transistor M5 and wiring GNDL. The second terminal of transistor M5 is connected to the first terminal of transistor M6, and the gate of transistor M5 is connected to the first terminal of capacitor CC. The second terminal of transistor M6 is connected to wiring BIL, and the gate of transistor M6 is connected to wiring RWL.

[0354] The wiring BIL functions as a bit line, the wiring WOL functions as a write word line, and the wiring RWL functions as a read word line. The wiring GNDL is a wiring that applies a low-level potential.

[0355] Data is written by applying a high-level potential to the wiring WOL, turning on the transistor M4, and establishing electrical continuity between the wiring BIL and the first terminal of the capacitor CC. Specifically, when the transistor M4 is on, a potential corresponding to the information to be recorded is applied to the wiring BIL, and the potential is written to the first terminal of the capacitor CC and the gate of the transistor M5. Then, a low-level potential is applied to the wiring WOL, turning off the transistor M4, thereby maintaining the potential of the first terminal of the capacitor CC and the potential of the gate of the transistor M5.

[0356] Data is read by precharging the wiring BIL to a predetermined potential, then electrically floating the wiring BIL, and applying a high-level potential to the wiring RWL. Because the wiring RWL is at a high-level potential, the transistor M6 is turned on, and the wiring BIL and the second terminal of the transistor M5 are electrically connected. At this time, the potential of the wiring BIL is applied to the second terminal of the transistor M5. The potential of the second terminal of the transistor M5 and the potential of the wiring BIL change depending on the potential held in the first terminal of the capacitor CC (or the gate of the transistor M5). By reading the potential of the wiring BIL, the potential held in the first terminal of the capacitor CC (or the gate of the transistor M5) can be read. In other words, information written in this memory cell can be read from the potential held in the first terminal of the capacitor CC (or the gate of the transistor M5).

[0357] Note that at least the transistor M4 is preferably an OS transistor.

[0358] Note that Si transistors may be used as the transistors M5 and M6. As described above, Si transistors may have higher field-effect mobility than OS transistors depending on the crystalline state of silicon used in the semiconductor layer.

[0359] When OS transistors are used as the transistors M5 and M6, the memory cell can be configured using only n-channel transistors.

[0360] 22H shows an example of a static random access memory (SRAM) using an OS transistor. In this specification and the like, an SRAM using an OS transistor is referred to as an oxide semiconductor SRAM (OS-SRAM). Note that a memory cell 958 shown in FIG. 22H is a memory cell of an SRAM capable of backing up data.

[0361] The memory cell 958 includes transistors M7 to M10, transistors MS1 to MS4, and capacitors CD1 and CD2. Note that the transistors MS1 and MS2 are p-channel transistors, and the transistors MS3 and MS4 are n-channel transistors.

[0362] A first terminal of transistor M7 is connected to wiring BIL, and a second terminal of transistor M7 is connected to a first terminal of transistor MS1, a first terminal of transistor MS3, the gate of transistor MS2, the gate of transistor MS4, and a first terminal of transistor M10. The gate of transistor M7 is connected to wiring WOL. A first terminal of transistor M8 is connected to wiring BILB, and a second terminal of transistor M8 is connected to a first terminal of transistor MS2, the first terminal of transistor MS4, the gate of transistor MS1, the gate of transistor MS3, and a first terminal of transistor M9. The gate of transistor M8 is connected to wiring WOL.

[0363] A second terminal of the transistor MS1 is connected to the wiring VDL. A second terminal of the transistor MS2 is connected to the wiring VDL. A second terminal of the transistor MS3 is connected to the wiring GNDL. A second terminal of the transistor MS4 is connected to the wiring GNDL.

[0364] A second terminal of the transistor M9 is connected to a first terminal of the capacitor CD1, and a gate of the transistor M9 is connected to the wiring BRL. A second terminal of the transistor M10 is connected to a first terminal of the capacitor CD2, and a gate of the transistor M10 is connected to the wiring BRL.

[0365] A second terminal of the capacitance element CD1 is connected to the wiring GNDL, and a second terminal of the capacitance element CD2 is connected to the wiring GNDL.

[0366] The wirings BIL and BILB function as bit lines, the wiring WOL functions as a word line, and the wiring BRL is a wiring that controls the on / off states of the transistors M9 and M10.

[0367] The wiring VDL is a wiring that applies a high-level potential, and the wiring GNDL is a wiring that applies a low-level potential.

[0368] Data is written by applying a high-level potential to the wiring WOL and a high-level potential to the wiring BRL. Specifically, when the transistor M10 is on, a potential corresponding to information to be written is applied to the wiring BIL, and the potential is written to the second terminal of the transistor M10.

[0369] Since the memory cell 958 includes an inverter loop formed by the transistors MS1 and MS2, an inverted signal of the data signal corresponding to the potential is input to the second terminal of the transistor M8. Because the transistor M8 is on, the potential applied to the wiring BIL, i.e., the inverted signal of the signal input to the wiring BIL, is output to the wiring BILB. Because the transistors M9 and M10 are on, the potentials of the second terminals of the transistors M7 and M8 are held in the first terminals of the capacitors CD2 and CD1, respectively. Then, a low-level potential is applied to the wiring WOL and a low-level potential is applied to the wiring BRL to turn off the transistors M7 to M10, thereby holding the potentials of the first terminals of the capacitors CD1 and CD2.

[0370] The following describes how data is read. First, the wirings BIL and BILB are precharged to a predetermined potential. Next, a high-level potential is applied to the wiring WOL, and a high-level potential is applied to the wiring BRL. At this time, the potential of the first terminal of the capacitor CD1 is refreshed by the inverter loop of the memory cell 958 and output to the wiring BILB. The potential of the first terminal of the capacitor CD2 is refreshed by the inverter loop of the memory cell 958 and output to the wiring BIL. Since the potentials of the wirings BIL and BILB change from the precharged potentials to the potentials of the first terminals of the capacitor CD2 and the first terminals of the capacitor CD1, respectively, the potential held in the memory cell can be read from the potential of the wiring BIL or the wiring BILB.

[0371] Note that OS transistors are preferably used as the transistors M7 to M10. This allows written data to be held by the transistors M7 to M10 for a long time, which reduces the frequency of refreshing the memory cells. Alternatively, refreshing the memory cells can be eliminated.

[0372] Note that Si transistors may be used as the transistors MS1 to MS4.

[0373] The driver circuit 910 and memory array 920 of the semiconductor device 900 may be provided on the same plane. Alternatively, as shown in FIG. 23A, the driver circuit 910 and memory array 920 may be provided overlapping each other. By providing the driver circuit 910 and memory array 920 overlapping each other, the signal propagation distance can be shortened. Alternatively, as shown in FIG. 23B, the memory array 920 may be provided in multiple layers on the driver circuit 910.

[0374] Next, an example of a processing unit that can include a semiconductor device such as the memory device will be described.

[0375] 24 shows a block diagram of the arithmetic device 960. The arithmetic device 960 shown in FIG. 24 can be applied to, for example, a CPU (Central Processing Unit). The arithmetic device 960 can also be applied to processors such as a GPU (Graphics Processing Unit), a TPU (Tensor Processing Unit), and an NPU (Neural Processing Unit) that have a larger number (several tens to several hundreds) of processor cores capable of parallel processing than a CPU.

[0376] The arithmetic device 960 shown in FIG. 24 has an ALU 991 (ALU: Arithmetic logic unit, arithmetic circuit), an ALU controller 992, an instruction decoder 993, an interrupt controller 994, a timing controller 995, a register 996, a register controller 997, a bus interface 998, a cache 999, and a cache interface 989 on a substrate 990. The substrate 990 may be a semiconductor substrate, an SOI substrate, a glass substrate, or the like. It may also have a rewritable ROM and a ROM interface. The cache 999 and the cache interface 989 may also be provided on separate chips.

[0377] The cache 999 is connected to a main memory provided on a separate chip via a cache interface 989. The cache interface 989 has a function of supplying part of the data held in the main memory to the cache 999. The cache interface 989 also has a function of outputting part of the data held in the cache 999 to the ALU 991, register 996, etc. via the bus interface 998.

[0378] As will be described later, a memory array 920 can be provided by stacking it on the arithmetic unit 960. The memory array 920 can be used as a cache. In this case, the cache interface 989 may have a function of supplying data held in the memory array 920 to the cache 999. In this case, it is preferable that a drive circuit 910 be included as part of the cache interface 989.

[0379] It is also possible to use only the memory array 920 as a cache without providing the cache 999 .

[0380] The arithmetic device 960 shown in FIG. 24 is merely an example of a simplified configuration, and actual arithmetic devices 960 have a wide variety of configurations depending on their applications. For example, it is preferable to use a configuration including the arithmetic device 960 shown in FIG. 24 as one core, and to include multiple such cores, each of which operates in parallel, in a so-called multi-core configuration. The greater the number of cores, the higher the computational performance. The greater the number of cores, for example, two, preferably four, more preferably eight, even more preferably twelve, and even more preferably sixteen or more. Furthermore, when extremely high computational performance is required, such as for server applications, a multi-core configuration having 16 or more, preferably 32 or more, and even more preferably 64 or more cores is preferable. Furthermore, the number of bits that the arithmetic device 960 can handle via its internal computation circuit, data bus, etc. can be, for example, 8 bits, 16 bits, 32 bits, 64 bits, etc.

[0381] An instruction input to the arithmetic unit 960 via the bus interface 998 is input to the instruction decoder 993, decoded, and then input to the ALU controller 992, interrupt controller 994, register controller 997, and timing controller 995.

[0382] The ALU controller 992, interrupt controller 994, register controller 997, and timing controller 995 perform various controls based on the decoded instructions. Specifically, the ALU controller 992 generates signals for controlling the operation of the ALU 991. Furthermore, the interrupt controller 994 determines and processes interrupt requests from external input / output devices, peripheral circuits, etc. based on their priority, mask status, etc. while the arithmetic unit 960 is executing a program. The register controller 997 generates addresses for registers 996 and performs read and write operations on the registers 996 depending on the state of the arithmetic unit 960.

[0383] Furthermore, the timing controller 995 generates signals that control the timing of the operations of the ALU 991, the ALU controller 992, the instruction decoder 993, the interrupt controller 994, and the register controller 997. For example, the timing controller 995 includes an internal clock generation unit that generates an internal clock signal based on a reference clock signal, and supplies the internal clock signal to the various circuits described above.

[0384] 24, the register controller 997 selects the holding operation of the register 996 in accordance with an instruction from the ALU 991. That is, it selects whether the memory cells of the register 996 will hold data using flip-flops or using capacitive elements. If holding data using flip-flops is selected, a power supply voltage is supplied to the memory cells in the register 996. If holding data using capacitive elements is selected, the data is rewritten to the capacitive elements, and the supply of power supply voltage to the memory cells in the register 996 can be stopped.

[0385] The memory array 920 and the arithmetic unit 960 can be provided overlapping each other. Perspective views of a semiconductor device 970A are shown in Figures 25A and 25B. The semiconductor device 970A has a layer 930 on which memory arrays are provided above the arithmetic unit 960. The layer 930 is provided with memory arrays 920L1, 920L2, and 920L3. The arithmetic unit 960 and each memory array have overlapping regions. To make the configuration of the semiconductor device 970A easier to understand, the arithmetic unit 960 and the layer 930 are shown separately in Figure 25B.

[0386] By stacking the layer 930 having the memory array and the arithmetic unit 960, the connection distance between them can be shortened, thereby increasing the communication speed between them. In addition, the short connection distance reduces power consumption.

[0387] As a method for stacking the layer 930 having a memory array and the arithmetic device 960, a method (also called monolithic stacking) in which the layer 930 having a memory array is stacked directly on the arithmetic device 960 may be used, or a method in which the arithmetic device 960 and the layer 930 are formed on different substrates, and the two substrates are bonded together and connected using a through-via or conductive film bonding technology (such as Cu-Cu bonding) may be used. The former method does not require consideration of misalignment during bonding, and therefore can not only reduce the chip size but also reduce manufacturing costs.

[0388] Here, the arithmetic unit 960 does not have a cache 999, and the memory arrays 920L1, 920L2, and 920L3 provided in the layer 930 can each be used as a cache. In this case, for example, the memory array 920L1 can be used as an L1 cache (also referred to as a level 1 cache), the memory array 920L2 can be used as an L2 cache (also referred to as a level 2 cache), and the memory array 920L3 can be used as an L3 cache (also referred to as a level 3 cache). Of the three memory arrays, the memory array 920L3 has the largest capacity and the lowest access frequency. Furthermore, the memory array 920L1 has the smallest capacity and the highest access frequency.

[0389] When the cache 999 provided in the arithmetic unit 960 is used as an L1 cache, each memory array provided in the layer 930 can be used as a lower-level cache or a main memory. The main memory has a larger capacity than the cache and is accessed less frequently.

[0390] 25B, a driving circuit 910L1, a driving circuit 910L2, and a driving circuit 910L3 are provided. The driving circuit 910L1 is connected to the memory array 920L1 via a connection electrode 940L1. Similarly, the driving circuit 910L2 is connected to the memory array 920L2 via a connection electrode 940L2, and the driving circuit 910L3 is connected to the memory array 920L3 via a connection electrode 940L3.

[0391] Although the number of memory arrays functioning as caches is three in this example, the number may be one or two, or four or more.

[0392] When the memory array 920L1 is used as a cache, the driver circuit 910L1 may function as part of the cache interface 989, or may be configured to be connected to the cache interface 989. Similarly, the driver circuits 910L2 and 910L3 may also function as part of the cache interface 989, or may be configured to be connected thereto.

[0393] Whether the memory array 920 is made to function as a cache or as a main memory is determined by a control circuit 912 included in each drive circuit 910. The control circuit 912 can cause some of the memory cells 950 included in the semiconductor device 900 to function as RAM based on a signal supplied from the arithmetic device 960.

[0394] The semiconductor device 900 can cause some of the memory cells 950 to function as a cache and the other memory cells to function as a main memory. That is, the semiconductor device 900 can function as both a cache and a main memory. The semiconductor device 900 according to one embodiment of the present invention can function as, for example, a universal memory.

[0395] Furthermore, a layer 930 having one memory array 920 may be provided over the arithmetic device 960. Figure 26A shows a perspective view of a semiconductor device 970B.

[0396] In the semiconductor device 970B, one memory array 920 can be divided into multiple areas, each of which can be used for a different function. Fig. 26A shows an example in which area L1 is used as an L1 cache, area L2 is used as an L2 cache, and area L3 is used as an L3 cache.

[0397] Furthermore, in the semiconductor device 970B, the capacity of each of the areas L1 to L3 can be changed depending on the situation. For example, if it is desired to increase the capacity of the L1 cache, this can be achieved by increasing the area of ​​the area L1. This configuration can improve the efficiency of calculation processing and increase the processing speed.

[0398] Also, multiple memory arrays may be stacked. Figure 26B shows a perspective view of a semiconductor device 970C.

[0399] The semiconductor device 970C includes a layer 930L1 having a memory array 920L1, a layer 930L2 having a memory array 920L2 on top of that, and a layer 930L3 having a memory array 920L3 on top of that. The memory array 920L1, which is physically closest to the arithmetic unit 960, can be used as a higher-level cache, and the memory array 920L3, which is farthest, can be used as a lower-level cache or main memory. This configuration allows the capacity of each memory array to be increased, thereby further improving processing power.

[0400] At least a part of the configuration examples exemplified in this embodiment and the corresponding drawings can be combined as appropriate with other configuration examples or drawings.

[0401] Embodiment 5 In this embodiment, an application example of a semiconductor device of one embodiment of the present invention will be described. The semiconductor device of one embodiment of the present invention can be used for, for example, electronic components, electronic devices, mainframes, space equipment, and data centers (also referred to as data centers (DCs)). Electronic components, electronic devices, mainframes, space equipment, and data centers using the semiconductor device of one embodiment of the present invention are effective in achieving high performance, such as low power consumption.

[0402] [Electronic Component] FIG. 27A shows a perspective view of a substrate (mounting substrate 704) on which electronic component 700 is mounted. Electronic component 700 shown in FIG. 27A has semiconductor device 710 inside mold 711. FIG. 27A omits some parts to show the interior of electronic component 700. Electronic component 700 has lands 712 on the outside of mold 711. Lands 712 are electrically connected to electrode pads 713, and electrode pads 713 are electrically connected to semiconductor device 710 via wires 714. Electronic component 700 is mounted on, for example, a printed circuit board 702. A plurality of such electronic components are combined and electrically connected on printed circuit board 702 to complete mounting substrate 704.

[0403] The semiconductor device 710 also includes a drive circuit layer 715 and a memory layer 716. The memory layer 716 has a configuration in which multiple memory cell arrays are stacked. The stacked configuration of the drive circuit layer 715 and the memory layer 716 can be a monolithic stacked configuration. In a monolithic stacked configuration, the layers can be connected without using through-electrode technology such as a TSV (Through Silicon Via) or a bonding technology such as Cu-Cu direct bonding. By configuring the drive circuit layer 715 and the memory layer 716 as a monolithic stacked configuration, for example, a so-called on-chip memory configuration can be achieved in which the memory is formed directly on the processor. The on-chip memory configuration enables the operation of the interface between the processor and the memory to be faster.

[0404] Furthermore, by configuring an on-chip memory, the size of the connection wiring can be reduced compared to technologies that use through electrodes such as TSVs, and the number of connection pins can be increased. Increasing the number of connection pins enables parallel operation, which makes it possible to improve the memory bandwidth (also called memory bandwidth).

[0405] It is also preferable that the memory cell arrays included in the memory layer 716 are formed using OS transistors and the memory cell arrays are monolithically stacked. By forming the memory cell arrays in a monolithic stacked structure, one or both of the memory bandwidth and the memory access latency can be improved. Note that the bandwidth is the amount of data transferred per unit time, and the access latency is the time from access to the start of data exchange. Note that when Si transistors are used for the memory layer 716, it is more difficult to form a monolithic stacked structure than when OS transistors are used. Therefore, it can be said that OS transistors have a superior structure to Si transistors in a monolithic stacked structure.

[0406] The semiconductor device 710 may also be referred to as a die. In this specification, a die refers to a chip piece obtained by forming a circuit pattern on, for example, a disk-shaped substrate (also called a wafer) and dicing it into cubes during the semiconductor chip manufacturing process. Examples of semiconductor materials that can be used for the die include silicon (Si), silicon carbide (SiC), and gallium nitride (GaN). For example, a die obtained from a silicon substrate (also called a silicon wafer) may be called a silicon die.

[0407] 27B shows a perspective view of an electronic component 730. The electronic component 730 is an example of a SiP (System in Package) or an MCM (Multi-Chip Module). The electronic component 730 has an interposer 731 provided on a package substrate 732 (printed circuit board), and a semiconductor device 735 and a plurality of semiconductor devices 710 provided on the interposer 731.

[0408] The electronic component 730 shows an example in which the semiconductor device 710 is used as a high bandwidth memory (HBM). The semiconductor device 735 can be used in an integrated circuit such as a central processing unit (CPU), a graphics processing unit (GPU), a neural processing unit (NPU), or a field programmable gate array (FPGA).

[0409] For example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate can be used as the package substrate 732. For example, a silicon interposer or a resin interposer can be used as the interposer 731.

[0410] The interposer 731 has multiple wirings and functions to electrically connect multiple integrated circuits with different terminal pitches. The multiple wirings are provided in a single layer or multiple layers. The interposer 731 also functions to electrically connect the integrated circuits provided on the interposer 731 to electrodes provided on the package substrate 732. For these reasons, the interposer is sometimes called a "rewiring substrate" or "intermediate substrate." In addition, through electrodes may be provided in the interposer 731, and the integrated circuits and the package substrate 732 may be electrically connected using the through electrodes. In addition, with a silicon interposer, a TSV may also be used as the through electrode.

[0411] In an HBM, many wirings must be connected to achieve a wide memory bandwidth. Therefore, the interposer on which the HBM is mounted must have fine and high-density wiring. Therefore, it is preferable to use a silicon interposer for the interposer on which the HBM is mounted.

[0412] Furthermore, in SiPs, MCMs, and the like that use silicon interposers, a decrease in reliability due to differences in the coefficient of expansion between the integrated circuit and the interposer is unlikely to occur. Furthermore, because the silicon interposer has a highly flat surface, poor connection between the integrated circuit mounted on the silicon interposer and the silicon interposer is unlikely to occur. In particular, it is preferable to use silicon interposers in 2.5D packages (2.5-dimensional packaging) in which multiple integrated circuits are arranged horizontally on an interposer.

[0413] On the other hand, when electrically connecting multiple integrated circuits with different terminal pitches using a silicon interposer, a TSV, or the like, a space is required, such as the width of the terminal pitch. Therefore, when attempting to reduce the size of the electronic component 730, the width of the terminal pitch becomes an issue, and it may be difficult to provide the many wirings necessary to achieve a wide memory bandwidth. Therefore, as described above, a monolithic stacked structure using OS transistors is preferable. A composite structure may be formed by combining a memory cell array stacked using TSVs and a monolithically stacked memory cell array.

[0414] A heat sink (heat dissipation plate) may be provided overlapping the electronic component 730. When a heat sink is provided, it is preferable to align the height of an integrated circuit provided on the interposer 731. For example, in the electronic component 730 shown in this embodiment, it is preferable to align the height of the semiconductor device 710 and the height of the semiconductor device 735.

[0415] Electrodes 733 may be provided on the bottom of package substrate 732 in order to mount electronic component 730 on another substrate. FIG. 27B shows an example in which electrodes 733 are formed with solder balls. By providing solder balls in a matrix on the bottom of package substrate 732, BGA (Ball Grid Array) mounting can be achieved. Electrodes 733 may also be formed with conductive pins. By providing conductive pins in a matrix on the bottom of package substrate 732, PGA (Pin Grid Array) mounting can be achieved.

[0416] The electronic component 730 can be mounted on other substrates using various mounting methods, including, but not limited to, BGA and PGA, such as a staggered pin grid array (SPGA), a land grid array (LGA), a quad flat package (QFP), a quad flat J-leaded package (QFJ), and a quad flat non-leaded package (QFN).

[0417] 28A shows a perspective view of a mainframe computer 5600. The mainframe computer 5600 has a rack 5610 housing a plurality of rack-mounted computers 5620. The mainframe computer 5600 may also be called a supercomputer.

[0418] 28B shows a perspective view of an example of a computer 5620. The computer 5620 has a motherboard 5630. The motherboard 5630 is provided with a plurality of slots 5631 and a plurality of connection terminals. A PC card 5621 is inserted into the slot 5631. In addition, the PC card 5621 has connection terminals 5623, 5624, and 5625, which are each connected to the motherboard 5630.

[0419] Fig. 28C shows an example of a PC card 5621. The PC card 5621 is a processing board equipped with, for example, a CPU, a GPU, a storage device, etc. The PC card 5621 has a board 5622 and connection terminals 5623, 5624, 5625, electronic components 5626, 5627, 5628, and 5629 mounted on the board 5622. Note that Fig. 28C illustrates components other than electronic components 5626, 5627, and 5628.

[0420] The connection terminal 5629 has a shape that allows it to be inserted into a slot 5631 of the motherboard 5630, and the connection terminal 5629 functions as an interface for connecting the PC card 5621 and the motherboard 5630. An example of the standard for the connection terminal 5629 is PCIe.

[0421] The connection terminals 5623, 5624, and 5625 can be, for example, interfaces for supplying power to the PC card 5621, inputting signals, etc. Furthermore, they can be, for example, interfaces for outputting signals calculated by the PC card 5621. Examples of standards for the connection terminals 5623, 5624, and 5625 include USB (Universal Serial Bus), SATA (Serial ATA), and SCSI (Small Computer System Interface). Furthermore, when a video signal is output from the connection terminals 5623, 5624, and 5625, examples of the respective standards include HDMI (registered trademark).

[0422] The electronic component 5626 has a terminal (not shown) for inputting and outputting signals, and the electronic component 5626 and the board 5622 can be electrically connected by inserting the terminal into a socket (not shown) provided on the board 5622.

[0423] The electronic components 5627 and 5628 have multiple terminals, and can be mounted on wiring provided on the board 5622 by, for example, reflow soldering the terminals. Examples of the electronic component 5627 include an FPGA, a GPU, and a CPU. For example, the electronic component 730 can be used as the electronic component 5627. For example, the electronic component 5628 includes a storage device. For example, the electronic component 700 can be used as the electronic component 5628.

[0424] The mainframe computer 5600 can also function as a parallel computer. By using the mainframe computer 5600 as a parallel computer, it is possible to perform large-scale calculations required for, for example, learning and inference in artificial intelligence.

[0425] [Space Equipment] The semiconductor device of one embodiment of the present invention can be suitably used in space equipment.

[0426] A semiconductor device according to one embodiment of the present invention includes an OS transistor. The OS transistor exhibits small changes in electrical characteristics due to radiation exposure. That is, the OS transistor has high radiation resistance and can be suitably used in an environment where radiation may be incident. For example, the OS transistor can be suitably used in outer space. Specifically, the OS transistor can be used as a transistor for a semiconductor device provided in a space shuttle, an artificial satellite, or a space probe. Examples of radiation include X-rays and neutrons. Note that outer space refers to an altitude of 100 km or higher, but the outer space described in this specification may include one or more of the thermosphere, the mesosphere, and the stratosphere.

[0427] Fig. 29A shows an artificial satellite 6800 as an example of space equipment. The artificial satellite 6800 has a body 6801, a solar panel 6802, an antenna 6803, a secondary battery 6805, and a control device 6807. Note that Fig. 29A shows a planet 6804 in space as an example.

[0428] 29A , a battery management system (also referred to as a BMS) or a battery control circuit may be provided for the secondary battery 6805. The use of an OS transistor in the battery management system or the battery control circuit is preferable because it consumes low power and has high reliability even in space.

[0429] Furthermore, outer space is an environment with radiation levels 100 times higher than on Earth. Examples of radiation include electromagnetic waves (electromagnetic radiation) such as X-rays and gamma rays, and particle radiation such as alpha rays, beta rays, neutron rays, proton rays, heavy ion rays, and meson rays.

[0430] When sunlight is irradiated onto the solar panel 6802, the power required for the operation of the satellite 6800 is generated. However, for example, in a situation where sunlight is not irradiated onto the solar panel or where the amount of sunlight irradiating the solar panel is small, the generated power is small. Therefore, there is a possibility that the power required for the operation of the satellite 6800 will not be generated. In order to operate the satellite 6800 even in a situation where the generated power is small, it is preferable to provide a secondary battery 6805 on the satellite 6800. Note that the solar panel may be called a solar cell module.

[0431] The satellite 6800 can generate a signal. The signal is transmitted via an antenna 6803, and can be received by, for example, a receiver installed on the ground or another satellite. By receiving the signal transmitted by the satellite 6800, the position of the receiver that received the signal can be determined. As described above, the satellite 6800 can constitute a satellite positioning system.

[0432] The control device 6807 has a function of controlling the satellite 6800. The control device 6807 is configured using, for example, one or more selected from a CPU, a GPU, and a storage device. Note that a semiconductor device including an OS transistor, which is one embodiment of the present invention, is preferably used for the control device 6807. The OS transistor has smaller fluctuations in electrical characteristics due to radiation exposure than a Si transistor. That is, the OS transistor has high reliability even in an environment where radiation may be incident, and can be preferably used.

[0433] The artificial satellite 6800 can also be configured to include a sensor. For example, by including a visible light sensor, the artificial satellite 6800 can have the function of detecting sunlight reflected from an object on the ground. Alternatively, by including a thermal infrared sensor, the artificial satellite 6800 can have the function of detecting thermal infrared rays emitted from the earth's surface. As described above, the artificial satellite 6800 can function as, for example, an earth observation satellite.

[0434] Although an artificial satellite is described as an example of space equipment in this embodiment, the present invention is not limited thereto. For example, the semiconductor device of one embodiment of the present invention can be suitably used in space equipment such as a spaceship, a space capsule, or a space probe.

[0435] As described above, OS transistors have excellent advantages over Si transistors, such as the ability to achieve a wide memory bandwidth and high radiation resistance.

[0436] [Data Center] The semiconductor device of one embodiment of the present invention can be suitably used in a storage system applied to, for example, a data center. Data centers are required to perform long-term management of data, such as ensuring data immutability. Managing long-term data requires larger buildings, such as installing storage and servers for storing huge amounts of data, ensuring a stable power supply for data retention, or ensuring cooling equipment required for data retention.

[0437] By using the semiconductor device of one embodiment of the present invention in a storage system applied to a data center, it is possible to reduce the power required to store data and the size of the semiconductor device that stores data. Therefore, it is possible to reduce the size of the storage system, the size of the power supply for storing data, the scale of the cooling equipment, and the like. Therefore, it is possible to reduce the space required for the data center.

[0438] Furthermore, the semiconductor device of one embodiment of the present invention has low power consumption, which allows heat generation from the circuit to be reduced. Therefore, adverse effects of the heat generation on the circuit itself, peripheral circuits, and modules can be reduced. Furthermore, by using the semiconductor device of one embodiment of the present invention, a data center that operates stably even in a high-temperature environment can be realized. Therefore, the reliability of the data center can be improved.

[0439] Fig. 29B shows a storage system applicable to a data center. The storage system 6000 shown in Fig. 29B has multiple servers 6001sb as hosts 6001 (illustrated as Host Computers). It also has multiple storage devices 6003md as storage 6003 (illustrated as Storage). The host 6001 and storage 6003 are shown connected via a storage area network 6004 (illustrated as SAN: Storage Area Network) and a storage control circuit 6002 (illustrated as Storage Controller).

[0440] The host 6001 corresponds to a computer that accesses data stored in the storage 6003. The hosts 6001 may be connected to each other via a network.

[0441] Although the storage 6003 uses flash memory to reduce the data access speed, i.e., the time required to store and output data, this time is significantly longer than the time required for DRAM, which can be used as cache memory within the storage. In order to solve the problem of the long access speed of the storage 6003, a storage system typically provides cache memory within the storage to reduce the time required to store and output data.

[0442] The cache memory described above is used in the storage control circuit 6002 and the storage 6003. Data exchanged between the host 6001 and the storage 6003 is stored in the cache memory in the storage control circuit 6002 and the storage 6003, and then output to the host 6001 or the storage 6003.

[0443] By using OS transistors as transistors for storing data in the cache memory and holding a potential corresponding to the data, the frequency of refresh operations can be reduced, and power consumption can be reduced.

[0444] Note that the application of the semiconductor device of one embodiment of the present invention to any one or more selected from electronic components, electronic devices, mainframe computers, space equipment, and data centers is expected to have an effect of reducing power consumption. Therefore, while energy demand is expected to increase with the improvement in performance or high integration of semiconductor devices, the use of the semiconductor device of one embodiment of the present invention can contribute to the reduction of carbon dioxide (CO ２ Furthermore, the semiconductor device of one embodiment of the present invention is effective as a countermeasure against global warming because it consumes low power.

[0445] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0446] In this example, the sheet resistance of the oxide film was evaluated.

[0447] [Sample Preparation] First, a thermally oxidized silicon film having a thickness of about 100 nm was formed on a silicon wafer, and an In-Sn oxide film (ITO) having a thickness of about 20 nm was formed thereon by sputtering.

[0448] Subsequently, a heat treatment was performed under a reduced pressure atmosphere. Here, a sample was prepared without heat treatment, and three types of samples were prepared by heat treatment under the following conditions: the first was at 200°C for 5 minutes, the second was at 250°C for 5 minutes, and the third was at 250°C for 10 minutes.

[0449] Next, the sheet resistance of each of the four samples was measured at 25 locations within the substrate for each sample.

[0450] The results of measuring the sheet resistance are shown in Figure 30. It can be seen that the sheet resistance of the heat-treated sample is reduced compared to the sample that was not heat-treated. Furthermore, the sheet resistance of the sample that was heat-treated at 250°C for 10 minutes was reduced by more than one order of magnitude compared to the other conditions, and the variation was also significantly reduced.

[0451] From the above results, it was confirmed that the electrical resistance of an In-Sn oxide film formed by sputtering can be significantly reduced by subjecting it to a heat treatment at an appropriate temperature and time in a reduced pressure atmosphere.

[0452] In this example, a transistor according to one embodiment of the present invention was fabricated, and cross-sectional observation and evaluation of electrical characteristics were performed. Here, a transistor based on the transistor 10a described in Structural Example 2 of Embodiment 1 was fabricated. The transistor was fabricated by the fabrication method described in the fabrication method example of Embodiment 1.

[0453] [Preparation of Samples] In this example, three samples (sample 1A, sample 1B, and sample 1C) were prepared under different conditions.

[0454] The lower electrodes were fabricated by depositing a titanium nitride (TiNx) film approximately 5 nm thick, a tungsten (W) film approximately 40 nm thick, and an In-Sn oxide (ITO) film approximately 20 nm thick on the substrate. The titanium nitride and tungsten films were formed by CVD, and the In-Sn oxide film was formed by sputtering.

[0455] Next, a silicon nitride film (SiNx) with a thickness of about 5 nm, a silicon nitride film with a thickness of about 10 nm, a silicon oxide film (SiOx) with a thickness of about 80 nm, and a silicon nitride film with a thickness of about 10 nm were used to cover the lower electrode as spacer insulating layers. The first silicon nitride film was deposited by the ALD method, and the others were deposited by the sputtering method.

[0456] A tungsten film and an In—Sn oxide film having a thickness of approximately 10 nm were formed as upper electrodes on the spacer insulating layer by sputtering. The thickness of the tungsten film was 30 nm in Samples 1A and 1B, and 15 nm in Sample 1C.

[0457] Subsequently, an opening reaching the lower electrode was formed in the upper electrode and the spacer insulating layer. Thereafter, only Sample 1A was subjected to a heat treatment at 250° C. for 1 hour in a reduced pressure atmosphere.

[0458] Next, an indium oxide (InOx) film with a thickness of approximately 5 nm was formed as a semiconductor layer by the ALD method, followed by a heat treatment at 250°C for 5 minutes in a reduced pressure atmosphere, followed by a sputtering method to form an In-Ga-Zn oxide (IGZO) film with a thickness of approximately 5 nm. The semiconductor layer and upper electrode were then processed. The IGZO film was formed using an oxide sputtering target with an atomic ratio of metal elements of In:Ga:Zn = 1:1:1.2.

[0459] Subsequently, as gate insulating layers, an aluminum oxide film having a thickness of about 1 nm, a silicon oxide film having a thickness of about 2 nm, a hafnium oxide film having a thickness of about 2 nm, and a silicon nitride film having a thickness of about 1 nm were each formed by ALD.

[0460] Subsequently, a titanium nitride film (TiNx) having a thickness of about 5 nm and a tungsten film having a thickness of about 20 nm were formed as gate electrodes by CVD, and then processed to obtain gate electrodes.

[0461] Through the above steps, samples 1A, 1B, and 1C were obtained.

[0462] [Cross-Section Observation] The cross-sections of the prepared Samples 1A and 1B were observed by the STEM method.

[0463] Fig. 31 is a cross-sectional observation image of Sample 1B. Fig. 31 is a cross-sectional image of a transistor in which the spacer opening diameter is 60 nm (design value). It can be seen that the semiconductor layer (InOx) is formed with a uniform thickness along the sidewall of the spacer from the upper electrode to the lower electrode.

[0464] 32 and 33 are cross-sectional observation images of Sample 1A. Figures 32 and 33 are cross-sectional images of a transistor in which the spacer opening diameter is 28 nm (design value). It can be seen that no grain boundaries are observed in the semiconductor layer from the lower electrode to the upper electrode.

[0465] 32 shows electron diffraction images obtained at one point on the bottom electrode and four points on the semiconductor layer in a cross section perpendicular to the substrate, and the crystal orientation determined based on the images. As shown in FIG. 32, it can be confirmed that the crystal orientation

[110] is consistent at the four points on the bottom electrode and the semiconductor layer. It can also be confirmed that the crystals in the semiconductor layer are oriented in a counterclockwise direction from the bottom electrode toward the top electrode, with the Z direction (perpendicular to the substrate) as the axis.

[0466] It was also confirmed that the lower electrode also had a crystalline region, just like the semiconductor layer. Furthermore, it was confirmed that the crystal orientation of the lower electrode and the crystal orientation of the region of the semiconductor layer near the lower electrode were consistent with each other. This suggests that the crystal growth of the semiconductor layer progressed while reflecting the crystal orientation of the lower electrode.

[0467] Figure 33 shows a cross section parallel to the substrate of a transistor different from that shown in Figure 32. Similar to Figure 32, Figure 33 shows electron beam diffraction images and crystal orientations at five positions in the semiconductor layer. As shown in Figure 33, it can be seen that no grain boundaries are observed in the semiconductor layer. Furthermore, since the crystal orientations at the five points in the semiconductor layer are completely consistent, it can be said that the observed region has a circular single crystal structure.

[0468] [Evaluation of Electrical Characteristics] Subsequently, the Id-Vg characteristics were measured for Sample 1A, Sample 1B, and Sample 1C. The source-drain current was measured when the drain voltage was set to 0.1 V or 1.2 V and the gate voltage was swept from −4 V to 4 V. The measured transistors had an aperture diameter of 60 nm (design value), and nine measurements were performed.

[0469] 34A, 34B, and 34C show the Id-Vg characteristics of Samples 1A, 1B, and 1C, respectively. All of the samples exhibit good electrical characteristics with little variation.

[0470] Sample 1B had higher field-effect mobility and on-current than Sample 1C. This is presumably because Sample 1B had a thicker tungsten film used in the upper electrode, resulting in lower electrical resistance. Sample 1B had an average field-effect mobility (Vd = 0.1 V) of 57.8 cm ２ / Vs.

[0471] Furthermore, Sample 1A had higher field-effect mobility and on-state current than Sample 1B. Sample 1A had an average field-effect mobility (Vd = 0.1 V) of 70.4 cm ２ This is presumably due to the effect of the heat treatment after the formation of the openings significantly reducing the electrical resistance of the In-Sn oxide film used for the upper and lower electrodes.

[0472] Next, the reliability evaluation results for the transistor of Sample 1A are shown. The reliability evaluation was performed using a GBT (Gate Bias Temperature) stress test. The test was performed at a stage temperature of 125°C, a gate voltage of 1.98V, and drain and source voltages of 0V. During the test, the Id-Vg characteristics were measured at regular intervals. The drain voltage was set to 0.1V or 1.2V, and the source-drain current was measured when the gate voltage was swept from -1.8V to 1.8V. The test was performed on two transistors (n1 and n2) of Sample 1A.

[0473] The evaluation results are shown in Figure 35A. In Figure 35A, the horizontal axis represents test time, and the vertical axis represents the amount of change in the shift voltage Vsh. The shift voltage Vsh was measured when the tangent to the point where the slope of the curve in the Id-Vg characteristic was maximum was Id = 1 pA (1 x 10 −１２ 35A) and 35B) show the Id-Vg characteristics of transistors n1 and n2 before and after the stress test, respectively. As shown in FIGS. 35A, 35B, and 35C, it was confirmed that the transistor of Sample 1A fabricated in this example had extremely high reliability.

[0474] In this example, a transistor according to one embodiment of the present invention was fabricated, and cross-sectional observation and evaluation of electrical characteristics were performed. Here, a transistor having a slit-shaped opening was fabricated.

[0475] [Preparation of Samples] In this example, two samples (sample 2A and sample 2B) were prepared under different conditions.

[0476] A titanium nitride film with a thickness of approximately 5 nm, a tungsten film with a thickness of approximately 40 nm, and an oxide film with a thickness of approximately 20 nm were formed on a substrate as the bottom electrode, and these were then processed to obtain the bottom electrode. Sample 2A used an In—Sn oxide film as the oxide film, and Sample 2B used an In—Sn oxide film containing silicon (ITSO). The titanium nitride film and tungsten film were formed by CVD, and the oxide film was formed by sputtering.

[0477] Next, a silicon nitride film (SiNx) with a thickness of about 5 nm, a silicon nitride film with a thickness of about 10 nm, a silicon oxide film (SiOx) with a thickness of about 80 nm, and a silicon nitride film with a thickness of about 10 nm were used to cover the lower electrode as spacer insulating layers. The first silicon nitride film was deposited by the ALD method, and the others were deposited by the sputtering method.

[0478] A tungsten film having a thickness of approximately 15 nm and an oxide film having a thickness of approximately 15 nm were formed as upper electrodes on the spacer insulating layer by sputtering. Sample 2A used an In—Sn oxide film as the oxide film, and Sample 2B used an In—Sn oxide film containing silicon.

[0479] Subsequently, a slit reaching the lower electrode was formed in the upper electrode and the spacer insulating layer.

[0480] Next, an indium oxide (InOx) film with a thickness of approximately 5 nm was formed as a semiconductor layer by the ALD method, followed by a heat treatment at 250°C for 5 minutes in a reduced pressure atmosphere, followed by a sputtering method to form an In-Ga-Zn oxide (IGZO) film with a thickness of approximately 5 nm. The semiconductor layer and upper electrode were then processed. The IGZO film was formed using an oxide sputtering target with an atomic ratio of metal elements of In:Ga:Zn = 1:1:1.2.

[0481] Subsequently, as gate insulating layers, an aluminum oxide film having a thickness of about 1 nm, a silicon oxide film having a thickness of about 2 nm, a hafnium oxide film having a thickness of about 2 nm, and a silicon nitride film having a thickness of about 1 nm were each formed by ALD.

[0482] Subsequently, a titanium nitride film (TiNx) having a thickness of about 5 nm and a tungsten film having a thickness of about 20 nm were formed as gate electrodes by CVD, and then processed to obtain gate electrodes.

[0483] Through the above steps, samples 2A and 2B were obtained.

[0484] [Cross-Section Observation] The cross-section of the fabricated sample 2A was observed by the STEM method.

[0485] A cross-sectional observation image is shown in Figure 36. Figure 36 is a cross-sectional view of a transistor with a slit width of 60 nm (design value). It can be seen that the sidewalls of the slits have a tapered shape, and that a semiconductor layer of uniform thickness is formed along the sidewalls of the slits.

[0486] [Evaluation of Electrical Characteristics] Subsequently, the Id-Vg characteristics of Sample 2A and Sample 2B were evaluated. The measurement conditions were the same as those of the above-described example. The measured transistors had a slit width of 60 nm (design value), and nine measurements were performed.

[0487] 37A and 37B show the Id-Vg characteristics of Samples 2A and 2B, respectively. Both samples exhibit good electrical characteristics with little variation.

[0488] Sample 2A had higher field-effect mobility and on-current than Sample 2B. Sample 2A had an average field-effect mobility (Vd = 0.1 V) of 53.1 cm ２ / Vs. This is presumably due to the effect of significantly reducing the electrical resistance by using low-resistance In—Sn oxide for the upper and lower electrodes. Furthermore, according to Examples 1 and 2, it is presumed that a further improvement in field-effect mobility can be expected by the heat treatment after the slit formation.

[0489] Next, the reliability of the transistors of Sample 2A was evaluated by the same method as in Example 2. Here, the reliability of two transistors (n3 and n4) of Sample 2A was measured.

[0490] 38A shows the amount of change in the shift voltage Vsh, and FIGS. 38B and 38C show the Id-Vg characteristics before and after the stress test. As shown in FIGS. 38A, 38B, and 38C, it was confirmed that the transistor of Sample 2A fabricated in this example had high reliability.

[0491] 10: transistor, 10a: transistor, 10b: transistor, 10d: transistor, 10e: transistor, 11: insulating layer, 15: memory cell, 20: slit, 20a: opening, 20b: opening, 20d: opening, 20e: opening, 21: semiconductor layer, 21f: semiconductor film, 21x: region, 22: insulating layer, 23: conductive layer, 23a: conductive layer, 23b: conductive layer, 24: conductive layer, 24a: conductive layer, 24b: conductive layer, 25: conductive layer, 25a: conductive layer, 25af: conductive film, 25b: conductive layer, 25bf: conductive film, 25o: oxide, 26: conductive layer, 27: plug, 2 9: conductive layer, 30: memory cell, 30a: memory cell, 31: conductive layer, 34: conductive layer, 40: slit, 41: insulating layer, 41a: insulating layer, 41b: insulating layer, 41c: insulating layer, 42: insulating layer, 43: insulating layer, 44: insulating layer, 45: insulating layer, 48: insulating layer, 50: capacitor, 51: conductive layer, 52: conductive layer, 53: insulating layer, 55: insulating layer, 55a: insulating layer, 55b: insulating layer, 55c: insulating layer, 56: insulating layer, 60[1,1]: memory unit, 60[2,4]: memory unit, 60[a,b]: memory unit, 60: memory unit, 61: conductive layer, 62 : Conductive layer, 63: Conductive layer, 65: Insulating layer, 70: Transistor, 71: Semiconductor layer, 72: Insulating layer, 73: Conductive layer, 74a: Conductive layer, 74b: Conductive layer, 75a: Conductive layer, 75b: Conductive layer, 80[1]: Layer, 80[2]: Layer, 80[m]: Layer, 80: Layer, 90: Transistor, 91: Substrate, 92: Semiconductor region, 93: Insulating layer, 94: Conductive layer, 95a: Low resistance region, 95b: Low resistance region, 700: Electronic component, 702: Printed circuit board, 704: Mounting board, 710: Semiconductor device, 711: Mold, 712: Land, 713: Electrode pad, 714: Wire, 715 : Drive circuit layer, 716: Memory layer, 730: Electronic component, 731: Interposer, 732: Package substrate, 733: Electrode, 735: Semiconductor device, 900: Semiconductor device, 910: Drive circuit, 911: Peripheral circuit, 912: Control circuit, 915: Peripheral circuit, 920: Memory array, 923: Row driver, 924: Column driver, 925: Input circuit, 926: Output circuit, 927: Sense amplifier, 928: Voltage generation circuit, 930: Layer, 931: PSW, 932: PSW, 941: Row decoder, 942: Column decoder, 950: Memory cell, 951: Memory cell,952: memory cell, 953: memory cell, 954: memory cell, 955: memory cell, 956: memory cell, 957: memory cell, 958: memory cell, 960: arithmetic unit, 970A: semiconductor device, 970B: semiconductor device, 970C: semiconductor device, 989: cache interface, 990: substrate, 991: ALU, 992: ALU controller, 993: instruction decoder, 994: interrupt controller, 995: timing controller, 996: register, 997: register controller, 998: bus interface, 999: cache, 5600: mainframe computer, 5 610: rack, 5620: computer, 5621: PC card, 5622: board, 5623: connection terminal, 5624: connection terminal, 5625: connection terminal, 5626: electronic component, 5627: electronic component, 5628: electronic component, 5629: connection terminal, 5630: motherboard, 5631: slot, 6000: storage system, 6001: host, 6001sb: server, 6002: storage control circuit, 6003: storage, 6003md: storage device, 6800: artificial satellite, 6801: aircraft, 6802: solar panel, 6803: antenna, 6804: planet, 6805: secondary battery, 6807: control device,

Claims

a first conductive layer, a second conductive layer, a third conductive layer, a semiconductor layer, a first insulating layer, and a second insulating layer; the first insulating layer has a portion located on the first conductive layer and has an opening reaching the first conductive layer; the second conductive layer has a portion located on the first insulating layer; the semiconductor layer has a portion in contact with an upper surface and a side surface of the second conductive layer, a portion in contact with a side surface of the first insulating layer within the opening, and a portion in contact with an upper surface of the first conductive layer within the opening; the second insulating layer covers the semiconductor layer in the opening; the third conductive layer covers the second insulating layer in the opening; a portion of the first conductive layer in contact with the semiconductor layer and a portion of the second conductive layer in contact with the semiconductor layer each contain an oxide containing indium; the semiconductor layer contains indium oxide, and in a cross section parallel to the height direction of the opening, no grain boundary is observed in a portion in contact with the first insulating layer, and the crystal orientations of two or more portions in contact with the first insulating layer are the same; Semiconductor device. 　 a first conductive layer, a second conductive layer, a third conductive layer, a semiconductor layer, a first insulating layer, and a second insulating layer; the first insulating layer has a portion located on the first conductive layer and has an opening reaching the first conductive layer; the second conductive layer has a portion located on the first insulating layer; the semiconductor layer has a portion in contact with an upper surface and a side surface of the second conductive layer, a portion in contact with a side surface of the first insulating layer within the opening, and a portion in contact with an upper surface of the first conductive layer within the opening; the second insulating layer covers the semiconductor layer in the opening; the third conductive layer covers the second insulating layer in the opening; a portion of the first conductive layer in contact with the semiconductor layer and a portion of the second conductive layer in contact with the semiconductor layer each contain an oxide containing indium; the semiconductor layer contains indium oxide, and in a cross section parallel to the height direction of the opening, no grain boundaries are observed in a portion in contact with the first insulating layer, and the semiconductor layer has a region in which crystals are twisted around a specific crystal orientation without grain boundaries in the portion in contact with the first insulating layer. Semiconductor device. 　 In claim 1 or claim 2, the semiconductor layer has an annular shape in a cross section perpendicular to a height direction of the opening, and the crystal orientations of two or more portions in the cross section are the same; Semiconductor device. 　 In claim 1 or claim 2, the first conductive layer and the second conductive layer each have a first layer and a second layer on the first layer; the second layer has an upper surface in contact with the semiconductor layer, the second layer contains indium and tin and has a polycrystalline structure or a single crystalline structure; Semiconductor device. 　 In claim 1 or claim 2, the first conductive layer has crystallinity; the semiconductor layer has a region whose crystal orientation coincides with that of a crystalline region of the first conductive layer; Semiconductor device. 　 forming a first insulating layer on the first conductive layer; forming a second conductive layer on the first insulating layer; forming an opening in the first insulating layer that reaches the first conductive layer; Heat treatment is carried out, forming a semiconductor film in contact with an upper surface of the second conductive layer, a side surface of the first insulating layer within the opening, and an upper surface of the first conductive layer within the opening; the first conductive layer and the second conductive layer contain a metal oxide containing indium; the semiconductor film contains indium oxide; A method for manufacturing a semiconductor device. In claim 6, The heat treatment is carried out in a reduced pressure atmosphere at a temperature of 100° C. or higher and 400° C. or lower. A method for manufacturing a semiconductor device. 　 In claim 6, the first conductive layer and the second conductive layer each contain indium and tin, and have a polycrystalline structure or a single crystalline structure after the heat treatment; A method for manufacturing a semiconductor device.

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