Multilayer ceramic capacitor

Abstract

The present invention provides a multilayer ceramic capacitor in which measures against steps are taken to improve the reliability of the multilayer ceramic capacitor and in which the withstand voltage characteristics can be improved. A multilayer ceramic capacitor (1) includes: a first auxiliary dielectric layer (211), in which the grain size of the dielectric is larger than the grain size thereof in a central dielectric part and which is disposed between a first internal electrode (31) and a second end surface (E2); and a second auxiliary dielectric layer (212), in which the grain size of the dielectric is larger than the grain size thereof in the central dielectric part and which is disposed between a second internal electrode (32) and a first end surface (E1). The first auxiliary dielectric layer (211) is disposed so as to surround a longitudinal end (151) on the second end surface (E2) side of the first internal electrode (31). The second auxiliary dielectric layer (212) is disposed so as to surround a longitudinal end (152) on the first end surface (E1) side of the second internal electrode (32).

Description

Multilayer ceramic capacitors

[0001] The present invention relates to a multilayer ceramic capacitor.

[0002] Multilayer ceramic capacitors, which include a laminate in which dielectric layers and internal electrodes are alternately stacked, and external electrodes electrically connected to the internal electrodes, are one type of electronic component and are used in a wide range of fields, such as communications, IoT, automobiles, and medicine. In recent years, there has been an urgent need to further improve the reliability of multilayer ceramic capacitors and to increase their capacitance per size.

[0003] Patent Document 1 discloses a technique for improving reliability against structural defects by reducing steps in a laminate caused by the presence or absence of internal electrodes.

[0004] Japanese Patent Application Laid-Open No. 2022-141958

[0005] However, with conventional technology, it is difficult to realize a multilayer ceramic capacitor that can improve reliability against structural defects by reducing the steps and improve voltage resistance reliability by reducing short circuits between internal electrodes. In particular, it is difficult to suppress electric field concentration at the longitudinal center and the lateral center of the internal electrodes and to suppress the occurrence of short circuits due to this electric field concentration.

[0006] SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a multilayer ceramic capacitor capable of improving the withstand voltage characteristics while taking measures against steps and improving the reliability of the multilayer ceramic capacitor.

[0007] The multilayer ceramic capacitor of the present invention comprises a laminate including a plurality of laminated dielectric layers and a plurality of first and second internal electrodes, the laminate having first and second main surfaces facing each other in a lamination direction of the dielectric layers and the first and second internal electrodes, a first side surface facing each other in a width direction perpendicular to the lamination direction, and a first end surface facing each other in a length direction perpendicular to the lamination direction and the width direction; a first external electrode electrically connected to the first internal electrodes and provided on a surface of the laminate; and a second external electrode electrically connected to the second internal electrodes and provided on the surface of the laminate, the first internal electrode being extended to the first end surface and the second internal electrode being extended to the When the portion sandwiched between the first internal electrode and the second internal electrode at the center in the longitudinal direction, the center in the width direction, and the center in the stacking direction is defined as a central dielectric portion, the dielectric layer has a first auxiliary dielectric layer having a larger dielectric grain size than the central dielectric portion and arranged between the first internal electrode and the second end face, and a second auxiliary dielectric layer having a larger dielectric grain size than the central dielectric portion and arranged between the second internal electrode and the first end face, the first auxiliary dielectric layer is arranged around the end of the first internal electrode on the second end face side, and the second auxiliary dielectric layer is arranged around the end of the second internal electrode on the first end face side.

[0008] According to the present invention, it is possible to provide a multilayer ceramic capacitor capable of improving the withstand voltage characteristics while taking measures against steps and improving the reliability of the multilayer ceramic capacitor.

[0009] FIG. 1 is an external perspective view of a multilayer ceramic capacitor according to an embodiment of the present disclosure. FIG. 2 is a cross-sectional view taken along line 101-101 in FIG. 1. FIG. 3 is a cross-sectional view taken along line 102-102 in FIG. 1. FIG. 4 is a cross-sectional view taken along line 103-103 in FIG. 1. FIG. 5 is a cross-sectional view taken along line 103-103 in FIG. 1 at the center of the width direction of a multilayer ceramic capacitor according to an embodiment of the present disclosure, in the length direction and lamination direction. FIG. 6 is a cross-sectional view taken along line 103-103 in FIG. 1 at the center of the length direction of a multilayer ceramic capacitor according to an embodiment of the present disclosure, in the width direction and lamination direction. FIG. 7 is a diagram showing the state in which an internal electrode paste and an auxiliary dielectric paste are applied to ceramic green sheets. FIG. 8 is a diagram showing evaluation results of examples and comparative examples.

[0010] First Embodiment A multilayer ceramic capacitor 1 according to one embodiment of the present disclosure will be described with reference to the drawings. Fig. 1 is a perspective view of the appearance of the multilayer ceramic capacitor 1 according to the first embodiment of the present disclosure.

[0011] As shown in Fig. 1, the multilayer ceramic capacitor 1 has a substantially rectangular parallelepiped shape. The multilayer ceramic capacitor 1 includes a laminate 2 and external electrodes. The laminate 2 has a substantially rectangular parallelepiped shape. The external electrodes are disposed at opposite ends of the laminate 2 and spaced apart from each other. The external electrodes include a first external electrode 41 and a second external electrode 42.

[0012] The directions in the multilayer ceramic capacitor 1 and the laminate 2 will now be described. Arrow T in FIG. 1 indicates the stacking direction T. Arrow L indicates the length direction L. The length direction L is a direction perpendicular to the stacking direction T. Arrow W indicates the width direction W. The width direction W is a direction perpendicular to the stacking direction T and the length direction L. The stacking direction T, the length direction L, and the width direction W are perpendicular to one another. The arrows T, L, and W indicate the same directions as those described above in figures other than FIG. 1 as well.

[0013] One of the pair of external electrodes is provided at one end in the longitudinal direction L of the laminate 2. The other of the pair of external electrodes is provided at the other end in the longitudinal direction L of the laminate 2. One of the external electrodes is a first external electrode 41. The other external electrode is a second external electrode 42.

[0014] (Laminate) The laminate 2 will be described with reference to Figs. 2, 3, and 4 in addition to Fig. 1. Fig. 2 is a cross-sectional view taken along line 101-101 of Fig. 1. Fig. 3 is a cross-sectional view taken along line 102-102 of Fig. 1. Fig. 4 is a cross-sectional view taken along line 103-103 of Fig. 1. The laminate 2 includes dielectric layers 20 and internal electrodes. The internal electrodes include a first internal electrode 31 and a second internal electrode 32. As shown in Fig. 2, a plurality of dielectric layers 20 and a plurality of internal electrodes are stacked on top of each other.

[0015] The two surfaces of the laminate 2 facing each other in the stacking direction T are called the first main surface M1 and the second main surface M2. The two surfaces of the laminate 2 facing each other in the width direction W are called the first side surface S1 and the second side surface S2. The two surfaces of the laminate 2 facing each other in the length direction L are called the first end surface E1 and the second end surface E2.

[0016] The portion where two surfaces of the laminate 2 intersect is called a ridge portion. The portion where three surfaces of the laminate 2 intersect is called a corner portion. The corners and ridge portions are preferably rounded. Some or all of the main surface, side surface, and end surface may have irregularities formed thereon.

[0017] (Dielectric Layer) The total number of dielectric layers 20 included in the laminate 2 is preferably 15 or more and 1800 or less.

[0018] An example of the ceramic material contained in the dielectric layer 20 is BaTiO ３ , CaTiO ３ , SrTiO ３ , CaZrO ３ The ceramic material may be a dielectric ceramic containing these elements as its main components, to which secondary components such as Mg, Mn, Si, Ni, Fe, Cr, Co, etc., or compounds containing these elements, have been added.

[0019] The dimensions of the laminate 2 are not particularly limited. The preferred dimension of the laminate 2 in the length direction L is 0.2 mm or more and 10 mm or less. The preferred dimension of the laminate 2 in the width direction W is 0.1 mm or more and 10 mm or less. The preferred dimension of the laminate 2 in the stacking direction T is 0.1 mm or more and 5 mm or less.

[0020] (Internal Electrodes) The internal electrodes will now be described. The internal electrodes include a plurality of first internal electrodes 31 and a plurality of second internal electrodes 32. The first internal electrodes 31 are internal electrodes exposed at the first end face E1. The second internal electrodes 32 are internal electrodes exposed at the second end face E2. FIG. 3 shows the first internal electrodes 31.

[0021] The first internal electrode 31 has a first opposing portion 33 and a first lead portion 35. The first opposing portion 33 is a portion that faces the second internal electrode 32. The first lead portion 35 is a portion that is led from the first opposing portion 33 to the first end face E1. The second internal electrode 32 has a second opposing portion 34 and a second lead portion 36. The second opposing portion 34 is a portion that faces the first internal electrode 31. The second lead portion 36 is a portion that is led from the second opposing portion 34 to the second end face E2.

[0022] The shape of the first facing portion 33 is not particularly limited. The shape of the first facing portion 33 is preferably rectangular. The corners of the first facing portion 33 may be rounded or may be obliquely formed (tapered). The shape of the second facing portion 34 is not particularly limited. The shape of the second facing portion 34 is preferably rectangular. The corners of the second facing portion 34 may be rounded or may be obliquely formed (tapered). The taper may have a slope in thickness toward the end.

[0023] The shape of the first lead portion 35 is not particularly limited. The shape of the first lead portion 35 is preferably rectangular. The corners of the first lead portion 35 may be rounded or may be obliquely formed (tapered). The shape of the second lead portion 36 is not particularly limited. The shape of the second lead portion 36 is preferably rectangular. The corners of the second lead portion 36 may be rounded or may be obliquely formed (tapered). The taper may have a slope in thickness toward the end.

[0024] The corner portions are portions located at the corners of the outer shape of the internal electrode when the internal electrode is viewed in cross section in the length direction L and width direction W.

[0025] The width in the width direction W of the first opposing portion 33 and the width in the width direction W of the first lead-out portion 35 may be the same, or one of the widths may be narrower. The width in the width direction W of the second opposing portion 34 and the width in the width direction W of the second lead-out portion 36 may be the same, or one of the widths may be narrower.

[0026] The first internal electrode 31 and the second internal electrode 32 can be made of an appropriate conductive material, for example, a metal such as Ni, Cu, Ag, Pd, or Au, or an alloy containing at least one of these metals, such as an Ag-Pd alloy.

[0027] The thickness of each of the first internal electrode 31 and the second internal electrode 32 is preferably, for example, about 0.2 μm or more and 2.0 μm or less.

[0028] The total number of the first internal electrodes 31 and the second internal electrodes 32 is preferably 15 or more and 1700 or less.

[0029] (Outer Layer Portion and Inner Layer Portion) The following describes the division of the laminate 2 in the stacking direction T. As shown in Figures 2 and 4, the laminate 2 can be divided into an inner layer portion 10, a first outer layer portion 12, and a second outer layer portion 13 in the stacking direction T.

[0030] The inner layer portion 10 is a portion of the laminate 2 included in the stacking direction T between the position of the internal electrode closest to the first main surface M1 and the position of the internal electrode closest to the second main surface M2.

[0031] The first outer layer portion 12 is a portion of the laminate 2 that is included between the first main surface M1 and the position of the internal electrode that is closest to the first main surface M1 in the stacking direction T. The first outer layer portion 12 is a portion of the laminate 2 that is included between the inner layer portion 10 and the first main surface M1.

[0032] The second outer layer portion 13 is a portion of the laminate 2 that is included between the second main surface M2 and the position of the internal electrode closest to the second main surface M2 in the stacking direction T. The second outer layer portion 13 is a portion of the laminate 2 that is included between the inner layer portion 10 and the second main surface M2. The first outer layer portion 12 and the second outer layer portion 13 are collectively referred to as the outer layer portions.

[0033] (Core Portion and W Gap) The division of the laminate 2 in the width direction W will be described. As shown in Figures 3 and 4, the laminate 2 can be divided into a core portion 25, a first W gap 15, and a second W gap 16 in the width direction W. The core portion 25 is the portion of the laminate 2 in which internal electrodes are provided in the width direction W. The first W gap 15 is the portion of the laminate 2 between the core portion 25 and the first side surface S1. The second W gap 16 is the portion of the laminate 2 between the core portion 25 and the second side surface S2. The first W gap 15 and the second W gap 16 are collectively referred to as the W gap. No internal electrodes are provided in the W gap. Only a dielectric layer is provided in the W gap. The W gap is also called a side gap.

[0034] (Effective Portion and Ineffective Portion) The division of the core portion 25 in the stacking direction T will be described. As shown in FIG. 4 , the core portion 25 can be divided into an effective portion 26, a first ineffective portion 28, and a second ineffective portion 29 in the stacking direction T. The effective portion 26 is the portion of the core portion 25 in which the first internal electrode 31 or the second internal electrode 32 is arranged in the stacking direction T. The first ineffective portion 28 is the portion of the core portion 25 between the effective portion 26 and the first main surface M1 in the stacking direction T. The second ineffective portion 29 is the portion of the core portion 25 between the effective portion 26 and the second main surface M2 in the stacking direction T. The first ineffective portion 28 and the second ineffective portion 29 are collectively referred to as the ineffective portion. No internal electrodes are provided in the ineffective portions. Only a dielectric layer is provided in the ineffective portions.

[0035] (Opposite Electrode Portion) The portion where the first internal electrode 31 and the second internal electrode 32 overlap is called the opposite electrode portion 38. The opposite electrode portion 38 is the portion where the first opposite portion 33 and the second opposite portion 34 overlap. In the multilayer ceramic capacitor 1, capacitance is formed when the opposite portions of the internal electrodes face each other with the dielectric layer interposed therebetween. In other words, capacitance is formed in the opposite electrode portion 38. This capacitance allows the multilayer ceramic capacitor 1 to exhibit capacitor characteristics.

[0036] (L Gap) The L gap will be described with reference to Figures 2 and 3. In the laminate 2, the portion located between the opposing electrode portion 38 and the end face and including the lead portion of either the first internal electrode 31 or the second internal electrode 32 is called the L gap. The L gap includes a first L gap 18 and a second L gap 19. The first L gap 18 is located between the opposing electrode portion 38 and the first end face E1 and is a portion including the first lead portion 35. The second L gap 19 is located between the opposing electrode portion 38 and the second end face E2 and is a portion including the second lead portion 36.

[0037] (External Electrodes) The external electrodes include a first external electrode 41 and a second external electrode 42. The first external electrode 41 is connected to the first internal electrode 31 and is disposed on the first end face E1. The first external electrode 41 may also be disposed on a portion of the first main face M1 and a portion of the second main face M2, as well as a portion of the first side face S1 and a portion of the second side face S2. In this embodiment, the first external electrode 41 extends from the first end face E1 to a portion of the first main face M1 and a portion of the second main face M2, as well as a portion of the first side face S1 and a portion of the second side face S2.

[0038] The second external electrode 42 is connected to the second internal electrode 32 and is disposed on the second end face E2. The second external electrode 42 may also be disposed on a portion of the first principal surface M1 and a portion of the second principal surface M2, as well as a portion of the first side surface S1 and a portion of the second side surface S2. In this embodiment, the second external electrode 42 extends from the second end face E2 to a portion of the first principal surface M1 and a portion of the second principal surface M2, as well as a portion of the first side surface S1 and a portion of the second side surface S2.

[0039] The external electrodes preferably have a base electrode layer and a plating layer. The base electrode layer included in the first external electrode 41 is referred to as a first base electrode layer 51. The base electrode layer included in the second external electrode 42 is referred to as a second base electrode layer 52.

[0040] The plating layer included in the first external electrode 41 is referred to as a first plating layer 61. The plating layer included in the second external electrode 42 is referred to as a second plating layer 62.

[0041] (Base Electrode Layer) The base electrode layer includes at least one selected from a baking layer, a conductive resin layer, a thin film layer, and the like. A case where the base electrode layer is a baking layer will be described. The baking layer includes a glass component and a metal. The glass component of the baking layer includes at least one element selected from, for example, B, Si, Ba, Mg, Al, and Li. The metal of the baking layer includes at least one element selected from, for example, Cu, Ni, Ag, Pd, an Ag—Pd alloy, and Au.

[0042] The baked layer may be formed in multiple layers. The baked layer is formed by applying a conductive paste containing a glass component and a metal to the laminate and baking it. The baked layer may be baked simultaneously with the firing of the internal electrodes and the dielectric layers. It may also be baked after the firing of the internal electrodes. The baked layer may also be baked after the firing of the internal electrodes and the dielectric layers. When the baked layer is baked simultaneously with the firing of the internal electrodes and the dielectric layers, it is preferable to form the baked layer by adding a dielectric material instead of the glass component.

[0043] The thickness in the length direction L at the center position in the stacking direction T of the baked layer located on the first end face E1 and the second end face E2 is preferably, for example, about 3 μm or more and 160 μm or less.

[0044] Furthermore, when a baked layer is provided as a base electrode layer on a portion of the first main surface M1 and a portion of the second main surface M2, and on a portion of the first side surface S1 and a portion of the second side surface S2, it is preferable that the thickness in the stacking direction T at the center position in the length direction L of the base electrode layer located on the first main surface M1 and the second main surface M2, and the first side surface S1 and the second side surface S2 is, for example, approximately 3 μm or more and 40 μm or less.

[0045] (Plating Layer) The first plating layer 61 is disposed so as to cover the first base electrode layer 51. The second plating layer 62 is disposed so as to cover the second base electrode layer 52.

[0046] The material constituting the plating layer includes, for example, at least one selected from Cu, Ni, Sn, Ag, Pd, an Ag—Pd alloy, and Au.

[0047] The plating layer may be formed of multiple layers. In this embodiment, the first plating layer 61 and the second plating layer 62 each include two plating layers. When the plating layer has a two-layer structure, preferably, one layer is a Ni plating layer and the other layer is a Sn plating layer. The Ni plating layer included in the first plating layer 61 is referred to as a first Ni plating layer 63. The Ni plating layer included in the second plating layer 62 is referred to as a second Ni plating layer 64. The Sn plating layer included in the first plating layer 61 is referred to as a first Sn plating layer 65. The Sn plating layer included in the second plating layer 62 is referred to as a second Sn plating layer 66.

[0048] The Ni plating layer prevents the base electrode layer from being eroded by solder when mounting the ceramic electronic component. The Sn plating layer improves the wettability of the solder when mounting the ceramic electronic component, thereby facilitating mounting. For these reasons, it is preferable that the plating layers in contact with the base electrode layer are Ni plating layer and Sn plating layer, in that order. The plating layers may be three or more layers. The main component of the plating layer may be a metal species other than Ni and Sn.

[0049] The preferred thickness of each plating layer is 2 μm or more and 15 μm or less.

[0050] (When no base electrode layer is provided) The external electrode may be formed only with a plating layer, without providing a base electrode layer. A structure in which only a plating layer is provided without providing a base electrode layer will be described. The external electrode does not have a base electrode layer, and the plating layer is formed directly on the surface of the laminate. The internal electrode is directly electrically connected to the plating layer. When the external electrode does not include a base electrode layer, a catalyst may be disposed on the surface of the laminate as a pre-plating treatment, and then the plating layer may be formed.

[0051] The plating layer preferably includes a lower-layer plating electrode formed on the surface of the laminate and an upper-layer plating electrode formed on the surface of the lower-layer plating electrode. The lower-layer plating electrode and the upper-layer plating electrode preferably include at least one metal selected from, for example, Cu, Ni, Sn, Pb, Au, Ag, Pd, Bi, and Zn, or an alloy containing such a metal. The lower-layer plating electrode is preferably formed using Ni, which has solder barrier properties. The upper-layer plating electrode is preferably formed using Sn or Au, which have good solder wettability.

[0052] When the first and second internal electrodes are formed using Ni, the lower-layer plated electrode is preferably formed using Cu, which has good bonding properties with Ni. The upper-layer plated electrode may be formed as needed, and the external electrode may be composed of only the lower-layer plated electrode. The upper-layer plated electrode may be the outermost layer of the plated layer, or another plated electrode may be formed on the surface of the upper-layer plated electrode.

[0053] The thickness of each plating layer disposed without a base electrode layer is preferably 1 μm or more and 15 μm or less. The plating layer preferably does not contain glass. The metal content per unit volume of the plating layer is preferably 99% by volume or more.

[0054] (Dimensions of Multilayer Ceramic Capacitor) The size of the multilayer ceramic capacitor 1 including the laminate 2 and the external electrodes will be described. It will be described as "length direction (L) dimension x width direction (W) dimension x stacking direction (T) dimension." Possible dimensions of the multilayer ceramic capacitor 1 include, for example, "1.6 mm x 0.8 mm x 0.8 mm," "1.0 mm x 0.5 mm x 0.5 mm," "0.6 mm x 0.3 mm x 0.3 mm," "0.4 mm x 0.2 mm x 0.2 mm," and "0.2 mm x 0.1 mm x 0.1 mm." The dimensions of the multilayer ceramic capacitor 1 are not limited to these examples.

[0055] The multilayer ceramic capacitor 1 of this embodiment is preferably used in a multilayer ceramic capacitor 1 having a size of 1.0 mm×0.5 mm×0.5 mm or more.

[0056] (Inner Dielectric Layers and Auxiliary Dielectric Layers) The multilayer ceramic capacitor 1 of this embodiment includes inner dielectric layers 210 and auxiliary dielectric layers. The inner dielectric layers 210 and auxiliary dielectric layers have different grain diameters. The arrangement of the inner dielectric layers 210 and the grain diameters will be described below.

[0057] The arrangement of the inner dielectric layer 210 and the auxiliary dielectric layer will be described with reference to FIGS. 5 and 6 . In FIGS. 3 and 4 , the center position in the width direction W of the laminate 2 is designated as the width direction center 111. FIG. 5 is a cross-sectional view of the width direction center 111 of the multilayer ceramic capacitor 1 in the length direction L and the lamination direction T. In FIGS. 2 and 3 , the center position in the length direction L of the laminate 2 is designated as the length direction center 112. FIG. 6 is a cross-sectional view of the length direction center 112 of the multilayer ceramic capacitor 1 in the width direction W and the lamination direction T. For ease of explanation, FIGS. 5 and 6 show one first internal electrode 31 and one second internal electrode 32, and omit illustration of the remaining internal electrodes. Furthermore, in FIG. 6 , the second side surface S2 side is shown in detail, and the first side surface S1 side is omitted. The multilayer ceramic capacitor 1 has the same configuration as the other portions.

[0058] (Inner dielectric layer) As shown in Figures 5 and 6, a dielectric layer 20 having a dielectric grain size of a predetermined value or less is called an inner dielectric layer 210. The inner dielectric layer 210 is mainly present in a portion sandwiched between internal electrodes on both sides in the stacking direction T. The preferred thickness of the inner dielectric layer 210 is 0.6 µm or more and 0.8 µm or less. Here, the inner dielectric layer 210 is a dielectric layer in the inner layer portion 10 that is not included in the definition of an auxiliary dielectric layer.

[0059] (Definition of auxiliary dielectric layer) The auxiliary dielectric layer is a layer in which grains significantly larger than the grain size of the central dielectric portion are arranged in the portion from the longitudinal end of the internal electrode to the end face and in the portion extending 0.4 μm from the internal electrode in the stacking direction. The grain size is measured using the D50 measurement method described below. (Auxiliary dielectric layer) The auxiliary dielectric layer is a layer in the dielectric layer 20 that contains a dielectric and is arranged between the internal electrode and the end face, separate from the inner dielectric layer 210. As shown in FIG. 5, the auxiliary dielectric layer includes a first auxiliary dielectric layer 211 and a second auxiliary dielectric layer 212.

[0060] The end of the first inner electrode 31 in the longitudinal direction L on the second end face E2 side is called the first longitudinal end 151. The first auxiliary dielectric layer 211 is an auxiliary dielectric layer disposed between the first longitudinal end 151 and the second end face E2.

[0061] The end of the second inner electrode 32 in the longitudinal direction L on the first end face E1 side is referred to as the second longitudinal end 152. The second auxiliary dielectric layer 212 is an auxiliary dielectric layer disposed between the second longitudinal end 152 and the first end face E1.

[0062] The first auxiliary dielectric layer 211 is further disposed surrounding the first longitudinal end 151. The second auxiliary dielectric layer 212 is further disposed surrounding the second longitudinal end 152.

[0063] (Side Side) The first auxiliary dielectric layer 211 and the second auxiliary dielectric layer 212 may be disposed between the internal electrode and the end face, as well as between the internal electrode and the side face. This will be described with reference to Fig. 6. In Fig. 6, the auxiliary dielectric layers and the like are shown on the second side face S2 side, and are not shown on the first side face S1 side.

[0064] The end portion of the first internal electrode 31 in the width direction W on the first side surface S1 side is referred to as the first width direction end portion 161. The first auxiliary dielectric layer 211 may be disposed between the first width direction end portion 161 and the first side surface S1.

[0065] The end portion of the first internal electrode 31 in the width direction W on the second side surface S2 side is referred to as the second width direction end portion 162. The first auxiliary dielectric layer 211 may be disposed between the second width direction end portion 162 and the second side surface S2.

[0066] The end portion of the second internal electrode 32 in the width direction W on the first side surface S1 side is referred to as the third width direction end portion 163. The second auxiliary dielectric layer 212 may be disposed between the third width direction end portion 163 and the first side surface S1.

[0067] The end of the second internal electrode 32 in the width direction W on the second side surface S2 side is referred to as the fourth width direction end 164. The second auxiliary dielectric layer 212 may be disposed between the fourth width direction end 164 and the second side surface S2.

[0068] The first auxiliary dielectric layer 211 may be further disposed so as to surround the first widthwise end 161 and the second widthwise end 162. The second auxiliary dielectric layer 212 may be further disposed so as to surround the third widthwise end 163 and the fourth widthwise end 164.

[0069] (Grain Size) The grain size of the dielectric material contained in the auxiliary dielectric layer is larger than the grain size of the dielectric material contained in the inner dielectric layer 210 .

[0070] 5 and 6 , the grains included in the first auxiliary dielectric layer 211 are shown as first auxiliary grains 221, and the grains included in the second auxiliary dielectric layer 212 are shown as second auxiliary grains 222. Furthermore, the grains included in the inner dielectric layer 210 are shown as inner layer grains 201. The grain size of the first auxiliary grains 221 and the grain size of the second auxiliary grains 222 are larger than the grain size of the inner layer grains 201.

[0071] Specifically, (grain diameter D50 of the auxiliary dielectric layer)>(grain diameter D50 of the inner dielectric layer 210 in the dielectric layer 20).

[0072] In this embodiment, the dielectric layer 20 having a grain size D50 of 170 nm or more is defined as the auxiliary dielectric layer. That is, the grain size D50 of the first auxiliary grains 221 and the grain size D50 of the second auxiliary grains 222 are 170 nm or more.

[0073] The inner dielectric layer 210 has a grain diameter D50 of less than 170 nm. That is, the grain diameter D50 of the inner layer grains 201 is less than 170 nm.

[0074] The boundary of the grain size between the auxiliary dielectric layer and the dielectric layer other than the auxiliary dielectric layer is not limited to 170 nm, and can be set appropriately, for example, between 170 nm and 230 nm.

[0075] (Aspect ratio) The shape of the dielectric grains contained in the auxiliary dielectric layer is flat. In a cross section of the length direction L and the stacking direction T, when the stacking direction T is the vertical direction, the grains of the auxiliary dielectric layer are horizontally elongated. In other words, the length of the grain in the length direction L is longer than the length of the grain in the stacking direction T. Also, in a cross section of the width direction W and the stacking direction T, when the stacking direction T is the vertical direction, the grains of the auxiliary dielectric layer are horizontally elongated. In other words, the length of the grain in the width direction W is longer than the length of the grain in the stacking direction T.

[0076] A preferred aspect ratio of the grain is (size of the grain in the stacking direction T): (size of the grain in the length direction L) = 3:5 to 4:5 in a cross section in the length direction L and stacking direction T. Also, a preferred aspect ratio of the grain is (size of the grain in the stacking direction T) : (size of the grain in the width direction W) = 3:5 to 4:5 in a cross section in the width direction W and stacking direction T.

[0077] (Additives) The types of main components and additives of the auxiliary dielectric layer are, for example, Ni, Mg, Mn, and Si, and the auxiliary dielectric layer may contain at least one of them. However, it is preferable that the amount of additive contained in the auxiliary dielectric layer is less than the amount of additive contained in the portion of the dielectric layer 20 other than the auxiliary dielectric layer.

[0078] The preferred thickness of the auxiliary dielectric layer is 0.16 μm or more and 0.64 μm or less. The auxiliary dielectric layer is also arranged in a range of 0.08 μm or more and 0.32 μm or less from the internal electrode in the stacking direction T. The auxiliary dielectric layer is arranged in a range of 40 μm or more and 80 μm or less from the longitudinal end of the internal electrode toward the longitudinal center 112. The auxiliary dielectric layer is arranged in a range of 40 μm or more and 80 μm or less from the widthwise end of the internal electrode toward the widthwise center 111. This will be explained in detail below.

[0079] (Cross-section in the longitudinal direction L and the stacking direction T) With reference to Fig. 5 , the auxiliary dielectric layers observed in the cross-section in the longitudinal direction L and the stacking direction T will be described. The auxiliary dielectric layers are arranged between the ends and end faces of the internal electrodes in the longitudinal direction L. In other words, the auxiliary dielectric layers are arranged in the L gaps. The first auxiliary dielectric layer 211 is an auxiliary dielectric layer arranged in the first L gap 18. The second auxiliary dielectric layer 212 is an auxiliary dielectric layer arranged in the second L gap 19.

[0080] The thickness of the auxiliary dielectric layer in the stacking direction T is indicated by a thickness T11. The thickness T11 can be set to, for example, 0.16 μm or more and 0.64 μm or less.

[0081] The length T21 of the range in which the auxiliary dielectric layers are arranged in the stacking direction T from the internal electrode is shown. The length T21 can be, for example, 0.08 μm or more and 0.32 μm or less.

[0082] Regarding the range in which the auxiliary dielectric layer is arranged in the longitudinal direction L, the length in the longitudinal direction L from the end of the internal electrode in the longitudinal direction L toward the longitudinal center 112 is indicated by a length L11. The length L11 can be, for example, 40 μm or more and 80 μm or less.

[0083] The auxiliary dielectric layer is disposed in the stacking direction T, sandwiched between the end of the internal electrode in the length direction L and the internal dielectric layer 210. An overlapping portion is formed among the internal electrode, the auxiliary dielectric layer, and the internal dielectric layer 210.

[0084] The presence of the auxiliary dielectric layer between the inner dielectric layer 210 and the internal electrode allows a dielectric with a relatively large grain size to be in contact with the end of the internal electrode in the length direction L. The presence of a dielectric with a relatively large grain size around the end of the internal electrode in the length direction L alleviates electric field concentration at the center of the internal electrode in the length direction L, thereby improving the withstand voltage reliability of the multilayer ceramic capacitor 1.

[0085] (Longitudinal overlap region) In the auxiliary dielectric layer, the region disposed between the inner dielectric layer 210 and the first inner electrode 31 or between the inner dielectric layer 210 and the second inner electrode 32 and extending in the longitudinal direction L is called the longitudinal overlap region.

[0086] (First Region and Second Region) In the longitudinal overlapping region, the longitudinal overlapping region on one side of the stacking direction T of the internal electrodes is called the first region 261, and the longitudinal overlapping region on the other side is called the second region 262. The length of the first region 261 in the longitudinal direction L is indicated by length L1. The length of the second region 262 in the longitudinal direction L is indicated by length L2.

[0087] The length L1 is longer than the length L2. The length L1 may be, for example, 70 μm or more and 110 μm or less. The length L2 may be, for example, 40 μm or more and 80 μm or less.

[0088] Because the length L1 is longer than the length L2, there are areas where the electric field is concentrated in stages, making it possible to prevent the electric field from concentrating suddenly at the ends of the internal electrodes. In other words, because the first region 261 and the second region 262 have different dimensions in the length direction L, it is possible to prevent the electric field from concentrating suddenly at the ends of the internal electrodes in the length direction L while preventing the electric field from concentrating in the center of the internal electrodes in the length direction L, thereby improving the withstand voltage reliability of the multilayer ceramic capacitor 1 as a whole.

[0089] The ratio of length L1 to length L2, i.e., L1 / L2, is preferably 1.10 or more and 2.75 or less. This allows both voltage resistance reliability and resistance value (log(IR)) to be improved, thereby achieving both voltage resistance reliability and insulation resistance. Note that the first region 261 and the second region 262 do not have to be continuous. For example, if the first region 261 is divided into two parts in the longitudinal direction L, the length L1 is the sum of the lengths of the divided parts in the longitudinal direction L.

[0090] (Cross-section in width direction W and stacking direction T) The auxiliary dielectric layer observed in a cross-section in the width direction W and stacking direction T will be described with reference to Fig. 6. Note that a description of matters already described with reference to Fig. 5 will be omitted.

[0091] The auxiliary dielectric layer may be disposed between the end of the internal electrode in the length direction L and the end face, and also between the end of the internal electrode in the width direction W and the side face. In other words, the auxiliary dielectric layer may be disposed in part of the W gap.

[0092] In the example shown in FIG. 6, the first auxiliary dielectric layer 211 and the second auxiliary dielectric layer 212 are disposed in a part of the first W gap 15 and a part of the second W gap 16, respectively.

[0093] Regarding the range in which the auxiliary dielectric layer is arranged in the width direction W, the length in the width direction W from the end of the internal electrode in the width direction W toward the width direction center 111 is indicated as a length W11. The length W11 can be, for example, 40 μm or more and 80 μm or less.

[0094] The auxiliary dielectric layer is disposed in the stacking direction T, sandwiched between the end of the internal electrode in the width direction W and the dielectric layer 20. An overlapping portion is formed among the internal electrode, the auxiliary dielectric layer, and the inner dielectric layer 210.

[0095] The presence of the auxiliary dielectric layer between the inner dielectric layer 210 and the internal electrode allows a dielectric with a relatively large grain size to come into contact with the end of the internal electrode in the width direction W. The presence of a dielectric with a relatively large grain size around the end of the internal electrode in the width direction W alleviates electric field concentration at the center of the internal electrode in the width direction W, thereby improving the withstand voltage reliability of the multilayer ceramic capacitor 1.

[0096] (Width-direction overlapping region) In the auxiliary dielectric layer, the region that is arranged between the inner dielectric layer 210 and the first internal electrode 31 or between the inner dielectric layer 210 and the second internal electrode 32 and extends along the width direction W is called the width-direction overlapping region.

[0097] (Third Region and Fourth Region) In the widthwise overlapping region, the widthwise overlapping region on one side in the stacking direction T of the internal electrodes is called the third region 263, and the widthwise overlapping region on the other side is called the fourth region 264. The length of the third region 263 in the width direction W is indicated by length W3. The length of the fourth region 264 in the width direction L is indicated by length W4.

[0098] The length W3 is longer than the length W4. The length W3 may be, for example, 70 μm or more and 110 μm or less. The length W4 may be, for example, 40 μm or more and 80 μm or less.

[0099] Because the length W3 is longer than the length W4, there are areas where the electric field is concentrated in stages, making it possible to prevent the electric field from concentrating suddenly at the ends of the internal electrodes. In other words, because the third region 263 and the fourth region 264 have different dimensions in the width direction W, it is possible to prevent the electric field from concentrating suddenly at the ends of the internal electrodes in the width direction W while preventing the electric field from concentrating at the center of the internal electrodes in the width direction W, and it is possible to improve the withstand voltage reliability of the multilayer ceramic capacitor 1 as a whole.

[0100] The multilayer ceramic capacitor 1 of this embodiment has a structure that can suppress abrupt electric field concentration not only from the internal electrode at the lengthwise center 112 to the internal electrode at the end in the lengthwise direction L, but also from the internal electrode at the widthwise center 111 to the internal electrode at the end in the widthwise direction W. In other words, the multilayer ceramic capacitor 1 has a structure that suppresses abrupt electric field concentration over the entire internal electrode, thereby further improving the withstand voltage reliability.

[0101] The ratio of length W4 to length W3, i.e., W3 / W4, is preferably 1.10 or greater and 2.75 or less. This allows for further improvement in capacitance. Note that third region 263 and fourth region 264 do not have to be continuous. For example, if third region 263 is divided into two parts in the length direction L, length W3 is the sum of the lengths of the divided parts in the width direction W.

[0102] (Thickness of Dielectric Layer) The thickness of the dielectric layer 20 at the longitudinal center 112 and the thickness of the dielectric layer 20 at the end faces will be described. In Fig. 2, the distance between adjacent first internal electrodes 31 in the stacking direction T at the first end face E1 is indicated by distance T1. In Fig. 2, the distance between adjacent first internal electrodes 31 and second internal electrodes 32 in the stacking direction T at the longitudinal center 112 is indicated by distance T2. Both distance T1 and distance T2 are the distances in the stacking direction T of the dielectric layers 20 at the widthwise center of the laminate 2 in the cross section of the longitudinal direction L and stacking direction T. Distance T1 is greater than twice distance T2.

[0103] (Method for Manufacturing Multilayer Ceramic Capacitor) A method for manufacturing the multilayer ceramic capacitor 1 will be described. Note that the method for manufacturing the multilayer ceramic capacitor 1 is not limited to the method described below.

[0104] A dielectric sheet and a conductive paste for the internal electrodes are prepared. The dielectric sheet and the conductive paste for the internal electrodes contain a binder and a solvent. Known binders and solvents can be used. The dielectric sheet is also called a ceramic green sheet. The conductive paste is also called a paste for the internal electrodes.

[0105] A dielectric sheet on which an internal electrode pattern is formed is prepared. A conductive paste for the internal electrodes is printed on the dielectric sheet in a predetermined pattern, thereby preparing a dielectric sheet on which a first internal electrode pattern is formed and a dielectric sheet on which a second internal electrode pattern is formed. The printing is performed by, for example, screen printing or gravure printing.

[0106] A predetermined number of dielectric sheets not printed with an internal electrode pattern are stacked to form a portion that will become a first outer layer portion. Dielectric sheets printed with a first internal electrode pattern and a second internal electrode pattern are stacked in order on top of that to form a portion that will become an inner layer portion. Furthermore, a predetermined number of dielectric sheets not printed with an internal electrode pattern are stacked on top of the portion that will become an inner layer portion to form a portion that will become a second outer layer portion. In this way, a laminated sheet is produced.

[0107] (Auxiliary dielectric paste) In the multilayer ceramic capacitor 1 of this embodiment, an auxiliary dielectric paste is applied before and after the application of the internal electrode paste. That is, the manufacturing process includes an auxiliary dielectric paste application step. The auxiliary dielectric paste application step is performed before and after the internal electrode paste printing step. The material of the auxiliary dielectric paste will be described later.

[0108] In the auxiliary dielectric paste application process, the auxiliary dielectric paste is applied from the position corresponding to the longitudinal end of the internal electrode to the end face. Subsequently, in the internal electrode paste printing process, the internal electrode paste is printed so as to overlap the auxiliary dielectric paste. After that, the auxiliary dielectric paste is further applied on top of the internal electrode paste so as to overlap the internal electrode paste to any desired length.

[0109] The overlap amount between the internal electrode paste and the auxiliary dielectric paste can be, for example, 40 μm to 80 μm in the width direction and 40 μm to 80 μm in the length direction. Overlapping the internal electrode paste and the auxiliary dielectric paste results in a structure in which dielectric particles with large grain sizes overlap at the widthwise and lengthwise ends of the internal electrodes. Furthermore, the auxiliary dielectric layer is disposed surrounding the widthwise and lengthwise ends of the internal electrodes.

[0110] This will be described in detail with reference to Fig. 7. Fig. 7 is a diagram showing a ceramic green sheet 1000 on which an internal electrode paste 1010, an auxiliary dielectric paste 1021, and an auxiliary dielectric paste 1022 are printed or applied.

[0111] 7, the auxiliary dielectric paste 1021, the internal electrode paste 1010, and the auxiliary dielectric paste 1022 are arranged in this order, with parts of them overlapping each other, on the ceramic green sheet 1000. The auxiliary dielectric paste 1021 is an auxiliary dielectric paste that is applied before the internal electrode paste 1010 is applied. The auxiliary dielectric paste 1022 is an auxiliary dielectric paste that is applied after the internal electrode paste 1010 is applied.

[0112] The overlap width, i.e., the amount of overlap, between the auxiliary dielectric paste 1021 and the internal electrode paste 1010 is indicated by distance 1051. The overlap amount between the internal electrode paste 1010 and the auxiliary dielectric paste 1022 is indicated by distance 1052. The distances 1051 and 1052 can be set to, for example, 40 μm or more and 80 μm or less.

[0113] Furthermore, the distances 1051 and 1052 can be adjusted as appropriate. By adjusting the distances 1051 and 1052, it is possible to adjust the size of the overlapping regions between the auxiliary dielectric layers and the internal electrodes on both sides in the stacking direction T of the internal electrodes. For example, by setting the distances 1051 and 1052 to different values, it is possible to make different the size of the overlapping regions between the auxiliary dielectric layers and the internal electrodes on both sides in the stacking direction T of the internal electrodes.

[0114] The composition of the auxiliary dielectric paste will be described. The auxiliary dielectric paste may contain the same material as the dielectric material contained in the dielectric sheets constituting the inner layer portion, such as the above-mentioned inner dielectric layer. The auxiliary dielectric paste contains, as an additive, elements that densify the grains of the dielectric, such as Mg, Mn, Si, and Ni. The amount of additive contained in the auxiliary dielectric paste can be less than the amount of additive contained in the dielectric sheets constituting the inner layer portion. This allows the amount of additive contained in the auxiliary dielectric layer to be less than the amount of additive contained in the dielectric layer in the multilayer ceramic capacitor.

[0115] By reducing the amount of additives contained in the auxiliary dielectric paste, the grain size of the dielectric contained in the auxiliary dielectric layer in the W gap and L gap of the multilayer ceramic capacitor can be made larger than the grain size of the dielectric layers other than the auxiliary dielectric layer.

[0116] Furthermore, when preparing the auxiliary dielectric paste, the dielectric powder may be pulverized to form elongated grains, thereby making the grains horizontally elongated.

[0117] The prepared auxiliary dielectric paste is applied so as to partially overlap the internal electrode paste as described above, thereby obtaining a laminated sheet including a layer coated with the auxiliary dielectric paste.

[0118] The laminated sheets are pressed in the lamination direction by means of a hydrostatic press or the like to produce a laminated block.

[0119] The laminated block is cut into individual pieces to produce laminated chips. Specifically, the laminated block is cut into individual pieces using a cutting blade to produce pre-fired laminates.

[0120] The laminated chip is fired to produce a laminate. Before firing, the corners and ridges of the laminated chip may be rounded by barrel polishing or the like. The firing temperature is preferably 900°C or higher and 1400°C or lower, depending on the materials of the dielectric and internal electrodes. The above-mentioned barrel polishing or the like can also be performed on the laminated body after firing.

[0121] Next, the external electrodes are formed. First, a conductive paste that will become the base electrode layer is applied to both end surfaces of the laminate 2 to form the base electrode layer. When forming a baked layer as the base electrode layer, a conductive paste containing a glass component and a metal is applied by a method such as dipping, and then a baking process is performed to form the base electrode layer. The baking temperature at this time is preferably 700°C or higher and 900°C or lower.

[0122] Then, a plating layer is formed on the surface of the base electrode layer. A Ni plating layer and a Sn plating layer are formed on the base electrode layer. The Ni plating layer and the Sn plating layer are formed sequentially by, for example, barrel plating. In this manner, a multilayer ceramic capacitor is obtained.

[0123] (Measurement Method) The inner dielectric layer 210 and the auxiliary dielectric layer can be distinguished by the grain size of the dielectric. The method for measuring the grain size will be explained below. The grain size is measured in a cross section of the laminate 2 at the width center 111 in the length direction L and stacking direction T. The cross section is observed under a microscope. The grain sizes of the grains found through the observation are averaged. This averaged grain size is taken as the grain size of the ceramic. The average is taken as the D50 average.

[0124] The observation range is a rectangular range with a length of 60 μm in the longitudinal direction L and a length of 30 μm in the stacking direction T. Each side of the rectangle is parallel to the longitudinal direction L or the stacking direction T. FIG. 2 shows a first observation range 121 and a second observation range 122. The first observation range 121 is a range for measuring the grain size of the dielectric of the inner dielectric layer 210. The second observation range 122 is a range for measuring the grain size of the dielectric of the auxiliary dielectric layer.

[0125] (First Observation Range) The first observation range 121 is located at the center of the length direction L and the center of the stacking direction T of the laminate 2. The first observation range 121 is a portion sandwiched between the first internal electrode 31 and the second internal electrode 32 on both sides in the stacking direction T at the center of the length direction L. The first observation range 121 is part of the central dielectric portion. In FIG. 2, the center position of the laminate 2 in the stacking direction T is shown as the stacking direction center 113. The intersection of the length direction center 112 and the stacking direction center 113 is shown as the first intersection 118. The first observation range 121 is positioned with the first intersection 118 at its center. The length 125 is the length of the first observation range 121 in the length direction L. The length 125 is 60 μm. The length 126 is the length of the first observation range 121 in the stacking direction T. The length 126 is 30 μm.

[0126] (Second Observation Area) The second observation area 122 is located near the center of the second L gap 19 in the length direction L and the center of the stacking direction T. In FIG. 2 , the center of the second L gap 19 in the length direction L is shown as the L gap length direction center 115. The first internal electrode 31 closest to the stacking direction center 113 is shown as the central internal electrode 311. A line extending from the central internal electrode 311 in the length direction L is shown as the L gap stacking direction center 116. The intersection of the L gap length direction center 115 and the L gap stacking direction center 116 is shown as the second intersection 119. The second observation area 122 is positioned with the second intersection 119 at its center. The length 125 of the second observation area 122 in the length direction L is 60 μm, similar to the first observation area 121. The length 126 of the second observation area 122 in the stacking direction T is 30 μm, similar to the first observation area 121.

[0127] As described above, a dielectric layer having a grain size D50 of 170 nm or more is defined as an auxiliary dielectric layer. A dielectric layer having a grain size D50 of less than 170 nm is defined as a dielectric layer other than the auxiliary dielectric layer, for example, the inner dielectric layer 210.

[0128] (Examples and Comparative Examples) Examples and Comparative Examples of the multilayer ceramic capacitor 1 of the present invention will be described with reference to Figure 8. Figure 8 is a diagram showing the evaluation results of the examples and comparative examples. (Experimental Method) 1. Fabrication of Multilayer Ceramic Capacitor for Evaluation Dimensions of multilayer ceramic capacitor: Dimension in length direction L × Dimension in stacking direction T × Dimension in width direction W = 3.45 mm × 1.84 mm × 1.85 mm Multilayer ceramic capacitors for evaluation were fabricated according to the above-described method for fabricating a multilayer ceramic capacitor. The multilayer ceramic capacitor of the comparative example was fabricated so as not to form the first region and the second region.

[0129] 2. Measurement of the length ratio between the first region and the second region: A cross section in the length direction L and the stacking direction T was polished at the widthwise center 111 of the multilayer ceramic capacitor 1. Of the regions where the average diameter of dielectric grains was 170 nm or more, i.e., the auxiliary dielectric layers, the dimensions in the length direction L of the auxiliary dielectric layers on both sides of the stacking direction T of the internal electrodes, i.e., the first region 261 and the second region 262, were measured. Then, the ratio of the length in the length direction L of the first region 261 (first region / second region) was calculated using the length in the length direction L of the second region 262 as a reference.

[0130] 3. Evaluation (1) Measurement of Withstand Voltage Reliability Under conditions of a voltage step-up of 50 V / s and a detection current of 200 mA, a withstand voltage measurement test (BDV, dielectric breakdown voltage) was performed for the Comparative Example and Examples 1 to 7. (2) IR (Insulation Resistance) Measurement IR measurements were performed on 100 samples for each of the Comparative Example and Examples 1 to 7. (3) The evaluation was made based on the balance between withstand voltage reliability and insulation resistance, with a rating of ○ (good) or ⊚ (very good).

[0131] 4. Results: When the ratio of the first region to the second region is 1.03 or more and 2.75 or less, the withstand voltage at the center of the internal electrode can be more reliably increased (improving the withstand voltage of the entire multilayer ceramic capacitor) and rapid electric field concentration at the end of the internal electrode can be suppressed. In other words, when the ratio of the first region to the second region is 1.03 or more and 2.75 or less, the withstand voltage characteristics are good.

[0132] Furthermore, when the ratio of the first region to the second region is 1.10 or more and 2.75 or less, the withstand voltage characteristics are also good, and the IR degradation (insulation resistance) is also good (log(IR) is 7 or more). From the above, when the ratio of the first region to the second region is 1.10 or more and 2.75 or less, both the withstand voltage reliability and the insulation reliability are good. In other words, the evaluation is very good.

[0133] Although the embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments, and various changes, modifications, and combinations are possible.

[0134] Although the embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments, and various changes, modifications, and combinations are possible.

[0135] <1> A laminate including a plurality of laminated dielectric layers and a plurality of first internal electrodes and second internal electrodes, the laminate having first and second main surfaces facing each other in a lamination direction of the dielectric layers and the first internal electrodes and the second internal electrodes, first side surfaces facing each other in a width direction perpendicular to the lamination direction, and first end surfaces facing each other in a length direction perpendicular to the lamination direction and the width direction; a first external electrode electrically connected to the first internal electrodes and provided on a surface of the laminate; and a second external electrode electrically connected to the second internal electrodes and provided on the surface of the laminate, the first internal electrode being extended to the first end surface, and the second internal electrode being extended to the second end surface, and when a portion sandwiched between the first internal electrodes and the second internal electrodes on both sides in the lamination direction at the center in the length direction, the center in the width direction, and the center in the lamination direction is defined as a central dielectric portion, A multilayer ceramic capacitor comprising: a first auxiliary dielectric layer having a larger dielectric grain size than the central dielectric portion and disposed between the first internal electrode and the second end face; a second auxiliary dielectric layer having a larger dielectric grain size than the central dielectric portion and disposed between the second internal electrode and the first end face; the first auxiliary dielectric layer is disposed around an end portion of the first internal electrode on the second end face side in the longitudinal direction; and the second auxiliary dielectric layer is disposed around an end portion of the second internal electrode on the first end face side in the longitudinal direction.

[0136] <2> The multilayer ceramic capacitor according to <1>, wherein in a cross section in the longitudinal direction and the stacking direction at the center in the width direction, the first auxiliary dielectric layer and the second auxiliary dielectric layer have a longitudinal overlap region arranged between an inner layer dielectric layer and the first internal electrode or the second internal electrode, the longitudinal overlap region having a first region and a second region, and the longitudinal dimension of the first region is larger than the longitudinal dimension of the second region.

[0137] <3> The multilayer ceramic capacitor according to <2>, wherein in a cross section of the widthwise center taken along the length direction and the stacking direction, a ratio of the lengthwise dimension of the second region to the lengthwise dimension of the first region is 1.10 or more and 2.75 or less.

[0138] <4> The multilayer ceramic capacitor according to any one of <1> to <3>, wherein in a cross section in the width direction and the stacking direction at the center in the longitudinal direction, the first auxiliary dielectric layer and the second auxiliary dielectric layer have a width direction overlapping region arranged between an inner layer dielectric layer and the first internal electrode or the second internal electrode, the width direction overlapping region having a third region and a fourth region, and the width direction dimension of the third region is larger than the width direction dimension of the fourth region.

[0139] <5> The multilayer ceramic capacitor according to <4>, wherein in a cross section in the width direction and the stacking direction at the center in the longitudinal direction, a ratio of the width direction dimension of the fourth region to the width direction dimension of the third region is 1.10 or more and 2.75 or less.

[0140] <6> The multilayer ceramic capacitor according to any one of <1> to <5>, wherein the auxiliary dielectric layer contains an additive, and the amount of the additive contained in the auxiliary dielectric layer is less than the amount of the additive contained in the inner dielectric layer.

[0141] <7> The multilayer ceramic capacitor according to any one of <1> to <6>, wherein the lengthwise dimension is 1.0 mm or more, and the widthwise dimension and the lamination direction dimension are 0.5 mm or more.

[0142] <8> The multilayer ceramic capacitor according to any one of <1> to <7>, wherein, in a cross section in the length direction and the stacking direction at the center in the width direction, a distance T1 between adjacent first internal electrodes on the first end face is greater than twice a distance T2 between the first internal electrode and the second internal electrode at the center in the length direction.

[0143] REFERENCE SIGNS LIST 1 Multilayer ceramic capacitor 2 Laminate 10 Inner layer portion 12 First outer layer portion 13 Second outer layer portion 20 Dielectric layer 25 Core portion 26 Effective portion 28 First ineffective portion 29 Second ineffective portion 31 First internal electrode 32 Second internal electrode 33 First opposing portion 34 Second opposing portion 35 First lead portion 36 Second lead portion 38 Opposing electrode portion 41 First external electrode 42 Second external electrode 51 First base electrode layer 52 Second base electrode layer 61 First plating layer 62 Second plating layer 111 Width direction center 112 Direction center 113 Stacking direction center 115 L gap length direction center 116 L gap stacking direction center 118 First intersection 119 Second intersection 121 First observation range 122 Second observation area 151 First lengthwise end 152 Second lengthwise end 161 First widthwise end 162 Second widthwise end 163 Third widthwise end 164 Fourth widthwise end 210 Inner dielectric layer 211 First auxiliary dielectric layer 212 Second auxiliary dielectric layer 261 First region 262 Second region 263 Third region 264 Fourth region 311 Central internal electrode 1000 Ceramic green sheet 1010 Internal electrode paste 1021 Auxiliary dielectric paste 1022 Auxiliary dielectric paste

Claims

1. A laminate including a plurality of laminated dielectric layers and a plurality of first and second internal electrodes, the laminate having first and second main surfaces facing each other in the lamination direction of the dielectric layers and the first and second internal electrodes, first side surfaces facing each other in a width direction perpendicular to the lamination direction, and first end surfaces facing each other in a length direction perpendicular to the lamination direction and the width direction; a first external electrode electrically connected to the first internal electrode and provided on the surface of the laminate; and a second external electrode electrically connected to the second internal electrode and provided on the surface of the laminate, the first internal electrode being extended to the first end surface, and the second internal electrode being extended to the second end surface, and when the portion sandwiched between the first internal electrode and the second internal electrode on both sides in the lamination direction at the center in the length direction, the center in the width direction, and the center in the lamination direction is defined as a central dielectric portion, A multilayer ceramic capacitor comprising: a first auxiliary dielectric layer having a larger dielectric grain size than the central dielectric portion and disposed between the first internal electrode and the second end face; a second auxiliary dielectric layer having a larger dielectric grain size than the central dielectric portion and disposed between the second internal electrode and the first end face; the first auxiliary dielectric layer is disposed around an end portion of the first internal electrode on the second end face side in the longitudinal direction; and the second auxiliary dielectric layer is disposed around an end portion of the second internal electrode on the first end face side in the longitudinal direction.

2. The multilayer ceramic capacitor according to claim 1, wherein, in a cross section in the longitudinal direction and the lamination direction at the center in the width direction, the first auxiliary dielectric layer and the second auxiliary dielectric layer have a longitudinal overlap region disposed between an inner dielectric layer and the first internal electrode or the second internal electrode, the longitudinal overlap region having a first region and a second region, and the longitudinal dimension of the first region is greater than the longitudinal dimension of the second region.

3. The multilayer ceramic capacitor according to claim 2, wherein in a cross section of the widthwise center taken along the length direction and the lamination direction, the ratio of the lengthwise dimension of the second region to the lengthwise dimension of the first region is 1.10 or more and 2.75 or less.

4. The multilayer ceramic capacitor according to any one of claims 1 to 3, wherein, in a cross section in the width direction and the stacking direction at the center in the longitudinal direction, the first auxiliary dielectric layer and the second auxiliary dielectric layer have a widthwise overlapping region disposed between an inner layer dielectric layer and the first internal electrode or the second internal electrode, the widthwise overlapping region having a third region and a fourth region, and the widthwise dimension of the third region is larger than the widthwise dimension of the fourth region.

5. The multilayer ceramic capacitor according to claim 4, wherein in a cross section of the longitudinal center taken along the width direction and the stacking direction, the ratio of the width dimension of the fourth region to the width dimension of the third region is 1.10 or more and 2.75 or less.

6. The multilayer ceramic capacitor according to any one of claims 1 to 5, wherein the auxiliary dielectric layer contains an additive, and the amount of the additive contained in the auxiliary dielectric layer is less than the amount of the additive contained in the inner dielectric layer.

7. The multilayer ceramic capacitor according to any one of claims 1 to 6, wherein the lengthwise dimension is 1.0 mm or more, and the widthwise dimension and the lamination direction dimension are 0.5 mm or more.

8. The multilayer ceramic capacitor according to any one of claims 1 to 7, wherein, in a cross section at the center in the width direction taken along the length direction and the lamination direction, a distance T1 between adjacent first internal electrodes on the first end face is greater than twice a distance T2 between the first internal electrode and the second internal electrode at the center in the length direction.

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