Multilayer ceramic capacitor

Abstract

Provided is a multilayer ceramic capacitor having further improved reliability.　A multilayer ceramic capacitor 1 comprises: a laminate 2 including a dielectric layer 5 and an internal electrode layer 6; and a plurality of external electrodes provided on the surface of the laminate 2 and connected to a part of the internal electrode layer 6, wherein the titanium concentration at an interface 50 between the dielectric layer 5 and the internal electrode layer 6 is higher than the titanium concentration of the dielectric layer 5.

Description

Multilayer ceramic capacitor

[0001] The present invention relates to a multilayer ceramic capacitor.

[0002] In recent years, the application of multilayer ceramic capacitors to communication devices and in-vehicle devices that require high capacitance and high reliability has been progressing. Patent Document 1 describes a technique for improving the performance of multilayer ceramic capacitors by adjusting the distribution of nickel near grain boundaries and the like.

[0003] Japanese Patent Application Laid-Open No. 2017-228590

[0004] However, in the technique described in Patent Document 1, the improvement in reliability may not be sufficient. Specifically, in use under high-temperature and high-humidity conditions, the insulation of the dielectric layer may deteriorate, and eventually dielectric breakdown may occur.

[0005] Therefore, an object of the present invention is to provide a multilayer ceramic capacitor with improved reliability.

[0006] The multilayer ceramic capacitor of the present invention includes a plurality of stacked dielectric layers and a plurality of internal electrode layers, and has a first main surface and a second main surface facing each other in the stacking direction, a first side surface and a second side surface facing each other in the width direction which is a direction orthogonal to the stacking direction, and a first end surface and a second end surface facing each other in the length direction which is a direction orthogonal to the stacking direction and the width direction. The multilayer ceramic capacitor further includes a plurality of external electrodes provided on the surface of the stacked body and connected to a part of the internal electrode layers. The titanium concentration at the interface between the dielectric layer and the internal electrode layer is higher than the titanium concentration of the dielectric layer.

[0007] According to the present invention, a multilayer ceramic capacitor with improved reliability can be provided.

[0008] FIG. 1 is a perspective view of a multilayer ceramic capacitor according to an embodiment of the present invention. FIG. 2 is a cross-sectional view taken along line I-I of FIG. 1. FIG. 3 is a cross-sectional view taken along line II-II of FIG. 1. FIG. 4 is a view showing a part of a cross-section parallel to the length direction and the stacking direction of the stacked body.

[0009] Embodiments for carrying out the invention will be described with reference to Figure 1. Figure 1 is a perspective view of a multilayer ceramic capacitor 1 according to an embodiment of the present invention. Note that Figure 1 shows a so-called two-terminal multilayer ceramic capacitor. However, the multilayer ceramic capacitor 1 of the present invention is not limited to a two-terminal multilayer ceramic capacitor. The multilayer ceramic capacitor 1 of the present invention may be a multi-terminal multilayer ceramic capacitor, such as a three-terminal capacitor.

[0010] (Laminate) Laminate 2 includes a plurality of stacked dielectric layers and a plurality of internal electrode layers. The shape of laminate 2 is approximately a rectangular parallelepiped.

[0011] In the laminate 2, the direction in which the dielectric layer and the internal electrode layer are stacked is defined as the height direction T. The direction perpendicular to the height direction T is defined as the width direction W. The direction perpendicular to both the height direction T and the width direction W is defined as the length direction L.

[0012] In the laminate 2, one of the two faces facing each other in the height direction T is designated as the first main face M1. The remaining face is designated as the second main face M2. In the laminate 2, one of the two faces facing each other in the width direction W is designated as the first side face S1. The remaining face is designated as the second side face S2. In the laminate 2, one of the two faces facing each other in the length direction L is designated as the first end face E1. The remaining face is designated as the second end face E2.

[0013] Regarding the cross-section of the laminate 2, the section along line I-I in Figure 1 is designated as the LT section. Regarding the cross-section of the laminate 2, the section along line II-II in Figure 1 is designated as the WT section.

[0014] The points where three faces of the laminate 2 intersect are defined as corners of the laminate 2, and the points where two faces of the laminate 2 intersect are defined as edges of the laminate 2. It is preferable that the corners and edges are rounded.

[0015] (Dielectric Layer) The total number of dielectric layers included in the laminate 2 is preferably 15 to 2000. The main material of the dielectric layer is a ceramic material. Examples of ceramic materials include dielectric ceramics mainly composed of barium titanate, calcium titanate, strontium titanate, etc. The ceramic material may also be a dielectric ceramic in which minor components such as manganese compounds, iron compounds, chromium compounds, cobalt compounds, and nickel compounds are added to these main components.

[0016] The dielectric layer contains crystalline particles. These crystalline particles are the main components of the dielectric layer and are composed of a perovskite-type oxide containing A-site and B-site elements. The general formula for perovskite-type oxides is: ABO ３ It has a composition represented by [formula]. Each atom of the A-site element and each atom of the B-site element are ionized and occupy the A-site and B-site of the perovskite structure. Examples of A-site elements include elements with relatively large ion sizes, such as barium, calcium, and strontium. Examples of B-site elements include elements with relatively small ion sizes, such as titanium, zirconium, and hafnium.

[0017] The combination of A-site elements and B-site elements is not particularly limited, as long as the perovskite structure is maintained. Furthermore, each of the A-site and B-site elements may consist of only one type of element, or a combination of multiple elements.

[0018] Preferably, the A-site element contains barium, and the B-site element contains titanium. In other words, the perovskite-type oxide is preferably a barium titanate-based compound.

[0019] The thickness of each dielectric layer is preferably 0.3 μm or more and 10 μm or less.

[0020] (Division of the Laminate) The division of the laminate 2 in the longitudinal direction L will be explained based on Figure 2. Figure 2 is a cross-sectional view taken along line I-I in Figure 1. The laminate 2 can be divided in the height direction T into a first main surface-side outer layer OL1, an inner layer range IL, and a second main surface-side outer layer OL2. The first main surface-side outer layer OL1, the inner layer range IL, and the second main surface-side outer layer OL2 are arranged in this order from the first main surface M1 to the second main surface M2 in the height direction T.

[0021] The first main surface-side outer layer portion OL1 is the portion between the internal electrode layer closest to the first main surface M1 and the first main surface M1. The inner layer range IL is the range where the internal electrode layers face each other. The second main surface-side outer layer portion OL2 is the portion between the internal electrode layer closest to the second main surface M2 and the second main surface M2.

[0022] The first main surface-side outer layer OL1 is located on the first main surface M1 side of the laminate 2. The first main surface-side outer layer OL1 is formed by an assembly of multiple dielectric layers located between the first main surface M1 and the internal electrode layer closest to the first main surface M1.

[0023] The second main surface-side outer layer OL2 is located on the second main surface M2 side of the laminate 2. The second main surface-side outer layer OL2 is formed by an assembly of multiple dielectric layers located between the second main surface M2 and the internal electrode layer closest to the second main surface M2.

[0024] The inner layer area IL is the area sandwiched between the first main surface-side outer layer portion OL1 and the second main surface-side outer layer portion OL2.

[0025] Of the dielectric layers 5, the dielectric layers 5 located in the first main surface-side outer layer portion OL1 and the second main surface-side outer layer portion OL2 are designated as the outer dielectric layer 3. Of the dielectric layers 5, the dielectric layers 5 located in the inner layer range IL are designated as the inner dielectric layer 4.

[0026] The following terms may be used in describing length and position.

[0027] The length in the length direction L is defined as the length direction length. The length in the width direction W is defined as the width direction length. The length in the height direction T is defined as the height direction length.

[0028] The position at half the length in the longitudinal direction is defined as the center position in the longitudinal direction L. The center position in the longitudinal direction L is defined as the longitudinal center position.

[0029] The position at half the length in the width direction is defined as the center position in the width direction W. The center position in the width direction W is defined as the width direction center position.

[0030] The position at half the length in the height direction is defined as the center position in the height direction T. The center position in the height direction T is defined as the height direction center position.

[0031] The end in the length direction L is defined as the lengthwise end. The end in the width direction W is defined as the widthwise end. The end in the height direction T is defined as the heightwise end.

[0032] The size of the laminate 2 is not particularly limited. The length of the laminate is preferably 0.2 mm or more and 10 mm or less. The width of the laminate 2 is preferably 0.1 mm or more and 5 mm or less. The height of the laminate 2 is preferably 0.1 mm or more and 5 mm or less.

[0033] (L Gap) The division of the laminate 2 in the longitudinal direction L is explained. The laminate 2 can be divided in the longitudinal direction L into a first end face side outer layer LG1, a longitudinally opposing part LF, and a second end face side outer layer LG2. The first end face side outer layer LG1, the longitudinally opposing part LF, and the second end face side outer layer LG2 are arranged in this order in the longitudinal direction L from the first end face E1 to the second end face E2.

[0034] The longitudinally opposed portion LF is the portion where the internal electrode layers face each other in the height direction T. The first end-face side outer layer portion LG1 is the portion between the longitudinally opposed portion LF and the first end face E1. The second end-face side outer layer portion LG2 is the portion between the longitudinally opposed portion LF and the second end face E2. The longitudinally opposed portion LF corresponds to the opposing electrode portion of the internal electrode layer. The first end-face side outer layer portion LG1 and the second end-face side outer layer portion LG2 correspond to the leading electrode portion of the internal electrode layer. The first end-face side outer layer portion LG1 and the second end-face side outer layer portion LG2 are also called the L gap.

[0035] The opposing electrode section includes a first opposing electrode section 7a and a second opposing electrode section 7b. The lead-out electrode section includes a first lead-out electrode section 8a and a second lead-out electrode section 8b. The opposing electrode section and the lead-out electrode section will be described later.

[0036] The first end-face side outer layer LG1 is located on the first end face E1 side. The first end-face side outer layer LG1 is located between the first end face E1 and the end of the second internal electrode layer 6b on the first end face E1 side.

[0037] The second end-face side outer layer LG2 is located on the second end face E2 side. The second end-face side outer layer LG2 is located between the second end face E2 and the end of the first internal electrode layer 6a on the second end face E2 side. The first internal electrode layer 6a and the second internal electrode layer 6b together are called the internal electrode layer 6.

[0038] (W Gap) The division of the laminate 2 in the width direction W will be explained based on Figure 3. Figure 3 is a cross-sectional view taken along line II-II in Figure 1. The laminate 2 can be divided in the width direction W into a first side outer layer WG1, a width-direction opposing part WF, and a second side outer layer WG2. The first side outer layer WG1, the width-direction opposing part WF, and the second side outer layer WG2 are arranged in this order from the first side S1 to the second side S2 in the width direction W.

[0039] The widthwise opposing portion WF is the portion where the internal electrode layer faces in the height direction T. The first side outer layer portion WG1 is the portion between the widthwise opposing portion WF and the first side surface S1. The second side outer layer portion WG2 is the portion between the widthwise opposing portion WF and the second side surface S2. The first side outer layer portion WG1 and the second side outer layer portion WG2 are also called the W gap.

[0040] The first side outer layer WG1 and the second side outer layer WG2 are portions in which there is no internal electrode layer in the height direction T. The first side outer layer WG1 is located on the first side S1 side.

[0041] The second side outer layer portion WG2 is located on the second side S2 side. The second side outer layer portion WG2 is formed by a plurality of dielectric layers located between the second side S2 and the outermost surface of the width direction facing portion WF on the second side S2 side.

[0042] (Internal electrode layer) The internal electrode layer includes a plurality of first internal electrode layers 6a and a plurality of second internal electrode layers 6b. The first internal electrode layer 6a is an internal electrode layer exposed on the first end face E1. The second internal electrode layer 6b is an internal electrode layer exposed on the second end face E2.

[0043] The first internal electrode layer 6a can be divided into a first opposing electrode portion 7a and a first lead-out electrode portion 8a. The first opposing electrode portion 7a is the portion facing the second internal electrode layer 6b. The first lead-out electrode portion 8a is the portion drawn from the first opposing electrode portion 7a to the first end face E1 of the laminate 2.

[0044] The end of the first lead-out electrode portion 8a on the first end face E1 side is drawn out to the surface of the first end face E1 of the laminate 2. The end of the first lead-out electrode portion 8a drawn out to the first end face E! is exposed on the first end face E1.

[0045] The second internal electrode layer 6b can be divided into a second opposing electrode portion 7b and a second lead-out electrode portion 8b. The second opposing electrode portion 7b is the portion facing the first internal electrode layer 6a. The second lead-out electrode portion 8b is the portion drawn from the second opposing electrode portion 7b to the second end face E2 of the laminate 2.

[0046] The end of the second lead-out electrode portion 8b on the second end face E2 side is drawn out to the surface of the second end face E2 of the laminate 2. The end of the second lead-out electrode portion 8b drawn out to the second end face E2 is exposed on the second end face E2.

[0047] The materials of the first internal electrode layer 6a and the second internal electrode layer 6b can be, for example, metals such as nickel, copper, silver, palladium, gold, tin, etc. The materials of the first internal electrode layer 6a and the second internal electrode layer 6b can be alloys containing at least one of the aforementioned metals, such as silver-palladium alloy, etc.

[0048] In the multilayer ceramic capacitor 1, a capacitance is formed by the first opposing electrode portion 7a and the second opposing electrode portion 7b opposing each other through the inner dielectric layer 4. Thereby, the characteristics of a capacitor are exhibited in the multilayer ceramic capacitor 1.

[0049] The thickness of the first internal electrode layer 6a and the thickness of the second internal electrode layer 6b are preferably, for example, about 0.2 μm or more and 2.0 μm or less. The total number of the first internal electrode layer 6a and the second internal electrode layer 6b added together is preferably 15 or more and 2000 or less.

[0050] (Inner layer portion) A portion where the first internal electrode layer 6a and the second internal electrode layer 6b oppose each other is defined as an inner layer portion 10. The inner layer portion 10 is a portion where the length-direction opposing portion LF shown in FIG. 2, the width-direction opposing portion WF shown in FIG. 3, and the inner layer range IL overlap. The shape of the inner layer portion 10 is approximately a rectangular parallelepiped. In FIG. 2, a portion where the length-direction opposing portion LF and the inner layer range IL overlap is shown as the inner layer portion 10. Also, in FIG. 3, a portion where the width-direction opposing portion WF and the inner layer range IL overlap is shown as the inner layer portion 10.

[0051] (External electrodes) The external electrodes will be described. The external electrodes include a first external electrode 20a and a second external electrode 20b. The first external electrode 20a is an external electrode connected to the first internal electrode layer 6a. The second external electrode 20b is an external electrode connected to the second internal electrode layer 6b.

[0052] The first external electrode 20a is disposed on a part of the first end face E1, a part of the first main face M1, a part of the second main face M2, a part of the first side face S1, and a part of the second side face S2. The second external electrode 20b is disposed on a part of the second end face E2, a part of the first main face M1, a part of the second main face M2, a part of the first side face S1, and a part of the second side face S2.

[0053] The external electrodes include an underlayer electrode layer and a plating layer. The plating layer includes a Ni plating layer and a Sn plating layer. These layers are arranged in the order of the underlayer electrode layer, the Ni plating layer, and the Sn plating layer from the end face of the laminate 2.

[0054] The first external electrode 20a includes a first base electrode layer 22a, a first Ni plating layer 23a, and a first Sn plating layer 24a. The second external electrode 20b includes a second base electrode layer 22b, a second Ni plating layer 23b, and a second Sn plating layer 24b.

[0055] (Underlayment electrode layer) The first underlayment electrode layer 22a is positioned on the first end face E1 of the laminate 2 and covers the first end face E1. The first underlayment electrode layer 22a extends from the first end face E1 to a part of the first main surface M1, a part of the second main surface M2, a part of the first side surface S1, and a part of the second side surface S2.

[0056] The second base electrode layer 22b is positioned on the second end face E2 of the laminate 2 and covers the second end face E2. The second base electrode layer 22b extends from the second end face E2 to a portion of the first main surface M1, a portion of the second main surface M2, a portion of the first side surface S1, and a portion of the second side surface S2.

[0057] The underlying electrode layer contains a glass component and a metal. The glass component includes at least one selected from B, Si, Ba, Mg, Al, Li, etc. The metal includes at least one selected from, for example, Cu, Ni, Ag, Pd, Ag-Pd alloy, Au, etc.

[0058] (Ni plating layer and Sn plating layer) The first Ni plating layer 23a is arranged to cover the first under electrode layer 22a. The first Sn plating layer 24a is arranged to cover the first Ni plating layer 23a.

[0059] The second Ni plating layer 23b is positioned to cover the second under electrode layer 22b. The second Sn plating layer 24b is positioned to cover the second Ni plating layer 23b.

[0060] The Ni plating layer prevents the underlying electrode layer from being corroded by the solder used when mounting the multilayer ceramic capacitor 1. The Sn plating layer improves the wettability of the solder used when mounting the multilayer ceramic capacitor 1, making mounting easier.

[0061] Furthermore, a conductive resin layer can be placed between the base electrode layer and the Ni plating layer. The conductive resin layer may include epoxy resin and metal fillers.

[0062] The size of the multilayer ceramic capacitor 1 is not particularly limited. The preferred length of the multilayer ceramic capacitor 1, including the laminate 2 and external electrodes, is 0.2 mm to 10 mm. The preferred height of the multilayer ceramic capacitor 1, including the laminate 2 and external electrodes, is 0.1 mm to 5 mm. The preferred width of the multilayer ceramic capacitor 1, including the laminate 2 and external electrodes, is 0.1 mm to 10 mm.

[0063] (Titanium Concentration) The interface 50 between the dielectric layer 5 and the internal electrode layer 6 in the multilayer ceramic capacitor 1 of this embodiment will be described with reference to Figure 4. Figure 4 is a diagram showing a part of the cross-section of the laminate 2 parallel to the length direction L and the stacking direction T. Figure 4 shows the cross-section of the laminate 2 as observed with a scanning transmission electron microscope. Figure 4 shows an enlarged view of the interface 50 between the dielectric layer 5 and the internal electrode layer 6.

[0064] In the multilayer ceramic capacitor 1 of this embodiment, the titanium concentration at the interface 50 between the dielectric layer 5 and the internal electrode layer 6 is higher than in the parts of the dielectric layer 5 other than the interface 50. Therefore, the multilayer ceramic capacitor 1 of this embodiment can suppress the deterioration of insulation at the interface 50 between the dielectric layer 5 and the internal electrode layer 6, and in the vicinity of the interface 50 between the dielectric layer 5 and the internal electrode layer 6. This will be explained below.

[0065] Titanium has a higher affinity for oxygen than barium. In other words, titanium has a stronger ability to retain oxygen than barium.

[0066] By forming a layer with a high titanium concentration at the interface 50 between the dielectric layer 5 and the internal electrode layer 6, oxygen vacancies are less likely to form at the interface 50 between the dielectric layer 5 and the internal electrode layer 6. This is because titanium attracts a large amount of oxygen and does not release the attracted oxygen.

[0067] In the multilayer ceramic capacitor 1 of this embodiment, oxygen vacancies are less likely to form at the interface 50, so that the deterioration of insulation can be suppressed at the interface 50 between the dielectric layer 5 and the internal electrode layer 6 and in the vicinity of the interface 50.

[0068] The interface 50 refers to the boundary surface between the dielectric layer 5 and the internal electrode layer 6. The vicinity of the interface 50 refers to the range of 1 μm in each direction of the stacking direction T from the interface surface. In the region within 1 nm of the interface, Ti / Ba is 1.3 to 2.5. In the region further from the interface, Ti / Ba is approximately 0.9 to 1.1 using the same analysis method.

[0069] To increase the titanium concentration at the interface 50 between the dielectric layer 5 and the internal electrode layer 6, it is conceivable to regularly join the dielectric layer 5 and the internal electrode layer 6 at the atomic level at the interface 50. By regularly joining the dielectric layer 5 and the internal electrode layer 6 at the atomic level, the interface 50 between the dielectric layer 5 and the internal electrode layer 6, which have different lattice sizes, can be made energetically unstable. When the interface 50 becomes energetically unstable, titanium atoms are more likely to bleed into the interface 50. This is because the interface 50 is stabilized by the bleeding of titanium atoms into the interface 50.

[0070] As described above, by regularly joining the dielectric layer 5 and the internal electrode layer 6 at the atomic level, the titanium concentration at the interface 50 between the dielectric layer 5 and the internal electrode layer 6 can be increased. As a result, the deterioration of the insulating properties of the multilayer ceramic capacitor 1 can be suppressed.

[0071] Furthermore, in order to regularly join the dielectric layer 5 and the internal electrode layer 6 at the atomic level, it is necessary that the arrangement of atoms constituting the dielectric layer 5 and the arrangement of atoms constituting the internal electrode layer 6 are both aligned.

[0072] (Atomic arrangement) The atomic arrangement will be explained with reference to Figure 4. When the dielectric layer 5 and the internal electrode layer 6 are said to be regularly joined at the atomic level at the interface, it means, for example, that both the dielectric layer 5 and the internal electrode layer 6 are in contact with each other in a state where their atomic arrangements are aligned.

[0073] A state of aligned atomic arrangement refers to a state in which, for example, when observing a cross-section of the dielectric layer 5 or the internal electrode layer 6, the atoms are observed to be arranged in a regular pattern.

[0074] In the laminate 2 shown in Figure 4, the dielectric layer 5 contains barium titanate, and the internal electrode layer 6 contains nickel.

[0075] In the dielectric layer 5 shown in Figure 4, point 60 represents a barium atom, and point 62 represents a titanium atom. As shown in Figure 4, it can be observed that the barium atoms 60 and titanium atoms 62 are arranged in a regular pattern.

[0076] In the internal electrode layer 6 shown in Figure 4, the striped lines 66 represent the arrangement of nickel atoms. As shown in Figure 4, it can be observed that the nickel atoms 66 are arranged in a regular pattern.

[0077] Furthermore, in the multilayer ceramic capacitor 1 of this embodiment, the dielectric layer 5 and the internal electrode layer 6 are regularly joined at the atomic level at the interface.

[0078] (Crystal Orientation) The observed crystal orientation will be explained with reference to Figure 4. In Figure 4, the crystal orientation 100 of the crystal formed by the atoms constituting the dielectric layer 5 is observed. In other words, in Figure 4, the 100th plane of the barium titanate crystal is observed.

[0079] Furthermore, in Figure 4, the crystal orientation 110 of the crystal formed by the atoms constituting the internal electrode layer 6 is observed. In other words, in Figure 4, the 110 plane of the nickel crystal is observed.

[0080] In a cross-sectional view, 110 crystal faces of the atoms constituting the internal electrode layer 6, such as the nickel crystal of the internal electrode layer 6, can be observed, and 100 crystal faces of the atoms constituting the dielectric layer 5, such as the barium titanate crystal of the dielectric layer 5, can be observed. This makes it possible to more reliably suppress the deterioration of the insulating properties of the multilayer ceramic capacitor 1.

[0081] (Angle between alignment directions) Referring to Figure 4, the angle between the alignment direction of the atoms constituting the internal electrode layer 6 and the alignment direction of the atoms constituting the dielectric layer 5 will be explained. Line L1 in Figure 4 shows one of the alignment directions of barium atoms. Line L2 in Figure 4 shows the alignment direction L2 of nickel atoms. Angle A in Figure 4 shows the angle A between alignment direction L1 and alignment direction L2.

[0082] Furthermore, Nos. 1 to 5 in Figure 4 show the angles A when the above-mentioned angle A is measured at different positions in the longitudinal direction L at the interface 50 between the dielectric layer 5 and the internal electrode layer 6. In this embodiment, the angle A for No. 1 is 90.7 degrees, the angle A for No. 2 is 89.4 degrees, the angle A for No. 3 is 91.9 degrees, the angle A for No. 4 is 91.2 degrees, and the angle A for No. 5 is 89.3 degrees.

[0083] The angle A between the array direction L1 and the array direction L2 is preferably between 85 degrees and 95 degrees. Having the angle A within this range can further improve the reliability of the multilayer ceramic capacitor 1.

[0084] By having the angle A within the range described above, the interstitial distance of the atoms constituting the dielectric layer 5 and the interstitial distance of the atoms constituting the internal electrode layer 6 can be brought closer together at the interface 50 between the dielectric layer 5 and the internal electrode layer 6.

[0085] By reducing the interlattice distance between the layers, the junction between the dielectric layer 5 and the internal electrode layer 6 can be strengthened. As a result, the reliability of the multilayer ceramic capacitor 1 can be further improved.

[0086] Furthermore, when the angle A between the alignment direction L1 and the alignment direction L2 is between 85 degrees and 95 degrees, the overlap between the electron clouds of the atoms constituting the internal electrode layer 6 and the electron clouds of the atoms constituting the dielectric layer 5 can be increased. As a result, the junction between the dielectric layer 5 and the internal electrode layer 6 can be made stronger.

[0087] (Evaluation Method) (Titanium Concentration) The titanium concentration at the interface between the dielectric layer and the internal electrode layer can be measured using an energy-dispersive X-ray spectrometer (EDS) or the like. The titanium concentration can be measured in cross-section of the laminate.

[0088] The titanium concentration at the interface between the dielectric layer and the internal electrode layer is defined as the titanium concentration at the interface relative to the barium concentration between the dielectric layer and the internal electrode layer.

[0089] Regarding the titanium concentration of the dielectric layer, in a dielectric layer sandwiched between two adjacent internal electrode layers in the stacking direction, the titanium concentration of the dielectric layer relative to the barium concentration at an intermediate position in the stacking direction between the two internal electrode layers is defined as the titanium concentration of the dielectric layer.

[0090] (Atomic arrangement and crystal orientation) The atomic arrangement and crystal orientation can be observed by imaging a cross-section parallel to the length L and stacking direction T of the laminate using a scanning transmission electron microscope.

[0091] (Method for manufacturing a multilayer ceramic capacitor) The method for manufacturing a multilayer ceramic capacitor 1 is described below. (1) Prepare a dielectric sheet and a conductive paste for the internal electrodes. The dielectric sheet and the conductive paste for the internal electrodes contain a binder and a solvent. The binder and solvent may be known organic binders and organic solvents, etc.

[0092] (2) A conductive paste for the internal electrodes is printed on the dielectric sheet in a predetermined pattern. The internal electrode pattern is formed by printing the conductive paste. Printing can be done by, for example, screen printing or gravure printing.

[0093] (3) A predetermined number of dielectric sheets for the outer layer are stacked. The dielectric sheets for the outer layer do not have the internal electrode pattern printed on them. Dielectric sheets with the internal electrode pattern printed on them are stacked sequentially on top of the stacked dielectric sheets. Furthermore, a predetermined number of dielectric sheets for the outer layer are stacked on top of that. A laminated sheet is produced by these stacking processes.

[0094] (4) A laminated block is produced by pressing the laminated sheets in the height direction. The pressing method can be hydrostatic pressing.

[0095] (5) Cut the laminated block to the specified size. This cut will produce the laminated chips. After cutting, the corners and edges of the laminated chips may be rounded. Barrel polishing can be used to round the edges.

[0096] (6) The laminated chips are fired. This firing process produces the laminate. The preferred firing temperature is 900°C to 1200°C. The firing temperature can be changed depending on the materials of the dielectric and internal electrodes.

[0097] Cooling after heating to the firing temperature should be faster than natural cooling. For example, cooling from the firing temperature of 900°C to 1200°C to a temperature of 100°C to 300°C should be done within 5 minutes. Preferably, cooling from 1000°C to 200°C should be done within 3 minutes. More preferably, cooling from 1000°C to 200°C should be done within 1 minute.

[0098] By cooling in this way, productivity can be improved compared to simply leaving it to cool naturally.

[0099] Here, cooling does not simply mean placing the stacked chip in a gas at a predetermined temperature. Cooling means more actively cooling the stacked chip. For example, a gas at a predetermined temperature can be blown onto the stacked chip. A gas at a predetermined temperature would be, for example, nitrogen gas at 30°C or nitrogen gas cooled to 0°C. Alternatively, a solid or liquid at a predetermined temperature can be brought into contact with the stacked chip.

[0100] (External electrodes) Next, the external electrodes are formed. First, a conductive paste, which will serve as the base electrode layer, is applied to the two end faces of the laminate 2. The conductive paste contains glass components and metal components, etc. The conductive paste can be applied by methods such as dipping. After application, a baking treatment is performed to form the base electrode layer. The baking treatment temperature is preferably 500°C to 900°C. The baking treatment time is preferably 30 minutes to 2 hours.

[0101] Next, a Ni plating layer is formed on the surface of the base electrode layer. Furthermore, a Sn plating layer is formed on the surface of the Ni plating layer. The Ni plating layer and the Sn plating layer can be formed by methods such as barrel plating. In this way, a multilayer ceramic capacitor 1 is obtained.

[0102] Another embodiment of the multilayer ceramic capacitor 1 of the present invention will be described below. In the following description, the differences from the multilayer ceramic capacitor 1 described above will be mainly explained. Also, parts having similar functions, etc., will be denoted by the same reference numerals.

[0103] Another form of multilayer ceramic capacitor comprises a laminate having a plurality of stacked dielectric layers and a plurality of internal electrode layers, a first main surface and a second main surface facing each other in the stacking direction, a first side surface and a second side surface facing each other in the width direction which is perpendicular to the stacking direction, and a first end surface and a second end surface facing each other in the length direction which is perpendicular to the stacking direction and the width direction, and a plurality of external electrodes provided on the surface of the laminate and connected to a portion of the internal electrode layers, wherein when a cross section of the laminate parallel to the length direction and the stacking direction is observed with a scanning transmission electron microscope, atoms constituting the internal electrode layers and atoms constituting the dielectric layers are observed.

[0104] In recent years, multilayer ceramic capacitors have been increasingly applied to communication equipment and automotive equipment that require high capacitance and high reliability. Japanese Patent Publication No. 2013-30753 describes a technique for improving the performance of multilayer ceramic capacitors by controlling the grain diameter of the dielectric material.

[0105] However, the technology described in Japanese Patent Publication No. 2013-30753 may not provide sufficient improvement in reliability. Specifically, when used under high temperature and high humidity conditions, the insulating properties of the dielectric layer may deteriorate, potentially leading to dielectric breakdown.

[0106] Therefore, the objective of other configurations is to provide multilayer ceramic capacitors with improved capacitance without compromising reliability.

[0107] Other embodiments of the present invention will be described below.

[0108] (Observation of Atoms) The method of observing the atoms constituting the dielectric layer 5 and the atoms constituting the internal electrode layer 6 in another embodiment of the multilayer ceramic capacitor 1 will be explained with reference to Figure 4. Figure 4 is a diagram showing a part of the cross-section of the laminate 2 parallel to the length direction L and the stacking direction T. Figure 4 shows the cross-section of the laminate 2 as observed with a scanning transmission electron microscope. Figure 4 shows a magnified view of the interface 50 between the dielectric layer 5 and the internal electrode layer 6.

[0109] In the multilayer ceramic capacitor 1 of the other embodiment, when a cross-section parallel to the length L and stacking direction T of the laminate 2 is observed with a scanning transmission electron microscope, atoms constituting the internal electrode layer 6 and atoms constituting the dielectric layer 5 can be observed. Therefore, in the multilayer ceramic capacitor 1 of the other embodiment, the bonding between the dielectric layer 5 and the internal electrode layer 6 is good, the relative permittivity of the dielectric layer 5 can be improved, and the capacitance can be increased.

[0110] The atoms constituting the internal electrode layer 6 are called atoms 1. The atoms constituting the dielectric layer 5 are called atoms 2. When atoms 1 and atoms 2 are observed, the overlap between the electron clouds of atoms 1 and the atomic clouds of atoms 2 increases at the interface 50 between the dielectric layer 5 and the internal electrode layer 6. As a result, the bonding strength between the internal electrode layer 6 and the dielectric layer 5 is improved, and the tensile stress applied from the internal electrode layer 6 to the dielectric layer 5 can be increased. Consequently, in the multilayer ceramic capacitor 1 of the other embodiment, the displacement of the Ti atoms, which are the source of the relative permittivity of the dielectric layer 5, can be aligned in one direction, and a multilayer ceramic capacitor with improved capacitance can be provided.

[0111] This section explains the criteria for determining whether or not atoms are observed. Whether or not atoms are observed can be determined by the way the atomic concentration changes depending on the measurement location, as measured by an energy-dispersive X-ray fluorescence spectrometer (EDX).

[0112] Specifically, whether or not an atom is observed can be determined by the full width at half maximum (FWHM) from the peak of the atomic concentration. In another embodiment, an atom is considered to be observed if the FWHM is 0.4 nm or less. This is because when the FWHM is 0.4 nm or less, the edges of the atomic image are considered to be sharp. The measurement using an energy-dispersive X-ray fluorescence spectrometer (EDX) can be performed in the cross-section shown in Figure 4.

[0113] Let us explain this in more detail with reference to Figure 4. In the laminate 2 shown in Figure 4, the dielectric layer 5 contains barium titanate, and the internal electrode layer 6 contains nickel.

[0114] In the dielectric layer 5 shown in Figure 4, point 60 represents a barium atom, and point 62 represents a titanium atom. As shown in Figure 4, the barium atom 60 and the titanium atom 62 are clearly visible to the naked eye when observed with a scanning transmission electron microscope.

[0115] In the internal electrode layer 6 shown in Figure 4, the striped lines 66 represent the arrangement of nickel atoms. As shown in Figure 4, the nickel atoms 66 are clearly visible to the naked eye when observed with a scanning transmission electron microscope.

[0116] The results of measuring the atomic concentrations of barium atoms 60 and titanium atoms 62 contained in the dielectric layer 5 using an energy-dispersive X-ray fluorescence analyzer (EDX) showed that the above-mentioned half-width of 0.4 nm or less was met.

[0117] Furthermore, the atomic concentration of nickel atoms 66 contained in the internal electrode layer 6, measured using an energy-dispersive X-ray fluorescence analyzer (EDX), met the above-mentioned requirement of a full width at half maximum of 0.4 nm or less. The atomic concentration of nickel atoms 66 was measured while changing position in a direction perpendicular to the straight line 66.

[0118] Thus, in the multilayer ceramic capacitor 1 of the other embodiment, when a cross-section parallel to the length direction L and the stacking direction T of the laminate 2 is observed with a scanning transmission electron microscope, atoms constituting the internal electrode layer 6 and atoms constituting the dielectric layer 5 can be observed.

[0119] (Crystal Orientation) The observed crystal orientation will be explained with reference to Figure 4. In Figure 4, the crystal orientation 100 of the crystal formed by the atoms constituting the dielectric layer 5 is observed. In other words, in Figure 4, the 100th plane of the barium titanate crystal is observed.

[0120] Furthermore, in Figure 4, the crystal orientation 110 of the crystal formed by the atoms constituting the internal electrode layer 6 is observed. In other words, in Figure 4, the 110 plane of the nickel crystal is observed.

[0121] In a cross-sectional view, 110 crystal faces of the atoms constituting the internal electrode layer 6, such as nickel crystals in the internal electrode layer 6, can be observed, and 100 crystal faces of the atoms constituting the dielectric layer 5, such as barium titanate crystals in the dielectric layer 5, can be observed, thereby improving the capacitance of the multilayer ceramic capacitor 1.

[0122] (Angle between alignment directions) Referring to Figure 4, the angle between the alignment direction of the atoms constituting the internal electrode layer 6 and the alignment direction of the atoms constituting the dielectric layer 5 will be explained. Line L1 in Figure 4 shows one of the alignment directions L1 of barium atoms. Line L2 in Figure 4 shows the alignment direction L2 of nickel atoms. Angle A in Figure 4 shows the angle A between alignment direction L1 and alignment direction L2.

[0123] Furthermore, Nos. 1 to 5 in Figure 4 show the case where the angle A described above is measured at different positions in the longitudinal direction L at the interface 50 between the dielectric layer 5 and the internal electrode layer 6. In other embodiments, the angle A for No. 1 is 90.7 degrees, the angle A for No. 2 is 89.4 degrees, the angle A for No. 3 is 91.9 degrees, the angle A for No. 4 is 91.2 degrees, and the angle A for No. 5 is 89.3 degrees.

[0124] The angle A between the array direction L1 and the array direction L2 is preferably between 85 degrees and 95 degrees. Having the angle A within this range can further improve the reliability of the multilayer ceramic capacitor 1.

[0125] By having the angle A within the range described above, the interstitial distance of the atoms constituting the dielectric layer 5 and the interstitial distance of the atoms constituting the internal electrode layer 6 can be brought closer together at the interface 50 between the dielectric layer 5 and the internal electrode layer 6.

[0126] By reducing the interlattice distance between the layers, the junction between the dielectric layer 5 and the internal electrode layer 6 can be strengthened. As a result, the capacitance of the multilayer ceramic capacitor 1 can be further improved.

[0127] Furthermore, when the angle A between the alignment direction L1 and the alignment direction L2 is between 80 degrees and 90 degrees, the overlap between the electron cloud of atom 1 and the atomic cloud of atom 2 can be increased. As a result, the junction between the dielectric layer 5 and the internal electrode layer 6 can be strengthened, and the tensile stress applied from the internal electrode layer 6 to the dielectric layer 5 can be improved.

[0128] (Evaluation Method) The method for observing atoms is described below. At arbitrary positions in a cross section parallel to the length direction L and the stacking direction T at the center of the width direction W, the interface 50 between the dielectric layer 5 and the internal electrode layer 6 is observed at 100 locations using a scanning transmission electron microscope. The observation area consists of multiple 1.0 μm × 1.0 μm rectangular areas. If atoms constituting the internal electrode layer 6 and atoms constituting the dielectric layer 5 are observed at one or more of the 100 observed locations, then it is considered that atoms constituting the internal electrode layer 6 and atoms constituting the dielectric layer 5 are observed.

[0129] (Atomic arrangement and crystal orientation) The atomic arrangement and crystal orientation can be observed by imaging a cross-section parallel to the length L and stacking direction T of the laminate using a scanning transmission electron microscope.

[0130] Although embodiments of the present invention have been described above, the present invention is not limited to the embodiments described above, and various modifications and variations are possible.

[0131] 1. Multilayer ceramic capacitor 2. Laminate 3. Outer dielectric layer 4. Inner dielectric layer 5. Dielectric layer 6. Internal electrode layer 6a. First internal electrode layer 6b. Second internal electrode layer 20a. First external electrode 20b. Second external electrode 50. Interface

Claims

1. A multilayer ceramic capacitor comprising: a laminate including a plurality of stacked dielectric layers and a plurality of internal electrode layers, having a first main surface and a second main surface facing each other in the stacking direction, a first side surface and a second side surface facing each other in the width direction which is perpendicular to the stacking direction, and a first end surface and a second end surface facing each other in the length direction which is perpendicular to the stacking direction and the width direction; and a plurality of external electrodes provided on the surface of the laminate and connected to a portion of the internal electrode layers, wherein the titanium concentration at the interface between the dielectric layer and the internal electrode layer is higher than the titanium concentration of the dielectric layer.

2. When a cross-section of the laminate parallel to the longitudinal direction and the stacking direction is observed with a scanning transmission electron microscope, the crystal orientation 110 of the crystal formed by the atoms constituting the internal electrode layer is observed, and the crystal orientation 100 of the crystal formed by the atoms constituting the dielectric layer is observed, as described in claim 1.

3. The arrangement of atoms constituting the internal electrode layer is observed to be linear, and the angle between the direction of arrangement of atoms constituting the internal electrode layer and one of the directions of arrangement of atoms constituting the dielectric layer is 85 degrees or more and 95 degrees or less, as described in claim 2.

4. A multilayer ceramic capacitor comprising: a laminate including a plurality of stacked dielectric layers and a plurality of internal electrode layers, having a first main surface and a second main surface facing each other in the stacking direction, a first side surface and a second side surface facing each other in the width direction which is perpendicular to the stacking direction, and a first end surface and a second end surface facing each other in the length direction which is perpendicular to the stacking direction and the width direction; and a plurality of external electrodes provided on the surface of the laminate and connected to a portion of the internal electrode layers, wherein when a cross section of the laminate parallel to the length direction and the stacking direction is observed with a scanning transmission electron microscope, the atomic arrangement constituting the internal electrode layers and the atomic arrangement constituting the dielectric layers are observed within the same field of view.

5. When a cross-section of the laminate parallel to the longitudinal direction and the stacking direction is observed with a scanning transmission electron microscope, the crystal orientation 110 of the crystal formed by the atoms constituting the internal electrode layer is observed, and the crystal orientation 100 of the crystal formed by the atoms constituting the dielectric layer is observed, as described in claim 4.

6. The arrangement of atoms constituting the internal electrode layer is observed to be linear, and the angle between the direction of arrangement of atoms constituting the internal electrode layer and one of the directions of arrangement of atoms constituting the dielectric layer is 85 degrees or more and 95 degrees or less, as described in claim 5.

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