Semiconductor device

Abstract

A semiconductor device according to the present invention comprises: an insulating layer that covers a wiring layer and a device structure formed on a chip; a plurality of first contacts that are embedded in the insulating layer, are connected to a plurality of unit cells, and have a line width designed in accordance with a first design rule; a plurality of second contacts that are embedded in the insulating layer and connected to the wiring layer, the respective second contacts being disposed in a striped shape and having a line width designed in accordance with the first design rule using the same material as the first contacts; a first main surface electrode connected to the first contacts; and a second main surface electrode connected to the second contacts.

Description

Semiconductor Devices Related Applications

[0001] This application corresponds to Japanese Patent Application No. 2024-129233 filed with the Japan Patent Office on August 5, 2024, the entire disclosure of which is incorporated herein by reference.

[0002] The present disclosure relates to semiconductor devices.

[0003] Patent Document 1 discloses a semiconductor device including a semiconductor layer having a first main surface on one side and a second main surface on the other side, a plurality of gate electrodes arranged at intervals on the first main surface of the semiconductor layer, an interlayer insulating film formed on the first main surface of the semiconductor layer so as to cover the gate electrodes, an electrode film formed on the interlayer insulating film, and a plurality of tungsten plugs arranged between pairs of adjacent gate electrodes. The plurality of tungsten plugs are embedded in a plurality of contact openings formed in the interlayer insulating film at intervals in the direction in which the pairs of adjacent gate electrodes face each other. Each tungsten plug has a bottom portion in contact with the semiconductor layer and a top portion in contact with the electrode film.

[0004] Japanese Patent Application Laid-Open No. 2020-198425

[0005] an insulating layer covering the device structure and the wiring layer; a plurality of first contacts embedded in the insulating layer and connected to the plurality of unit cells, the first contacts having a line width designed in accordance with a first design rule; a plurality of second contacts embedded in the insulating layer and connected to the wiring layer, the plurality of second contacts being made of the same material as the first contacts, having a line width designed in accordance with the first design rule, and arranged in a stripe pattern; first main surface electrodes formed on the insulating layer and connected to the first contacts; and second main surface electrodes formed on the insulating layer and connected to the second contacts.

[0006] FIG. 1 is a plan view of a semiconductor device according to an embodiment of the present disclosure. FIG. 2 is a plan view showing the layout of a principal surface electrode film. FIG. 3 is a plan view showing the layout of an underlying wiring layer. FIG. 4 is an enlarged view of a portion surrounded by a two-dot chain line IV in FIG. 3. FIG. 5 is an enlarged view of a portion surrounded by a two-dot chain line V in FIG. 3. FIG. 6 is a cross-sectional view taken along line VI-VI in FIG. 4. FIG. 7 is a cross-sectional view taken along line VII-VII in FIG. 4. FIG. 8 is a cross-sectional view taken along line VII-VII in FIG. 5. FIGS. 9A to 9C are diagrams showing variations in the planar shapes of source contacts and gate contacts. FIG. 10 is a diagram showing a first embodiment of a gate contact layout. FIG. 11 is a diagram showing a second embodiment of a gate contact layout. FIG. 12 is a diagram showing a third embodiment of a gate contact layout. FIG. 13 is a diagram showing a fourth embodiment of a gate contact layout. FIG. 14 is a diagram showing a fifth embodiment of a gate contact layout. FIG. 15 is a diagram showing a sixth embodiment of a gate contact layout. Fig. 16 is a diagram showing a seventh embodiment of the gate contact layout. Fig. 17 is a diagram showing an eighth embodiment of the gate contact layout. Fig. 18 is a cross-sectional view showing a second embodiment of the device structure. Fig. 19 is a plan view showing a second embodiment of the gate contact arrangement pattern.

[0007] DETAILED DESCRIPTION Next, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0008] The accompanying drawings are all schematic diagrams and are not strictly illustrated, and the scale, ratio, angle, etc. are not necessarily consistent. Corresponding structures among the accompanying drawings are given the same reference numerals, and duplicated explanations have been omitted or simplified. For structures whose explanations have been omitted or simplified, the explanation given before the omission or simplification applies.

[0009] When the term "substantially" is used in this specification, this term includes a numerical value (form) that is substantially equal to the numerical value (form) of the comparison target, as well as a numerical error (form error) within a range of ±10% based on the numerical value (form) of the comparison target. In the following description, terms such as "first," "second," and "third" are used, but these are symbols attached to the names of each structure to clarify the order of description, and are not intended to limit the names of each structure.

[0010] In the following description, the conductivity type of a semiconductor (impurity) is indicated using "p-type" or "n-type," but "n-type" may also be referred to as the "first conductivity type" and "p-type" as the "second conductivity type." Of course, "p-type" may also be referred to as the "first conductivity type" and "n-type" as the "second conductivity type." "n-type" is a conductivity type resulting from a pentavalent element, and "p-type" is a conductivity type resulting from a trivalent element. Unless otherwise specified, the trivalent element is at least one of boron, aluminum, gallium, and indium. Unless otherwise specified, the pentavalent element is at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth.

[0011] (1) Planar Structure of Semiconductor Device 1 Fig. 1 is a plan view of a semiconductor device according to an embodiment of the present disclosure. Fig. 2 is a plan view showing the layout of a main surface electrode film 19. Fig. 3 is a plan view showing the layout of an underlying wiring layer 9.

[0012] The semiconductor device 1 is a semiconductor switching device having an insulated gate transistor structure Tr as an example of a device structure. The transistor structure Tr has a planar gate vertical structure.

[0013] 1 to 3, semiconductor device 1 includes chip 2 formed in a hexahedral shape (specifically, a rectangular parallelepiped shape). In this embodiment, chip 2 includes a single crystal of a wide bandgap semiconductor. In other words, semiconductor device 1 is a "wide bandgap semiconductor device." Chip 2 may also be referred to as a "semiconductor chip," a "wide bandgap semiconductor chip," or the like.

[0014] A wide bandgap semiconductor is a semiconductor having a bandgap that exceeds the bandgap of Si (silicon). Examples of wide bandgap semiconductors include GaN (gallium nitride), SiC (silicon carbide), and C (diamond). In this embodiment, the chip 2 is a "SiC chip" that includes a hexagonal SiC single crystal as an example of a wide bandgap semiconductor. In other words, the semiconductor device 1 is a "SiC semiconductor device."

[0015] Hexagonal SiC single crystal has a plurality of polytypes including 2H (Hexagonal)-SiC single crystal, 4H-SiC single crystal, 6H-SiC single crystal, etc. In this embodiment, an example is shown in which the chip 2 includes a 4H-SiC single crystal, but the chip 2 may also include other polytypes.

[0016] The chip 2 has a first main surface 3 on one side, a second main surface 4 (not shown in FIGS. 1 to 3 ) on the other side, and first to fourth side surfaces 5A to 5D connecting the first main surface 3 and the second main surface 4. The first main surface 3 and the second main surface 4 are formed in a quadrangular shape when viewed in a plan view from the vertical direction Z (hereinafter simply referred to as a "plan view"). The vertical direction Z is also the thickness direction of the chip 2 and the normal direction to the first main surface 3 (second main surface 4). The first main surface 3 and the second main surface 4 may be formed in a square or rectangular shape when viewed in a plan view.

[0017] The first main surface 3 and the second main surface 4 are preferably formed by the c-plane of the SiC single crystal. In this case, the first main surface 3 is preferably formed by the silicon surface ((0001) surface) of the SiC single crystal, and the second main surface 4 is preferably formed by the carbon surface ((000-1) surface) of the SiC single crystal. The first main surface 3 and the second main surface 4 may have an off-angle inclined at a predetermined angle in a predetermined off-direction with respect to the c-plane. The off-direction is preferably the a-axis direction ([11-20] direction) of the SiC single crystal. The off-angle may be greater than 0° and not more than 10°. The off-angle is preferably not more than 5°.

[0018] The first side surface 5A and the second side surface 5B extend in a first direction X along the first main surface 3 and face a second direction Y that intersects with the first direction X along the first main surface 3. Specifically, the second direction Y is perpendicular to the first direction X. The third side surface 5C and the fourth side surface 5D extend in the second direction Y and face the first direction X.

[0019] In this embodiment, the first direction X is the m-axis direction ([1-100] direction) of the SiC single crystal, and the second direction Y is the a-axis direction ([11-20] direction) of the SiC single crystal. Of course, the first direction X may be the a-axis direction of the SiC single crystal, and the second direction Y may be the m-axis direction of the SiC single crystal.

[0020] The XY plane including the first direction X and the second direction Y forms a horizontal plane perpendicular to the vertical direction Z. Hereinafter, an axis extending along the vertical direction Z may be referred to as a "vertical axis." Also, below, the first direction X and the second direction Y may be referred to as a "horizontal direction." The horizontal direction is also a direction extending along the first main surface 3.

[0021] The first to fourth side surfaces 5A to 5D may have lengths of 0.5 mm or more and 20 mm or less in plan view. The lengths of the first to fourth side surfaces 5A to 5D may have a value that belongs to any one of the ranges of 0.5 mm or more and 1 mm or less, 1.5 mm or more and 2 mm or less, 2 mm or more and 5 mm or less, 5 mm or more and 10 mm or less, 10 mm or more and 15 mm or less, and 15 mm or more and 20 mm or less. The lengths of the first to fourth side surfaces 5A to 5D may be 5 mm or more.

[0022] 3, semiconductor device 1 includes an active region 6 and a peripheral region 7 defined on first main surface 3 of chip 2. FIGS. 1 to 3 are diagrams showing layer structures formed on active region 6 and peripheral region 7, layer by layer. Of FIGS. 1 to 3, FIG. 3 shows the lowest layer, FIG. 2 shows a layer above FIG. 1, and FIG. 3 shows a layer above FIG. 2.

[0023] Referring to FIG. 3 , the active region 6 includes a device structure (i.e., a transistor structure Tr) and is a region (element region) where an output current (drain current) is generated. The active region 6 is set in an inner portion of the chip 2 at a distance from the periphery of the chip 2 (first to fourth side surfaces 5A to 5D) in a plan view. The active region 6 is formed in a polygonal shape having sides parallel to the periphery of the chip 2 in a plan view. In this embodiment, the active region 6 is formed in a polygonal shape having a recessed portion along a gate pad electrode 24 (described later) in a plan view. The active region 6 may also be formed in a quadrangular shape in a plan view. The planar area of ​​the active region 6 is preferably 50% to 90% of the planar area of ​​the first main surface 3.

[0024] The peripheral region 7 is a region that does not include a device structure (transistor structure Tr). In plan view, the peripheral region 7 is provided in a region between the periphery of the chip 2 and the active region 6. In plan view, the peripheral region 7 extends in a strip shape along the active region 6 and is set in a polygonal ring shape (a square ring in this embodiment) that surrounds the active region 6.

[0025] 3 , the semiconductor device 1 includes a plurality of gate electrodes 8 formed on the first main surface 3 in the active region 6. A gate potential is applied to the plurality of gate electrodes 8 as a control potential. In this embodiment, the plurality of gate electrodes 8 are arranged at intervals in the second direction Y (m-axis direction) and are formed in stripes extending in the first direction X (a-axis direction). In this embodiment, the plurality of gate electrodes 8 are arranged in stripes extending in the a-axis direction (first direction X). The extending direction of the plurality of gate electrodes 8 coincides with the off direction of the chip 2.

[0026] 3 , the semiconductor device 1 includes an underlying wiring layer 9 as an example of a wiring layer formed on the first main surface 3 in the peripheral region 7. The underlying wiring layer 9 supplies current from a gate pad electrode 24 (described later) to a plurality of gate electrodes 8. The underlying wiring layer 9 is disposed in the same layer as an electrode (in this embodiment, the gate electrode 8) of a device structure (transistor structure Tr). In this embodiment, the underlying wiring layer 9 is an underlying layer for a metallic main surface electrode film 19 (described later) on an interlayer insulating film 18 (described later), and is laid out directly below the main surface electrode film 19. For clarity, in FIG. 3 , the formation regions of the underlying wiring layer 9 and the gate electrodes 8 are indicated by hatching, and the outline of the main surface electrode film 19 above the underlying wiring layer 9 is indicated by a dashed line.

[0027] In this embodiment, the underlying wiring layer 9 is made of the same material as the gate electrode 8 and is formed integrally with the gate electrode 8. The underlying wiring layer 9 and the gate electrode 8 may contain either or both of p-type conductive polysilicon and n-type conductive polysilicon.

[0028] The underlying wiring layer 9 includes a base portion 10 and an extension portion 11. The base portion 10 is disposed directly below a gate pad electrode 24 (described later). The base portion 10 is formed in a ring shape surrounding the periphery of the gate pad electrode 24 in a plan view. The base portion 10 is disposed near one of the first to fourth side surfaces 5A to 5D of the chip 2. In this embodiment, the base portion 10 is disposed close to the first side surface 5A at the center of the first side surface 5A in the first direction X.

[0029] The extension portion 11 extends outward in a strip shape from the outer edge of the annular base portion 10. The semiconductor device 1 includes a plurality of extension portions 12 to 14 that extend in strip shapes in different directions from the outer edge of the base portion 10. The plurality of extension portions 12 to 14 are arranged in a non-parallel positional relationship with each other. The plurality of extension portions 12 to 14 may include a first extension portion 12, a second extension portion 13, and a third extension portion 14.

[0030] The first extension 12 and the second extension 13 extend from the base 10 in opposite directions along the periphery of the chip 2, surrounding the active region 6 as a whole. In this embodiment, the first extension 12 extends from the base 10 in the first direction X along the first side surface 5A, the third side surface 5C, and the second side surface 5B in this order, and has a first tip 15 at the center of the fourth side surface 5D in the first direction X. The second extension 13 extends from the base 10 in the first direction X along the first side surface 5A, the fourth side surface 5D, and the second side surface 5B in this order, and has a second tip 16 at the center of the fourth side surface 5D in the first direction X. The first tip 15 and the second tip 16 face each other in the first direction X with a space S between them.

[0031] The first extension 12 and the second extension 13 are each formed in a substantially U-shape in a plan view, and have a corner C2 at a position corresponding to a corner C of the chip 2. The first extension 12 may be referred to as, for example, a "first peripheral underlay wiring," a "first peripheral underlay electrode," a "first peripheral underlay finger wiring," a "first peripheral underlay finger electrode," or the like. The second extension 13 may be referred to as, for example, a "second peripheral underlay wiring," a "second peripheral underlay electrode," a "second peripheral underlay finger wiring," a "second peripheral underlay finger electrode," or the like. The first extension 12 and the second extension 13 may be collectively referred to as a "peripheral underlay wiring," a "peripheral underlay electrode," a "peripheral underlay finger wiring," a "peripheral underlay finger electrode," or the like that surround the active region 6.

[0032] The third extension 14 extends from the base 10 toward the center of the chip 2 and crosses the active region 6. The third extension 14 may extend from the base 10 toward the second side surface 5B and divide the active region 6 into left and right sides (both sides of the third side surface 5C and the fourth side surface 5D). The third extension 14 has a third tip 17 located inside the area surrounded by the first extension 12 and the second extension 13. The third tip 17 is disposed closer to the active region 6 than the first tip 15 and the second tip 16. The third tip 17 faces the space S between the first tip 15 and the second tip 16 in the second direction Y. The third extension 14 may be referred to as, for example, a "central underlying wiring," a "central underlying electrode," a "central underlying finger wiring," a "central underlying finger electrode," or the like.

[0033] The plurality of gate electrodes 8 may be arranged across two different locations on the underlying wiring layer 9. One end and the other end of each strip-shaped gate electrode 8 are connected to two different locations on the underlying wiring layer 9. In this embodiment, the plurality of gate electrodes 8 electrically connect between the base portion 10 and the first extension portion 12, between the base portion 10 and the second extension portion 13, between the first extension portion 12 and the third extension portion 14, and between the second extension portion 13 and the third extension portion 14.

[0034] 2, the semiconductor device 1 includes an interlayer insulating film 18 as an example of an insulating layer that covers the underlying wiring layer 9, and a main surface electrode film 19 disposed on the interlayer insulating film 18. In Fig. 2, the interlayer insulating film 18 is shown as a white region, and the main surface electrode film 19 is shown as a hatched region. To clarify the positional relationship between the main surface electrode film 19 and the underlying wiring layer 9, the outline of a gate electrode film 21 of the main surface electrode film 19 is shown by a dashed line in Fig. 3.

[0035] The interlayer insulating film 18 may be formed, for example, over the entire first main surface 3. The interlayer insulating film 18 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The interlayer insulating film 18 may also be referred to as an "insulating layer," an "interlayer film," an "intermediate insulating film," or the like.

[0036] The principal surface electrode film 19 includes a source electrode film 20 as an example of a first principal surface electrode, and a gate electrode film 21 as an example of a second principal surface electrode.

[0037] The source electrode film 20 is a film that is physically and electrically separated from the gate electrode film 21. The source electrode film 20 is disposed on the interlayer insulating film 18 at a distance from the gate electrode film 21. The source electrode film 20 is an electrode to which a source potential is applied from the outside. The source electrode film 20 may also be called a "first main surface electrode," a "source pad electrode," a "source metal," a "first pad electrode," or the like.

[0038] The source electrode film 20 is formed of a metal material containing Al (aluminum). The source electrode film 20 includes an Al-based metal film. The source electrode film 20 may include at least one of a pure Al film (an Al film with a purity of 99% or more), an AlCu alloy film, an AlSi alloy film, and an AlSiCu alloy film. The source electrode film 20 may also be a metal film other than an Al-based metal film. The source electrode film 20 may include at least one of a Ti film, a TiN film, a W film, a Cu film, a Cu alloy film, and a conductive polysilicon film.

[0039] In this embodiment, the source electrode film 20 is disposed on the active region 6 in a planar view. The source electrode film 20 is formed in a polygonal shape in a planar view. The source electrode film 20 includes a first source electrode film 22 and a second source electrode film 23 that are separated from each other. In this embodiment, the source electrode film 20 includes the first source electrode film 22 disposed in a region closer to the third side surface 5C than a central position in the first direction X of the active region 6 (first main surface 3), and the second source electrode film 23 disposed in a region closer to the fourth side surface 5D than the central position. The first source electrode film 22 and the second source electrode film 23 may be connected to each other at their ends on the second side surface 5B side.

[0040] The gate electrode film 21 is an electrode to which a gate potential is applied from the outside. The gate electrode film 21 may also be called a "second main surface electrode," a "gate pad electrode 24," a "gate metal," a "second pad electrode," or the like.

[0041] The gate electrode film 21 is formed of a metal material containing Al (aluminum). The gate electrode film 21 includes an Al-based metal film. The gate electrode film 21 may include at least one of a pure Al film (an Al film with a purity of 99% or more), an AlCu alloy film, an AlSi alloy film, and an AlSiCu alloy film. The gate electrode film 21 may also be a metal film other than an Al-based metal film. The gate electrode film 21 may include at least one of a Ti film, a TiN film, a W film, a Cu film, a Cu alloy film, and a conductive polysilicon film.

[0042] The gate electrode film 21 includes a gate pad electrode 24 and a gate wiring 25. In this embodiment, the gate pad electrode 24 is disposed on the peripheral region 7. Specifically, the gate pad electrode 24 is disposed in a region close to the center of one side of the first main surface 3 (the first side surface 5A in this embodiment) in a plan view. The gate pad electrode 24 is disposed in a recess formed in the source electrode film 20. The gate pad electrode 24 may be disposed in a region along the center of any of the first to fourth side surfaces 5A to 5D. The gate pad electrode 24 may be disposed at any corner C of the chip 2 on the first main surface 3 in a plan view. The gate pad electrode 24 may be disposed in the center of the first main surface 3 in a plan view. The gate pad electrode 24 may be disposed on the active region 6. In this embodiment, the gate pad electrode 24 is formed in a quadrangular shape in a plan view.

[0043] The gate wiring 25 is routed from the gate pad electrode 24 around the periphery of the active region 6, surrounding the active region 6. The gate wiring 25 transmits the gate potential applied to the gate pad electrode 24 to the plurality of gate electrodes 8.

[0044] The gate wiring 25 includes a base wiring 26 and finger wiring 27. The base wiring 26 is disposed directly above the base portion 10 of the underlying wiring layer 9. The base wiring 26 is formed in a ring shape that overlaps the base portion 10, and surrounds the periphery of the gate pad electrode 24 in a plan view.

[0045] The finger wirings 27 extend outward in a strip shape from the outer edge of the annular base wiring 26. The semiconductor device 1 includes a plurality of finger wirings 28 to 30 extending in strip shapes in different directions from the outer edge of the base wiring 26. The plurality of finger wirings 28 to 30 are arranged in a non-parallel positional relationship with each other. The plurality of finger wirings 28 to 30 may include a first finger wiring 28, a second finger wiring 29, and a third finger wiring 30.

[0046] The first finger wiring 28 and the second finger wiring 29 extend from the base wiring 26 in opposite directions along the periphery of the chip 2, surrounding the source electrode film 20 as a whole. In this configuration, the first finger wiring 28 extends from the base wiring 26 along the first side surface 5A, the third side surface 5C, and the second side surface 5B in this order in the first direction X, and has a first tip 31 at the center of the fourth side surface 5D in the first direction X. The second finger wiring 29 extends from the base wiring 26 along the first side surface 5A, the fourth side surface 5D, and the second side surface 5B in this order in the first direction X, and has a second tip 32 at the center of the fourth side surface 5D in the first direction X. The first tip 31 and the second tip 32 face each other in the first direction X with a space S2 between them.

[0047] The first finger wiring 28 and the second finger wiring 29 are each formed in a substantially U-shape in plan view so as to overlap the first extension portion 12 and the second extension portion 13, and have a corner C3 at a position corresponding to the corner C of the chip 2. The first finger wiring 28 may be referred to as, for example, a "first peripheral wiring," a "first peripheral electrode," a "first peripheral finger wiring," a "first peripheral finger electrode," etc. The second finger wiring 29 may be referred to as, for example, a "second peripheral wiring," a "second peripheral electrode," a "second peripheral finger wiring," a "second peripheral finger electrode," etc. The first finger wiring 28 and the second finger wiring 29 may be collectively referred to as a "peripheral wiring," a "peripheral electrode," a "peripheral finger wiring," a "peripheral finger electrode," etc. that surround the active region 6.

[0048] The third finger wiring 30 extends from the base wiring 26 toward the center of the chip 2 and crosses the source electrode film 20. The third finger wiring 30 may extend from the base wiring 26 toward the second side surface 5B and divide the source electrode film 20 into a first source electrode film 22 and a second source electrode film 23. The third finger wiring 30 has a third tip portion 33 inside the region surrounded by the first finger wiring 28 and the second finger wiring 29. The third finger wiring 30 may be referred to as, for example, a "central wiring," a "central electrode," a "central finger wiring," a "central finger electrode," or the like.

[0049] 1 , the semiconductor device 1 includes a surface insulating film 34 that selectively covers the main surface electrode film 19 and the interlayer insulating film 18 on the first main surface 3. The surface insulating film 34 includes a gate pad opening 36 that exposes a portion of the gate pad electrode 24 as a gate pad 35. The surface insulating film 34 covers the periphery of the gate pad electrode 24 and the entire area of ​​the gate wiring 25. The gate pad opening 36 is formed in a quadrangular shape in a plan view.

[0050] 1 , the surface insulating film 34 includes a first source pad opening 38 that exposes a part of the first source electrode film 22 as a first source pad 37, and a second source pad opening 40 that exposes a part of the second source electrode film 23 as a second source pad 39. The surface insulating film 34 covers the peripheral edge of the first source electrode film 22 and the peripheral edge of the second source electrode film 23.

[0051] The first source pad opening 38 is formed in a polygonal shape that follows the peripheral edge of the first source electrode film 22 in a plan view. The second source pad opening 40 is formed in a polygonal shape that follows the peripheral edge of the second source electrode film 23 in a plan view. The planar areas of the first source pad opening 38 and the second source pad opening 40 are preferably larger than the planar area of ​​the gate pad opening 36.

[0052] The surface insulating film 34 may have a layered structure including an inorganic insulating film and an organic insulating film stacked in this order from the chip 2 side, for example. The surface insulating film 34 may include at least one of an inorganic insulating film and an organic insulating film, and does not necessarily have to include both an inorganic insulating film and an organic insulating film at the same time. The inorganic insulating film may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The inorganic insulating film preferably includes an insulating material different from that of the interlayer insulating film 18. The organic insulating film is preferably made of a polyimide film, a polyamide film, or a polybenzoxazole film. In this embodiment, the organic insulating film includes a polybenzoxazole film.

[0053] (2) Internal Planar Structure and Cross-Sectional Structure of Semiconductor Device 1 Next, the internal planar structure and cross-sectional structure of the semiconductor device 1 will be described in detail with reference to FIGS. 4 to 8. FIG. 4 is an enlarged view of a portion surrounded by a two-dot chain line IV shown in FIG. 3. FIG. 5 is an enlarged view of a portion surrounded by a two-dot chain line V shown in FIG. 3. FIG. 6 is a cross-sectional view taken along line VI-VI shown in FIG. 4. FIG. 7 is a cross-sectional view taken along line VII-VII shown in FIG. 4. FIG. 8 is a cross-sectional view taken along line VII-VII shown in FIG. 5.

[0054] 6 to 8, semiconductor device 1 includes an n-type first semiconductor layer 41 formed in a surface layer portion of second main surface 4. A drain potential is applied to first semiconductor layer 41 as a first potential (high potential). First semiconductor layer 41 may also be referred to as a "semiconductor region (layer)," a "base region (layer)," a "drain region (layer)," or the like.

[0055] The first semiconductor layer 41 extends in a layered form along the second main surface 4, and forms the second main surface 4 and first to fourth side surfaces 5A to 5D. In this embodiment, the first semiconductor layer 41 is made of an n-type semiconductor layer. Specifically, the first semiconductor layer 41 is made of a substrate (SiC substrate) containing SiC single crystal (semiconductor single crystal), and has the second main surface 4 and first to fourth side surfaces 5A to 5D. In this embodiment, the first semiconductor layer 41 is made of a substrate made of SiC single crystal (i.e., a SiC substrate).

[0056] The first semiconductor layer 41 has a thickness of 1×10 １８ cm －３1x10 or more ２１ cm －３ The n-type impurity concentration may have the following peak value: The first semiconductor layer 41 preferably has a substantially constant n-type impurity concentration in the thickness direction.

[0057] The first semiconductor layer 41 may have a thickness of 10 μm or more and 500 μm or less. The thickness of the first semiconductor layer 41 may have a value belonging to at least one of the ranges of 10 μm or more and 50 μm or less, 50 μm or more and 100 μm or less, 100 μm or more and 150 μm or less, 150 μm or more and 200 μm or less, 200 μm or more and 300 μm or less, 300 μm or more and 400 μm or less, and 400 μm or more and 500 μm or less.

[0058] 6 to 8 , the semiconductor device 1 includes a drain pad electrode 42 covering the second main surface 4. The drain pad electrode 42 is mechanically and electrically connected to the first semiconductor layer 41. The drain pad electrode 42 forms ohmic contact with the first semiconductor layer 41.

[0059] The drain pad electrode 42 may cover the entire second main surface 4 so as to be continuous with the periphery (first to fourth side surfaces 5A to 5D) of the second main surface 4. The drain pad electrode 42 may also cover part of the second main surface 4 so as to expose the periphery of the second main surface 4.

[0060] A breakdown voltage that can be applied between the source electrode film 20 and the drain pad electrode 42 (between the first main surface 3 and the second main surface 4) may be 500 V or more and 3000 V or less. The breakdown voltage may have a value belonging to at least one of the ranges of 500 V or more and 750 V or less, 750 V or more and 1000 V or less, 1000 V or more and 1250 V or less, 1250 V or more and 1500 V or less, 1500 V or more and 1750 V or less, 1750 V or more and 2000 V or less, 2000 V or more and 2250 V or less, 2250 V or more and 2500 V or less, and 2500 V or more and 3000 V or less.

[0061] 6 to 8, semiconductor device 1 includes an n-type second semiconductor layer 43 formed in a surface layer portion of first main surface 3. Second semiconductor layer 43 may also be referred to as a "semiconductor region (layer)," a "drift region (layer)," or the like. Second semiconductor layer 43 extends in a layered form along first main surface 3, and forms first main surface 3 and first to fourth side surfaces 5A to 5D.

[0062] In this embodiment, the second semiconductor layer 43 is an n-type semiconductor layer. The second semiconductor layer 43 may be an epitaxial layer (SiC epitaxial layer) containing a SiC single crystal (semiconductor single crystal). The second semiconductor layer 43 is an epitaxial layer (i.e., a SiC epitaxial layer) grown from the first semiconductor layer 41.

[0063] The second semiconductor layer 43 has a lower end and an upper end. The lower end of the second semiconductor layer 43 is the starting point of crystal growth, and the upper end of the second semiconductor layer 43 is the ending point of crystal growth. The lower end of the second semiconductor layer 43 is also the bottom of the second semiconductor layer 43. Because the second semiconductor layer 43 is grown continuously from the first semiconductor layer 41, the lower end of the second semiconductor layer 43 coincides with the upper end of the first semiconductor layer 41.

[0064] The second semiconductor layer 43 includes an n-type drift region 44 as an example of a first impurity region. In this embodiment, the drift region 44 is formed by a part (n-type portion) of the second semiconductor layer 43.

[0065] The second semiconductor layer 43 has a thickness less than the thickness of the first semiconductor layer 41. The thickness of the second semiconductor layer 43 may be 5 μm or more and 15 μm or less. The thickness of the second semiconductor layer 43 may have a value belonging to at least one of the ranges of 5 μm or more and 7.5 μm or less, 7.5 μm or more and 10 μm or less, 10 μm or more and 12.5 μm or less, and 12.5 μm or more and 15 μm or less.

[0066] 6 and 8 , the semiconductor device 1 includes a plurality of p-type body regions 45 formed in the active region 6. In this embodiment, the plurality of body regions 45 are arranged at intervals in the second direction Y and are each formed in a strip shape extending in the first direction X. The plurality of body regions 45 are arranged in a stripe shape as a whole. Each body region 45 provides a unit cell UC of a planar gate transistor. Each unit cell UC includes at least a body region 45 and a source region 46 (described later), and may be the minimum unit that functions as a MIS transistor.

[0067] The plurality of body regions 45 may be, for example, 1×10 １５ cm －３ 1x10 or more １８ cm －３ The p-type impurity concentration may have a peak value of 0.01 μm or less. The pitch between the plurality of body regions 45 (the pitch BP of the unit cells (UCs)) is, for example, 2.2 μm or more and 4.2 μm or less. The pitch BP may have a value belonging to at least one of the ranges of 2.2 μm or more and 2.6 μm or less, 2.6 μm or more and 3.0 μm or less, 3.0 μm or more and 3.4 μm or less, 3.4 μm or more and 3.8 μm or less, and 3.8 μm or more and 4.2 μm or less. The pitch BP may be the distance between adjacent body regions 45.

[0068] 4, 5 and 6, semiconductor device 1 includes one or more n-type source regions 46 formed in the surface layer portions of the plurality of body regions 45 in active region 6. In this embodiment, a plurality of (two in this embodiment) source regions 46 are formed at intervals in the surface layer portion of each body region 45. The plurality of source regions 46 have an n-type impurity concentration higher than the n-type impurity concentration of drift region 44. The plurality of source regions 46 have an n-type impurity concentration of 1×10 １８ cm －３ 1x10 or more ２１ cm －３ The n-type impurity concentration may have the following peak value:

[0069] The plurality of source regions 46 may each extend in a strip shape along the extension direction of the corresponding body region 45. Of course, the plurality of source regions 46 may be formed at intervals along the extension direction of the corresponding body region 45. The plurality of source regions 46 are formed at intervals from the bottom of the corresponding body region 45 toward the first main surface 3, and are formed at intervals inward from the periphery of the corresponding body region 45. Referring to FIG. 6 , the plurality of source regions 46 define a channel region 47 along the first main surface 3 at the periphery of the body region 45.

[0070] 6 and 8 , the semiconductor device 1 includes one or more p-type body contact regions 48 formed in the surface layer portions of the plurality of body regions 45 in the active region 6. The body contact region 48 may also be referred to as a "back gate region." In this embodiment, one body contact region 48 is formed in a region between the plurality of source regions 46 adjacent to each other in the surface layer portion of each body region 45.

[0071] The plurality of body contact regions 48 have a p-type impurity concentration (peak value) higher than the p-type impurity concentration (peak value) of the plurality of body regions 45. The plurality of body contact regions 48 have a p-type impurity concentration (peak value) higher than the p-type impurity concentration (peak value) of the plurality of body regions 45. １８ cm －３ 1x10 or more ２１ cm －３ The p-type impurity concentration may have the following peak value:

[0072] The body contact regions 48 may each extend in a strip shape along the extension direction of the corresponding body region 45. Of course, the body contact regions 48 may also be formed at intervals along the extension direction of the corresponding body region 45. The body contact regions 48 are formed at intervals from the bottom of the corresponding body region 45 toward the first main surface 3, and are formed at intervals inward from the peripheral edge of the corresponding body region 45.

[0073] 7, the semiconductor device 1 includes a p-type periphery well region 49 formed in the active region 6. In this embodiment, the periphery well region 49 is formed in the periphery region 7, spaced apart from the body region 45. The periphery well region 49 may be formed throughout the entire periphery region 7, and exposed from the first to fourth side surfaces 5A to 5D. The p-type impurity concentration of the periphery well region 49 may be the same as the p-type impurity concentration of the body region 45. The periphery well region 49 has a p-type impurity concentration of, for example, 1×10 １５ cm －３ 1x10 or more １８ cm －３ The p-type impurity concentration may have the following peak value:

[0074] 4 to 6 and 8, the plurality of gate electrodes 8 are arranged at intervals on the first main surface 3 so as to overlap with at least one channel region 47 in the stacking direction. The plurality of gate electrodes 8 control the inversion and non-inversion of the channel (current path) in the body region 45 in response to a gate potential.

[0075] 6 , the semiconductor device 1 includes a gate insulating film 50 disposed between the plurality of gate electrodes 8 and the first main surface 3. The gate insulating film 50 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the gate insulating film 50 has a single-layer structure made of a silicon oxide film. The gate insulating film 50 may include a silicon oxide film made of an oxide of the chip 2.

[0076] 7 and 8 , semiconductor device 1 includes a main surface insulating film 51 disposed between underlying wiring layer 9 and first main surface 3. Main surface insulating film 51 is formed integrally with gate insulating film 50. Main surface insulating film 51 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, main surface insulating film 51 has a single-layer structure made of a silicon oxide film. Main surface insulating film 51 may include a silicon oxide film made of an oxide of chip 2.

[0077] 4 to 6 and 8, a plurality of source contact openings 52 are formed in the interlayer insulating film 18 in a region between the pair of gate electrodes 8, i.e., directly above the body region 45. The plurality of source contact openings 52 penetrate the interlayer insulating film 18 and the gate insulating film 50. The plurality of source contact openings 52 are arranged at intervals in the direction in which the pair of gate electrodes 8 face each other, i.e., in the second direction Y.

[0078] In this embodiment, the multiple source contact openings 52 are formed in strips extending along the first direction X, one for each unit cell UC. Multiple source contact openings 52 may be formed in each unit cell UC. For example, multiple strip-shaped source contact openings 52 may be formed in each unit cell UC along the first direction X, or relatively short strip-shaped source contact openings 52 may be arranged in a line along the first direction X for each unit cell UC.

[0079] A source contact 53, which is an example of a first contact, is buried in the source contact opening 52. The source contact 53 includes a first barrier layer 54 and a first plug layer 55. The first barrier layer 54 is a thin metal layer formed to cover the inner surface of the source contact opening 52. The first barrier layer 54 defines a groove-shaped first recess 56 corresponding to the shape of the source contact opening 52 on its inside. A first plug layer 55 is buried in this first recess 56.

[0080] 6 , the first barrier thickness BT1 of the first barrier layer 54 is, for example, not less than 1000 Å and not more than 1500 Å. The first barrier thickness BT1 may have a value belonging to at least one of the ranges of not less than 1000 Å and not more than 1100 Å, not more than 1100 Å and not more than 1200 Å, not more than 1200 Å and not more than 1300 Å, not more than 1300 Å and not more than 1400 Å, and not more than 1400 Å and not more than 1500 Å.

[0081] The first barrier layer 54 mainly suppresses or prevents the constituent material of the first plug layer 55 (for example, tungsten) from diffusing into the interlayer insulating film 18. The first barrier layer 54 includes, for example, one or both of Ti and TiN. The first barrier layer 54 may be a laminated film in which a Ti film and a TiN film are stacked.

[0082] 6 , the first recess width RW1 of the first recess 56 may be one to three times the first barrier thickness BT1. The first recess width RW1 may be, for example, 0.1 μm to 3 μm. The first recess width RW1 may have a value belonging to at least one of the following ranges: 0.1 μm to 0.5 μm, 0.5 μm to 1.0 μm, 1.0 μm to 2.0 μm, and 2.0 μm to 3.0 μm.

[0083] The source contacts 53 are buried in the source contact openings 52, and are therefore provided in the same arrangement as the source contact openings 52. That is, a plurality of source contacts 53 are arranged in the region between the pair of gate electrodes 8, i.e., directly above the body region 45.

[0084] The source contact 53 is connected to the source region 46 and the body contact region 48 within the source contact opening 52. The source contact 53 is electrically connected to the body region 45 via the body contact region 48.

[0085] 6, the source contact 53 has a first contact width W1 designed in accordance with a first design rule. The "design rule" is, for example, a design constraint that must be observed for the circuit of the MIS transistor Tr to operate normally. Examples of the constraint include dimensional constraints such as a minimum wiring width and a minimum distance between wirings.

[0086] In this embodiment, the first contact width W1 is, for example, 0.3 μm to 0.5 μm. The first contact width W1 may have a value belonging to at least one of the following ranges: 0.3 μm to 0.35 μm, 0.35 μm to 0.4 μm, 0.4 μm to 0.45 μm, and 0.45 μm to 0.5 μm. The first contact width W1 is, for example, the dimension of the source contact 53 in a direction perpendicular to the longitudinal direction of the source contact 53.

[0087] 4 and 5 , the first pitch P1 of the source contacts 53 connected to adjacent unit cells UC is, for example, 2.2 μm to 4.2 μm. The first pitch P1 may have a value belonging to at least one of the following ranges: 2.2 μm to 2.6 μm, 2.6 μm to 3.0 μm, 3.0 μm to 3.4 μm, 3.4 μm to 3.8 μm, and 3.8 μm to 4.2 μm. The first pitch P1 may be the distance between adjacent source contacts 53.

[0088] 6 , the first contact thickness T1 of the source contact 53 (the depth of the source contact opening 52) is, for example, 0.3 μm to 2.0 μm. The first contact thickness T1 may have a value belonging to at least one of the ranges of 0.3 μm to 0.8 μm, 0.8 μm to 1.3 μm, 1.3 μm to 1.8 μm, and 1.8 μm to 2.0 μm. The first contact thickness T1 is, for example, the dimension of the source contact 53 in the depth direction of the source contact opening 52.

[0089] The first aspect ratio (T1 / W1), which is the ratio of the first contact thickness T1 to the first contact width W1, is, for example, not less than 1 and not more than 6.7. The first aspect ratio (T1 / W1) may have a value belonging to at least one of the ranges of not less than 1 and not more than 2, not more than 2 and not more than 3, not more than 3 and not more than 4, not more than 4 and not more than 5, not more than 5 and not more than 6, and not more than 6 and not more than 6.7.

[0090] Next, prior to describing the gate contact 65 (described later) connected to the underlying wiring layer 9, a detailed description will be given of the configuration of the underlying wiring layer 9.

[0091] 4, the base portion 10 is formed in a ring shape surrounding the gate pad electrode 24 in a plan view. In this embodiment, the base portion 10 is formed in a quadrangular ring shape parallel to the four sides of the gate pad electrode 24, which is quadrangular in a plan view. The base portion 10 has a first portion 101, a second portion 102, a third portion 103, and a fourth portion 104 corresponding to each side of the quadrangular ring shape.

[0092] The first portion 101 is disposed in a position of the base portion 10 close to the side surface of the chip 2 (in this embodiment, the first side surface 5A). The first portion 101 is the base end of the first extension portion 12 and the second extension portion 13, and may form a strip-shaped finger base portion integrally with the first extension portion 12 and the second extension portion 13. The first portion 101 has a gate protrusion 57 that protrudes toward the inside of the gate pad electrode 24 in a plan view. The gate protrusion 57 is disposed at a distance from the third portion 103 and the fourth portion 104. As a result, the internal opening 58 of the annular base portion 10 has spaces 59 that selectively protrude between the gate protrusion 57 and the third portion 103 and the fourth portion 104.

[0093] The second portion 102 is disposed on the opposite side of the gate pad electrode 24 from the first portion 101. The second portion 102 is a base end portion of the third extension portion 14, and is formed in a strip shape that is perpendicular to the third extension portion 14. The first portion 101 and the second portion 102 provide a pair of opposing sides of the base portion 10.

[0094] The third portion 103 and the fourth portion 104 face each other in the first direction X across the gate pad electrode 24, and connect the first portion 101 and the second portion 102. The third portion 103 and the fourth portion 104 provide a pair of opposing sides of the base portion 10. A plurality of gate electrodes 8 extend in the first direction X with the third portion 103 and the fourth portion 104 as base ends.

[0095] Each portion of the underlying wiring layer 9 has a width that allows connection of a contact having a width designed in accordance with the second design rule. The second design rule may have fewer dimensional constraints than the first design rule. For example, the second design rule allows connection of a contact with a wider width than the first design rule. For example, the wiring width W0 of each portion of the underlying wiring layer 9 may be 5 to 200 times the first contact width W1. The wiring width W0 is 1.5 μm to 100 μm. The wiring width W0 may have a value belonging to at least one of the ranges of 1.5 μm to 25 μm, 25 μm to 50 μm, 50 μm to 75 μm, and 75 μm to 100 μm. The wiring width W0 is, for example, the dimension of the underlying wiring layer 9 in a direction perpendicular to the longitudinal direction of each portion of the underlying wiring layer 9.

[0096] 4, 5, 7 and 8, a plurality of gate contact openings 60 are formed in interlayer insulating film 18 directly above underlying wiring layer 9. Gate contact openings 60 penetrate interlayer insulating film 18. Gate contact openings 60 include a base gate contact opening 61, a pad contact opening 62, a peripheral gate contact opening 63, and an inner gate contact opening 64.

[0097] The base gate contact opening 61 is disposed directly above the second portion 102, the third portion 103, and the fourth portion 104 of the base portion 10 of the underlying wiring layer 9. The pad contact opening 62 is disposed directly above the gate protrusion 57 of the base portion 10 of the underlying wiring layer 9. The peripheral gate contact opening 63 is disposed directly above the first portion 101, the first extension portion 12, and the second extension portion 13 of the base portion 10 of the underlying wiring layer 9. The inner gate contact opening 64 is disposed directly above the third extension portion 14 of the underlying wiring layer 9.

[0098] The plurality of gate contact openings 60 are formed in stripes at intervals in each portion of the underlying wiring layer 9. The first extension portion 12, the second extension portion 13, the third extension portion 14, the base portion 10, and the gate protrusion portion 57 of the underlying wiring layer 9 are each formed in a strip shape or a ring shape made up of a combination of strip-shaped portions. The plurality of gate contact openings 60 are stripe-shaped extending along the longitudinal direction of the strip-shaped underlying wiring layer 9, and are arranged at intervals in a direction perpendicular to the extension direction of the underlying wiring layer 9. The plurality of gate contact openings 60 may extend parallel to each other.

[0099] The number of the plurality of stripe-shaped gate contact openings 60 in each portion of the underlying wiring layer 9 can be appropriately selected depending on the wiring width W0 of the underlying wiring layer 9. The number of the plurality of gate contact openings 60 may be, for example, two or more and five or less for each portion of the underlying wiring layer 9.

[0100] In this embodiment, two base gate contact openings 61 are arranged for each of the second portion 102, the third portion 103, and the fourth portion 104 of the base portion 10 of the underlying wiring layer 9. The base gate contact openings 61 are preferably separated at the intersections between the second portion 102 and the third portion 103 and between the second portion 102 and the fourth portion 104. If the base gate contact openings 61 are formed so as to bend at the intersections, the opening width will be selectively widened at the bent portions. This is because it becomes difficult to fill the base gate contact openings 61 with a contact plug material with a uniform deposition amount.

[0101] Two pad contact openings 62 are arranged for each gate protrusion 57 of the base portion 10 of the underlying wiring layer 9. Three peripheral gate contact openings 63 are arranged for each first portion 101, first extension portion 12, and second extension portion 13 of the base portion 10 of the underlying wiring layer 9. The peripheral gate contact openings 63 may extend continuously from the first tip portion 15 of the first extension portion 12, via the first portion 101 of the base portion 10, to the second tip portion 16 of the second extension portion 13. Three internal gate contact openings 64 are arranged for each third extension portion 14 of the underlying wiring layer 9.

[0102] The strip-shaped gate contact openings 60 may be relatively short strip-shaped gate contact openings 60 arranged in a line along the extension direction of each portion of the underlying wiring layer 9. In other words, the strip-shaped gate contact openings 60 may be intermittently separated and formed in the shape of a plurality of stripes spaced apart from one another.

[0103] A gate contact 65 is buried in the gate contact opening 60. The gate contact 65 includes a second barrier layer 66 and a second plug layer 67. The second barrier layer 66 is a thin metal layer formed to cover the inner surface of the gate contact opening 60. The second barrier layer 66 defines a groove-shaped second recess 68 corresponding to the shape of the gate contact opening 60 on its inside. A second plug layer 67 is buried in this second recess 68.

[0104] 7 and 8, the second barrier thickness BT2 of the second barrier layer 66 is, for example, not less than 1000 Å and not more than 1500 Å. The second barrier thickness BT2 may have a value belonging to at least one of the ranges of not less than 1000 Å and not more than 1100 Å, not more than 1100 Å and not more than 1200 Å, not more than 1200 Å and not more than 1300 Å, not more than 1300 Å and not more than 1400 Å, and not more than 1400 Å and not more than 1500 Å.

[0105] The second barrier layer 66 mainly suppresses or prevents the constituent material of the second plug layer 67 (for example, tungsten) from diffusing into the interlayer insulating film 18. The second barrier layer 66 contains, for example, one or both of Ti and TiN. The second barrier layer 66 may be a laminated film in which a Ti film and a TiN film are stacked.

[0106] 7 and 8 , the second recess width RW2 of the second recess 68 may be one to three times the second barrier thickness BT2. The second recess width RW2 may be, for example, 0.1 μm to 3 μm. The second recess width RW2 may have a value belonging to at least one of the following ranges: 0.1 μm to 0.5 μm, 0.5 μm to 1.0 μm, 1.0 μm to 2.0 μm, and 2.0 μm to 3.0 μm.

[0107] The gate contacts 65 are buried in the gate contact openings 60, and are therefore provided in the same arrangement as the gate contact openings 60. The gate contacts 65 are connected to the underlying wiring layer 9 within the multiple gate contact openings 60. The gate contacts 65 are electrically connected to the gate electrode 8 via the underlying wiring layer 9.

[0108] 7 and 8 , the gate contact 65 has a second contact width W2 designed in accordance with the same first design rule as the source contact 53. In this embodiment, the second contact width W2 is preferably the same as the first contact width W1. The second contact width W2 is, for example, 0.3 μm to 0.5 μm. The second contact width W2 may have a value belonging to at least one of the following ranges: 0.3 μm to 0.35 μm, 0.35 μm to 0.4 μm, 0.4 μm to 0.45 μm, and 0.45 μm to 0.5 μm. The second contact width W2 is, for example, the dimension of the gate contact 65 in a direction perpendicular to the longitudinal direction of the gate contact 65.

[0109] 4 and 5 , the second pitch P2 between adjacent gate contacts 65 may be larger than the first pitch P1. The second pitch P2 is, for example, 2.2 μm or more and 50 μm or less. It may have a value belonging to at least one of the ranges of 2.2 μm or more and 5 μm or less, 5 μm or more and 10 μm or less, 10 μm or more and 20 μm or less, 20 μm or more and 30 μm or less, 30 μm or more and 40 μm or less, and 40 μm or more and 50 μm or less. The second pitch P2 may be the distance between adjacent gate contacts 65.

[0110] 7 and 8 , the second contact thickness T2 of the gate contact 65 (the depth of the gate contact opening 60) is, for example, not less than 0.2 μm and not more than 1.9 μm. The second contact thickness T2 may have a value belonging to at least one of the ranges of not less than 0.2 μm and not more than 0.7 μm, not more than 0.7 μm, not more than 1.2 μm, not more than 1.2 μm and not more than 1.7 μm, and not more than 1.7 μm and not more than 1.9 μm. The second contact thickness T2 is, for example, the dimension of the gate contact 65 in the depth direction of the gate contact opening 60.

[0111] The second aspect ratio (T2 / W2), which is the ratio of the second contact thickness T2 to the second contact width W2, is, for example, 0.6 to 6.4, and may have a value belonging to at least one of the following ranges: 0.6 to 2, 2 to 3, 3 to 4, 4 to 5, 5 to 6, and 6 to 6.4.

[0112] A principal surface electrode film 19 is formed to cover the interlayer insulating film 18. Referring to Fig. 6, the source electrode film 20 of the principal surface electrode film 19 is electrically connected to the source region 46 and the body contact region 48 via a source contact 53. Referring to Fig. 7, the gate pad electrode 24 of the principal surface electrode film 19 is electrically connected to the base portion 10 (first portion 101) of the underlying wiring layer 9 via a gate contact 65 in a pad contact opening 62.

[0113] The base wiring 26 of the principal surface electrode film 19 is electrically connected to the base portion 10 (second to fourth portions 102 to 104) of the underlying wiring layer 9 via a gate contact 65 in the base gate contact opening 61. The first finger wiring 28 and the second finger wiring 29 of the principal surface electrode film 19 are electrically connected to the first extension portion 12, the second extension portion 13 and the first portion 101 of the base portion 10 of the underlying wiring layer 9 via a gate contact 65 in the peripheral gate contact opening 63. The third finger wiring 30 of the principal surface electrode film 19 is electrically connected to the third extension portion 14 of the underlying wiring layer 9 via a gate contact 65 in the inner gate contact opening 64.

[0114] (3) Planar Shapes of the Source Contact 53 and the Gate Contact 65 FIGS. 9A to 9C show variations in the planar shapes of the source contact 53 and the gate contact 65. FIG.

[0115] As described above, the source contacts 53 and the gate contacts 65 are formed as lines that have or have ends in a plan view. In other words, it is preferable that the source contacts 53 and the gate contacts 65 do not have intersections of multiple line-shaped contacts. Even if the source contacts 53 and the gate contacts 65 are formed with a constant width in the longitudinal direction (e.g., the first contact width W1 and the second contact width W2 in FIGS. 6 to 8 ), the diagonal width of the intersections becomes larger than the first contact width W1 and the second contact width W2. As a result, it becomes difficult to fill the source contact openings 52 and the gate contact openings 60 with a uniform deposition amount of contact plug material.

[0116] There are many variations in the end shapes of the terminated, linear source contacts 53 and gate contacts 65. The source contacts 53 and gate contacts 65 in Figures 9A to 9C include a pair of side surfaces 69 extending in the longitudinal direction and a pair of end surfaces 70 connecting the pair of side surfaces 69 at the ends in the longitudinal direction.

[0117] Referring to FIG. 9A , both the side surface 69 and the end surface 70 of the source contact 53 and the gate contact 65 may be flat. In FIG. 9A , the side surface 69 and the end surface 70 may intersect at a right angle, and the corners 71 of the source contact 53 and the gate contact 65 may be sharp. Referring to FIG. 9 , when the flat side surface 69 and the flat end surface 70 intersect at a right angle, the corners 71 of the source contact 53 and the gate contact 65 may be rounded. Referring to FIG. 9C , the end surface 70 may be a curved surface that protrudes outward. As a result, the source contact 53 and the gate contact 65 do not need to have corners.

[0118] 9A to 9C show examples of variations in the end shapes of source contact 53 and gate contact 65, but the end shapes depend on the conditions used for etching source contact opening 52 and gate contact opening 60. For example, forming source contact opening 52 and gate contact opening 60 under certain etching conditions may result in the end shape shown in FIG. 9A, while using different etching conditions may result in the end shape shown in FIG. 9C.

[0119] (4) Layout of Contact Region 72 of Gate Contact 65 Next, variations of layout examples of the gate contact 65 will be described with reference to Figures 10 to 17. Figures 10 to 17 are diagrams showing first to eighth forms of layout of the gate contact 65, respectively.

[0120] 10 to 17, the contact region 72 in which the gate contacts 65 are arranged is indicated by cross-hatching. The multiple gate contacts 65 may be arranged in various patterns within the contact region 72. For example, as described above, the gate contacts 65 may extend continuously from one end of the underlying wiring layer 9 to the other (for example, from the first tip 15 of the first extension 12, via the first portion 101 of the base 10, to the second tip 16 of the second extension 13), or the gate contacts 65 may be intermittently separated into multiple stripes spaced apart from one another.

[0121] Referring to FIG. 10 , the contact region 72 is set directly below the base wiring 26, the first finger wiring 28, the second finger wiring 29, and the third finger wiring 30, that is, directly below the entire gate wiring 25, and these gate wirings 25 and the underlying wiring layer 9 may be connected by gate contacts 65.

[0122] Referring to FIG. 11 , contact region 72 may be selectively set directly below base wiring 26 , and base wiring 26 and underlying wiring layer 9 may be connected by gate contact 65 .

[0123] Referring to FIG. 12 , contact regions 72 may be selectively set directly below base wiring 26 and third finger wiring 30 , and these gate wirings 25 and underlying wiring layer 9 may be connected by gate contacts 65 .

[0124] Referring to FIG. 13 , the contact region 72 may be selectively set directly below the base wiring 26, the first finger wiring 28, and the second finger wiring 29, and these gate wirings 25 and the underlying wiring layer 9 may be connected by gate contacts 65.

[0125] 14 , the contact region 72 may be selectively set directly below the base wiring 26, and the base wiring 26 and the underlying wiring layer 9 may be connected by a gate contact 65. Furthermore, when the gate wiring 25 includes a branch wiring 73 extending outward from the base wiring 26 in the first direction X, the contact region 72 may be set directly below the branch wiring 73.

[0126] 15 , contact region 72 may be selectively set directly below base wiring 26, and base wiring 26 and underlying wiring layer 9 may be connected by gate contact 65. Furthermore, when gate wiring 25 includes branch wiring 73 extending outward in first direction X from base wiring 26 and branch wiring 74 extending outward in first direction X from third finger wiring 30, contact region 72 may be set directly below branch wiring 73, 74.

[0127] 16 , contact region 72 may be set directly below base wiring 26, first finger wiring 28, second finger wiring 29, and third finger wiring 30, that is, directly below gate wiring 25, and these gate wirings 25 may be connected to underlying wiring layer 9 by gate contacts 65. Furthermore, when gate wiring 25 includes branch wirings 75 extending inward in first direction X from first finger wiring 28 and second finger wiring 29, contact region 72 may be set directly below these branch wirings 75.

[0128] 17 , contact region 72 does not need to be continuous in the longitudinal direction of gate wiring 25. For example, contact region 72 may be divided at an intersection or corner (e.g., corner C3) of gate wiring 25. Furthermore, contact region 72 may be divided at a linear portion (third finger wiring 30 in FIG. 17 ) of gate wiring 25. This allows all gate contacts 65 arranged in contact region 72 to be formed linearly without intersections.

[0129] (5) Effects of the Semiconductor Device 1: In recent years, as device structures have become increasingly miniaturized, there has been a demand for thinner contacts connecting the device structures to surface electrodes. For example, in FIG. 6, as the pitch (pitch BP of unit cells (UCs)) between the body regions 45 becomes narrower, the distance between adjacent gate electrodes 8 also becomes narrower. Because the space for the source contacts 53 is limited, it is desirable to form source contacts 53 with a narrower line width.

[0130] Conventionally, contacts to device structures have been formed by depositing a film of electrode material such as aluminum (Al) using a sputtering method. As device structures have become increasingly miniaturized, the sputtering method has been associated with the problem of voids forming inside the contact. To improve the fillability of the contact, a method has been adopted in which tungsten is embedded using a CVD method or the like to form the contact.

[0131] The unit cells UC in the active region 6 are preferably thinned to improve performance through miniaturization. On the other hand, thick wires are preferred for contacts to conductive structures other than the unit cells UC (e.g., the gate wiring portion in the peripheral region 7). This is, for example, to facilitate pattern formation and to reduce the associated operational stability and contact resistance. Particles or foreign matter on the pattern during the process can thin the wires or, depending on the pattern dimensions, can cause wire breakage. Thick wires prevent wire breakage and thus achieve operational stability. However, when thin and thick wires coexist within a common chip 2, the thick wires are not buried during tungsten filling and must be aligned with the thin wires. This raises concerns about the operational stability and contact resistance of the device structure associated with pattern formation.

[0132] Therefore, in semiconductor device 1, the wiring width W0 of each portion of underlying wiring layer 9 is several times or more the first contact width W1 of source contact 53. Wiring width W0 is a width that allows connection of a contact having a width designed in accordance with a second design rule that is less restrictive than source contact 53 designed in accordance with the first design rule. Despite this, gate contacts 65 are designed in accordance with the first design rule, and multiple gate contacts 65 are provided in a stripe shape, with each gate contact corresponding to each portion (e.g., each strip-shaped portion) of underlying wiring layer 9.

[0133] This allows for redundancy in pattern formation and ensures operational stability. Thinning each gate contact 65 reduces the contact area, increasing the contact resistance per unit area. However, providing multiple gate contacts 65 ensures a large overall contact area, allowing the contact resistance to be kept low.

[0134] (6) Another Form of Device Structure Fig. 18 is a cross-sectional view showing a second form of device structure. Referring to Fig. 18, a transistor structure Tr of a semiconductor device 1 of this form has a trench gate type vertical structure.

[0135] The semiconductor device 1 includes a plurality of trenches 76 formed in the first main surface 3. Between adjacent trenches 76, mesa portions 77 are formed by parts of the second semiconductor layer 43. The mesa portions 77 are strip-shaped extending along the first direction X and arranged alternately in the second direction Y. The plurality of trenches 76 and the plurality of mesa portions 77 are arranged in a stripe pattern as a whole. Each mesa portion 77 provides a unit cell UC of a trench-gate transistor. Each mesa portion 77 includes at least a body region 45 and a source region 46, and may be the minimum unit that functions as a MIS transistor.

[0136] The semiconductor device 1 includes a trench insulating film 78 that covers the inner surface of the trench 76. The trench insulating film 78 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the trench insulating film 78 has a single-layer structure made of a silicon oxide film. The trench insulating film 78 may also include a silicon oxide film made of an oxide of the chip 2.

[0137] The semiconductor device 1 includes a buried conductive layer 79 (gate electrode) buried in the trench 76. The buried conductive layer 79 faces the body region 45 (channel region 47) across the trench insulating film 78. The buried conductive layer 79 may include p-type or n-type conductive polysilicon.

[0138] The semiconductor device 1 according to the second embodiment can also achieve the same effects as the semiconductor device 1 according to the previous embodiment.

[0139] (7) Other Arrangement Patterns of Gate Contacts 65 Fig. 19 is a plan view showing a second arrangement pattern of the gate contacts 65. Referring to Fig. 19, the plurality of stripe-shaped gate contacts 65 may be arranged in the extension direction of the gate wiring (finger wirings 27 in Fig. 19). That is, the plurality of gate contacts 65 may be a band-shaped collection extending along the extension direction of the finger wirings 27 as shown in Fig. 4, or may be a band-shaped collection extending along a direction perpendicular to the extension direction of the finger wirings 27 as shown in Fig. 19.

[0140] Although embodiments of the present disclosure have been described, the present disclosure may be embodied in other forms.

[0141] For example, in each of the above-described embodiments, the first semiconductor layer 41 and the second semiconductor layer 43 each contain a SiC single crystal. However, at least one or all of the first semiconductor layer 41 and the second semiconductor layer 43 may contain a single crystal of a wide bandgap semiconductor other than a SiC single crystal.

[0142] The first semiconductor layer 41 and the second semiconductor layer 43 may be made of the same type of single crystal or different types of single crystal, and at least one of the first semiconductor layer 41 and the second semiconductor layer 43 or all of the first semiconductor layer 41 and the second semiconductor layer 43 may be made of silicon (Si).

[0143] For example, the wiring layer having a width designed in accordance with a design rule that is less restrictive than that of the source contact 53 is not limited to the underlying wiring layer 9 for the gate contact 65 described above. For example, it may be an electrode of a resistor element, a diode element, a capacitor element, or the like, disposed outside the active region 6.

[0144] Below, examples of features extracted from this specification and the drawings are shown. Below, alphanumeric characters in parentheses represent corresponding components in the above-mentioned embodiments, but are not intended to limit the scope of each clause to the embodiments. The "semiconductor device" in the following items may be replaced with "SiC semiconductor device," "wide bandgap semiconductor device," "semiconductor switching device," "semiconductor rectifier device," "MISFET device," "IGBT device," "diode device," etc., as necessary.

[0145] [Supplementary Note 1-1] A chip (2) having a main surface (3) including an active region (6); a device structure including a plurality of unit cells (UC) formed in the active region (6) and extending in a stripe pattern; a wiring layer (9) arranged in a region on the main surface (3) separated from the device structure in a lateral direction along the main surface (3); an insulating layer (18) covering the device structure and the wiring layer (9); a plurality of first contacts (53) embedded in the insulating layer (18) and connected to the plurality of unit cells (UC), the first contacts having a line width designed in accordance with a first design rule; a plurality of second contacts (65) embedded in the insulating layer (18) and connected to the wiring layer (9), each of the second contacts (65) being made of the same material as the first contacts (53), having a line width designed in accordance with the first design rule, and arranged in a stripe pattern; and a first main surface electrode (20) formed on the insulating layer (18) and connected to the first contacts (53). a second principal surface electrode (21) formed on the insulating layer (18) and connected to the second contact (65).

[0146] [Appendix 1-2] The semiconductor device (1) according to Appendix 1-1, wherein the wiring layer (9) is arranged in a region outside the active region (6) on the main surface (3) and is formed in an endless or terminated line shape having a width at least 5 times to 200 times the line width.

[0147] [Supplementary Note 1-3] The semiconductor device (1) according to Supplementary Note 1-1 or Supplementary Note 1-2, wherein the plurality of stripe-shaped second contacts (65) are arranged in a direction perpendicular to the extension direction of the wiring layer (9).

[0148] [Appendix 1-4] The semiconductor device (1) according to any one of Appendices 1-1 to 1-3, wherein a second pitch (P2) of the plurality of second contacts (65) is greater than a first pitch (P1) of the plurality of first contacts (53).

[0149] [Appendix 1-5] The semiconductor device (1) according to any one of Appendices 1-1 to 1-4, wherein the first contact (53) and the second contact (65) have a stacked structure including a barrier layer (54, 66) that is in contact with the insulating layer (18) and defines a recess (56, 68) therein, and a plug layer (55, 67) that is embedded in the recess (56, 68).

[0150] [Supplementary Note 1-6] The semiconductor device (1) according to Supplementary Note 1-5, wherein a width (RW1, RW2) of the recess (56, 68) is equal to or greater than one time and equal to or less than three times a thickness (BT1, BT2) of the barrier layer (54, 66).

[0151] [Supplementary Note 1-7] The semiconductor device (1) according to Supplementary Note 1-5 or Supplementary Note 1-6, wherein the width (RW1, RW2) of the recess (56, 68) is 0.1 μm or more and 3 μm or less.

[0152] [Supplementary Note 1-8] The semiconductor device (1) according to any one of Supplementary Note 1-1 to Supplementary Note 1-7, comprising: a first impurity region (8) of a first conductivity type formed in a surface layer portion of the main surface (3); the device structure comprising a planar structure including: a plurality of second impurity regions (45) of a second conductivity type arranged in a stripe pattern in a surface layer portion of the first impurity region (8) and providing the unit cell (UC); the third impurity region (46) arranged in an inner region of each of the second impurity regions (45); and a gate electrode (8) formed on the first main surface (3) and facing the second impurity region (45) via a gate insulating film (50); and the plurality of first contacts (53) including contact plugs (53) embedded in contact openings (52) formed in the insulating layer (18) between a pair of adjacent gate electrodes (8) and electrically connected to the second impurity region (45) and the third impurity region (46) within the contact openings (52).

[0153] [Supplementary Note 1-9] The device structure includes a first impurity region (8) of a first conductivity type formed in a surface layer portion of the main surface (3), the device structure including a trench (76) that defines a stripe-shaped mesa portion (77) that provides the plurality of unit cells (UC), a gate electrode (79) embedded in the trench (76) with a gate insulating film (78) interposed therebetween, and a trench structure including a second impurity region (45) of a second conductivity type and a third impurity region (46) of a first conductivity type that are formed in this order in the mesa portion (77) from a bottom of the trench (76) toward the main surface (3), The semiconductor device (1) according to any one of Appendices 1-1 to 1-7, wherein the plurality of first contacts (53) are embedded in contact openings (52) formed in the insulating layer (18) between adjacent pairs of the gate electrodes (8), and include contact plugs (53) electrically connected to the second impurity region (45) and the third impurity region (46) within the contact openings (52).

[0154] [Supplementary Note 1-10] The semiconductor device (1) according to Supplementary Note 1-8 or Supplementary Note 1-9, wherein the wiring layer (9) is made of the same material as the gate electrode (8, 79), is integrated with the gate electrode (8, 79), and includes an underlying wiring layer (9) arranged from the active region (6) to a region outside the active region (6), the second main surface electrode (21) is an electrode covering the underlying wiring layer (9) via the insulating layer (18), and includes a gate pad (24) and a linear gate wiring (25) electrically connected to the gate pad (24), and the plurality of second contacts (65) connect the underlying wiring layer (9) and the gate wiring (25).

[0155] [Supplementary Note 1-11] The semiconductor device (1) according to Supplementary Note 1-10, wherein the plurality of stripe-shaped second contacts (65) are arranged in a direction perpendicular to the extension direction of the gate wiring (25).

[0156] [Supplementary Note 1-12] The semiconductor device (1) according to Supplementary Note 1-10, wherein the plurality of stripe-shaped second contacts (65) are arranged in the extension direction of the gate wiring (25).

[0157] [Appendix 1-13] The semiconductor device (1) according to any one of Appendices 1-10 to 1-12, wherein the gate wiring (25) includes peripheral gate wiring (28, 29) extending along the periphery of the chip (2) and surrounding the active region (6), and a central gate wiring (30) extending across the active region (6), and the plurality of second contacts (65) connect both the peripheral gate wiring (28, 29) and the central gate wiring (30) to the underlying wiring layer (9).

[0158] [Appendix 1-14] The semiconductor device (1) according to any one of Appendices 1-1 to 1-13, wherein a second width (W2) that is the line width of the second contact (65) is the same as a first width (W1) that is the line width of the first contact (53).

[0159] [Appendix 1-15] The semiconductor device (1) according to appendix 1-14, wherein the first width (W1) and the second width (W2) are 0.3 μm or more and 0.5 μm or less.

[0160] [Appendix 1-16] The semiconductor device (1) according to appendix 1-14 or appendix 1-15, wherein a first aspect ratio (T1 / W1) which is a ratio of a first thickness (T1) of the first contact (53) to the first width (W1) is 1 or more and 6.7 or less, and a second aspect ratio (T2 / W2) which is a ratio of a second thickness (T2) of the contact to the second width (W2) is 0.6 or more and 6.4 or less.

[0161] [Appendix 1-17] The semiconductor device (1) according to any one of Appendices 1-1 to 1-16, wherein the chip (2) includes a SiC chip (2).

[0162] REFERENCE SIGNS LIST 1...Semiconductor device, 2...Chip, 3...First main surface, 4...Second main surface, 5A...First side surface, 5B...Second side surface, 5C...Third side surface, 5D...Fourth side surface, 6...Active region, 7...Peripheral region, 8...Gate electrode, 9...Underlying wiring layer, 10...Base portion, 11...Extension portion, 12...First extension portion, 13...Second extension portion, 14...Third extension portion, 15...First tip portion, 16...Second tip portion, 17...Third tip portion, 18...Interlayer insulating film, 19...Main surface electrode film, 20...Source electrode film, 21...Gate electrode film, 22...First source electrode film, 23 ...second source electrode film, 24...gate pad electrode, 25...gate wiring, 26...base wiring, 27...finger wiring, 28...first finger wiring, 29...second finger wiring, 30...third finger wiring, 31...first tip portion, 32...second tip portion, 33...third tip portion, 34...surface insulating film, 35...gate pad, 36...gate pad opening, 37...first source pad, 38...first source pad opening, 39...second source pad, 40...second source pad opening, 41...first semiconductor layer, 4 2...Drain pad electrode, 43...Second semiconductor layer, 44...Drift region, 45...Body region, 46...Source region, 47...Channel region, 48...Body contact region, 49...Peripheral well region, 50...Gate insulating film, 51...Main surface insulating film, 52...Source contact opening, 53...Source contact, 54...First barrier layer, 55...First plug layer, 56...First recess, 57...Gate protrusion, 58...Inner opening, 59...Space, 60...Gate contact opening, 61...Base gate contact 1. Gate opening, 62...pad contact opening, 63...peripheral gate contact opening, 64...internal gate contact opening, 65...gate contact, 66...second barrier layer, 67...second plug layer, 68...second recess, 69...side surface, 70...end surface, 71...corner portion, 72...contact region, 73...branch wiring, 74...branch wiring, 75...branch wiring, 76...trench, 77...mesa portion, 78...trench insulating film, 79...buried conductive layer, 101...first portion, 102...second portion, 103...third portion, 104...fourth portion

Claims

1. A semiconductor device comprising: a chip having a main surface including an active region; a device structure including a plurality of unit cells formed in the active region and extending in a stripe pattern; a wiring layer disposed on the main surface in a region separated from the device structure in a lateral direction along the main surface from the device structure; an insulating layer covering the device structure and the wiring layer; a plurality of first contacts embedded in the insulating layer and connected to the plurality of unit cells, the first contacts having a line width designed in accordance with a first design rule; a plurality of second contacts embedded in the insulating layer and connected to the wiring layer, the second contacts being made of the same material as the first contacts, having a line width designed in accordance with the first design rule, and arranged in a stripe pattern; first main surface electrodes formed on the insulating layer and connected to the first contacts; and second main surface electrodes formed on the insulating layer and connected to the second contacts.

2. The semiconductor device according to claim 1, wherein the wiring layer is arranged in an area outside the active region on the main surface and is formed in an endless or terminated line shape having a width at least 5 times to 200 times the line width.

3. The semiconductor device according to claim 1 or 2, wherein the plurality of stripe-shaped second contacts are arranged in a direction perpendicular to the extension direction of the wiring layer.

4. The semiconductor device according to any one of claims 1 to 3, wherein a second pitch P2 of the plurality of second contacts is larger than a first pitch P1 of the plurality of first contacts.

5. A semiconductor device according to any one of claims 1 to 4, wherein the first contact and the second contact have a laminated structure including a barrier layer in contact with the insulating layer and defining a recess therein, and a plug layer buried in the recess.

6. The semiconductor device according to claim 5, wherein the width of said recess is at least one time and at most three times the thickness of said barrier layer.

7. The semiconductor device according to claim 5 or 6, wherein the width of said recess is not less than 0.1 μm and not more than 3 μm.

8. The semiconductor device according to any one of claims 1 to 7, comprising a first impurity region of a first conductivity type formed in a surface layer portion of said main surface, said device structure comprising a planar structure including a plurality of second impurity regions of a second conductivity type arranged in stripes on a surface layer portion of said first impurity region and providing said unit cells, said third impurity regions arranged in inner regions of each of said second impurity regions, and gate electrodes formed on said first main surface and facing said second impurity regions via gate insulating films, said plurality of first contacts being embedded in contact openings formed in said insulating layer between a pair of adjacent said gate electrodes and comprising contact plugs electrically connected to said second impurity region and said third impurity region within said contact openings.

9. The semiconductor device according to any one of claims 1 to 7, comprising a first impurity region of a first conductivity type formed in a surface layer portion of the main surface, wherein the device structure comprises a trench structure including: a trench defining a striped mesa portion providing the plurality of unit cells; a gate electrode embedded in the trench via a gate insulating film; and a second impurity region of a second conductivity type and a third impurity region of the first conductivity type formed in this order in the mesa portion in a direction from the bottom of the trench toward the main surface, wherein the plurality of first contacts comprise contact plugs embedded in contact openings formed in the insulating layer between a pair of adjacent gate electrodes and electrically connected to the second impurity region and the third impurity region within the contact opening.

10. The semiconductor device described in claim 8 or 9, wherein the wiring layer includes an underlying wiring layer that is integral with the gate electrode and made of the same material as the gate electrode, and that is arranged in a region extending from the active region to the outside of the active region; the second main surface electrode is an electrode that covers the underlying wiring layer via the insulating layer, and includes a gate pad and a linear gate wiring electrically connected to the gate pad; and the plurality of second contacts connect the underlying wiring layer and the gate wiring.

11. The semiconductor device according to claim 10, wherein the plurality of stripe-shaped second contacts are arranged in a direction perpendicular to the extension direction of the gate wiring.

12. The semiconductor device according to claim 10, wherein the plurality of stripe-shaped second contacts are arranged in the direction in which the gate wiring extends.

13. The semiconductor device according to any one of claims 10 to 12, wherein the gate wiring includes a peripheral gate wiring that extends along the periphery of the chip and surrounds the active region, and a central gate wiring that extends across the active region, and the plurality of second contacts connect both the peripheral gate wiring and the central gate wiring to the underlying wiring layer.

14. The semiconductor device according to any one of claims 1 to 13, wherein a second width W2, which is the line width of the second contact, is the same as a first width W1, which is the line width of the first contact.

15. The semiconductor device according to claim 14, wherein the first width W1 and the second width W2 are not less than 0.3 μm and not more than 0.5 μm.

16. The semiconductor device described in claim 14 or 15, wherein a first aspect ratio (T1 / W1) which is the ratio of the first thickness T1 of the first contact to the first width W1 is not less than 1 and not more than 6.7, and a second aspect ratio (T2 / W2) which is the ratio of the second thickness T2 of the contact to the second width W2 is not less than 0.6 and not more than 6.

4.

17. The semiconductor device according to any one of claims 1 to 16, wherein the chip includes a SiC chip.

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