Through-electrode substrate, through-electrode substrate equipped with element, connection substrate, and semiconductor device

Abstract

The present disclosure provides a through-electrode substrate to be connected to a wiring board, the through-electrode substrate including: a glass substrate having a first surface and a second surface facing the first surface, and a first through hole; a through-electrode disposed in the first through hole of the glass substrate; a multilayer insulating layer disposed on the first surface side of the glass substrate and having a plurality of insulating layers; and a conductive layer disposed in each gap between the insulating layers and electrically connected to the through-electrode. When the shear elastic modulus of the multilayer insulating layer is G1 (GPa), the difference in amount of strain between the wiring board and the glass substrate is γ1 (mm), and the total thickness of the multilayer insulating layer is h1 (mm), the shear elastic modulus G1 is 0.036 GPa or more, and the stress F1A calculated by the following (expression 1-1) is 4.35 GPa or less. (Expression 1-1): F1A = (G1×γ1) / h1

Description

Through-electrode substrate, through-electrode substrate with element, connection substrate, and semiconductor device

[0001] The present disclosure relates to a through electrode substrate, a through electrode substrate with an element, a connection substrate, and a semiconductor device.

[0002]

[0003] Various technologies have been proposed for interposers that connect chips and motherboards with different terminal pitches. It is known to use a through-electrode substrate having through-electrodes as an interposer. For example, Patent Document 1 (JP-A-2005-102666) discloses an interposer that includes a lower wiring substrate portion, an upper wiring substrate portion disposed above the lower wiring substrate portion, and through-electrodes that penetrate the upper wiring substrate portion and extend into the lower wiring substrate portion to connect the upper wiring substrate portion and the lower wiring substrate portion, the lower wiring substrate portion and the upper wiring substrate portion being spaced apart from each other, and a side surface of the through-electrode being exposed in a space formed between the lower wiring substrate portion and the upper wiring substrate portion.

[0003] JP 2013-4881 A

[0004] Known types of interposers include, for example, silicon interposers, organic interposers, and glass interposers, among which organic interposers and glass interposers have attracted attention for their cost reduction potential.

[0005] However, the thermal expansion coefficient of the organic material, such as glass epoxy, used in the organic interposer is significantly different from that of the semiconductor material, such as silicon, used in the element. Therefore, when heating is performed in the manufacturing process of the semiconductor device or the semiconductor device is used in a high-temperature environment, the difference in the thermal expansion coefficient between the organic material and the semiconductor material causes stress in the joints, pads, and wiring that electrically connect the organic interposer and the element, which can easily cause cracks and disconnections.

[0006] On the other hand, in the case of a glass interposer, the difference between the thermal expansion coefficient of the glass substrate used in the glass interposer and the thermal expansion coefficient of the semiconductor material can be made small.

[0007] However, the thermal expansion coefficient of the glass substrate is significantly different from that of the glass epoxy substrate commonly used for motherboards. Therefore, when heating is performed during the manufacturing process of a semiconductor device or when the semiconductor device is used in a high-temperature environment, the difference in the thermal expansion coefficient between the glass substrate of the glass interposer and the glass epoxy substrate of the motherboard causes stress to be generated in the joints and pads that electrically connect the glass interposer and the motherboard, making them more susceptible to cracks and breaks and reducing the connection reliability.

[0008] In recent years, semiconductor devices have been required to operate at higher speeds, and the density and integration of elements have been increasing. To address this, technologies for increasing the size of interposers have been developed. However, the above-mentioned stress problem becomes more pronounced with large-area glass interposers.

[0009] The present disclosure is an invention made in view of the above circumstances, and has a first object to provide a through electrode substrate with good connection reliability.

[0010] In addition, the present disclosure is an invention made in consideration of the above-mentioned situation, and has a second object to provide a connection substrate for electrically connecting a through-hole electrode substrate having a glass substrate to a wiring substrate, which can increase the connection reliability between the through-hole electrode substrate and the wiring substrate.

[0011] One embodiment of the present disclosure is a through electrode substrate connected to a wiring substrate, the through electrode substrate having a first surface and a second surface opposite to the first surface, a glass substrate having a first through hole, a through electrode disposed in the first through hole of the glass substrate, a multilayer insulating layer disposed on the first surface side of the glass substrate and having a plurality of insulating layers, and a conductive layer disposed between the insulating layers and electrically connected to the through electrode, wherein the shear modulus of the multilayer insulating layer is G1 (GPa), the difference in strain between the wiring substrate and the glass substrate is γ1 (mm), and the total thickness of the multilayer insulating layer is h1 (mm), the shear modulus of the multilayer insulating layer is 0.036 GPa or more, and a stress F1 calculated by the following (Equation 1-1) Ａ The present invention provides a through-hole electrode substrate having a modulus of elastic modulus of 4.35 GPa or less. Ａ =(G1×γ1) / h1 (Formula 1-1)

[0012] Another embodiment of the present disclosure is a through electrode substrate connected to a wiring substrate, the through electrode substrate having a first surface and a second surface opposite to the first surface, a glass substrate having a first through hole, a through electrode disposed in the first through hole of the glass substrate, a multilayer insulating layer having a plurality of insulating layers disposed on the first surface side of the glass substrate, an elastic insulating layer disposed on the surface of the multilayer insulating layer opposite the glass substrate, and a conductive layer disposed between the insulating layers and between the multilayer insulating layer and the elastic insulating layer, and electrically connected to the through electrode, wherein the shear modulus G2 is 0.036 GPa or more, and the stress F2 calculated by the following (Equation 2-1) is Ａ F2 Ａ =(G2×γ1) / h2 (Formula 2-1)

[0013] One embodiment of the present disclosure is a through electrode substrate connected to a wiring substrate, the through electrode substrate having a first surface and a second surface opposite to the first surface, a glass substrate having a first through hole, a through electrode disposed in the first through hole of the glass substrate, a multilayer insulating layer disposed on the first surface side of the glass substrate and having a plurality of insulating layers, a hard insulating layer disposed on the surface of the multilayer insulating layer opposite the glass substrate, and a conductive layer disposed between the insulating layers and between the multilayer insulating layer and the hard insulating layer, and electrically connected to the through electrode, wherein the shear modulus G1 is 0.036 GPa or more, and a stress F1 calculated by the following (Equation 1-2) is Ｂ The present invention provides a through hole electrode substrate in which the thermal expansion coefficient difference Δα between the wiring substrate and the hard insulating layer is 75% or less, calculated by the following formula (3) where the thermal expansion coefficient of the wiring substrate is α1 ( / °C) and the thermal expansion coefficient of the hard insulating layer is α3 ( / °C). Ｂ=(G1×γ2) / h1 (Formula 1-2) Δα=(|α1-α3| / α1)×100 (Formula 3)

[0014] Another embodiment of the present disclosure is a through electrode substrate connected to a wiring substrate, the through electrode substrate having a first surface and a second surface opposite to the first surface, a glass substrate having a first through hole, a through electrode arranged in the first through hole of the glass substrate, a multilayer insulating layer arranged on the first surface side of the glass substrate and having a plurality of insulating layers, an elastic insulating layer arranged on the surface of the multilayer insulating layer opposite the glass substrate, a hard insulating layer arranged on the surface of the elastic insulating layer opposite the multilayer insulating layer, and a conductive layer arranged between the insulating layers, between the multilayer insulating layer and the elastic insulating layer, and between the elastic insulating layer and the hard insulating layer, and electrically connected to the through electrode, wherein the shear modulus G2 is 0.036 GPa or more, and a stress F2 calculated by the following (Equation 2-2) is Ｂ The through hole electrode substrate has a thermal expansion coefficient difference Δα of 75% or less, calculated by the following formula (3) when the thermal expansion coefficient of the wiring substrate is α1 ( / °C) and the thermal expansion coefficient of the hard insulating layer is α3 ( / °C). Ｂ =(G2×γ) / h2 (Formula 2-2) Δα=(|α1-α3| / α1)×100 (Formula 3)

[0015] Another embodiment of the present disclosure provides a through hole electrode substrate with an element, including the through hole electrode substrate described above and an element mounted on the through hole electrode substrate.

[0016] Another embodiment of the present disclosure provides a semiconductor device having the above-mentioned element-equipped through-electrode substrate, a joint electrically connected to the conductive layer in the through-electrode substrate, and a wiring substrate electrically connected to the joint.

[0017] Another embodiment of the present disclosure provides a connection substrate for electrically connecting a glass substrate and a through electrode substrate having through electrodes penetrating the glass substrate to a wiring substrate, the connection substrate having a resin layer and a conductive portion penetrating the resin layer, wherein the thermal expansion coefficient of the resin layer in the plane direction is between the thermal expansion coefficient of the glass substrate in the plane direction and the thermal expansion coefficient of the wiring substrate in the plane direction, and the shear modulus of the resin layer is 0.036 GPa or more and 20 GPa or less.

[0018] Another embodiment of the present disclosure is a connection substrate for electrically connecting a glass substrate and a through electrode substrate having through electrodes penetrating the glass substrate to a wiring substrate, the connection substrate including a resin layer and a conductive portion penetrating the resin layer, wherein the thermal expansion coefficient of the resin layer in a plane direction is between the thermal expansion coefficient of the glass substrate in a plane direction and the thermal expansion coefficient of the wiring substrate in a plane direction, and the thermal expansion coefficient α of the resin layer in a plane direction is Ｐ and the thermal expansion coefficient α in the thickness direction of the resin layer. Ｔ The difference between Ｐ -α Ｔ is 9 ppm / °C or less.

[0019] Another embodiment of the present disclosure provides a connection substrate for electrically connecting a glass substrate and a through electrode substrate having through electrodes penetrating the glass substrate to a wiring substrate, the connection substrate having a base having an outer through hole, an elastic portion disposed within the outer through hole of the base and having an inner through hole, and a conductive portion disposed within the inner through hole of the elastic portion.

[0020] Another embodiment of the present disclosure provides a connection substrate for electrically connecting a glass substrate and a through electrode substrate having through electrodes penetrating the glass substrate to a wiring substrate, the connection substrate having a support layer, a first elastic insulating layer arranged on a first surface side of the support layer and having an uneven shape including a plurality of convex portions and a plurality of concave portions on a surface opposite the support layer, a conductive portion that penetrates the support layer and the first elastic insulating layer, and a first bellows wiring layer arranged on the surface having the uneven shape of the first elastic insulating layer, having a bellows-shaped portion having a plurality of peaks and a plurality of valleys, and electrically connected to the conductive portion.

[0021] Another embodiment of the present disclosure provides a semiconductor device having the above-mentioned connection substrate, a wiring substrate arranged on a first surface side of the connection substrate, a through electrode substrate arranged on a second surface side of the connection substrate, an element arranged on the opposite side of the through electrode substrate from the connection substrate, a third joint that electrically connects the conductive portion in the connection substrate and the wiring substrate, a fourth joint that electrically connects the conductive portion in the connection substrate and the through electrode in the through electrode substrate, and a fifth joint that electrically connects the through electrode in the through electrode substrate and the element.

[0022] Another embodiment of the present disclosure provides a semiconductor device comprising: a through electrode substrate having a glass substrate and through electrodes penetrating the glass substrate; a wiring substrate; a connection substrate arranged between the through electrode substrate and the wiring substrate, the connection substrate having a resin substrate and a conductive portion penetrating the resin substrate; an element arranged on the opposite side of the through electrode substrate from the connection substrate; a third joint portion electrically connecting the conductive portion of the connection substrate and the wiring substrate; a fourth joint portion electrically connecting the conductive portion of the connection substrate and the through electrode of the through electrode substrate; and a fifth joint portion electrically connecting the through electrode of the through electrode substrate and the element, wherein the thermal expansion coefficient of the resin substrate in the plane direction is between the thermal expansion coefficient of the glass substrate in the plane direction and the thermal expansion coefficient of the wiring substrate in the plane direction.

[0023] The present disclosure provides an effect of providing a semiconductor device that uses a through-hole electrode substrate having a glass substrate as an interposer and has good connection reliability.

[0024] Furthermore, the present disclosure has the effect of providing a connection substrate that can increase the connection reliability between a through-hole electrode substrate having a glass substrate and a wiring substrate.

[0025] FIG. 1 is a schematic cross-sectional view illustrating a through electrode substrate according to a first embodiment of the present disclosure. FIG. 2 is a schematic cross-sectional view illustrating a through electrode substrate with elements according to the first embodiment of the present disclosure. FIG. 3 is a schematic cross-sectional view illustrating a semiconductor device according to the first embodiment of the present disclosure. FIG. 4 is a schematic cross-sectional view illustrating the cross-sectional shape of a first through hole in a glass substrate of a through electrode substrate according to the present disclosure. FIG. 5 is a schematic cross-sectional view illustrating a gap and a bulge that occur in a through electrode substrate. FIG. 6 is a schematic cross-sectional view illustrating a covering insulating layer of a through electrode substrate according to the present disclosure. FIG. 7 is a schematic cross-sectional view illustrating a through electrode substrate according to a second embodiment of the present disclosure. FIG. 8 is a schematic cross-sectional view illustrating a through electrode substrate with elements according to the second embodiment of the present disclosure. FIG. 9 is a schematic cross-sectional view illustrating a semiconductor device according to the second embodiment of the present disclosure. FIG. 10 is a schematic cross-sectional view illustrating a through electrode substrate according to a third embodiment of the present disclosure. FIG. 11 is a schematic cross-sectional view illustrating a through electrode substrate with elements according to the third embodiment of the present disclosure. FIG. 12 is a schematic cross-sectional view illustrating a semiconductor device according to the third embodiment of the present disclosure. FIG. 13 is a schematic cross-sectional view illustrating a through electrode substrate according to a fourth embodiment of the present disclosure. FIG. 14 is a schematic cross-sectional view illustrating a through electrode substrate with elements according to the fourth embodiment of the present disclosure. FIG. 1 is a schematic cross-sectional view illustrating a connection board according to a fifth embodiment and a second embodiment of the present disclosure. FIG. 2 is a schematic cross-sectional view illustrating a semiconductor device according to a fifth embodiment and a second embodiment of the present disclosure. FIG. 3 is a schematic cross-sectional view illustrating a connection board according to a seventh embodiment of the present disclosure. FIG. 4 is a schematic cross-sectional view illustrating a semiconductor device according to a seventh embodiment of the present disclosure. FIG. 5 is a schematic cross-sectional view illustrating a connection board according to an eighth embodiment of the present disclosure. FIG. 6 is a schematic plan view illustrating a connection board according to an eighth embodiment of the present disclosure. FIG. 7 is a schematic cross-sectional view illustrating a semiconductor device according to an eighth embodiment of the present disclosure. FIG. 8 is a schematic cross-sectional view illustrating an elastic insulating layer and a bellows wiring of a connection board according to an eighth embodiment of the present disclosure. FIG. 9 is a schematic cross-sectional view and a schematic plan view illustrating a connection board according to an eighth embodiment of the present disclosure. FIG. 10 is a schematic plan view illustrating a bellows wiring according to an eighth embodiment of the present disclosure.FIG. 13 is a schematic cross-sectional view illustrating a semiconductor device according to a ninth embodiment of the present disclosure.

[0026] Embodiments of the present disclosure will be described below with reference to the drawings and the like. However, the present disclosure can be implemented in many different forms and should not be construed as being limited to the description of the embodiments exemplified below. Furthermore, to clarify the explanation, the drawings may show the width, thickness, shape, etc. of each part schematically compared to the actual form, but these are merely examples and do not limit the interpretation of the present disclosure. Furthermore, in this specification and each drawing, elements similar to those described above with reference to the previous drawings may be designated by the same reference numerals, and detailed descriptions may be omitted as appropriate.

[0027] In this specification, when describing an aspect in which another component is placed on a certain component, the term "above" or "below" refers to both a case in which another component is placed directly above or below the component so as to be in contact with the component, and a case in which another component is placed above or below the component with another component interposed therebetween, unless otherwise specified. Also, in this specification, when describing an aspect in which another component is placed on the surface of a certain component, the term "on the surface side" or "on the surface" refers to both a case in which another component is placed directly above or below the component so as to be in contact with the component, and a case in which another component is placed above or below the component with another component interposed therebetween, unless otherwise specified.

[0028] Hereinafter, the present disclosure will be described in detail with respect to a first embodiment and a ninth embodiment.

[0029] I. First Embodiment A1. Through-hole Electrode Substrate A through-hole electrode substrate in this embodiment is a through-hole electrode substrate connected to a wiring substrate, and includes: a glass substrate having a first surface and a second surface opposing the first surface, and having a first through hole; a through-hole electrode disposed in the first through hole of the glass substrate; a multilayer insulating layer disposed on the first surface side of the glass substrate and having a plurality of insulating layers; and a conductive layer disposed between the insulating layers and electrically connected to the through-hole electrode; wherein the shear modulus of the multilayer insulating layer is G1 (GPa), the difference in strain between the wiring substrate and the glass substrate is γ1 (mm), and the total thickness of the multilayer insulating layer is h1 (mm), the shear modulus of elasticity G1 is 0.036 GPa or more, and a stress F1 calculated by the following (Equation 1-1) Ａ is 4.35 GPa or less. F1 Ａ =(G1×γ1) / h1 (Formula 1-1)

[0030] 1 is a schematic cross-sectional view showing an example of a through electrode substrate according to this embodiment. As shown in FIG. 1, the through electrode substrate 1A includes a glass substrate 2 having a first surface 2a and a second surface 2b opposite the first surface 2a, and a first through hole 2c, a through electrode 3 disposed in the first through hole 2c of the glass substrate 2, a multilayer insulating layer 4 disposed on the first surface 2a of the glass substrate 2 and having a plurality of first insulating layers 4a, and a first conductive layer 5 disposed between the first insulating layers 4a and electrically connected to the through electrode 3. In FIG. 1, the through electrode substrate 1A includes a first via 6 electrically connected to the through electrode 3 and electrically connecting the first conductive layers 4a, and a wiring board connection pad 11 disposed on the surface of the multilayer insulating layer 4 opposite the glass substrate 2 and electrically connected to the first conductive layer 5. In the following, the insulating layers that make up the multilayer insulating layer may be referred to as first insulating layers, the conductive layers arranged between each first insulating layer may be referred to as first conductive layers, and the vias that electrically connect each first conductive layer may be referred to as first vias.

[0031] 1 , the through electrode substrate 1A has a plurality of second insulating layers 14a arranged on the second surface 2b side of the glass substrate 2, second conductive layers 15 arranged between each of the second insulating layers 14a, and third vias 16 that electrically connect each of the second conductive layers 15. Furthermore, the through electrode substrate 1A has element connection pads 21 that are arranged on the surface of the second insulating layers 14a opposite the glass substrate 2, are electrically connected to the second conductive layers 15, and are electrically connected to the elements 30.

[0032] 2 is a schematic cross-sectional view showing an example of a through electrode substrate with elements having a through electrode substrate according to the present disclosure. As shown in Fig. 2, the through electrode substrate with elements 50A includes a through electrode substrate 1A, a second bonding portion 35 electrically connected to an element connection pad portion 21 of the through electrode substrate 1A, and an element 30 electrically connected to the second bonding portion 35.

[0033] 3 is a schematic cross-sectional view showing an example of a semiconductor device having a through electrode substrate according to the present disclosure. As shown in FIG. 3, a semiconductor device 10A includes a through electrode substrate 1A, a second bonding portion 35 electrically connected to an element connection pad 21 of the through electrode substrate 1A, an element 30 electrically connected to the second bonding portion 35, a first bonding portion 25 electrically connected to a wiring substrate connection pad 11 of the through electrode substrate 1A, and a wiring substrate 20 electrically connected to the first bonding portion 25. Hereinafter, the bonding portion electrically connecting the through electrode substrate and the element may be referred to as the second bonding portion, and the bonding portion electrically connecting the through electrode substrate and the wiring substrate may be referred to as the first bonding portion.

[0034] For example, if the second joint is a solder joint, and the through-hole electrode substrate and the element are joined via the solder joint during a reflow soldering process in the manufacturing process of the semiconductor device, the through-hole electrode substrate and the element expand due to heat and then contract due to cooling. If the difference in thermal expansion coefficient between the through-hole electrode substrate and the element is large, stress is generated in the second joint and the element connection pad, making cracks and disconnections more likely. Furthermore, for example, when the semiconductor device is used in a high-temperature environment, if the difference in thermal expansion coefficient between the through-hole electrode substrate and the element is large, stress is generated in the second joint and the element connection pad, making cracks and disconnections more likely.

[0035] In contrast, in the semiconductor device 10A of this embodiment, the through-hole electrode substrate 1A has a glass substrate 2, and the through-hole electrode substrate 1A is used as a so-called glass interposer. This reduces the difference in thermal expansion coefficient between the glass substrate 2 and the element 30, and suppresses stress from occurring in the second bonding portion 35 and the element connection pad portion 21. This prevents cracks and breaks in the second bonding portion 35 and the element connection pad portion 21.

[0036] Furthermore, for example, when the first joint portion is a solder joint portion and the through-hole electrode substrate and the wiring substrate are joined via the solder joint portion in a reflow soldering process in the manufacturing process of the semiconductor device, the through-hole electrode substrate and the wiring substrate expand due to heat and then contract due to cooling. At this time, if the difference in thermal expansion coefficient between the through-hole electrode substrate and the wiring substrate is large, disconnection between the through-hole electrode substrate and the wiring substrate is likely to occur. Furthermore, for example, when the semiconductor device is used in a high-temperature environment, if the difference in thermal expansion coefficient between the through-hole electrode substrate and the wiring substrate is large, stress is generated in the first joint portion and the wiring substrate connection pad portion, making cracks and disconnection more likely to occur.

[0037] The inventors of the present application have found, based on the experimental results described in Examples and Comparative Examples below, that the shear modulus of the multilayer insulating layer, the difference in the amount of strain between the wiring substrate and the glass substrate, and the stress F1 calculated from the total thickness of the multilayer insulating layer are Ａ It has been found that by making the shear modulus G1 of the multilayer insulating layer equal to or greater than a predetermined value, the stress acting on the first bonding portion and the wiring board connection pad portion can be suppressed, thereby preventing disconnection. Furthermore, it has been found that by making the shear modulus G1 of the multilayer insulating layer equal to or greater than a predetermined value, sufficient insulation properties can be obtained for the insulating layers constituting the multilayer insulating layer. This embodiment is based on such findings. Therefore, in this embodiment, the stress F1 calculated by the above (Equation 1-1) Ａ Furthermore, by having the shear modulus G1 within the above range, connection reliability can be improved.

[0038] Hereinafter, the through electrode substrate in this embodiment will be described for each configuration.

[0039] 1. Stress In this embodiment, when the shear modulus of the multilayer insulating layer is G1 (GPa), the difference in strain between the wiring substrate and the glass substrate is γ1 (mm), and the total thickness of the multilayer insulating layer is h1 (mm), the stress F1 calculated by the following (Equation 1-1) is Ａ is 4.35 GPa or less. F1 Ａ =(G1×γ1) / h1 (Formula 1-1)

[0040] Stress F1 Ａ is preferably 2.90 GPa or less, and more preferably 2.20 GPa or less. Ａ If the stress F1 is within the above range, cracks and breaks in the second bonding portion and the wiring board connection pad portion can be suppressed. Ａ is, for example, 0.052 GPa or more, may be 0.073 GPa or more, or may be 0.20 GPa or more. Ａ is preferably 0.052 GPa or more and 4.35 GPa or less, more preferably 0.073 GPa or more and 2.90 GPa or less, and particularly preferably 0.20 GPa or more and 2.20 GPa or less.

[0041] G1 indicates the shear modulus of elasticity of the multilayer insulating layer. The shear modulus of elasticity G1 of the multilayer insulating layer is 0.036 GPa or more, preferably 0.050 GPa or more, and more preferably 0.140 GPa or more. If the shear modulus of elasticity G1 of the multilayer insulating layer is within the above range, the insulating properties of the insulating layers constituting the multilayer insulating layer will be good. On the other hand, the shear modulus of elasticity G1 of the multilayer insulating layer is, for example, 3.0 GPa or less, and may be 2.0 GPa or less, or 1.5 GPa or less. When the shear modulus of elasticity G1 of the multilayer insulating layer is within the above range, the stress F1 Ａ Specifically, the shear modulus G1 of the multilayer insulating layer is preferably 0.036 GPa or more and 3.0 GPa or less, more preferably 0.050 GPa or more and 2.0 GPa or less, and particularly preferably 0.140 GPa or more and 1.5 GPa or less.

[0042] The shear modulus G1 of the multilayer insulating layer is measured using the following method. First, if a solder resist layer is disposed on the surface of the multilayer insulating layer opposite the glass substrate in the through-hole electrode substrate, the solder resist layer is removed. Next, the Young's modulus is measured for the surface of the multilayer insulating layer in accordance with ISO 14577. It is also possible to measure the Young's modulus for a cross section of the multilayer insulating layer. In this case, the measurement may be performed on the cross section of any of the first insulating layers constituting the multilayer insulating layer. The measured values ​​are equivalent and there is no substantial difference between measuring the Young's modulus for the surface of the multilayer insulating layer and measuring the Young's modulus for the cross section of the multilayer insulating layer. The measurement conditions are as follows: indenter: Berkovich indenter, pressure approach speed: 100 nm / sec, maximum load: 10 mN, load application rate: 50 mN / sec, maximum load holding time: 10 seconds, and unloading rate: 50 mN / sec. The measurement environment is a temperature of 25°C and a humidity of 60% RH. The measured Young's modulus is the Young's modulus of the multilayer insulating layer. The average value of the measurements at 10 different locations is then used. Next, the shear modulus G1 (GPa) of the multilayer insulating layer is calculated from the Young's modulus E1 (GPa) and the Poisson's ratio v1 of the multilayer insulating layer using the following formula. Note that the Poisson's ratio does not vary significantly depending on the resin material, and the Poisson's ratio of resin materials is generally around 0.4, so the Poisson's ratio v1 is set to 0.4. G1 = E1 / 2 (1 + v1)

[0043] γ1 indicates the difference (mm) in the amount of strain between the wiring substrate and the glass substrate. The difference γ1 in the amount of strain is, for example, 0.200 mm or less, preferably 0.150 mm or less, more preferably 0.100 mm or less, even more preferably 0.080 mm or less, and particularly preferably 0.070 mm or less. When the difference γ1 in the amount of strain is in the above range, the stress F1 Ａis likely to be in the above range. On the other hand, the difference γ1 in the amount of strain is, for example, 0.010 mm or more, may be 0.020 mm or more, may be 0.030 mm or more, or may be 0.040 mm or more. The difference γ1 in the amount of strain is, for example, 0.010 mm or more and 0.200 mm or less, preferably 0.010 mm or more and 0.150 mm or less, more preferably 0.020 mm or more and 0.100 mm or less, still more preferably 0.030 mm or more and 0.080 mm or less, and particularly preferably 0.040 mm or more and 0.070 mm or less.

[0044] The difference in strain amount γ1 can be calculated by the following formula (Formula 4): γ1 = |α1 - α2| × ΔT × (L / 2) (Formula 4) In the above formula 4, α1 is the thermal expansion coefficient of the wiring substrate ( / °C), α2 is the thermal expansion coefficient of the glass substrate ( / °C), ΔT is the difference between the heating temperature and room temperature, which is 230°C, and L is the length of the diagonal of the through electrode substrate.

[0045] The difference in strain γ1 is proportional to the difference |α1-α2| between the thermal expansion coefficient α1 of the wiring substrate and the thermal expansion coefficient α2 of the glass substrate. Therefore, it is preferable that the difference |α1-α2| between the thermal expansion coefficient α1 of the wiring substrate and the thermal expansion coefficient α2 of the glass substrate is small. It is preferable to reduce the difference |α1-α2| between the thermal expansion coefficient α1 of the wiring substrate and the thermal expansion coefficient α2 of the glass substrate, because this reduces the difference in strain γ1.

[0046] In this specification, the thermal expansion coefficient refers to the linear expansion coefficient. The thermal expansion coefficient of a glass substrate is measured by thermomechanical analysis (TMA) in accordance with JIS R3102:1995. The thermal expansion coefficient of a glass substrate is the average linear expansion coefficient from 30°C to 260°C. Measurement condition 1 for the thermal expansion coefficient of a glass substrate is shown below. Furthermore, the thermal expansion coefficient of a wiring board is measured by thermomechanical analysis (TMA) in accordance with JIS K7197:2012. The thermal expansion coefficient of a wiring board is the average linear expansion coefficient from 20°C to 180°C. Measurement condition 2 for the thermal expansion coefficient of a wiring board is shown below. As the TMA device, a "TMA-60" manufactured by Shimadzu Corporation can be used. <Measurement condition 1> Constant load tensile mode: 20 mN Measurement temperature range: 0°C to 300°C Temperature range for calculating linear expansion coefficient: 30°C to 260°C <Measurement condition 2> Constant load tensile mode: 20 mN Measurement temperature range: 0°C to 200°C Temperature range for calculating linear expansion coefficient: 20°C to 180°C The thermal expansion coefficient α1 of the wiring substrate and the thermal expansion coefficient α2 of the glass substrate will be described later.

[0047] The temperature difference ΔT was set to 230° C., assuming the difference between the heating temperature in the reflow soldering process and room temperature. Regarding the length L of the diagonal of the through hole electrode substrate, since the through hole electrode substrate usually has a rectangular shape in a plan view, half of the length of the diagonal was adopted as the position farthest from the center.

[0048] h1 indicates the total thickness (mm) of the multilayer insulating layer. The total thickness h1 of the multilayer insulating layer is, for example, 0.025 mm or more, may be 0.050 mm or more, or may be 0.075 mm or more. When the total thickness h1 of the multilayer insulating layer is in the above range, the stress F1 Ａ is likely to be within the above range. On the other hand, the total thickness h1 of the multilayer insulating layer is, for example, 0.200 mm or less, and may be 0.150 mm or less, or 0.125 mm or less. If the total thickness h1 of the multilayer insulating layer is too thick, it is disadvantageous in terms of cost. Specifically, the total thickness h1 of the multilayer insulating layer is, for example, 0.025 mm or more and 0.200 mm or less, preferably 0.050 mm or more and 0.150 mm or less, and more preferably 0.075 mm or more and 0.125 mm or less.

[0049] The multilayer insulating layer in this embodiment is a stack of insulating layers located between the glass substrate 2 and the first bonding portion 25, as shown in Fig. 1. In Fig. 1, a solder resist layer 12 is disposed on the surface of the multilayer insulating layer 4 opposite the glass substrate 2. The solder resist layer 12 is not normally present between the first bonding portion 25 and the multilayer insulating layer 4. Therefore, the solder resist layer 12 is not included in the multilayer insulating layer 4. The total thickness h1 of the multilayer insulating layer refers to the distance from the surface of the multilayer insulating layer 4 facing the glass substrate 2 to the surface of the multilayer insulating layer 4 opposite the glass substrate 2, as shown in Fig. 1.

[0050] In this specification, the thickness of each layer is measured based on an image of the cross section of the through hole electrode substrate taken using a scanning electron microscope (SEM). The thickness is the arithmetic average of thicknesses at any five points.

[0051] 2. Through electrode substrate The through electrode substrate in this embodiment includes a glass substrate 2 having a first surface 2 a and a second surface 2 b facing the first surface 2 a and having a first through hole 2 c, a through electrode 3 arranged in the first through hole 2 c of the glass substrate 2, a multilayer insulating layer 4 arranged on the first surface 2 a side of the glass substrate 2 and having a plurality of first insulating layers 4 a, and a first conductive layer 5 arranged between each of the first insulating layers 4 a and electrically connected to the through electrode 3.

[0052] (1) Multilayer Insulation Layer The multilayer insulation layer has multiple first insulation layers. The first insulation layers are not particularly limited as long as the multilayer insulation layer satisfies the shear modulus G1. The material of the first insulation layers is preferably an insulating resin. Examples of insulating resins include polyimide, polyamide, polyamideimide, polyethylene terephthalate, polyethylene naphthalate, polyphenylene sulfide, polyether ether ketone, polyether sulfone, polycarbonate, polyetherimide, epoxy resin, phenolic resin, polyphenylene ether, acrylic resin, polyolefin, polycycloolefin, and liquid crystal polymer compound. Examples of polyolefins include polyethylene and polypropylene. Examples of polycycloolefins include polynorbornene. From the viewpoint of good heat resistance and processability, epoxy resin and polyimide are preferred. The materials of the multiple first insulation layers may be the same or different.

[0053] In the present disclosure, in order for the multilayer insulating layer to satisfy the shear modulus G1, it is preferable to use a resin with a low Young's modulus as the material for the first insulating layer. Examples of such resins include the above-mentioned resins that have a flexible structure within the molecule. Examples of the flexible structure include a resin skeleton having a linear or branched hydrocarbon group.

[0054] The number of first insulating layers in the multilayer insulating layer is 2 or more, preferably 3 or more, and more preferably 4 or more, while the number of first insulating layers is preferably 10 or less, more preferably 8 or more, and particularly preferably 7 or less.

[0055] The thickness of the first insulating layer is, for example, 1.5 μm or more, and may be 2.5 μm or more. On the other hand, the thickness of the first insulating layer is, for example, 6 μm or less. The thickness of the first insulating layer is, for example, 1.5 μm or more and 6 μm or less, and may be 2.5 μm or more and 6 μm or less.

[0056] The first insulating layer may be formed by, for example, photolithography or printing.

[0057] (2) The first conductive layer and first via through electrode substrate have a first conductive layer disposed between each first insulating layer and electrically connected to the through electrode. The first conductive layer may be one layer or two or more layers. When the through electrode substrate has two or more first conductive layers, each first conductive layer is stacked in the thickness direction via a first insulating layer. Furthermore, each first conductive layer is electrically connected via a first via. For example, in FIG. 1 , a multilayer insulating layer 4 having multiple stacked first insulating layers 4 a and a first conductive layer 5 disposed between each first insulating layer 4 a are disposed on the first surface 2 a of the glass substrate 2, and each first conductive layer 5 is electrically connected by a first via 6. The first conductive layer 5 located on the surface opposite the glass substrate 2 of the first insulating layer 4 a disposed farthest from the glass substrate includes a wiring substrate connection pad portion 11.

[0058] The material for the first conductive layer is not particularly limited as long as it is a conductive material, and a conductive material generally used for wiring of an interposer can be used. Examples of conductive materials include metallic materials such as metals and metal oxides, conductive resins containing conductive fillers and resins, and conductive polymers.

[0059] The thickness of the first conductive layer is, for example, 0.1 μm or more, or may be 0.5 μm or more, 1 μm or more, 3 μm or more, or 5 μm or more. On the other hand, the thickness of the first conductive layer is, for example, 20 μm or less, or may be 15 μm or less. The thickness of the first conductive layer is, for example, 0.1 μm or more to 20 μm or less, or may be 0.5 μm or more to 15 μm or less, or 1 μm or more to 15 μm or less, or may be 3 μm or more to 15 μm or less, or may be 5 μm or more to 15 μm or less. For example, when the first conductive layer is formed by a sputtering method, a relatively thin first conductive layer can be obtained. Furthermore, when the first conductive layer is formed by a plating method, a relatively thick first conductive layer can be obtained.

[0060] The method for forming the first conductive layer may be an additive method or a subtractive method. In the additive method, for example, a resist pattern is formed by photolithography, and a patterned wiring layer is obtained by plating the portions exposed from the resist pattern. When using electrolytic plating, a conductive film may be formed on the first surface of the glass substrate or on the surface of the first insulating layer opposite the glass substrate before forming the resist pattern. In the subtractive method, for example, a resist pattern is formed on a conductive film formed on the entire first surface of the glass substrate, and the portions exposed from the resist pattern are etched to obtain a patterned first conductive layer.

[0061] The first via in this embodiment is electrically connected to the through electrode and the wiring board connection pad portion.

[0062] The material for the first via is not particularly limited as long as it is a conductive material, and conductive materials used for general vias can be used, and is selected appropriately depending on the shape of the via, the formation method, etc.

[0063] The first via can be formed by a common via formation method, which is appropriately selected depending on the shape of the via. In the first via formation method, a through hole is first formed in the first insulating layer, and then the first via is formed in the through hole in the first insulating layer. Examples of methods for forming a via in the through hole in the first insulating layer include PVD methods such as vacuum deposition and sputtering, CVD, and plating. A conductive material may be filled into the through hole in the first insulating layer to form a via, and simultaneously a wiring board connection pad may be formed from this conductive material. In the plating method, a through hole is first formed in the first insulating layer, and then a seed layer is formed on the entire surface of the first insulating layer by sputtering or the like. A photoresist layer is then formed on the seed layer, and the photoresist layer is subsequently patterned to have an opening for the wiring board connection pad. Next, electroplating is performed on the opening in the photoresist layer to form a plating layer, thereby simultaneously forming the first via and the wiring board connection pad. In this case, the first via and the wiring board connection pad have a seed layer and a plating layer.

[0064] (3) Glass Substrate The glass substrate in this embodiment has a first surface and a second surface opposite to the first surface, and has a first through-hole penetrating the glass substrate in the thickness direction.

[0065] Glass substrates have excellent flatness, allowing for the formation of fine wiring at narrow pitches. In addition, the thermal expansion coefficient of glass substrates can be adjusted by changing the composition, allowing for the selection of glass substrates with a desirable thermal expansion coefficient.

[0066] Examples of glass used for the glass substrate include alkali-free glass and quartz.

[0067] The thermal expansion coefficient of the glass substrate is preferably, for example, 2 ppm / ° C. to 9 ppm / ° C. If the thermal expansion coefficient of the glass substrate is within the above range, the difference between the thermal expansion coefficient of the glass substrate and the thermal expansion coefficient of the element can be sufficiently reduced.

[0068] The shape of the glass substrate in a plan view is not particularly limited, and examples thereof include rectangular shapes such as a rectangle and a square. The size of the glass substrate is not particularly limited, and when the glass substrate is rectangular, the length of the diagonal is, for example, 70 mm to 170 mm, or alternatively, 90 mm to 150 mm, or alternatively, 100 mm to 140 mm.

[0069] The planar shape of the first through hole in the glass substrate is, for example, substantially circular. The cross-sectional shape of the first through hole 2c in the glass substrate 2 can be, for example, a straight shape as shown in FIG. 4 , an inverted tapered shape as shown in FIG. 4(a) in which the opening diameter on the first surface 2a side is larger than the opening diameter on the second surface 2b side, a forward tapered shape as shown in FIG. 4(b) in which the opening diameter on the first surface 2a side is smaller than the opening diameter on the second surface 2b side, an hourglass shape as shown in FIG. 4(c) in which the diameter is minimum at a predetermined position between the first surface 2a and the second surface 2b, or a bowing shape as shown in FIG. 4(d) in which the diameter is maximum at a predetermined position between the first surface 2a and the second surface 2b. FIGS. 4(a) to 4(d) are schematic cross-sectional views illustrating examples of the cross-sectional shape of the first through hole in the glass substrate. The cross-sectional shape of the first through hole in the glass substrate is preferably either an inverted tapered shape or an hourglass shape. In addition, in each cross-sectional shape of the first through hole in the glass substrate, an edge E1 of the opening of the first through hole 2c on the first surface 2a of the glass substrate 2, an edge E2 of the opening of the first through hole 2c on the second surface 2b of the glass substrate 2, and a minimum and maximum diameter portions of the first through hole 2c on the glass substrate 2 preferably have curved surfaces, which can suppress disconnection between the through electrode and the via or conductive layer in contact with the through electrode.

[0070] The thickness of the glass substrate is, for example, 100 μm or more, or may be 200 μm or more, 300 μm or more, or 400 μm or more. Having a glass substrate thickness within the above range can prevent the glass substrate from warping too much. This can prevent the glass substrate from being difficult to handle during the manufacturing process or from warping due to internal stress of a thin film or the like disposed on the first or second surface of the glass substrate. On the other hand, the thickness of the glass substrate is, for example, 2000 μm or less, or may be 1000 μm or less, or may be 800 μm or less. A glass substrate thickness within the above range can shorten the time required for the process of forming through holes in the glass substrate. Specifically, the thickness of the glass substrate is 100 μm or more and 2000 μm or less, or may be 200 μm or more and 1000 μm or less, or 300 μm or more and 1000 μm or less, or 400 μm or more and 800 μm or less.

[0071] (4) Through Electrode The through electrode in this embodiment is disposed in the first through hole of the glass substrate.

[0072] The through electrode may be of any form, as long as it can electrically connect the first and second surfaces of the glass substrate. The through electrode may be, for example, a through electrode filling the first through hole of the glass substrate, a so-called filled via, or a through electrode arranged only on the side wall of the first through hole of the glass substrate, a so-called conformal via. Furthermore, when the through electrode is a conformal via, a hollow portion may be arranged within the first through hole, or the through hole may be filled with a resin portion. In particular, since the aforementioned problems due to thermal expansion and gas of the through electrode are likely to occur and the effects of the present disclosure are fully exhibited, it is preferable that the through electrode be a so-called filled via, in which the first through hole is filled with a conductive material.

[0073] The material of the through electrode is not particularly limited as long as it is a conductive material, and conductive materials commonly used for through electrodes can be used, and the material is appropriately selected depending on the shape of the through electrode, the method of formation, etc. Examples of materials for the through electrode include metals such as copper, gold, silver, platinum, rhodium, tin, aluminum, nickel, and chromium, and alloys containing these metals.

[0074] The through electrode may be a single layer or a multilayer structure having multiple layers stacked thereon. For example, the through electrode may have a seed layer disposed on the sidewall of the first through hole in the glass substrate and a plating layer disposed on the surface of the seed layer opposite the sidewall of the first through hole. The material of the seed layer can be appropriately selected from materials used for seed layers in general plating methods. The material of the seed layer is preferably a conductive material that has adhesion to the glass substrate, such as titanium, molybdenum, tungsten, tantalum, nickel, chromium, aluminum, compounds thereof, and alloys thereof. When the plating layer contains copper, the material of the seed layer is preferably a material that can suppress the diffusion of copper into the glass substrate, such as titanium nitride, molybdenum nitride, and tantalum nitride. The material of the plating layer is preferably a conductive material that has adhesion to the seed layer, such as the materials of the through electrode described above.

[0075] Furthermore, in the through electrode, it is preferable that an adhesion layer is disposed on the side wall of the first through hole in the glass substrate. The adhesion layer improves adhesion between the glass substrate and the through electrode. The adhesion layer has high adhesion to the glass substrate. Furthermore, the adhesion layer may have the role of suppressing diffusion of metal elements in the through electrode into the interior of the glass substrate via the side wall of the through hole. When the through electrode has an adhesion layer, the through electrode may have, in this order from the side wall side of the first through hole in the glass substrate, an adhesion layer, a seed layer, and a plating layer.

[0076] When the conductive material constituting the through electrode is copper, examples of the material for the adhesion layer include titanium, titanium oxide, titanium nitride, molybdenum, molybdenum nitride, tantalum, and tantalum nitride. The adhesion layer may be a single layer or a multilayer. In particular, it is preferable that the adhesion layer contains titanium oxide as a main component.

[0077] Furthermore, when the through electrode is a conformal via and the through hole is filled with a resin portion, examples of the material for the resin portion include epoxy resin, acrylic resin, polyimide, polyamide, polyester, etc.

[0078] As a method for forming the through electrode, a general method for forming a through electrode can be used, and is appropriately selected depending on the shape of the through electrode, etc. Examples of the method for forming the through electrode include PVD methods such as vacuum deposition and sputtering, CVD methods, and plating methods.

[0079] (5) Preferred Embodiments In the manufacture of semiconductor devices, heat treatments such as annealing and reflow soldering are performed. Figures 5(a) and 5(b) are schematic diagrams illustrating the state of a through electrode substrate during heat treatment in the manufacturing process of a semiconductor device. In a through electrode substrate having a through electrode 3 filled in a first through hole 2c as shown in Figure 5(a), a gap G may occur between the glass substrate 2 and the through electrode 3 during heat treatment, as shown in Figure 5(b), due to the difference in thermal expansion coefficients between the glass substrate 2 and the through electrode 3. Furthermore, as shown in Figure 5(b), the through electrode 3 may bulge relative to the first or second surface of the glass substrate 2 during heat treatment due to the difference in thermal expansion coefficients between the glass substrate 2 and the through electrode 3. Furthermore, during heat treatment, gas components such as moisture and hydrogen remaining in the material constituting the through electrode 3 may be released, pushing up the through electrode 3. Such a gap or bulge may cause a disconnection in the first conductive layer located near the boundary between the through electrode and the glass substrate. Furthermore, if such swelling propagates through the multilayer insulating layer, conductive layer, and via to the wiring board connection pad, the pad and the wiring connected to the pad may be disconnected, and a connection failure with the wiring board may occur.

[0080] 1 , of the multiple first insulating layers 4a in the multilayer insulating layer 4 arranged on the first surface 2a side of the glass substrate 2, the first insulating layer 4a located closest to the glass substrate 2 is preferably a first covering insulating layer 41. The first covering insulating layer 41 is arranged on the first surface 2a side of the glass substrate 2 so as to cover the boundary α between the through electrode 3 and the glass substrate 2, and has a second through hole 41c connecting to the first through hole 2c. A second via 7 electrically connected to the through electrode 3 is arranged in the second through hole 41c of the first covering insulating layer 41. Note that hereinafter, the covering insulating layer in the multilayer insulating layer may be referred to as the first covering insulating layer.

[0081] In this way, the first covering insulating layer is arranged so as to cover the boundary between the glass substrate and the through electrode, thereby making it possible to prevent disconnection of the conductive layer and pad portion arranged near the boundary between the through electrode and the glass substrate, thereby improving yield.

[0082] As described below, a resin is used for the first covering insulating layer 41. As shown in FIG. 1 , when the first covering insulating layer 41 is arranged to cover the boundary α between the glass substrate 2 and the through electrode 3, a portion of the first covering insulating layer 41 contacts a portion of the through electrode 3. Therefore, even if gas is released from inside the through electrode 3 during heat treatment, the gas can be released to the outside through the first covering insulating layer 41. This prevents swelling of the first conductive layer 5 arranged near the boundary α. Furthermore, because the first covering insulating layer 41 is arranged to cover the boundary α between the glass substrate 2 and the through electrode 3, even if a gap occurs between the through electrode 3 and the glass substrate 2 during heat treatment, the gap between the through electrode 3 and the glass substrate 2 can be covered by the first covering insulating layer 41, preventing disconnection of the first conductive layer 5 located on the boundary α. Furthermore, even if a step occurs between the through electrode 3 and the glass substrate 2 due to a gap or swelling during heat treatment, the first covering insulating layer 41 can absorb the step between the through electrode 3 and the glass substrate 2, thereby preventing a sudden step from occurring in the first conductive layer 5 disposed near the boundary α. Therefore, it is possible to prevent such swelling from being transmitted to the wiring board connection pad portion 11. ＡBy controlling the thickness to be within the above range and providing the first covering insulating layer 41, breakage and cracking of the wiring board connection pad portion 11 and the first bonding portion 25 can be further suppressed, resulting in a semiconductor device with even higher connection reliability.

[0083] The first covering insulating layer is preferably in direct contact with the glass substrate.

[0084] 6(a) to 6(c) are schematic cross-sectional views illustrating the arrangement of the first through hole of the glass substrate and the first covering insulating layer in the through electrode substrate. In FIGS. 6(a) to 6(c), components other than the glass substrate and the covering insulating layer are omitted. As shown in FIG. 6(a), the second through hole 41c in the first covering insulating layer 41 is connected to the first through hole 2c in the glass substrate 2. It is preferable that the central axis C1 of the first through hole 2c in the glass substrate 2 substantially coincides with the central axis C2 of the second through hole 41c in the covering insulating layer 41.

[0085] Furthermore, the opening diameter d2 of the second through hole 41c of the first covering insulating layer 41 on the glass substrate 2 side is preferably smaller than the opening diameter d1 of the first through hole 2c of the glass substrate 2 on the first surface 2a side. The ratio of d2 / d1 may be, for example, 0.5 or greater but less than 1.0, or 0.6 or greater but 0.9 or less. The opening diameter d1 of the first through hole 2c of the glass substrate 2 on the first surface 2a side may be, for example, 50 μm or greater but 100 μm or less, or 60 μm or greater but 90 μm or less. On the other hand, the opening diameter d2 of the second through hole 41c of the first covering insulating layer 41 on the glass substrate 2 side is not particularly limited and may be, for example, 40 μm or greater but 85 μm or less, or 50 μm or greater but 80 μm or less.

[0086] It is also preferable that an edge E4 of the opening of the second through hole 41c on the surface of the first covering insulating layer 41 facing the glass substrate 2 is located more inward than an edge E1 of the opening of the first through hole 2c on the first surface 2c of the glass substrate 2. By arranging the first covering insulating layer 41 having such second through hole 41c, the boundary α between the glass substrate 2 and the through electrode 3 can be covered by the first covering insulating layer 41.

[0087] The cross-sectional shape of the second through hole 41c in the first covering insulating layer 41 is preferably an inverted tapered shape, as shown in FIG. 6B , in which the opening diameter d2 of the second through hole 41c on the glass substrate 2 side is smaller than the opening diameter d3 of the second through hole 41c on the side opposite the glass substrate 2. When the second through hole 41c has an inverted tapered shape, the angle θ between the sidewall SS of the second through hole 41c and the surface of the first covering insulating layer 41 opposite the glass substrate 2 becomes an obtuse angle in a cross-sectional view in the thickness direction of the first covering insulating layer 41. Therefore, even if the through electrode 3 expands and bulges, stress concentration near the edge E3 of the opening of the second through hole 41c on the surface of the first covering insulating layer 41 opposite the glass substrate 2 can be suppressed. This suppresses disconnection of the pad portion and the conductive layer arranged on the surface of the covering insulating layer opposite the glass substrate.

[0088] The angle θ is not particularly limited and may be, for example, more than 90 degrees and not more than 130 degrees, or 100 degrees or more and not more than 120 degrees. By keeping the angle θ within the above range, disconnection of the pad portion and the conductive layer arranged on the surface of the first covering insulating layer opposite the glass substrate can be further suppressed. On the other hand, if the angle θ is too large, the opening diameter d3 of the second through hole 41c on the side opposite the glass substrate 2 becomes large, which may make it unsuitable for high-density mounting.

[0089] 6(c), in a cross-sectional view of the first covering insulating layer 41 in the thickness direction, it is preferable that an edge E3 of the opening of the second through hole 41c on the surface of the first covering insulating layer 41 opposite to the glass substrate 2 has a curved surface. By having the edge E3 have a curved surface, it is possible to further suppress disconnection of the pad portion and the conductive layer arranged on the surface of the first covering insulating layer opposite to the glass substrate.

[0090] The method for forming the second through holes is appropriately selected depending on the material of the first covering insulating layer, and examples thereof include photolithography and laser processing. In the case of photolithography, the material of the first covering insulating layer may be a photosensitive material, and a resist pattern may be formed on the first covering insulating layer.

[0091] The second via in this embodiment is disposed in the second through hole of the first covering insulating layer and is electrically connected to the through electrode, the first via, and the wiring board connection pad portion. The second via is preferably directly connected to the through electrode.

[0092] The second via may be a via that fills the second through hole in the first covering insulating layer, a so-called filled via, or a via that is arranged only on the side wall of the second through hole in the first covering insulating layer, a so-called conformal via.

[0093] The material of the second via is the same as the material of the through electrode, which will be described later. It is preferable that the material of the through electrode and the material of the second via are the same.

[0094] The second via can be formed by, for example, electrolytic plating. When the first conductive layer is disposed on the surface of the first coating insulating layer opposite to the glass substrate, the second via is preferably formed simultaneously with the first conductive layer.

[0095] (6) Wiring Board Connection Pad Portion The wiring board connection pad portion in this embodiment is disposed on the surface of the multilayer insulating layer opposite the glass substrate, and is electrically connected to the first via and the wiring board.

[0096] The material of the wiring board connection pad portion is not particularly limited as long as it is a conductive material, and conductive materials used in general wiring can be used. Examples of conductive materials that can be used include metals such as copper, molybdenum, titanium, tungsten, tantalum, aluminum, gold, silver, nickel, and palladium, alloys containing at least one selected from these metals, and metal oxides such as indium tin oxide (ITO) and indium zinc oxide (IZO). Among these, copper is preferably used.

[0097] The shape of the wiring board connection pad portion in plan view is not particularly limited, and examples thereof include a circle, an ellipse, a square, and a rectangle.

[0098] The thickness of the wiring board connection pad is the same as that of a general wiring. The thickness of the wiring board connection pad is, for example, 0.05 μm to 100 μm, or 0.1 μm to 50 μm, or 0.2 μm to 10 μm. This allows sufficient conductivity to be obtained.

[0099] The pad portion for connecting to the wiring board can be formed by a general wiring formation method, such as a dry film formation method using PVD methods such as CVD and sputtering, or a plating method, and then patterning the conductive film by photolithography.

[0100] Furthermore, it is preferable that the wiring substrate connection pads are regularly arranged in a plan view, which makes the thermal history of the first joints electrically connecting the through electrode substrate and the wiring substrate uniform during the manufacturing process of the semiconductor device using the through electrode substrate, thereby improving the yield.

[0101] (7) Second Insulating Layer, Second Conductive Layer, and Third Via The through electrode substrate in this embodiment may have a second insulating layer disposed on the second surface side of the glass substrate and electrically connected to the through electrode. It is preferable that a plurality of second insulating layers are stacked on the second surface side of the glass substrate. The number of layers of the second insulating layer is two or more, preferably three or more, and more preferably four or more. On the other hand, the number of layers of the second insulating layer is preferably 10 or less, more preferably eight or more, and particularly preferably seven or less.

[0102] The number of second insulating layers is preferably the same as the number of first insulating layers in the multilayer insulating layer. This is because warping of a large glass substrate can be suppressed when using a large glass substrate. This is also preferable because the first insulating layers and the second insulating layers can be alternately stacked on the glass substrate in the manufacturing process of the through hole electrode substrate.

[0103] The through-hole electrode substrate may have a second conductive layer disposed between each second insulating layer and electrically connected to the through-hole electrode. The second conductive layer may be a single layer or two or more layers. When the through-hole electrode substrate has two or more second conductive layers, the second conductive layers are stacked in the thickness direction via the second insulating layer. The second conductive layers are electrically connected via third vias. For example, in FIG. 1 , multiple second insulating layers 14a are stacked on the second surface 2b of the glass substrate 2, and second conductive layers 15 are partially disposed between the multiple second insulating layers 14a, and the second conductive layers 15 are electrically connected by third vias 16. The second conductive layer 15 located on the surface opposite the glass substrate 2 of the second insulating layer 14a disposed farthest from the glass substrate includes an element connection pad portion 21.

[0104] The second conductive layer and the second insulating layer are similar to the first conductive layer and the first insulating layer.

[0105] The shape of the element connection pad portion in plan view is the same as the shape of the wiring board connection pad portion in plan view.

[0106] 1 , of the plurality of second insulating layers 14a arranged on the second surface 2b side of the glass substrate 2, the second insulating layer 14a located closest to the glass substrate 2 is preferably a second covering insulating layer 141. The second covering insulating layer 141 is arranged on the second surface 2b side of the glass substrate 2 so as to cover the boundary β between the through electrode 3 and the glass substrate 2, and has a fourth through hole 141c connecting to the first through hole 2c. A fourth via 17 electrically connected to the through electrode 3 is arranged in the fourth through hole 141c of the second covering insulating layer 141. The fourth via 17 is electrically connected to the element connecting pad 21 via the second conductive layer 15 and the third via 16.

[0107] The second covering insulating layer has the same effect as the first covering insulating layer. The second covering insulating layer and the fourth via are similar to the first covering insulating layer and the second via, respectively.

[0108] (8) Solder Resist As shown in Fig. 1, the through hole electrode substrate 1A in this embodiment may have a solder resist layer 12 disposed on the surface of the multilayer insulating layer 4 opposite to the glass substrate 2. The solder resist layer 12 is not usually present between the wiring board connection pad portion 11 and the multilayer insulating layer 4. A general solder resist can be used as the solder resist.

[0109] (9) Through-hole electrode substrate The planar shape of the through-hole electrode substrate is not particularly limited, but examples thereof include rectangular shapes such as a rectangle, a square, etc. The size of the through-hole electrode substrate is not particularly limited, but when the through-hole electrode substrate is rectangular, the length of the diagonal line is, for example, 70 mm or more and 170 mm or less, or may be 90 mm or more and 150 mm or less, or may be 100 mm or more and 140 mm or less.

[0110] B1. Through-hole electrode substrate with element The through-hole electrode substrate with element in this embodiment has the through-hole electrode substrate described above and an element mounted on the through-hole electrode substrate.

[0111] 2 is a schematic cross-sectional view showing an example of an element-equipped through electrode substrate according to the present embodiment. As shown in Fig. 2, element-equipped through electrode substrate 50A includes the above-described through electrode substrate 1A, second bonding portions 35 electrically connected to element connection pad portions 21 of through electrode substrate 1A, and elements 30 electrically connected to second bonding portions 35.

[0112] The element-equipped through hole electrode substrate of this embodiment has the above-described through hole electrode substrate, and therefore can improve connection reliability.

[0113] Hereinafter, the element-equipped through hole electrode substrate according to this embodiment will be described for each configuration.

[0114] 1. Through Electrode Substrate The through electrode substrate has been described in detail above in "A1. Through Electrode Substrate," so a detailed description thereof will be omitted here.

[0115] 2. Elements In this embodiment, examples of elements include active elements such as ICs, transistors, and diodes, and passive elements such as resistors, capacitors, and inductors. Further, examples of elements include IC chips, LSI chips, and MEMS chips.

[0116] The element is mounted on the element connection pad of the through-hole electrode substrate via a second bonding portion. A bonding portion generally used for mounting elements can be used as the second bonding portion. The material of the second bonding portion is the same as the material of the first bonding portion described below.

[0117] Furthermore, an underfill resin portion may be disposed by filling an underfill resin between the through electrode substrate and the element, or the element may be sealed with a mold resin, so that the mold resin portion is disposed to cover the element.

[0118] C1. Semiconductor Device The semiconductor device in this embodiment includes the above-described element-equipped through electrode substrate, a joint electrically connected to the conductive layer in the through electrode substrate, and a wiring substrate electrically connected to the joint.

[0119] 3 is a schematic cross-sectional view showing an example of a semiconductor device according to the present disclosure. As shown in Fig. 3, semiconductor device 10A includes through-hole electrode substrate 1A, second bonding portions 35 electrically connected to element connection pad portions 21 of through-hole electrode substrate 1A, element 30 electrically connected to second bonding portions 35, first bonding portions 25 electrically connected to wiring board connection pads 11 of through-hole electrode substrate 1A, and wiring board 20 electrically connected to first bonding portions 25.

[0120] The semiconductor device of this embodiment has the above-described element-equipped through electrode substrate, and therefore can improve connection reliability.

[0121] Hereinafter, the semiconductor device according to the present disclosure will be described for each of its components.

[0122] 1. Through-hole electrode substrate with element Since the through-hole electrode substrate with element has been described in detail in "B1. Through-hole electrode substrate with element" above, a description thereof will be omitted here.

[0123] 2. Wiring Board and First Bonding Portion In this embodiment, a general wiring board can be used as the wiring board. The thermal expansion coefficient of the wiring board is, for example, 3 ppm / °C to 17 ppm / °C, and preferably 8 ppm / °C to 12 ppm / °C. If the thermal expansion coefficient of the wiring board is within the above range, the difference between the thermal expansion coefficient of the glass substrate and the thermal expansion coefficient of the wiring board becomes relatively large, which raises concerns about stress concentration in the second bonding portion and the wiring board connection pad portion. However, in this embodiment, the multilayer insulating layer can alleviate the stress applied to the second bonding portion and the wiring board connection pad portion.

[0124] The "thermal expansion coefficient of a wiring board" refers to the thermal expansion coefficient of a substrate used in the wiring board. Examples of the substrate include a resin substrate and a ceramic substrate. In particular, from the viewpoint of cost, the substrate used in the wiring board is preferably a resin substrate. Examples of the resin substrate include a glass epoxy substrate and a glass polyimide substrate.

[0125] The wiring board is electrically connected to the wiring board connection pad portion of the through electrode substrate via a first bonding portion, which may be made of a material such as solder, gold or a gold alloy, a conductive paste, an anisotropic conductive paste, or an anisotropic conductive film.

[0126] 3. Applications The applications of the semiconductor device of this embodiment are not particularly limited, and examples thereof include notebook personal computers, tablet terminals, mobile phones, smartphones, digital video cameras, digital cameras, digital clocks, and servers.

[0127] II. Second Embodiment A2. Through Electrode Substrate The through electrode substrate in this embodiment is a through electrode substrate connected to a wiring substrate, and includes a glass substrate having a first surface and a second surface opposing the first surface, and having a first through hole; a through electrode disposed in the first through hole of the glass substrate; a multilayer insulating layer having a plurality of insulating layers disposed on the first surface side of the glass substrate; an elastic insulating layer disposed on the surface of the multilayer insulating layer opposite the glass substrate; and conductive layers disposed between the insulating layers and between the multilayer insulating layer and the elastic insulating layer, and electrically connected to the through electrode; wherein the shear modulus G2 is 0.036 GPa or more, and a stress F2 calculated by the following (Equation 2-1) is Ａ is 4.35 GPa or less. F2 Ａ =(G2×γ1) / h2 (Formula 2-1)

[0128] 7 is a schematic cross-sectional view showing an example of a through electrode substrate according to this embodiment. As shown in FIG. 7 , the through electrode substrate 1B includes a glass substrate 2 having a first surface 2a and a second surface 2b opposite the first surface 2a, a through electrode 3 disposed in the first through hole 2c of the glass substrate 2, a multilayer insulating layer 4 disposed on the first surface 2a of the glass substrate 2 and having a plurality of first insulating layers 4a, an elastic insulating layer 8 disposed on the surface of the multilayer insulating layer 4 opposite the glass substrate 2, and a first conductive layer 5 disposed between the first insulating layers 4a and between the multilayer insulating layer 4 and the elastic insulating layer 8 and electrically connected to the through electrode 3. In FIG. 7 , the through electrode substrate 1B includes a first via 6 electrically connected to the through electrode 3 and electrically connecting the first conductive layers 4a, a fifth via 9 disposed in a third through hole 8c of the elastic insulating layer 8, and a wiring board connection pad 11 disposed on the surface of the elastic insulating layer 8 opposite the multilayer insulating layer 4 and electrically connected to the first conductive layer 5. In the following, the insulating layers that make up the multilayer insulating layer may be referred to as first insulating layers, the conductive layers arranged between each first insulating layer and between the multilayer insulating layer 4 and the elastic insulating layer 8 may be referred to as first conductive layers, and the vias that electrically connect each first conductive layer may be referred to as first vias.

[0129] 7, the through electrode substrate 1B has a plurality of second insulating layers 14a arranged on the second surface 2b side of the glass substrate 2, second conductive layers 15 arranged between each of the second insulating layers 14a, and third vias 16 that electrically connect each of the second conductive layers 15. Furthermore, the through electrode substrate 1B has element connection pads 21 that are arranged on the surface of the second insulating layers 14a opposite the glass substrate 2, are electrically connected to the second conductive layers 15, and are electrically connected to the elements 30.

[0130] 8 is a schematic cross-sectional view showing an example of a through electrode substrate with elements having a through electrode substrate according to the present disclosure. As shown in Fig. 8, the through electrode substrate with elements 50B has a through electrode substrate 1B, a second bonding portion 35 electrically connected to an element connection pad portion 21 of the through electrode substrate 1B, and an element 30 electrically connected to the second bonding portion 35.

[0131] 9 is a schematic cross-sectional view showing an example of a semiconductor device having a through electrode substrate according to the present disclosure. As shown in Fig. 9, a semiconductor device 10B includes a through electrode substrate 1B, a second bonding portion 35 electrically connected to an element connection pad 21 of the through electrode substrate 1B, an element 30 electrically connected to the second bonding portion 35, a first bonding portion 25 electrically connected to a wiring substrate connection pad 11 of the through electrode substrate 1B, and a wiring substrate 20 electrically connected to the first bonding portion 25.

[0132] For example, if the second joint is a solder joint, and the through-hole electrode substrate and the element are joined via the solder joint during a reflow soldering process in the manufacturing process of the semiconductor device, the through-hole electrode substrate and the element expand due to heat and then contract due to cooling. If the difference in thermal expansion coefficient between the through-hole electrode substrate and the element is large, stress is generated in the second joint and the element connection pad, making cracks and disconnections more likely. Furthermore, for example, when the semiconductor device is used in a high-temperature environment, if the difference in thermal expansion coefficient between the through-hole electrode substrate and the element is large, stress is generated in the second joint and the element connection pad, making cracks and disconnections more likely.

[0133] In contrast, in the semiconductor device 1 of this embodiment, the through electrode substrate 1B has the glass substrate 2, and the through electrode substrate 1B is used as a so-called glass interposer. This reduces the difference in thermal expansion coefficient between the glass substrate 2 and the element 30, and suppresses stress from occurring in the second bonding portion 35 and the element connection pad portion 21. This prevents cracks and disconnections in the second bonding portion 35 and the element connection pad portion 21.

[0134] Furthermore, for example, when the first joint portion is a solder joint portion and the through-hole electrode substrate and the wiring substrate are joined via the solder joint portion in a reflow soldering process in the manufacturing process of the semiconductor device, the through-hole electrode substrate and the wiring substrate expand due to heat and then contract due to cooling. At this time, if the difference in thermal expansion coefficient between the through-hole electrode substrate and the wiring substrate is large, disconnection between the through-hole electrode substrate and the wiring substrate is likely to occur. Furthermore, for example, when the semiconductor device is used in a high-temperature environment, if the difference in thermal expansion coefficient between the through-hole electrode substrate and the wiring substrate is large, stress is generated in the first joint portion and the wiring substrate connection pad portion, making cracks and disconnection more likely to occur.

[0135] In the semiconductor device 10B of this embodiment, an elastic insulating layer 8 having elasticity is disposed on the surface of the multilayer insulating layer 4 opposite the glass substrate 2, and therefore the surface of the elastic insulating layer 8 facing the wiring board connection pad 11 is stretchable. Furthermore, as the surface of the elastic insulating layer 8 facing the wiring board connection pad 11 stretches and contracts, the fifth via 9 disposed in the third through hole 8c of the elastic insulating layer 8 deforms obliquely. In this way, the surface of the elastic insulating layer 8 facing the wiring board connection pad 11 stretches and contracts, and the fifth via 9 deforms obliquely, thereby alleviating stress due to the difference in thermal expansion coefficients between the through electrode substrate 1 and the wiring substrate 20.

[0136] The inventors of the present application have found, based on the experimental results described in the Examples and Comparative Examples below, that the shear modulus of the multilayer insulating layer and the elastic insulating layer, the difference in the amount of strain between the wiring substrate and the glass substrate, and the stress F2 calculated from the thickness of the elastic insulating layer Ａ It has been found that by making the shear modulus G2 of the multilayer insulating layer and the elastic insulating layer equal to or greater than a predetermined value, the stress acting on the first bonding portion and the wiring board connection pad portion can be suppressed, thereby preventing disconnection. Furthermore, it has been found that by making the shear modulus G2 of the multilayer insulating layer and the elastic insulating layer equal to or greater than a predetermined value, the insulating properties of the insulating layers constituting the multilayer insulating layer and the elastic insulating layer can be sufficiently obtained. This embodiment is based on such findings. Therefore, in this embodiment, the stress F2 calculated by the above formula (2) Ａ Furthermore, by having the shear modulus G2 within the above range, connection reliability can be improved.

[0137] Hereinafter, the through electrode substrate in this embodiment will be described for each configuration.

[0138] 1. Stress In this embodiment, when the shear modulus of the multilayer insulating layer and the elastic insulating layer is G2 (GPa), the difference in strain between the wiring substrate and the glass substrate is γ1 (mm), and the thickness of the elastic insulating layer is h2 (mm), the stress F2 calculated by the following (Equation 2-1) is Ａ is 4.35 GPa or less. F2 Ａ =(G2×γ1) / h2 (Formula 2-1)

[0139] Stress F2 Ａ If the stress F2 is within the above range, cracks and breaks in the first bonding portion and the wiring board connection pad portion can be suppressed. Ａ is preferably 2.90 GPa or less, more preferably 2.20 GPa or less. Ａ is, for example, 0.052 GPa or more, may be 0.073 GPa or more, or may be 0.20 GPa or more. Ａ is preferably 0.052 GPa or more and 4.35 GPa or less, more preferably 0.073 GPa or more and 2.90 GPa or less, and particularly preferably 0.20 GPa or more and 2.2 GPa or less.

[0140] G2 indicates the shear modulus of elasticity of the multilayer insulating layer and the elastic insulating layer. The shear modulus of elasticity G2 of the multilayer insulating layer and the elastic insulating layer is 0.036 GPa or more. If the shear modulus of elasticity G2 of the multilayer insulating layer and the elastic insulating layer is within the above range, the insulating properties of the multilayer insulating layer and the elastic insulating layer will be good. The shear modulus of elasticity G2 of the multilayer insulating layer and the elastic insulating layer is preferably 0.050 GPa or more, and more preferably 0.14 GPa or more. On the other hand, the shear modulus of elasticity G2 of the multilayer insulating layer and the elastic insulating layer is, for example, 3.0 GPa or less, may be 2.0 GPa or less, or may be 1.5 GPa or less. When the shear modulus of elasticity G2 of the multilayer insulating layer and the elastic insulating layer is within the above range, the stress F2 Ａis likely to be in the above range. Specifically, the shear modulus G2 of the multilayer insulating layer and the elastic insulating layer is preferably 0.036 GPa or more and 3.0 GPa or less, more preferably 0.050 GPa or more and 2.0 GPa or less, and particularly preferably 0.14 GPa or more and 1.5 GPa or less. The "shear modulus of the multilayer insulating layer and the elastic insulating layer" refers to the shear modulus of the laminate of the multilayer insulating layer and the elastic insulating layer.

[0141] The shear modulus of the multilayer insulating layer and the elastic insulating layer is measured using the following method. First, if a solder resist layer is disposed on the surface of the elastic insulating layer opposite the glass substrate in the through-hole electrode substrate, the solder resist layer is removed. Next, the Young's modulus is measured on the surface of the elastic insulating layer in accordance with ISO 14577. It is also possible to measure the Young's modulus on the cross section of the elastic insulating layer. The measured values ​​are equivalent and there is no substantial difference between measuring the Young's modulus on the surface of the elastic insulating layer and measuring the Young's modulus on the cross section of the elastic insulating layer. The measurement conditions are as follows: indenter: Berkovich indenter, pressure approach speed: 100 nm / s, maximum load: 10 mN, load application rate: 50 mN / s, maximum load holding time: 10 seconds, and unloading rate: 50 mN / s. The measurement environment is a temperature of 25°C and a humidity of 60% RH. The measured Young's modulus is the Young's modulus of the laminate of the multilayer insulating layer and the elastic insulating layer. The average value of 10 measurement locations is used. Next, the shear modulus G2 (GPa) of the multilayer insulating layer and the elastic insulating layer is calculated from the Young's modulus E2 (GPa) of the laminate of the multilayer insulating layer and the elastic insulating layer and the Poisson's ratio v2 of the laminate of the multilayer insulating layer and the elastic insulating layer using the following formula. Note that the Poisson's ratio does not vary significantly depending on the resin material, and since the Poisson's ratio of resin materials is generally about 0.4, the Poisson's ratio v2 is set to 0.4: G2 = E2 / 2(1 + v2)

[0142] γ1 indicates the difference (mm) in the amount of distortion between the wiring substrate and the glass substrate. γ1 is the same as in the first embodiment, so a description thereof will be omitted here.

[0143] h2 indicates the thickness (mm) of the elastic insulating layer. The thickness of the elastic insulating layer is, for example, 5 μm or more, may be 15 μm or more, or may be 50 μm or more. If the thickness of the elastic insulating layer is within the above range, the surface of the elastic insulating layer on the wiring board connection pad side will be more likely to expand and contract. In addition, if the thickness h2 of the elastic insulating layer is within the above range, the stress F2 Ａ is likely to be within the above range. On the other hand, the thickness of the elastic insulating layer is, for example, 200 μm or less, may be 100 μm or less, or may be 60 μm or less. If the thickness of the elastic insulating layer is too thick, the thickness of the entire through-hole electrode substrate may become thick. Specifically, the thickness of the elastic insulating layer is 5 μm or more and 200 μm or less, may be 15 μm or more and 100 μm or less, or may be 50 μm or more and 60 μm or less. The thickness h2 of the elastic insulating layer refers to the distance from the surface of the elastic insulating layer 8 facing the multilayer insulating layer 4 to the surface of the elastic insulating layer 8 opposite the multilayer insulating layer 4, as shown in FIG. 7.

[0144] 2. Through electrode substrate The through electrode substrate in this embodiment includes a glass substrate 2 having a first surface 2a and a second surface 2b opposite the first surface 2a and having a first through hole 2c, a through electrode 3 arranged in the first through hole 2c of the glass substrate 2, a multilayer insulating layer 4 formed by stacking a plurality of first insulating layers 4a and arranged on the first surface 2a side of the glass substrate 2, an elastic insulating layer 8 arranged on the surface of the multilayer insulating layer 4 opposite the glass substrate 2, and a first conductive layer 5 electrically connected to the through electrode 3, arranged between each first insulating layer 4a and between the multilayer insulating layer 4 and the elastic insulating layer 8, and electrically connected to the through electrode 3.

[0145] (1) Multilayer Insulating Layer The multilayer insulating layer has multiple first insulating layers. The multiple first insulating layers are not particularly limited as long as they satisfy the shear modulus G2 when stacked together. In this embodiment, the material of the first insulating layer is preferably an insulating resin. Because the shear modulus G2 can be adjusted by the material of the elastic insulating layer, the insulating resin for the first insulating layer in this embodiment has greater freedom of material selection than in the first embodiment. Examples of insulating resins include polyimide, polyamide, polyamideimide, polyethylene terephthalate, polyethylene naphthalate, polyphenylene sulfide, polyether ether ketone, polyethersulfone, polycarbonate, polyetherimide, epoxy resin, phenolic resin, polyphenylene ether, acrylic resin, polyolefin, polycycloolefin, and liquid crystal polymer compound. Examples of polyolefins include polyethylene and polypropylene. Examples of polycycloolefins include polynorbornene. From the viewpoint of good heat resistance and processability, epoxy resin and polyimide are preferred.

[0146] The shear modulus G1' of the multilayer insulating layer in this embodiment is not particularly limited, but is 0.010 GPa or more, preferably 0.050 GPa or more, and more preferably 0.100 GPa or more. On the other hand, the shear modulus G1' of the multilayer insulating layer is, for example, 5.0 GPa or less, or may be 4.0 GPa or less, or may be 3.0 GPa or less. Specifically, the shear modulus G1' of the multilayer insulating layer is 0.010 GPa or more and 5.0 GPa or less, or may be 0.050 GPa or more and 4.0 GPa or less, or may be 0.100 GPa or more and 3.0 GPa or less.

[0147] Other details of the first insulating layer are the same as those in the first embodiment.

[0148] In the multilayer insulating layer, the insulating layer closest to the glass substrate is preferably a first covering insulating layer. The first covering insulating layer is arranged to cover at least the boundary between the through electrode and the glass substrate, and has a second through hole that connects to the first through hole in the glass substrate and penetrates the first covering insulating layer in the thickness direction. The first covering insulating layer and the second through hole in this embodiment are the same as those of the first covering insulating layer in the first embodiment. Furthermore, for example, a second via is arranged in the second through hole of the first covering insulating layer and is electrically connected to the through electrode, the first via, and the wiring board connection pad. The second via is preferably directly connected to the through electrode.

[0149] (2) First Conductive Layer and First Via The first conductive layer and first via in this embodiment are the same as the first conductive layer and first via in the first embodiment.

[0150] (3) Elastic Insulating Layer The elastic insulating layer in this embodiment is disposed on the surface of the multilayer insulating layer opposite the glass substrate, and has a third through-hole that penetrates the elastic insulating layer in the thickness direction.

[0151] (a) Physical Properties of the Elastic Insulating Layer The elastic modulus of the elastic insulating layer measured by nanoindentation is, for example, preferably 5 GPa or less, more preferably 1 GPa or less. If the elastic modulus is within the above range, the stress due to the difference in thermal expansion coefficient between the through-hole electrode substrate and the wiring substrate can be alleviated, and the stress F2 Ａ The modulus of elasticity is easily adjusted to fall within the above range. On the other hand, the modulus of elasticity is, for example, 0.01 GPa or more, and may be 0.05 GPa or more. Specifically, the modulus of elasticity is preferably 0.01 GPa or more and 5 GPa or less, and more preferably 0.05 GPa or more and 1 GPa or less.

[0152] The modulus of elasticity is measured by nanoindentation at 25°C in accordance with ISO 14577. Nanoindentation measurements are performed using a nanoindenter. For example, a HYSITRON "TI950 TriboIndenter" is used as the nanoindenter. A Berkovich indenter is used as the indenter. The surface of the elastic insulating layer onto which the Berkovich indenter is pressed is the surface of the elastic insulating layer facing the wiring board connection pad portion. The surface of the elastic insulating layer onto which the Berkovich indenter is pressed may also be the cross section of the elastic insulating layer. Measurements performed on the surface of the elastic insulating layer and on the cross section of the elastic insulating layer yield equivalent values, with no substantial difference. Measurement conditions are a maximum indentation depth of 100 nm, a loading time of 5 seconds, a holding time of 5 seconds, and an unloading time of 5 seconds. Measurements are performed at five random locations, and the arithmetic average value is used as the modulus of elasticity.

[0153] Furthermore, the elastic insulating layer preferably exhibits a thermal weight change rate of, for example, 3% or less when heated for 1 hour at 260° C. If the thermal weight change rate is within the above range, sufficient heat resistance can be obtained.

[0154] The rate of change in thermogravimetry is measured by thermogravimetry (TGA). The measurement conditions are as follows. For example, a "TGA550" manufactured by TA Instruments is used as the thermogravimetry measuring device. <Measurement conditions> Atmosphere: Nitrogen atmosphere Heating rate: 10°C / min Holding time: 1 hour

[0155] (b) Material for the Elastic Insulation Layer Examples of materials for the elastic insulation layer include elastomers. Examples of elastomers include styrene-based elastomers, olefin-based elastomers, urethane-based elastomers, amide-based elastomers, nitrile-based elastomers, vinyl chloride-based elastomers, ester-based elastomers, 1,2-polybutadiene-based elastomers, fluorine-based elastomers, silicone rubber, urethane rubber, fluorine-containing rubber, polybutadiene, polyisobutylene, polystyrene butadiene, and polychloroprene. The material for the elastic insulation layer may also be photosensitive.

[0156] (c) Method for forming the elastic insulating layer: The elastic insulating layer can be formed by applying the above-mentioned material. The method for forming the third through hole is appropriately selected depending on the material of the elastic insulating layer, and examples thereof include photolithography, laser processing, and shaping using a mold. In the case of photolithography, the material of the elastic insulating layer may be a photosensitive material, and a resist pattern may be formed on the elastic insulating layer. In the case of shaping using a mold, a concave-convex shape may be formed on the surface of the elastic insulating layer by shaping using the mold, and at the same time, a third through hole may be formed in the elastic insulating layer by shaping using the mold. Another example of a method for forming the concave-convex shape is shaping using a mold.

[0157] (4) Fifth Via The fifth via in this embodiment is disposed in the third through hole of the elastic insulating layer, and is electrically connected to the first via and the wiring board connection pad portion.

[0158] The material for the fifth via is not particularly limited as long as it is a conductive material, and conductive materials used for general vias can be used, and is selected appropriately depending on the shape of the via, the formation method, etc.

[0159] The fifth via can be formed by a common via formation method, which is appropriately selected depending on the shape of the via. In the fifth via formation method, a third through-hole is first formed in the elastic insulating layer, and then a fifth via is formed in the third through-hole of the elastic insulating layer. Examples of methods for forming a via in the third through-hole of the elastic insulating layer include PVD methods such as vacuum deposition and sputtering, CVD, and plating. A conductive material may be filled into the third through-hole of the elastic insulating layer to form a via, and simultaneously a wiring board connection pad may be formed using this conductive material. In the plating method, after first forming the third through-hole in the elastic insulating layer, a seed layer is formed on the entire surface of the elastic insulating layer by sputtering or the like, a photoresist layer is then formed on the seed layer, the photoresist layer is subsequently patterned to have an opening for the wiring board connection pad, and the opening in the photoresist layer is then electroplated to form a plating layer, thereby simultaneously forming the fifth via and the wiring board connection pad. In this case, the fifth via and the wiring board connection pad have a seed layer and a plating layer.

[0160] (5) Glass Substrate and Through Electrode The glass substrate and through electrode in this embodiment are the same as those in the first embodiment.

[0161] (6) Second Insulating Layer, Second Conductive Layer, and Third Via: The through-hole electrode substrate of this embodiment may have a second insulating layer disposed on the second surface of the glass substrate and electrically connected to the through-hole electrode. The through-hole electrode substrate may also have a second conductive layer disposed on the second surface of the glass substrate and partially interposed between the plurality of second insulating layers, electrically connected to the through-hole electrode. Each second conductive layer is electrically connected via a third via. As shown in FIG. 7 , in the through-hole electrode substrate 1B of this embodiment, among the plurality of second insulating layers 14a disposed on the second surface 2b of the glass substrate 2, the second insulating layer 14a closest to the glass substrate 2 is preferably the second covering insulating layer 141. A fourth via 17 electrically connected to the through-hole electrode 3 is disposed within a fourth through hole 141c of the second covering insulating layer 141. Details of the second insulating layer, second covering insulating layer, second conductive layer, third via, and fourth via are the same as those in the first embodiment.

[0162] (7) Others The through electrode substrate in this embodiment may have at least one of an element connection pad portion, a wiring substrate connection pad portion, and a solder resist. The details of the element connection pad portion, the wiring substrate connection pad portion, and the solder resist are the same as those in the first embodiment.

[0163] B2. Through-hole electrode substrate with element The through-hole electrode substrate with element in this embodiment has the through-hole electrode substrate described above and an element mounted on the through-hole electrode substrate.

[0164] 8 is a schematic cross-sectional view showing an example of an element-equipped through electrode substrate according to the present embodiment. As shown in Fig. 8, element-equipped through electrode substrate 50B includes through electrode substrate 1B described above, second bonding portion 35 electrically connected to element connection pad portion 21 of through electrode substrate 1B, and element 30 electrically connected to second bonding portion 35.

[0165] The element-equipped through hole electrode substrate of this embodiment has the above-described through hole electrode substrate, and therefore can improve connection reliability.

[0166] Hereinafter, the element-equipped through hole electrode substrate according to this embodiment will be described for each configuration.

[0167] 1. Through Electrode Substrate The through electrode substrate has been described in detail above in "A2. Through Electrode Substrate," so a detailed description thereof will be omitted here.

[0168] 2. Element and Second Joint Portion Details of the element and the second joint portion in this embodiment are the same as those in the first embodiment.

[0169] C2. Semiconductor Device The semiconductor device in this embodiment includes the above-described through hole electrode substrate with elements, a joint electrically connected to the conductive layer in the through hole electrode substrate, and a wiring substrate electrically connected to the joint.

[0170] 9 is a schematic cross-sectional view showing an example of a semiconductor device according to the present disclosure. As shown in Fig. 9, semiconductor device 10B includes through electrode substrate 1B, second bonding portions 35 electrically connected to element connection pads 21 of through electrode substrate 1B, elements 30 electrically connected to second bonding portions 35, first bonding portions 25 electrically connected to wiring board connection pads 11 of through electrode substrate 1B, and wiring board 20 electrically connected to first bonding portions 25.

[0171] The semiconductor device of this embodiment has the above-described element-equipped through electrode substrate, and therefore can improve connection reliability.

[0172] Hereinafter, the semiconductor device according to the present disclosure will be described for each of its components.

[0173] 1. Through-hole electrode substrate with element Since the through-hole electrode substrate with element has been described in detail in "B2. Through-hole electrode substrate with element" above, a description thereof will be omitted here.

[0174] 2. Wiring Board and First Joint Portion Details of the wiring board and the first joint portion are the same as those in the first embodiment.

[0175] 3. Uses The uses of the semiconductor device in this embodiment are the same as those in the first embodiment described above.

[0176] III. Third Embodiment A3. Through Electrode Substrate A through electrode substrate in this embodiment is a through electrode substrate connected to a wiring substrate, and includes a glass substrate having a first surface and a second surface opposing the first surface, and having a first through hole; a through electrode disposed in the first through hole of the glass substrate; a multilayer insulating layer disposed on the first surface side of the glass substrate and having a plurality of insulating layers; a hard insulating layer disposed on the surface of the multilayer insulating layer opposite the glass substrate; and conductive layers disposed between the insulating layers and between the multilayer insulating layer and the hard insulating layer and electrically connected to the through electrode; wherein the shear modulus G1 of the multilayer insulating layer is G1 (GPa), the difference in strain between the hard insulating layer and the glass substrate is γ2 (mm), and the total thickness of the multilayer insulating layer is h1 (mm), the shear modulus G1 is 0.036 GPa or more, and a stress F1 calculated by the following (Equation 1-2) Ｂ is 4.35 GPa or less, and when the thermal expansion coefficient of the wiring board is α1 ( / °C) and the thermal expansion coefficient of the hard insulating layer is α3 ( / °C), the difference in thermal expansion coefficient Δα calculated by the following (Equation 3) is 75% or less. Ｂ =(G1×γ2) / h1 (Formula 1-2) Δα=(|α1-α3| / α1)×100 (Formula 3)

[0177] 10 is a schematic cross-sectional view showing an example of a through electrode substrate according to this embodiment. As shown in Fig. 10, the through electrode substrate 1A includes a glass substrate 2 having a first surface 2a and a second surface 2b opposite to the first surface 2a and having a first through hole 2c, a through electrode 3 arranged in the first through hole 2c of the glass substrate 2, a multilayer insulating layer 4 arranged on the first surface 2a side of the glass substrate 2 and having a plurality of first insulating layers 4a, a hard insulating layer 19 arranged on the surface of the multilayer insulating layer 4 opposite the glass substrate 2, and a first conductive layer 5 arranged between each first insulating layer 4a and between the multilayer insulating layer 4 and the hard insulating layer 19, and electrically connected to the through electrode 3. 10 , the through electrode substrate 1A has a first via 6 electrically connected to the through electrode 3 and electrically connecting each first conductive layer 4a, a sixth via 18 arranged in a fifth through hole 19c of the hard insulating layer 19, and a wiring board connection pad portion 11 arranged on the side of the hard insulating layer 19 opposite the multilayer insulating layer 4 and electrically connected to the sixth via 18. Note that hereinafter, the insulating layers constituting the multilayer insulating layer will be referred to as first insulating layers, the conductive layers arranged between each first insulating layer and between the multilayer insulating layer and the hard insulating layer will be referred to as first conductive layers, the vias electrically connecting each first conductive layer will be referred to as first vias, and the vias arranged in the fifth through holes of the hard insulating layer will be referred to as sixth vias.

[0178] 10 , the through electrode substrate 1A has a plurality of second insulating layers 14a arranged on the second surface 2b side of the glass substrate 2, second conductive layers 15 arranged between each of the second insulating layers 14a, and third vias 16 that electrically connect each of the second conductive layers 15. Furthermore, the through electrode substrate 1A has element connection pads 21 that are arranged on the surface of the second insulating layers 14a opposite the glass substrate 2, are electrically connected to the second conductive layers 15, and are electrically connected to the elements 30.

[0179] 11 is a schematic cross-sectional view showing an example of a through electrode substrate with elements having a through electrode substrate according to the present disclosure. As shown in Fig. 11, the through electrode substrate with elements 50A includes a through electrode substrate 1A, a second bonding portion 35 electrically connected to an element connection pad portion 21 of the through electrode substrate 1A, and an element 30 electrically connected to the second bonding portion 35.

[0180] 12 is a schematic cross-sectional view showing an example of a semiconductor device having a through electrode substrate according to the present disclosure. As shown in Fig. 12, a semiconductor device 10A includes a through electrode substrate 1A, a second bonding portion 35 electrically connected to an element connection pad portion 21 of the through electrode substrate 1A, an element 30 electrically connected to the second bonding portion 35, a first bonding portion 25 electrically connected to a wiring substrate connection pad portion 11 of the through electrode substrate 1A, and a wiring substrate 20 electrically connected to the first bonding portion 25.

[0181] For example, if the second joint is a solder joint, and the through-hole electrode substrate and the element are joined via the solder joint during a reflow soldering process in the manufacturing process of the semiconductor device, the through-hole electrode substrate and the element expand due to heat and then contract due to cooling. If the difference in thermal expansion coefficient between the through-hole electrode substrate and the element is large, stress is generated in the second joint and the element connection pad, making cracks and disconnections more likely. Furthermore, for example, when the semiconductor device is used in a high-temperature environment, if the difference in thermal expansion coefficient between the through-hole electrode substrate and the element is large, stress is generated in the second joint and the element connection pad, making cracks and disconnections more likely.

[0182] In contrast, in the semiconductor device 10A of this embodiment, the through-hole electrode substrate 1A has a glass substrate 2, and the through-hole electrode substrate 1A is used as a so-called glass interposer. This reduces the difference in thermal expansion coefficient between the glass substrate 2 and the element 30, and suppresses stress from occurring in the second bonding portion 35 and the element connection pad portion 21. This prevents cracks and breaks in the second bonding portion 35 and the element connection pad portion 21.

[0183] Furthermore, for example, when the first joint portion is a solder joint portion and the through-hole electrode substrate and the wiring substrate are joined via the solder joint portion in a reflow soldering process in the manufacturing process of the semiconductor device, the through-hole electrode substrate and the wiring substrate expand due to heat and then contract due to cooling. At this time, if the difference in thermal expansion coefficient between the through-hole electrode substrate and the wiring substrate is large, disconnection between the through-hole electrode substrate and the wiring substrate is likely to occur. Furthermore, for example, when the semiconductor device is used in a high-temperature environment, if the difference in thermal expansion coefficient between the through-hole electrode substrate and the wiring substrate is large, stress is generated in the first joint portion and the wiring substrate connection pad portion, making cracks and disconnection more likely to occur.

[0184] The inventors of the present application conducted extensive research to reduce stress on the first joint and the wiring board connection pad. They discovered that by placing a hard insulating layer on the surface of the multilayer insulating layer opposite the glass substrate and reducing the difference in thermal expansion coefficient between the hard insulating layer and the wiring board, stress is more likely to be applied to the entire interface between the hard insulating layer and the multilayer insulating layer, reducing stress on the first joint and the wiring board connection pad located between the hard insulating layer and the wiring board. Typically, the difference in thermal expansion coefficient between the glass substrate and the wiring board is large, and therefore the difference in thermal expansion coefficient between the hard insulating layer and the wiring board is small. Therefore, stress is more likely to be applied to the interface between the hard insulating layer and the multilayer insulating layer. Furthermore, because the hard insulating layer is hard, stress is more likely to be applied to the entire interface between the hard insulating layer and the multilayer insulating layer. Therefore, force is distributed throughout the hard insulating layer. Therefore, stress is less likely to occur in the first conductive layer, the wiring board connection pad, and the first joint, which are disposed between the multilayer insulating layer and the hard insulating layer, and stress concentration in the first conductive layer, the wiring board connection pad, and the first joint, which are disposed between the multilayer insulating layer and the hard insulating layer, can be suppressed.

[0185] Furthermore, the inventors of the present application have found, based on the experimental results described in Examples and Comparative Examples below, that the shear modulus of the multilayer insulating layer, the difference in the amount of strain between the hard insulating layer and the glass substrate, and the stress F1 calculated from the total thickness of the multilayer insulating layer ＢIt has been found that by making the shear modulus G1 of the multilayer insulating layer equal to or greater than a predetermined value, the stress generated at the interface between the hard insulating layer and the multilayer insulating layer can be reduced. Furthermore, it has been found that by making the shear modulus G1 of the multilayer insulating layer equal to or greater than a predetermined value, the insulating layers constituting the multilayer insulating layer can have sufficient insulating properties. This embodiment is based on such findings.

[0186] Therefore, in this embodiment, a hard insulating layer is disposed on the surface of the multilayer insulating layer opposite to the glass substrate, and the stress F1 calculated by the above (Equation 1-2) Ｂ Furthermore, by having the shear modulus G1 of the multilayer insulating layer fall within the above range, disconnection can be suppressed and connection reliability can be improved.

[0187] Hereinafter, the through electrode substrate in this embodiment will be described for each configuration.

[0188] 1. Stress In this embodiment, when the shear modulus of the multilayer insulating layer is G1 (GPa), the difference in strain between the rigid insulating layer and the glass substrate is γ2 (mm), and the total thickness of the multilayer insulating layer is h1 (mm), the stress F1 calculated by the following (Equation 1-2) is Ｂ is 4.35 GPa or less. F1 Ｂ =(G1×γ2) / h1 (Formula 1-2)

[0189] Stress F1 Ｂ is preferably 2.90 GPa or less, and more preferably 2.20 GPa or less. Ｂ If the stress F1 is within the above range, the stress occurring at the interface between the hard insulating layer and the multilayer insulating layer can be reduced, and disconnection can be suppressed. Ｂ is, for example, 0.052 GPa or more, may be 0.073 GPa or more, or may be 0.100 GPa or more. Ｂ is preferably 0.052 GPa or more and 4.35 GPa or less, more preferably 0.073 GPa or more and 2.9 GPa or less, and particularly preferably 0.100 GPa or more and 2.20 GPa or less.

[0190] G1 indicates the shear modulus of elasticity of the multilayer insulating layer. The shear modulus of elasticity G1 of the multilayer insulating layer is the same as that described in the first embodiment above. The method for measuring the shear modulus of elasticity G1 of the multilayer insulating layer is also the same as that described in the first embodiment above. When measuring the shear modulus of elasticity G1 of the multilayer insulating layer, the hard insulating layer is also removed.

[0191] γ2 indicates the difference (mm) in the amount of strain between the hard insulating layer and the glass substrate. The difference γ in the amount of strain is, for example, 0.200 mm or less, preferably 0.150 mm or less, more preferably 0.100 mm or less, even more preferably 0.080 mm or less, and particularly preferably 0.070 mm or less. When the difference γ2 in the amount of strain is in the above range, the stress F1 Ｂ is likely to be in the above range. On the other hand, the difference γ2 in the amount of strain is, for example, 0.010 mm or more, and may be 0.020 mm or more, 0.030 mm or more, or 0.040 mm or more. The difference γ2 in the amount of strain is, for example, 0.010 mm or more and 0.200 mm or less, preferably 0.010 mm or more and 0.150 mm or less, more preferably 0.020 mm or more and 0.100 mm or less, still more preferably 0.030 mm or more and 0.080 mm or less, and particularly preferably 0.040 mm or more and 0.070 mm or less.

[0192] The difference in strain amount γ2 is found by the following formula (Formula 5): γ2 = |α2 - α3| × ΔT × (L / 2) (Formula 5) In the above formula 5, α2 is the thermal expansion coefficient of the glass substrate ( / °C), α3 is the thermal expansion coefficient of the hard insulating layer ( / °C), ΔT is the difference between the heating temperature and room temperature, which is 230°C, and L is the length of the diagonal of the through electrode substrate.

[0193] The difference in strain γ2 is proportional to the difference |α2-α3| between the thermal expansion coefficient α2 of the glass substrate and the thermal expansion coefficient α3 of the hard insulating layer. Therefore, it is preferable that the difference |α2-α3| between the thermal expansion coefficient α2 of the glass substrate and the thermal expansion coefficient α3 of the hard insulating layer is small. It is preferable to reduce the difference |α2-α3| between the thermal expansion coefficient α2 of the glass substrate and the thermal expansion coefficient α3 of the hard insulating layer, because this reduces the difference in strain γ2.

[0194] The thermal expansion coefficient of the hard insulating layer is measured by thermomechanical analysis (TMA) in accordance with JIS K7197:2012. The thermal expansion coefficient of the hard insulating layer is the average linear expansion coefficient from 20°C to 180°C. The conditions for measuring the thermal expansion coefficient of the hard insulating layer are the same as those for measuring the thermal expansion coefficient of the wiring board described in the first embodiment above.

[0195] The thermal expansion coefficient α1 of the wiring substrate, the thermal expansion coefficient α3 of the hard insulating layer, and the thermal expansion coefficient α2 of the glass substrate will be described later.

[0196] The temperature difference ΔT is the same as that described in the first embodiment.

[0197] h1 indicates the total thickness (mm) of the multilayer insulating layer, which is the same as that described in the first embodiment.

[0198] The multilayer insulating layer in this embodiment is a laminate of insulating layers located between the glass substrate 2 and the hard insulating layer 19, as shown in Fig. 10. The multilayer insulating layer does not include the hard insulating layer or the solder resist. The total thickness h1 of the multilayer insulating layer refers to the distance from the surface of the multilayer insulating layer 4 facing the glass substrate 2 to the surface of the multilayer insulating layer 4 opposite the glass substrate 2, as shown in Fig. 10.

[0199] 2. Through electrode substrate The through electrode substrate in this embodiment includes a glass substrate 2 having a first surface 2a and a second surface 2b opposite the first surface 2a and having a first through hole 2c, a through electrode 3 arranged in the first through hole 2c of the glass substrate 2, a multilayer insulating layer 4 arranged on the first surface 2a side of the glass substrate 2 and having a plurality of first insulating layers 4a, a hard insulating layer 19 arranged on the surface of the multilayer insulating layer 4 opposite the glass substrate 2, and first conductive layers 5 arranged between each first insulating layer 4a and between the multilayer insulating layer 4 and the hard insulating layer 19, and electrically connected to the through electrode 3.

[0200] (1) Hard Insulation Layer and Sixth Via: The hard insulation layer in the present disclosure is disposed on the surface of the multilayer insulation layer opposite the glass substrate, and has a predetermined thermal expansion coefficient. The hard insulation layer has, for example, a fifth through hole penetrating the hard insulation layer in the thickness direction, and a sixth via is disposed in the fifth through hole.

[0201] (a) Physical Properties of the Hard Insulation Layer In this embodiment, the difference Δα between the thermal expansion coefficient α3 of the hard insulation layer and the thermal expansion coefficient α1 of the wiring substrate, calculated by the following (Equation 3), is 75% or less: Δα=(|α1-α3| / α1)×100 (Equation 3)

[0202] The Δα is preferably 75% or less, more preferably 60% or less, and even more preferably 50% or less. If the Δα is within the above range, the hard insulating layer has a thermal expansion coefficient close to that of the wiring board, and therefore the hard insulating layer expands and contracts to the same extent as the wiring board. Therefore, stress is likely to occur at the interface between the hard insulating layer and the multilayer insulating layer. On the other hand, the smaller the Δα, the better, and there is no particular limit to the lower limit of the Δα.

[0203] The thermal expansion coefficient α3 of the hard insulating layer is not particularly limited as long as the above Δα is within a predetermined range, but is preferably, for example, 6 ppm / ° C. to 18 ppm / ° C. If the thermal expansion coefficient α3 of the hard insulating layer is within the above range, the above Δα can be made sufficiently small.

[0204] The shear modulus G3 of the hard insulating layer is 5.00 GPa or more, preferably 6.00 GPa or more, and more preferably 7.00 GPa or more. If the shear modulus G3 of the hard insulating layer is within the above range, the hard insulating layer is sufficiently hard and the effects of the hard insulating layer are easily obtained. On the other hand, the shear modulus G3 of the hard insulating layer is, for example, 12.0 GPa or less, or may be 11.0 GPa or less, or may be 10.0 GPa or less. Specifically, the shear modulus G3 of the hard insulating layer is preferably 5.00 GPa or more and 12.0 GPa or less, more preferably 6.00 GPa or more and 11.0 GPa or less, and particularly preferably 7.00 GPa or more and 10.0 GPa or less.

[0205] The shear modulus of the hard insulating layer is measured by the following method. First, the wiring substrate and the first bonding portion are removed from the semiconductor device. Furthermore, if a solder resist layer is disposed on the side of the hard insulating layer opposite the glass substrate in the through-hole electrode substrate, the solder resist layer is removed. Next, the Young's modulus is measured for the surface of the hard insulating layer in accordance with ISO 14577. It is also possible to measure the Young's modulus for the cross section of the hard insulating layer. The measured values ​​are equivalent and there is no substantial difference between measuring the Young's modulus for the surface of the hard insulating layer and measuring the Young's modulus for the cross section of the hard insulating layer. The measurement conditions are as follows: indenter: Berkovich indenter, pressure approach speed: 100 nm / s, maximum load: 10 mN, load application rate: 50 mN / s, maximum load holding time: 10 seconds, and unloading rate: 50 mN / s. The measurement environment is a temperature of 25°C and a humidity of 60% RH. The measured Young's modulus is the Young's modulus of the hard insulating layer. The average value of the measurements taken at 10 different locations is then used. Next, the shear modulus G3 (GPa) of the multilayer insulation layer is calculated from the Young's modulus E3 (GPa) of the hard insulation layer and the Poisson's ratio v3 of the hard insulation layer using the following formula. Note that the Poisson's ratio does not vary significantly depending on the resin material, and the Poisson's ratio of resin materials is generally around 0.4, so the Poisson's ratio v3 is set to 0.4. G3 = E3 / 2(1 + v3)

[0206] (b) Material for the Hard Insulation Layer The material for the hard insulation layer is not particularly limited as long as it has insulating properties and the above-mentioned thermal expansion coefficient and can form a hard layer. The hard insulation layer may contain, for example, a cured product of a curable resin composition, or may contain a resin component and a filler. It may also be a glass epoxy resin in which glass fibers are impregnated with an epoxy resin. In particular, it is preferable that the hard insulation layer contains a cured product of a curable resin composition containing a filler.

[0207] When the hard insulating layer contains a cured product of a curable resin composition, examples of the curable resin composition include a thermosetting resin composition and an ionizing radiation curable resin composition. Examples of the ionizing radiation curable resin composition include an electron beam curable resin composition and an ultraviolet light curable resin composition. Specifically, the curable resin composition can be a curable resin composition generally used for encapsulating resins. Among these, a thermosetting resin composition is preferred.

[0208] A thermosetting resin composition is a composition containing at least a thermosetting resin. Examples of thermosetting resins include acrylic resins, urethane resins, phenolic resins, urea melamine resins, epoxy resins, unsaturated polyester resins, and silicone resins. The thermosetting resins may be used alone or in combination of two or more. A curing agent may be added to the thermosetting resin composition as needed.

[0209] The curable resin composition preferably further contains a filler. The inclusion of a filler makes it possible to adjust the thermal expansion coefficient of the hard insulating layer. Examples of fillers include inorganic particles and organic particles. Examples of inorganic particles include particles made of inorganic materials such as silica, alumina, zirconia, titania, kaolinite, calcium carbonate, and barium sulfate. Examples of organic particles include particles made of resins such as acrylic resins, urethane resins, silicone resins, and polyamide resins such as nylon. One type of particle may be used alone, or two or more types may be used in combination.

[0210] The average particle size of the filler is not particularly limited. The average particle size of the filler is, for example, 0.1 μm or more and 3 μm or less, or may be 0.3 μm or more and 2.0 μm or more. The average particle size of the filler is the arithmetic average value when 20 random fillers are measured in an image of a cross section of the hard insulating layer observed with a scanning electron microscope (SEM).

[0211] When the hard insulating layer contains a resin component and a filler, the resin component is not particularly limited, and the filler is as described above.

[0212] When the hard insulation layer contains a filler, the content of the filler in the hard insulation layer is not particularly limited as long as the thermal expansion coefficient of the hard insulation layer can be set within a predetermined range. For example, the content of the filler may be 30 parts by mass or more and 90 parts by mass or less, or 40 parts by mass or more and 80 parts by mass or less, relative to 100 parts by mass of the resin component of the hard insulation layer.

[0213] The thickness of the hard insulating layer is, for example, 50 μm or more, and may be 100 μm or more. When the thickness of the hard insulating layer is in the above range, the thermal expansion coefficient α3 of the hard insulating layer is likely to be in the above range. On the other hand, the thickness of the hard insulating layer is, for example, 300 μm or less, and may be 200 μm or less. When the thickness of the hard insulating layer is in the above range, warping of the through electrode substrate can be suppressed in the case of a large-area through electrode substrate. Specifically, the thickness of the hard insulating layer is preferably 50 μm or more and 300 μm or less, and more preferably 100 μm or more and 200 μm or less.

[0214] (c) Sixth Via In this embodiment, the sixth via is disposed in the fifth through hole of the hard insulating layer and is electrically connected to the first via and the wiring board connection pad. The material of the sixth via is not particularly limited as long as it is a conductive material, and conductive materials used for general vias can be used, and the material is selected appropriately depending on the shape of the via, the formation method, etc.

[0215] The sixth via can be formed by a common via formation method, which is appropriately selected depending on the shape of the via. In the sixth via formation method, a fifth through-hole is first formed in the hard insulating layer, and then a sixth via is formed in the fifth through-hole in the hard insulating layer. Examples of methods for forming a via in the fifth through-hole in the hard insulating layer include PVD methods such as vacuum deposition and sputtering, CVD, and plating. A conductive material may be filled in the fifth through-hole in the hard insulating layer to form a via, and a wiring board connection pad may be formed from the conductive material. In the plating method, a fifth through-hole is first formed in the hard insulating layer, and then a seed layer is formed on the entire surface of the hard insulating layer by sputtering or the like. A photoresist layer is then formed on the seed layer. The photoresist layer is then patterned to have an opening for the wiring board connection pad. The opening in the photoresist layer is then electroplated to form a plating layer, thereby simultaneously forming the sixth via and the wiring board connection pad. In this case, the sixth via and the wiring board connection pad portion have a seed layer and a plating layer.

[0216] (2) Multilayer Insulation Layer The details of the multilayer insulation layer are the same as those in the first embodiment.

[0217] (3) The first conductive layer and first via-through electrode substrate has a first conductive layer disposed between each first insulating layer and electrically connected to the through electrode. The first conductive layers are electrically connected via the first vias. Details of the first conductive layers and the first vias are the same as those in the first embodiment.

[0218] (4) Glass Substrate The details of the glass substrate are the same as those in the first embodiment.

[0219] (5) Through Electrode Details of the through electrode are the same as those in the first embodiment.

[0220] (6) Preferred Aspect As shown in Figure 10, of the multiple first insulating layers 4a in the multilayer insulating layer 4 arranged on the first surface 2a side of the glass substrate 2, the first insulating layer 4a located closest to the glass substrate 2 is preferably a first covering insulating layer 41. The first covering insulating layer 41 is arranged on the first surface 2a side of the glass substrate 2 so as to cover the boundary α between the through electrode 3 and the glass substrate 2, and has a second through hole 41c connecting to the first through hole 2c. A second via 7 electrically connected to the through electrode 3 is arranged in the second through hole 41c of the first covering insulating layer 41. Details of the first covering insulating layer and the second through hole are the same as those in the first embodiment.

[0221] The second via in this embodiment is disposed in the second through hole of the first covering insulating layer and is electrically connected to the through electrode, the first conductive layer, the first via, the sixth via, and the wiring board connection pad. The second via is preferably directly connected to the through electrode. Details of the second via are the same as those in the first embodiment.

[0222] (7) Wiring Board Connection Pad The wiring board connection pad in this embodiment is disposed on the side of the hard insulating layer opposite the multilayer insulating layer, and is electrically connected to the sixth via and the wiring board. The details of the wiring board connection pad are the same as those in the first embodiment.

[0223] (8) Second insulating layer, second conductive layer, and third via The through electrode substrate in this embodiment may have a second insulating layer arranged on the second surface side of the glass substrate and electrically connected to the through electrode.

[0224] The through electrode substrate may have a second conductive layer disposed between each second insulating layer and electrically connected to the through electrode. The second conductive layers are electrically connected via a third via. For example, in FIG. 10 , a plurality of second insulating layers 14 a are stacked on the second surface 2 b of the glass substrate 2, and second conductive layers 15 are disposed partially between the plurality of second insulating layers 14 a, and the second conductive layers 15 are electrically connected by a third via 16. The second conductive layer 15 located on the surface opposite the glass substrate 2 of the second insulating layer 14 a disposed farthest from the glass substrate includes an element connection pad portion 21.

[0225] 10 , of the plurality of second insulating layers 14a arranged on the second surface 2b side of the glass substrate 2, the second insulating layer 14a located closest to the glass substrate 2 is preferably a second covering insulating layer 141. The second covering insulating layer 141 is arranged on the second surface 2b side of the glass substrate 2 so as to cover the boundary β between the through electrode 3 and the glass substrate 2, and has a fourth through hole 141c connecting to the first through hole 2c. A fourth via 17 electrically connected to the through electrode 3 is arranged in the fourth through hole 141c of the second covering insulating layer 141. The fourth via 17 is electrically connected to the element connecting pad 21 via the second conductive layer 15 and the third via 16.

[0226] The details of the second insulating layer, the second covering insulating layer, the second conductive layer, the third via, the fourth via, and the element connecting pad portion are the same as those in the first embodiment.

[0227] 10, the through hole electrode substrate 1A in this embodiment may have a solder resist layer 12 disposed on the surface of the hard insulating layer 19 opposite to the glass substrate 2. Details of the solder resist layer are the same as those in the first embodiment.

[0228] (10) Through Electrode Substrate The planar shape and size of the through electrode substrate are the same as those described in the first embodiment.

[0229] B3. Through-hole electrode substrate with element The through-hole electrode substrate with element in this embodiment has the through-hole electrode substrate described above and an element mounted on the through-hole electrode substrate.

[0230] 11 is a schematic cross-sectional view showing an example of a through hole electrode substrate with elements according to this embodiment. As shown in Fig. 11, the through hole electrode substrate with elements 50A includes the above-mentioned through hole electrode substrate 1A, second bonding portions 35 electrically connected to the element connection pad portions 21 of the through hole electrode substrate 1A, and elements 30 electrically connected to the second bonding portions 35.

[0231] The element-equipped through hole electrode substrate according to the present disclosure has the above-described through hole electrode substrate, and therefore can improve connection reliability.

[0232] Hereinafter, the element-equipped through hole electrode substrate according to this embodiment will be described for each configuration.

[0233] 1. Through Electrode Substrate The through electrode substrate has been described in detail above in "A3. Through Electrode Substrate," so a detailed description thereof will be omitted here.

[0234] 2. Element and Second Joint The details of the element and the second joint are the same as those in the first embodiment.

[0235] C3. Semiconductor Device The semiconductor device in this embodiment includes the element-equipped through electrode substrate described above, the joint portion electrically connected to the conductive layer in the through electrode substrate, and the wiring substrate electrically connected to the joint portion.

[0236] 12 is a schematic cross-sectional view showing an example of a semiconductor device according to the present disclosure. As shown in Fig. 12, a semiconductor device 10A includes the above-described through electrode substrate 1A, a second bonding portion 35 electrically connected to an element connection pad portion 21 of the through electrode substrate 1A, an element 30 electrically connected to the second bonding portion 35, a first bonding portion 25 electrically connected to a wiring board connection pad 11 of the through electrode substrate 1A, and a wiring board 20 electrically connected to the first bonding portion 25.

[0237] The semiconductor device of this embodiment has the above-described element-equipped through electrode substrate, and therefore can improve connection reliability.

[0238] Hereinafter, the semiconductor device according to the present disclosure will be described for each of its components.

[0239] 1. Through-hole electrode substrate with element Since the through-hole electrode substrate with element has been described in detail in "B3. Through-hole electrode substrate with element" above, a description thereof will be omitted here.

[0240] 2. Wiring Substrate and First Bonding Portion In this embodiment, a general wiring substrate can be used as the wiring substrate. The thermal expansion coefficient of the wiring substrate is, for example, 3 ppm / °C to 18 ppm / °C, preferably 8 ppm / °C to 16 ppm / °C. If the thermal expansion coefficient of the wiring substrate is within the above range, the difference between the thermal expansion coefficient of the glass substrate and the thermal expansion coefficient of the wiring substrate becomes relatively large, which raises concerns about stress concentration in the first bonding portion and the wiring substrate connection pad portion disposed between the glass substrate and the wiring substrate. However, in this embodiment, by disposing a hard insulating layer and a multilayer insulating layer between the glass substrate and the wiring substrate, stress is less likely to occur in the first bonding portion and the wiring substrate connection pad portion, thereby preventing disconnections.

[0241] The details of the wiring substrate and the first bonding portion are the same as those in the first embodiment.

[0242] 3. Uses The uses of the semiconductor device in this embodiment are the same as those in the first embodiment.

[0243] IV. Fourth Embodiment A4. Through Electrode Substrate The through electrode substrate in this embodiment is a through electrode substrate connected to a wiring substrate, and includes a glass substrate having a first surface and a second surface opposing the first surface, and having a first through hole; a through electrode disposed in the first through hole of the glass substrate; a multilayer insulating layer disposed on the first surface side of the glass substrate and having a plurality of insulating layers; an elastic insulating layer disposed on the surface of the multilayer insulating layer opposite the glass substrate; and a hard insulating layer disposed on the surface of the elastic insulating layer opposite the multilayer insulating layer. , and conductive layers disposed between the insulating layers, between the multilayer insulating layer and the elastic insulating layer, and between the elastic insulating layer and the hard insulating layer, and electrically connected to the through electrodes, wherein the shear modulus of the multilayer insulating layer and the elastic insulating layer is G2 (GPa), the difference in strain between the hard insulating layer and the glass substrate is γ2 (mm), and the thickness of the elastic insulating layer is h2 (mm), the shear modulus of elasticity G2 is 0.036 GPa or more, and a stress F2 calculated by the following (Equation 2-2) Ｂis 4.35 GPa or less, and when the thermal expansion coefficient of the wiring board is α1 ( / °C) and the thermal expansion coefficient of the hard insulating layer is α3 ( / °C), the difference in thermal expansion coefficient Δα calculated by the following (Equation 3) is 75% or less. Ｂ =(G2×γ2) / h2 (Formula 2-2) Δα=(|α1-α3| / α1)×100 (Formula 3)

[0244] 13 is a schematic cross-sectional view showing an example of a through electrode substrate according to this embodiment. As shown in FIG. 13, the through electrode substrate 1B includes a glass substrate 2 having a first surface 2a and a second surface 2b opposite the first surface 2a, a first through hole 2c, through electrodes 3 arranged in the first through holes 2c of the glass substrate 2, a multilayer insulating layer 4 arranged on the first surface 2a of the glass substrate 2 and having a plurality of first insulating layers 4a, an elastic insulating layer 13 arranged on the side of the multilayer insulating layer 4 opposite the glass substrate 2, a hard insulating layer 19 arranged on the side of the elastic insulating layer 13 opposite the multilayer insulating layer 4, and first conductive layers 5 arranged between the first insulating layers 4a, between the multilayer insulating layer 4 and the elastic insulating layer 13, and between the elastic insulating layer 13 and the hard insulating layer 19, and electrically connected to the through electrodes 3. 13 , the through electrode substrate 1B has a first via 6 electrically connected to the through electrode 3 and electrically connecting each first conductive layer 4a, a fifth via 9 arranged in a third through hole 13c of the elastic insulating layer 13, a sixth via 18 arranged in a fifth through hole 19c of the hard insulating layer 19, and a wiring board connection pad portion 11 arranged on the surface of the elastic insulating layer 13 opposite the multilayer insulating layer 4 and electrically connected to the first conductive layer 5. Note that hereinafter, the insulating layers constituting the multilayer insulating layer will be referred to as first insulating layers, the conductive layers arranged between each first insulating layer, between the multilayer insulating layer 4 and the elastic insulating layer 13, and between the elastic insulating layer 13 and the hard insulating layer 19 will be referred to as first conductive layers, and the vias electrically connecting each first conductive layer will be referred to as first vias, the vias arranged in the hard insulating layer 19 will be referred to as sixth vias, and the vias arranged in the elastic insulating layer 13 will be referred to as fifth vias.

[0245] 13 , the through electrode substrate 1B has a plurality of second insulating layers 14a arranged on the second surface 2b side of the glass substrate 2, second conductive layers 15 arranged between each of the second insulating layers 14a, and third vias 16 that electrically connect each of the second conductive layers 15. Furthermore, the through electrode substrate 1B has element connection pads 21 that are arranged on the surface of the second insulating layers 14a opposite the glass substrate 2, are electrically connected to the second conductive layers 15, and are electrically connected to the elements 30.

[0246] 14 is a schematic cross-sectional view showing an example of a through electrode substrate with elements having a through electrode substrate according to the present disclosure. As shown in Fig. 14, the through electrode substrate with elements 50B has a through electrode substrate 1B, a second bonding portion 35 electrically connected to an element connection pad portion 21 of the through electrode substrate 1B, and an element 30 electrically connected to the second bonding portion 35.

[0247] 15 is a schematic cross-sectional view showing an example of a semiconductor device having a through electrode substrate according to the present disclosure. As shown in Fig. 15, a semiconductor device 10B includes a through electrode substrate 1B, a second bonding portion 35 electrically connected to an element connection pad 21 of the through electrode substrate 1B, an element 30 electrically connected to the second bonding portion 35, a first bonding portion 25 electrically connected to a wiring substrate connection pad 11 of the through electrode substrate 1B, and a wiring substrate 20 electrically connected to the first bonding portion 25.

[0248] For example, if the second joint is a solder joint, and the through-hole electrode substrate and the element are joined via the solder joint during a reflow soldering process in the manufacturing process of the semiconductor device, the through-hole electrode substrate and the element expand due to heat and then contract due to cooling. If the difference in thermal expansion coefficient between the through-hole electrode substrate and the element is large, stress is generated in the second joint and the element connection pad, making cracks and disconnections more likely. Furthermore, for example, when the semiconductor device is used in a high-temperature environment, if the difference in thermal expansion coefficient between the through-hole electrode substrate and the element is large, stress is generated in the second joint and the element connection pad, making cracks and disconnections more likely.

[0249] In contrast, in the semiconductor device 10B of this embodiment, the through electrode substrate 1B has the glass substrate 2, and the through electrode substrate 1B is used as a so-called glass interposer. This reduces the difference in thermal expansion coefficient between the glass substrate 2 and the element 30, and suppresses stress from occurring in the second bonding portion 35 and the element connection pad portion 21. This prevents cracks and breaks in the second bonding portion 35 and the element connection pad portion 21.

[0250] Furthermore, for example, when the first joint portion is a solder joint portion and the through-hole electrode substrate and the wiring substrate are joined via the solder joint portion in a reflow soldering process in the manufacturing process of the semiconductor device, the through-hole electrode substrate and the wiring substrate expand due to heat and then contract due to cooling. At this time, if the difference in thermal expansion coefficient between the through-hole electrode substrate and the wiring substrate is large, disconnection between the through-hole electrode substrate and the wiring substrate is likely to occur. Furthermore, for example, when the semiconductor device is used in a high-temperature environment, if the difference in thermal expansion coefficient between the through-hole electrode substrate and the wiring substrate is large, stress is generated in the first joint portion and the wiring substrate connection pad portion, making cracks and disconnection more likely to occur.

[0251] The inventors of the present application conducted extensive research to reduce stress on the first joint and the wiring board connection pad. They discovered that by placing a hard insulating layer on the surface of the elastic insulating layer opposite the glass substrate and reducing the difference in thermal expansion coefficient between the hard insulating layer and the wiring board, stress is more likely to be applied to the entire interface between the hard insulating layer and the elastic insulating layer, reducing stress on the first joint and the wiring board connection pad located between the hard insulating layer and the wiring board. Typically, the difference in thermal expansion coefficient between the glass substrate and the wiring board is large, and therefore the difference in thermal expansion coefficient between the hard insulating layer and the wiring board is small, resulting in a larger difference in thermal expansion coefficient between the hard insulating layer and the glass substrate compared to the difference in thermal expansion coefficient between the hard insulating layer and the wiring board. This increases the stress on the interface between the hard insulating layer and the elastic insulating layer. Furthermore, because the hard insulating layer is hard, stress is more likely to be applied to the entire interface between the hard insulating layer and the elastic insulating layer. Therefore, force is distributed throughout the hard insulating layer. Therefore, stress is less likely to occur in the first conductive layer, the wiring board connection pad, and the first joint, which are disposed between the elastic insulating layer and the hard insulating layer, and stress concentration in the first conductive layer, the wiring board connection pad, and the first joint, which are disposed between the elastic insulating layer and the hard insulating layer, can be suppressed.

[0252] Furthermore, in the semiconductor device 10B of this embodiment, an elastic insulating layer 13 is disposed on the surface of the multilayer insulating layer 4 opposite the glass substrate 2, and the elastic insulating layer 13 is elastic and stretchable. Therefore, as the elastic insulating layer 13 stretches and contracts, the fifth via 9 disposed in the third through hole 13c of the elastic insulating layer 13 deforms obliquely. In this way, the elastic insulating layer 13 stretches and contracts, and the fifth via 9 deforms obliquely, thereby alleviating stress caused by the difference in thermal expansion coefficient between the through electrode substrate 1B and the wiring substrate 20.

[0253] Furthermore, the inventors of the present application have found, based on the experimental results described in the Examples and Comparative Examples below, that the shear modulus G2 of the multilayer insulating layer and the elastic insulating layer, the difference in the amount of strain between the rigid insulating layer and the glass substrate, and the stress F2 calculated from the thickness of the elastic insulating layer ＢIt has been found that by making the shear modulus G2 of the multilayer insulating layer and the elastic insulating layer equal to or less than a predetermined value, the stress generated at the interface between the hard insulating layer and the elastic insulating layer can be reduced. Furthermore, it has been found that by making the shear modulus G2 of the multilayer insulating layer and the elastic insulating layer equal to or greater than a predetermined value, the insulating properties of the insulating layers constituting the multilayer insulating layer and the elastic insulating layer can be sufficiently obtained. This embodiment is based on such findings.

[0254] Therefore, in this embodiment, an elastic insulating layer is disposed on the surface of the multilayer insulating layer opposite to the glass substrate, and a hard insulating layer is disposed on the surface of the elastic insulating layer opposite to the multilayer insulating layer, and the stress F2 calculated by the above (Equation 2-2) Ｂ Furthermore, by ensuring that the shear modulus G2 of the multilayer insulating layer and the elastic insulating layer is within the above range, disconnection can be suppressed and connection reliability can be improved.

[0255] Hereinafter, the through electrode substrate in this embodiment will be described for each configuration.

[0256] 1. Stress In the semiconductor device of this embodiment, when the shear modulus of elasticity of the multilayer insulating layer and the elastic insulating layer is G2 (GPa), the difference in strain between the hard insulating layer and the glass substrate is γ2 (mm), and the thickness of the elastic insulating layer is h2 (mm), the stress F2 calculated by the following (Equation 2-2) is Ｂ is 4.35 GPa or less. F2 Ｂ =(G2×γ2) / h2 (Formula 2-2) Stress F2 Ｂ If the stress F2 is within the above range, the stress occurring at the interface between the hard insulating layer and the elastic insulating layer can be reduced, and cracks and breaks in the first bonding portion and the wiring board connection pad portion can be suppressed. Ｂ is preferably 2.90 GPa or less, more preferably 2.20 GPa or less. Ｂ is, for example, 0.052 GPa or more, may be 0.073 GPa or more, or may be 0.100 GPa or more. Ｂ is preferably 0.052 GPa or more and 4.35 GPa or less, more preferably 0.073 GPa or more and 2.90 GPa or less, and particularly preferably 0.100 GPa or more and 2.20 GPa or less.

[0257] G2 indicates the shear modulus of elasticity of the multilayer insulating layer and the elastic insulating layer. The shear modulus of elasticity G2 of the multilayer insulating layer and the elastic insulating layer is the same as that described in the second embodiment above. The method for measuring the shear modulus of elasticity G2 of the multilayer insulating layer and the elastic insulating layer is also the same as that described in the second embodiment above. When measuring the shear modulus of elasticity G2 of the multilayer insulating layer and the elastic insulating layer, the hard insulating layer is also removed.

[0258] γ2 indicates the difference (mm) in the amount of strain between the hard insulating layer and the glass substrate. γ2 is the same as in the third embodiment, and therefore, a description thereof will be omitted here.

[0259] h2 indicates the thickness (mm) of the elastic insulating layer, which is the same as that described in the second embodiment.

[0260] 2. Through electrode substrate The through electrode substrate in this embodiment includes a glass substrate 2 having a first surface 2a and a second surface 2b opposite the first surface 2a and having a first through hole 2c, a through electrode 3 arranged in the first through hole 2c of the glass substrate 2, a multilayer insulating layer 4 formed by stacking a plurality of first insulating layers 4a and arranged on the first surface 2a side of the glass substrate 2, an elastic insulating layer 13 arranged on the side of the multilayer insulating layer 4 opposite the glass substrate 2, a hard insulating layer 19 arranged on the side of the elastic insulating layer 13 opposite the multilayer insulating layer 4, and a first conductive layer 5 electrically connected to the through electrode 3 and arranged between each of the first insulating layers 4a and between the multilayer insulating layer 4 and the elastic insulating layer 13, and electrically connected to the through electrode 3.

[0261] (1) Hard Insulation Layer and Sixth Via: The hard insulation layer in the present disclosure is disposed on the surface of the elastic insulation layer opposite the multilayer insulation layer, and has a predetermined thermal expansion coefficient. The hard insulation layer has, for example, a fifth through hole penetrating the hard insulation layer in the thickness direction, and a sixth via is disposed in the fifth through hole.

[0262] In this embodiment, the difference Δα between the thermal expansion coefficient α3 of the hard insulating layer and the thermal expansion coefficient α1 of the wiring substrate, calculated by the following (Equation 3), is 75% or less: Δα = (|α1 - α3| / α1) × 100 (Equation 3) Since Δα is the same as in the third embodiment, its explanation will be omitted here.

[0263] The hard insulating layer and the sixth via are the same as those in the third embodiment.

[0264] (2) Multilayer Insulation Layer The details of the multilayer insulation layer are the same as those in the second embodiment.

[0265] In the multilayer insulating layer, the insulating layer closest to the glass substrate is preferably the first covering insulating layer. The first covering insulating layer is arranged to cover at least the boundary between the through electrode and the glass substrate, and has a second through hole that connects to the first through hole in the glass substrate and penetrates the first covering insulating layer in the thickness direction. The first covering insulating layer and the second through hole in this embodiment are the same as those of the first covering insulating layer in the first embodiment. Furthermore, for example, a second via is arranged in the second through hole of the first covering insulating layer and is electrically connected to the through electrode, the first via, the fifth via, the sixth via, and the wiring board connection pad portion. The second via is preferably directly connected to the through electrode.

[0266] (3) First Conductive Layer and First Via The first conductive layer and first via in this embodiment are the same as the first conductive layer and first via in the first embodiment.

[0267] (4) Elastic Insulating Layer and Fifth Via: The elastic insulating layer in this embodiment is disposed on the surface of the multilayer insulating layer opposite the glass substrate and has a third through hole penetrating the elastic insulating layer in the thickness direction. The elastic insulating layer is disposed between the multilayer insulating layer and the hard insulating layer. The fifth via is disposed in the third through hole of the elastic insulating layer and is electrically connected to the first via, the sixth via, and the wiring board connection pad portion. Details of the elastic insulating layer and the fifth via are the same as those in the second embodiment.

[0268] (5) Glass Substrate and Through Electrode The glass substrate and through electrode in this embodiment are the same as those in the first embodiment.

[0269] (6) Second Insulating Layer, Second Conductive Layer, and Third Via: The through-hole electrode substrate of this embodiment may have a second insulating layer disposed on the second surface of the glass substrate and electrically connected to the through-hole electrode. The through-hole electrode substrate may also have a second conductive layer disposed on the second surface of the glass substrate and partially interposed between the plurality of second insulating layers, electrically connected to the through-hole electrode. Each second conductive layer is electrically connected via a third via. As shown in FIG. 13 , in the through-hole electrode substrate 1B of this embodiment, among the plurality of second insulating layers 14a disposed on the second surface 2b of the glass substrate 2, the second insulating layer 14a closest to the glass substrate 2 is preferably the second covering insulating layer 141. A fourth via 17 electrically connected to the through-hole electrode 3 is disposed within a fourth through hole 141c of the second covering insulating layer 141. Details of the second insulating layer, second covering insulating layer, second conductive layer, third via, and fourth via are the same as those in the first embodiment.

[0270] (7) Others The through electrode substrate in this embodiment may have at least one of an element connection pad portion, a wiring substrate connection pad portion, and a solder resist. The details of the element connection pad portion, the wiring substrate connection pad portion, and the solder resist are the same as those in the first embodiment.

[0271] B4. Through-hole electrode substrate with element The through-hole electrode substrate with element in this embodiment has the through-hole electrode substrate described above and an element mounted on the through-hole electrode substrate.

[0272] 14 is a schematic cross-sectional view showing an example of an element-equipped through electrode substrate according to the present embodiment. As shown in Fig. 14, element-equipped through electrode substrate 50B includes the above-described through electrode substrate 1B, second bonding portions 35 electrically connected to element connection pad portions 21 of through electrode substrate 1B, and elements 30 electrically connected to second bonding portions 35.

[0273] The element-equipped through hole electrode substrate according to the present disclosure has the above-described through hole electrode substrate, and therefore can improve connection reliability.

[0274] Hereinafter, the element-equipped through hole electrode substrate according to this embodiment will be described for each configuration.

[0275] 1. Through Electrode Substrate The through electrode substrate has been described in detail above in "A4. Through Electrode Substrate," so a detailed description thereof will be omitted here.

[0276] 2. Element and Second Joint Portion Details of the element and the second joint portion in this embodiment are the same as those in the first embodiment.

[0277] C4. Semiconductor Device The semiconductor device in this embodiment includes the above-described element-equipped through electrode substrate, a joint electrically connected to the conductive layer in the through electrode substrate, and a wiring substrate electrically connected to the joint.

[0278] 15 is a schematic cross-sectional view showing an example of a semiconductor device according to the present disclosure. As shown in Fig. 15, a semiconductor device 10B includes the through electrode substrate 1B described above, a second bonding portion 35 electrically connected to an element connection pad portion 21 of the through electrode substrate 1B, an element 30 electrically connected to the second bonding portion 35, a first bonding portion 25 electrically connected to a wiring board connection pad 11 of the through electrode substrate 1B, and a wiring board 20 electrically connected to the first bonding portion 25.

[0279] The semiconductor device of this embodiment has the above-described element-equipped through electrode substrate, and therefore can improve connection reliability.

[0280] Hereinafter, the semiconductor device according to the present disclosure will be described for each of its components.

[0281] 1. Through-hole electrode substrate with element Since the through-hole electrode substrate with element has been described in detail in "B4. Through-hole electrode substrate with element" above, a description thereof will be omitted here.

[0282] 2. Wiring Board and First Joint Portion Details of the wiring board and the first joint portion are the same as those in the first embodiment.

[0283] 3. Uses The uses of the semiconductor device in this embodiment are the same as those in the first embodiment described above.

[0284] V. Fifth Embodiment A5. Connection Board The connection board in this embodiment is a connection board for electrically connecting a glass substrate and a through electrode substrate having through electrodes penetrating the glass substrate to a wiring substrate, and includes a resin layer and a conductive portion penetrating the resin layer, wherein the thermal expansion coefficient in the plane direction of the resin layer is between the thermal expansion coefficient in the plane direction of the glass substrate and the thermal expansion coefficient in the plane direction of the wiring substrate, and the shear modulus of the resin layer is 0.036 GPa or more and 20 GPa or less.

[0285] FIG. 16 is a schematic cross-sectional view showing an example of a connection board according to this embodiment. As shown in FIG. 16 , a connection board 70A has a first surface 72a and a second surface 72b opposite the first surface 72a. The connection board 70A includes a resin layer 72 having a through hole 72c, and a conductive portion 73 disposed in the through hole 72c of the resin layer 72 and penetrating the resin layer 72. The connection board 70A is used to connect a through electrode substrate having a glass substrate to a wiring substrate. In this embodiment, the thermal expansion coefficient of the resin layer 72 in the plane direction is between the thermal expansion coefficient of the glass substrate and the thermal expansion coefficient of the wiring substrate in the plane direction. The shear modulus of the resin layer 72 is within a predetermined range. The connection board 70A in FIG. 16 includes a wiring substrate connection pad 81 disposed on the first surface 72a of the resin layer 72 and electrically connected to the wiring substrate, and a through electrode substrate connection pad 82 disposed on the second surface 72b of the resin layer 72 and electrically connected to the through electrode substrate.

[0286] 17 is a schematic cross-sectional view showing an example of a semiconductor device having a connection substrate according to this embodiment. As shown in FIG. 17, the semiconductor device 10A includes the connection substrate 70A described above, a fourth bonding portion 62 electrically connected to the through electrode substrate connection pad portion 82 of the connection substrate 70A, a through electrode substrate 1 electrically connected to the fourth bonding portion 62, a third bonding portion 61 electrically connected to the wiring substrate connection pad portion 81 of the connection substrate 70A, a wiring substrate 20 electrically connected to the third bonding portion 61, a fifth bonding portion 63 electrically connected to the element connection pad portion 84 of the through electrode substrate 1, and an element 30 electrically connected to the fifth bonding portion 63. Hereinafter, the bonding portion electrically connecting the connection substrate and the wiring substrate will be referred to as the third bonding portion, the bonding portion electrically connecting the connection substrate and the through electrode substrate will be referred to as the fourth bonding portion, and the bonding portion electrically connecting the through electrode substrate and the element will be referred to as the fifth bonding portion.

[0287] The through electrode substrate 1 has a first surface 2a and a second surface 2b opposite the first surface 2a, a glass substrate 2 having a first through hole 2c, and a through electrode 3 arranged in the first through hole 2c of the glass substrate 2. The through electrode substrate 1 in Fig. 17 further has a multilayer insulating layer 4 having a plurality of first insulating layers 4a arranged on the first surface 2a side of the glass substrate 2, and a first conductive layer 5 arranged between each first insulating layer 4a and electrically connected to the through electrode 3. In Fig. 17, the through electrode substrate 1 has first vias 6 electrically connected to the through electrodes 3 and electrically connecting each first conductive layer 5, and connection substrate connection pads 83 arranged on the surface of the multilayer insulating layer 4 opposite the glass substrate 2 and electrically connected to the first conductive layer 5. In the following, the insulating layer arranged on the first surface side of the glass substrate may be referred to as the first insulating layer, the conductive layer arranged between each first insulating layer may be referred to as the first conductive layer, and the via electrically connecting each first conductive layer may be referred to as the first via.

[0288] 17 includes a multilayer insulating layer 14 having a plurality of second insulating layers 14a arranged on the second surface 2b side of the glass substrate 2, second conductive layers 15 arranged between the second insulating layers 14a, and third vias 16 that electrically connect the second conductive layers 15. Furthermore, the through electrode substrate 1 includes an element connection pad 84 arranged on the surface of the multilayer insulating layer 14 opposite the glass substrate 2, electrically connected to the second conductive layer 15, and electrically connected to the element 30.

[0289] Conventionally, a through-hole electrode substrate and a wiring substrate are electrically connected via a joint. For example, the joint connecting the through-hole electrode substrate and the wiring substrate is a solder joint. When the through-hole electrode substrate and the wiring substrate are connected via the solder joint during a reflow soldering process in a semiconductor device manufacturing process, the through-hole electrode substrate and the wiring substrate expand due to heat and then contract due to cooling. At this time, if the difference in thermal expansion coefficient between the through-hole electrode substrate and the wiring substrate is large, stress is generated in the joint connecting the through-hole electrode substrate and the wiring substrate and in the pad connected to this joint, making cracks and disconnections more likely. Furthermore, for example, when a semiconductor device is used in a high-temperature environment, if the difference in thermal expansion coefficient between the through-hole electrode substrate and the wiring substrate is large, stress is generated in the joint connecting the through-hole electrode substrate and the wiring substrate and in the pad connected to this joint, making cracks and disconnections more likely.

[0290] On the other hand, in the present disclosure, the through electrode substrate and the wiring substrate are electrically connected via a connection substrate. The through electrode substrate and the connection substrate are electrically connected via a joint, and the connection substrate and the wiring substrate are electrically connected via a joint. In this embodiment, the thermal expansion coefficient of the connection substrate in the plane direction is between the thermal expansion coefficient of the glass substrate constituting the through electrode substrate and the thermal expansion coefficient of the wiring substrate in the plane direction. Therefore, the difference in thermal expansion coefficient between the through electrode substrate and the connection substrate, and the difference in thermal expansion coefficient between the connection substrate and the wiring substrate, can be made smaller than the difference in thermal expansion coefficient between the through electrode substrate and the wiring substrate. Therefore, by disposing a connection substrate having a thermal expansion coefficient intermediate between that of the glass substrate and that of the wiring substrate between the through electrode substrate and the wiring substrate, stress generated in the joints and pads disposed between the through electrode substrate and the connection substrate, and in the joints and pads disposed between the connection substrate and the wiring substrate, can be alleviated.

[0291] Furthermore, as described above, because the difference in thermal expansion coefficient between the through-hole electrode substrate and the wiring substrate is large, shear stress occurs in the connection substrate due to thermal expansion. In this embodiment, the shear modulus of the resin layer is within a predetermined range, so the connection substrate is less likely to deform due to shear stress, and the rigidity of the connection substrate is increased. Therefore, by optimizing the shear modulus of the resin layer, stress generated in the joints and pads arranged between the through-hole electrode substrate and the connection substrate, and in the joints and pads arranged between the connection substrate and the wiring substrate, can be alleviated.

[0292] Therefore, in this embodiment, it is possible to prevent cracks and breaks from occurring in the bonding portions and pad portions as described above, and to improve connection reliability.

[0293] Furthermore, in order to improve connection reliability, it is also possible to arrange a member for stress relief in the through electrode substrate. However, as mentioned above, the size of through electrode substrates is increasing, and there are concerns about a decrease in yield. In this embodiment, the connection substrate is fabricated separately from the through electrode substrate and the wiring substrate, which improves yield. Therefore, manufacturing costs can be reduced.

[0294] Hereinafter, the connection board in this embodiment will be described in detail for each component.

[0295] 1. Resin Layer The connection board in this embodiment includes a resin layer 72. As shown in Fig. 16, the resin layer 72 has a first surface 72a and a second surface 72b facing the first surface 72a, and has a through hole 72c penetrating the resin layer 72 in the thickness direction.

[0296] (1) Resin Layer Characteristics (a) Shear Modulus The shear modulus of the resin layer is 0.036 GPa or more, preferably 0.1 GPa or more, and more preferably 1 GPa or more. On the other hand, the shear modulus of the resin layer is 20 GPa or less, preferably 10 GPa or less, and more preferably 5 GPa or less. Specifically, the shear modulus of the resin layer is 0.036 GPa or more and 20 GPa or less, preferably 0.1 GPa or more and 10 GPa or less, and more preferably 1 GPa or more and 5 GPa or less. If the shear modulus of the resin layer is within the above range, the connection substrate is less likely to deform under shear stress, and the rigidity of the connection substrate is increased. Therefore, stress generated in the bonding portions and pad portions arranged between the through-hole electrode substrate and the connection substrate, and the bonding portions and pad portions arranged between the connection substrate and the wiring substrate, can be alleviated.

[0297] The shear modulus of the resin layer can be adjusted by the type of resin that is the material of the resin layer and the amount of filler added.

[0298] The shear modulus of the resin layer is measured by the following method. First, the Young's modulus is measured on the surface of the resin layer in accordance with ISO 14577. It should be noted that the Young's modulus may also be measured on the cross section of the resin layer. When measuring the Young's modulus on the surface of the resin layer, the measured values ​​are equivalent and there is no substantial difference between them. The measurement conditions are as follows: indenter: Berkovich indenter, pressure approach speed: 100 nm / sec, maximum load: 10 mN, load application rate: 50 mN / sec, maximum load holding time: 10 sec, unloading rate: 10 mN / sec. The measurement environment is temperature: 25°C, humidity: 60% RH. The measured Young's modulus is the Young's modulus of the resin layer. The average value of 10 different measurement locations is then adopted. The shear modulus G11 (GPa) of the resin layer is calculated from the Young's modulus E11 (GPa) of the resin layer and the Poisson's ratio v11 of the resin layer using the following formula: The Poisson's ratio does not vary significantly depending on the resin material, and since the Poisson's ratio of resin materials is generally about 0.4, the Poisson's ratio v11 is set to 0.4. G11 = E11 / 2(1 + v11)

[0299] (b) Thermal Expansion Coefficient: The thermal expansion coefficient of the resin layer in the plane direction is between that of the glass substrate and that of the wiring substrate. Since the thermal expansion coefficient of the resin layer in the plane direction is between that of the glass substrate and that of the wiring substrate, the difference in the thermal expansion coefficients between the through-hole electrode substrate and the connection substrate, and the difference in the thermal expansion coefficients between the connection substrate and the wiring substrate, can be made smaller than the difference in the thermal expansion coefficients between the through-hole electrode substrate and the wiring substrate. Therefore, stresses generated in the bonding portions and pads arranged between the through-hole electrode substrate and the connection substrate, and in the bonding portions and pads arranged between the connection substrate and the wiring substrate, can be alleviated.

[0300] Thermal expansion coefficient α in the plane direction of the resin layer Ｐ The thermal expansion coefficient α11 of the glass substrate in the surface direction may be between the thermal expansion coefficient α11 of the glass substrate in the surface direction and the thermal expansion coefficient α12 of the wiring substrate in the surface direction, but is preferably within a range of ±30% of the median value α13 of the thermal expansion coefficient α11 of the glass substrate in the surface direction and the thermal expansion coefficient α12 of the wiring substrate in the surface direction, and more preferably within a range of ±20% of the median value α13. The median value α13 is calculated by (α11 + α12) / 2.

[0301] In addition, the thermal expansion coefficient α of the resin layer in the surface direction Ｐ and the thermal expansion coefficient α in the thickness direction of the resin layer Ｔ The difference between Ｐ -α Ｔ is preferably 9 ppm / °C or less, more preferably 6 ppm / °C or less, and particularly preferably 3 ppm / °C or less. When the difference is within the above range, it can be said that the thermal expansion coefficient of the resin layer is isotropic. When the thermal expansion coefficient of the resin layer is isotropic, breakage or cracks are less likely to occur in the joints and pads arranged between the through-hole electrode substrate and the connection substrate, and in the joints and pads arranged between the connection substrate and the wiring substrate. Therefore, the connection reliability between the through-hole electrode substrate and the wiring substrate can be improved. On the other hand, the above |α Ｐ -α Ｔ may be, for example, 0 ppm / °C or more, 0.5 ppm / °C or more, or 1 ppm / °C or more. Specifically, the difference is preferably 0.5 ppm / °C or more and 9 ppm / °C or less, more preferably 0.5 ppm / °C or more and 6 ppm / °C or less, and more preferably 1 ppm / °C or more and 3 ppm / °C or less.

[0302] Thermal expansion coefficient α in the plane direction of the resin layer Ｐ is, for example, preferably 3 ppm / °C or more and 18 ppm / °C or less, and more preferably 4 ppm / °C or more and 9 ppm / °C or less. Ｔ is, for example, preferably 3 ppm / °C or more and 18 ppm / °C or less, and more preferably 4 ppm / °C or more and 9 ppm / °C or less.

[0303] The thermal expansion coefficients in the planar direction and the thickness direction of the resin layer are average linear expansion coefficients from 20°C to 180°C, and are values ​​measured by thermomechanical analysis (TMA) under the following conditions in accordance with JIS K7197:2012. The TMA device used can be a "TMA-60" manufactured by Shimadzu Corporation. <Measurement conditions> Constant load tension mode: 20 mN Measurement temperature range: 0°C to 200°C Temperature range for calculating linear expansion coefficient: 20°C to 180°C

[0304] The thermal expansion coefficient of the resin layer in the planar direction and the thickness direction can be adjusted by the type of resin that is the material of the resin layer and the amount of filler added.

[0305] (2) Material for Resin Layer The material for the resin layer is not particularly limited as long as it has insulating properties and the above-mentioned shear modulus and thermal expansion coefficient. The resin layer may contain, for example, a cured product of a curable resin composition, or may contain a resin component and a filler. In particular, the resin layer preferably contains a cured product of a curable resin composition containing a filler.

[0306] When the resin layer contains a cured product of a curable resin composition, examples of the curable resin composition include a heat-curable resin composition and an ionizing radiation-curable resin composition. Examples of the ionizing radiation-curable resin composition include an electron beam-curable resin composition and an ultraviolet light-curable resin composition. Specifically, the curable resin composition can be a curable resin composition generally used for encapsulating resins. Among these, a heat-curable resin composition is preferred.

[0307] A thermosetting resin composition is a composition containing at least a thermosetting resin. Examples of thermosetting resins include acrylic resins, urethane resins, phenolic resins, urea melamine resins, epoxy resins, unsaturated polyester resins, and silicone resins. The thermosetting resins may be used alone or in combination of two or more. A curing agent may be added to the thermosetting resin composition as needed.

[0308] Furthermore, it is preferable that the curable resin composition further contains a filler. By containing a filler, it is possible to adjust the shear modulus and thermal expansion coefficient of the resin layer. The filler may be any filler as long as it has insulating properties, and examples thereof include inorganic particles and organic particles. Examples of inorganic particles include particles made of inorganic materials such as silica, alumina, zirconia, titania, kaolinite, calcium carbonate, and barium sulfate. Examples of organic particles include particles made of resins such as acrylic resins, urethane resins, silicone resins, and polyamide resins such as nylon. One type of particle may be used alone, or two or more types may be used in combination.

[0309] The average particle size of the filler is not particularly limited. The average particle size of the filler is, for example, 0.01 μm or more and 1 μm or less, or may be 0.1 μm or more and 0.5 μm or less. The average particle size of the filler is the arithmetic average value when 20 random fillers are measured in an image of the cross section of the resin layer observed with a scanning electron microscope (SEM).

[0310] When the resin layer contains a resin component and a filler, the resin component is not particularly limited as long as it has insulating properties, and may be, for example, a curable resin or a thermoplastic resin. The filler is as described above.

[0311] When the resin layer contains a filler, the content of the filler in the resin layer is not particularly limited as long as the shear modulus and thermal expansion coefficient of the resin layer can be set within a predetermined range, and may be, for example, 10 parts by mass or more and 90 parts by mass or less, or 30 parts by mass or more and 80 parts by mass or less, per 100 parts by mass of the resin component of the resin layer.

[0312] (3) Other Points of the Resin Layer The thickness of the resin layer is, for example, 0.1 mm or more, and may be 0.4 mm or more. When the thickness of the resin layer is in the above range, the effect of stress relaxation by the resin layer is easily obtained. On the other hand, the thickness of the resin layer may be, for example, 1.0 mm or less, and may be 0.6 mm or less. If the thickness of the resin layer is too thick, it is disadvantageous in terms of cost. Specifically, the thickness of the resin layer may be, for example, 0.1 mm or more and 1.0 mm or less, and 0.4 mm or more and 0.6 mm or less.

[0313] The resin layer is usually a single layer. The resin layer can be formed by applying the above-mentioned material and, if necessary, performing a curing treatment. The resin layer has through-holes that penetrate through the thickness direction. The method for forming the through-holes will be described later.

[0314] 2. Conductive Portion The conductive portion in this embodiment is disposed in the through hole of the resin layer.

[0315] The form of the conductive portion may be, for example, a conductive portion that fills the through hole of the resin layer, a so-called filled via, or a conductive portion that is arranged only on the side wall of the through hole of the resin layer, a so-called conformal via.

[0316] The material of the conductive portion is not particularly limited as long as it is a material having conductivity, and may be appropriately selected depending on the shape of the conductive portion, the method of formation, etc. Examples of the material of the conductive portion include metals such as copper, gold, silver, platinum, rhodium, tin, aluminum, nickel, and chromium, and alloys containing these metals.

[0317] A method for forming a conductive portion includes, for example, forming a through-hole in a resin layer and then forming a conductive portion in the through-hole. Methods for forming a through-hole in a resin layer include laser processing, photolithography, and molding using a mold. Methods for forming a conductive portion in a through-hole in a resin layer include, for example, PVD methods such as vacuum deposition and sputtering, CVD, and plating. A conductive material may be filled into the through-hole in the resin layer to form a conductive portion, and at least one of a wiring substrate connection pad and a through-electrode substrate connection pad may be formed using this conductive material. Hereinafter, the wiring substrate connection pad and the through-electrode substrate connection pad may be simply referred to as "pads." In addition, in the case of a plating method, a through-hole is first formed in the resin layer, and then a seed layer is formed on the entire surface of the resin layer by sputtering or the like. A photoresist layer is then formed on the seed layer, and the photoresist layer is subsequently patterned to have openings for the pads. The openings in the photoresist layer are then electroplated to form a plating layer, thereby simultaneously forming the conductive portion and the pad. In this case, the conductive portion and the pad portion have a seed layer and a plating layer.

[0318] 16 , the connection substrate in this embodiment can have wiring substrate connection pads 81 that are arranged on the first surface 72 a of the resin layer 72 and are electrically connected to the wiring substrate, and through electrode substrate connection pads 82 that are arranged on the second surface 72 b of the resin layer 72 and are electrically connected to the through electrode substrate.

[0319] The material, planar shape, thickness and formation method of the wiring substrate connection pad portion and the through electrode substrate connection pad portion are the same as the material, planar shape, thickness and formation method of the connection substrate connection pad portion in the through electrode substrate described below.

[0320] The wiring board is electrically connected to the wiring board connection pad portion of the connection board via a third joint. Examples of materials for the third joint include solder, gold or gold alloy, conductive paste, anisotropic conductive paste, and anisotropic conductive film. The through-hole electrode board is electrically connected to the through-hole electrode board connection pad portion of the connection board via a fourth joint. The material for the fourth joint is the same as that for the third joint. In particular, the third and fourth joints are preferably solder bumps primarily made of solder. Solder bumps have a lower modulus of elasticity than copper and the like, and thus have a stress buffering effect. Furthermore, it is preferable to use a solder material using liquid metal, which has a lower modulus of elasticity, for either the third or fourth joint. This enhances the stress buffering effect.

[0321] 4. Other: The resin layer of the connection board in this embodiment is a single layer. Furthermore, although the connection board has pad portions on the first and second surfaces of the resin layer, it does not have wiring on either the first or second surface of the resin layer. On the other hand, in general, a wiring board has multiple insulating layers and multiple conductive layers alternately stacked, and the wiring board has wiring formed from patterns of the conductive layers. Therefore, the connection board in this embodiment is distinguished from a wiring board.

[0322] B5. Semiconductor Device The semiconductor device of this embodiment has the connection board of the fifth embodiment described above, a wiring board arranged on a first surface side of the connection board, a through electrode substrate arranged on a second surface side of the connection board, an element arranged on the opposite side of the through electrode substrate to the connection board, a third joint that electrically connects the conductive portion of the connection board and the wiring board, a fourth joint that electrically connects the conductive portion of the connection board and the through electrode of the through electrode substrate, and a fifth joint that electrically connects the through electrode of the through electrode substrate and the element.

[0323] 17 is a schematic cross-sectional view showing an example of a semiconductor device according to this embodiment. Since FIG. 17 has been described above, a description thereof will be omitted here.

[0324] The semiconductor device of this embodiment has the connection substrate of the fifth embodiment. Therefore, for the reasons described above, it is possible to alleviate stress generated in the fourth bonding portion 62 and pad portion (connection substrate connection pad portion 83 and through electrode substrate connection pad portion 82) disposed between the through electrode substrate 1 and the connection substrate 70A, and the third bonding portion 61 and pad portion (wiring substrate connection pad portion 81) disposed between the connection substrate 70A and the wiring substrate 20. This makes it possible to prevent cracks and breaks from occurring in these bonding portions and pad portions.

[0325] Furthermore, for example, when the joint connecting the element and the through electrode is a solder joint, and when the through electrode substrate and the element are joined via the solder joint during a reflow soldering process in the manufacturing process of the semiconductor device, the through electrode substrate and the element expand due to heat and then contract due to cooling. At this time, if the difference in thermal expansion coefficient between the through electrode substrate and the element is large, stress is generated in the fifth joint and the element connection pad, making it more likely to crack and break. Also, for example, when the semiconductor device is used in a high-temperature environment, if the difference in thermal expansion coefficient between the through electrode substrate and the element is large, stress is generated in the fifth joint and the element connection pad, making it more likely to crack and break.

[0326] In contrast, in the semiconductor device 10A of this embodiment, the through electrode substrate 1 has the glass substrate 2, and the through electrode substrate 1 can be used as a so-called glass interposer. This reduces the difference in thermal expansion coefficient between the glass substrate 2 and the element 30, and suppresses stress from occurring in the fifth joint portion 63 and the element connection pad portion 84. This prevents cracks and breaks in the fifth joint portion 63 and the element connection pad portion 84.

[0327] Therefore, in this embodiment, the connection reliability can be improved.

[0328] 1. Connection Board The connection board has been described in detail above in "A5. Connection Board," so a detailed description will be omitted here.

[0329] 2. Through-hole electrode substrate The through-hole electrode substrate is disposed on the second surface side of the connection substrate. The through-hole electrode substrate and the connection substrate are electrically connected via a fourth joint. As shown in FIG. 17 , the through-hole electrode substrate 1 has a first surface 2a and a second surface 2b facing the first surface 2a, and includes a glass substrate 2 having a first through hole 2c, and through electrodes 3 disposed in the first through holes 2c of the glass substrate 2. The through-hole electrode substrate 1 is preferably disposed on the first surface 2a side of the glass substrate 2 and includes a multilayer insulating layer 4 having a plurality of first insulating layers 4a, and a first conductive layer 5 disposed between each of the first insulating layers 4a and electrically connected to the through electrodes 3.

[0330] (1) Glass Substrate The details of the glass substrate are the same as those in the first embodiment. The thermal expansion coefficient in the plane direction of the glass substrate and the method for measuring it are the same as those in the first embodiment.

[0331] (2) Through Electrode Details of the through electrode are the same as those in the first embodiment.

[0332] (3) Insulating Layer The through-hole electrode substrate preferably has an insulating layer (first insulating layer) on the first surface side of the glass substrate. The insulating layer disposed on the first surface side of the glass substrate may be one layer or multiple layers. The through-hole electrode substrate preferably has an insulating layer (second insulating layer) on the second surface side of the glass substrate. The insulating layer disposed on the second surface side of the glass substrate may be one layer or multiple layers. In particular, it is preferable that a multi-layer insulating layer having multiple insulating layers is disposed on both the first surface side and the second surface side of the glass substrate. Details of the insulating layer and the multi-layer insulating layer are the same as those in the first embodiment.

[0333] (4) The first conductive layer and first via-through electrode substrate has a first conductive layer disposed between each first insulating layer and electrically connected to the through electrode. The first conductive layers are electrically connected via the first vias. Details of the first conductive layers and the first vias are the same as those in the first embodiment.

[0334] (5) The second conductive layer and the third via-through electrode substrate may have a second conductive layer disposed between each second insulating layer and electrically connected to the through electrode. Furthermore, each second conductive layer is electrically connected via a third via. For example, in FIG. 17 , a multilayer insulating layer 14 having multiple second insulating layers 14 a is disposed on the second surface 2 b of the glass substrate 2, and second conductive layers 15 are disposed partially between the multiple second insulating layers 14 a, and each second conductive layer 15 is electrically connected by a third via 16. The second conductive layer 15 located on the surface opposite the glass substrate 2 from the second insulating layer 14 a disposed farthest from the glass substrate includes an element connection pad portion 84. Details of the second conductive layer, the third via, and the element connection pad portion are the same as those in the first embodiment.

[0335] 17 , of the multiple first insulating layers 4a in the multilayer insulating layer 4 arranged on the first surface 2a side of the glass substrate 2, the first insulating layer 4a located closest to the glass substrate 2 is preferably a first covering insulating layer 41. The first covering insulating layer 41 is arranged on the first surface 2a side of the glass substrate 2 so as to cover the boundary α between the through electrode 3 and the glass substrate 2, and has a second through hole 41c connecting to the first through hole 2c. A second via 7 electrically connected to the through electrode 3 is arranged in the second through hole 41c of the first covering insulating layer 41. Details of the first covering insulating layer and the second through hole are the same as those in the first embodiment.

[0336] The second via in this embodiment is disposed in the second through hole of the first covering insulating layer and is electrically connected to the through electrode, the first via, and the wiring board connection pad. The second via is preferably directly connected to the through electrode. Details of the second via are the same as those in the first embodiment.

[0337] 17 , of the plurality of second insulating layers 14a arranged on the second surface 2b of the glass substrate 2, the second insulating layer 14a located closest to the glass substrate 2 is preferably a second covering insulating layer 141. The second covering insulating layer 141 is arranged on the second surface 2b of the glass substrate 2 so as to cover the boundary β between the through electrode 3 and the glass substrate 2, and has a fourth through hole 141c connecting to the first through hole 2c. A fourth via 17 electrically connected to the through electrode 3 is arranged in the fourth through hole 141c of the second covering insulating layer 141. The fourth via 17 is electrically connected to the element connecting pad 84 via the second conductive layer 15 and the third via 16.

[0338] The second covering insulating layer has the same effect as the first covering insulating layer. The second covering insulating layer and the fourth via are similar to the first covering insulating layer and the second via, respectively.

[0339] (7) Connection Board Connection Pads The connection board connection pads are disposed on the surface of the first insulating layer (multi-layer insulating layer) opposite the glass substrate, and are electrically connected to the first vias and the connection board. Details of the wiring board connection pads are the same as those in the first embodiment.

[0340] (8) Element Connection Pad Section The material, planar shape, thickness and formation method of the element connection pad section are the same as the material, planar shape, thickness and formation method of the connection board connection pad section in the through electrode substrate described above.

[0341] 17, the through hole electrode substrate 1 in this embodiment may have a solder resist layer 12 disposed on the surface of the multilayer insulating layer 4 opposite to the glass substrate 2. Details of the solder resist layer are the same as those in the first embodiment.

[0342] 3. Wiring Board As the wiring board in this embodiment, a general wiring board can be used.

[0343] The thermal expansion coefficient of the wiring substrate in the plane direction is, for example, 9 ppm / °C or more and 18 ppm / °C or less, and preferably 10 ppm / °C or more and 14 ppm / °C or less. If the thermal expansion coefficient of the wiring substrate is within the above range, the difference between the thermal expansion coefficient of the glass substrate and the thermal expansion coefficient of the wiring substrate becomes relatively large, which raises concerns about stress concentration in the fourth joint portion and the wiring substrate connection pad portion. In contrast, in this embodiment, by disposing a connection substrate between the through electrode substrate and the wiring substrate, it is possible to alleviate stress generated in the joint portion and the pad portion.

[0344] The "thermal expansion coefficient in the plane direction of a wiring board" refers to the thermal expansion coefficient in the plane direction of a substrate used in the wiring board. Examples of the substrate include a resin substrate and a ceramic substrate. In particular, from the viewpoint of cost, the substrate used in the wiring board is preferably a resin substrate. Examples of the resin substrate include a glass epoxy substrate and a glass polyimide substrate.

[0345] The thermal expansion coefficient of the wiring board in the surface direction is measured by the same method as that used to measure the thermal expansion coefficient of the resin layer in the surface direction.

[0346] 4. Element and Third Junction The details of the element and the third junction are similar to those of the element and the second junction in the first embodiment.

[0347] 5. Uses The uses of the semiconductor device in this embodiment are the same as those in the first embodiment.

[0348] VI. Sixth Embodiment A6. Connection Board The connection board in this embodiment is a connection board for connecting a glass substrate and a through electrode substrate having through electrodes penetrating the glass substrate to a wiring substrate, the connection board having a resin layer and a conductive portion penetrating the resin layer, the thermal expansion coefficient of the resin layer in the surface direction being between the thermal expansion coefficient of the glass substrate in the surface direction and the thermal expansion coefficient of the wiring substrate in the surface direction, and the thermal expansion coefficient α of the resin layer in the surface direction being Ｐ and the thermal expansion coefficient α in the thickness direction of the resin layer. Ｔ The difference between Ｐ -α Ｔ | is 9 ppm / °C or less.

[0349] FIG. 16 is a schematic cross-sectional view showing an example of a connection board according to this embodiment. As shown in FIG. 16 , the connection board 70B includes a resin layer 72 having a first surface 72a and a second surface 72b opposite the first surface 72a, and a conductive portion 73 penetrating the resin layer 72. The connection board 70B is used to connect a glass substrate and a through-hole electrode substrate having through-hole electrodes penetrating the glass substrate to a wiring board. In this embodiment, the thermal expansion coefficient of the resin layer 72 in the plane direction is between the thermal expansion coefficient of the glass substrate in the plane direction and the thermal expansion coefficient of the wiring board in the plane direction. Furthermore, the difference between the thermal expansion coefficient of the resin layer 72 in the plane direction and the thermal expansion coefficient of the resin layer 72 in the thickness direction is equal to or less than a predetermined value. The connection board 70B in FIG. 16 includes a wiring board connection pad 81 disposed on the first surface 72a of the resin layer 72 and electrically connected to the wiring board, and a through-hole electrode substrate connection pad 82 disposed on the second surface 72b of the resin layer 72 and electrically connected to the through-hole electrode substrate.

[0350] 17 is a schematic cross-sectional view showing an example of a semiconductor device having a connection substrate according to this embodiment. Since Fig. 17 has been described in the fifth embodiment, its description will be omitted here.

[0351] Conventionally, a through-hole electrode substrate and a wiring substrate are electrically connected via a joint. For example, the joint connecting the through-hole electrode substrate and the wiring substrate is a solder joint. When the through-hole electrode substrate and the wiring substrate are connected via the solder joint during a reflow soldering process in a semiconductor device manufacturing process, the through-hole electrode substrate and the wiring substrate expand due to heat and then contract due to cooling. At this time, if the difference in thermal expansion coefficient between the through-hole electrode substrate and the wiring substrate is large, stress is generated in the joint connecting the through-hole electrode substrate and the wiring substrate and in the pad connected to this joint, making cracks and disconnections more likely. Furthermore, for example, when a semiconductor device is used in a high-temperature environment, if the difference in thermal expansion coefficient between the through-hole electrode substrate and the wiring substrate is large, stress is generated in the joint connecting the through-hole electrode substrate and the wiring substrate and in the pad connected to this joint, making cracks and disconnections more likely.

[0352] On the other hand, in the present disclosure, the through electrode substrate and the wiring substrate are electrically connected via a connection substrate. The through electrode substrate and the connection substrate are electrically connected via a joint, and the connection substrate and the wiring substrate are electrically connected via a joint. In this embodiment, the thermal expansion coefficient of the connection substrate in the plane direction is between the thermal expansion coefficient of the glass substrate constituting the through electrode substrate and the thermal expansion coefficient of the wiring substrate in the plane direction. Therefore, the difference in thermal expansion coefficient between the through electrode substrate and the connection substrate, and the difference in thermal expansion coefficient between the connection substrate and the wiring substrate, can be made smaller than the difference in thermal expansion coefficient between the through electrode substrate and the wiring substrate. Therefore, by disposing a connection substrate having a thermal expansion coefficient intermediate between that of the glass substrate and that of the wiring substrate between the through electrode substrate and the wiring substrate, stress generated in the joints and pads disposed between the through electrode substrate and the connection substrate, and in the joints and pads disposed between the connection substrate and the wiring substrate, can be alleviated.

[0353] Furthermore, in this embodiment, the difference between the thermal expansion coefficient of the resin layer in the plane direction and the thermal expansion coefficient of the resin layer in the thickness direction is equal to or less than a predetermined value, and the thermal expansion coefficient of the resin layer can be said to be isotropic. When the thermal expansion coefficient of the resin layer is isotropic, fractures and cracks are less likely to occur in the joints and pads arranged between the through-hole electrode substrate and the connection substrate, and in the joints and pads arranged between the connection substrate and the wiring substrate. Therefore, the connection reliability between the through-hole electrode substrate and the wiring substrate can be improved.

[0354] Therefore, in this embodiment, it is possible to prevent cracks and breaks from occurring in the bonding portions and pad portions as described above, and to improve connection reliability.

[0355] Furthermore, in order to improve connection reliability, it is also possible to arrange a member for stress relief in the through electrode substrate. However, as mentioned above, the size of through electrode substrates is increasing, and there are concerns about a decrease in yield. In this embodiment, the connection substrate is fabricated separately from the through electrode substrate and the wiring substrate, which improves yield. Therefore, manufacturing costs can be reduced.

[0356] 1. Resin layer In this embodiment, the thermal expansion coefficient α of the resin layer in the plane directionＰ is between the thermal expansion coefficient α11 of the glass substrate in the surface direction and the thermal expansion coefficient α12 of the wiring substrate in the surface direction.

[0357] In this embodiment, the thermal expansion coefficient α of the resin layer in the plane direction is Ｐ and the thermal expansion coefficient α in the thickness direction of the resin layer Ｔ The difference between Ｐ -α Ｔ | is 9 ppm / °C or less.

[0358] The thermal expansion coefficient in the planar direction of the resin layer and the thermal expansion coefficient in the thickness direction of the resin layer are the same as those described in the fifth embodiment.

[0359] The material and thickness of the resin layer are the same as those described in the fifth embodiment.

[0360] 2. Other points of the connection board in this embodiment are the same as those described in the fifth embodiment.

[0361] B6. Semiconductor Device The semiconductor device in this embodiment has the connection board of the sixth embodiment described above, the wiring board arranged on the first surface side of the connection board, the through electrode substrate arranged on the second surface side of the connection board, an element arranged on the opposite side of the through electrode substrate to the connection board, a third joint that electrically connects the conductive portion of the connection board and the wiring board, a fourth joint that electrically connects the conductive portion of the connection board and the through electrode in the through electrode substrate, and a fifth joint that electrically connects the through electrode in the through electrode substrate and the element.

[0362] 17 is a schematic cross-sectional view showing an example of a semiconductor device including a connection substrate 70B according to this embodiment. Since FIG. 17 has been described in detail in the fifth embodiment, a description thereof will be omitted here.

[0363] In the semiconductor device of this embodiment, the connection substrate of the second embodiment described above is arranged between the through electrode substrate and the wiring substrate, thereby alleviating stresses that occur in the joints and pads arranged between the through electrode substrate and the connection substrate, and in the joints and pads arranged between the connection substrate and the wiring substrate, thereby suppressing cracks and breaks.

[0364] Furthermore, in this embodiment, as in the above-mentioned fifth embodiment, the through electrode substrate has a glass substrate, which alleviates stress generated in the joints and pads arranged between the through electrode substrate and the element, thereby suppressing cracks and breaks.

[0365] Therefore, in this embodiment, the connection reliability can be improved.

[0366] 1. Connection Board The connection board in this embodiment has been described in detail above in "A6. Connection Board," so a detailed description will be omitted here.

[0367] 2. Others The other points of the semiconductor device in this embodiment are the same as those described in the fifth embodiment.

[0368] VII. Seventh Embodiment A7. Connection Board The connection board in this embodiment is a connection board for electrically connecting a glass substrate and a through electrode substrate having through electrodes penetrating the glass substrate to a wiring substrate, and includes a base having an outer through hole, an elastic portion disposed in the outer through hole of the base and having an inner through hole, and a conductive portion disposed in the inner through hole of the elastic portion.

[0369] FIG. 18 is a schematic cross-sectional view showing an example of a connection board according to this embodiment. As shown in FIG. 18 , a connection board 70C includes a base 74 having a first surface 74a and a second surface 74b facing the first surface 74a, an outer through-hole 74c, an elastic portion 75 disposed within the outer through-hole 74c of the base 74 and having an inner through-hole 75c, and a conductive portion 76 disposed within the inner through-hole 75c of the elastic portion 75. The connection board 70C is used to connect a glass substrate and a through-electrode substrate having through-electrodes penetrating the glass substrate to a wiring board. The connection board 70C in FIG. 18 also includes a wiring board connection pad 81 disposed on the first surface 74a of the base 74 and electrically connected to the wiring board, and a through-electrode substrate connection pad 82 disposed on the second surface 74b of the base 74 and electrically connected to the through-electrode substrate.

[0370] 19 is a schematic cross-sectional view showing an example of a semiconductor device having a connection substrate according to this embodiment. The semiconductor device 10C shown in FIG. 19 includes the connection substrate 70C described above, a fourth bonding portion 62 electrically connected to a through electrode substrate connection pad portion 82 of the connection substrate 70C, a through electrode substrate 1 electrically connected to the fourth bonding portion 62, a third bonding portion 61 electrically connected to a wiring substrate connection pad portion 81 of the connection substrate 70C, and a wiring substrate 20 electrically connected to the third bonding portion 61. In FIG. 19 , the semiconductor device 10C further includes a fifth bonding portion 63 electrically connected to an element connection pad portion 84 of the through electrode substrate 1, and an element 30 electrically connected to the fifth bonding portion 63.

[0371] Conventionally, a through-hole electrode substrate and a wiring substrate are electrically connected via a joint. For example, the joint connecting the through-hole electrode substrate and the wiring substrate is a solder joint. When the through-hole electrode substrate and the wiring substrate are connected via the solder joint during a reflow soldering process in a semiconductor device manufacturing process, the through-hole electrode substrate and the wiring substrate expand due to heat and then contract due to cooling. At this time, if the difference in thermal expansion coefficient between the through-hole electrode substrate and the wiring substrate is large, stress is generated in the joint connecting the through-hole electrode substrate and the wiring substrate and in the pad connected to this joint, making cracks and disconnections more likely. Furthermore, for example, when a semiconductor device is used in a high-temperature environment, if the difference in thermal expansion coefficient between the through-hole electrode substrate and the wiring substrate is large, stress is generated in the joint connecting the through-hole electrode substrate and the wiring substrate and in the pad connected to this joint, making cracks and disconnections more likely.

[0372] On the other hand, in the present disclosure, the through electrode substrate and the wiring substrate are electrically connected via a connection substrate. The through electrode substrate and the connection substrate are electrically connected via a joint, and the connection substrate and the wiring substrate are electrically connected via a joint. In the connection substrate of this embodiment, an elastic portion is disposed around the conductive portion within the through hole of the base. Because the elastic portion has elasticity, the elastic portion can absorb stress due to the difference in thermal expansion coefficient between the through electrode substrate and the wiring substrate. Therefore, by disposing such a connection substrate between the through electrode substrate and the wiring substrate, stress generated in the joints and pads disposed between the through electrode substrate and the connection substrate, and in the joints and pads disposed between the connection substrate and the wiring substrate, can be alleviated. Therefore, in this embodiment, cracks and breaks can be suppressed in the joints and pads described above, thereby improving connection reliability.

[0373] Furthermore, in order to improve connection reliability, it is also possible to arrange a member for stress relief in the through electrode substrate. However, as mentioned above, the size of through electrode substrates is increasing, and there are concerns about a decrease in yield. In this embodiment, the connection substrate is fabricated separately from the through electrode substrate and the wiring substrate, which improves yield. Therefore, manufacturing costs can be reduced.

[0374] 1. Base The base in this embodiment has outer through-holes.

[0375] The material of the substrate is not particularly limited as long as it can provide a substrate having through holes and has insulating properties, and examples thereof include materials used for insulating substrates and insulating layers in general wiring substrates. Examples of the substrate include glass epoxy substrates and glass polyimide substrates. The resin layer in the fifth and sixth embodiments can also be used as the substrate.

[0376] In this embodiment, since the elastic portion can absorb stress, the thermal expansion coefficient of the base is not particularly limited. The thermal expansion coefficient of the base in the planar direction is preferably between the thermal expansion coefficient of the glass substrate and the thermal expansion coefficient of the wiring substrate. The thermal expansion coefficient of the base in the planar direction is, for example, 3 ppm / °C or more and 18 ppm / °C or less, and may be 6 ppm / °C or more and 12 ppm / °C or less. This is because connection reliability is further improved.

[0377] Furthermore, the difference between the thermal expansion coefficient of the substrate in the planar direction and the thermal expansion coefficient of the substrate in the thickness direction is preferably equal to or less than a predetermined value. The preferred range of this difference is the same as the preferred range of the difference between the thermal expansion coefficient of the resin layer in the planar direction and the thermal expansion coefficient of the resin layer in the thickness direction.

[0378] The thermal expansion coefficient of the substrate in the planar direction and the thermal expansion coefficient of the substrate in the thickness direction are measured by the same method as the method for measuring the thermal expansion coefficient of the resin layer in the planar direction and the thermal expansion coefficient of the resin layer in the thickness direction.

[0379] The shear modulus of the substrate is preferably within a predetermined range. The preferred range of the shear modulus of the substrate is the same as the preferred range of the shear modulus of the resin layer. The method for measuring the shear modulus of the substrate is the same as the method for measuring the shear modulus of the resin layer.

[0380] The thermal expansion coefficient and shear modulus of the substrate can be adjusted by the substrate material. For example, a glass epoxy substrate may be used, but it is preferable to use a substrate in which a filler is dispersed in an epoxy resin or a glass ceramic substrate.

[0381] The planar shape of the outer through-hole in the base is, for example, substantially circular. The cross-sectional shape of the outer through-hole may be, for example, the straight shape shown in FIG. 18 . The opening diameter d4 of the outer through-hole 74c is, for example, 10 μm or more, and may be 20 μm or more. Meanwhile, the opening diameter d4 may be, for example, 200 μm or less, and may be 160 μm or less. Furthermore, the ratio (d5 / d4) of the opening diameter d5 of the inner through-hole 75c (described later) to the opening diameter d4 of the outer through-hole 74c is preferably 0.7 or more, more preferably 0.8 or more, and particularly preferably 0.9 or more. This is because the effect of stress absorption by the elastic portion is easily obtained. Meanwhile, the ratio (d5 / d4) is preferably 1.0 or less, more preferably 0.95 or less, and particularly preferably 0.93 or less.

[0382] 2. Elastic Section The elastic section in this embodiment is disposed within the outer through-hole of the base body and has an inner through-hole.

[0383] Examples of materials for the elastic portion include elastomers, such as styrene-based elastomers, acrylic-based elastomers, olefin-based elastomers, urethane-based elastomers, silicone rubber, urethane rubber, fluororubber, nitrile rubber, polybutadiene, polyisobutylene, polystyrene butadiene, and polychloroprene.

[0384] The glass transition temperature (Tg) of the elastomer contained in the elastic portion is preferably 0°C or lower, for example. By including an elastomer with a glass transition temperature of 0°C or lower, stress due to the difference in thermal expansion coefficient between the through-hole electrode substrate and the wiring substrate can be alleviated. The glass transition temperature (Tg) is measured using a differential scanning calorimetry (DSC) device in accordance with JIS K7121:2012. Specifically, it is the midpoint glass transition temperature obtained from a DSC curve obtained when a sample taken from the elastic portion is held at -50°C for 10 minutes and then heated to 150°C at a heating rate of 20°C / min. A STA300 manufactured by Hitachi High-Tech Science Corporation can be used as the differential scanning calorimetry device.

[0385] The inner through-hole in the elastic portion has a generally circular shape in plan view, for example. The cross-sectional shape of the inner through-hole may be, for example, a straight shape as shown in Fig. 18. The opening diameter d5 of the inner through-hole 75c is, for example, 10 µm or more, preferably 20 µm or more, from the viewpoint of ensuring electrical conductivity. On the other hand, the opening diameter d5 may be, for example, 200 µm or less, or 160 µm or less.

[0386] 3. Conductive Part The conductive part in this embodiment is disposed inside the inner through-hole of the elastic part. The shape, material and method of forming the conductive part are the same as those of the conductive part in the fifth embodiment.

[0387] As described above, the conductive portion may be in the form of a filled via or a conformal via. Among these, a conformal via or a via formed by filling an outer through-hole of the base with the material of the elastic portion, then forming an inner through-hole with a laser, and filling the inner through-hole with the material of the conductive portion is preferred because the via diameter becomes larger.

[0388] B7. Semiconductor Device The semiconductor device of this embodiment has the connection board of the seventh embodiment described above, the wiring board arranged on the first surface side of the connection board, the through electrode substrate arranged on the second surface side of the connection board, an element arranged on the opposite side of the through electrode substrate to the connection board, a third joint that electrically connects the conductive portion of the connection board and the wiring board, a fourth joint that electrically connects the conductive portion of the connection board and the through electrode in the through electrode substrate, and a fifth joint that electrically connects the through electrode in the through electrode substrate and the element.

[0389] 19 is a schematic cross-sectional view showing an example of a semiconductor device according to this embodiment. Since FIG. 19 has been described above, a description thereof will be omitted here.

[0390] In the semiconductor device of this embodiment, the connection substrate of the seventh embodiment described above is arranged between the through electrode substrate and the wiring substrate, thereby alleviating stresses that occur in the joints and pads arranged between the through electrode substrate and the connection substrate, and in the joints and pads arranged between the connection substrate and the wiring substrate, thereby suppressing cracks and breaks.

[0391] Furthermore, in this embodiment, as in the above-mentioned fifth embodiment, the through electrode substrate has a glass substrate, which alleviates stress generated in the joints and pads arranged between the through electrode substrate and the element, thereby suppressing cracks and breaks.

[0392] Therefore, in this embodiment, the connection reliability can be improved.

[0393] 1. Connection Board The connection board has been described in detail above in "A7. Connection Board," so a detailed description will be omitted here.

[0394] 2. Others The other points of the semiconductor device in this embodiment are the same as those described in the fifth embodiment.

[0395] VIII. Eighth Embodiment A8. Connection Board The connection board in this embodiment is a connection board for electrically connecting a glass substrate and a through electrode substrate having through electrodes penetrating the glass substrate to a wiring board, and includes: a support layer; a first elastic insulating layer that is disposed on a first surface side of the support layer and has an uneven shape including a plurality of convex portions and a plurality of concave portions on a surface opposite to the support layer; a conductive portion that penetrates the support layer and the first elastic insulating layer; and a first bellows wiring layer that is disposed on the surface of the first elastic insulating layer that has the uneven shape, has a bellows-shaped portion with a plurality of peaks and a plurality of valleys, and is electrically connected to the conductive portion.

[0396] 20( a) and 20(b) are schematic cross-sectional views showing an example of a connection board according to this embodiment. A connection board 70D shown in Fig. 20(a) includes a support layer 77, a first elastic insulating layer 8A disposed on a first surface 77a of the support layer 77 and having an uneven shape including a plurality of protrusions and a plurality of recesses on the surface opposite the support layer 77, a conductive portion 79 penetrating the support layer 77 and the first elastic insulating layer 8A, a first conductive portion pad 85A disposed on the surface of the first elastic insulating layer 8A opposite the support layer 77 and electrically connected to the conductive portion 79, and a first connection pad P1 disposed on the surface of the first elastic insulating layer 8A opposite the support layer 77. The connection board 70D further includes a first bellows wiring layer 87A that is disposed on the uneven surface of the first elastic insulating layer 8A, has a bellows-shaped portion 86 with multiple peaks 86a and multiple valleys 86b, and electrically connects the first conductive portion pads 85A and the first connection pads P1. The connection board 70D further includes a second connection pad P2 on the surface of the support layer 77 opposite to the first elastic insulating layer 8A.

[0397] 20(b) includes a support layer 77, a first elastic insulating layer 8A disposed on a first surface 7a of the support layer 77 and having an uneven shape including multiple protrusions and multiple recesses on the surface opposite the support layer 77, and a second elastic insulating layer 8B disposed on a second surface 7b of the support layer 77 and having an uneven shape including multiple protrusions and multiple recesses on the surface opposite the support layer 77. The connection board 70D further includes a conductive portion 79 that penetrates all of the support layer 77, the first elastic insulating layer 8A, and the second elastic insulating layer 8B, a first conductive portion pad 85A disposed on the surface of the first elastic insulating layer 8A opposite the support layer 77 and electrically connected to the conductive portion 79, and a second conductive portion pad 85B disposed on the surface of the second elastic insulating layer 8B opposite the support layer 77 and electrically connected to the conductive portion 79. The connection board 70D further includes a first connection pad P1 arranged on the side of the first elastic insulating layer 8A opposite the support layer 77, a second connection pad P2 arranged on the side of the second elastic insulating layer 8B opposite the support layer 77, a first bellows wiring layer 87A arranged on the uneven surface of the first elastic insulating layer 8A and having a bellows-shaped portion 86 with multiple peaks 86a and multiple valleys 86b, electrically connecting the first conductive portion pad 85A and the first connection pad P1, and a second bellows wiring layer 87B arranged on the uneven surface of the second elastic insulating layer 8B and having a bellows-shaped portion 86 with multiple peaks 86a and multiple valleys 86b, electrically connecting the second conductive portion pad 85B and the second connection pad P2. The connection board 70D is used to electrically connect a through electrode substrate to a wiring board.

[0398] In this embodiment, the first connection pad may be a wiring substrate connection pad. In this case, the second connection pad becomes a through electrode substrate connection pad. On the other hand, the first connection pad may be a through electrode substrate connection pad. In this case, the second connection pad becomes a wiring substrate connection pad.

[0399] FIG. 22 is a schematic cross-sectional view showing an example of a semiconductor device 10D including a connection substrate 70D shown in FIG. 20(b). The semiconductor device 10D shown in FIG. 22 includes the above-described connection substrate 70D, a fourth joint portion 62 electrically connected to the through electrode substrate connection pad portion 82 of the connection substrate 70D, a through electrode substrate 1 electrically connected to the fourth joint portion 62, a third joint portion 61 electrically connected to the wiring substrate connection pad portion 81 of the connection substrate 70D, and a wiring substrate 20 electrically connected to the third joint portion 61. In FIG. 22, the semiconductor device 10D further includes a fifth joint portion 63 electrically connected to the element connection pad portion 84 of the through electrode substrate 1, and an element 30 electrically connected to the fifth joint portion 63.

[0400] Conventionally, a through electrode substrate and a wiring substrate are electrically connected via a joint portion. For example, the joint portion connecting the through electrode substrate and the wiring substrate is a solder joint portion. When connecting the through electrode substrate and the wiring substrate via the solder joint portion in a reflow soldering process in the manufacturing process of the semiconductor device, the through electrode substrate and the wiring substrate expand due to heat and then contract due to cooling. At this time, if the difference in the thermal expansion coefficients of the through electrode substrate and the wiring substrate is large, stress is generated in the joint portion connecting the through electrode substrate and the wiring substrate and the pad portion connected to this joint portion, and cracks and disconnection are likely to occur. Also, for example, when the semiconductor device is used in a high-temperature environment, if the difference in the thermal expansion coefficients of the through electrode substrate and the wiring substrate is large, stress is generated in the joint portion connecting the through electrode substrate and the wiring substrate and the pad portion connected to this joint portion, and cracks and disconnection are likely to occur.

[0401] On the other hand, in the present disclosure, the through electrode substrate and the wiring substrate are electrically connected via a connection substrate. The through electrode substrate and the connection substrate are electrically connected via a joint portion, and the connection substrate and the wiring substrate are electrically connected via a joint portion.

[0402] In the connection board of this embodiment, the elastic insulating layer has elasticity, and the surface of the elastic insulating layer opposite the support layer has an uneven shape, so that the surface of the elastic insulating layer opposite the support layer is stretchable. Furthermore, as the surface of the elastic insulating layer opposite the support layer stretches and contracts, the conductive portion deforms obliquely. In this way, the surface of the elastic insulating layer opposite the support layer stretches and contracts, and the conductive portion deforms obliquely, thereby alleviating stress caused by the difference in thermal expansion coefficients between the through-hole electrode substrate and the wiring substrate.

[0403] Furthermore, in the connection board of this embodiment, since the elastic insulating layer has an uneven surface, the bellows wiring layer disposed on the surface of the elastic insulating layer has an bellows-shaped portion that conforms to the uneven surface of the elastic insulating layer. Furthermore, since the bellows-shaped portion is provided, the bellows wiring layer has flexibility. In this way, the flexibility of the bellows wiring layer can alleviate stress caused by the difference in thermal expansion coefficient between the through electrode substrate and the wiring substrate.

[0404] Therefore, in this embodiment, by disposing the connection substrate as described above between the through electrode substrate and the wiring substrate, it is possible to alleviate stress occurring in the joints and pads disposed between the through electrode substrate and the connection substrate, and in the joints and pads disposed between the connection substrate and the wiring substrate. Therefore, in this embodiment, it is possible to suppress the occurrence of cracks and breaks in the joints and pads described above, thereby improving connection reliability.

[0405] Furthermore, in order to improve connection reliability, it is also possible to arrange a member for stress relief in the through electrode substrate. However, as mentioned above, the size of through electrode substrates is increasing, and there are concerns about a decrease in yield. In this embodiment, the connection substrate is fabricated separately from the through electrode substrate and the wiring substrate, which improves yield. Therefore, manufacturing costs can be reduced.

[0406] 1. Elastic Insulation Layer The elastic insulation layer in the present disclosure may be disposed on one side of the support layer 77, as shown in Fig. 20(a), or may be disposed on both sides of the support layer 77, as shown in Fig. 20(b).

[0407] (1) The uneven elastic insulating layer has an uneven shape including a plurality of projections and a plurality of recesses on the surface opposite to the support layer.

[0408] In the concave-convex shape, the difference in height between adjacent convex and concave portions is preferably smaller than the thickness of the elastic insulating layer. The difference in height is, for example, 50 μm or less, and may be 15 μm or less, or 10 μm or less. If the difference in height is too large, the bellows wiring layer disposed on the surface of the elastic insulating layer opposite the support layer may come into contact with the wiring board or the through-hole electrode substrate. On the other hand, the difference in height is, for example, 1 μm or more, or may be 3 μm or more, or may be 5 μm or more. If the difference in height is too small, the surface of the elastic insulating layer opposite the support layer may be difficult to expand and contract. Specifically, the difference in height is 1 μm or more and 50 μm or less, or may be 3 μm or more and 15 μm or less, or may be 5 μm or more and 10 μm or less. The height difference between adjacent convex portions 8a and concave portions 8b is indicated by the symbol H1, as shown in Figure 23(a), for example, and is the distance between adjacent convex portions 8a and concave portions 8b in the normal direction of the first surface of the support layer.

[0409] The height difference between adjacent convex and concave portions is measured based on an image of the cross section of the connection board taken with a scanning electron microscope (SEM). The height difference between adjacent convex and concave portions is the arithmetic mean value of the height differences at any 10 points.

[0410] In the concave-convex shape, the spacing between adjacent convex portions is, for example, 2 μm or more, or may be 5 μm or more, or 6 μm or more. On the other hand, the spacing between adjacent convex portions is, for example, 20 μm or less, or may be 10 μm or less, or may be 9 μm or less. The spacing is preferably larger within the above range. The larger spacing can reduce the stress amplitude in the bellows wiring layer disposed on the surface of the elastic insulating layer opposite the support layer. Therefore, when the bellows wiring layer is subjected to repeated thermal stress, disconnection is suppressed and connection reliability is improved. Specifically, the spacing is 2 μm or more and 20 μm or less, or may be 5 μm or more and 10 μm or less, or may be 6 μm or more and 9 μm or less. The spacing between adjacent convex portions is indicated by the symbol P11, as shown in FIG. 23( a), for example.

[0411] The distance between adjacent protrusions is measured based on an image of the cross section of the connection board taken with a scanning electron microscope (SEM), and is taken as the arithmetic mean value of the distances between adjacent protrusions at 10 arbitrary locations.

[0412] In the uneven shape, the convex portions and concave portions may be arranged regularly or irregularly.

[0413] The cross-sectional shape of the convex portion is preferably such that the top of the convex portion is rounded, e.g., semicircular or semi-elliptical. The cross-sectional shape of the concave portion is preferably such that the bottom of the concave portion is rounded, e.g., semicircular or semi-elliptical. Such a shape can prevent breakage of the bellows wiring layer disposed on the surface of the elastic insulating layer facing the conductive portion pad portion and the wiring board connection pad portion.

[0414] On the surface of the elastic insulating layer opposite the support layer, the uneven shape may be at least arranged in the region where the bellows wiring layer is to be disposed. For example, on the surface of the elastic insulating layer opposite the support layer, the uneven shape may be arranged over the entire surface or partially. For example, in FIGS. 20( a) and 20(b), the uneven shape is arranged in the region where the bellows wiring layer is to be disposed. For example, in FIG. 24(a), the uneven shape including the convex portion 8a and the concave portion 8b is arranged not only in the region where the bellows wiring layer is to be disposed but also in the region between the first connection pad P1 corresponding to the first conductive portion pad 85A electrically connected to one of the adjacent conductive portions 79 and the first conductive portion pad 85A electrically connected to the other conductive portion 79. Also, in FIG. 24(a), the uneven shape is arranged in the region other than the first conductive portion pad 85A and the first connection pad P1. 25( a), the uneven shape is arranged in the areas other than the first conductive portion pads 85A and the first connection pads P1, and further in the areas other than the second conductive portion pads 85B and the second connection pads P2. Furthermore, when the uneven shape is arranged over the entire surface of the elastic insulating layer opposite the support layer, the bellows wiring layer may also serve as the conductive portion pads and the connection pads, as described below. In this case, the uneven shape is also arranged in the areas of the conductive portion pads and the connection pads on the surface of the elastic insulating layer opposite the support layer.

[0415] (2) Physical Properties of the Elastic Insulating Layer The physical properties of the elastic insulating layer are the same as those described in the second embodiment.

[0416] (3) Materials of the Elastic Insulating Layer The physical properties of the elastic insulating layer are the same as those described in the second embodiment.

[0417] (4) Shape of the Elastic Insulating Layer The thickness of the elastic insulating layer is, for example, 5 μm or more, or may be 15 μm or more, or 50 μm or more. If the thickness of the elastic insulating layer is within the above range, the surface of the elastic insulating layer opposite the support layer is likely to stretch. On the other hand, the thickness of the elastic insulating layer is, for example, 200 μm or less, or may be 100 μm or less, or may be 60 μm or less. If the thickness of the elastic insulating layer is too thick, the thickness of the connection board may become thick. Specifically, the thickness of the elastic insulating layer is 5 μm or more and 200 μm or less, or may be 15 μm or more and 100 μm or less, or may be 50 μm or more and 60 μm or less.

[0418] (5) Method for forming the elastic insulating layer The elastic insulating layer can be formed by applying the above-mentioned material. In addition, as a method for forming the concave and convex shape, for example, shaping using a mold can be mentioned.

[0419] 2. Support Layer The support layer in this embodiment is a layer that supports the elastic insulating layer.

[0420] The material for the support layer is not particularly limited as long as it can provide a support layer capable of supporting the elastic insulating layer and has insulating properties, and examples thereof include materials used for insulating substrates and insulating layers in general wiring boards.

[0421] The modulus of elasticity of the support layer, as measured by nanoindentation, is preferably greater than the modulus of elasticity of the elastic insulating layer, thereby increasing the strength of the connection board.

[0422] The thickness of the support layer is, for example, 100 μm to 600 μm, and may be 200 μm to 400 μm. If the support layer is too thin, it may be difficult to support the elastic insulating layer. If the support layer is too thick, the thickness of the connection board may become too thick.

[0423] 3. Conductive Part The conductive part in the present disclosure penetrates the elastic insulating layer and the support layer and is electrically connected to the through-electrode. When an elastic insulating layer (first elastic insulating layer) is disposed on the first surface of the support layer, the conductive part penetrates the support layer and the first elastic insulating layer. When the first elastic insulating layer is disposed on the first surface of the support layer and the second elastic insulating layer is disposed on the second surface of the support layer, the conductive part penetrates all of the first elastic insulating layer, the support layer, and the second elastic insulating layer.

[0424] The shape, material and method of forming the conductive portion are the same as those of the conductive portion in the fifth embodiment.

[0425] 4. Bellows Wiring Layer In this embodiment, the bellows wiring layer is disposed on the surface of the elastic insulating layer opposite the support layer. The bellows wiring layer has a bellows-shaped portion with multiple peaks and valleys, and electrically connects, for example, conductive portion pads and connection pads. In FIG. 20( a), a first bellows wiring layer 87A electrically connects a first conductive portion pad 85A and a first connection pad P1. In FIG. 20( b), the first bellows wiring layer 87A electrically connects a first conductive portion pad 85A and a first connection pad P1, and a second bellows wiring layer 87B electrically connects a second conductive portion pad 85B and a second connection pad P2.

[0426] (1) Bellows-Shaped Portion The bellows-shaped wiring layer has a bellows-shaped portion having a plurality of peaks and a plurality of valleys.

[0427] In the bellows-shaped portion, the height difference between adjacent peaks and valleys is preferably smaller than the thickness of the third joint that electrically connects the connection substrate and the wiring substrate in the semiconductor device having the connection substrate of this embodiment. Furthermore, in the bellows-shaped portion, the height difference between adjacent peaks and valleys is preferably smaller than the thickness of the fourth joint that electrically connects the connection substrate and the through electrode substrate. The height difference is, for example, 50 μm or less, or may be 15 μm or less, or 10 μm or less. If the height difference is too large, the bellows wiring layer may come into contact with the through electrode substrate or the wiring substrate. On the other hand, the height difference is, for example, 1 μm or more, or may be 3 μm or more, or may be 5 μm or more. If the height difference is too small, the bellows wiring layer may be difficult to expand and contract. The height difference is, for example, 1 μm or more to 50 μm or less, or may be 3 μm or more to 15 μm or less, or may be 5 μm or more to 10 μm or less. The height difference between adjacent peaks and valleys is indicated by the symbol H2, as shown in FIG. 23(b), and is the distance between adjacent peaks and valleys in the normal direction of the first surface of the support layer.

[0428] The height difference between adjacent peaks and valleys is measured based on an image of the cross section of the through hole electrode substrate taken with a scanning electron microscope (SEM). The height difference between adjacent peaks and valleys is the arithmetic mean value of the height differences at any 10 locations.

[0429] In the bellows-shaped portion, the spacing between adjacent peaks is, for example, 2 μm or more, or may be 5 μm or more, or 6 μm or more. On the other hand, the spacing between adjacent peaks is, for example, 20 μm or less, or may be 10 μm or less, or may be 9 μm or less. The spacing is preferably large within the above range. A large spacing can reduce the stress amplitude in the bellows wiring layer. Therefore, when the bellows wiring layer is repeatedly subjected to thermal stress, disconnection is suppressed and connection reliability is improved. Specifically, the spacing is 2 μm or more and 20 μm or less, or may be 5 μm or more and 10 μm or less, or may be 6 μm or more and 9 μm or less. The spacing between adjacent peaks is indicated by symbol P12, as shown in FIG. 23(b), for example.

[0430] The distance between adjacent peaks is measured based on an image of the cross section of the through hole electrode substrate taken with a scanning electron microscope (SEM). The distance between adjacent peaks is the arithmetic mean value of the distances at 10 arbitrary points.

[0431] In the bellows-shaped portion, the peaks and valleys may be arranged regularly or irregularly.

[0432] (2) Form of the bellows wiring layer The bellows wiring layer is arranged, for example, so as to electrically connect the conductive pads and the connection pads.

[0433] The planar shape of the bellows wiring layer may be any shape as long as it is arranged to electrically connect the conductive pads and the connection pads. Examples of such shapes include straight lines as shown in FIGS. 21( a ) and 21( b ), curves as shown in FIG. 27 , and wavy lines, zigzag lines, and right-angled lines (not shown). When the planar shape of the bellows wiring layer is other than straight, the length of the bellows wiring layer increases. This reduces the stress amplitude. Therefore, when the bellows wiring layer is repeatedly subjected to thermal stress, breakage is suppressed, improving connection reliability.

[0434] The length of the bellows wiring layer is appropriately set depending on the size of the through-hole electrode substrate, but is preferably 50 μm or more, and may be 100 μm or more, or 200 μm or more. If the length of the bellows wiring layer is too short, the bellows wiring layer may be less flexible and more prone to breakage. If the length of the bellows wiring layer is within the above range, the stress amplitude can be reduced. Therefore, when the bellows wiring layer is repeatedly subjected to thermal stress, breakage is suppressed and connection reliability can be maintained. On the other hand, the length of the bellows wiring layer is, for example, 1000 μm or less, or may be 500 μm or less, or may be 300 μm or less. If the length of the bellows wiring layer is too long, the electrical characteristics may be degraded. Specifically, the length of the bellows wiring layer is 50 μm or more and 1000 μm or less, or may be 100 μm or more and 500 μm or less, or may be 200 μm or more and 300 μm or less. The length of the bellows wiring layer refers to the length of the bellows wiring layer in a planar view.

[0435] The thickness of the bellows wiring layer is not particularly limited. For example, when the material of the bellows wiring layer is not elastic, as described below, the thickness of the bellows wiring layer is, for example, 1 nm or more, or may be 100 nm or more, or 1000 nm or more. In this case, the thickness of the bellows wiring layer is, for example, 100 μm or less, or may be 10 μm or less, or may be 3 μm or less. That is, in this case, the thickness of the bellows wiring layer is, for example, 1 nm or more and 100 μm or less, or may be 100 nm or more and 10 μm or less, or may be 1000 nm or more and 3 μm or less. On the other hand, when the material of the bellows wiring layer is elastic, as described below, the thickness of the bellows wiring layer is, for example, 5 μm or more, or may be 10 μm or more, or may be 20 μm or more. In this case, the thickness of the bellows wiring layer is, for example, 60 μm or less, or may be 50 μm or less, or may be 40 μm or less. That is, in this case, the thickness of the bellows wiring layer is, for example, 5 μm or more and 60 μm or less, or may be 10 μm or more and 50 μm or less, or may be 20 μm or more and 40 μm or less.

[0436] The width of the bellows wiring layer is, for example, not less than 10 μm and not more than 100 μm.

[0437] As described above, when a concave-convex shape is arranged over the entire surface of the elastic insulating layer opposite the support layer, the bellows wiring layer may also serve as the conductive portion pads and the connection pads. For example, in Figure 24(b), a concave-convex shape is arranged over the entire surface of the first elastic insulating layer 8A opposite the support layer 77, and the first bellows wiring layer 87A also serves as the first conductive portion pads 85A and the first connection pads P1. In this case, a concave-convex shape is also arranged in the conductive portion pads and connection pads on the surface of the elastic insulating layer opposite the support layer.

[0438] Furthermore, as shown in Figures 25(a) and 25(b), when a second elastic insulating layer 8B is also arranged on the second surface 7b of the support layer 77 and an uneven shape is arranged over the entire surface of the second elastic insulating layer 8B on the side opposite the support layer 77, as shown in Figure 25(a), the second bellows wiring layer 87B may electrically connect the second conductive part pad portion 85B and the second connection pad portion P2, or as shown in Figure 25(b), the second bellows wiring layer 87B may also serve as the second conductive part pad portion 85B and the second connection pad portion P2.

[0439] (3) Physical Properties of the Corrugated Wiring Layer The elastic modulus of the corrugated wiring layer measured by nanoindentation is, for example, 100 MPa or more, and may be 200 MPa or more. On the other hand, the elastic modulus is, for example, 300 GPa or less, may be 200 GPa or less, or may be 100 GPa or less. That is, the elastic modulus may be 100 MPa or more and 300 GPa or less, 100 MPa or more and 200 GPa or less, 200 MPa or more and 200 GPa or less, or may be 200 MPa or more and 100 GPa or less.

[0440] (4) Material of the Corrugated Wiring Layer The material of the corrugated wiring layer may or may not be stretchable. Examples of non-stretchable materials include metals such as gold, silver, copper, aluminum, platinum, and chromium, and alloys containing these metals. On the other hand, examples of stretchable materials include conductive compositions containing conductive particles and an elastomer. In this case, the corrugated wiring layer includes conductive particles and an elastomer. Examples of conductive particles include particles of gold, silver, copper, nickel, palladium, platinum, and carbon. Examples of elastomers include styrene-based elastomers, acrylic-based elastomers, olefin-based elastomers, urethane-based elastomers, silicone rubber, urethane rubber, fluororubber, nitrile rubber, polybutadiene, and polychloroprene.

[0441] (5) Method for Forming the Bellows Wiring Layer The method for forming the Bellows wiring layer is not particularly limited. For example, when the material of the Bellows wiring layer is not stretchable, a conductive film may be formed by a method such as vapor deposition, sputtering, plating, metal foil transfer, or pressure bonding, and then the conductive film may be patterned by photolithography. On the other hand, when the material of the Bellows wiring layer is stretchable, a conductive composition containing conductive particles and an elastomer may be printed in a pattern by a general printing method.

[0442] 3. First Polymer Layer: The connection board in this embodiment preferably has a first polymer layer between the elastic insulating layer and the bellows wiring layer. For example, in FIG. 28, a first polymer layer 88 is disposed between the first elastic insulating layer 8A and the first bellows wiring layer 87A. The first polymer layer can reduce the stress and stress amplitude applied to the bellows wiring layer.

[0443] The elastic modulus of the first polymer layer is preferably greater than that of the elastic insulating layer. If the elastic modulus of the first polymer layer is smaller than that of the elastic insulating layer and is therefore too soft, the stress applied to the bellows wiring layer may become uneven. This may result in stress concentration and lead to breakage of the bellows wiring layer.

[0444] The elastic modulus of the first polymer layer, as measured by nanoindentation, is, for example, 20 GPa or less. If the elastic modulus is too large, the first polymer layer may be torn and the bellows wiring layer may be broken. On the other hand, as described above, the elastic modulus of the first polymer layer is preferably greater than the elastic modulus of the elastic insulating layer, and the lower limit of the first polymer layer is not particularly limited.

[0445] The material of the first polymer layer is preferably polyimide or parylene.

[0446] The first polymer layer only needs to be disposed in the area where the bellows wiring layer is disposed in a plan view. As shown in Fig. 28, it is particularly preferable that the first polymer layer 88 is not disposed in any area other than the area where the bellows wiring layer 87A is disposed. The first polymer layer may restrict expansion and contraction of the surface of the elastic insulating layer opposite the support layer.

[0447] The first polymer layer is arranged to have openings above the conductive pads and the connection pads in a plan view so that the bellows wiring layer is electrically connected to the conductive pads and the connection pads.

[0448] The first polymer layer also has a bellows-shaped portion in a region overlapping with the bellows wiring layer in a plan view.

[0449] The thickness of the first polymer layer is, for example, not less than 1 nm and not more than 100 μm.

[0450] 4. Second Polymer Layer: The connection board in this embodiment preferably has a second polymer layer on the side of the bellows wiring layer opposite the elastic insulating layer. For example, in FIG. 28, a second polymer layer 89 is disposed on the side of the first bellows wiring layer 87A opposite the first elastic insulating layer 8A. The second polymer layer reduces the stress and stress amplitude applied to the bellows wiring layer.

[0451] It is preferable that at least one of the first polymer layer and the second polymer layer is disposed, more preferable that at least the first polymer layer is disposed, and even more preferable that both the first polymer layer and the second polymer layer are disposed. For example, in Figure 28, both the first polymer layer 88 and the second polymer layer 89 are disposed.

[0452] The modulus of elasticity, material and thickness of the second polymer layer are the same as those of the first polymer layer.

[0453] The second polymer layer 89 may be disposed at least in the area where the bellows wiring layer is disposed in a plan view. As shown in FIG. 28, the second polymer layer 89 is preferably not disposed in any area other than the area where the first bellows wiring layer 87A, the first conductive portion pad 85A, and the first connection pad P1 are disposed. The second polymer layer may restrict expansion and contraction of the surface of the elastic insulating layer facing the conductive portion pad and the connection pad.

[0454] As illustrated in FIG. 28, the second polymer layer 89 is preferably disposed so as to overlap the first conductive portion pad portion 85A and the first connection pad portion P1 in plan view.

[0455] The second polymer layer also has a bellows-shaped portion in a region overlapping with the bellows wiring layer in a plan view.

[0456] 5. Conductive Portion Pad Portion In this embodiment, the conductive portion pad portion is disposed on the surface of the elastic insulating layer opposite the support layer, and is electrically connected to the conductive portion.

[0457] The material, thickness, planar shape and forming method of the conductive portion pad are the same as those of the connection board connecting pad in the through electrode substrate.

[0458] 6. Connection Pads In this embodiment, the connection pads are through-hole electrode substrate connection pads or wiring substrate connection pads. The connection substrate has wiring substrate connection pads for connecting to the wiring substrate on its surface facing the wiring substrate. The connection substrate also has through-hole electrode substrate connection pads for connecting to the through-hole electrode substrate on its surface facing the through-hole electrode substrate. Note that, as shown in FIG. 20( a), when the first elastic insulating layer and the first bellows wiring layer are provided only on the first surface of the support layer 77, the connection pads arranged on the second surface of the support layer 77 also serve as the conductive portion pads described above.

[0459] The material, shape in plan view, thickness and forming method of the connection pad portion are the same as the material, shape in plan view, thickness and forming method of the connection board connection pad portion in the through electrode substrate.

[0460] The conductive pads and the connection pads are electrically connected by the bellows wiring layer, so that the conductive pads and the connection pads are disposed close to each other.

[0461] In this case, the distance from the conductive pad to the connection pad is appropriately set depending on the size of the connection board, but may be, for example, 50 μm or more, or 200 μm or more. If the distance is too short, the length of the bellows wiring layer tends to be short, making the bellows wiring layer less flexible and more susceptible to breakage. If the distance is within the above range, the length of the bellows wiring layer can be ensured and the stress amplitude can be reduced. Therefore, when the bellows wiring layer is repeatedly subjected to thermal stress, breakage is suppressed and connection reliability can be maintained. On the other hand, the distance is, for example, 1000 μm or less, or may be 500 μm or less, or may be 300 μm or less. If the distance is too long, the length of the bellows wiring layer tends to be long, which may result in deterioration of electrical characteristics. Specifically, the distance is 50 μm or more to 1000 μm or less, or may be 100 μm or more to 500 μm or less, or may be 200 μm or more to 300 μm or less. The distance from the conductive pad to the connection pad refers to the distance from the center of the conductive pad to the center of the connection pad.

[0462] As described above, when the elastic insulating layer has an uneven surface on the entire surface opposite the support layer, and when the bellows wiring layer also serves as a conductive pad and a connection pad, as described below, it is difficult to define the conductive pad and the connection pad. In such a case, in a semiconductor device having a connection substrate, it is sufficient that the distance from the conductive portion penetrating the connection substrate to the joint (third joint or fourth joint) is within the above range. The distance from the conductive portion to the joint refers to the distance from the center of the conductive portion to the center of the joint.

[0463] The first conductive portion pads 85A and the first connection pads P1 are preferably arranged radially in a plan view, as shown in FIG. 21( a), for example. Similarly, the second conductive portion pads 85B and the second connection pads P2 are preferably arranged radially in a plan view, as shown in FIG. 21( b), for example. This facilitates alleviation of stress due to the difference in thermal expansion coefficients between the through-hole electrode substrate and the wiring substrate. In this case, as shown in FIGS. 21( a) and 21(b), the conductive portion pads 85A, 85B and the connection pads P1, P2 may be arranged radially so that the conductive portion pads 85A, 85B are on the inside and the connection pads P1, P2 are on the outside. Alternatively, although not shown, the conductive portion pads and the connection pads may be arranged radially so that the conductive portion pads are on the outside and the connection pads are on the inside.

[0464] Furthermore, it is preferable that the connection pads are regularly arranged in a plan view, which makes the thermal history of the third and fourth bonding portions, which electrically connect the through-hole electrode substrate and the wiring substrate, uniform during the manufacturing process of the semiconductor device, thereby improving yield.

[0465] 20(b) and 26, the first connection pad portion P1 and the second connection pad portion P2 are preferably arranged in overlapping positions in a plan view, because overlapping positions of the first connection pad portion P1 and the second connection pad portion P2 can suppress distortion occurring in the connection substrate 70D.

[0466] B8. Semiconductor Device The semiconductor device of this embodiment has the connection board of the above-described eighth embodiment, the wiring board arranged on the first surface side of the connection board, the through electrode substrate arranged on the second surface side of the connection board, an element arranged on the opposite side of the through electrode substrate to the connection board, a third joint that electrically connects the conductive portion of the connection board and the wiring board, a fourth joint that electrically connects the conductive portion of the connection board and the through electrode of the through electrode substrate, and a fifth joint that electrically connects the through electrode of the through electrode substrate and the element.

[0467] 22 is a schematic cross-sectional view showing an example of a semiconductor device according to this embodiment. Since FIG. 22 has been described above, a description thereof will be omitted here.

[0468] In the semiconductor device of this embodiment, the connection substrate of the above-mentioned eighth embodiment is arranged between the through electrode substrate and the wiring substrate, thereby alleviating stress generated in the joints and pads arranged between the through electrode substrate and the connection substrate, and in the joints and pads arranged between the connection substrate and the wiring substrate, thereby suppressing cracks and breaks.

[0469] Furthermore, in this embodiment, as in the above-mentioned fifth embodiment, the through electrode substrate has a glass substrate, which alleviates stress generated in the joints and pads arranged between the through electrode substrate and the element, thereby suppressing cracks and breaks.

[0470] Therefore, in this embodiment, the connection reliability can be improved.

[0471] 1. Connection Board The connection board has been described in detail above in "A8. Connection Board," so a detailed description will be omitted here.

[0472] 2. Others The other points of the semiconductor device in this embodiment are the same as those described in the fifth embodiment.

[0473] IX. Ninth Embodiment B9. Semiconductor Device A semiconductor device in this embodiment includes a through electrode substrate having a glass substrate and through electrodes penetrating the glass substrate, a wiring substrate, a connection substrate disposed between the through electrode substrate and the wiring substrate and having a resin substrate and a conductive portion penetrating the resin substrate, an element disposed on the opposite side of the through electrode substrate from the connection substrate, a third joint portion electrically connecting the conductive portion of the connection substrate to the wiring substrate, a fourth joint portion electrically connecting the conductive portion of the connection substrate to the through electrode of the through electrode substrate, and a fifth joint portion electrically connecting the through electrode of the through electrode substrate to the element, wherein the thermal expansion coefficient of the resin substrate in the surface direction is between the thermal expansion coefficient of the glass substrate in the surface direction and the thermal expansion coefficient of the wiring substrate in the surface direction.

[0474] 29 is a schematic cross-sectional view showing an example of a semiconductor device according to this embodiment. The semiconductor device 10E shown in FIG. 29 includes a through hole electrode substrate 1, a wiring substrate 20, a connection substrate 70E disposed between the through hole electrode substrate 1 and the wiring substrate 20 and having a resin substrate 91 and a conductive portion 92 penetrating the resin substrate 91, and an element 30 disposed on the opposite side of the through hole electrode substrate 1 from the connection substrate 70E. The semiconductor device 10E further includes a third bonding portion 61 electrically connecting the conductive portion 92 of the connection substrate 70E to the wiring substrate 40, a fourth bonding portion 62 electrically connecting the conductive portion 92 of the connection substrate 70E to the through hole electrode 3 of the through hole electrode substrate 1, and a fifth bonding portion 63 electrically connecting the through hole electrode 3 of the through hole electrode substrate 1 to the element 30. The thermal expansion coefficient of the resin substrate 91 in the planar direction is between the thermal expansion coefficient of the glass substrate 2 and the thermal expansion coefficient of the wiring substrate 20 in the planar direction.

[0475] Conventionally, a through-hole electrode substrate and a wiring substrate are electrically connected via a joint. For example, the joint connecting the through-hole electrode substrate and the wiring substrate is a solder joint. When the through-hole electrode substrate and the wiring substrate are connected via the solder joint during a reflow soldering process in a semiconductor device manufacturing process, the through-hole electrode substrate and the wiring substrate expand due to heat and then contract due to cooling. At this time, if the difference in thermal expansion coefficient between the through-hole electrode substrate and the wiring substrate is large, stress is generated in the joint connecting the through-hole electrode substrate and the wiring substrate and in the pad connected to this joint, making cracks and disconnections more likely. Furthermore, for example, when a semiconductor device is used in a high-temperature environment, if the difference in thermal expansion coefficient between the through-hole electrode substrate and the wiring substrate is large, stress is generated in the joint connecting the through-hole electrode substrate and the wiring substrate and in the pad connected to this joint, making cracks and disconnections more likely.

[0476] On the other hand, in the present disclosure, the through-hole electrode substrate and the wiring substrate are electrically connected via a connection substrate. The through-hole electrode substrate and the connection substrate are electrically connected via a joint, and the connection substrate and the wiring substrate are electrically connected via a joint. In this embodiment, the thermal expansion coefficient of the connection substrate in the plane direction is between the thermal expansion coefficient of the glass substrate constituting the through-hole electrode substrate and the thermal expansion coefficient of the wiring substrate in the plane direction. Therefore, the difference in the thermal expansion coefficient between the through-hole electrode substrate and the connection substrate, and the difference in the thermal expansion coefficient between the connection substrate and the wiring substrate, can be made smaller than the difference in the thermal expansion coefficient between the through-hole electrode substrate and the wiring substrate. Therefore, by disposing a connection substrate having a thermal expansion coefficient intermediate between that of the glass substrate and that of the wiring substrate between the through-hole electrode substrate and the wiring substrate, stress generated in the joints and pads disposed between the through-hole electrode substrate and the connection substrate, and in the joints and pads disposed between the connection substrate and the wiring substrate, can be alleviated. Therefore, in this embodiment, cracks and breaks in the joints and pads described above can be suppressed, thereby improving connection reliability.

[0477] Furthermore, in order to improve connection reliability, it is also possible to arrange a member for stress relief in the through electrode substrate. However, as mentioned above, the size of through electrode substrates is increasing, and there are concerns about a decrease in yield. In this embodiment, the connection substrate is fabricated separately from the through electrode substrate and the wiring substrate, which improves yield. Therefore, manufacturing costs can be reduced.

[0478] 1. Connection Board The connection board in this embodiment has a resin substrate and a conductive portion that penetrates the resin substrate.

[0479] (1) Resin Substrate The thermal expansion coefficient of the resin substrate in the plane direction is between that of the glass substrate and that of the wiring substrate. The thermal expansion coefficient of the resin substrate in the plane direction is the same as that of the resin layer in the fifth embodiment.

[0480] The material of the resin substrate is not particularly limited as long as it has insulating properties and the above-mentioned thermal expansion coefficient, and examples of the resin substrate include materials used for insulating substrates and insulating layers in general wiring boards. Examples of the resin substrate include a glass epoxy substrate and a glass polyimide substrate.

[0481] The thickness of the resin substrate is, for example, 100 μm or more, and may be 200 μm or more. When the thickness of the resin substrate is in the above range, the effect of stress relaxation by the resin substrate is easily obtained. On the other hand, the thickness of the resin substrate is, for example, 1 mm or less, and may be 600 μm or less. If the thickness of the resin substrate is too thick, it is disadvantageous in terms of cost. Specifically, the thickness of the resin substrate may be 100 μm or more and 1 mm or less, and 200 μm or more and 600 μm or less.

[0482] The resin substrate has through holes in the thickness direction. The method for forming the through holes is appropriately selected depending on the material of the resin substrate, and examples thereof include photolithography and laser processing. In the case of photolithography, the material of the resin substrate may be a photosensitive material, and a resist pattern may be formed on the resin substrate.

[0483] (2) Conductive Portion The shape, material and method of forming the conductive portion are the same as those of the conductive portion in the fifth embodiment.

[0484] (3) Other: The resin substrate of the connection board in this embodiment is a single layer. Furthermore, although the connection board has pad portions on the first and second surfaces of the resin substrate, it does not have wiring on either the first or second surface of the resin substrate. On the other hand, a wiring board generally has multiple insulating layers and multiple conductive layers alternately stacked, and the wiring board has wiring formed from patterns of the conductive layers. Therefore, the connection board in this embodiment is distinguished from a wiring board.

[0485] 2. Others The other points of the semiconductor device in this embodiment are the same as those described in the fifth embodiment.

[0486] The present disclosure is not limited to the above-described embodiments. The above-described embodiments are merely examples, and any configuration that is substantially identical to the technical idea described in the claims of the present disclosure and that provides similar effects is included within the technical scope of the present disclosure.

[0487] [Embodiment 1] [Examples 1-1 to 1-16, Comparative Examples 1-1 to 1-6] The semiconductor device shown in FIG. 3 was fabricated. A glass substrate 2 with a thermal expansion coefficient α2 of 3 ppm / °C and a thickness of 400 μm was used. A motherboard with a glass epoxy substrate (thermal expansion coefficient α1 of 12 ppm / °C) and a wiring pattern was used as the wiring substrate 20. The multilayer insulating layer 4 disposed on the first surface 2a of the glass substrate 2 included multiple first insulating layers 4a formed from polyimide resin. The first insulating layer closest to the glass substrate was a covering insulating layer 41 disposed to cover at least the boundary between the through electrode 3 and the glass substrate 2 and having a second through hole connecting to the first through hole. The number of layers of the second insulating layer 14a disposed on the second surface 2b of the glass substrate 2 was the same as the number of layers of the first insulating layer 4a. As shown in Tables 1 and 2, semiconductor devices were fabricated by varying the shear modulus G1 and thickness h1 of the multilayer insulating layer 4. The method for measuring the shear modulus G1 and thickness h1 of the multilayer insulating layer 4 is as described above. When determining the shear modulus of the multilayer insulating layer, the Young's modulus of the surface of the multilayer insulating layer was measured using an iNanoInForce50 model device manufactured by KLA Corporation. For each example and comparative example, the stress F1 calculated by the above (Equation 1-1) was Ａ The difference γ1 in the amount of strain in the above (Equation 1-1) was calculated by the above (Equation 4). That is, the difference γ1 in the amount of strain is the difference between the thermal expansion coefficient α1 of the wiring substrate and the thermal expansion coefficient α2 of the glass substrate (9×10 －６ / °C) by the temperature difference ΔT (230°C) and ½ of the length L of the diagonal line of the through electrode substrate (70 mm).

[0488] [Examples 1-17 to 1-29, Comparative Examples 1-7 to 1-10] Through hole electrode substrates and semiconductor devices were fabricated in the same manner as in Example 2-1, except that a glass substrate having a thermal expansion coefficient α2 of 7.2 ppm / °C and a thickness of 400 μm was used.

[0489] <Evaluation Method> The bonding reliability of each manufactured semiconductor device was evaluated according to the following criteria. The results are shown in Tables 1 to 3. A: No cracks or breaks occurred in the solder balls, pads, or wiring that electrically connect the through electrode substrate and the motherboard, and no defects occurred in ball mounting (misalignment of the ball). B: A crack or break occurred in the solder balls, pads, or wiring that electrically connect the through electrode substrate and the motherboard, or a defect occurred in ball mounting (misalignment of the ball).

[0490]

[0491]

[0492]

[0493] As shown in Tables 1 to 3, the shear modulus G1 of the multilayer insulating layer is 0.036 GPa or more, and the stress F1 Ａ It was confirmed that the connection reliability was good when the elastic modulus was 4.35 GPa or less.

[0494] [Embodiment 2] [Examples 2-1 to 2-16, Comparative Examples 2-1 to 2-6] The semiconductor device shown in Figure 9 was fabricated. A glass substrate 2 with a thermal expansion coefficient α2 of 3 ppm / °C and a thickness of 400 μm was used. A motherboard with a glass epoxy substrate (thermal expansion coefficient α1 of 12 ppm / °C) and a wiring pattern was used as the wiring substrate 20. The multilayer insulating layer 4 disposed on the first surface 2a of the glass substrate 2 included multiple first insulating layers 4a formed from polyimide resin. The first insulating layer 4a located closest to the glass substrate was a covering insulating layer 41 disposed to cover at least the boundary between the through electrode 3 and the glass substrate 2 and having a second through hole connecting to the first through hole. The shear modulus G1' of the multilayer insulating layer 4 is shown in Tables 3 and 4. A bismaleimide resin was used as the elastic insulating layer material. On the other hand, the number of layers of the second insulating layer 14a disposed on the second surface 2b side of the glass substrate 2 was the same as the number of layers of the first insulating layer 4a. As shown in Tables 3 and 4, semiconductor devices were manufactured by changing the shear modulus G2 of the multilayer insulating layer and the elastic insulating layer and the thickness h2 of the elastic insulating layer. The method for measuring the shear modulus G2 of the multilayer insulating layer and the elastic insulating layer and the thickness h2 of the elastic insulating layer was as described above. For each example and comparative example, the stress F2 calculated by the above (Equation 2-1) Ａ The difference γ1 in the amount of strain in the above (Equation 2-1) was calculated by the above (Equation 4). That is, the difference γ1 in the amount of strain is the difference between the thermal expansion coefficient α1 of the wiring substrate and the thermal expansion coefficient α2 of the glass substrate (9×10 －６ / °C) by the temperature difference ΔT (230°C) and ½ of the length L of the diagonal line of the through electrode substrate (70 mm).

[0495] <Evaluation Method> The bonding reliability of each of the manufactured semiconductor devices was evaluated. The results are shown in Tables 4 and 5.

[0496]

[0497]

[0498] As shown in Tables 4 and 5, the shear modulus G2 of the multilayer insulating layer and the elastic insulating layer is 0.036 GPa or more, and the stress F2 ＡIt was confirmed that the connection reliability was good when the elastic modulus was 4.35 GPa or less.

[0499] [Embodiment 3] [Examples 3-1 to 3-13, Comparative Examples 3-1 to 3-7] The semiconductor device shown in FIG. 12 was fabricated. A glass substrate 2 with a thermal expansion coefficient α2 of 3 ppm / °C and a thickness of 400 μm was used. A motherboard with a glass epoxy substrate (thermal expansion coefficient α1 of 16 ppm / °C) and a wiring pattern was used as the wiring substrate 20. The multilayer insulating layer 4 disposed on the first surface 2a of the glass substrate 2 included multiple first insulating layers 4a formed from polyimide resin. The first insulating layer closest to the glass substrate was a covering insulating layer 41 disposed to cover at least the boundary between the through electrode 3 and the glass substrate 2 and having a second through hole connecting to the first through hole. The number of layers of the second insulating layer 14a disposed on the second surface 2b of the glass substrate 2 was the same as the number of layers of the first insulating layer 4a. The hard insulating layer 8 disposed on the side of the multilayer insulating layer 4 opposite the glass substrate 2 was a cured product of a curable resin composition containing epoxy resin and a filler. As shown in Tables 5 and 6, semiconductor devices were manufactured by changing the shear modulus G1 of the multilayer insulating layer 4. The method for measuring the shear modulus G1 of the multilayer insulating layer 4 was as described above. When determining the shear modulus of the multilayer insulating layer, an iNanoInForce50 model device manufactured by KLA Corporation was used to measure the Young's modulus of the surface of the multilayer insulating layer. For each example and each comparative example, the stress F1 calculated by the above (Equation 1-2) was Ｂ The difference γ2 in the amount of strain in the above (Equation 1-2) was calculated by the above (Equation 5). That is, the difference γ2 in the amount of strain is calculated by the difference (9×10 －６ / °C) by the temperature difference ΔT (230°C) and ½ of the length L of the diagonal line of the through hole electrode substrate (70 mm). In addition, the thermal expansion coefficient difference Δα was calculated using the above (Equation 3).

[0500] <Evaluation> Ten semiconductor devices were manufactured for each example and comparative example, and the bonding reliability was evaluated according to the following criteria. The results are shown in Tables 6 and 7. AA: In all ten semiconductor devices, there were no cracks or breaks in the solder balls, pads, or wiring that electrically connect the through-hole electrode substrate and the motherboard, and no defects (misalignment of the ball) occurred during ball mounting. A: Of the ten semiconductor devices, two or fewer semiconductor devices had cracks or breaks in the solder balls, pads, or wiring that electrically connect the through-hole electrode substrate and the motherboard, or there was a defect during ball mounting (misalignment of the ball). B: Of the ten semiconductor devices, there were three or more semiconductor devices had cracks or breaks in the solder balls, pads, or wiring that electrically connect the through-hole electrode substrate and the motherboard, or there was a defect during ball mounting (misalignment of the ball).

[0501]

[0502]

[0503] As shown in Table 1 of the first embodiment, in a semiconductor device without a hard insulating layer, the shear modulus G1 of the multilayer insulating layer is 0.036 GPa or more, and the stress F1 Ａ On the other hand, when the shear modulus G1 and stress F1 of the multilayer insulating layer were 4.35 GPa or less (Examples 1-1 to 1-9), the connection reliability was good. Ｂ When either one of the above did not satisfy the above range (Comparative Examples 1-8 to 1-9, and Comparative Examples 1-10 to 1-12), the connection reliability decreased. Ｂ was confirmed to be important.

[0504] Furthermore, as shown in Tables 6 and 7, even in semiconductor devices having a hard insulating layer, the shear modulus G1 of the multilayer insulating layer is 0.036 GPa or more, and the stress F1 ＢWhen the shear modulus G1 and stress F1 of the multilayer insulating layer were 4.35 GPa or less and the difference in thermal expansion coefficient Δα between the wiring board and the hard insulating layer was 75% or less (Examples 3-1 to 3-13), the connection reliability was good. Ｂ When either one of the differences Δα in thermal expansion coefficient did not satisfy the above range (Comparative Examples 3-1 to 3-7), the connection reliability was reduced.

[0505] The shear modulus G1 of the multilayer insulating layer is 0.036 GPa or more, and the stress F1 Ｂ is 4.35 GPa or less and the difference in thermal expansion coefficient Δα between the wiring substrate and the hard insulating layer is 75% or less, the semiconductor devices having the hard insulating layer (Examples 3-1 to 3-13) have further improved connection reliability compared to the semiconductor devices not having the hard insulating layer (Reference Examples 3-1 to 3-9).

[0506] [Embodiment 4] [Examples 4-1 to 4-13, Comparative Examples 4-1 to 4-7] The semiconductor device shown in Figure 15 was fabricated. A glass substrate 2 with a thermal expansion coefficient α2 of 3 ppm / °C and a thickness of 400 μm was used. A motherboard with a glass epoxy substrate (thermal expansion coefficient α1 of 16 ppm / °C) and a wiring pattern was used as the wiring substrate 20. The multilayer insulating layer 4 disposed on the first surface 2a of the glass substrate 2 included multiple first insulating layers 4a formed from polyimide resin. The first insulating layer 4a located closest to the glass substrate was a covering insulating layer 41 disposed to cover at least the boundary between the through electrode 3 and the glass substrate 2 and having a second through hole connecting to the first through hole. The shear modulus G1' of the multilayer insulating layer 4 is shown in Tables 3 and 4. A bismaleimide resin was used as the elastic insulating layer material. On the other hand, the number of layers of the second insulating layer 14a disposed on the second surface 2b side of the glass substrate 2 was the same as the number of layers of the first insulating layer 4a. The hard insulating layer 8 disposed on the side of the multilayer insulating layer 4 opposite the glass substrate 2 was a cured product of a curable resin composition containing an epoxy resin and a filler. As shown in Tables 8 and 9, semiconductor devices were manufactured by changing the shear modulus G2 of the multilayer insulating layer and the elastic insulating layer and the thermal expansion coefficient α3 of the hard insulating layer. The methods for measuring the shear modulus G2 of the multilayer insulating layer and the elastic insulating layer and the thermal expansion coefficient α3 of the hard insulating layer were as described above. For each example and comparative example, the stress F2 calculated by the above (Equation 2-2) was Ｂ The difference γ2 in the amount of strain in the above (Equation 2-2) was calculated by the above (Equation 5). That is, the difference γ2 in the amount of strain is calculated by the difference between the thermal expansion coefficient α3 of the hard insulating layer and the thermal expansion coefficient α2 of the glass substrate (9×10 －６ / °C) by the temperature difference ΔT (230°C) and ½ of the length L of the diagonal line of the through hole electrode substrate (70 mm). In addition, the thermal expansion coefficient difference Δα was calculated using the above (Equation 3).

[0507] <Evaluation Method> The bonding reliability of each manufactured semiconductor device was evaluated according to the same criteria as in Embodiment 1. The results are shown in Tables 8 and 9.

[0508]

[0509]

[0510] As shown in Tables 8 and 9, the shear modulus G2 of the multilayer insulating layer and the elastic insulating layer is 0.036 GPa or more, and the stress F2 Ｂ When the shear modulus G2 and stress F2 of the multilayer insulating layer and the elastic insulating layer were 4.35 GPa or less and the difference in thermal expansion coefficient Δα between the wiring board and the hard insulating layer was 75% or less (Examples 4-1 to 4-13), the connection reliability was improved. Ｂ When either one of the differences in thermal expansion coefficient did not satisfy the above range (Comparative Examples 4-1 to 4-7), the connection reliability was reduced.

[0511] The present disclosure provides the following inventions: [1A] A through electrode substrate connected to a wiring substrate, comprising: a glass substrate having a first surface and a second surface opposite to the first surface and having a first through hole; a through electrode disposed in the first through hole of the glass substrate; a multilayer insulating layer disposed on the first surface side of the glass substrate and having a plurality of insulating layers; and a conductive layer disposed between the insulating layers and electrically connected to the through electrode, wherein when the shear modulus of the multilayer insulating layer is G1 (GPa), the difference in strain between the wiring substrate and the glass substrate is γ1 (mm), and the total thickness of the multilayer insulating layer is h1 (mm), the shear modulus of the multilayer insulating layer is 0.036 GPa or more, and a stress F1 calculated by the following (Equation 1-1) Ａ A through-hole electrode substrate, wherein F1 is 4.35 GPa or less. Ａ= (G1 × γ1) / h1 (Formula 1-1) [2A] A through electrode substrate connected to a wiring substrate, comprising: a glass substrate having a first surface and a second surface opposing the first surface and having a first through hole; a through electrode arranged in the first through hole of the glass substrate; a multilayer insulating layer having a plurality of insulating layers arranged on the first surface side of the glass substrate; an elastic insulating layer arranged on the surface of the multilayer insulating layer opposite the glass substrate; and conductive layers arranged between the insulating layers and between the multilayer insulating layer and the elastic insulating layer, and electrically connected to the through electrode; wherein when a shear modulus of elasticity of the multilayer insulating layer and the elastic insulating layer is G2 (GPa), a difference in strain amount between the wiring substrate and the glass substrate is γ1 (mm), and a thickness of the elastic insulating layer is h2 (mm), the shear modulus of elasticity G2 is 0.036 GPa or more, and a stress F2 calculated by the following (Formula 2-1) Ａ F2: A through-hole electrode substrate having a modulus of 4.35 GPa or less. Ａ = (G2 × γ1) / h2 (Formula 2-1) [3A] The through-hole electrode substrate according to [1A] or [2A], wherein the insulating layer located closest to the glass substrate in the multilayer insulating layer is a covering insulating layer arranged on the first surface side of the glass substrate so as to cover at least the boundary between the through-hole electrode and the glass substrate, and having a second through hole connecting to the first through hole. [4A] The through-hole electrode substrate according to any of [1A] to [3A], wherein the through-hole electrode substrate has a plurality of second insulating layers on the second surface side of the glass substrate. [5A] A through-hole electrode substrate with element, comprising: the through-hole electrode substrate according to any of [1A] to [4A]; and an element mounted on the through-hole electrode substrate. [6A] A semiconductor device comprising: the through-hole electrode substrate with element according to [5A]; a joint electrically connected to the conductive layer in the through-hole electrode substrate; and the wiring substrate electrically connected to the joint.

[0512] [1B] A through electrode substrate connected to a wiring substrate, comprising: a glass substrate having a first surface and a second surface opposite to the first surface and having a first through hole; a through electrode arranged in the first through hole of the glass substrate; a multilayer insulating layer arranged on the first surface side of the glass substrate and having a plurality of insulating layers; a hard insulating layer arranged on the surface of the multilayer insulating layer opposite the glass substrate; and conductive layers arranged between the insulating layers and between the multilayer insulating layer and the hard insulating layer and electrically connected to the through electrode, wherein when the shear modulus of the multilayer insulating layer is G1 (GPa), the difference in strain between the hard insulating layer and the glass substrate is γ2 (mm), and the total thickness of the multilayer insulating layer is h1 (mm), the shear modulus of elasticity G1 is 0.036 GPa or more, and a stress F1 calculated by the following (Equation 1-2) is 4.35 GPa or less, A through hole electrode substrate, wherein the difference in thermal expansion coefficient Δα calculated by the following (Equation 3) is 75% or less, where the thermal expansion coefficient of the wiring substrate is α1 ( / °C) and the thermal expansion coefficient of the hard insulating layer is α3 ( / °C). Ｂ = (G1 × γ2) / h1 (Formula 1-2) Δα = (|α1 - α3| / α1) × 100 (Formula 3) [2B] A through electrode substrate to be connected to a wiring substrate, comprising: a glass substrate having a first surface and a second surface opposing the first surface and having a first through hole; a through electrode arranged in the first through hole of the glass substrate; a multilayer insulating layer arranged on the first surface side of the glass substrate and having a plurality of insulating layers; an elastic insulating layer arranged on a surface of the multilayer insulating layer opposite to the glass substrate; a hard insulating layer arranged on a surface of the elastic insulating layer opposite to the multilayer insulating layer; and conductive layers arranged between the insulating layers, between the multilayer insulating layer and the elastic insulating layer, and between the elastic insulating layer and the hard insulating layer, and electrically connected to the through electrode, When the shear modulus of elasticity of the multilayer insulating layer and the elastic insulating layer is G2 (GPa), the difference in strain between the rigid insulating layer and the glass substrate is γ2 (mm), and the thickness of the elastic insulating layer is h2 (mm), the shear modulus of elasticity G2 is 0.036 GPa or more, and a stress F2 calculated by the following (Equation 2-2) Ｂa thermal expansion coefficient difference Δα calculated by the following formula (3) is 75%...

Claims

1. A through electrode substrate connected to a wiring substrate, comprising: a glass substrate having a first surface and a second surface opposite to the first surface and having a first through hole; a through electrode disposed in the first through hole of the glass substrate; a multilayer insulating layer disposed on the first surface side of the glass substrate and having a plurality of insulating layers; and a conductive layer disposed between the insulating layers and electrically connected to the through electrode, wherein the shear modulus of the multilayer insulating layer is G1 (GPa), the difference in strain between the wiring substrate and the glass substrate is γ1 (mm), and the total thickness of the multilayer insulating layer is h1 (mm), the shear modulus of the multilayer insulating layer is 0.036 GPa or more, and a stress F1 calculated by the following (Equation 1-1) Ａ A through-hole electrode substrate, wherein F1 is 4.35 GPa or less. Ａ =(G1×γ1) / h1 (Formula 1-1) 2. A through electrode substrate connected to a wiring substrate, comprising: a glass substrate having a first surface and a second surface opposite to the first surface and having a first through hole; a through electrode disposed in the first through hole of the glass substrate; a multilayer insulating layer having a plurality of insulating layers disposed on the first surface side of the glass substrate; an elastic insulating layer disposed on the surface of the multilayer insulating layer opposite the glass substrate; and conductive layers disposed between the insulating layers and between the multilayer insulating layer and the elastic insulating layer, and electrically connected to the through electrode; wherein, when the shear modulus of the multilayer insulating layer and the elastic insulating layer is G2 (GPa), the difference in strain between the wiring substrate and the glass substrate is γ1 (mm), and the thickness of the elastic insulating layer is h2 (mm), the shear modulus of elasticity G2 is 0.036 GPa or more, and a stress F2 calculated by the following (Equation 2-1) Ａ F2: A through-hole electrode substrate having a modulus of 4.35 GPa or less. Ａ =(G2×γ1) / h2 (Formula 2-1) 3. A through electrode substrate connected to a wiring substrate, comprising: a glass substrate having a first surface and a second surface opposite to the first surface and having a first through hole; a through electrode disposed in the first through hole of the glass substrate; a multilayer insulating layer disposed on the first surface side of the glass substrate and having a plurality of insulating layers; a hard insulating layer disposed on the surface of the multilayer insulating layer opposite the glass substrate; and conductive layers disposed between the insulating layers and between the multilayer insulating layer and the hard insulating layer and electrically connected to the through electrode; wherein, when the shear modulus of the multilayer insulating layer is G1 (GPa), the difference in strain between the hard insulating layer and the glass substrate is γ2 (mm), and the total thickness of the multilayer insulating layer is h1 (mm), the shear modulus of elasticity G1 is 0.036 GPa or more, and a stress F1 calculated by the following (Equation 1-2) Ｂ a thermal expansion coefficient of the wiring substrate is α1 ( / °C) and a thermal expansion coefficient of the hard insulating layer is α3 ( / °C), the thermal expansion coefficient difference Δα calculated by the following (Equation 3) is 75% or less. Ｂ =(G1×γ2) / h1 (Formula 1-2) Δα=(|α1-α3| / α1)×100 (Formula 3) 4. A through electrode substrate connected to a wiring substrate, comprising: a glass substrate having a first surface and a second surface opposite the first surface and having a first through hole; a through electrode disposed in the first through hole of the glass substrate; a multilayer insulating layer having a plurality of insulating layers disposed on the first surface side of the glass substrate; an elastic insulating layer disposed on the surface of the multilayer insulating layer opposite the glass substrate; a hard insulating layer disposed on the surface of the elastic insulating layer opposite the multilayer insulating layer; and conductive layers disposed between the insulating layers, between the multilayer insulating layer and the elastic insulating layer, and between the elastic insulating layer and the hard insulating layer, and electrically connected to the through electrode; wherein the shear modulus of elasticity of the multilayer insulating layer and the elastic insulating layer is G2 (GPa), the difference in strain between the hard insulating layer and the glass substrate is γ2 (mm), and the thickness of the elastic insulating layer is h2 (mm), the shear modulus of elasticity G2 is 0.036 GPa or more, and a stress F2 calculated by the following (Equation 2-2) Ｂ a thermal expansion coefficient of the wiring substrate is α1 ( / °C) and a thermal expansion coefficient of the hard insulating layer is α3 ( / °C), the difference in thermal expansion coefficient Δα calculated by the following (Equation 3) is 75% or less. Ｂ =(G2×γ2) / h2 (Formula 2-2) Δα=(|α1-α3| / α1)×100 (Formula 3) 5. A through electrode substrate according to any one of claims 1 to 4, wherein the insulating layer of the multilayer insulating layer located closest to the glass substrate is a covering insulating layer arranged on the first surface side of the glass substrate so as to cover at least the boundary between the through electrode and the glass substrate, and has a second through hole connected to the first through hole.

6. The through hole electrode substrate according to any one of claims 1 to 4, further comprising a plurality of second insulating layers on the second surface side of the glass substrate.

7. A through hole electrode substrate with an element, comprising: a through hole electrode substrate according to any one of claims 1 to 4; and an element mounted on the through hole electrode substrate.

8. A semiconductor device comprising: a through-hole electrode substrate with an element according to claim 7; a joint electrically connected to the conductive layer in the through-hole electrode substrate; and a wiring substrate electrically connected to the joint.

9. A connection board for electrically connecting a glass substrate and a through electrode substrate having through electrodes penetrating the glass substrate to a wiring board, the connection board having: a resin layer; and a conductive portion penetrating the resin layer, wherein the thermal expansion coefficient in the plane direction of the resin layer is between the thermal expansion coefficient in the plane direction of the glass substrate and the thermal expansion coefficient in the plane direction of the wiring board, and the shear modulus of the resin layer is 0.036 GPa or more and 20 GPa or less.

10. A connection board for electrically connecting a glass substrate and a through electrode board having through electrodes penetrating the glass substrate to a wiring board, the connection board having a resin layer and a conductive portion penetrating the resin layer, wherein the thermal expansion coefficient of the resin layer in the surface direction is between the thermal expansion coefficient of the glass substrate in the surface direction and the thermal expansion coefficient of the wiring board in the surface direction, and the thermal expansion coefficient α of the resin layer in the surface direction Ｐ and the thermal expansion coefficient α in the thickness direction of the resin layer. Ｔ The difference between Ｐ -α Ｔ is 9 ppm / °C or less.

11. A connection board for electrically connecting a glass substrate and a through electrode substrate having through electrodes penetrating the glass substrate to a wiring board, the connection board comprising: a base having an outer through hole; an elastic part having an inner through hole, which is disposed within the outer through hole of the base; and a conductive part disposed within the inner through hole of the elastic part.

12. A connection board for electrically connecting a glass substrate and a through electrode substrate having through electrodes penetrating the glass substrate to a wiring board, the connection board comprising: a support layer; a first elastic insulating layer disposed on a first surface of the support layer and having an uneven shape including a plurality of convex portions and a plurality of concave portions on a surface opposite to the support layer; a conductive portion penetrating the support layer and the first elastic insulating layer; and a first bellows wiring layer disposed on the surface of the first elastic insulating layer having the uneven shape, having a bellows-shaped portion with a plurality of ridges and a plurality of valleys, and electrically connected to the conductive portion.

13. The connection board according to claim 12, further comprising: a second elastic insulating layer disposed on the second surface of the support layer and having an uneven shape including a plurality of convex portions and a plurality of concave portions on the surface opposite the support layer; and a second bellows wiring layer disposed on the surface of the second elastic insulating layer having the uneven shape, having a bellows-shaped portion with a plurality of peaks and a plurality of valleys, and electrically connected to the conductive portion.

14. A semiconductor device comprising: a connection board according to any one of claims 9 to 13; the wiring board arranged on a first surface side of the connection board; the through electrode board arranged on a second surface side of the connection board; an element arranged on the opposite side of the through electrode board to the connection board; a third joint that electrically connects the conductive portion of the connection board and the wiring board; a fourth joint that electrically connects the conductive portion of the connection board and the through electrode of the through electrode board; and a fifth joint that electrically connects the through electrode of the through electrode board and the element.

15. A semiconductor device comprising: a through electrode substrate having a glass substrate and through electrodes penetrating the glass substrate; a wiring substrate; a connection substrate arranged between the through electrode substrate and the wiring substrate and having a resin substrate and a conductive portion penetrating the resin substrate; an element arranged on the opposite side of the through electrode substrate to the connection substrate; a third joint portion electrically connecting the conductive portion of the connection substrate to the wiring substrate; a fourth joint portion electrically connecting the conductive portion of the connection substrate to the through electrode of the through electrode substrate; and a fifth joint portion electrically connecting the through electrode of the through electrode substrate to the element, wherein the thermal expansion coefficient of the resin substrate in the plane direction is between the thermal expansion coefficient of the glass substrate in the plane direction and the thermal expansion coefficient of the wiring substrate in the plane direction.

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