Pulse generator and pulse generation method based on multi-phase delay-locked loop and high-precision nor gate

Abstract

Disclosed are a pulse generator and a pulse generation method based on a multi-phase delay-locked loop and a high-precision NOR gate. The pulse generator based on a multi-phase delay-locked loop and a high-precision NOR gate according to the present invention comprises: a delay-locked loop module that generates and outputs a phase of an input clock as a plurality of half-phase delay signals; a NOR edge-combining module including a plurality of NOR gates which generate, through pulse-edge combining using the plurality of half-phase delay signals, a specific pulse that satisfies a predetermined condition; a multiplexer that receives, from the NOR edge-combining module, specific pulses classified according to respective conditions, and selects and outputs a specific pulse corresponding to a pulse-selection signal received from a digital block among the received specific pulses; and a pulse-repetition-interval gating module that generates an output pulse by combining the specific pulse outputted from the multiplexer with a pulse-repetition-interval signal.

Description

Pulse generator and pulse generation method based on multiphase delay-locked loop and high-precision NOR gate

[0001] The present invention relates to a pulse generator and a pulse generation method based on a multiphase delay-locked loop and a high-precision NOR gate, and more particularly, to a pulse generator and a pulse generation method based on a multiphase delay-locked loop and a high-precision NOR gate capable of low power and an expanded pulse adjustment range.

[0002] In general, in the past, an oscillator with a phase-locked loop (PLL) structure consisting of a voltage-controlled oscillator, a phase frequency detector, and a filter was used to create a high-band frequency. However, an oscillator using a phase-locked loop has limitations in improving noise characteristics due to the technical limitations of the phase-locked loop.

[0003] In addition, recently, there is a demand for oscillators with better noise characteristics than conventional ones for application to various systems. Accordingly, various methods of generating high frequencies using a delay locked loop (DLL, hereinafter referred to as DLL) have been proposed. That is, in conventional communication systems, a delay locked loop that delays the phase of an input signal at each of the transmitter and receiver ends and a voltage controlled oscillator that controls the oscillation frequency through voltage control are used to convert an RF signal into an intermediate frequency signal or to generate a reference frequency signal for converting an intermediate frequency signal into an RF signal.

[0004] For example, a method of creating a desired frequency by selecting each delay cell within a delay-locked loop through a multiplexer and a method of creating various frequencies by placing two decoders for selecting pulses and a part for creating fractions in the part for selecting delay cells within the delay-locked loop are proposed.

[0005] However, the method of creating a desired frequency by switching delay cells, i.e. buffers, using a multiplexer requires more buffers to create various frequencies, which increases the layout area, and has the problem that noise characteristics deteriorate as the number of buffers increases due to noise generated in each buffer.

[0006] In addition, the method of generating various frequencies by placing two decoders and a part that generates fractions can generate frequencies that are not integer multiples of the desired frequency by randomizing each of them at a certain cycle to generate frequencies other than integer multiples, since the frequencies generated by switching each buffer depend on the delay time of each buffer. Therefore, although this method can generate frequencies that are each fractional multiples, there is a problem that noise is generated because the switches operate repeatedly, which deteriorates the overall noise characteristics.

[0007] Meanwhile, in a MIMO (Multiple Input Multiple Output) radar as illustrated in Fig. 1, a pulse generator that provides a wide pulse adjustment range and low pulse width error is required.

[0008] However, conventional MIMO radars detect objects by transmitting short pulses and measuring their reflections. However, the short pulses present challenges due to low average signal power. Furthermore, MIMO radar-based imaging systems require precise timing adjustments and precisely controlled phases of global clock signals for optimal performance.

[0009] The aforementioned MIMO radar-based system uses an array to improve the signal-to-noise ratio (SNR), and since each transmitter adjusts its transmission time relative to other transmitters to ensure consistent output performance, a pulse generation circuit capable of expanding the pulse adjustment range with a wide range of pulse widths and a fast response time is essential to ensure accurate and reliable operation of the pulse radar array.

[0010] Furthermore, even if a pulse generator capable of either a wide pulse tuning range or a fast response time is implemented, if it requires high power that would burden operation or has problems with phase response, it will still not meet the pulse generator requirements applied to systems based on MIMO radar.

[0011] Therefore, a method is needed to implement a pulse generator that can satisfy the pulse generator requirements applied to systems based on MIMO radar, etc., by reflecting the problems described above.

[0012] Accordingly, the present invention was created to solve the above problems, and the purpose of the present invention is to provide a pulse generator and pulse generation method based on a multi-phase delay-locked loop and a high-precision NOR gate capable of low power and pulse adjustment range expansion.

[0013] The purpose of the invention is not limited to the purposes mentioned above, and other purposes not mentioned will be clearly understood by those skilled in the art from the description below.

[0014] According to a first aspect of the present invention for achieving the above object, a pulse generator based on a multi-phase delay-locked loop and a high-precision NOR gate includes a delay-locked loop module that generates and outputs a phase of an input clock as a plurality of anti-phase delay signals, a NOR edge combining module having a plurality of NOR gates that generates a specific pulse that satisfies a predetermined specific condition by pulse edge combining using the plurality of anti-phase delay signals, a multiplexer that receives specific pulses classified by specific conditions from the NOR edge combining module and selects and outputs a specific pulse corresponding to a pulse selection signal received from a digital block among the received specific pulses, and a pulse repetition interval gating module that generates an output pulse that combines the specific pulse output from the multiplexer and a pulse repetition interval signal.

[0015] The above NOR edge coupling module can generate the specific pulse based on a two-channel pulse generation structure for the plurality of anti-phase delay signals.

[0016] The above digital block transmits the pulse selection signal to the multiplexer and transmits the pulse repetition interval signal to the pulse repetition interval gating module, and the pulse selection signal and the pulse repetition interval signal can be changed and set through serial parallel interface (SPI) control.

[0017] The above delay-locked loop module generates an odd number of the above-described anti-phase delay signals, and instead of outputting the last generated anti-phase delay signal to the NOR edge coupling module, it can be used for phase comparison between an input signal input to the delay-locked loop module and an output signal of the delay-locked loop module.

[0018] The above NOR edge coupling module can adjust the pulse width according to a pulse coupling method based on the delay sequence of the plurality of anti-phase delay signals.

[0019] According to a second aspect of the present invention for achieving the above object, a pulse generation method based on a multi-phase delay-locked loop and a high-precision NOR gate comprises a delay-locked loop step for generating and outputting a phase of an input clock as a plurality of anti-phase delay signals in a pulse generator based on a multi-phase delay-locked loop and a high-precision NOR gate, a NOR edge combining step for generating a specific pulse that meets predetermined specific conditions by pulse edge combining using the plurality of anti-phase delay signals, a multiplexer operation step for selecting and outputting a specific pulse corresponding to a pulse selection signal received from a digital block among the generated specific pulses, and a pulse repetition interval gating step for generating an output pulse by combining the selected and output specific pulse and a pulse repetition interval signal.

[0020] The above NOR edge coupling step may include a step of generating the specific pulse based on a two-channel pulse generation structure for the plurality of anti-phase delay signals.

[0021] The method may further include a step of changing and setting the pulse selection signal and the pulse repetition interval signal through serial parallel interface (SPI) control.

[0022] The above NOR edge coupling step may include a step of adjusting the pulse width according to a pulse coupling method based on the delay sequence for the plurality of anti-phase delay signals.

[0023] Therefore, the present invention has the advantage of enabling an extended pulse tuning range while reducing RMS jitter (Root Mean Square Jitter) through a multi-phase DLL architecture and a NOR gate-based pulse combining structure capable of high-precision pulse selection.

[0024] The effects of the present invention are not limited to the effects mentioned above, and other effects not mentioned will be clearly understood by those skilled in the art from the description of the claims.

[0025] Fig. 1 is an exemplary circuit diagram showing a MIMO pulse radar array according to the prior art.

[0026] Figure 2 is a schematic diagram showing a pulse generator according to one embodiment of the present invention.

[0027] Fig. 3 is a circuit diagram showing a more specific example of the pulse generator of Fig. 2.

[0028] Fig. 4 is a circuit diagram showing an example of the voltage control delay line of Fig. 3.

[0029] Figure 5 is a graph showing the simulation results for the circuit diagram of Figure 3.

[0030] Fig. 6 is a circuit diagram and graph showing an example of a circuit configuration and timing diagram for the phase detector of Fig. 3.

[0031] Figure 7 is a chip micrograph of a prototype circuit for the pulse generator of Figure 3.

[0032] Figure 8 is a graph showing the results of a simulation performed on the chip micrograph design of Figure 7.

[0033] And, Fig. 9 is a flowchart showing a pulse generation method according to one embodiment of the present invention.

[0034] The advantages and features of the present invention, and the methods for achieving them, will become clearer with reference to the embodiments described in detail below together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below and may be implemented in various different forms. These embodiments are provided only to ensure that the disclosure of the present invention is complete and to fully inform those skilled in the art of the scope of the invention, and the present invention is defined only by the scope of the claims. Like reference numerals designate like elements throughout the specification.

[0035] Furthermore, the embodiments described herein will be described with reference to cross-sectional and / or schematic drawings, which are ideal illustrations of the present invention. Therefore, the form of the illustrations may be modified due to manufacturing techniques and / or tolerances. Furthermore, in each drawing illustrated in the present invention, each component may be depicted somewhat enlarged or reduced for convenience of explanation.

[0036] The multi-phase delay-locked loop and high-precision NOR gate-based pulse generator and pulse generation method of the present invention are configured to enable an extended pulse adjustment range while reducing RMS jitter through a multi-phase DLL architecture and a NOR gate-based pulse combining structure capable of high-precision pulse selection.

[0037] Figure 2 is a schematic diagram showing a pulse generator according to one embodiment of the present invention.

[0038] As illustrated in FIG. 2, the pulse generator (100) of the present invention includes a delay-locked loop module (110) that generates and outputs the phase of an input clock as a plurality of anti-phase delay signals, a NOR edge combining module (120) having a plurality of NOR gates that generates a specific pulse that satisfies a predetermined specific condition by pulse edge combining using a plurality of anti-phase delay signals, a multiplexer (130) that receives specific pulses classified by specific conditions from the NOR edge combining module (120), and selects and outputs a specific pulse corresponding to a pulse selection signal received from a digital block (140) among the received specific pulses, and a pulse repetition interval gating module (150) that generates an output pulse that combines a specific pulse output from the multiplexer (130) and a pulse repetition interval signal.

[0039] Here, the generation of a specific pulse that meets a predetermined specific condition means a pulse having a phase and pulse width that is to be output from the pulse generator (100) of the present invention, which can be generated by a NOR gate based on a plurality of anti-phase delay signals.

[0040] That is, a number of specific pulses can be generated through NOR gates equipped according to the specific conditions described above.

[0041] Additionally, one of the multiple specific pulses can be selected through the digital block (140), and an output pulse can be generated by combining the selected specific pulse and the pulse repetition interval signal.

[0042] The pulse repetition interval signal means the time interval between specific pulses, and any one specific pulse can be selected from among the multiple specific pulses described above, and the pulse repetition interval can be adjusted for the selected specific pulse, so not only is high-precision pulse selection possible, but also the pulse adjustment range can be expanded.

[0043] Fig. 3 is a circuit diagram showing a more specific example of the pulse generator of Fig. 2.

[0044] As illustrated in FIG. 3, the NOR edge coupling module (120) can generate a specific pulse based on a two-channel pulse generation structure for a plurality of anti-phase delay signals.

[0045] The delay-locked loop module (110) generates an odd number of anti-phase delay signals, and instead of outputting the last generated anti-phase delay signal to the NOR edge coupling module (120), it uses it for phase comparison between the input signal input to the delay-locked loop module (110) and the output signal of the delay-locked loop module, thereby enabling the phase of the input signal and the phase of the output signal to be precisely aligned.

[0046] Specifically, the delay-locked loop module (110) may include a phase detector (PD), a charge pump (CP) that adjusts voltage according to the output of the phase detector, a loop filter (LF) that smoothes the output of the charge pump to generate a stable control voltage, and a voltage-controlled delay line (VCDL) that adjusts signal delay according to the control voltage.

[0047] In addition, the digital block (140) transmits a pulse selection signal to the multiplexer (130) and a pulse repetition interval signal to the pulse repetition interval gating module (150), and the pulse selection signal and the pulse repetition interval signal can be changed and set through serial parallel interface (SPI: Serial Parallel Interface) control.

[0048] The NOR edge coupling module (120) can adjust the pulse width according to a pulse coupling method based on the delay sequence of a plurality of anti-phase delay signals.

[0049] Examples of multiple anti-phase delay signals based on the circuit diagram of Fig. 3 are given in Table 1 below.

[0050] Pulse NumberΦAΦBDelaySimulated Pulse Width (ps)1Φ20Φ21τ243.92Φ19Φ223τ731.73Φ18Φ235τ1219.54Φ17Φ247τ1707.35Φ16Φ259τ2195.16Φ1 5Φ2611τ2682.97Φ14Φ2713τ3170.78Φ13Φ2815τ3658.59Φ12Φ2917τ4146.310Φ11Φ3019τ4634.111 Φ10Φ3121τ5121.912Φ9Φ3223τ5609.713Φ8Φ3325τ6097.514Φ7Φ3427τ6585.315Φ6Φ3529τ7073.1 16Φ5Φ3631τ7560.917Φ4Φ3733τ8048.718Φ3Φ3835τ8536.519Φ2Φ3937τ9024.420Φ1Φ4039τ9512.2

[0051] In Fig. 3, as an example of generating and outputting 41 anti-phase delay signals, the last signal, Φ41 signal, is input to a phase detector and can be used for comparison, and signals Φ1 to Φ40 are input to a NOR edge coupling module and are generated as specific pulses through edge coupling of each NOR gate.

[0052] By NOR edge coupling for the Φ20 signal and the Φ21 signal, a short pulse with a pulse width of 243.9 ps can be generated, and by NOR edge coupling for the Φ1 signal and the Φ40 signal, a long pulse with a pulse width of 9512.2 ps can be generated.

[0053] Such pulse width can be approximated to the theoretical pulse width through Equation 1 below.

[0054] [Formula 1]

[0055]

[0056] Here, PWN refers to the pulse width of the selected NOR gate.

[0057] Fig. 4 is a circuit diagram showing an example of the voltage control delay line of Fig. 3.

[0058] As illustrated in FIG. 4, each stage of the voltage-controlled delay line can be equipped with a nine-stage inverter cell with a variable capacitor load, the delay of each stage contributing to the edge coupling configuration, and the output of the final stage can be used for comparison with a reference signal of a phase detector.

[0059] Additionally, a 180-degree phase shift is applied using an odd number of inverters in each stage, and the delay (τ) per stage is defined as in Equation 2 below.

[0060] [Formula 2]

[0061]

[0062] Here, N represents the number of stages.

[0063] And, in the drawing a) of Fig. 5, the simulation results show the delay per stage of VCDL according to VTUNE for TT (typical-typical), SS (slow-slow), and FF (fast-fast) corners. When VTUNE changes from 100 mV to 900 mV, it can be confirmed that the TT, SS, and FF corners show delays of 135.3-300 ps, ​​148.9-330.7 ps, and 120-258.8 ps, respectively.

[0064] In the drawing b) of Fig. 5, the timing diagram from the delay stage Φ18 to Φ21 and the subsequent NOR gate that inverts the adjacent outputs and then generates the minimum pulse width (τ) and the next minimum pulse width (3τ) are shown.

[0065] In the example of FIG. 3 of the present invention, a 50 MHz reference clock was selected, which theoretically results in a per-line delay of approximately 244 ps. Table 1, mentioned above, lists combinations of DLL outputs and corresponding pulse widths in the implemented 50 MHz FREF.

[0066] Fig. 6 is a circuit diagram and graph showing an example of a circuit configuration and timing diagram for the phase detector of Fig. 3.

[0067] Drawing a) of Fig. 6 shows an example of a circuit configuration of a phase detector, which can alleviate the stuck issue by incorporating AND logic, and as shown in b) of Fig. 6, when the loop is locked to a specific phase and the reference frequency FREF and the final VCDL output FDIV are not aligned by 180°, a reset (RST) pulse is generated to reset the phase detector and restore the state. Conversely, when the loop is stabilized and the DLL is locked, the RST pulse has a duty ratio of 50% and is aligned with FREF and FDIV.

[0068] FIG. 7 is a chip micrograph of a prototype circuit for the pulse generator of FIG. 3, and FIG. 8 is a graph showing the results of a simulation performed on the chip micrograph design of FIG. 7.

[0069] As shown in Figs. 7 and 8, a prototype pulse generator (100) manufactured using TSMC 45nm technology is shown, and occupies 0.8mm² including the pad. An individual pulse generator including the DLL is only 0.048mm². For measurements, an Agilent 33250A arbitrary waveform generator (AWG) was used to generate reference clocks of 40, 45, and 50MHz, and interfaced with the digital pad and input driver.

[0070] Measurements were performed primarily using a Tektronix MDO3102 oscilloscope, and jitter measurements were performed using a Keysight MSOS804A. The digital pad and input drivers were operated at 2.5 V, and the pulse generator (100) was operated at 1 V.

[0071] The chip design and verification were performed using an ideal rectangular pulse. To analyze the impact of a non-ideal input signal (limited slew rate of the rectangular pulse when measured at a high reference frequency), simulations were performed using square and sine wave reference clocks, with the input buffer and digital pad level-shifting the reference clock from 2.5 V to 1 V at the core of the pulse generator (100). The simulation results (Figs. 8(a), (b)) showed that at a 50 MHz input reference, the square wave generated a pulse width of 10 ns, while the sine wave generated a pulse width of 12.4 ns, with duty cycles of the desired 50% and the non-ideal 62.4%, respectively. Despite the uneven duty cycle of the sine wave, the DLL was confirmed to be stably locked (Fig. 8(c)). The voltage difference between the square and sine wave signals, which was affected by the digital I / O buffer provided in the standard library, affected the phase detector reading, resulting in a shorter pulse in the case of the sine wave. The simulation results confirmed that the pulse width was 215 ps for the square wave and 174 ps for the sine wave at a 50 MHz input reference.

[0072] Meanwhile, jitter measurements were performed at a 50-MHz operating frequency at the maximum pulse width setting, and while jitter characteristics may accumulate in a typical DLL due to various delay paths, the multi-phase DLL design of the present invention and subsequent processing in the pulse combiner significantly reduced the measured jitter, as can be seen in Table 2 below.

[0073] ParametersJSSC13[5]TCAS-Ⅱ14

[0013] TCAS-Ⅱ14

[0014] TVLSI 15

[0015] TCAS-Ⅱ22

[0016] This workProcess0.13μm SiGe BiCMOS0.15μm0.13μmCMOS0.13μmCMOS180nmCMOS45nmCMOSBlocksDLL+Pulser+BufferDLLDLLDLLDLLDLL+Pulser+BufferSupply[V]2.51.81.21.51.81Frequency[GHz]1.470.02-0.1350.4-0.80.08-0.450.25†0.04-0.09Lock time-< 25cycles-8-16cycles-†10cyclesOutput phase9744441Jitter rms [ps]-#13 @ 0.1-GHz2.3 @ 0.8-GHz2.3 @ 0.18-GHz#2 @ 0.25-GHz6 @ 0.05-GHzPower[mW]2352.2 @0.13-GHz7.2 @0.8-GHz26 @0.18-GHz2.28 @0.25-GHz3.2 @0.05-GHz*PEF[J]17.762.412.2536.112.281.56Active area[mm 2 ]0.250.0230.0250.080.090.048

[0074] *: PEF(Power Efficiency Factor) = Power[mW] / (Frequency[GHz] x Output Phases).

[0075] #: Converted from p-p jitter by multiplying with 10 -12 BER tolerance.

[0076] †: Simulated results.

[0077]

[0078] Accordingly, the present invention enables expansion of the pulse adjustment range while overcoming the problem of increased power consumption due to accumulation of jitter characteristics according to multiple delay paths of a DLL through a multi-phase DLL architecture and a NOR gate-based pulse coupling structure capable of high-precision pulse selection.

[0079] And, Fig. 9 is a flowchart showing a pulse generation method according to one embodiment of the present invention.

[0080] As illustrated in Fig. 9, the pulse generation method based on a multi-phase delay-locked loop and a high-precision NOR gate proceeds by generating and outputting the phase of an input clock as a plurality of anti-phase delay signals in a pulse generator (100) based on a multi-phase delay-locked loop and a high-precision NOR gate (S100).

[0081] An additional process of generating specific pulses that meet specific pre-determined conditions by combining pulse edges using multiple anti-phase delay signals output at step S100 is performed (S102).

[0082] A multiplexer operation process is performed to select and output a specific pulse corresponding to a pulse selection signal received from a digital block among specific pulses generated in S102 (S104), and a process is performed to generate and output an output signal that combines the selected specific pulse and a pulse repetition interval signal (S106).

[0083] Afterwards, if there is a setting to change the pulse selection signal and pulse repetition interval signal through serial parallel interface (SPI: Serial Parallel Interface) control, the above S104 to S108 processes can be performed again.

[0084] Detailed steps and additional descriptions of the steps described above will be based on FIGS. 2 to 8 and the descriptions of these drawings.

[0085] Although the embodiments of the present invention have been described with reference to the above and the attached drawings, those skilled in the art will understand that the present invention can be implemented in other specific forms without altering the technical concept or essential characteristics thereof. Therefore, the embodiments described above should be understood to be illustrative in all respects and not restrictive.

[0086] In addition, the present invention provides a pulse generator and pulse generation method based on a multi-phase delay-locked loop capable of low power and pulse adjustment range expansion and a high-precision NOR gate, and thus, the invention has sufficient possibility of being commercialized or sold, and is thus an invention with industrial applicability to the extent that it can be clearly implemented in reality.

Claims

1. A delay-locked loop module that generates and outputs the phase of an input clock as a number of anti-phase delay signals; A NOR edge coupling module having a plurality of NOR gates that generate a specific pulse that meets a predetermined specific condition by using the plurality of anti-phase delay signals and pulse edge coupling; A multiplexer that receives specific pulses classified by specific conditions from the NOR edge coupling module, and selects and outputs a specific pulse corresponding to a pulse selection signal received from a digital block among the received specific pulses; and A pulse generator based on a high-precision NOR gate and a multi-phase delay-locked loop including a pulse repetition interval gating module that generates an output pulse by combining a specific pulse output from the multiplexer and a pulse repetition interval signal.

2. In paragraph 1, The above NOR edge coupling module is a multi-phase delay-locked loop that generates the specific pulse based on a two-channel pulse generation structure for the above multiple anti-phase delay signals and a pulse generator based on a high-precision NOR gate.

3. In paragraph 1, The digital block transmits the pulse selection signal to the multiplexer and the pulse repetition interval signal to the pulse repetition interval gating module, and the pulse selection signal and the pulse repetition interval signal are a pulse generator based on a multi-phase delay locked loop and a high-precision NOR gate that are changed and set through serial parallel interface (SPI) control.

4. In paragraph 1, The above delay-locked loop module generates an odd number of the above-mentioned anti-phase delay signals, and instead of outputting the last generated anti-phase delay signal to the NOR edge coupling module, uses the input signal input to the delay-locked loop module and the output signal of the delay-locked loop module for phase comparison, and a pulse generator based on a high-precision NOR gate.

5. In paragraph 4, The above NOR edge coupling module is a multi-phase delay-locked loop that adjusts the pulse width according to a pulse coupling method based on the delay sequence of the plurality of anti-phase delay signals and a pulse generator based on high-precision NOR gates.

6. In a pulse generator based on a multi-phase delay-locked loop and a high-precision NOR gate, a delay-locked loop stage that generates and outputs the phase of an input clock as a plurality of anti-phase delay signals; A NOR edge coupling step for generating specific pulses that each meet predetermined specific conditions by using the above multiple anti-phase delay signals and pulse edge coupling; A multiplexer operation step for selecting and outputting a specific pulse corresponding to a pulse selection signal received from a digital block among the generated specific pulses; and A pulse generation method based on a multi-phase delay-locked loop and a high-precision NOR gate, including a pulse repetition interval gating step for generating an output pulse by combining the above-mentioned selected and output specific pulse and pulse repetition interval signal.

7. In paragraph 6, A pulse generation method based on a multi-phase delay-locked loop and a high-precision NOR gate, wherein the NOR edge coupling step includes a step of generating the specific pulse based on a two-channel pulse generation structure for the plurality of anti-phase delay signals.

8. In paragraph 6, A pulse generation method based on a multi-phase delay-locked loop and a high-precision NOR gate, further comprising a step of changing and setting the pulse selection signal and the pulse repetition interval signal through serial parallel interface (SPI) control.

9. In paragraph 6, A pulse generation method based on a multi-phase delay-locked loop and a high-precision NOR gate, wherein the above NOR edge coupling step includes a step of adjusting a pulse width according to a pulse coupling method based on the delay sequence for the plurality of anti-phase delay signals.

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