Array substrate, display panel, and display device

Abstract

An array substrate (001), a display panel (PNL), and a display device. The array substrate (001) comprises: a base substrate (101); a plurality of pixel electrodes (102) arranged in an array on the base substrate (101); a plurality of data lines (103) extending in column gaps between the pixel electrodes (102); a plurality of gate lines (104) extending in row gaps between the pixel electrode (102), two gate lines being included in the same row gap (104); a plurality of first common electrode lines (105) arranged in the same layer as the plurality of gate lines (104), each first common electrode line (105) being located between the two gate lines (104) in the same row gap; a plurality of second common electrode lines (106) arranged in the same layer as the plurality of data lines (103), the second common electrode lines (106) and the data lines (103) being alternately arranged in different column gaps between the pixel electrodes (102), and the orthographic projections of the second common electrode lines (106) on the base substrate (101) and the orthographic projections of the first common electrode lines (105) on the base substrate (101) intersecting with one another to form a mesh; an insulating layer (107) comprising first via holes (V1) exposing the positions at which the first common electrode lines (105) intersect with the second common electrode lines (106); and transparent electrodes (108) respectively electrically connected to the first common electrode lines (105) and the second common electrode lines (106) by means of the first via holes (V1).

Description

Array substrate, display panel and display device TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, and particularly relates to an array substrate, a display panel and a display device. BACKGROUND

[0002] Thin Film Transistor Liquid Crystal Display (TFT-LCD) has the characteristics of small volume, low power consumption, high picture quality, no radiation and portability, and has been rapidly developed in recent years, and has gradually replaced the traditional Cathode Ray Tube display (CRT) and occupies a dominant position in the current flat panel display market. At present, TFT-LCD has been widely used in various large, medium and small size products, and almost covers the main electronic products in today's information society, such as liquid crystal televisions, high-definition digital televisions, computers (desktop and notebook), mobile phones, tablet computers, navigation instruments, vehicle-mounted displays, projection displays, video cameras, digital cameras, electronic watches, calculators, electronic instruments, instruments, public displays and virtual reality displays, etc.

[0003] SUMMARY

[0004] The array substrate, the display panel and the display device provided by the present disclosure have the following specific solutions.

[0005] In one aspect, the present disclosure provides an array substrate, comprising:

[0006] a substrate substrate;

[0007] a plurality of pixel electrodes arranged in an array on the substrate substrate;

[0008] a plurality of data lines extending at column gaps of the pixel electrodes;

[0009] a plurality of gate lines extending at row gaps of the pixel electrodes, and each row gap includes two gate lines;

[0010] a plurality of first common electrode lines arranged in the same layer as the plurality of gate lines, and the first common electrode lines are located between the two gate lines in the same row gap;

[0011] a plurality of second common electrode lines arranged in the same layer as the plurality of data lines, and the second common electrode lines are alternately arranged with the data lines at different column gaps of the pixel electrodes, and the orthographic projection of the second common electrode lines on the substrate substrate and the orthographic projection of the first common electrode lines on the substrate substrate cross each other to form a mesh shape;

[0012] an insulating layer comprising a first via hole exposing an intersection of the first common electrode line and the second common electrode line;

[0013] a transparent electrode electrically connected to the first common electrode line and the second common electrode line through the first via hole.

[0014] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, the transparent electrode comprises a plurality of first hollow structures, and a projection of the first hollow structure on the substrate substrate and a projection of the pixel electrode on the substrate substrate overlap each other.

[0015] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, the transparent electrode is a planar electrode covering the plurality of pixel electrodes.

[0016] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, the data line and / or the second common electrode line comprises a connection part spanning two gate lines and a signal part between adjacent pixel electrodes in the same row; wherein,

[0017] The line width of the signal part is greater than the line width of the connection part, and the junction line of the signal part and the connection part extends in a direction perpendicular to the signal part.

[0018] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, the projection of the transparent electrode on the substrate substrate and the projection of the data line on the substrate substrate overlap each other.

[0019] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, further comprising a plurality of transistors located at the row gap;

[0020] The insulating layer further comprises a second via hole arranged on both sides of the first via hole extending in the column direction, and the pixel electrode is electrically connected to the first electrode of the transistor through the second via hole.

[0021] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, the center of the first via hole and the center of the second via hole are arranged substantially collinearly in the row direction.

[0022] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, further comprising a plurality of overlapping electrodes arranged in the same layer as the transparent electrode, the overlapping electrodes covering at least the bottom of the second via hole, and the overlapping electrodes being connected between the pixel electrode and the first electrode of the transistor.

[0023] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, the transparent electrode further comprises a plurality of second hollow structures, and the second hollow structures are provided with the overlap electrodes.

[0024] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, the second hollow structure is mutually overlapped with the projection of the transistor on the substrate.

[0025] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, the insulating layer comprises a color resistance layer, and the color resistance layer comprises a plurality of openings.

[0026] The projection of the opening on the substrate covers the projections of the first via and the two second vias between the two adjacent data lines on the substrate.

[0027] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, further comprising a spacer, and the projection of the spacer on the substrate is mutually overlapped with the area surrounded by the projection of the opening on the substrate, the projection of the data line on the substrate, and the projections of the two pixel electrodes arranged in the column direction on the substrate.

[0028] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, the color resistance layer comprises color resistance strips of multiple colors extending in the column direction, and the adjacent edges of the adjacent color resistance strips are mutually overlapped.

[0029] The projection of the second common electrode line on the substrate is mutually overlapped with the projection of the overlapped edges of the adjacent color resistance strips on the substrate.

[0030] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, the insulating layer further comprises a gate insulating layer between the layer where the gate line is located and the layer where the data line is located, a passivation layer between the layer where the data line is located and the color resistance layer, a first planar layer between the color resistance layer and the layer where the transparent electrode is located, and a second planar layer between the layer where the transparent electrode is located and the layer where the pixel electrode is located.

[0031] The first via penetrates the gate insulating layer, the passivation layer, the color resistance layer and the first planar layer at the overlapping position with the first common electrode line, and the first via penetrates the passivation layer, the color resistance layer and the first planar layer at the overlapping position with the second common electrode line.

[0032] The second via penetrates the passivation layer, the color resistance layer, the first planar layer and the second planar layer.

[0033] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, the gate of the transistor is located on one side of the gate line close to the first common electrode line.

[0034] The first electrode of the transistor includes an electrode portion, and a projection of the electrode portion on the substrate substrate along a row direction across a projection of the gate of the transistor on the substrate substrate.

[0035] The second electrode of the transistor is located on one side of the data line close to the gate of the transistor, and a projection of the second electrode of the transistor on the substrate substrate along a row direction across a projection of the gate of the transistor on the substrate substrate.

[0036] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, the projection of the first electrode of the transistor on the substrate substrate and the projection of the first common electrode line on the substrate substrate overlap each other.

[0037] In another aspect, the embodiments of the present disclosure provide a display panel, comprising an array substrate and an opposite substrate, the array substrate being the above-mentioned array substrate provided by the embodiments of the present disclosure.

[0038] In some embodiments, in the display panel provided by the embodiments of the present disclosure, the opposite substrate comprises a common electrode.

[0039] In some embodiments, in the display panel provided by the embodiments of the present disclosure, the opposite substrate further comprises a black matrix, and the common electrode is located on one side of the black matrix facing the array substrate.

[0040] The projection of the black matrix on the substrate substrate and the projection of the row gap on the substrate substrate overlap each other, and do not overlap with the projection of the column gap between the pixel electrodes in the same row on the substrate substrate.

[0041] In another aspect, the embodiments of the present disclosure provide a display device, comprising the above-mentioned display panel provided by the embodiments of the present disclosure, and a backlight module located on the light side of the display panel. BRIEF DESCRIPTION OF DRAWINGS

[0042] FIG. 1 is a structural schematic diagram of an array substrate provided by the embodiments of the present disclosure;

[0043] FIG. 2 is a structural schematic diagram of eight sub-pixel regions in the array substrate provided by the embodiments of the present disclosure;

[0044] FIG. 3 is a structural schematic diagram of the layer where the transistor is located and the layer where the via is located in twelve sub-pixel regions provided by the embodiments of the present disclosure;

[0045] FIG. 4 is a structure diagram of a zoomed-in view of the Z1 region in FIG. 2;

[0046] FIG. 5 is a structure diagram of the insulating layer in FIG. 4;

[0047] FIG. 6 is a structure diagram of a cross-sectional view along the line I-I' in FIG. 4;

[0048] FIG. 7 is a structure diagram of a cross-sectional view along the line II-II' in FIG. 2;

[0049] FIG. 8 is a structure diagram of another cross-sectional view of an array substrate provided by an embodiment of the present disclosure;

[0050] FIG. 9 is a structure diagram of a zoomed-in view of the Z2 region in FIG. 3;

[0051] FIG. 10 is a structure diagram of a zoomed-in view of the Z3 region in FIG. 3;

[0052] FIG. 11 is a structure diagram of the gate metal layer in FIG. 2;

[0053] FIG. 12 is a structure diagram of the active layer in FIG. 2;

[0054] FIG. 13 is a structure diagram of the source-drain metal layer in FIG. 2;

[0055] FIG. 14 is a structure diagram of the color resist layer in FIG. 2;

[0056] FIG. 15 is a structure diagram of the gate insulating layer, the passivation layer, and the first planarization layer in FIG. 2;

[0057] FIG. 16 is a structure diagram of the layer in which the transparent electrode is located in FIG. 2;

[0058] FIG. 17 is a structure diagram of the second planarization layer in FIG. 2;

[0059] FIG. 18 is a structure diagram of the layer in which the pixel electrode is located in FIG. 2;

[0060] FIG. 19 is a structure diagram of a pixel electrode provided by an embodiment of the present disclosure;

[0061] FIG. 20 is a structure diagram of another pixel electrode provided by an embodiment of the present disclosure;

[0062] FIG. 21 is a structure diagram of two sub-pixel regions in a display panel provided by an embodiment of the present disclosure;

[0063] FIG. 22 is a structure diagram of a cross-sectional view along the line III-III' in FIG. 21;

[0064] FIG. 23 is a structure diagram of a display device provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0065] For the purpose of making the objects, technical solutions and advantages of the embodiments of the present disclosure clearer, the following will be described with reference to the drawings of the embodiments of the present disclosure. In the drawings, the thicknesses of layers, films, panels, regions and the like are exaggerated for clarity. In the present disclosure, example embodiments are described with reference to cross-sectional views that are schematic illustrations of idealized embodiments. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, embodiments described in the present disclosure are not to be construed as being limited to the particular shapes of regions as illustrated but are to include deviations in shapes that result from, for example, manufacturing. For example, an area illustrated or described as flat can typically have rough and / or nonlinear features; an illustrated sharp angle can be rounded, etc. Thus, the regions illustrated in the figures are schematic and their shapes are not intended to illustrate the precise shape of a region and are not reflective of the true scale or proportions of a region. Like numbers refer to like or similar elements throughout.

[0066] Unless otherwise defined, technical terms or scientific terms used herein shall have the same meaning as is commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terms "first", "second", and similar terms do not denote any order, quantity, or importance, but are used to distinguish one element from another, and the terms "comprises", "comprising", "includes", "including" and the like can be used herein and mean including but not limited to as set out herein. The terms "connected", "coupled", and the like, can be used herein and mean one or more elements or components connected or coupled at least indirectly together, whether connected or coupled directly together or connected or coupled indirectly together, via one or more interposed elements or components. The terms "inner", "outer", "upper", "lower", and the like, can be used herein and mean relative positions for the purposes of illustration only, and can be reversed when the positions of the described objects are changed.

[0067] In the following description, when an element or layer is referred to as being "on" or "connected to" another element or layer, it can be directly on the other element or layer, or be directly connected to the other element or layer, or intervening elements or layers can be present. When an element or layer is referred to as being "on one side of" another element or layer, it can be directly on the side of the other element or layer, or be directly connected to the other element or layer, or intervening elements or layers can be present. When an element or layer is referred to as being "directly on" or "directly connected to" another element or layer, there are no intervening elements or layers present. The term "and / or" includes any and all combinations of one or more of the associated listed items. The various embodiments of the present disclosure can be combined with each other, without conflict, if not incompatible.

[0068] In a display product, such as a curved display product, a dual gate (Dual Gate) combined with a color resist layer (COA) process arranged on an array substrate has a good cost advantage and will have better market competitiveness. However, the inventors have found that the common electrode line of the related dual gate product cannot form a mesh structure, resulting in a large resistance of the common electrode line, which cannot quickly recover after the common voltage signal is coupled, thereby causing quality problems such as lateral crosstalk.

[0069] To improve the above technical problems existing in the related art, an array substrate is provided in the embodiments of the present disclosure. FIG. 1 is a structural schematic diagram of an array substrate provided by the embodiments of the present disclosure, FIG. 2 is a structural schematic diagram of eight sub-pixel regions in the array substrate provided by the embodiments of the present disclosure, FIG. 3 is a structural schematic diagram of a layer where transistors are located and a layer where vias are located in twelve sub-pixel regions provided by the embodiments of the present disclosure, FIG. 4 is an enlarged structural schematic diagram of a Z1 region in FIG. 2, FIG. 5 is a structural schematic diagram of an insulating layer in FIG. 4, FIG. 6 is a cross-sectional structural schematic diagram along line I-I' in FIG. 3, FIG. 7 is a cross-sectional structural schematic diagram along line II-II' in FIG. 2, FIG. 8 is another cross-sectional structural schematic diagram of the array substrate provided by the embodiments of the present disclosure, FIG. 9 is an enlarged structural schematic diagram of a Z2 region in FIG. 3, FIG. 10 is an enlarged structural schematic diagram of a Z3 region in FIG. 3, FIGS. 11 to 18 are structural schematic diagrams of each film layer in FIG. 4, respectively, FIG. 19 is a structural schematic diagram of a pixel electrode provided by the embodiments of the present disclosure, and FIG. 20 is another structural schematic diagram of a pixel electrode provided by the embodiments of the present disclosure.

[0070] In some embodiments, as shown in FIGS. 1 to 18, the array substrate provided by the embodiments of the present disclosure can include:

[0071] A substrate 101, which can include red sub-pixel regions R, green sub-pixel regions G, blue sub-pixel regions B, and the like arranged in an array; in some embodiments, the substrate 101 is a substrate that allows visible light to pass through, such as a glass, quartz, plastic, or the like.

[0072] A plurality of pixel electrodes 102 arranged in an array in the red sub-pixel regions R, the green sub-pixel regions G, and the blue sub-pixel regions B, and each adjacent two columns of pixel electrodes 102 can be a pixel electrode group PX; the material of the pixel electrode 102 can include at least one transparent conductive material, such as indium tin oxide (ITO), indium zinc oxide (IZO), aluminum zinc oxide (AZO), gallium zinc oxide (GZO), or the like.

[0073] It should be noted that the pixel electrode 102 can include a pixel portion P1 located in the pixel opening region and a lap portion P2 located in the pixel non-opening region. In some embodiments, the pixel portion P1 can be a block electrode as shown in FIG. 18, a dual-domain slit electrode as shown in FIG. 19, or a four-domain slit electrode as shown in FIG. 20. Optionally, the multiple electrode strips of the slit electrode can be connected together at the four peripheral edges or can be connected in the middle and disconnected from each other at at least one of the four peripheral edges. In addition, the row gap of the pixel electrode 102 in the present disclosure specifically refers to the row gap of the pixel portion P1, and the column gap of the pixel electrode 102 specifically refers to the column gap of the pixel portion P1.

[0074] A plurality of data lines 103 extend at the column gaps of the pixel electrodes 102. In some embodiments, each data line 103 can be electrically connected to a pixel electrode group PX, and the data line 103 is located in the column gap between the two pixel electrodes 102 in the pixel electrode group PX. In some embodiments, the material of the data line 103 can include metals such as molybdenum (Mo), aluminum (Al), titanium (Ti), chromium (Cr), and nickel (Ni). The data line 103 can have a single-layer structure or a stacked structure, for example, the data line 103 can have a stacked structure composed of a Mo / Ni metal layer / Cu metal layer.

[0075] A plurality of gate lines 104 extend at the row gaps of the pixel electrodes 102. The same row gap includes two gate lines 104, one of which can be electrically connected to the odd-numbered pixel electrodes 102 in its adjacent row, and the other of which can be electrically connected to the even-numbered pixel electrodes 102 in its adjacent row. In some embodiments, the material of the gate line 104 can include metals such as molybdenum (Mo), aluminum (Al), titanium (Ti), chromium (Cr), and nickel (Ni). The gate line 104 can have a single-layer structure or a stacked structure, for example, the gate line 104 can have a stacked structure composed of a Mo / Ni metal layer / Cu metal layer.

[0076] A plurality of first common electrode lines 105 are arranged in the same layer and made of the same material as the plurality of gate lines 104. The first common electrode line 105 is located between the two gate lines 104 in the same row gap. In the present disclosure, "in the same layer" means that the film layer used to make a specific pattern is formed by the same film forming process, and then the layer structure is formed by one patterning process using the same mask plate. That is, one patterning process corresponds to one mask (also known as a photomask). According to different specific patterns, one patterning process can include multiple exposure, development or etching processes, and the specific patterns in the formed layer structure can be continuous or discontinuous, and these specific patterns can be at the same height or have the same thickness, or can be at different heights or have different thicknesses.

[0077] A plurality of second common electrode lines 106 are arranged in the same layer and of the same material as the plurality of data lines 103, the second common electrode lines 106 and the data lines 103 are arranged alternately at the column gap of the pixel electrodes 102, and optionally, the data lines 103 are arranged at the column gap of the two columns of pixel electrodes 102 included in the pixel electrode group PX, the second common electrode lines 106 are arranged at the column gap of the adjacent pixel electrode group PX, and the orthogonal projection of the second common electrode lines 106 on the substrate 101 can cross the orthogonal projection of the first common electrode lines 105 on the substrate 101 to form a mesh shape.

[0078] The insulating layer 107 includes a first via V1, the first via V1 exposes the intersection position of the first common electrode line 105 and the second common electrode line 106, and in some embodiments, the first via V1 can partially expose the intersection position of the first common electrode line 105 and the second common electrode line 106, and the first via V1 extends left and right to expose the part of the first common electrode line 105 that does not overlap with the second common electrode line 106.

[0079] The transparent electrode 108 is electrically connected with the first common electrode line 105 and the second common electrode line 106 through the first via V1, thereby realizing the electrical connection of the first common electrode line 105 and the second common electrode line 106 arranged in different layers and crossing each other.

[0080] In the array substrate provided in the embodiments of the present disclosure, the first common electrode line 105 and the second common electrode line 106 are arranged in different layers and cross each other and are electrically connected to form a mesh-shaped common electrode line, which can reduce the overall resistance of the common electrode line, so that the common voltage signal can quickly recover after being coupled, thereby effectively improving the picture quality problems such as lateral crosstalk.

[0081] In some embodiments, in the array substrate provided in the embodiments of the present disclosure, as shown in FIGS. 1, 4, 13 and 16, the orthogonal projection of the transparent electrode 108 on the substrate 101 can overlap with the orthogonal projection of the data line 103 on the substrate 101, and optionally, the orthogonal projection of the data line 103 on the substrate 101 is located within the orthogonal projection of the transparent electrode 108 on the substrate 101. The related art uses a shielding metal line to shield the coupling capacitance Cpd between the data line 103 and the pixel electrode 102. Specifically, the layer where the shielding metal line is located is between the layer where the data line 103 is located and the substrate 101, and the orthogonal projection of the shielding metal line is located on both sides of the orthogonal projection of the data line 103, resulting in a large coupling capacitance between the data line 103 and the shielding metal line. In actual display operation, the coupling of the data signal (Data) jump to the shielding metal line will cause the crosstalk phenomenon. The present disclosure uses the transparent electrode 108 to replace the shielding metal line to shield Cpd, which can avoid the coupling capacitance between the data line 103 and the shielding metal line, thereby improving the crosstalk phenomenon.

[0082] In some embodiments, in the array substrate provided in the embodiments of the present disclosure, as shown in FIGS. 1, 4 and 7, the transparent electrode 108 can include a plurality of first hollow structures OW1, the orthogonal projection of the first hollow structure OW1 on the substrate 101 overlaps with the orthogonal projection of the pixel electrode 102 on the substrate 101, and optionally, the orthogonal projection of the first hollow structure OW1 on the substrate 101 is located within the orthogonal projection of the pixel electrode 102 on the substrate 101, which can reduce the storage capacitance formed by the transparent electrode 108 and the pixel electrode 102, improve the charging rate, and be suitable for high refresh rate products (such as 144Hz, 240Hz, etc.). In products with low refresh rate (such as 60Hz), the transparent electrode 108 can be a planar electrode covering all the pixel electrodes 102 (as shown in FIG. 8), which can better shield the coupling capacitance Cpd between the data line 103 and the pixel electrode 102 while meeting the charging rate.

[0083] In some embodiments, in the array substrate provided in the embodiments of the present disclosure, as shown in FIGS. 2, 3, 9 and 13, the data line 103 and / or the second common electrode line 106 comprises a connection part SD1 spanning two gate lines 104, and a signal part SD2 located between the pixel electrodes 102 in the same row; the line width of the signal part SD2 is greater than that of the connection part SD1, so as to reduce the coupling capacitance between the data line 103 and / or the second common electrode line 106 and the gate line 104. Optionally, unlike the design of using an oblique angle (for example, 45°) at the position where the line width of the data line 103 changes in the related art, which causes the reflection of the data line 103 to be unable to be blocked by the liquid crystal layer and results in poor light leakage, the design of using a right angle at the position where the line width of the data line 103 and / or the second common electrode line 106 changes in the present disclosure, in other words, the intersection line L between the signal part SD2 and the connection part SD1 extends along a direction perpendicular to the signal part SD2, so as to ensure that the reflection of the data line 103 and / or the second common electrode line 106 is blocked by the liquid crystal layer, thereby reducing the light leakage in the dark state and improving the contrast.

[0084] In some embodiments, in the array substrate provided in the embodiments of the present disclosure, as shown in FIGS. 2, 3 to 6, 11 to 15, 17 and 18, a plurality of transistors 109 located at the row gap of the pixel electrode 102 can be further included; the insulating layer 107 comprises a second via V2 arranged on the left and right sides of the first via V1 extending along the column direction Y, and the pixel electrode 102 is electrically connected to the first electrode D of the transistor 109 through the second via V2; optionally, the center O of the first via V1 and the center O of the second via V2 are arranged in the row direction X and are substantially collinear. In this way, the space occupied by the first via V1 and the second via V2 can be saved as much as possible, so as to ensure that the station space of the spacers PS is sufficient.

[0085] It should be noted that in the embodiments provided in the present disclosure, due to the limitation of process conditions or the influence of other factors such as measurement, the "substantially collinear" relationship between the related features can be exactly collinear, or there can be some deviation (for example, with a deviation of ±1 μm), and therefore the "substantially collinear" relationship between the related features as long as the error is allowed belongs to the protection scope of the present disclosure.

[0086] In some embodiments, in the array substrate provided in this disclosure, as shown in FIG9 and FIG10, the gate G' of transistor 109 is located on the side of gate line 104 near the first common electrode line 105; the first electrode D of transistor 109 includes an electrode portion D', the orthographic projection of the electrode portion D' on the substrate 101 spans the orthographic projection of the gate G' of transistor 109 on the substrate 101 along the row direction X; the second electrode S of transistor 109 is located on the side of data line 103 near the gate G' of transistor 109, the orthographic projection of the second electrode S of transistor 109 on the substrate 101 spans the orthographic projection of the gate G' of transistor 109 on the substrate 101 along the row direction X; optional The linewidth of electrode D' is approximately the same as that of the second electrode S. The distance (e.g., more than 2 μm) that electrode D' extends to the left (i.e., closer to data line 103) relative to gate G' is approximately the same as the distance (e.g., more than 2 μm) that the second electrode S extends to the right (i.e., further away from data line 103) relative to gate G'. This makes electrode D', the second electrode S, and the gate G' between them form an "I" shaped structure. This ensures that when the gate metal layer and the source / drain metal layer undergo an off-center (OVL) shift, the coupling capacitance Cgd between gate G' and electrode D' on both sides of data line 103, and the coupling capacitance Cgs between gate G' and the second electrode S can remain stable, avoiding problems such as flickering caused by inconsistent capacitance.

[0087] In some embodiments, in the array substrate provided in this disclosure, as shown in FIG9, the projection of the first electrode D of transistor 109 onto the substrate 101 can overlap with the orthographic projection of the first common electrode line 105 onto the substrate 101. When the pixel electrode 102 is abnormally bright, the first electrode D of transistor 109 and the first common electrode line 105 can be switched on at the overlapping position to darken the pixel. Furthermore, since a black matrix is ​​typically provided at the row gaps of the pixel electrode 102, the switching position of the first electrode D of transistor 109 and the first common electrode line 105 is located within the black matrix and will not affect the transmittance.

[0088] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, as shown in FIGS. 2, 4, 6 and 16, the array substrate can further include a plurality of overlap electrodes 110 arranged in the same layer as the transparent electrode 108, the overlap electrodes 110 cover at least the bottom of the second via V2, and the overlap electrodes 110 are connected between the pixel electrode 102 (specifically, the overlap portion P2 included in the pixel electrode 102) and the first electrode D of the transistor 109. The overlap electrodes 110 covering at least the bottom of the second via V2 can avoid etching the first electrode D at the bottom of the second via V2 in the process of etching to form the transparent electrode 108 and the overlap electrodes 110. In addition, to ensure the electrical connection effect, the edge of the overlap portion P2 included in the pixel electrode 102 around the second via V2 can cover the edge of the overlap electrodes 110, that is, the orthogonal projection of the overlap portion P2 on the substrate 101 can be larger than the orthogonal projection of the overlap electrodes 110 on the substrate 101.

[0089] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, as shown in FIGS. 1, 4, 11-13 and 16, to avoid short circuiting between the transparent electrode 108 and the overlap electrode 110, the second hollow structure OW2 can be arranged in the transparent electrode 108, and the overlap electrode 110 is arranged in the second hollow structure OW2. Optionally, the orthogonal projection of the second hollow structure OW2 on the substrate 101 and the orthogonal projection of the transistor 109 on the substrate 101 overlap each other, and in some embodiments, the orthogonal projection of the transistor 109 on the substrate 101 is located in the orthogonal projection of the second hollow structure OW2 on the substrate 101, to avoid the coupling capacitance between the transparent electrode 108 and the transistor 109 from interfering with each other.

[0090] In some embodiments, in the array substrate provided in the embodiments of the present disclosure, as shown in FIGS. 4 to 7, the insulating layer 107 can include a color resist layer CF, the color resist layer CF including a plurality of openings OW3 penetrating through the thickness of the color resist layer CF; the opening OW3 covers the orthographic projection of the first via V1 and the two second vias V2 between the two adjacent data lines 103 on the substrate 101, that is, the first via V1 and the two second vias V2 all penetrate through the color resist layer CF, and one first via V1 and two second vias V2 between the two adjacent data lines 103 form a large hole V in the color resist layer CF, and the large hole V is located in the opening OW3. Optionally, for the convenience of description, the present disclosure refers to one first via V1 and two second vias V2 penetrating through the insulating layer 107 and located between the two adjacent data lines 103 as a triple hole, and the orthographic projection of the opening OW3 on the substrate 101 can be extended by a certain distance (for example, 5 μm) up, down, left and right relative to the orthographic projection of the triple hole on the substrate 101, so that the opening OW3 of the color resist layer CF can accommodate the triple hole, and at the same time, the standing space of the spacers PS in the non-opening area can be ensured, and the pixel aperture ratio can be effectively improved.

[0091] In some embodiments, as shown in FIG. 4, the orthographic projection of the spacer PS on the substrate 101 (i.e., the standing space of the spacer PS) can be mutually overlapped with the area surrounded by the orthographic projection of the opening OW3 on the substrate 101, the orthographic projection of the data line 103 on the substrate 101, and the orthographic projection of the two pixel electrodes 102 arranged in the column direction Y on the substrate 101, and exemplarily, the orthographic projection of the spacer PS on the substrate 101 (i.e., the standing space of the spacer PS) is located in the area surrounded by the orthographic projection of the opening OW3 on the substrate 101, the orthographic projection of the data line 103 on the substrate 101, and the orthographic projection of the two pixel electrodes 102 arranged in the column direction Y on the substrate 101. In some embodiments, the spacer PS can be arranged on the array substrate or on the opposite substrate, which is not limited in the present disclosure.

[0092] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, as shown in FIGS. 4, 5, 7 and 8, the color resist layer CF includes color resist strips of multiple colors (for example, red color resist strips r corresponding to the red sub-pixel area R, green color resist strips g corresponding to the green sub-pixel area G, and blue color resist strips b corresponding to the blue sub-pixel area B, etc.) extending along the column direction Y, and adjacent edges of adjacent color resist strips (for example, the red color resist strip r and the green color resist strip g, the green color resist strip g and the blue color resist strip b, the blue color resist strip b and the red color resist strip r, etc.) overlap each other; the orthogonal projection of the second common electrode line 106 on the substrate 101 can overlap the orthogonal projection of the overlapping edges of adjacent color resist strips (for example, the red color resist strip r and the green color resist strip g, the green color resist strip g and the blue color resist strip b, the blue color resist strip b and the red color resist strip r, etc.) on the substrate 101, and optionally, the orthogonal projection of the second common electrode line 106 on the substrate 101 covers the orthogonal projection of the overlapping edges of adjacent color resist strips (for example, the red color resist strip r and the green color resist strip g, the green color resist strip g and the blue color resist strip b, the blue color resist strip b and the red color resist strip r, etc.) on the substrate 101, so as to block light in the color resist overlapping area by the second common electrode line 106 to prevent color mixing failure.

[0093] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, as shown in FIG. 6, the insulating layer 107 can further include a gate insulating layer GI between the layer where the gate line 104 is located and the layer where the data line 103 is located, a passivation layer PVX between the layer where the data line 103 is located and the color resist layer CF, a first planarization layer ORG1 between the color resist layer CF and the layer where the transparent electrode 108 is located, and a second planarization layer ORG2 between the layer where the transparent electrode 108 is located and the layer where the pixel electrode 102 is located; the first via V1 penetrates the gate insulating layer GI, the passivation layer PVX, the color resist layer CF and the first planarization layer ORG1 at the overlapping position of the first common electrode line 105, and the first via V1 penetrates the passivation layer PVX, the color resist layer CF and the first planarization layer ORG1 at the overlapping position of the second common electrode line 106; the second via V2 penetrates the passivation layer PVX, the color resist layer CF, the first planarization layer ORG1 and the second planarization layer ORG2.

[0094] Based on the same inventive concept, the display panel provided by the embodiments of the present disclosure is provided. FIG. 21 is a structural schematic diagram of two sub-pixel regions in the display panel provided by the embodiments of the present disclosure, and FIG. 22 is a cross-sectional structural schematic diagram along the line III-III' in FIG. 21. As shown in FIG. 21 and FIG. 22, the display panel includes an array substrate 001 and an opposite substrate 002 opposite to each other, wherein the array substrate 001 is the array substrate 001 provided by the embodiments of the present disclosure, and the opposite substrate 002 includes a common electrode 201, a black matrix 202 and a substrate 203. The common electrode 201 is located on a side of the black matrix 202 away from the substrate 203. Optionally, the common electrode 201 is provided on the entire display area AA. The black matrix 202 is arranged on the substrate 101. The orthogonal projection of the black matrix 202 on the substrate 101 and the orthogonal projection of the inter-row gap on the substrate 101 overlap each other, and the orthogonal projection of the column gap of the pixel electrode 102 in the same row on the substrate 101 does not overlap the orthogonal projection of the black matrix 202 on the substrate 101. That is, the black matrix 202 of the present disclosure exposes the column gap of the pixel electrode 102 in the same row and the transverse opening OW4 of the pixel part P1 in the same row, so as to avoid the longitudinal black matrix from blocking the pixel opening area due to the alignment deviation and affecting the display in the curved display panel. In some embodiments, the common electrode 201 can also be provided on the array substrate 001, which is not limited herein. The present disclosure takes the common electrode 201 provided on the opposite substrate 002 as an example for description.

[0095] In some embodiments, the display panel provided by the embodiments of the present disclosure can be a curved display panel. The display panel can further include a liquid crystal layer 003 between the array substrate and the opposite substrate, a first polarizer 004 on a side of the array substrate 001 away from the opposite substrate 002, and a second polarizer 005 on a side of the opposite substrate 002 away from the array substrate 001. The polarization direction of the first polarizer 004 is perpendicular to the polarization direction of the second polarizer 005. The other indispensable components of the display panel should be understood by those skilled in the art, which are not described herein and should not be regarded as a limitation on the present disclosure.

[0096] Based on the same inventive concept, the display device provided by the embodiments of the present disclosure comprises the display panel PNL provided by the embodiments of the present disclosure and a backlight module BLU located on the light-in side of the display panel PNL, as shown in FIG. 23. The backlight module BLU can be a direct backlight module or a side backlight module. Optionally, the side backlight module can comprise a lamp bar, a reflector sheet, a light guide plate, a diffusion sheet, a prism group and the like, and the lamp bar is located on one side of the light guide plate in the thickness direction. The direct backlight module can comprise a matrix light source, a reflector sheet, a diffusion plate and a brightness enhancement film and the like which are stacked on the light-out side of the matrix light source, and the reflector sheet comprises apertures which are arranged opposite to the positions of the lamp beads in the matrix light source. The lamp beads in the lamp bar and the lamp beads in the matrix light source can be light-emitting diodes (LEDs), such as micro light-emitting diodes (Mini LED, Micro LED and the like).

[0097] The micro light-emitting diode in the order of sub-millimeter or even micrometer and the organic light-emitting diode (OLED) are both self-luminous devices. Like the organic light-emitting diode, the micro light-emitting diode has a series of advantages such as high brightness, ultra-low delay, ultra-large viewing angle and the like. Moreover, since the inorganic light-emitting diode emits light based on the metal semiconductor with more stable properties and lower resistance, it has the advantages of lower power consumption, longer service life and better resistance to high and low temperatures compared with the organic light-emitting diode which emits light based on organic matter. When the micro light-emitting diode is used as a backlight source, it can realize more precise dynamic backlight effect, effectively improve the brightness and contrast of the screen, and solve the glare phenomenon caused by the traditional dynamic backlight between the bright and dark areas of the screen, thereby optimizing the visual experience.

[0098] In some embodiments, the display device provided by the embodiments of the present disclosure can be any product or component with display function, such as a projector, a 3D printer, a virtual reality device, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigation device, a smart watch, a fitness wristband, a personal digital assistant, and the like. Optionally, the display device provided by the embodiments of the present disclosure includes, but is not limited to, a radio frequency unit, a network module, an audio output & input unit, a sensor, a display unit, a user input unit, an interface unit, a control chip, and the like. Optionally, the control chip is a central processing unit, a digital signal processor, a system chip (SoC), and the like. For example, the control chip can further include a memory, and can further include a power module, and the like, and the power supply and signal input and output functions are realized through wires, signal lines, and the like arranged additionally. For example, the control chip can further include hardware circuitry and computer executable code, and the like. The hardware circuitry can include conventional very large scale integration (VLSI) circuitry or gate array, and existing semiconductors or other discrete elements such as logic chips, transistors, and the like; the hardware circuitry can also include field programmable gate array, programmable array logic, programmable logic device, and the like. In addition, those skilled in the art can understand that the above structure does not constitute a limitation on the display device provided by the embodiments of the present disclosure, in other words, the display device provided by the embodiments of the present disclosure can include more or less components, or combine certain components, or arrange different components.

[0099] Although the preferred embodiments of the present disclosure have been described, those skilled in the art can make additional changes and modifications to the embodiments once they know the basic inventive concept. Therefore, the appended claims are intended to be interpreted as including all the preferred embodiments and all the changes and modifications falling within the scope of the present disclosure.

[0100] Obviously, those skilled in the art can make various modifications and variations to the embodiments of the present disclosure without departing from the spirit and scope of the embodiments of the present disclosure. Thus, if these modifications and variations of the embodiments of the present disclosure fall within the scope of the claims of the present disclosure and their equivalent technologies, the present disclosure is also intended to include these modifications and variations.

Claims

1. An array substrate, wherein, The application relates to a display panel, comprising: a substrate; a plurality of pixel electrodes arranged in an array on the substrate; a plurality of data lines extending at column gaps of the pixel electrodes; a plurality of gate lines extending at row gaps of the pixel electrodes, each row gap comprising two gate lines; a plurality of first common electrode lines arranged in the same layer as the gate lines, the first common electrode lines being located between the two gate lines in the same row gap; a plurality of second common electrode lines arranged in the same layer as the data lines, the second common electrode lines being alternately arranged with the data lines at different column gaps of the pixel electrodes, and the orthogonal projection of the second common electrode lines on the substrate and the orthogonal projection of the first common electrode lines on the substrate intersect each other to form a mesh shape; an insulating layer comprising a first via hole exposing the intersection position of the first common electrode lines and the second common electrode lines; a transparent electrode electrically connected with the first common electrode lines and the second common electrode lines through the first via hole.

2. The array substrate of claim 1, wherein, The transparent electrode comprises a plurality of first hollow structures, and the orthogonal projection of the first hollow structures on the substrate is located in the orthogonal projection of the pixel electrodes on the substrate.

3. The array substrate of claim 1, wherein, The transparent electrode is a planar electrode covering the plurality of pixel electrodes.

4. The array substrate according to any one of claims 1 to 3, wherein, The data lines and / or the second common electrode lines comprise a connecting portion crossing two gate lines and a signal portion located between adjacent pixel electrodes in the same row; wherein the line width of the signal portion is greater than that of the connecting portion, and the boundary line between the signal portion and the connecting portion extends in a direction perpendicular to the signal portion. The orthogonal projection of the transparent electrode on the substrate and the orthogonal projection of the data lines on the substrate overlap each other.

5. The array substrate according to any one of claims 1 to 4, wherein, Further comprising a plurality of transistors located at the row gaps; 6. The array substrate according to any one of claims 1 to 5, wherein, the insulating layer further comprises a second via hole arranged on both sides of the first via hole extending in the column direction, and the pixel electrodes are electrically connected with the first electrodes of the transistors through the second via hole. The center of the first via hole and the center of the second via hole are arranged in the same line in the row direction.

7. The array substrate of claim 6, wherein, Further comprising a plurality of overlapping electrodes arranged in the same layer as the transparent electrode, the overlapping electrodes at least covering the bottom of the second via hole, and the overlapping electrodes being connected between the pixel electrodes and the first electrodes of the transistors.

8. The array substrate of claim 6 or 7, wherein, The transparent electrode further comprises a plurality of second hollow structures, and the orthogonal projection of the second hollow structures on the substrate covers the orthogonal projection of the overlapping electrodes on the substrate.

9. The array substrate of claim 8, wherein, The orthogonal projection of the second hollow structures on the substrate and the orthogonal projection of the transistors on the substrate overlap each other.

10. The array substrate of claim 9, wherein, The insulating layer comprises a color resistance layer, and the color resistance layer comprises a plurality of openings; 11. The array substrate according to any one of claims 6 to 10, wherein, the orthogonal projection of the openings on the substrate covers the orthogonal projection of the first via hole and the two second via holes on the substrate between the adjacent two data lines. ​ 12. The array substrate of claim 11, wherein, The spacer further includes a projection on the substrate, which overlaps with a region surrounded by a projection on the substrate of the opening, a projection on the substrate of the data line, and projections on the substrate of two pixel electrodes arranged along a column direction.

13. The array substrate of claim 11 or 12, wherein, The color resist layer includes color resist strips of multiple colors extending along a column direction, and adjacent edges of adjacent color resist strips overlap with each other. A projection on the substrate of the second common electrode line overlaps with a projection on the substrate of an overlapping edge of adjacent color resist strips.

14. The array substrate of any one of claims 11 to 13, wherein, The insulating layer further includes a gate insulating layer between the layer where the gate line is located and the layer where the data line is located, a passivation layer between the layer where the data line is located and the color resist layer, a first planarization layer between the color resist layer and the layer where the transparent electrode is located, and a second planarization layer between the layer where the transparent electrode is located and the layer where the pixel electrode is located. The first via penetrates the gate insulating layer, the passivation layer, the color resist layer, and the first planarization layer at an overlapping position with the first common electrode line, and penetrates the passivation layer, the color resist layer, and the first planarization layer at an overlapping position with the second common electrode line. The second via penetrates the passivation layer, the color resist layer, the first planarization layer, and the second planarization layer.

15. The array substrate according to any one of claims 6 to 14, wherein, The gate of the transistor is located on one side of the gate line close to the first common electrode line. The first pole of the transistor includes an electrode portion, and a projection on the substrate of the electrode portion spans a projection on the substrate of the gate of the transistor along a row direction. The second pole of the transistor is located on one side of the data line close to the gate of the transistor, and a projection on the substrate of the second pole of the transistor spans a projection on the substrate of the gate of the transistor along a row direction.

16. The array substrate according to any one of claims 6 to 15, wherein, The first pole of the transistor overlaps with a projection on the substrate of the first common electrode line.

17. A display panel, wherein, The array substrate includes the array substrate as claimed in any one of claims 1-16.

18. The display panel of claim 17, wherein, The opposite substrate includes a common electrode.

19. The display panel of claim 17 or 18, wherein, The opposite substrate further includes a black matrix, and the common electrode is located on one side of the black matrix facing the array substrate. A projection on the substrate of the black matrix overlaps with a projection on the substrate of an inter-row gap, and does not overlap with a projection on the substrate of an inter-column gap between pixel electrodes in the same row.

20. A display device comprising: The display panel includes the display panel as claimed in any one of claims 17-19, and a backlight module located on a light-incident side of the display panel.

Images