Chip stacking structure, manufacturing method therefor, chip packaging structure, and electronic device

Abstract

The present application provides a chip stacking structure, a manufacturing method therefor, a chip packaging structure, and an electronic device. The chip stacking structure comprises: a first chip, at least one second chip, and a support structure. Each second chip is located between the first chip and the support structure. The first chip is electrically connected to each second chip, and the support structure is connected to each second chip. An integrated passive device is provided in the support structure, and the integrated passive device is electrically connected to the at least one second chip; and / or the integrated passive device is electrically connected to the first chip. In embodiments of the present application, the integrated passive device is integrated into the support structure, so that the integrated passive device, the second chip, and the first chip can be stacked in the vertical direction, the interconnection distance between the second chip and / or the first chip and the integrated passive device can be greatly reduced, the level of integration of the chip stacking structure can be improved, and the manufacturing costs can be reduced. Moreover, the substrate utilization rate of the support structure can also be increased, and the internal structure of the chip stacking structure can be reasonably used.

Description

Chip stacking structure, manufacturing method thereof, chip packaging structure and electronic device

[0001] Cross-reference to related applications

[0002] The present application claims priority to the Chinese patent application No. 202411136478.7, filed on August 16, 2024, and entitled "Chip stacking structure, manufacturing method thereof, chip packaging structure and electronic device", the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0003] The present application relates to the technical field of chip packaging, and in particular to a chip stacking structure, a manufacturing method thereof, a chip packaging structure and an electronic device. BACKGROUND

[0004] With Moore's Law gradually reaching its limit, chip packaging technology is gradually developing in the direction of three-dimensional (3D) stacking. The 3D stacked chip packaging form provides a new "performance / size ratio" solution for the industry in the post-Moore era and has been widely used in the fields of high-performance computing, high-bandwidth storage, mobile communication miniaturization, etc.

[0005] At present, three-dimensional stacking technology includes die to die (D2D) stacking, die to wafer (D2W) stacking, wafer to wafer (W2W) stacking and other stacking methods. However, in the existing die to wafer (D2W) stacking structure, the chip and the integrated passive device (IPD) are independently packaged respectively, and the chip and the integrated passive device are interconnected through the wiring in the substrate (or interposer). The chip and the integrated passive device are arranged in a plane on the substrate (or interposer), and the interconnection distance between the chip and the integrated passive device is relatively long. In addition, in the chip packaging structure containing the chip stacking structure and the substrate (interposer), the chip and the integrated passive device each occupy the area of the substrate (or interposer), which may cause the chip packaging structure to have a large volume and a low integration level, and is not conducive to the miniaturization and lightweight development of the chip packaging structure. SUMMARY

[0006] The embodiments of the present application provide a chip stacking structure, a manufacturing method thereof, a chip packaging structure and an electronic device, which can shorten the interconnection distance between the chip and the integrated passive device, reduce the area overhead of the substrate (or interposer) in the chip packaging structure, and improve the integration level of the chip packaging structure.

[0007] In a first aspect, an embodiment of the present application provides a chip stacking structure. The chip stacking structure can include a first chip, at least one second chip, and a support structure integrated with an integrated passive device (IPD). The second chips are located between the first chip and the support structure. The first chip is electrically connected to the second chips. For example, the first chip and the second chips can be electrically connected by hybrid bonding, or the first chip and the second chips can be electrically connected by welding or other means. The support structure is connected to the second chips. For example, the support structure and the second chips can be connected by hybrid bonding or fusion bonding. Fusion bonding refers to bonding of two interfaces through a medium material, and hybrid bonding refers to bonding of two interfaces through a medium material and a metal material. The support structure is provided with an integrated passive device. The integrated passive device is electrically connected to the at least one second chip and / or the first chip. The integrated passive device can include passive devices such as resistors, capacitors, and inductors, and an interconnection structure connected to the passive devices. The passive devices can transmit signals, store energy, and filter signals. The integrated passive device can adjust power supply and signals, and provide the adjusted power supply and signals to the second chips and / or the first chip. In addition, the integrated passive device can shield electromagnetic interference to better protect the second chips and the first chip from external electromagnetic signals.

[0008] In related technologies, the support structure is a substrate without any function. For example, the support structure can be a silicon wafer without devices and functions. The substrate utilization rate of the support structure is low. In the chip stacking structure provided by the present application, the integrated passive device is integrated into the support structure. On the one hand, the integrated passive device, the second chips, and the first chip can be stacked in the vertical direction (perpendicular to the surface of the first chip). The interconnection distance between the second chips and / or the first chip and the integrated passive device can be greatly reduced. The second chips and / or the first chip and the integrated passive device do not need to be interconnected through a substrate (or an intermediate board), thereby reducing the area overhead of the substrate (or the intermediate board). In turn, the volume of the chip packaging structure including the chip stacking structure and the substrate (or the intermediate board) can be reduced, the integration of the chip packaging structure can be improved, and the cost of the chip packaging can be reduced. On the other hand, the support structure provided by the present application can have a device function, and the internal structure of the chip stacking structure can be reasonably utilized. In addition, the support structure is generally a silicon wafer, and the heat dissipation efficiency of silicon material is high. Therefore, the support structure can also have good heat dissipation effect, and can also have the functions of heat equalization and heat dissipation enhancement.

[0009] In the embodiments of the present application, the second chip can be an unpackaged die, and the second chip can be a chip with various functions such as computing and storage. The chip stacking structure in the embodiments of the present application can include one or more second chips, and the number of second chips can be set according to actual needs in specific settings. When the chip stacking structure includes more second chips, the specific implementation of other second chips can be implemented with reference to the description of the present application. The first chip can be a wafer or a part obtained by cutting a wafer. For example, the first chip can include a semiconductor material such as silicon or silicon carbide, and the first chip can be a chip with various functions such as computing and storage. The second chip and the first chip are connected by hybrid bonding, that is, the second chip and the first chip are stacked by die-to-wafer hybrid bonding (D2W HB). The support structure can be a wafer or a part obtained by cutting a wafer. For example, the support structure can include a semiconductor material such as silicon or silicon carbide. The support structure and the second chip can be connected by hybrid bonding or fusion bonding.

[0010] In the embodiments of the present application, the support structure has a relatively large thickness, which can increase the thickness of the entire chip stacking structure. Therefore, the support structure can function as a heat equalizer. When the chip stacking structure of the present application is applied to an electronic device, a heat sink can be arranged on the side of the support structure away from the first chip. The support structure can provide a heat conduction path between each second chip and the heat sink. In addition, the first chip can have a first surface and a second surface arranged opposite to each other. During the manufacturing process, at least one second chip is mounted on the first surface of the first chip, and the support structure is bonded to the side of each second chip away from the first chip. After the bonding of each second chip and the bonding of the support structure are completed, in some cases, the second surface of the first chip can be thinned and subjected to subsequent processes. The support structure can serve as a structural support for the first chip during the thinning and subsequent processes of the first chip.

[0011] In a possible implementation, the support structure can include a first substrate and a first interconnection layer located on the side of the first substrate close to the first chip. For example, the first substrate can include a semiconductor material such as silicon or silicon carbide. The integrated passive device is located on the first substrate close to the first interconnection layer. The integrated passive device is electrically connected to at least one second chip through the first interconnection layer; and / or, the integrated passive device is electrically connected to the first chip through the first interconnection layer. In the embodiments of the present application, the integrated passive device is arranged in the first substrate close to the first interconnection layer, which can shorten the distance between the integrated passive device and the second chip (and / or the first chip) in the vertical direction, making it easier to interconnect the integrated passive device and the second chip (and / or the first chip), thereby simplifying the interconnection structure in the first interconnection layer.

[0012] In the embodiments of the present application, the first interconnection layer and the second chip (and / or the first chip) can be interconnected in various ways. The ways of interconnecting the first interconnection layer and the second chip are described in detail below.

[0013] Way one:

[0014] In some embodiments of the present application, the first interconnection layer is provided with the first connecting end on the surface close to the first chip. The second chip can include a second substrate and a second interconnection layer, and the second interconnection layer is located on the side of the second substrate close to the first chip. That is, the second chip can be flip-chip mounted on the first chip. Of course, in some cases, the second chip can also be surface mounted on the first chip, and the mounting way of the second chip is not limited here. The second substrate can include a semiconductor material such as silicon or silicon carbide, for example, the second substrate can be a silicon wafer. The first conductive via is provided in the second chip, the first conductive via penetrates from the surface of the second substrate close to the support structure to the inside of the second interconnection layer, and the first conductive via is electrically connected with the second interconnection layer. In specific implementation, the second substrate can include silicon material, the first conductive via can be a through silicon via (TSV), and the first conductive via can include metal material such as copper or tungsten. The first connecting end is electrically connected with the end of the first conductive via close to the support structure. By providing the first conductive via in the second chip, the first conductive via can connect the second interconnection layer to the surface of the second substrate close to the support structure, so that the interconnection distance between the second chip and the first interconnection layer is short.

[0015] In specific implementation, the first interconnection layer is provided with the first dielectric film on the side close to the second chip, and the first connecting end is exposed through the via in the first dielectric film. The second chip is provided with the second dielectric film on the side close to the support structure, and the end of the first conductive via is exposed through the via in the second dielectric film. The second dielectric film on the surface of the second chip is bonded with the first dielectric film on the surface of the support structure, and the first connecting end is bonded with the end of the first conductive via, so that the second chip and the support structure are hybrid bonded.

[0016] Way two:

[0017] In some embodiments of the present application, the first interconnection layer is provided with the first connecting end on the surface close to the first chip. The second chip can include a second substrate and a second interconnection layer, and the second interconnection layer is located on the side of the second substrate close to the first chip. That is, the second chip can be flip-chip mounted on the first chip. Of course, in some cases, the second chip can also be surface mounted on the first chip, and the mounting way of the second chip is not limited here.

[0018] The chip stacking structure can further include a dielectric layer between the first chip and the support structure, the dielectric layer being filled in a position between the first chip and the support structure except for the second chips. Exemplarily, the dielectric layer can include an inorganic dielectric material such as silicon oxide. The dielectric layer is provided with a conductive through dielectric via (TDV). The TDV is electrically connected to the first connection end at one end close to the support structure, and is electrically connected to the second interconnection layer and / or the first chip at the other end. In a specific arrangement, the TDV can be directly connected in contact with the first connection end, or the TDV can be connected to the first connection end through an interconnection line. The TDV can be connected to the second interconnection layer and / or the first chip through an interconnection line. In the embodiments of the present application, the TDV is formed by punching the dielectric layer, and the first connection end is electrically connected to the second interconnection layer through the TDV. Compared with the above-mentioned mode one, mode two does not need to punch the second chip, can simplify the process flow of the second chip, improve the active area ratio of the second chip, and thus reduce the cost.

[0019] In a specific arrangement, the first interconnection layer is provided with a first dielectric film on the side close to the first chip, and the first connection end is exposed through a via in the first dielectric film. The second chip is provided with a second dielectric film on the side close to the support structure, and the TDV passes through the second dielectric film to be bonded to the first connection end. Moreover, the second dielectric film on the surface of the second chip is bonded to the first dielectric film on the surface of the support structure, so that the support structure is mixedly bonded to the lower die and wafer stacking structure (the stacking structure composed of the second chip and the first chip).

[0020] Mode three:

[0021] In some other embodiments of the present application, the first interconnection layer is provided with the first connection end on the surface close to the first chip, and the second chip can include a second substrate and a second interconnection layer, the second interconnection layer being located on the side of the second substrate close to the first chip. That is, the second chip can be flip-chip mounted on the first chip. Of course, in some cases, the second chip can also be surface-mounted on the first chip, and the mounting mode of the second chip is not limited here.

[0022] The chip stacking structure can further include a bridge chip between the first chip and the support structure. The bridge chip is provided with a second conductive via penetrating through the bridge chip. One end of the second conductive via close to the side of the support structure is electrically connected with the first connection end, and the other end is electrically connected with the second interconnection layer and / or the first chip. In a specific implementation, one or more second conductive vias can be provided in the bridge chip, and the number of the second conductive vias in the bridge chip can be set according to actual needs, which is not limited herein. The bridge chip and the second chip are arranged in a horizontal direction (parallel to the surface of the first chip). The bridge chip can be arranged around the second chip, so that the distance between the bridge chip and the second chip is relatively short. In a specific arrangement, the second conductive via can be connected with the first connection end through an interconnection line, and the second conductive via can be connected with the second interconnection layer and / or the first chip through an interconnection line. In a possible implementation, the substrate of the bridge chip includes silicon material, and the second conductive via can be a silicon via. Unlike the structure of the second chip, the bridge chip can not be provided with an interconnection layer. At least one second conductive via is formed in the substrate by punching, so as to obtain the bridge chip. That is, the bridge chip does not have processing functions such as calculation and storage, and the bridge chip is used to electrically connect the second interconnection layer of the second chip with the first connection end. In the embodiment of the present application, the first connection end and the second interconnection layer are electrically connected through the bridge chip. Compared with the above-mentioned mode one, mode three does not need to punch the second chip, can simplify the process flow of the second chip, improve the active area ratio of the second chip, and thus reduce the cost. In the embodiment of the present application, the chip stacking structure can include one or more bridge chips, and the number and position of the bridge chips can be set according to actual needs, which is not limited herein.

[0023] In a specific arrangement, the first interconnection layer is provided with a first dielectric film on the side close to the second chip, and the first connection end is exposed through a via in the first dielectric film. The second chip is provided with a second dielectric film on the side close to the support structure, and the second conductive via in the bridge chip is electrically connected with the first connection end through an interconnection line in the second dielectric film. Furthermore, the second dielectric film on the surface of the second chip is bonded with the first dielectric film on the surface of the support structure, so as to mix the support structure with the lower die and wafer stacking structure (the stacking structure composed of the second chip and the first chip) by bonding.

[0024] In a possible implementation, the chip stacking structure can include at least two second chips, and adjacent two second chips can be electrically connected with different second conductive vias in the bridge chip, and the bridge chip can be located between the adjacent two second chips. In this way, the distance between the bridge chip and the adjacent two second chips can be relatively short, and the interconnection distance between the second chip and the first interconnection layer can be shortened.

[0025] The above introduces several interconnection modes of the first interconnection layer and the second chip and / or the first chip. In a specific implementation, the above mode 1 to mode 3 can be combined with each other. For example, mode 1 and mode 2 can be combined, and the dielectric via is arranged in the dielectric layer on the basis of the first conductive via arranged in the second chip. Of course, in some cases, the first interconnection layer and the second chip and / or the first chip can also adopt other interconnection modes, and can be reasonably arranged according to the interconnection requirement.

[0026] In a possible implementation, the first chip can include a third substrate and a third interconnection layer, and the third interconnection layer is located on a side of the third substrate close to the support structure. Exemplarily, the third substrate can include a semiconductor material such as silicon or silicon carbide. The surface of the first chip close to the support structure is provided with a second connection end, that is, the third interconnection layer is provided with the second connection end on the surface close to the second chip, the second interconnection layer is provided with a third connection end on the surface close to the first chip, and the second connection end is electrically connected with the third connection end, so as to realize the interconnection between the second chip and the first chip. In a specific arrangement, the side of the third interconnection layer close to the second chip is provided with a third dielectric film, and the second connection end is exposed through a via in the third dielectric film. The surface of the second chip close to the first chip is provided with a fourth dielectric film, and the third connection end is exposed through a via in the fourth dielectric film. The fourth dielectric film on the surface of the second chip is bonded with the third dielectric film on the surface of the third interconnection layer. Thus, the second chip and the first chip are hybrid bonded. In the embodiment of the present application, the third interconnection layer is arranged on the side of the third substrate close to the support structure, so that the interconnection distance between the third interconnection layer and the second chip is relatively short. Of course, in some cases, the third interconnection layer in the first chip can also be located on the side of the third substrate away from the support structure, which is not limited here.

[0027] In addition, the side of the first chip away from the support structure can also be provided with a fourth connection end, and the fourth connection end is electrically connected with the third interconnection layer. When the chip stacking structure in the embodiment of the present application is applied to an electronic device, the chip stacking structure can be electrically connected with a circuit board through the fourth connection end.

[0028] In a second aspect, the embodiment of the present application further provides a manufacturing method of the chip stacking structure. The manufacturing method of the chip stacking structure provided by the embodiment of the present application can include:

[0029] Step one, placing at least one second chip on the first chip, and electrically connecting each second chip with the first chip; wherein the second chip is a diced die, and the second chip can be a chip with various functions such as computing and storage. The first chip can be a wafer or a part of a wafer diced, and the first chip can include semiconductor materials such as silicon and silicon carbide. After bonding the second chip with the first chip, a die and wafer (D2W) stacked structure can be obtained.

[0030] Step two, placing a support structure provided with integrated passive devices on a side of each second chip away from the first chip, and connecting the support structure with each second chip; wherein the integrated passive devices are electrically connected with at least one second chip; and / or, the integrated passive devices are electrically connected with the first chip. The support structure can be a wafer or a part of a wafer diced, and the support structure can include semiconductor materials such as silicon and silicon carbide. The integrated passive devices can include passive devices such as resistors, capacitors, and inductors, and an interconnection structure connected with the passive devices. The passive devices can function to transmit signals, store energy, and filter signals. The integrated passive devices can adjust power supply and signals, and provide the adjusted power supply and signals to the second chip. In addition, the integrated passive devices can also function to shield electromagnetic interference, so that the second chip or the first chip can achieve better electromagnetic protection and avoid interference of electromagnetic signals on the second chip and the first chip.

[0031] In the chip stacking structure manufacturing method provided by the embodiments of the present application, by integrating the integrated passive devices into the support structure, on the one hand, the integrated passive devices, the second chip, and the first chip can be stacked in the vertical direction (perpendicular to the surface of the first chip), which can greatly reduce the interconnection distance between the second chip and / or the first chip and the integrated passive devices, and the second chip and / or the first chip and the integrated passive devices do not need to be interconnected through a substrate (or an intermediate board), thereby reducing the area overhead of the substrate (or the intermediate board) and the manufacturing cost of the chip stacking structure. Furthermore, the volume of a chip packaging structure containing the chip stacking structure and the substrate (or the intermediate board) can be reduced, and the integration of the chip packaging structure can be improved. On the other hand, the substrate utilization rate of the support structure can be improved, and the internal structure of the chip stacking structure can be reasonably utilized. In addition, the support structure is generally a silicon wafer, and the heat dissipation efficiency of silicon material is relatively high, so the support structure can have good heat dissipation effect, and thus the support structure can also function to evenly heat and strengthen heat dissipation.

[0032] In addition, after the step one and before the step two, the manufacturing method in the embodiments of the present application can further include: filling a medium material in the gap between the second chips to form a medium layer. For example, the medium layer can be made of inorganic medium material such as silicon oxide. In some cases, after the medium layer is made, the back side (the side of the second chip facing away from the first chip) of the second chip can be planarized and thinned.

[0033] Based on the above description of the chip stacking structure, the first interconnection layer in the support structure can have multiple interconnection modes with the second chip and / or the first chip. The manufacturing method of the chip stacking structure with the above modes one to three will be described in detail below.

[0034] In some embodiments of the present application, when the chip stacking structure has the structure of the above mode one, the manufacturing method in the embodiments of the present application can specifically include:

[0035] The first chip can include a third substrate and a third interconnection layer. For example, the third substrate can include semiconductor material such as silicon or silicon carbide. The second chip can include a second substrate and a second interconnection layer. The above step one can specifically include: placing the second chip on the first chip with the surface of the third interconnection layer side up, and making the second interconnection layer of the second chip face the third interconnection layer. The second chip and the first chip are hybrid bonded to make the second interconnection layer and the third interconnection layer electrically connected. In the embodiments of the present application, the second chip can be flip-chip mounted on the first chip. In some cases, the second chip can also be surface mounted on the first chip, which is not limited here. In addition, the third interconnection layer in the first chip is located on the side of the third substrate close to the second chip, which can make the interconnection distance between the third interconnection layer and the second chip shorter. Of course, in some cases, the third interconnection layer in the first chip can also be located on the side of the third substrate away from the second chip, which is not limited here.

[0036] In a specific arrangement, the third interconnection layer is provided with a second connection end on the surface close to the second chip, and the second interconnection layer is provided with a third connection end on the surface close to the first chip. The second connection end and the third connection end are bonded to make the second chip and the first chip interconnected. In a specific arrangement, the third interconnection layer is provided with a third medium film on the side close to the second chip, and the second connection end is exposed through a via hole in the third medium film. The second chip is provided with a fourth medium film on the surface close to the first chip, and the third connection end is exposed through a via hole in the fourth medium film. The fourth medium film on the surface of the second chip and the third medium film on the surface of the third interconnection layer are bonded. Thus, the second chip and the first chip are hybrid bonded.

[0037] After step one and before step two, the manufacturing method in the embodiments of the present applicationapplicationalso include: perforating the second chip and filling the formed hole with conductive material, for example, using thin film deposition, electroplating and other processes to fill metal material to form a first conductive via penetrating from the surface of the second substrate away from the first chip to the inside of the second interconnection layer; wherein the first conductive via is electrically connected with the second interconnection layer. In order to facilitate bonding with the support structure, the first conductive viaapplicationprotrude from the surface of the second substrate away from the first chip.

[0038] Alternatively, the first conductive via has been provided in the second chip before the second chip is bonded with the first chip. After step one and before step two, the manufacturing method in the embodiments of the present applicationapplicationinclude: thinning the surface of the second substrate away from the first chip to expose the first conductive via.

[0039] Then, a second dielectric film is formed on the second chip and the dielectric layer, and the end of the first conductive via is exposed through the via in the second dielectric film.

[0040] After that, a support structure is provided, whichapplicationinclude: a first substrate and a first interconnection layer, and the first interconnection layer is provided with a first connecting end on the surface away from the first substrate. Step twoapplicationin particular include: placing the support structure on the second chip, and the first interconnection layer of the support structure faces the second chip. The support structure and each second chip are bonded, so that the first connecting end is electrically connected with the first conductive via. In the embodiments of the present application, by providing the first conductive via in the second chip, the first conductive viaapplicationconnect the second interconnection layer to the surface of the second substrate close to the support structure, so that the interconnection distance between the second chip and the first interconnection layer is short.

[0041] In addition, the support structureapplicationinclude a first dielectric film and a first connecting end, the first dielectric film is located on the side of the first interconnection layer close to the second chip, the first connecting end is electrically connected with the first interconnection layer, and the first connecting end is exposed through the via in the first dielectric film. In the bonding process in step two, the second dielectric film on the surface of the second chip is bonded with the first dielectric film on the surface of the support structure, and the first connecting end is bonded with the end of the first conductive via, so that the second chip and the support structure are mixedly bonded.

[0042] After step two, the manufacturing method in the embodiments of the present application can further include: thinning the surface of the first chip away from the second chip by using the support structure as a structure support. In addition, the third substrate can be punched, and the conductive material can be filled in the formed hole to form a conductive via penetrating through the third substrate, which can be electrically connected with the third interconnection layer. Then, the fourth connection end can be formed on the first chip, and the fourth connection end can be electrically connected with the third interconnection layer through the conductive via. During the thinning process of the first chip, the support structure can increase the total thickness of the entire chip stack structure, and can be used as a structure support for the thinning and subsequent processes of the first chip. Of course, in some cases, the thinning process of the first chip can be omitted, for example, the thickness of the first chip is thin enough and does not need to be thinned, or the third interconnection layer of the first chip is located on the side of the third substrate away from the support structure, and the first chip does not need to be thinned.

[0043] In some other embodiments of the present application, when the chip stack structure has the structure of the above-mentioned mode two, the manufacturing method in the embodiments of the present application can specifically include:

[0044] At least one second chip is placed on the first chip, and each second chip is electrically connected with the first chip. The specific connection mode of the second chip with the first chip can be referred to the above-mentioned related description, and the repeated parts will not be described herein.

[0045] In step two, the gap between each second chip is filled with a medium material to form a medium layer. For example, the medium layer can be made of inorganic medium material such as silicon oxide. In some cases, after the medium layer is made, the back side of the second chip (the side of the second chip away from the first chip) can be planarized and thinned.

[0046] After the medium layer is formed, before step two, the manufacturing method in the embodiments of the present application can further include: punching the medium layer, and filling the conductive material in the formed hole, for example, the metal material can be filled by using the thin film deposition, electroplating and other processes to form a medium via penetrating through the medium layer, and the medium via is electrically connected with the second interconnection layer and / or the first chip.

[0047] In some cases, after the medium layer is formed, a second medium film can be formed on the medium layer. After the second medium film is formed, the second medium film and the medium layer are punched, and the conductive material is filled in the formed hole to form a medium via penetrating through the second medium film and the medium layer.

[0048] Then, a support structure is provided, which can include a first substrate and a first interconnection layer, and the first interconnection layer is provided with a first connecting end on a surface facing away from the first substrate. The step two can specifically include: placing the support structure on the second chip, and the first interconnection layer of the support structure faces the second chip. The support structure and the second chip are bonded, so that the first connecting end is electrically connected with the medium via hole. In the embodiment of the application, the first connecting end can be electrically connected with the second interconnection layer and / or the first chip through the medium via hole by forming the medium via hole in the medium layer, without punching and metal filling on the second chip, simplifying the process flow of the second chip, improving the active area ratio of the second chip, and thus reducing the cost.

[0049] In addition, the support structure can further include a first dielectric film and a first connecting end, the first dielectric film is located on the side of the first interconnection layer close to the second chip, the first connecting end is electrically connected with the first interconnection layer, and the first connecting end is exposed through a via hole in the first dielectric film. In the bonding process in the step two, the second dielectric film on the surface of the second chip is bonded with the first dielectric film on the surface of the support structure, and the first connecting end is bonded with the end of the medium via hole, so that the support structure is mixedly bonded with the lower grain and wafer stacking structure (the stacking structure composed of the second chip and the first chip).

[0050] After the step two, the manufacturing method in the embodiment of the application can further include: using the support structure as a structure support to perform a thinning process on the surface of the first chip away from the second chip. In addition, the third substrate can be punched, and a conductive material can be filled in the formed hole to form a conductive via hole penetrating through the third substrate, which can be electrically connected with the third interconnection layer. Then, a fourth connecting end is formed on the first chip, which can be electrically connected with the third interconnection layer through the conductive via hole. In the process of thinning the first chip, the thickness of the support structure is relatively thick, and the support structure can increase the total thickness of the entire chip stacking structure, and can be used as a structure support for thinning the first chip. Of course, in some cases, the process of thinning the first chip can be omitted, for example, the thickness of the first chip is relatively thin, and the first chip does not need to be thinned, and for another example, when the third interconnection layer of the first chip is located on the side of the third substrate away from the support structure, the first chip does not need to be thinned.

[0051] In some other embodiments of the application, when the chip stacking structure has the structure of the above-mentioned mode three, the manufacturing method in the embodiment of the application can specifically include:

[0052] The bridge chip is provided with a second conductive via hole penetrating through the bridge chip. In specific implementation, one or more second conductive via holes can be arranged in the bridge chip, and the number of the second conductive via holes in the bridge chip can be set according to actual needs, which is not limited herein. In step one, the second chips and the bridge chip are placed on the first chip, that is, the bridge chip is placed on the first chip except for the second chips. The second chips and the first chip are electrically connected, and the bridge chip and the first chip are electrically connected. In specific implementation, the second chip and the bridge chip can be electrically connected to the first chip in a hybrid bonding manner. The second chip can be bonded first, and then the bridge chip is bonded, or the bridge chip can be bonded first, and then the second chip is bonded, and the bonding sequence of the second chip and the bridge chip is not limited herein. The specific bonding manner of the second chip and the first chip can be referred to the related description above, and details are not described herein. In the embodiments of the present application, the chip stacking structure can include one or more bridge chips, and the number and position of the bridge chips can be set according to actual needs, which is not limited herein.

[0053] In step two, the medium material is filled in the area on the first chip except for the second chips and the bridge chip to form a medium layer. In some cases, the surface of the medium layer can also be planarized and thinned. Then, a second medium film is formed on the second chips and the bridge chip, and an interconnection line for leading out the second conductive via hole is formed, and at least a part of the interconnection line can be exposed on the surface of the second medium film.

[0054] Then, a support structure is provided, which can include a first substrate and a first interconnection layer provided with a first connection end on the surface away from the first substrate. Step two can specifically include placing the support structure on the second chips, and the first interconnection layer of the support structure faces the second chips. The support structure and the second chips are bonded, so that the first connection end is electrically connected to the second conductive via hole, so that the first connection end is electrically connected to the second interconnection layer and / or the first chip through the second conductive via hole. In the embodiments of the present application, by installing the bridge chip on the first chip, the first connection end can be electrically connected to the second interconnection layer and / or the first chip, without the need to punch the second chip, which simplifies the process flow of the second chip, improves the active area ratio of the second chip, and thus reduces the cost.

[0055] In addition, the support structure can further include a first dielectric film and a first connecting end. The first dielectric film is located on the side of the first interconnection layer close to the second chip. The first connecting end is electrically connected to the first interconnection layer, and the first connecting end is exposed through a via in the first dielectric film. In the bonding process in step two, the second dielectric film on the surface of the second chip is bonded to the first dielectric film on the surface of the support structure, and the first connecting end is bonded to the second conductive via, so that the support structure is hybrid-bonded to the underlying die and wafer stack structure (the stack structure formed by the second chip and the first chip).

[0056] After step two, the manufacturing method in the embodiments of the present application can further include: using the support structure as a structure support to perform a thinning process on the surface of the first chip away from the second chip. In addition, the third substrate can be perforated, and a conductive material can be filled in the formed hole to form a conductive via penetrating through the third substrate. The conductive via can be electrically connected to the third interconnection layer. Then, a fourth connecting end can be formed on the first chip. The fourth connecting end can be electrically connected to the third interconnection layer through the conductive via. In the process of thinning the first chip, the support structure can increase the total thickness of the entire chip stack structure, and can serve as a structure support for thinning the first chip. Of course, in some cases, the process of thinning the first chip can be omitted. For example, the thickness of the first chip is thin enough and does not need to be thinned. For another example, when the third interconnection layer of the first chip is located on the side of the third substrate away from the support structure, the first chip does not need to be thinned.

[0057] The manufacturing method of the chip stack structure with the above-mentioned mode one to mode three is introduced above. In specific implementation, the above-mentioned mode one to mode three can be combined with each other, or the first interconnection layer and the second chip can use other interconnection modes. In this case, the manufacturing method can be implemented by referring to the above-mentioned manufacturing method, and the repeated parts will not be described again. In addition, in the above description, the manufacturing method of the chip stack structure is introduced by taking the chip stack structure including the second chip as an example. When the chip stack structure includes multiple chips, the manufacturing process of other chips can refer to the manufacturing process of the second chip, and the repeated parts will not be described again.

[0058] In a third aspect, the embodiments of the present application further provide a chip packaging structure. The chip packaging structure provided by the embodiments of the present application can include any chip stack structure in the above-mentioned first aspect and a substrate. The chip stack structure can be fixed on the substrate. In addition, in some cases, the chip packaging structure in the embodiments of the present application can further include an interposer. Since the chip stack structure in the above-mentioned first aspect can shorten the interconnection distance between the chip and the integrated passive device, the area overhead of the substrate (or the interposer) in the chip packaging structure can be reduced, so that the chip packaging structure has a smaller volume and a higher integration level.

[0059] In a fourth aspect, the embodiments of the present application further provide an electronic device. The electronic device provided by the embodiments of the present application can include the chip packaging structure and the circuit board in the third aspect, and the chip packaging structure is electrically connected with the circuit board. Since the chip stacking structure in the first aspect can shorten the interconnection distance between the chip and the integrated passive device, and can reduce the area overhead of the substrate (or the interposer) in the chip packaging structure, the volume of the chip packaging structure is small and the integration degree is high. Therefore, the volume of the electronic device including the chip packaging structure is also small and the integration degree is also high. BRIEF DESCRIPTION OF DRAWINGS

[0060] FIG. 1 is a structural schematic diagram of an electronic device provided by the embodiments of the present application;

[0061] FIG. 2 is a structural schematic diagram of a chip stacking structure provided by the embodiments of the present application;

[0062] FIG. 3 is another structural schematic diagram of a chip stacking structure provided by the embodiments of the present application;

[0063] FIG. 4 is another structural schematic diagram of a chip stacking structure provided by the embodiments of the present application;

[0064] FIG. 5 is a flowchart of a manufacturing method of a chip stacking structure provided by the embodiments of the present application;

[0065] FIGS. 6 to 8 are structural schematic diagrams corresponding to respective steps in the manufacturing method provided by the embodiments of the present application.

[0066] Reference signs: 100-electronic device; 101-chip packaging structure; 102-circuit board; 11-first chip; 111-third substrate; 112-third interconnection layer; 12-second chip; 121-second substrate; 122-second interconnection layer; 13-supporting structure; 131-first substrate; 132-first interconnection layer; 14-integrated passive device; 15-medium layer; 151-medium via hole; 161-first medium film; 162-second medium film; 163-third medium film; 164-fourth medium film; 17-bridge chip; T1-first conductive via hole; T2-second conductive via hole; Q1-first connection end; Q2-second connection end; Q3-third connection end; Q4-fourth connection end. DETAILED DESCRIPTION

[0067] In order to shorten the interconnection distance between the chip and the integrated passive device, reduce the area overhead of the substrate (or the interposer) in the chip packaging structure, and improve the integration of the chip packaging structure, embodiments of the present application provide a chip stacking structure, a manufacturing method thereof, a chip packaging structure, and an electronic device. The chip stacking structure in the embodiments of the present application can be applied to various types of electronic devices, for example, can be applied to terminal devices such as mobile phones, tablet computers, notebook computers, smart wearable devices, etc., or can also be applied to other electronic devices such as smart televisions, smart door locks, smart home appliances, etc.

[0068] In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be described in further detail below with reference to the drawings.

[0069] It should be noted that the drawings of the present application are only used to illustrate the relative position relationship and do not represent the true proportion. The same reference numerals in the drawings of the present application represent the same or similar structures, and thus repeated description thereof will be omitted.

[0070] The words expressing position and direction described in the present application, for example, the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. are all described based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and thus cannot be understood as indicating or implying that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus cannot be understood as limiting the present application. Changes can also be made as needed, and the changes made are all within the scope of protection of the present application. In addition, the terms "first" and "second" are only for descriptive purposes and cannot be understood as indicating or implying relative importance.

[0071] FIG. 1 is a structural schematic diagram of an electronic device provided by embodiments of the present application. The left part of FIG. 1 is a top view schematic diagram of the electronic device, and the right part of FIG. 1 is a sectional view schematic diagram of the top view of the electronic device at the virtual line AA'. As shown in FIG. 1, the electronic device 100 provided by embodiments of the present application can include a chip packaging structure 101 and a circuit board 102, and the chip packaging structure 101 is electrically connected to the circuit board 102. In FIG. 1, the electronic device 100 is taken as an example of a mobile phone, and when the electronic device 100 is another device, the positions, shapes, sizes, etc. of the chip packaging structure 101 and the circuit board 102 in the electronic device 100 can be reasonably set according to actual needs.

[0072] In the embodiments of the present application, the chip packaging structure can include a chip stack structure and a substrate, the chip stack structure can be fixed on the substrate, and in some cases, the chip packaging structure in the embodiments of the present application can further include an interposer. Since the chip stack structure in the embodiments of the present application can shorten the interconnection distance between the chip and the integrated passive device, and reduce the area overhead of the substrate (or the interposer), the chip packaging structure including the chip stack structure and the substrate (or the interposer) has a smaller volume and a higher integration. Thus, the electronic device including the chip packaging structure also has a smaller volume and a higher integration.

[0073] FIG. 2 is a structural schematic diagram of a chip stack structure provided by the embodiments of the present application. As shown in FIG. 2, the chip stack structure provided by the embodiments of the present application can include a first chip 11, at least one second chip 12, and a support structure 13. Each second chip 12 is located between the first chip 11 and the support structure 13. The first chip 11 is electrically connected to each second chip 12. For example, the first chip 11 and the second chip 12 can be electrically connected by hybrid bonding, or the first chip 11 and the second chip 12 can be electrically connected by welding or other means. The support structure 13 is connected to each second chip 12, for example, the support structure 13 and each second chip 12 can be connected by hybrid bonding or fusion bonding. The fusion bonding refers to the bonding of two interfaces through a medium material, and the hybrid bonding refers to the bonding of two interfaces through a medium material and a metal material. The support structure 13 is provided with an integrated passive device 14 (IPD), the integrated passive device 14 is electrically connected to at least one second chip 12; and / or, the integrated passive device 14 is electrically connected to the first chip 11. The integrated passive device 14 can include passive devices such as resistors, capacitors, inductors, and interconnection structures connected to the passive devices. The passive devices can play a role in transmitting signals, storing energy, and filtering signals. The integrated passive device 14 can adjust the power supply and signals, and provide the adjusted power supply and signals to at least one second chip 12 and / or the first chip 11. In addition, the integrated passive device 14 can also play a role in shielding electromagnetic interference, so that the second chip 12 or the first chip 11 can achieve better electromagnetic protection, and avoid interference of electromagnetic signals on the second chip 12 and the first chip 11.

[0074] In the related art, the support structure 13 is a substrate without any function, for example, the support structure 13 can be a silicon wafer, and the substrate utilization rate of the support structure 13 is low. In the chip stacking structure provided in the embodiments of the present application, the integrated passive device 14 is integrated into the support structure 13, on the one hand, the integrated passive device 14, the second chip 12 and the first chip 11 can be stacked in the vertical direction (perpendicular to the surface of the first chip 11), which can greatly reduce the interconnection distance between the second chip 12 and / or the first chip 11 and the integrated passive device 14, and the second chip 12 and / or the first chip 11 and the integrated passive device 14 do not need to be interconnected through a substrate (or an intermediate board), thereby reducing the area overhead of the substrate (or the intermediate board) and reducing the manufacturing cost of the chip stacking structure. Further, the volume of the chip packaging structure including the chip stacking structure and the substrate (or the intermediate board) can be reduced, and the integration of the chip packaging structure can be improved; on the other hand, the substrate utilization rate of the support structure 13 can be improved, and the internal structure of the chip stacking structure can be reasonably utilized. In addition, the support structure 13 is generally a silicon wafer, and the heat dissipation efficiency of silicon material is relatively high, so that the support structure 13 has good heat dissipation effect, and thus the support structure 13 can also play a role of heat equalization and heat dissipation enhancement.

[0075] In the embodiments of the present application, the second chip 12 is an unpackaged die, and the second chip 12 can be a chip with various functions such as computing and storage. The chip stacking structure in the embodiments of the present application can include one or more second chips, and in the drawings of the present application, two second chips 12 are taken as an example for illustration, and the number of second chips 12 can be set according to actual needs in specific settings. When the chip stacking structure includes one or more second chips 12, the implementation of other second chips 12 can refer to the description of the present application. The first chip 11 can be a wafer or a part obtained by cutting a wafer, and exemplarily, the first chip 11 can include semiconductor materials such as silicon and silicon carbide, and the first chip 11 can be a chip with various functions such as computing and storage. The second chip 12 and the first chip 11 can be connected by hybrid bonding, that is, the second chip 12 and the first chip 11 can be stacked by die and wafer hybrid bonding (D2W HB). The support structure 13 can be a wafer or a part obtained by cutting a wafer, and exemplarily, the support structure 13 can include semiconductor materials such as silicon and silicon carbide. The support structure 13 and the second chip 12 can be connected by hybrid bonding or fusion bonding.

[0076] In the embodiments of the present application, the support structure 13 has a relatively large thickness, which can increase the thickness of the whole chip stack structure. Therefore, the support structure 13 can serve as a heat equalizing structure. When the chip stack structure of the present application is applied to an electronic device, a heat sink can be arranged on the side of the support structure 13 away from the first chip 11, and the support structure 13 can provide a heat conduction path between each second chip 12 and the heat sink. In addition, the first chip 11 can have a first surface and a second surface arranged opposite to each other. During the manufacturing process, at least one second chip 12 is attached to the first surface of the first chip 11, and the support structure 13 is bonded to the side of each second chip 12 away from the first chip 11. After the bonding of each second chip 12 and the bonding of the support structure 13 are completed, in some cases, the surface of the first chip 11 away from the second chip 12 can be thinned, and the support structure 13 can serve as a structure support for the thinning of the first chip 11.

[0077] With continuous reference to FIG. 2, in a possible implementation, the support structure 13 can include a first substrate 131 and a first interconnection layer 132, and the first interconnection layer 132 is arranged on the side of the first substrate 131 close to the first chip 11. Exemplarily, the first substrate 131 can include a semiconductor material such as silicon or silicon carbide. The integrated passive device 14 is arranged on the side of the first substrate 131 close to the first interconnection layer 132. The integrated passive device 14 is electrically connected to the at least one second chip 12 through the first interconnection layer 132; and / or, the integrated passive device 14 is electrically connected to the first chip 11 through the first interconnection layer 132. In the embodiments of the present application, the integrated passive device 14 is arranged in the first substrate 131 close to the first interconnection layer 132, which can shorten the distance between the integrated passive device 14 and the second chip 12 (and / or the first chip 11) in the vertical direction, and make the integrated passive device 14 and the second chip 12 (and / or the first chip 11) more easily interconnected, thereby simplifying the interconnection structure in the first interconnection layer 132.

[0078] In the embodiments of the present application, the first interconnection layer 132 can be interconnected with the second chip 12 (and / or the first chip 11) in various ways. The interconnection ways between the first interconnection layer and the second chip are described in detail below with reference to the accompanying drawings.

[0079] Way one:

[0080] As shown in FIG. 2, in some embodiments of the present application, the first interconnection layer 132 is provided with the first connection end Q1 on the surface close to the first chip 11. The second chip 12 can include a second substrate 121 and a second interconnection layer 122 located on the side of the second substrate 121 close to the first chip 11. That is, the second chip 12 can be flip-chip mounted on the first chip 11. Of course, in some cases, the second chip 12 can also be surface mounted on the first chip 11, and the mounting mode of the second chip 12 is not limited here. The second substrate 121 can include a semiconductor material such as silicon or silicon carbide, for example, the second substrate 121 can be a silicon wafer. The second chip 12 is provided with a first conductive via T1 penetrating from the surface of the second substrate 121 close to the support structure 13 to the inside of the second interconnection layer 122, and the first conductive via T1 is electrically connected to the second interconnection layer 122. In specific implementation, the second substrate 121 can include a silicon material, the first conductive via T1 can be a through silicon via (TSV), and the first conductive via T1 can include a metal material such as copper or tungsten. The first connection end Q1 is electrically connected to the end of the first conductive via T1 close to the support structure 13. By providing the first conductive via T1 in the second chip 12, the first conductive via T1 can connect the second interconnection layer 122 to the surface of the second substrate 121 close to the support structure 13, and the interconnection distance between the second chip 12 and the first interconnection layer 132 can be shortened.

[0081] In specific implementation, the side of the first interconnection layer 132 close to the first chip 11 is provided with a first dielectric film 161, and the first connection end Q1 is exposed through a via in the first dielectric film 161. The side of the second chip 12 close to the support structure 13 is provided with a second dielectric film 162, and the end of the first conductive via T1 is exposed through a via in the second dielectric film 162. The second dielectric film 162 on the surface of the second chip 12 is bonded to the first dielectric film 161 on the surface of the support structure 13, and the first connection end Q1 is bonded to the end of the first conductive via T1, so that the second chip 12 and the support structure 13 are hybrid bonded.

[0082] Method two:

[0083] FIG. 3 is another structural schematic diagram of the chip stacking structure provided by the embodiments of the present application. As shown in FIG. 3, in some other embodiments of the present application, the first interconnection layer 132 is provided with a first connecting end Q1 near the surface of the first chip 11. The second chip 12 can include a second substrate 121 and a second interconnection layer 122, and the second interconnection layer 122 is located on the side of the second substrate 121 close to the first chip 11. That is, the second chip 12 can be flip-chip mounted on the first chip 11. Of course, in some cases, the second chip 12 can also be surface mounted on the first chip 11, and the mounting mode of the second chip 12 is not limited here.

[0084] The chip stacking structure can further include a dielectric layer 15 between the first chip 11 and the support structure 13, and the dielectric layer 15 fills the space between the first chip 11 and the support structure 13 except for each second chip 12. Exemplarily, the dielectric layer 15 can include inorganic dielectric materials such as silicon oxide. The dielectric layer 15 is provided with a conductive medium through hole 151 (TDV). One end of the medium through hole 151 close to the support structure 13 is electrically connected with the first connecting end Q1, and the other end is electrically connected with the second interconnection layer 122 and / or the first chip 11. In a specific arrangement, the medium through hole 151 can be directly connected in contact with the first connecting end Q1, or the medium through hole 151 can be connected with the first connecting end Q1 through an interconnection line. The medium through hole 151 can be connected with the second interconnection layer 122 and / or the first chip 11 through an interconnection line. In the embodiments of the present application, the medium through hole 151 is formed in the dielectric layer 15 by punching the dielectric layer 15, and the first connecting end Q1 is electrically connected with the second interconnection layer 122 through the medium through hole 151. Compared with the above-mentioned mode one, the mode two does not need to punch the second chip 12, which can simplify the process flow of the second chip, improve the active area ratio of the second chip, and thus reduce the cost.

[0085] In a specific arrangement, the side of the first interconnection layer 132 close to the first chip 11 is provided with a first dielectric film 161, and the first connecting end Q1 is exposed through a through hole in the first dielectric film 161. The side of the second chip 12 close to the support structure 13 is provided with a second dielectric film 162, and the medium through hole 151 is bonded with the first connecting end Q1 through the second dielectric film 162. Moreover, the second dielectric film 162 on the surface of the second chip 12 is bonded with the first dielectric film 161 on the surface of the support structure 13, so as to make the support structure 13 mixedly bonded with the lower die and wafer stacking structure (the stacking structure composed of the second chip 12 and the first chip 11).

[0086] Mode three:

[0087] FIG. 4 is another structural schematic diagram of the chip stacking structure provided by the embodiments of the present application. As shown in FIG. 4, in some other embodiments of the present application, the first interconnection layer 132 is provided with the first connection end Q1 close to the surface of the first chip 11, and the second chip 12 can include: a second substrate 121 and a second interconnection layer 122, and the second interconnection layer 122 is located on the side of the second substrate 121 close to the first chip 11. That is, the second chip 12 can be flip-chip mounted on the first chip 11. Of course, in some cases, the second chip 12 can also be surface mounted on the first chip 11, and the mounting mode of the second chip 12 is not limited here.

[0088] The chip stacking structure can further include a bridge chip 17 located between the first chip 11 and the support structure 13. The bridge chip 17 is provided with a second conductive via T2 penetrating through the bridge chip 17. One end of the second conductive via T2 close to the support structure 13 is electrically connected with the first connection end Q1, and the other end is electrically connected with the second interconnection layer 122 and / or the first chip 11. In a specific implementation, one or more second conductive vias T2 can be provided in the bridge chip 17, and the number of the second conductive vias T2 in the bridge chip 17 can be set according to actual needs, which is not limited here. The bridge chip 17 and the second chip 12 are arranged in a horizontal direction (parallel to the surface of the first chip 11), and the bridge chip 17 can be arranged around the second chip 12 so that the distance between the bridge chip 17 and the second chip 12 is relatively close. In a specific arrangement, the second conductive via T2 can be connected with the first connection end Q1 through an interconnection line, and the second conductive via T2 can be connected with the second interconnection layer 122 and / or the first chip 11 through an interconnection line. In a possible implementation, the substrate of the bridge chip 17 includes silicon material, and the second conductive via T2 can be a silicon via. Unlike the structure of the second chip 12, the bridge chip 17 can not be provided with an interconnection layer, and at least one second conductive via T2 can be formed in the substrate by punching the substrate to obtain the bridge chip 17. That is, the bridge chip 17 does not have processing functions such as calculation and storage, and the bridge chip 17 is used to electrically connect the second interconnection layer 122 of the second chip 12 with the first connection end Q1. In the embodiments of the present application, the first connection end Q1 and the second interconnection layer 122 are electrically connected through the bridge chip 17, and compared with the above-mentioned mode one, the mode three does not need to punch the second chip 12, which can simplify the process flow of the second chip, improve the active area ratio of the second chip 12, and thus reduce the cost. In the embodiments of the present application, the chip stacking structure can include one or more bridge chips 17, and the number and position of the bridge chips 17 can be set according to actual needs, which is not limited here.

[0089] In a specific arrangement, the first interconnection layer 132 is provided with a first dielectric film 161 on the side close to the second chip 12, and the first connection end Q1 is exposed through a via hole in the first dielectric film 161. The second chip 12 is provided with a second dielectric film 162 on the side close to the support structure 13, and the second conductive via hole T2 in the bridge chip 17 is electrically connected with the first connection end Q1 through an interconnection line in the second dielectric film 162. Moreover, the second dielectric film 162 on the surface of the second chip 12 is bonded with the first dielectric film 161 on the surface of the support structure 13, so as to mix-bond the support structure 13 with the lower grain and wafer stacking structure (the stacking structure composed of the second chip 12 and the first chip 11).

[0090] With continuous reference to FIG. 4, in a possible implementation, the chip stacking structure can include at least two second chips 12, and adjacent two second chips 12 can be electrically connected with different second conductive via holes T2 in the bridge chip 17, and the bridge chip 17 can be located between the adjacent two second chips 12. In this way, the distance between the bridge chip 17 and the adjacent two second chips 12 can be relatively short, and the interconnection distance between the second chip 12 and the first interconnection layer 132 can be shortened.

[0091] The above introduces several interconnection modes of the first interconnection layer with the second chip and / or the first chip, and in a specific implementation, the above mode 1 to mode 3 can also be combined with each other, for example, mode 1 and mode 2 can be combined, and on the basis of providing the first conductive via hole in the second chip, a dielectric via hole is provided in the dielectric layer. Of course, in some cases, the first interconnection layer and the second chip and / or the first chip can also adopt other interconnection modes, and reasonable arrangement can be made according to the interconnection requirement.

[0092] In a possible implementation, as shown in FIG. 2, the first chip 11 can include a third substrate 111 and a third interconnection layer 112 located on a side of the third substrate 111 close to the support structure 13. Exemplarily, the third substrate 111 can include a semiconductor material such as silicon, silicon carbide, etc. The surface of the first chip 11 close to the support structure 13 is provided with a second connection end Q2, that is, the third interconnection layer 112 is provided with the second connection end Q2 on the surface close to the second chip 12, the second interconnection layer 122 is provided with a third connection end Q3 on the surface close to the side of the first chip 11, and the second connection end Q2 is electrically connected with the third connection end Q3 to realize interconnection between the second chip 12 and the first chip 11. In a specific arrangement, the third interconnection layer 112 is provided with a third dielectric film 163 on the side close to the second chip 12, and the second connection end Q2 is exposed through a via in the third dielectric film 163. The surface of the second chip 12 close to the first chip 11 is provided with a fourth dielectric film 164, and the third connection end Q3 is exposed through a via in the fourth dielectric film 164. The fourth dielectric film 164 on the surface of the second chip 12 is bonded with the third dielectric film 163 on the surface of the third interconnection layer 112. Thus, the second chip 12 is hybrid-bonded with the first chip 11. In the embodiment of the present application, the third interconnection layer 112 is arranged on the side of the third substrate 111 close to the support structure 13, which can make the interconnection distance between the third interconnection layer 112 and the second chip 12 shorter. Of course, in some cases, the third interconnection layer 112 in the first chip 11 can also be located on the side of the third substrate 111 away from the support structure 13, which is not limited here.

[0093] In addition, with continuous reference to FIG. 2, the side of the first chip 11 away from the support structure 13 can also be provided with a fourth connection end Q4 electrically connected with the third interconnection layer 112. When the chip stacking structure in the embodiment of the present application is applied to an electronic device, the chip stacking structure can be electrically connected with a circuit board through the fourth connection end Q4.

[0094] Based on the same technical concept, the embodiment of the present application also provides a manufacturing method of the chip stacking structure. FIG. 5 is a flow chart of the manufacturing method of the chip stacking structure provided by the embodiment of the present application, and FIGS. 6-8 are structure schematic diagrams corresponding to each step in the manufacturing method provided by the embodiment of the present application. As shown in FIG. 5, the manufacturing method of the chip stacking structure provided by the embodiment of the present application can include:

[0095] S201, placing at least one second chip on the first chip, and electrically connecting each second chip with the first chip; wherein the second chip can be a diced die, and the second chip can be a chip with various functions such as computing and storage. The first chip can be a wafer or a part of a wafer diced, and the first chip can include semiconductor materials such as silicon and silicon carbide, and the first chip can be a chip with various functions such as computing and storage. After the second chip is bonded with the first chip, a die and wafer (D2W) stacked structure can be obtained.

[0096] S202, placing a support structure provided with an integrated passive device on a side of each second chip away from the first chip, and connecting the support structure with each second chip; wherein the integrated passive device is electrically connected with at least one second chip, and / or the integrated passive device is electrically connected with the first chip. The support structure can be a wafer or a part of a wafer diced, and the support structure can include semiconductor materials such as silicon and silicon carbide. The integrated passive device can include passive devices such as resistors, capacitors, and inductors, and an interconnection structure connected with the passive devices. The passive devices can function to transmit signals, store energy, and filter signals. The integrated passive device can adjust power supply and signals, and provide the adjusted power supply and signals to the second chip. In addition, the integrated passive device can also function to shield electromagnetic interference, so that the second chip or the first chip achieves better electromagnetic protection and avoids interference of electromagnetic signals on the second chip and the first chip.

[0097] In the chip stacking structure manufacturing method provided by the embodiments of the present application, by integrating the integrated passive device into the support structure, on the one hand, the integrated passive device, the second chip, and the first chip can be stacked in the vertical direction (perpendicular to the surface of the first chip), which can greatly reduce the interconnection distance between the second chip and / or the first chip and the integrated passive device, and the second chip and / or the first chip and the integrated passive device do not need to be interconnected through a substrate (or an intermediate board), thereby reducing the area overhead of the substrate (or the intermediate board) and reducing the manufacturing cost of the chip stacking structure. Furthermore, the volume of a chip packaging structure containing the chip stacking structure and the substrate (or the intermediate board) can be reduced, and the integration of the chip packaging structure can be improved. On the other hand, the substrate utilization rate of the support structure can be improved, and the internal structure of the chip stacking structure can be reasonably utilized. In addition, the support structure is generally a silicon wafer, and the heat dissipation efficiency of silicon material is relatively high, so the support structure can have good heat dissipation effect, and thus the support structure can also function to evenly heat and strengthen heat dissipation.

[0098] In addition, before the step S202, the manufacturing method in the embodiments of the present application can further include: filling a medium material in the gap between the second chips to form a medium layer. For example, the medium layer can be made of inorganic medium material such as silicon oxide. In some cases, after the medium layer is made, the back side of the second chip (the side of the second chip facing away from the first chip) can be planarized and thinned.

[0099] Based on the above description of the chip stacking structure, the first interconnection layer in the support structure can have multiple interconnection modes with the second chip and / or the first chip. The manufacturing method of the chip stacking structure with the above modes 1-3 will be described in detail below with reference to the accompanying drawings.

[0100] In some embodiments of the present application, when the chip stacking structure has the structure of mode 1, the manufacturing method in the embodiments of the present application can specifically include:

[0101] Referring to (1) in FIG. 6, the first chip 11 can include a third substrate 111 and a third interconnection layer 112. For example, the third substrate 111 can include semiconductor material such as silicon or silicon carbide. The second chip 12 can include a second substrate 121 and a second interconnection layer 122. The step S201 can specifically include: placing the second chip 12 on the first chip 11 with the surface of the first chip 11 on the side of the third interconnection layer 112 facing up, and making the second interconnection layer 122 of the second chip 12 face the third interconnection layer 112. The second chip 12 and the first chip 11 are mixedly bonded to make the second interconnection layer 122 and the third interconnection layer 112 electrically connected. In the embodiments of the present application, the second chip 12 can be flip-chip mounted on the first chip 11 as an example. In some cases, the second chip 12 can also be mounted on the first chip 11 in a face-up manner, which is not limited herein. In addition, the third interconnection layer 112 in the first chip 11 is located on the side of the third substrate 111 close to the second chip 12, which can make the interconnection distance between the third interconnection layer 112 and the second chip 12 shorter. Of course, in some cases, the third interconnection layer 112 in the first chip 11 can also be located on the side of the third substrate 111 away from the second chip 12, which is not limited herein.

[0102] In a specific arrangement, the third interconnection layer 112 is provided with a second connection end Q2 on a surface close to the second chip 12, and the second interconnection layer 122 is provided with a third connection end Q3 on a surface close to the first chip 11, and the second connection end Q2 is bonded to the third connection end Q3 to realize interconnection between the second chip 12 and the first chip 11. In a specific arrangement, the third interconnection layer 112 is provided with a third dielectric film 163 on a side close to the second chip 12, and the second connection end Q2 is exposed through a via in the third dielectric film 163. The second chip 12 is provided with a fourth dielectric film 164 on a surface close to the first chip 11, and the third connection end Q3 is exposed through a via in the fourth dielectric film 164. The fourth dielectric film 164 on the surface of the second chip 12 is bonded to the third dielectric film 163 on the surface of the third interconnection layer 112. Thus, the second chip 12 is hybrid-bonded to the first chip 11.

[0103] Referring to (2) in FIG. 6, a dielectric material is filled in the gaps between the second chips 12 to form a dielectric layer 15. Exemplarily, the dielectric layer 15 can be made of an inorganic dielectric material such as silicon oxide. In some cases, after the dielectric layer 15 is made, the back side (the side of the second chip 12 facing away from the first chip 11) of the second chip 12 can be planarized and thinned.

[0104] Referring to (3) in FIG. 6, after the step S201 and before the step S202, the manufacturing method in the embodiment of the present application can further include: punching the second chip 12, and filling a conductive material in the formed hole, for example, a metal material can be filled by using a thin film deposition, electroplating or other process to form a first conductive via T1 penetrating from the surface of the second substrate 121 facing away from the first chip 11 to the inside of the second interconnection layer; wherein the first conductive via T1 is electrically connected to the second interconnection layer 122. In order to facilitate bonding with the support structure, the first conductive via T1 can protrude from the surface of the second substrate 121 facing away from the first chip 11.

[0105] Alternatively, the first conductive via T1 is already provided in the second chip 12 before the second chip 12 is bonded to the first chip 11. After the step S201 and before the step S202, the manufacturing method in the embodiment of the present application can further include: thinning the surface of the second substrate 121 facing away from the first chip 11 to expose the first conductive via T1, to obtain the structure shown in (3) in FIG. 6.

[0106] Then, a second dielectric film 162 is formed on the second chip 12 and the dielectric layer 15, and the end of the first conductive via T1 is exposed through a via in the second dielectric film 162.

[0107] Referring to (4) in FIG. 6, a support structure 13 is provided, which can include a first substrate 131 and a first interconnection layer 132 provided with a first connection end Q1 on a surface facing away from the first substrate 131. The step S202 can specifically include placing the support structure 13 above the second chip 12, with the first interconnection layer 132 of the support structure 13 facing the second chip 12. The support structure 13 and each second chip 12 are bonded, so that the first connection end Q1 is electrically connected to the first conductive via T1. In the embodiments of the present application, by providing the first conductive via T1 in the second chip 12, the first conductive via T1 can connect the second interconnection layer 122 to the surface of the second substrate 121 close to the support structure 13, so that the interconnection distance between the second chip 12 and the first interconnection layer 132 is short.

[0108] Continuing to refer to (4) in FIG. 6, the support structure 13 can further include a first dielectric film 161 on the side of the first interconnection layer 132 close to the second chip 12, and a first connection end Q1 electrically connected to the first interconnection layer 132 and exposed through a via in the first dielectric film 161. In the bonding process in the step S202, the second dielectric film 162 on the surface of the second chip 12 is bonded to the first dielectric film 161 on the surface of the support structure 13, and the first connection end Q1 is bonded to the end of the first conductive via T1, so that the second chip 12 and the support structure 13 are hybrid-bonded.

[0109] After the step S202, the manufacturing method in the embodiments of the present application can further include thinning the surface of the first chip 11 away from the second chip 12 with the support structure 13 as a structure support. In addition, the third substrate 111 can be perforated, and the formed hole can be filled with conductive material to form a conductive via penetrating through the third substrate 111, which can be electrically connected to the third interconnection layer 112. Then, a fourth connection end Q4 is formed above the first chip 11, which can be electrically connected to the third interconnection layer 112 through the conductive via, thereby obtaining the structure shown in FIG. 2. In the process of thinning the first chip 11, the support structure 13 can increase the total thickness of the entire chip stack structure, and can serve as a structure support for thinning the first chip 11. Of course, in some cases, the process of thinning the first chip 11 can be omitted, for example, the thickness of the first chip 11 is thin enough and does not need to be thinned, or the third interconnection layer 112 of the first chip 11 is located on the side of the third substrate 111 facing away from the support structure 13, so that the first chip 11 does not need to be thinned.

[0110] In some embodiments of the present application, when the chip stack structure has the structure of the above-mentioned mode two, the manufacturing method in the embodiments of the present application can specifically include:

[0111] Referring to (1) in FIG. 7, at least one second chip 12 is placed on the first chip 11, and each second chip 12 is electrically connected with the first chip 11. The specific connection mode of the second chip 12 with the first chip 11 can refer to the related description of (1) in FIG. 6 above, and the repeated parts will not be described herein.

[0112] Referring to (2) in FIG. 7, in the above-mentioned step S202, a dielectric material is filled in the gap between each second chip 12 to form a dielectric layer 15. Exemplarily, the dielectric layer 15 can be made of inorganic dielectric materials such as silicon oxide. In some cases, after the dielectric layer 15 is made, the back side (the side of the second chip 12 facing away from the first chip 11) of the second chip 12 can be planarized and thinned.

[0113] Referring to (3) in FIG. 7, after the dielectric layer 15 is formed, before the above-mentioned step S202, the manufacturing method in the embodiments of the present application can further include: perforating the dielectric layer 15, and filling a conductive material in the formed hole, for example, a metal material can be filled by using a thin film deposition, electroplating or other process, to form a dielectric via hole 151 penetrating through the dielectric layer 15, the dielectric via hole 151 being electrically connected with the second interconnection layer 122 and / or the first chip 11.

[0114] In some cases, after the dielectric layer 15 is formed, a second dielectric film 162 can be further formed on the dielectric layer 15, and after the second dielectric film 162 is formed, the second dielectric film 162 and the dielectric layer 15 are perforated, and a conductive material is filled in the formed hole to form a dielectric via hole 151 penetrating through the second dielectric film 162 and the dielectric layer 15.

[0115] Referring to (4) in FIG. 7, a support structure 13 is provided, which can include a first substrate 131 and a first interconnection layer 132, and the first interconnection layer 132 is provided with a first connection end Q1 on the surface facing away from the first substrate 131. The above-mentioned step S202 can specifically include: placing the support structure 13 on the second chip 12, and the first interconnection layer 132 of the support structure 13 faces the second chip 12. The support structure 13 and the second chip 12 are bonded, so that the first connection end Q1 is electrically connected with the dielectric via hole 151. In the embodiments of the present application, by forming the dielectric via hole 151 in the dielectric layer 15, the first connection end Q1 and the second interconnection layer 122 and / or the first chip 11 can be electrically connected through the dielectric via hole 151, without the need to perforate and fill metal in the second chip 12, which simplifies the process flow of the second chip, improves the active area ratio of the second chip, and thus reduces the cost.

[0116] Continuing to refer to (4) in FIG. 7, the support structure 13 can further include a first dielectric film 161 located on the side of the first interconnection layer 132 close to the second chip 12, and a first connection end Q1 electrically connected to the first interconnection layer 132 and exposed through a via in the first dielectric film 161. During the bonding process in step S202, the second dielectric film 162 on the surface of the second chip 12 is bonded to the first dielectric film 161 on the surface of the support structure 13, and the first connection end Q1 is bonded to the end of the dielectric via 151, so that the support structure 13 is hybrid-bonded to the underlying die and wafer stack structure (the stack structure composed of the second chip 12 and the first chip 11).

[0117] After step S202, the manufacturing method in the embodiments of the present application can further include thinning the surface of the first chip 11 away from the second chip 12 with the support structure 13 as the structural support. In addition, the third substrate 111 can be perforated, and the resulting hole can be filled with conductive material to form a conductive via penetrating through the third substrate 111, which can be electrically connected to the third interconnection layer 112. Then, a fourth connection end Q4 can be formed on the first chip 11, which can be electrically connected to the third interconnection layer 112 through the conductive via, thereby obtaining the structure shown in FIG. 3. During the thinning process of the first chip 11, the support structure 13 can increase the total thickness of the entire chip stack structure and serve as the structural support for the thinning of the first chip 11. Of course, in some cases, the process of thinning the first chip 11 can be omitted, for example, the thickness of the first chip 11 is thin enough and does not need to be thinned, or when the third interconnection layer 112 of the first chip 11 is located on the side of the third substrate 111 away from the support structure 13, the first chip 11 can also not be thinned.

[0118] In some other embodiments of the present application, when the chip stack structure has the structure of the above-mentioned mode three, the manufacturing method in the embodiments of the present application can specifically include:

[0119] Referring to (1) of FIG. 8, a bridge chip 17 is provided, and the bridge chip 17 is provided with a second conductive via T2 penetrating through the bridge chip 17. In a specific implementation, the bridge chip 17 can be provided with one or more second conductive vias T2, and the number of the second conductive vias T2 in the bridge chip 17 can be set according to actual needs, which is not limited herein. In step S201, the second chip 12 and the bridge chip 17 are placed on the first chip 11, that is, the bridge chip 17 is placed on the first chip 11 except for the second chip 12. The second chip 12 and the bridge chip 17 are electrically connected to the first chip 11. In a specific implementation, the second chip 12 and the bridge chip 17 can be electrically connected to the first chip 11 by hybrid bonding. The second chip 12 can be bonded first, or the bridge chip 17 can be bonded first, and the bonding sequence of the second chip 12 and the bridge chip 17 is not limited herein. The specific bonding manner of the second chip 12 and the first chip 11 can be referred to the related description of (1) of FIG. 6, and the repeated description is not repeated herein. In the embodiment of the present application, the chip stacking structure can include one or more bridge chips 17, and the number and position of the bridge chip 17 can be set according to actual needs, which is not limited herein.

[0120] Referring to (2) of FIG. 8, in step S202, the region on the first chip 11 except for the second chip 12 and the bridge chip 17 is filled with a dielectric material to form a dielectric layer 15. In some cases, the surface of the dielectric layer 15 can be planarized and thinned. Then, a second dielectric film 162 is formed on the second chip 12 and the bridge chip 17, and an interconnection line for leading out the second conductive via T2 is formed, and at least a part of the interconnection line can be exposed on the surface of the second dielectric film 162.

[0121] Referring to (3) in FIG. 8, a support structure 13 is provided, which can include a first substrate 131 and a first interconnection layer 132 provided with a first connection end Q1 on a surface facing away from the first substrate 131. The step S202 can specifically include placing the support structure 13 above each second chip 12, with the first interconnection layer 132 of the support structure 13 facing the second chip 12. The support structure 13 and each second chip 12 are bonded, so that the first connection end Q1 is electrically connected to the second conductive via T2, so that the first connection end Q1 is electrically connected to the second interconnection layer 122 and / or the first chip 11 through the second conductive via T2. In the embodiments of the present application, by installing the bridge chip 17 above the first chip 11, the first connection end Q1 can be electrically connected to the second interconnection layer 122 and / or the first chip 11, without the need to punch the second chip 12, simplifying the process flow of the second chip, improving the active area ratio of the second chip, thereby reducing the cost.

[0122] Continuing to refer to (3) in FIG. 8, the support structure 13 can further include a first dielectric film 161 located on a side of the first interconnection layer 132 close to the second chip 12, and a first connection end Q1 electrically connected to the first interconnection layer 132 and exposed through a via in the first dielectric film 161. In the bonding process in the above step S202, the second dielectric film 162 on the surface of the second chip 12 is bonded to the first dielectric film 161 on the surface of the support structure 13, and the first connection end Q1 is bonded to the second conductive via T2, so that the support structure 13 is mixedly bonded to the underlying die and wafer stack structure (the stack structure composed of the second chip 12 and the first chip 11).

[0123] After step S202, the manufacturing method in the embodiment of the present application can further include: thinning the surface of the first chip 11 away from the second chip 12 with the support structure 13 as a structure support. In addition, the third substrate 111 can be punched, and the conductive material can be filled in the formed hole to form a conductive via penetrating through the third substrate 111, which can be electrically connected with the third interconnection layer 112. Then, the fourth connection end Q4 is formed on the first chip 11, which can be electrically connected with the third interconnection layer 112 through the conductive via, thereby obtaining the structure shown in FIG. 4. In the process of thinning the first chip 11, the support structure 13 can increase the total thickness of the whole chip stack structure, and can be used as a structure support for thinning the first chip 11. Of course, in some cases, the process of thinning the first chip 11 can be omitted, for example, the thickness of the first chip 11 is thin enough and does not need to be thinned, or the third interconnection layer 112 of the first chip 11 is located on the side of the third substrate 111 away from the support structure 13, and the first chip 11 does not need to be thinned.

[0124] The manufacturing method of the chip stack structure with the above-mentioned mode one to mode three is introduced above. In the specific implementation, the above-mentioned mode one to mode three can be combined with each other, or the first interconnection layer and the second chip can use other interconnection modes, and the manufacturing method can be implemented by referring to the above-mentioned manufacturing method, and the repeated parts will not be described herein. In addition, in the above description, the manufacturing method of the chip stack structure is introduced by taking the chip stack structure including the second chip as an example. When the chip stack structure includes multiple chips, the manufacturing process of other chips can refer to the manufacturing process of the second chip, and the repeated parts will not be described herein.

[0125] Although the preferred embodiments of the present application have been described, those skilled in the art can make additional changes and modifications to the embodiments once they know the basic inventive concept. Therefore, the appended claims are intended to be interpreted as including all the preferred embodiments and all the changes and modifications falling within the scope of the present application.

[0126] Obviously, those skilled in the art can make various modifications and variations to the embodiments of the present application without departing from the spirit and scope of the embodiments of the present application. Thus, if these modifications and variations of the embodiments of the present application fall within the scope of the claims of the present application and their equivalent technologies, the present application is also intended to include these modifications and variations.

Claims

1. A chip stack structure, characterized by, The chip stack structure comprises: a first chip; a support structure, wherein an integrated passive device is arranged in the support structure; at least one second chip, which is located between the first chip and the support structure; the first chip is electrically connected with the at least one second chip, and the support structure is connected with the at least one second chip; the integrated passive device is electrically connected with at least one of the second chips; and / or, the integrated passive device is electrically connected with the first chip.

2. The chip stack structure of claim 1, wherein, The support structure comprises a first substrate and a first interconnection layer; the first interconnection layer is located on a side of the first substrate close to the first chip, and the integrated passive device is located on a side of the first substrate close to the first interconnection layer; the integrated passive device is electrically connected with at least one of the second chips through the first interconnection layer; and / or, the integrated passive device is electrically connected with the first chip through the first interconnection layer.

3. The chip stack structure of claim 2, wherein, The first interconnection layer is provided with a first connecting end on a surface of a side close to the first chip; The second chip comprises a second substrate and a second interconnection layer, and the second interconnection layer is located on a side of the second substrate close to the first chip; a first conductive via is arranged in the second chip, the first conductive via penetrates from a surface of a side of the second substrate close to the support structure to an inside of the second interconnection layer, and the first conductive via is electrically connected with the second interconnection layer; the first connecting end is electrically connected with an end of the first conductive via close to the support structure.

4. The chip stack structure of claim 2, wherein, The first interconnection layer is provided with a first connecting end on a surface of a side close to the first chip; The second chip comprises a second substrate and a second interconnection layer, and the second interconnection layer is located on a side of the second substrate close to the first chip; The chip stack structure further comprises a medium layer located between the first chip and the support structure, and a conductive medium via is arranged in the medium layer; one end of the medium via close to the support structure is electrically connected with the first connecting end, and the other end is electrically connected with the second interconnection layer and / or the first chip.

5. The chip stack structure of claim 2, wherein, The first interconnection layer is provided with a first connecting end on a surface of a side close to the first chip; The second chip comprises a second substrate and a second interconnection layer, and the second interconnection layer is located on a side of the second substrate close to the first chip; The chip stack structure further comprises a bridge chip located between the first chip and the support structure; a second conductive via is arranged in the bridge chip, and the second conductive via penetrates the bridge chip; one end of the second conductive via close to the support structure is electrically connected with the first connecting end, and the other end is electrically connected with the second interconnection layer and / or the first chip.

6. The chip stack structure of claim 5, wherein, The chip stack structure comprises at least two second chips, and the bridge chip is located between two adjacent second chips.

7. The chip stack structure according to any one of claims 3 to 6, wherein The first chip comprises a third substrate and a third interconnection layer, and the third interconnection layer is located on a side of the third substrate close to the support structure; The third interconnection layer is provided with a second connecting end on a surface close to the second chip, and the third interconnection layer is provided with a third connecting end on a surface close to the first chip side; The second connecting end is electrically connected with the third connecting end.

8. A chip package structure, comprising: The chip stack structure and the substrate are fixed on the substrate. The chip stack structure and the substrate are fixed on the substrate.

9. An electronic device, comprising: The chip stack structure and the substrate are fixed on the substrate. At least one second chip is placed on the first chip, and the at least one second chip is electrically connected with the first chip; 10. A method for fabricating a chip stack structure, the method comprising: A support structure provided with an integrated passive device is placed on a side of the at least one second chip away from the first chip, and the support structure is connected with the at least one second chip; wherein the integrated passive device is electrically connected with at least one of the second chips; and / or, the integrated passive device is electrically connected with the first chip. The first chip comprises a third substrate and a third interconnection layer, and the second chip comprises a second substrate and a second interconnection layer; The at least one second chip is placed on the first chip, and the at least one second chip is electrically connected with the first chip, specifically comprising:

11. The method of claim 10, wherein The first chip has a surface on a side of the third interconnection layer facing upward, the second chip is placed on the first chip, and the second interconnection layer of the second chip faces the third interconnection layer; The second chip and the first chip are hybrid bonded, and the second interconnection layer and the third interconnection layer are electrically connected. The second chip comprises a second substrate and a second interconnection layer, and the second interconnection layer is located on a side of the second substrate close to the first chip; After the at least one second chip is electrically connected with the first chip, before the support structure provided with the integrated passive device is placed on a side of the second chip away from the first chip, further comprising:

12. The production method according to claim 10 or 11, wherein The second chip is punched, and a conductive material is filled in the formed hole to form a first conductive via hole penetrating from a surface of the second substrate away from the first chip to an inside of the second interconnection layer; wherein the first conductive via hole is electrically connected with the second interconnection layer; Or, before the at least one second chip is electrically connected with the first chip, a first conductive via hole is provided in the second chip; after the at least one second chip is electrically connected with the first chip, before the support structure provided with the integrated passive device is placed on a side of the second chip away from the first chip, further comprising: A surface of the second substrate away from the first chip is thinned to expose the first conductive via hole; The support structure comprises a first substrate and a first interconnection layer, and the first interconnection layer is provided with a first connecting end on a surface away from the first substrate; and the support structure provided with the integrated passive device is placed on a side of the second chip away from the first chip, and the support structure is connected with the at least one second chip, specifically comprising: ​ ​ placing the support structure on the second chip, and the first interconnection layer of the support structure faces the second chip; bonding the support structure and the at least one second chip, so that the first connecting end is electrically connected with the first conductive via.

13. The production method according to claim 10 or 11, wherein The second chip comprises a second substrate and a second interconnection layer, and the second interconnection layer is located on the side of the second substrate close to the first chip; after the at least one second chip is electrically connected with the first chip, the support structure provided with the integrated passive device is placed on the side of the second chip away from the first chip, and further comprising: filling a medium material in the gap between the second chips to form a medium layer; punching the medium layer and filling a conductive material in the formed hole to form a medium via penetrating through the medium layer; the medium via is electrically connected with the second interconnection layer and / or the first chip; The support structure comprises a first substrate and a first interconnection layer, and the first interconnection layer is provided with a first connecting end on the surface of the side away from the first substrate; the support structure provided with the integrated passive device is placed on the side of the second chip away from the first chip, and the support structure is connected with the at least one second chip, specifically comprising: placing the support structure on the second chip, and the first interconnection layer of the support structure faces the second chip; bonding the support structure and the second chip, so that the first connecting end is electrically connected with the medium via.

14. The production method according to claim 10 or 11, wherein The second chip comprises a second substrate and a second interconnection layer, and the second interconnection layer is located on the side of the second substrate close to the first chip; before the at least one second chip is electrically connected with the first chip, further comprising: placing a bridge chip on the first chip in a position other than the at least one second chip, and electrically connecting the bridge chip with the first chip; wherein the bridge chip is provided with a second conductive via penetrating through the bridge chip; filling a medium material on the first chip in a region other than the second chips and the bridge chip to form a medium layer; The support structure comprises a first substrate and a first interconnection layer, and the first interconnection layer is provided with a first connecting end on the surface of the side away from the first substrate; the support structure provided with the integrated passive device is placed on the side of the second chip away from the first chip, and the support structure is connected with the second chip, specifically comprising: placing the support structure on the at least one second chip, and the first interconnection layer of the support structure faces the second chip; bonding the support structure and the at least one second chip, so that the first connecting end is electrically connected with the second conductive via, so that the first connecting end is electrically connected with the second interconnection layer through the second conductive via.

15. The method of making according to any one of claims 10 to 14, wherein, After the support structure is connected with the at least one second chip, further comprising: thinning the surface of the first chip away from the second chip by taking the support structure as a structural support. thinning the surface of the first chip away from the second chip by taking the support structure as a structural support.

Images