Neural network optimization circuit

Abstract

The present disclosure provides a neural network optimization circuit, comprising: a first conversion unit; a second conversion unit; a first multiplier, configured to output a prediction result signal on the basis of a target direct current level signal and an adder output signal; an error calculation unit, configured to calculate an error signal; a first differentiator, configured to receive the error signal; a second differentiator, configured to receive the adder output signal or a plurality of weight change signals; a second multiplier, configured to receive a first differentiator output signal and a second differentiator output signal; an integrator, configured to receive a second multiplier output signal; and an adder, configured to receive the plurality of weight change signals and an integrator output signal, wherein the weight change signals correspond to different weight values.

Description

Neural network optimization circuit TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of circuit, in particular to a neural network optimization circuit. BACKGROUND

[0002] In recent years, the application of neural network is more and more widely. With the development of AI technology, the demand for computing power is rising rapidly, and improving the optimization speed is an important development direction.

[0003] In the related art, the optimizer based on digital circuit or digital-analog hybrid circuit needs the participation of computer in each iteration during the training process, and also needs to perform AD conversion, error comparison, summation and error change judgment in turn. Limited by the frequency of clock signal, the process is complex and slow, and pure on-chip training cannot be performed. Moreover, the neural network needs the participation of computer multiple times when processing a piece of data, which destroys the continuity of the system, and the convergence speed is slow in the clock driving mode. In addition, during the processing of batch data by the neural network, the stability of the neural network data cannot be guaranteed due to the influence of disturbance power, and the convergence efficiency of the neural network data also cannot be guaranteed. SUMMARY

[0004] Therefore, the present disclosure provides a neural network optimization circuit, which is trained in an all-analog circuit manner. The problems of slow speed, poor system continuity and poor convergence speed of digital optimizer and digital-analog hybrid optimizer are solved, and the problems of unable to guarantee the convergence efficiency and stability of neural network data during the processing of batch data by the neural network are also solved.

[0005] According to a first aspect of the present disclosure, a neural network optimization circuit applied to a target neural network is provided, comprising: a first conversion unit configured to convert target training data into a target direct current level signal corresponding to the target training data; a second conversion unit configured to convert label data corresponding to the target training data into a label result level signal; a first multiplier configured to multiply the target direct current level signal corresponding to the target training data and an adder output signal to output a prediction result signal corresponding to the target training data; an error calculation unit configured to calculate an error signal between the prediction result signal and the label result level signal of the target training data; a first differentiator configured to receive the error signal and output a first differentiator output signal; a second differentiator configured to receive the adder output signal or a plurality of weight change signals of a plurality of weight change data and output a second differentiator output signal; a second multiplier configured to receive the first differentiator output signal and the second differentiator output signal and output a second multiplier output signal; an integrator configured to receive the second multiplier output signal and output an integrator output signal; an adder configured to receive the plurality of weight change signals of the plurality of weight change data and the integrator output signal and output the adder output signal; wherein each weight change signal corresponds to a different weight value, and each weight change data represents a change amount of the weight value corresponding to the weight change data over time.

[0006] According to a second aspect of the present disclosure, a neural network optimization circuit applied to a target neural network is provided, comprising: a first conversion unit configured to convert target training data into a target direct current level signal corresponding to the target training data; a second conversion unit configured to convert label data corresponding to the target training data into a label result level signal; a first multiplier configured to multiply the target direct current level signal corresponding to the target training data and an adder output signal to output a prediction result signal corresponding to the target training data; an error calculation unit configured to calculate an error signal between the prediction result signal and the label result level signal of the target training data; a first differentiator configured to receive the error signal and output a first differentiator output signal; a second differentiator configured to receive a third multiplier output signal or an adder output signal and output a second differentiator output signal; a second multiplier configured to receive the first differentiator output signal and the second differentiator output signal and output a second multiplier output signal; an integrator configured to receive the second multiplier output signal and output an integrator output signal; an adder configured to receive the third multiplier output signal and the integrator output signal; a third multiplier configured to receive the target direct current level signal corresponding to the target training data and a perturbation signal of each weight to output a third multiplier output signal; wherein the weight corresponding to the connection relationship between each neuron of each layer in the target neural network and the same neuron of the next layer comes from the same perturbation signal.

[0007] According to the neural network optimization circuit of the present disclosure, the optimization speed of the neural network training device is improved, and the ability of fast inference training, low expansion cost, high parallelism, storage and calculation integration, and on-chip learning is simultaneously possessed. Meanwhile, the present disclosure is implemented using analog circuits, and the computer does not need to participate in the calculation of the weight error value multiple times. There is no non-continuous signal such as a switching signal and a clock signal in the entire training process. The fast convergence is realized under the strict mathematical theory guarantee. On the other hand, by placing the second differentiator from the disturbance source to the position of the adder output, the original convergence direction of the circuit can be maintained, the requirement for the disturbance power is reduced, and the stability of the network is improved. In addition, the neural network optimization circuit uses analog circuits, and the expansion cost is low.

[0008] Alternatively, according to the neural network optimization circuit of the present disclosure, a third multiplier is added in front of the adder, and the constraint of the network is considered by adding the same disturbance to the weight corresponding to the connection relationship between each neuron of each layer of the fully connected neural network and the same neuron of the next layer, so as to reduce the total disturbance and maximize the convergence efficiency. In addition, by placing the second differentiator from the disturbance source to the position of the adder output, the original convergence direction of the circuit can be maintained, the requirement for the disturbance power is reduced, and the stability of the network is improved. BRIEF DESCRIPTION OF DRAWINGS

[0009] The above and other objects and features of the present disclosure will become more apparent from the following description made with reference to the accompanying drawings.

[0010] FIGS. 1A and 1B are schematic diagrams of a training process of a neural network optimization circuit according to an embodiment of the present disclosure.

[0011] FIG. 2 is a schematic diagram of a scenario in which a target neural network is a CNN convolutional neural network according to an embodiment of the present disclosure.

[0012] FIG. 3 is a schematic diagram of a training process and a structural framework of a neural network optimization circuit according to an embodiment of the present disclosure.

[0013] FIG. 4 is a schematic diagram of a circuit for processing batch data of a target neural network according to an embodiment of the present disclosure.

[0014] FIG. 5 is a schematic diagram of an inference process and a structural framework and a layout of internal modularization of an analog circuit neural network according to an embodiment of the present disclosure.

[0015] FIG. 6 is a schematic diagram of a specific circuit structure of a weight circuit according to an embodiment of the present disclosure.

[0016] FIGS. 7A and 7B are schematic diagrams of a training process of a neural network optimization circuit according to another embodiment of the present disclosure.

[0017] FIG. 8 is a schematic diagram of a training process and a structural framework of a neural network optimization circuit according to another embodiment of the present disclosure.

[0018] FIG. 9 is a schematic diagram of an inference process and a structural framework of a neural network optimization circuit according to another embodiment of the present disclosure and a layout schematic diagram of internal modularization of an analog circuit neural network.

[0019] FIG. 10 is a schematic diagram of a three-layer 2*2*2 neural network with an activation function built in simulink according to an embodiment of the present disclosure.

[0020] FIG. 11 is a schematic diagram of a loss curve of processing two pieces of data according to an embodiment of the present disclosure.

[0021] FIG. 12 is a schematic diagram of a change of a solution in a training process according to an embodiment of the present disclosure.

[0022] FIG. 13 is a schematic diagram of a training of a circuit to complete an XOR task within 10 ns according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0023] The following detailed description is provided to aid in understanding the method, device, and / or system described herein. No limitation on the method, device, and / or system described herein is intended based on the description provided. Rather, changes, modifications, and equivalents of the method, device, and / or system described herein will be apparent to those of ordinary skill in the art after having the benefit of the present disclosure. For instance, the order of the operations described herein is merely an example and is not limited to those set forth herein, but can be changed as will be apparent after having the benefit of the present disclosure. Furthermore, descriptions of features known to those of ordinary skill in the art can be omitted so as to make the present description more clear and concise.

[0024] The features described herein can be implemented in different ways depending on the specific application. Rather than be limited to the examples described herein, the examples described herein are provided to illustrate some of the many possible ways of implementing the method, device, and / or system described herein, which will be apparent to those of ordinary skill in the art after having the benefit of the present disclosure.

[0025] As used herein, the term “and / or” includes any one of the associated listed items, as well as any combination of any two or more of the associated listed items.

[0026] Although terms such as "first", "second", and "third" can be used herein to describe various components, assemblies, regions, layers or sections, these components, assemblies, regions, layers or sections should not be limited by these terms. Instead, these terms are only used to distinguish one component, assembly, region, layer or section from another component, assembly, region, layer or section. Thus, a first component, a first assembly, a first region, a first layer or a first section referred to in the examples described herein can also be referred to as a second component, a second assembly, a second region, a second layer or a second section without departing from the teachings of the examples.

[0027] In the specification, when an element (such as a layer, a region, or a substrate) is described as "on", "connected to", or "joined to" another element, it can be "directly on", "directly connected to", or "directly joined to" the other element, or one or more other elements can be interposed therebetween. In contrast, when an element is described as "directly on", "directly connected to", or "directly joined to" another element, no other element is interposed therebetween.

[0028] The terms used herein are only used to describe various examples, and are not intended to limit the disclosure. The singular form is intended to include the plural form unless the context clearly indicates otherwise. The terms "comprise", "include" and "have" indicate the presence of the stated feature, number, operation, component, element, and / or combinations thereof, but do not exclude the presence or addition of one or more other features, numbers, operations, components, elements, and / or combinations thereof.

[0029] Unless otherwise defined, all terms used herein, including technical terms and scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which the disclosure belongs after the disclosure is understood. Unless explicitly defined herein, terms such as those defined in a general dictionary should be interpreted as having meanings consistent with their meanings in the context of the relevant art and the disclosure, and should not be interpreted ideally or too formally.

[0030] In addition, in the description of the examples, when it is considered that a detailed description of the related structure or function known to cause ambiguity in the understanding of the disclosure will be omitted, such a detailed description will be omitted.

[0031] In recent years, with the development of AI technology, the demand for computing power has rapidly increased, and improving the optimization speed is an important development direction, therefore, the application of neural networks is becoming more and more widespread.

[0032] In the related art, an optimizer based on a digital circuit or a digital-analog hybrid circuit needs a computer to participate in each iteration in a training process, and also needs to sequentially perform AD conversion, error comparison, summation, and judgment of error change, is limited by a clock signal frequency, has a complex flow, is slow, cannot perform pure on-chip training, and the neural network needs multiple participation of the computer when processing one piece of data, which destroys the continuity of the system, and in a clock-driven manner, the convergence speed is slow. In addition, some neural networks can process batch data when processing batch data, but the weight change signal of the batch weight change data cannot guarantee the stability of the neural network data due to the influence of the disturbance power, and the weight disturbance signal cannot guarantee the convergence efficiency of the neural network data due to the influence of the network constraint, and in addition, the introduction of strong disturbance also affects the stability of the network. When an analog circuit neural network chip is made based on the random weight change (RWC) theory, the following problems exist.

[0033] First, the neural network of the RWC learning algorithm is driven by a clock, is a discrete system in nature, and in one control period, the weight can pass through and exceed the optimal value, and the circuit has no constraint, so the weight change rate of the circuit must be kept at a small level. That is, it is limited by the limit of the control period, and the convergence speed is slow. At the same time, the random disturbance direction cannot be guaranteed to be the loss decrease direction, so there are some control periods that make the loss increase.

[0034] Second, in the neural network of the RWC learning algorithm, if the total error increases, the weight will be randomly updated again, and the total output error needs to be collected from the chip by the digital computer and then calculated each time the random update is performed, so the feedback loop needs multiple participation of the digital computer, and pure on-chip training cannot be performed.

[0035] Third, in the neural network of the RWC learning algorithm, the part participating in the digital computer includes A / D conversion of the chip neuron output, error comparison, summation, judgment of error change, D / A conversion of the clock signal, causing a complex flow and slow speed.

[0036] Fourth, since the disturbance value of each weight of the circuit is discrete ±1, in the parameter space, the direction of the weight disturbance is all orthogonal, and the weight modification in any direction cannot be realized.

[0037] Fifth, multiple participation of the computer is needed when processing one piece of data, the continuity of the system is broken, and the speed advantage of the continuity of the analog circuit is not fully utilized.

[0038] Therefore, according to the embodiment of the present disclosure, a neural network optimization circuit is provided as shown in FIG. 1A and FIG. 1B, which is applied to a target neural network, and the neural network optimization circuit comprises a first conversion unit 51, a second conversion unit 52, a first multiplier 53, a first differentiator 54, a second differentiator 55, a second multiplier 56, an adder 57, an integrator 58, and an error calculation unit 59. The neural network optimization circuit shown in FIG. 1A and FIG. 1B is a basic training unit in the embodiment of the present disclosure, that is, the weight of the neural network. In FIG. 1A and FIG. 1B, the dashed box represents an arbitrary target neural network, which can be a Transformer neural network or a CNN convolutional neural network or an RNN recurrent neural network or a fully connected neural network.

[0039] In actual design, according to different introduction methods of the disturbance signal and different input positions of the second differentiator, the basic unit of the analog circuit neural network can be divided into several different basic structures. The neural network optimization circuit in the embodiment of the present disclosure is suitable for the scene of processing batch training data, and has the widest applicability, can be extended to batch processing, and has a common weight attention mechanism. That is, the neural network optimization circuit shown in FIG. 1A and FIG. 1B is suitable for the scene where the target neural network is a Transformer neural network or a CNN convolutional neural network or an RNN recurrent neural network, and each weight participates in the calculation of multiple data at the same time. As shown in FIG. 2, the target neural network in the dashed box is a CNN convolutional neural network, and each weight participates in the calculation of multiple data at the same time.

[0040] In the embodiment of the present disclosure, a two-layer 2x2 fully connected neural network is taken as an example. The left two circles are input neurons, and the input signal is a direct current level. The output signal is also a direct current level, and the input and output neurons are connected by four weights. The connection between the left and right neurons is a solid line. The analog circuit on the lower side in FIG. 1A and FIG. 1B shows the internal structure of the weight.

[0041] In FIG. 1A and FIG. 1B, the first conversion unit 51 is used to convert the target training data into a target direct current level signal corresponding to the target training data.

[0042] Specifically, as shown in FIG. 3, the first conversion unit 51 in the embodiment of the present disclosure can be a D / A digital-to-analog converter, which converts the target training data into a target direct current level signal corresponding to the target training data. The target training data can be a data sample set of different types, and each data in the data sample set is converted into a target direct current level signal, for example, the target training data is represented by M, M={a1, a2, a3,... a n} are converted into the target DC level signals corresponding to the n data in the data sample set. In the embodiments of the present disclosure, the target training data is also referred to as input training data. In the embodiments of the present disclosure, the target training data is converted into the target DC level signals corresponding to the target training data as the input signals of the neural network, which is beneficial to guarantee the continuity of the analog system signals, and thus the circuit can train the target neural network at a high speed.

[0043] In FIGS. 1A and 1B, the second conversion unit 12 is configured to convert the label data corresponding to the target training data into the annotation result level signal.

[0044] Specifically, as shown in FIG. 3, the second conversion unit 52 in the embodiments of the present disclosure can be a D / A digital-to-analog converter, which converts the label data corresponding to the target training data into the annotation result level signal. The annotation result level signal of the target training is the label data level signal, and in FIGS. 1A and 1B, the input data level signal x and the label data level signal y are given simultaneously. For example, the target training data is represented by M, M = {a1, a2, a3,... a n} are converted into the target data level signal x and the label data level signal y.

[0045] In FIGS. 1A and 1B, the first multiplier 53 is configured to output the prediction result signal corresponding to the target training data based on the target DC level signal corresponding to the target training data and the adder output signal.

[0046] Specifically, in FIGS. 1A and 1B, when the target neural network is inferred, taking the single weight calculation as an example, the target DC level signal corresponding to the target training data is multiplied by the weight value level signal at the output end of the adder 57 to obtain the output value , and the inference can be completed. For example, the target DC level signal x corresponding to the target training data is multiplied by the adder output signal (weight value level signal) to output the prediction result signal corresponding to the target training data.

[0047] In FIGS. 1A and 1B, the error calculation unit 59 is configured to calculate the error signal between the prediction result signal and the annotation result level signal of the target training data, for example, but not limited to, the MSE error signal, the cross-entropy error signal, and the like. The following is described taking the MSE error signal as an example.

[0048] Specifically, in FIG. 1A and FIG. 1B, the error calculation unit 59 and the first differentiator 54 can be an MSE differential unit (i.e., a DMSE error calculation unit as shown in FIG. 3), which receives the label data DC level output by the PC computer through the D / A converter, and internally calculates the negative of the MSE loss differential, and outputs it as a wire, which is then fed back to the analog circuit neural network. From this, the circuit forms a closed loop, and the analog circuit neural network weights will converge in the direction of minimizing the error, thus completing the training.

[0049] In FIG. 1A and FIG. 1B, the first differentiator 54 is configured to receive the MSE error signal and output a first differentiator output signal.

[0050] Specifically, in FIG. 1A and FIG. 1B, the target neural network, when training, is given the input data level signal x and the label data level signal y at the same time, and the output signal of the circuit is The MSE loss is calculated with y and the negative of the MSE loss is taken, which represents the negative of the change in the MSE loss, and is connected to the first differentiator 54 and the second multiplier 56 after the first differentiator 54.

[0051] In FIG. 1A and FIG. 1B, the second differentiator 55 is configured to receive the adder output signal or a plurality of weight change signals of a plurality of weight change data, and output a second differentiator output signal. Each weight change signal corresponds to a different weight value, and each weight change data represents the change in the weight value over time corresponding to the weight change data.

[0052] Specifically, in the embodiments of the present disclosure, the plurality of weight change signals of the plurality of weight change data represent weight perturbation noise signals. For example, when the target neural network processes batch data, there are N noise signals, which are described as a plurality of weight change signals, and if the target neural network has N weight change data, it means that there are N noise signals, and each noise signal represents the change in the weight value over time.

[0053] FIG. 4 shows a circuit schematic diagram of the target neural network (as shown in the dashed box) when processing batch data.

[0054] In FIG. 1A and FIG. 1B, the second multiplier 56 is configured to receive the first differentiator output signal and the second differentiator output signal, and output a second multiplier output signal. The integrator 58 is configured to receive the second multiplier output signal and output an integrator output signal. The adder 57 is configured to receive the plurality of weight change signals of the plurality of weight change data and the integrator output signal, and output an adder output signal.

[0055] Specifically, in FIG. 1A and FIG. 1B, the target neural network is in inference, the input data level signal x is given, multiplied with the weight value level signal at the output end of the adder 57, and the output value is obtained by adding according to the illustrated topological relationship That is, the inference is completed. In training, the input data level signal x and the label data level signal y are given at the same time. The output signal of the circuit The MSE loss is calculated with y, and the opposite number of the change amount of the MSE loss is taken, and then connected to the first differentiator 54 and the second multiplier 56. The other end of the second multiplier 56 is connected by the noise through the second differentiator 55, or connected by the adder output through the second differentiator 55. At the same time, the noise is connected to the input end of the adder 57, and the other input end of the adder 57 is the DC level signal of the weight. Therefore, the output of the adder 57 is the weight change signal of each weight change data after the disturbance and the update, that is, the weight value (W+ΔW). The weight DC level signal is also the output of the integrator 58, that is, the change amount of the weight value is determined by the product of the two input quantities of the lowermost second multiplier 56. One of the quantities is the opposite number of the differential quantity of the MSE loss, which represents the change trend of the loss under the current disturbance, and only pays attention to the positive and negative, respectively, indicating whether the error is getting smaller or larger. The other quantity represents the weight change amount. The product of the two is the weight change amount that reduces the error. For example, when the weight changes, if the opposite number of the differential quantity of the MSE loss is positive, it means that the error is getting smaller, and the weight should move in this direction. That is, the weight change amount should be a positive number multiplied by the original weight change amount. If the opposite number of the differential quantity of the MSE loss is negative, it means that the error is increasing, and the weight should move in the opposite direction of the weight change amount. That is, the weight change amount should be a negative number multiplied by the original weight change amount. In this way, the circuit can ensure that the weight value always moves in the direction that reduces the error, and completes the training of the neural network.

[0056] The neural network optimization circuit in the embodiment of the present disclosure improves the optimization speed of the neural network training device, and at the same time has the ability of fast inference training, low expansion cost, high parallelism, storage and calculation integration, and on-chip learning. Moreover, the neural network optimization circuit in the embodiment of the present disclosure is all implemented using analog circuits, without the need for a computer to participate in calculating the weight error value multiple times. There are no non-continuous signals such as switch signals and clock signals in the entire training process, and fast convergence is achieved under the guarantee of strict mathematical theory. The convergence speed is faster than that of existing optimizers.

[0057] In an alternative embodiment, the target neural network comprises a plurality of different sub-networks, each sub-network establishing a control chip, each pin on the input side of the control chip corresponding to an input neuron, and each pin on the output side of the control chip corresponding to an output neuron. The input neurons and the output neurons both process direct current level signals. In two adjacent sub-networks, the output neurons of the front sub-network are connected to the input neurons of the rear sub-network. When training the target training data in the target neural network, the MSE error signal is fed back to all the sub-networks of the target neural network through a wire.

[0058] Specifically, as shown in part B of FIG. 5, the structural framework of the circuit (analog neural network) for inference in the embodiment of the present disclosure is shown. The left side of the circuit is the input end, each pin corresponding to an input neuron, and the direct current level as the input signal. The right side of the circuit is the output end, each pin corresponding to an output neuron, and the direct current level as the output signal. The input signal is given by the computer-controlled D / A digital-to-analog converter. The output signal is converted into a digital signal by the A / D analog-to-digital converter and transmitted to the computer.

[0059] In part D of FIG. 5, the internal modular layout of the analog circuit neural network is shown. When the network is a large-scale network or has heterogeneity, the neural network can be divided into different sub-networks, each sub-network establishing a dedicated chip. In the forward propagation part, the output neurons of the front sub-network are connected to the input neurons of the rear sub-network. In the training part, the last error differential is fed back to all the sub-networks through a wire, and the training can be performed.

[0060] Therefore, the neural network optimization circuit in the embodiment of the present disclosure simultaneously trains all the target training data and optimizes the error of all the target training at the same time, has high parallelism, fast calculation speed, on-chip learning ability, and no non-continuous signals such as switch signals and clock signals in the training process, realizes fast convergence under the guarantee of strict mathematical theory, and all uses analog circuits, with low expansion cost. In addition, in the case where the second differentiator is placed from the perturbation source to the output of the adder, the original convergence direction of the circuit can be maintained, the requirement for the perturbation power is reduced, and the stability of the network is improved.

[0061] In the embodiment of the present disclosure, the input neurons and the output neurons both process direct current level signals. The circuit storage and calculation are both realized through weight levels, and are the same direct current level signals, thus belonging to the storage-computation integrated architecture. At the same time, the direct current level signals are beneficial to guarantee the continuity of the analog system signals, and thus the circuit can train the target neural network at high speed.

[0062] In an alternative embodiment, in FIGS. 1A and 1B, the input side of the target neural network is connected to the first conversion unit 51, and the output side of the target neural network is connected to the error calculation unit 59.

[0063] In an alternative embodiment, as shown in FIG. 3 and FIG. 5, the neural network optimization circuit further comprises a computer 50 and a third conversion unit 530, wherein the computer 50 is configured to send a digital signal corresponding to the target training data to the first conversion unit 51, send a digital signal corresponding to the label data of the target training data to the second conversion unit 52, and receive a predicted result signal corresponding to the target training data. The third conversion unit 530 is configured to convert the predicted result signal corresponding to the target training data into a digital signal and transmit it to the computer 50.

[0064] Specifically, the first conversion unit 51 and the second conversion unit 52 in the above are both D / A digital-to-analog converters, and the third conversion unit 530 is an A / D analog-to-digital converter. The computer 50 in FIG. 3 provides both input data and label data. The input data is provided to the first conversion unit 51, and the label data is provided to the second conversion unit 52. The computer in the embodiment of the present disclosure only has the function of providing data and does not participate in the weight error calculation. In the process of weight error calculation, it is realized through the circuit shown in FIG. 1A and FIG. 1B. Therefore, the neural network optimization circuit in the embodiment of the present disclosure is realized by using all analog circuits without the participation of computers or other digital circuits, which can take advantage of the fast speed of analog calculation.

[0065] In an alternative embodiment, when training the target neural network using the target training data, each weight change data corresponding to a different weight value is modified at the same time. Therefore, the neural network optimization circuit in the embodiment of the present disclosure has a high degree of parallelism. When the neural network is trained, all weights are modified at the same time, the time complexity is low, and the time complexity is only 1. The time complexity of only 1 means that all weight units are optimized at the same time. For each weight, the calculation process only needs to be calculated once to complete the optimization of the neural network.

[0066] In an alternative embodiment, in FIG. 1A and FIG. 1B, the adder 57 is a same-phase adder, which is configured to receive a plurality of weight change signals of a plurality of weight change data and a direct current level signal of a weight value corresponding to each weight change data, and transmit an updated weight change signal of each weight change data to the first multiplier 53 and the second differentiator 55, the plurality of weight change signals of the plurality of weight change data are the disturbance signals output by the introduced noise source. The second differentiator 55 is a same-phase differentiator, which is configured to transmit a change amount of the weight value corresponding to each weight change data over time to the second multiplier 56. The first multiplier 53 is configured to output a product of the first value (for example, but not limited to, 10v) direct current level signal and the weight change signal corresponding to each weight change data. The error calculation unit 59 includes a subtracter and a third multiplier. The first differentiator 54 is an opposite-phase differentiator. The subtracter is configured to subtract a second value (for example, but not limited to, 6v) direct current level signal of a true label corresponding to the label result level signal of the target training data from the product output by the first multiplier 53, and the third multiplier is configured to square the subtraction result. The opposite-phase differentiator is configured to differentiate the squared result and obtain an opposite number, so that the direct current level signal output by the opposite-phase differentiator represents the opposite number of the MSE differential amount. The second multiplier 56 is configured to receive the opposite number of the MSE differential amount and the change amount of the weight value corresponding to each weight change data over time, and provide the product output by the second multiplier 56 as the weight modification amount to the integrator 58. The integrator 58 is a proportional amplifier integrated integrator composed of an integrator and an amplifier.

[0067] Further, Multisim was used to build the neural network optimization circuits in Figures 1A and 1B. This circuit is a single-weight circuit. As shown in Figure 6, the first element in the first row is a multiplier, i.e., the first multiplier in Figures 1A and 1B. One end of its input, for example, a fixed DC level of 10V, represents the input signal x. The other end input comes from the device in the second row, representing the weight after adding perturbation. The output is the product of the two signals. The second element in the first row is a subtractor. One end of the subtractor's input comes from the first multiplier, and the other end comes from the second conversion unit. It subtracts from the actual label y, for example, a 6V level signal, and then performs a square calculation after passing through the third multiplier. The second and third elements in the first row form the circuit for calculating the MSE. The fourth element in the first row is an inverting differentiator, i.e., the first differentiator in Figures 1A and 1B, corresponding to the operation of differentiation and taking the inverse. Therefore, after the signal passes through the fourth element, the DC level signal represents the inverse of the differential of the MSE. The fifth element in the first row is the second multiplier, receiving the negative of the derivative of the MSE at one end and the weight change at the other. The product is provided as the weight modification to the integrator in the sixth element of the first row. The sixth element in the first row and the first element in the second row together form an integrator with proportional amplification, while the first element in the second row is an amplifier. Therefore, the output of the first element in the second row is the DC level of the weight signal. The second and third elements in the second row form a non-inverting adder, with the DC level weight signal at one input and the added noise source at the other. After passing through the non-inverting adder, the signal represents the weight after introducing noise. This weight is passed to both the first multiplier in the first row (mentioned above) and the fourth element in the second row (the second differentiator). The fourth and fifth elements in the second row form a non-inverting differentiator, which is passed as the weight change to the second multiplier in the fifth element of the first row, thus forming a closed loop. This circuit has been verified through simulation to achieve weight convergence.

[0068] Furthermore, there are several implementations in the circuit diagram that are not unique. These will be listed below. For the non-inverting integrator with proportional amplification, which is composed of the sixth element in the first row and the first element in the second row, this part can achieve both integration and proportional amplification by modifying the parameters of the surrounding circuit components of the sixth element in the first row and connecting the signal to the non-inverting input of the op-amp. This eliminates the need for the first element in the second row. Similarly, for the non-inverting adder composed of the second and third elements in the second row, the third element in the second row can be omitted by connecting the signal to the non-inverting input of the adder. Likewise, for the non-inverting differentiator composed of the fourth and fifth elements in the second row, the fifth element in the second row can be omitted by connecting the signal to the non-inverting input of the differentiator. Therefore, this circuit is a specialized form of the conceptual structure shown in Figures 1A and 1B, and its specific implementation is not unique.

[0069] Further, in FIG. 6, the circuit functions are introduced in the order of core elements. The first element on the left of the first row, for example, a 10V level signal, is input data, which is multiplied by the weight through the first multiplier to obtain the output y of the neural network. The output of the neural network is subtracted from, for example, a 6V level supervisory signal, and the MSE loss is calculated through the subtractor and the third multiplier. The inverse of the differential of the MSE loss is calculated through the first differentiator (inverse differential) as the input of the second multiplier. The second multiplier simultaneously receives the input of the weight change amount. The product of the two represents the weight change amount that minimizes the error loss. For example, if the inverse of the differential of the MSE loss is positive when the weight changes, it indicates that the error is decreasing, and the weight should move in this direction. That is, the weight change amount should be a positive number multiplied by the original weight change amount. If the inverse of the differential of the MSE loss is negative, it indicates that the error is increasing, and the weight should move in the opposite direction of the weight change amount. That is, the weight change amount should be a negative number multiplied by the original weight change amount. In this way, the circuit can ensure that the weight value always moves in the direction that reduces the error, completing the training of the neural network. The weight modification amount is the final weight DC level signal after passing through the integrator. Then, the weight DC level signal is disturbed by the noise source to become the weight signal with disturbance participating in the calculation. At the same time, the weight signal with disturbance is provided to the position of the weight change amount required in the calculation through the second differentiator.

[0070] Therefore, after the circuit is powered on, the weight DC level signal is immediately modified until the output value y of the circuit is always equal to the supervisory signal, the circuit reaches a steady state, and the training is completed.

[0071] In a specific example, the neural network optimization circuit in the embodiment of the present disclosure can realize fast inference training. Fast inference refers to how long the neural network takes to get a stable output after being given an input. Since the weight does not change in the inference stage, each weight unit only performs the calculation of the multiplier. Under ideal device conditions, the entire neural network inference time is only constrained by the speed of light, and under non-ideal device conditions, it is affected by device delay. Generally, it can be completed within ns or sub-ns time. The theoretical guarantee of fast training is that the weight training effect is equivalent to BP (back propagation), and the modification direction of the weight is the unbiased estimate of the gradient of the loss function with respect to the weight. When the input data and label data are externally given, the weight level of the neural network will converge, and the convergence direction is the negative direction of the gradient of the loss function with respect to the weight, that is, the weight modification direction of BP. Therefore, as long as the neural network can be trained using BP, theoretically, it can be trained using the circuit proposed in the embodiment of the present disclosure, and the training results are consistent. If the problem to be trained is a convex problem, the circuit can certainly converge to the optimal solution. The unbiased theoretical proof process is as follows:

[0072] Based on the weight disturbance algorithm, the transfer function of the circuit in FIG. 1A is as follows:

[0073] where W ∈ R N×1 is a weight parameter, L ∈ R is a loss function, ξ ∈ R N×1 is a disturbance, ξ = ∫δdt, δ ~ N(0, I N )O

[0074] Using the chain rule, we have the following formula:

[0075] where,

[0076] When ξ is small enough, i.e., satisfies , we have the following formula:

[0077] At this time,

[0078] n is the number of estimates of the gradient. In the analog circuit, the system is a continuous system, so in an infinitely short time step, since the electric field is established at the speed of light, in the case of a small enough circuit scale, it can be considered that n is infinite. Therefore, at any time, the amount of change of the weight satisfies the above formula (equivalent to BP).

[0079] The neural network optimization circuit as shown in FIG. IB is to place the second differentiator 55 from the disturbance source to the output position of the adder 57. The transfer function of the circuit is as follows:

[0080] The convergence of the circuit is proved as follows:

[0081] Let

[0082] The significance of this operation is to maintain the original convergence direction of the circuit, reduce the requirement for disturbance power, and improve the stability of the network. For fast training ability, since in the analog circuit, the system is a continuous system, it can be considered that the learning rate is infinitely small. According to the convergence theorem, the continuous convergence of the circuit can be guaranteed; and because the electric field is established at the speed of light, in the case of a small enough circuit scale, it can be considered that the iteration speed (the number of iterations per unit time) is infinite. Therefore, under the ideal condition of the device, the circuit can theoretically achieve extremely fast training speed.

[0083] According to another embodiment of the present disclosure, a neural network optimization circuit is provided as shown in FIGS. 7A and 7B, applied to a target neural network, the neural network optimization circuit comprises: a first conversion unit 11, a second conversion unit 12, a first multiplier 13, a first differentiator 14, a second differentiator 15, a second multiplier 16, a summer 17, an integrator 18, an error calculation unit 19, and a third multiplier 10. The neural network optimization circuit as shown in FIGS. 7A and 7B is a basic training unit in the embodiment of the present disclosure, i.e., the weight of the neural network. In FIGS. 7A and 7B, the dashed box represents an arbitrary target neural network, which can be a fully connected neural network.

[0084] In actual design, according to different perturbation types and introduction modes of perturbation signals, the basic unit of the analog circuit neural network can be divided into several different basic structures. The neural network optimization circuit in the embodiment of the present disclosure is suitable for the scene of a single piece of data, such as a fully connected neural network, fully considers the constraints of the network, and maximizes the convergence efficiency.

[0085] In the embodiment of the present disclosure, in FIGS. 7A and 7B, a two-layer 2x2 fully connected neural network is taken as an example. The left two circles are input neurons, the input signal is a direct current level, the output signal is also a direct current level, and the input and output neurons are fully connected by four weights. The connection between the left and right neurons is a solid line. The analog circuit on the lower side of FIGS. 7A and 7B shows the internal structure of the weight.

[0086] In FIGS. 7A and 7B, the first conversion unit 11 is used to convert the target training data into a target direct current level signal corresponding to the target training data.

[0087] Specifically, as shown in FIG. 8, the first conversion unit 11 in the embodiment of the present disclosure can be a D / A digital-to-analog converter, which converts the target training data into a target direct current level signal corresponding to the target training data. The target training data can be a data sample set of different types, and each data in the data sample set is converted into a target direct current level signal, for example, the target training data is represented by M, M={a1, a2, a3,... a n}, and each data in the data sample set is converted into a target direct current level signal. In the embodiment of the present disclosure, the target training data is the input training data. In the embodiment of the present disclosure, converting the target training data into a target direct current level signal corresponding to the target training data as the input signal of the neural network is beneficial to guarantee the continuity of the analog system signal, and further enables the circuit to train the target neural network at a high speed.

[0088] The second conversion unit 12 is used to convert the label data corresponding to the target training data into a label result level signal.

[0089] Specifically, in FIG. 8, the second conversion unit 12 in the embodiment of the present disclosure can be a D / A digital-to-analog converter, through which the label data corresponding to the target training data is converted into a label result level signal. The label result level signal of the target training is the label data level signal, which is simultaneously given in FIGS. 7A and 7B. For example, the target training data is denoted as M, M = {a1, a2, a3,... a n}, and each of the n data in the data sample set is converted into the target data level signal x and the label data level signal y.

[0090] In FIGS. 7A and 7B, the first multiplier 13 is configured to multiply the target DC level signal corresponding to the target training data and the adder output signal to output a prediction result signal corresponding to the target training data.

[0091] Specifically, in FIGS. 7A and 7B, when the inference target neural network is calculated by using a single weight, the target DC level signal corresponding to the target training data is multiplied by the weight value level signal at the output end of the adder 17 to obtain an output value , and the inference can be completed. For example, the target DC level signal x corresponding to the target training data is multiplied by the adder output signal (weight value level signal) to output a prediction result signal corresponding to the target training data.

[0092] In FIGS. 7A and 7B, the error calculation unit 19 is configured to calculate an error signal between the prediction result signal and the label result level signal of the target training data, for example, but not limited to, an MSE error signal, a cross-entropy error signal, and the like. Hereinafter, the MSE error signal is taken as an example for description.

[0093] In FIGS. 7A and 7B, the error calculation unit 19 and the first differentiator 14 can be an MSE differential unit (i.e., the DMSE error calculation unit shown in FIG. 8), which simultaneously receives the label data DC level output by the D / A converter of the PC computer. The MSE differential unit internally calculates the inverse of the MSE loss differential, which is output as a wire, and then fed back to the analog circuit neural network. From this, the circuit forms a closed loop, and the analog circuit neural network weight converges to the direction of minimizing the error, thereby completing the training.

[0094] In FIGS. 7A and 7B, the first differentiator 14 is configured to receive the error signal and output a first differentiator output signal. As described above, the error signal includes, but is not limited to, an MSE error signal, a cross-entropy error signal, and the like. Hereinafter, the MSE error signal is taken as an example for description.

[0095] Specifically, in FIG. 7A and FIG. 7B, the target neural network is trained at the same time given the input data level signal x and the label data level signal y, the output signal of the circuit The MSE loss is calculated with y and the opposite of the change amount of the MSE loss is taken, and then connected to the first differentiator 14 and the second multiplier 16 after the first differentiator 14.

[0096] In FIG. 7A and FIG. 7B, the second differentiator 15 is used to receive the adder output signal or the third multiplier output signal, and output the second differentiator output signal. The third multiplier output signal is generated based on the perturbation signal of each weight and the target DC level signal corresponding to the target training data. The second multiplier 16 is used to receive the first differentiator output signal and the second differentiator output signal, and output the second multiplier output signal. The integrator 18 is used to receive the second multiplier output signal and output the integrator output signal; the adder 17 is used to receive the third multiplier output signal and the integrator output signal; the third multiplier 10 is used to receive the target DC level signal corresponding to the target training data and the perturbation signal of each weight, and output the third multiplier output signal; wherein the weight corresponding to the connection relationship between each neuron of each layer in the target neural network and the same neuron of the next layer comes from the same perturbation signal.

[0097] Specifically, in FIG. 7A and FIG. 7B, the target neural network is trained at the same time given the input data level signal x and the label data level signal y, the output signal of the circuit The inference can be completed. During training, the input data level signal x and the label data level signal y are given at the same time. The output signal of the circuit The MSE loss is calculated with y and negated, which is the opposite of the change in the MSE loss, and is connected to the first differentiator 14 and the second multiplier 16 after the first differentiator 14. The other end of the second multiplier 16 is connected to the output end of the second differentiator 15. The noise (i.e., the disturbance signal of each weight) is connected to the input end of the third multiplier 10, and the target DC level signal corresponding to the target training data is connected to the other input end of the third multiplier 10. The output end of the third multiplier 10 is connected to the adder 17, so that the output of the adder 17 is the weight change signal after disturbance and update, that is, the weight value (W+ΔW). The weight DC level signal is also the output of the integrator 18, that is, the change in the weight value is determined by the product of the two input quantities of the lowermost second multiplier 16. One of the two quantities is the opposite of the differential of the MSE loss, which represents the change trend of the loss under the current disturbance, and only pays attention to the positive and negative, respectively, indicating whether the error is getting smaller or larger. The other quantity represents the weight change. The product of the two is the weight change that reduces the error. For example, when the weight changes, if the opposite of the differential of the MSE loss is positive, it means that the error is getting smaller, so the weight should move in this direction. That is, the weight change should be a positive number multiplied by the original weight change. If the opposite of the differential of the MSE loss is negative, it means that the error is increasing, so the weight should move in the opposite direction of the weight change. That is, the weight change should be a negative number multiplied by the original weight change. In this way, the circuit can ensure that the weight value always moves in the direction that reduces the error, completing the training of the neural network.

[0098] The neural network optimization circuit in the embodiments of the present disclosure improves the optimization speed of the neural network training device, and at the same time has the ability of fast inference training, low expansion cost, high parallelism, storage and calculation integration, and on-chip learning. Moreover, the neural network optimization circuit in the embodiments of the present disclosure is all implemented using analog circuits, without the need for a computer to participate in calculating the weight error value multiple times. There are no non-continuous signals such as switch signals and clock signals in the entire training process, and fast convergence is achieved under the guarantee of strict mathematical theory. The convergence speed is faster than that of the existing optimizer (the analog training speed of simulink is 147,900,000 times that of GPU).

[0099] In an optional implementation, the target neural network in the embodiments of the present disclosure includes a plurality of different subnets, each subnet establishing a control chip, each pin on the input side of the control chip corresponding to an input neuron, and each pin on the output side of the control chip corresponding to an output neuron. The input neurons and the output neurons all process DC level signals. In two adjacent subnets, the output neurons of the front-side subnet are connected to the input neurons of the rear-side subnet. When training the target training data in the target neural network, the MSE error signal is fed back to all the subnets of the target neural network through a wire.

[0100] Specifically, as shown in part B in FIG. 9, a structural framework of the circuit (analog neural network) in the embodiment of the present disclosure for inference is shown. The left side of the circuit is the input end, each pin corresponds to an input neuron, and the direct current level is the input signal. The right side of the circuit is the output end, each pin corresponds to an output neuron, and the direct current level is the output signal. The input signal is given by the computer control D / A digital-to-analog converter. The output signal is converted into a digital signal by the A / D analog-to-digital converter and transmitted to the computer.

[0101] In part D in FIG. 9, the internal modular layout of the analog circuit neural network is shown. When the network is a large-scale network or has heterogeneity, the neural network can be divided into different subnets, and each subnet establishes a dedicated chip. The forward propagation part, the output neurons of the front subnets are connected to the input neurons of the rear subnets. The training part and the last error differential component wire feedback to all subnets can be trained.

[0102] For FIGS. 7A and 7B, it is applied to a single data scenario. That is, the dashed box is a 2x2 neural network. At this time, the left two circles are input neurons, each inputting a level signal as input data x. When x is only one data, it is called a single data scenario. In this scenario, the network can perform inference and training on a single data. For example, in a fully connected neural network, the weight W ij represents the weight connecting the i-th input neuron and the j-th output neuron, W 12 , W 22 ,... W n2 The same amount of disturbance is introduced to the weight input, assuming that the input layer and the output layer neurons are n, and the total disturbance introduced by the full connection neural network in this layer is n.

[0103] Therefore, the neural network optimization circuit in the embodiment of the present disclosure optimizes the error of single target training in the scenario of using single target training data, has high parallelism, fast calculation speed, on-chip learning ability, and no non-continuous signals such as switch signals and clock signals in the training process, realizes fast convergence under the guarantee of strict mathematical theory, uses all analog circuits, and has low expansion cost. Moreover, by adding a third multiplier before the adder and processing single target training data through the full connection neural network, that is, by considering the constraint of the network through the weight corresponding to the connection relationship between each neuron in each layer of the full connection neural network and the same neuron in the next layer with the same disturbance mode, the total disturbance is reduced, and the convergence efficiency is maximized. In addition, the second differentiator is placed after the disturbance source to the position of the adder output, which can maintain the original convergence direction of the circuit, reduce the requirement for disturbance power, and thus improve the stability of the network.

[0104] In the embodiments of the present disclosure, the input neurons and the output neurons all process direct current level signals. The circuit storage and calculation are both implemented by weight levels, and the same direct current level signals, thus belonging to the storage-computing integrated architecture. Meanwhile, the direct current level signals are beneficial to ensuring the continuity of the analog system signals, and thus the circuit can train the target neural network at high speed.

[0105] In an alternative embodiment, in FIGS. 7A and 7B, the input side of the target neural network is connected with the first conversion unit 11, and the output side of the target neural network is connected with the error calculation unit 19.

[0106] In an alternative embodiment, as shown in FIGS. 8 and 9, further comprising a computer 20 and a third conversion unit 130. The computer 20 is configured to send the digital signal corresponding to the target training data to the first conversion unit 11, send the digital signal corresponding to the label data of the target training data to the second conversion unit 12, and receive the predicted result signal corresponding to the target training data. The third conversion unit 130 is configured to convert the predicted result signal corresponding to the target training data into a digital signal and transmit the digital signal to the computer 20.

[0107] Specifically, the first conversion unit 11 and the second conversion unit 12 in the above are both D / A digital-to-analog converters, and the third conversion unit 130 is an A / D analog-to-digital converter. The computer 20 in FIG. 9 provides input data and label data at the same time. The input data is provided to the first conversion unit 11, and the label data is provided to the second conversion unit 12. The computer in the embodiments of the present disclosure only has the function of providing data and does not participate in the weight error calculation. In the weight error calculation process, it is implemented by the circuit shown in FIGS. 7A and 7B. Therefore, the neural network optimization circuit in the embodiments of the present disclosure is all implemented by analog circuits without the participation of computers or other digital circuits, and can take advantage of the fast analog calculation speed.

[0108] In an alternative embodiment, when the target neural network is trained using the target training data, the different weight values corresponding to each weight change data are modified at the same time. Therefore, the neural network optimization circuit in the embodiments of the present disclosure has a high degree of parallelism. When the neural network is trained, all weights are modified at the same time, the time complexity is low, and the time complexity is only 1. The time complexity of 1 means that all weight units are optimized at the same time. For each weight, the calculation process only needs to be calculated once to complete the optimization of the neural network.

[0109] In a specific example, the neural network optimization circuit in the embodiments of the present disclosure can realize fast inference training. Fast inference refers to how long the neural network takes to get stable output after being given input. Since the weights do not change in the inference stage, each weight unit only performs multiplication calculation. In ideal device conditions, the entire neural network inference time is only constrained by the speed of light, and in non-ideal device conditions, it is affected by device delay. Generally, it can be completed in ns or sub-ns level time. The theoretical guarantee of fast training is that the weight training effect is equivalent to BP (back propagation), and the modification direction of the weight is the unbiased estimate of BP. When the external input data and label data are given, the weight level of the neural network will converge, and the convergence direction is the negative direction of the gradient of the loss function with respect to the weight, that is, the weight modification direction of BP. Therefore, as long as the neural network that can be trained using BP, theoretically, it can be trained using the circuit proposed in the embodiments of the present disclosure, and the training results are consistent. If the problem to be trained is a convex problem, the circuit can certainly converge to the optimal solution. The unbiased theoretical proof process is as follows:

[0110] In the neural network optimization circuit in the embodiments of the present disclosure, a third multiplier 10 is added before the adder 17 in FIGS. 7A and 7B, and the target training data corresponding to the target direct current level signal and the perturbation signal of each weight are transmitted to the third multiplier 10 through the third multiplier 10. Based on the node perturbation algorithm, the transfer function of the circuit in FIG. 7A is as follows:

[0111] where W ∈ R o×i is the weight parameter, L ∈ R is the loss function, and ξ ∈ R o×1 is the perturbation, ξ = ∫δdt, δ ~ N(0, I o ).

[0112] Using the chain rule, the following formula can be obtained:

[0113] where,

[0114] h = Wx

[0115] Similarly, at any time, the change of the weight satisfies the above formula (equivalent to BP).

[0116] As shown in the neural network optimization circuit in FIG. 7B, the second differentiator is placed after the perturbation source to the position of the adder output. That is, it is proved by the following formula:

[0117] The convergence is proved as follows:

[0118] Let

[0119] The operation can keep the original convergence direction of the circuit, reduce the requirement for perturbation power, and improve the stability of the network.

[0120] For the fast training capability, since the system is a continuous system in the analog circuit, the learning rate can be considered to be infinitely small, and according to the convergence theorem, the continuous convergence of the circuit can be ensured; and since the electric field is established at the speed of light, in the case of a small enough circuit scale, the iteration speed (the number of iterations per unit time) can be considered to be infinitely large. Therefore, under the ideal condition of the device, the circuit can theoretically achieve extremely fast training speed.

[0121] Next, the technical effects based on the embodiment of the present disclosure as shown in FIG. 7B are described exemplarily. Similar technical effects can also be obtained based on other embodiments of the present disclosure.

[0122] In the embodiment of the present disclosure, as shown in FIG. 10, a three-layer 2x2x2 neural network with an activation function built in simulink is shown. As shown in FIG. 11, the loss curves of two data are processed. In the experimental results, the training of the two data is completed within 1 ns. Among them, the data is switched 4-9 times. Under the same data and the same network, the GPU training is used: an average of 12 steps is needed, and the average time consumption is 13.6 ms. The circuit involved in the embodiment of the present disclosure is 13,600,000 times faster than the digital circuit GPU. In order to ensure the rigor of the experiment, the time of the GPU only counts the time of the forward propagation and the backward propagation, and does not include the GPU initialization, data initialization, and optimizer initialization time. In addition, the devices involved in the simulink simulation are ideal devices, and the delay, error, and noise factors are not considered. Moreover, the GPU is universal, and it can be applied to networks of different structures, so the GPU may sacrifice part of the speed for universality. The special digital circuit may be faster. But even the special digital circuit will not be so many orders of magnitude faster, so this experimental result can prove that the analog circuit is much faster than the GPU, as shown in Table 1 below.

[0123] Table 1

[0124] In order to further ensure the rigor, different cuda versions, different GPUs, and different operating systems are compared in the experiment, and similar experimental results are obtained.

[0125] As shown in FIG. 12, the change of the solution in the training process is shown. It can be seen from the figure that the solution is slid along the steepest descent direction to the lowest point. This is consistent with the conclusion of the proof of the unbiased theory. As shown in FIG. 13, the circuit completes the training of the XOR task within 10 ns. It is also proved that the circuit has a faster training speed. The XOR task is also a very classic task in neural networks, which requires multiple layers of nonlinear networks to learn. The circuit involved in the embodiments of the present disclosure also learns the XOR task within 10 ns. This shows that the circuit has the ability to expand to other neural network structures. For example, convolutional neural networks, ResNet, Transformer, GPT, and the like.

[0126] The low expansion cost mainly considers the complexity of the optimization unit and the influence of networking on efficiency. In terms of the complexity of the optimization unit, the circuit involved in the embodiments of the present disclosure is an infinite repetition of the weight circuit structure shown in FIGS. 1A and 1B and FIGS. 7A and 7B in the actual chip design process, and the circuit structure is simple. In contrast, the complexity of the GPU mainly reflects the following aspects: 1, complex programming and control logic. The GPU contains a complex control unit inside, which is used to manage the scheduling of tasks, memory management, error correction, and other system-level functions. 2, complex data path: the GPU is designed with a complex data path, which can handle the movement of a large amount of data, including data caching, prefetching, and efficient data transmission mechanisms. 3, complex thermal management and power management: high-performance GPUs require complex thermal management systems and power management strategies to cope with heat and power consumption under high load.

[0127] In terms of networking efficiency, the circuit in the embodiments of the present disclosure can be expanded using the structures shown in FIGS. 1A and 1B and FIGS. 7A and 7B. The output neurons of the forward-propagating front subnetwork are connected to the input neurons of the back subnetwork, and the last error differential is fed back to all subnetworks. In contrast, GPUs are much more complex when expanding the network. The main problems are as follows: 1. Data transfer delay. Cross-GPU communication: In the model parallel setting, different model parts are assigned to different GPUs. This means that the data generated by each GPU during the calculation process, such as activation values and gradients, needs to be passed to other GPUs. When GPUs are connected through a PCIe bus or through a network (in the case of cross-node), data transfer will cause significant delay. Bandwidth limitation: The speed of data transfer is limited by the hardware bandwidth. Even high-speed connections such as InfiniBand or NVLink can become a bottleneck when the data volume is large. 2. Synchronization overhead. Barrier synchronization: In parallel processing, it is necessary to ensure that all processing units have completed the current step before proceeding to the next step. This synchronization usually requires the use of a barrier synchronization mechanism, which ensures that all GPUs reach the same state before starting the next calculation cycle. Each synchronization causes all GPUs to wait for the slowest one, introducing delay. Consistency and state management: During parallel processing, it is necessary to maintain the consistency of data, which may involve additional communication and processing overhead to ensure that the data state of all processing units is consistent. 3. Ratio of communication to computation. Compute / communication ratio: This is an important indicator of parallel efficiency, which describes the ratio of the time required for execution to the time required for communication. In an ideal case, we want this ratio to be as high as possible, meaning that most of the time is spent on actual computation rather than data transfer. However, in many model parallel scenarios, especially when the model is large or distributed across multiple computing nodes, this ratio may be low.

[0128] High parallelism refers to the proportion of parameters being optimized simultaneously at the same time to the total number of parameters. The higher the proportion, the higher the parallelism of the computing hardware. The higher the parallelism, the higher the computing efficiency. According to Amdahl's Law, the proportion of tasks that can be executed in parallel is 1, the number of computing resources is the number of weights N, and the Amdahl speedup ratio is N. The advantage of high parallelism is mainly reflected in the time complexity, as shown in Table 2.

[0129] Table 2 Time complexity

[0130] L is the number of layers of the neural network, and N is the number of hidden layer neurons.

[0131] In the embodiments of the present disclosure, all weights of the analog circuit are optimized at the same time, so the time complexity is not affected by the size of the network. The optimization speed of the digital circuit will slow down as the size of the network increases.

[0132] Processing-In-Memory (PIM) is a technology that performs computing tasks directly in memory devices. The circuit architecture of the present disclosure belongs to the PIM architecture because the calculation of each weight and the storage are the same physical quantity, and the output level of the integrator determines it. This architecture breaks the boundary between the processor and the storage in the traditional architecture, allowing data to be processed during the storage phase, reducing the need for data transmission between the processor and the memory. The present disclosure belongs to the PIM architecture and has its advantages. PIM has several significant advantages, especially for data-intensive applications and large-scale data processing scenarios. 1. Reduce data transmission requirements: In traditional computing architectures, the CPU needs to frequently read and write data from the memory. This data movement can cause significant energy consumption and delay. PIM design significantly reduces data movement by processing data directly in memory, thereby reducing energy consumption and improving data processing speed. 2. Reduce energy consumption: Data transmission is one of the main sources of energy consumption in modern computing systems. PIM technology can effectively reduce the energy consumption of the entire system by reducing data transmission on the system bus and other interfaces. 3. Improve performance: Because the speed of data processing is limited by the speed of data transmission, the CPU in the traditional architecture often idles while waiting for data. PIM can reduce the waiting time of the processor, allowing faster completion of data processing tasks, thereby improving overall computing performance. 4. Scalability and flexibility: PIM technology provides greater flexibility, allowing customization of memory and computing resource configurations according to application needs. This allows it to be optimized for specific applications such as big data analysis and machine learning. 5. Simplify system design: By moving computing tasks to memory, the overall hardware design of the system can be simplified, reducing dependence on high-speed data buses and other high-cost hardware, and possibly reducing the physical size of the system. 6. Improve parallel processing capabilities: PIM architecture allows parallel execution of computing tasks in multiple memory modules, greatly enhancing parallel processing capabilities. This is particularly important for applications that require high parallelism. 7. Improve data processing security: By processing data directly in memory, data transmission within the system can be reduced, reducing the risk of potential data leakage and enhancing data security.

[0133] On-chip learning is a concept that involves implementing learning and inference tasks directly on a microchip, typically a specialized integrated circuit or processor. The invention is characterized by its fast training, allowing real-time training on edge devices, enabling on-chip learning. This approach is particularly important in the field of artificial intelligence, focusing on integrating the training and execution of machine learning models directly onto hardware devices, rather than relying on external large-scale computing systems or cloud infrastructure. On-chip learning is an important component of edge computing and intelligent hardware design, significantly improving data processing speed and efficiency while reducing data transmission requirements and latency.

[0134] In summary, the neural network optimization circuit in the embodiments of the present disclosure has the following advantages:

[0135] 1. Fast inference and training: The neural network is trained and inferred using analog circuits, while maintaining the continuity of analog system signals, allowing the circuit to train the neural network at high speed.

[0136] 2. Low expansion cost: Neural networks can be expanded through direct connection, without the need for signal conversion (such as nvlink), encoding and decoding operations between circuits. Secondly, the analog circuit neural network integrates storage and calculation, and the weight structure is simple, with low cost (compared to the GPU storage and calculation separation structure).

[0137] 3. High parallelism: When training the neural network, all weights are modified simultaneously, with low time complexity. The time complexity is only 1.

[0138] 4. Storage and calculation integration: Circuit storage and calculation are achieved through weight levels, and the same direct current level signal is used, so it belongs to the storage and calculation integration architecture.

[0139] 5. On-chip learning: There are few edge computing devices that can perform on-chip learning. Current on-chip learning devices generally have low training speed and can only train part of the weights. The embodiments of the present disclosure can achieve on-chip learning of all weights.

[0140] 6. Fast convergence speed: No clock-driven method is required to drive the circuit.

[0141] 7. The second differentiator is placed after the perturbation source and at the output of the adder, which can maintain the original convergence direction of the circuit, reduce the requirement for perturbation power, and improve the stability of the network.

[0142] 8. By adding the weights of each neuron in each layer of the fully connected neural network to the same neuron in the next layer, the network constraints are considered, the total perturbation is reduced, and the convergence efficiency is maximized.

[0143] While embodiments of the application have been described in connection with the preferred embodiments of the various figures, those of ordinary skill in the art will appreciate that various modifications and changes can be made without departing from the spirit and scope of the application, and that such modifications and changes fall within the scope of the appended claims.

Claims

1. A neural network optimization circuit, comprising: The application is applied to a target neural network, and comprises: a first conversion unit, configured to convert target training data into a target direct current level signal corresponding to the target training data; a second conversion unit, configured to convert label data corresponding to the target training data into a label result level signal; a first multiplier, configured to output a prediction result signal corresponding to the target training data based on the target direct current level signal corresponding to the target training data and an adder output signal; an error calculation unit, configured to calculate an error signal between the prediction result signal and the label result level signal of the target training data; a first differentiator, configured to receive the error signal and output a first differentiator output signal; a second differentiator, configured to receive the adder output signal or a plurality of weight change signals of a plurality of weight change data and output a second differentiator output signal; a second multiplier, configured to receive the first differentiator output signal and the second differentiator output signal and output a second multiplier output signal; an integrator, configured to receive the second multiplier output signal and output an integrator output signal; an adder, configured to receive the plurality of weight change signals of the plurality of weight change data and the integrator output signal and output the adder output signal; wherein each weight change signal corresponds to a different weight value, and each weight change data represents a change amount of a weight value corresponding to the weight change data over time.

2. The neural network optimization circuit of claim 1, wherein, The adder is a same-phase adder, The same-phase adder is configured to receive a plurality of weight change signals of the plurality of weight change data and a direct current level signal of the weight value corresponding to each weight change data, and transmit an updated weight change signal of each weight change data to the first multiplier and the second differentiator, wherein the plurality of weight change signals of the plurality of weight change data are disturbance signals output by a noise source.

3. The neural network optimization circuit of claim 2, wherein, The second differentiator is a same-phase differentiator; The same-phase differentiator is configured to transmit the change amount of the weight value corresponding to each weight change data over time to the second multiplier.

4. The neural network optimization circuit of claim 3, wherein, The first multiplier is configured to output a product of the first numerical direct current level signal and the updated weight change signal of each weight change data.

5. The neural network optimization circuit of claim 4, wherein, The error calculation unit comprises a subtractor and a third multiplier, The first differentiator is an inverse-phase differentiator; The subtractor subtracts a second numerical direct current level signal of a true label corresponding to the label result level signal of the target training data from the product, the third multiplier squares the subtraction result, and the inverse-phase differentiator differentiates the squared result and obtains an inverse number, wherein a direct current level signal output by the inverse-phase differentiator represents the inverse number of the differential amount; The second multiplier receives the inverse number of the differential amount and the change amount of the weight value corresponding to each weight change data over time, and provides the second multiplier output product as a weight modification amount to the integrator; The integrator is a proportional-amplification integrator composed of an integrator and an amplifier.

6. The neural network optimization circuit of claim 1, wherein, The target neural network comprises a plurality of different subnets, each subnet establishing a control chip, each pin on the input side of the control chip corresponding to an input neuron, and each pin on the output side of the control chip corresponding to an output neuron. The input neuron and the output neuron both process direct current level signals. In the two adjacent subnets, the output neuron of the front subnet is connected with the input neuron of the rear subnet. When the target training data is used to train the target neural network, the error signal is fed back to all the subnets of the target neural network through a wire.

7. The neural network optimization circuit of claim 1, wherein, The target neural network is connected with the first conversion unit on the input side, and is connected with the error calculation unit on the output side.

8. The neural network optimization circuit of claim 1, wherein, Further comprising: A computer is configured to send a digital signal corresponding to the target training data to the first conversion unit, send a digital signal corresponding to the label data of the target training data to the second conversion unit, and receive a prediction result signal corresponding to the target training data.

9. The neural network optimization circuit of claim 1, wherein, When the target training data is used to train the target neural network, each weight change data corresponding to a different weight value is modified.

10. The neural network optimization circuit of any one of claims 1 to 9, wherein, The target neural network comprises a Transformer neural network, a CNN convolutional neural network, an RNN recurrent neural network, or a fully connected neural network.

11. A neural network optimization circuit, comprising: Applied to a target neural network, comprising: A first conversion unit is configured to convert the target training data into a target direct current level signal corresponding to the target training data. A second conversion unit is configured to convert the label data corresponding to the target training data into a label result level signal. A first multiplier is configured to multiply the target direct current level signal corresponding to the target training data and the adder output signal, and output a prediction result signal corresponding to the target training data. An error calculation unit is configured to calculate an error signal between the prediction result signal and the label result level signal of the target training data. A first differentiator is configured to receive the error signal and output a first differentiator output signal. A second differentiator is configured to receive a third multiplier output signal or an adder output signal, and output a second differentiator output signal. A second multiplier is configured to receive the first differentiator output signal and the second differentiator output signal, and output a second multiplier output signal. An integrator is configured to receive the second multiplier output signal and output an integrator output signal. An adder is configured to receive the third multiplier output signal and the integrator output signal. A third multiplier is configured to receive the target direct current level signal corresponding to the target training data, a perturbation signal of each weight, and output a third multiplier output signal. The connection relationship between each neuron of each layer in the target neural network and the same neuron of the next layer corresponds to a weight from the same perturbation signal.

12. The neural network optimization circuit of claim 11, wherein, The target neural network comprises a plurality of different subnets, each subnet establishing a control chip, each pin on the input side of the control chip corresponding to an input neuron, and each pin on the output side of the control chip corresponding to an output neuron.

13. The neural network optimization circuit of claim 12, wherein, The input neuron and the output neuron both process direct current level signals.

14. The neural network optimization circuit of claim 12, wherein, In the two adjacent subnets, the output neurons of the front side subnet are connected with the input neurons of the back side subnet.

15. The neural network optimization circuit of claim 12, wherein, When training the target neural network using the target training data, the error signal is fed back to all subnets of the target neural network through a wire.

16. The neural network optimization circuit of claim 11, wherein, The target neural network is connected with the first conversion unit at the input side, and connected with the error calculation unit at the output side.

17. The neural network optimization circuit of claim 11, wherein, Further comprising: A computer for sending a digital signal corresponding to the target training data to the first conversion unit, sending a digital signal corresponding to the label data of the target training data to the second conversion unit, and receiving a prediction result signal corresponding to the target training data.

18. The neural network optimization circuit of claim 17, wherein, Further comprising: A third conversion unit for converting the prediction result signal corresponding to the target training data into a digital signal and transmitting it to the computer.

19. The neural network optimization circuit of claim 11, wherein, When training the target neural network using the target training data, the different weight values corresponding to each weight change data are modified at the same time.

20. The neural network optimization circuit of any one of claims 11-19, wherein, The target neural network comprises a fully connected neural network.

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