Semiconductor device and manufacturing method

Abstract

Provided is a semiconductor device which comprises: a semiconductor substrate that has an upper surface and a lower surface; and an upper surface electrode that is provided above the upper surface of the semiconductor substrate and contains aluminum. The average particle diameter of the upper surface electrode is 30 µm or more, and the (111) orientation ratio of the crystal structure is 98% or more. With respect to the semiconductor device, the minimum value of the particle diameter of the upper surface electrode may be 5 µm or more. With respect to the semiconductor device, the maximum value of the particle diameter of the upper surface electrode may be 140 µm to 200 µm inclusive.

Description

Semiconductor device and manufacturing method

[0001] The present invention relates to a semiconductor device and a manufacturing method.

[0002] A method for filling contact holes involves controlling the wafer heating temperature during sputtering to control the grain size of the formed film (see, for example, Patent Document 1). [Prior Art Literature] [Patent Document 1] JP 2019-145667 A General disclosure

[0003] (Problem to be Solved) It is preferable that the upper surface (front surface) electrode of the semiconductor device can fill the contact hole and has a good surface flatness. (Means for Solving the Problem)

[0004] In order to solve the above problems, one aspect of the present invention provides a semiconductor device including a semiconductor substrate having an upper surface and a lower surface. The semiconductor device may include an upper electrode containing aluminum provided above the upper surface of the semiconductor substrate. In any of the above semiconductor devices, the upper electrode may have an average grain size of 30 μm or more and a (111) orientation ratio of the crystal structure of 98% or more.

[0005] In any of the above semiconductor devices, the minimum grain size of the upper electrode may be 5 μm or more.

[0006] In any of the above semiconductor devices, the maximum grain size of the upper electrode may be 140 μm or more and 200 μm or less.

[0007] In any of the above semiconductor devices, the upper electrode may have a thickness of 3 μm or more.

[0008] In any of the above semiconductor devices, the upper electrode may have a single crystal grain formed from the upper surface to the lower surface in the depth direction.

[0009] In any of the above semiconductor devices, the upper electrode may be made of an aluminum-silicon alloy.

[0010] Any of the above semiconductor devices may further include an interlayer insulating film provided on the upper surface of the semiconductor substrate. In any of the above semiconductor devices, contact holes may be formed in the interlayer insulating film. In any of the above semiconductor devices, the average grain size may be 20 times or more the width of the contact holes.

[0011] In a second aspect of the present invention, there is provided a method for manufacturing a semiconductor device. In the manufacturing method, the semiconductor device may include a semiconductor substrate having an upper surface and a lower surface, and an upper surface electrode containing aluminum provided above the upper surface of the semiconductor substrate. In the manufacturing method, the temperature of the semiconductor substrate may be 440° C. or higher and 480° C. or lower in an electrode formation step of forming the upper surface electrode.

[0012] In any of the above manufacturing methods, in the electrode formation step, the upper electrode may be formed by sputtering. In the sputtering step in any of the above manufacturing methods, the ultimate vacuum of a chamber storing the semiconductor substrate may be 1×10 －4 It may be smaller than Pa.

[0013] In any of the above manufacturing methods, the electrode forming step may include a first sputtering step of forming a substrate-side electrode film of the upper electrode, and a second sputtering step of forming a surface-side electrode film of the upper electrode after the first sputtering step. In any of the above manufacturing methods, the sputtering power in the first sputtering step may be greater than the sputtering power in the second sputtering step.

[0014] In any of the above manufacturing methods, the substrate-side electrode film may have a thickness greater than that of the surface-side electrode film.

[0015] In any of the above manufacturing methods, the upper electrode formed in the electrode forming step may have an average grain size of 30 μm or more, and a (111) orientation ratio of the crystal structure may be 98% or more.

[0016] The above summary of the invention does not list all of the features of the present invention, and subcombinations of these features may also be inventions.

[0017] 1 is a diagram showing an example of a flowchart of a manufacturing method of a semiconductor device 100. FIG. 2 is a cross-sectional view of the semiconductor device 100 in the manufacturing method of FIG. 1. FIG. 3 is a diagram explaining an electrode formation step S104. FIG. 4 is a diagram showing an average grain size of the upper surface electrode 52 for each heating temperature T1. FIG. 5 is a diagram showing the orientation ratio of the upper surface electrode 52 for each heating temperature T1. FIG. 6 is a schematic SEM image of the upper surface electrode 52 when the heating temperature T1 is 470° C. FIG. 7 is a schematic SEM image of the upper surface electrode 52 when the heating temperature T1 is 450° C. FIG. 8 is a schematic SEM image of the upper surface electrode 52 when the heating temperature T1 is 430° C. FIG. 9 is a schematic SEM image of the upper surface electrode 52 when the heating temperature T1 is 490° C. FIG. 10 is a diagram showing observation results of grain size at each heating temperature. FIG. 11 is a diagram explaining an example of a semiconductor device 100 in an example. FIG. 12 is a diagram explaining an example of a semiconductor device 100 in a comparative example. FIG. 13 is a diagram explaining another example of a semiconductor device 100 in a comparative example. FIG. 14 is a diagram explaining another example of a flowchart of a manufacturing method of the semiconductor device 100. 10A and 10B are diagrams illustrating an example of a first sputtering step S205 and a second sputtering step S206.

[0018] The present invention will be described below through embodiments of the invention, but the following embodiments do not limit the scope of the invention. Furthermore, not all of the combinations of features described in the embodiments are necessarily essential to the solution of the invention. In this specification and drawings, elements having substantially the same function and configuration are designated by the same reference numerals to avoid redundant description, and elements not directly related to the present invention are not shown. Furthermore, in one drawing, elements having the same function and configuration may be designated by the same reference numeral, and the reference numerals may be omitted for other elements.

[0019] In this specification, one side in a direction parallel to the depth direction of a semiconductor substrate is referred to as "upper" and the other side as "lower." Of the two main surfaces of a substrate, layer, or other member, one surface is referred to as the upper surface and the other surface is referred to as the lower surface. The directions of "upper" and "lower" are not limited to the direction of gravity or the directions when the semiconductor module is mounted.

[0020] In this specification, technical matters may be described using orthogonal coordinate axes, i.e., the X-axis, Y-axis, and Z-axis. The orthogonal coordinate axes merely identify the relative positions of components and do not limit a specific direction. For example, the Z-axis does not limit the height direction relative to the ground. Note that the +Z-axis direction and the −Z-axis direction are opposite directions. When the Z-axis direction is referred to without specifying positive or negative, it means a direction parallel to the +Z-axis and −Z-axis. In this specification, the orthogonal axes parallel to the top and bottom surfaces of the semiconductor substrate are referred to as the X-axis and Y-axis. Furthermore, the axis perpendicular to the top and bottom surfaces of the semiconductor substrate is referred to as the Z-axis. In this specification, the direction of the Z-axis may be referred to as the depth direction. In this specification, the direction parallel to the top and bottom surfaces of the semiconductor substrate, including the X-axis and Y-axis, may be referred to as the horizontal direction.

[0021] In this specification, when we say "same" or "equal," it may also include cases where there is an error due to manufacturing variations, etc. The error is, for example, within 10%.

[0022] 1 is a diagram showing an example of a flowchart of a method for manufacturing a semiconductor device 100 (see FIG. 2). The method for manufacturing the semiconductor device 100 includes a preparation step S101, an interlayer insulating film formation step S102, a contact hole formation step S103, and an electrode formation step S104. The flowchart shown in FIG. 1 shows a part of the manufacturing process of the semiconductor device 100.

[0023] 2 is a cross-sectional view of the semiconductor device 100 during the manufacturing method of FIG. 1. The semiconductor device 100 functions as a power conversion device such as an inverter, for example. The semiconductor device 100 may include an insulated gate bipolar transistor (IGBT), a diode such as an FWD (Free Wheel Diode), a combination of these, such as an RC (Reverse Conducting)-IGBT, or a MOS transistor. The semiconductor device 100 is not limited to these examples.

[0024] First, in a preparation step S101, a semiconductor substrate 10 is prepared. The semiconductor substrate 10 may be a wafer including a plurality of semiconductor devices 100, or may be a substrate cut from the wafer. The material of the semiconductor substrate 10 may be silicon (Si) or silicon carbide (SiC). A plurality of semiconductor devices 100 may be manufactured by dicing the wafer-shaped semiconductor substrate 10. The semiconductor substrate 10 has an upper surface 21 and a lower surface. However, in FIG. 2 , the lower surface side of the semiconductor substrate 10 is not shown, and the vicinity of the upper surface 21 is shown enlarged.

[0025] The upper surface 21 of the semiconductor substrate 10 may be a surface on which a gate structure of an IGBT, a MOS transistor, or the like is formed. The gate structure is a structure including at least one of a gate electrode, a gate insulating film, a source region, an emitter region, and a channel region, for example. The upper surface 21 of the semiconductor substrate 10 may be a so-called device surface or a front surface.

[0026] Before the preparatory step S101, a predetermined pattern may be formed on the upper surface 21 of the semiconductor substrate 10. Before the preparatory step S101, a gate structure may be formed on the upper surface 21 of the semiconductor substrate 10. Before the preparatory step S101, a step of implanting impurities into a predetermined region of the semiconductor substrate 10 and a step of annealing the semiconductor substrate 10 may be performed. Note that in FIG. 2 , configurations such as the gate structure provided on the upper surface 21 of the semiconductor substrate 10 are omitted.

[0027] Next, in interlayer insulating film forming step S102, the interlayer insulating film 38 is formed. In interlayer insulating film forming step S102, the interlayer insulating film 38 is formed on the upper surface 21 of the semiconductor substrate 10. In interlayer insulating film forming step S102, the interlayer insulating film 38 may be formed over the entire upper surface 21 of the semiconductor substrate 10.

[0028] The interlayer insulating film 38 is a film including at least one layer of an insulating film such as silicate glass doped with impurities such as boron or phosphorus, a thermal oxide film, and other insulating films. The interlayer insulating film 38 is, for example, a boron phospho silicate glass (BPSG) film. The interlayer insulating film 38 is formed, for example, by atmospheric pressure chemical vapor deposition (CVD). The interlayer insulating film 38 may also be formed by other known methods.

[0029] Next, in contact hole formation step S103, contact holes 54 are formed in the interlayer insulating film 38. In this example, the contact holes 54 expose a portion of the upper surface 21 of the semiconductor substrate 10. The contact holes 54 do not need to expose the entire upper surface 21 of the semiconductor substrate 10. By forming the contact holes 54, the interlayer insulating film 38 is provided on a portion of the upper surface 21 of the semiconductor substrate 10. As an example, the interlayer insulating film 38 is provided so as to cover the upper part of the gate electrode.

[0030] The contact holes 54 may be formed by etching. The etching may be dry etching, wet etching, or the like. The etching may be performed by a known method. In the contact hole forming step S103, the etching may be performed with a resist pattern provided. In the contact hole forming step S103, a reflow process may be performed on the interlayer insulating film 38 after the etching process. As an example, the reflow process on the interlayer insulating film 38 is performed in a nitrogen atmosphere at a temperature of about 1000° C. for about 25 minutes.

[0031] After the contact hole forming step S103 and before the electrode forming step S104, a barrier metal may be formed above the interlayer insulating film 38. The barrier metal is omitted in FIG. 2 . The barrier metal may include Ti. The barrier metal may include TiN. The barrier metal may be a laminate of Ti and TiN. When the barrier metal is a laminate of Ti and TiN, the thickness of Ti may be about 50 nm, and the thickness of TiN may be about 110 nm. In this specification, thickness refers to the difference in height between the upper and lower surfaces of the film in the Z-axis direction. The barrier metal may be formed using a DC magnetron sputtering device.

[0032] Subsequently, in electrode formation step S104, an upper surface electrode 52 is formed. The upper surface electrode 52 may be a so-called main electrode of the semiconductor device 100. The main electrode may be the electrode that has the largest area in a top view among the electrodes arranged above the upper surface 21 of the semiconductor substrate 10. The main electrode may be electrically connected to the emitter region or source region of the transistor section, or may be electrically connected to the anode region of the diode section.

[0033] The top electrode 52 is provided above the top surface 21 of the semiconductor substrate 10. The top electrode 52 may also be provided above the interlayer insulating film 38. In this example, the top electrode 52 is provided so as to cover the interlayer insulating film 38. The top electrode 52 may also be provided in a contact hole 54. In this example, the contact hole 54 is filled with the top electrode 52.

[0034] 3 is a diagram illustrating the electrode formation step S104. The electrode formation step S104 is performed by an apparatus 200. FIG. 3 schematically illustrates the apparatus 200. The apparatus 200 may be a sputtering apparatus. In this example, the apparatus 200 is a DC sputtering apparatus such as a DC magnetron sputtering apparatus. In the electrode formation step S104, the upper electrode 52 is formed by sputtering.

[0035] The apparatus 200 includes a chamber 20 and a power supply 50. The chamber 20 houses a semiconductor substrate 10, a hot plate 30, and a target 40. Furthermore, since the apparatus 200 is a DC magnetron sputtering apparatus, it may include a magnet (not shown) that generates a magnetic force.

[0036] The hot plate 30 is a support table that holds the semiconductor substrate 10. The semiconductor substrate 10 is placed on the top surface of the hot plate 30 in contact with the top surface.

[0037] The target 40 is the material of the upper electrode 52. In this example, the target 40 contains aluminum elements. That is, the upper electrode 52 contains aluminum. The target 40 may be Al or AlSi. The ratio of aluminum elements in the target 40 may be 90 wt % or more.

[0038] The power supply 50 applies a voltage to the target 40 in the chamber 20. In this example, the anode is connected to ground and the cathode is connected to the target 40 to apply the voltage. The hot plate 30 may be at a floating potential. The power supplied by the power supply 50 is referred to as a sputtering power W1.

[0039] In the electrode formation step S104, when forming the upper electrode 52, the chamber 20 is first evacuated using a vacuum pump or the like. The minimum pressure reached at this time is called the ultimate vacuum. The ultimate vacuum of the chamber 20 is 1×10 －４ The pressure may be smaller than 0.2 Pa. The smaller the ultimate vacuum, the smaller the amount of impurities, making it easier to promote grain growth, which will be described later. After the chamber 20 is evacuated, a small amount of inert gas is introduced into the chamber 20. In this example, the inert gas is argon gas. The pressure in the chamber after the inert gas has been introduced is referred to as the gas pressure. The gas pressure is the pressure when the amount of inert gas introduced and the amount of exhaust from the vacuum pump are balanced. The gas pressure in the chamber 20 is, for example, 0.3 Pa.

[0040] When a voltage is applied from the power supply 50 at an appropriate gas pressure, argon elements are ionized into positive ions (argon ions 60), generating plasma. The argon ions 60 are then attracted to the target 40, which serves as the cathode, and collide with the target 40 at high speed. This causes AlSi molecules (molecules 70) to be emitted from the target 40. The emitted molecules 70 adhere to the upper surface 21 of the opposing semiconductor substrate 10, thereby forming an upper electrode 52 on the semiconductor substrate 10.

[0041] In this example, the hot plate 30 heats the semiconductor substrate 10 in the electrode formation step S104. The temperature of the semiconductor substrate 10 at this time is set to a heating temperature T1. That is, the upper electrode 52 is formed while the temperature of the semiconductor substrate 10 is at the heating temperature T1. The hot plate 30 heats the semiconductor substrate 10 so that the temperature of the semiconductor substrate 10 reaches the heating temperature T1.

[0042] In this example, the heating temperature T1 is set to 440° C. or higher and 480° C. or lower. As will be described in detail later, by setting the heating temperature T1 to 440° C. or higher and 480° C. or lower, grain growth during film formation is promoted, improving embeddability. Furthermore, the orientation ratio of the upper electrode 52 increases, improving surface flatness. Furthermore, reflow is promoted, improving surface flatness.

[0043] In at least a part of the process of forming the upper electrode 52 in the electrode formation step S104, the heating temperature T1 may be equal to or higher than 440° C. and equal to or lower than 480° C. In this example, in all the processes of forming the upper electrode 52 in the electrode formation step S104, the heating temperature T1 is equal to or higher than 440° C. and equal to or lower than 480° C.

[0044] The sputtering power W1 is, for example, 0.5 kW or more and 15 kW or less. The thickness of the upper electrode 52 to be formed is, for example, 5 μm. In sputtering, the film formation rate varies depending on the sputtering power W1 and the gas pressure in the chamber 20, so the film formation time may be adjusted to achieve the above thickness.

[0045] FIG. 4 is a diagram showing the average grain size of the top electrode 52 at each heating temperature T1. In FIG. 4, the average grain size was determined from SEM images of the top electrode 52 formed using the above-described manufacturing method at heating temperatures T1 of 430°C, 450°C, 470°C, and 490°C. FIG. 4 shows the average grain size of the top electrode 52 at each heating temperature T1 when viewed from above. The grain size refers to the size of the crystal grains in the top electrode 52. For example, the crystal grains are individual single crystal portions contained in the polycrystalline top electrode 52. If the crystal grains are spherical, the diameter of the crystal grain may be used as the grain size. If the crystal grains are not spherical, the longest length of a line connecting two points on the grain boundary may be used as the grain size. For example, if the crystal grains are ellipsoidal, the major axis may be used as the grain size. The average grain size of the crystal grains on the surface or cross section of the top electrode 52 parallel to the XY plane may be used as the average grain size of the top electrode 52. If the crystal grains on that plane are circular, the diameter of the crystal grain may be used as the grain size. If the crystal grains are not circular, the longest length of a line connecting two points on the crystal grain boundary may be used as the grain size. For example, if the crystal grains are elliptical, the major axis may be used as the grain size. The average grain size of the crystal grains may be measured on the top surface of the top electrode 52, or on an XY cross section at the center of the depth direction of the top electrode 52, or on an XY cross section at another position. In the example of FIG. 4 , the average grain size of the crystal grains is measured on the top surface of the top electrode 52. Note that the grain size shown in FIG. 4 is the result of forming an AlSi film on a Si wafer with a thermal oxide film, with the grain size being analyzed.

[0046] The average particle size was 13 μm when the heating temperature T1 was 430° C. The average particle size was 35 μm when the heating temperature T1 was 450° C. The average particle size was 43 μm when the heating temperature T1 was 470° C. The average particle size was 31 μm when the heating temperature T1 was 490° C. The average particle size values ​​for each heating temperature T1 are shown in the figure.

[0047] The average grain size of the top electrode 52 may be 30 μm or more. A large average grain size means that grain growth is promoted and the crystal grains are larger. Promotion of grain growth reduces voids between crystal grains. This improves the embeddability of the top electrode 52 when it fills a contact hole. The average grain size of the top electrode 52 may be 35 μm or more, or may be 40 μm or more. The average grain size of the top electrode 52 may be 100 μm or less.

[0048] In Fig. 4, the average grain size increases when the heating temperature T1 is in the range of 440°C or higher and 480°C or lower. The heating temperature T1 may be 450°C or higher and 470°C or lower, or 460°C or higher and 480°C or lower.

[0049] FIG. 5 shows the orientation ratio of the top electrode 52 for each heating temperature T1. The heating temperature T1 in this example is the same as in FIG. 4 . The orientation ratio is expressed as the deviation of the orientation from the (111) direction of the crystal structure of the top electrode 52. The orientation ratio may be measured on a surface or cross section parallel to the XY plane of the top electrode 52. As an example, the top electrode 52 is analyzed using XRD (X-ray diffraction) or EBSD (electron backscatter diffraction) to obtain a diffraction pattern. The position (angle) of the peak corresponding to the (111) of aluminum in the obtained diffraction pattern is used as the reference. Peaks located within 15° of the reference peak position (including the (111) peak) are classified as 0-15°. Peaks located between 15° and 30° from the reference peak position are classified as 15-30°. The same applies to 30-45° and 45-60°. In other words, a high ratio of 0-15° indicates a high (111) orientation ratio. The ratio may be the intensity ratio of peaks belonging to each angle range. In this specification, the ratio of 0-15° may be referred to as the (111) orientation ratio.

[0050] The (111) orientation ratio was 99% when the heating temperature T1 was 430°C. The (111) orientation ratio was 100% when the heating temperature T1 was 450°C. The (111) orientation ratio was 100% when the heating temperature T1 was 470°C. The (111) orientation ratio was 57% when the heating temperature T1 was 490°C. A (111) orientation ratio of 100% may mean that no peaks other than (111) were observed.

[0051] The (111) orientation ratio of the upper electrode 52 may be 98% or more. A high (111) orientation ratio means that crystals of other modes are not formed. This improves the surface flatness of the upper electrode 52. The (111) orientation ratio of the upper electrode 52 may be 99% or more, or even 100%.

[0052] The upper electrode 52 formed in the electrode formation step S104 may have an average grain size of 30 μm or more and a (111) orientation ratio of 98% or more in the crystal structure. That is, by setting the heating temperature T1 between 440°C and 480°C, the average grain size and orientation ratio of the upper electrode 52 fall within the above-mentioned ranges. This improves contact hole filling and surface flatness. However, even at temperatures below 430°C, the (111) orientation ratio is unlikely to decrease significantly, and therefore the decrease in surface flatness due to the crystal structure is unlikely to be significant. However, if the film formation temperature is low, reflow becomes less likely to occur, resulting in a decrease in surface flatness. On the other hand, if the temperature is increased to improve reflowability, the (111) orientation ratio decreases at temperatures above 490°C, and the surface flatness due to the crystal structure decreases. Therefore, it is preferable to set the heating temperature T1 between 440°C and 480°C.

[0053] 6 is a schematic diagram of an SEM image of the top electrode 52 when the heating temperature T1 is 470° C. The curves in the figure represent crystal grain boundaries. In the top electrode 52 of this example, relatively large crystal grain sizes were observed. Furthermore, only a single crystal pattern was observed, and the surface flatness was good.

[0054] 7 is a schematic diagram of an SEM image of the top electrode 52 when the heating temperature T1 is 450° C. The curves in the figure represent crystal grain boundaries. Relatively large crystal grain sizes were observed in the top electrode 52 of this example. Furthermore, only a single crystal pattern was observed, and the surface flatness was good.

[0055] 8 is a schematic diagram of an SEM image of the top electrode 52 when the heating temperature T1 is 430°C. The curves in the figure represent crystal grain boundaries. In the top electrode 52 of this example, the grain size of the crystal grains was smaller than when the heating temperature T1 was 450°C or 470°C. However, with regard to the crystal structure, only a single crystal pattern was observed, and the surface flatness was good.

[0056] FIG. 9 is a schematic diagram of an SEM image of the top electrode 52 when the heating temperature T1 is 490° C. The curves in the figure represent crystal grain boundaries. In the top electrode 52 of this example, scaly convex structures (hillocks) 58 were observed along with the crystal grains shown in FIGS. 6 to 8 . Therefore, the surface flatness is reduced compared to the cases of FIGS. 6 to 8 . Note that FIGS. 6 to 9 are all SEM images at the same magnification.

[0057] Fig. 10 is a diagram showing the results of observing the grain size at each heating temperature. In Fig. 10, the grain size of the upper electrode 52 was also examined when the heating temperature T1 was 430°C, 450°C, 470°C, and 490°C. In Fig. 10, the results of determining the average grain size, as well as the maximum, minimum, deviation, and number of grains, are shown. The average grain size is the same as in Fig. 4.

[0058] The minimum grain size of the upper electrode 52 may be 5 μm or more. A large minimum grain size means that the crystal grains are growing, which reduces voids between the crystal grains. In other words, the filling of the contact hole 54 is improved. The minimum grain size of the upper electrode 52 may be 10 μm or more, or may be 20 μm or more.

[0059] The maximum grain size of the upper electrode 52 may be 140 μm or more and 200 μm or less. A large maximum grain size means that the crystal grains are growing, which reduces voids between the crystal grains. In other words, the filling of the contact hole 54 is improved. The maximum grain size of the upper electrode 52 may be 150 μm or more, or may be 160 μm or more. The maximum grain size of the upper electrode 52 may be 190 μm or less, or may be 180 μm or less.

[0060] 11 is a diagram illustrating an example of a semiconductor device 100 according to an embodiment. This diagram illustrates the semiconductor device 100 after the electrode formation step S104 in the above-described manufacturing method. In the semiconductor device 100 of this embodiment, the upper electrode 52 is formed at a heating temperature T1 in the electrode formation step S104 of 440° C. or higher and 480° C. or lower.

[0061] The semiconductor device 100 includes a semiconductor substrate 10, an interlayer insulating film 38, and an upper electrode 52. The semiconductor substrate 10 has an upper surface 21 and a lower surface 23. The internal structure of the semiconductor substrate 10 is omitted in FIG. 11 . The interlayer insulating film 38 is provided above the upper surface 21 of the semiconductor substrate 10. A contact hole 54 is formed in the interlayer insulating film 38. The contact hole 54 connects the semiconductor substrate 10 and the upper electrode 52.

[0062] The top electrode 52 is provided above the top surface 21 of the semiconductor substrate 10. The above-mentioned barrier metal may be provided between the top electrode 52 and the semiconductor substrate 10 and between the top electrode 52 and the interlayer insulating film 38. The top electrode 52 may be made of aluminum or an aluminum alloy such as an aluminum-silicon alloy. A collector electrode in an IGBT or a drain electrode in a MOSFET may be provided on the bottom surface 23, or a cathode electrode in a diode may be provided on the bottom surface 23.

[0063] The thickness H1 of the upper electrode 52 may be 3.0 μm or more. The thickness H1 of the upper electrode 52 may be the average thickness between the upper surface 21 and the upper surface 53 of the upper electrode 52 (shown by the dashed dotted line). The thickness H1 of the upper electrode 52 may also be the thickness at the position where the contact hole 54 is provided. A large thickness H1 of the upper electrode 52 facilitates the growth of crystal grains, reducing voids between the crystal grains. The thickness H1 of the upper electrode 52 may be 5.0 μm or more, or may be 10 μm or more. The thickness H1 of the upper electrode 52 may be 20 μm or less.

[0064] The opening width D1 of the contact hole 54 may be 1.5 μm or less. The average grain size of the upper electrode 52 may be 20 times or more the width D1. By having the average grain size sufficiently larger than the width D1, it is possible to prevent voids from forming inside the contact hole 54. This allows the contact hole 54 to be filled even if the width D1 becomes narrower due to advances in miniaturization. The opening width D1 may be 1.0 μm or less. The average grain size of the upper electrode 52 may be 30 times or more the width D1. Furthermore, the center-to-center distance D2 (cell pitch) of adjacent interlayer insulating films 38 may be 3.5 μm or less. The average grain size of the upper electrode 52 may be 8 times or more the width D2.

[0065] The top electrode 52 may have a single crystal grain extending from the top surface 53 to the bottom surface in the depth direction. Here, the bottom surface of the top electrode 52 may be the top surface of the interlayer insulating film 38 or the top surface 21 of the semiconductor substrate 10. In other words, having a single crystal grain means that crystal grains with a (111) orientation have grown sufficiently. In this case, other crystal patterns (such as the above-mentioned convex structure 58) are not formed, improving surface flatness. The single crystal grain may be formed in at least a portion of a plane parallel to the top surface 53. Furthermore, the thickness H1 of the top electrode 52 may be smaller than the average grain size, and may be equal to or less than half or equal to or less than one-fifth of the average grain size.

[0066] The unevenness H2 of the upper surface 53 of the upper electrode 52 may be equal to or less than half the thickness H3 of the interlayer insulating film 38. The unevenness H2 of the upper surface 53 of the upper electrode 52 may be the difference in height between the portion of the upper surface 53 of the upper electrode 52 having the maximum height and the portion of the upper surface 53 of the upper electrode 52 having the minimum height. The thickness H3 of the interlayer insulating film 38 may be the difference in height between the portion of the upper surface of the interlayer insulating film 38 having the maximum height and the portion of the lower surface of the interlayer insulating film 38 having the minimum height. In this embodiment, the surface flatness can be improved by increasing the (111) orientation ratio. In addition, the surface flatness can also be improved by reflowing through heating.

[0067] The unevenness H2 of the upper surface 53 of the upper electrode 52 may be 0.5 μm or less. The unevenness H2 of the upper surface 53 of the upper electrode 52 may be 0.25 μm or less. The thickness H2 of the interlayer insulating film 38 may be 0.5 μm or more, or may be 1.0 μm or more. The thickness H2 of the interlayer insulating film 38 may be 2.0 μm or less.

[0068] Fig. 12 is a diagram illustrating an example of a semiconductor device 300 in a comparative example. Fig. 12 shows the semiconductor device 300 after the electrode formation step S104, similar to Fig. 11. However, the semiconductor device 300 in Fig. 12 is manufactured under low-temperature conditions with a heating temperature T1 of 430°C or less. Other conditions in Fig. 12 may be the same as those in Fig. 4.

[0069] In FIG. 12, because the heating temperature T1 is low, the crystal grains do not grow sufficiently, resulting in the formation of voids 80 within the upper electrode 52. In other words, the embedding property is poor. Furthermore, due to insufficient reflow caused by the low heating temperature T1, the shape of the interlayer insulating film 38 appears on the upper surface 53, and the unevenness H2 on the upper surface 53 is larger than in the example. In other words, the surface flatness is poor. However, in the cross section of FIG. 12, a single crystal grain is formed from the upper surface 53 to the lower surface of the upper electrode 52. This is due to the relatively high (111) orientation ratio shown in FIG. 5.

[0070] Fig. 13 is a diagram illustrating another example of a semiconductor device 300 according to a comparative example. Fig. 13 shows the semiconductor device 300 after the electrode formation step S104, similar to Fig. 11. However, the semiconductor device 300 in Fig. 13 is manufactured under high-temperature conditions with a heating temperature T1 of 490°C or higher. Other conditions in Fig. 13 may be the same as those in Fig. 4.

[0071] In the upper electrode 52 shown in Fig. 13, a convex structure 58 is formed due to a change in the crystal structure caused by high temperature conditions. In Fig. 13, the (111) oriented crystalline portion of the upper electrode 52 is indicated by reference numeral 52-1. The formation of the convex structure 58 significantly deteriorates the surface flatness.

[0072] 14 is a diagram illustrating another example of a flowchart of a method for manufacturing the semiconductor device 100. The method for manufacturing the semiconductor device 100 includes a preparation step S201, an interlayer insulating film forming step S202, a contact hole forming step S203, and an electrode forming step S204. The preparation step S201, the interlayer insulating film forming step S202, and the contact hole forming step S203 of FIG. 14 may be the same as the preparation step S101, the interlayer insulating film forming step S102, and the contact hole forming step S103 of FIG. 1.

[0073] In this example, the electrode formation step S204 includes a first sputtering step S205 and a second sputtering step S206. That is, in the electrode formation step S204, the upper electrode 52 is formed in two steps under different conditions. Specifically, the sputtering power is changed in the first sputtering step S205 and the second sputtering step S206. The sputtering power in the first sputtering step S205 may be higher than the sputtering power in the second sputtering step S206. The second sputtering step S206 is performed after the first sputtering step S205.

[0074] 15 is a diagram illustrating an example of the first sputtering step S205 and the second sputtering step S206. In the first sputtering step S205, a substrate-side electrode film 61 of the upper electrode 52 is formed. In the second sputtering step S206, a surface-side electrode film 62 of the upper electrode 52 is formed. The substrate-side electrode film 61 is located closer to the upper surface 21 of the semiconductor substrate 10 than the surface-side electrode film 62. In this example, the substrate-side electrode film 61 is in contact with the upper surface 21 of the semiconductor substrate 10, and the surface-side electrode film 62 is exposed on the upper surface 53 of the upper electrode 52. In this example, the upper electrode 52 is formed by stacking the substrate-side electrode film 61 and the surface-side electrode film 62.

[0075] Increasing the sputtering power in the first sputtering step S205 increases the film formation rate, thereby improving throughput. In this case, the unevenness of the upper surface 63 of the substrate-side electrode film 61 becomes greater than the unevenness of the upper surface 64 of the front-side electrode film 62. On the other hand, decreasing the sputtering power in the second sputtering step S206 reduces the film formation rate and lengthens the heating time, thereby promoting reflow. As a result, the unevenness of the upper surface 64 of the front-side electrode film 62 becomes smaller, and the flatness of the upper surface 53 of the upper electrode 52 becomes better.

[0076] The thickness H4 of the substrate-side electrode film 61 may be greater than the thickness H5 of the surface-side electrode film 62. As an example, the thickness H4 of the substrate-side electrode film 61 is 3 μm, and the thickness H5 of the surface-side electrode film 62 is 2 μm. This can further improve throughput. The thickness H4 may be at least twice, or even five times, the thickness H5. Note that the thicknesses H4 and H5 may be average thicknesses. The thicknesses H4 and H5 may be thicknesses at locations where the contact holes 54 are provided in the Z-axis direction. The thickness H4 may be greater than the thickness H3 of the interlayer insulating film 38. The thickness H4 may be at least twice, or even five times, the thickness H3.

[0077] In both the first sputtering step S205 and the second sputtering step S206, the heating temperature may be 440° C. or more and 480° C. or less. The heating temperatures in the first sputtering step S205 and the second sputtering step S206 may be the same. The upper electrode 52 formed in the electrode formation step S204 may have an average grain size of 30 μm or more and a (111) orientation ratio of the crystal structure of 98% or more.

[0078] Although the present invention has been described above using embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications and improvements can be made to the above embodiments. It is clear from the claims that such modifications and improvements can also be included within the technical scope of the present invention.

[0079] 10. Semiconductor substrate, 20. Chamber, 21. Upper surface, 23. Lower surface, 30. Hot plate, 38. Interlayer insulating film, 40. Target, 50. Power source, 52. Upper electrode, 53. Upper surface, 54. Contact hole, 58. Convex structure, 60. Argon ions, 61. Substrate-side electrode film, 62. Surface-side electrode film, 63. Upper surface, 64. Upper surface, 70. Molecules, 80. Voids, 100. Semiconductor device, 200. Device, 300. Semiconductor device

Claims

1. A semiconductor device comprising: a semiconductor substrate having an upper surface and a lower surface; and an upper surface electrode containing aluminum provided above the upper surface of the semiconductor substrate, wherein the average grain size of the upper surface electrode is 30 μm or more and the (111) orientation ratio of the crystal structure is 98% or more.

2. The semiconductor device according to claim 1, wherein the minimum grain size of said upper electrode is 5 μm or more.

3. The semiconductor device according to claim 2, wherein the maximum grain size of said upper electrode is 140 μm or more and 200 μm or less.

4. The semiconductor device according to claim 1, wherein the thickness of said upper electrode is 3 μm or more.

5. The semiconductor device according to claim 1, wherein the upper electrode has a single crystal grain formed from the upper surface to the lower surface in the depth direction.

6. The semiconductor device according to claim 1, wherein the upper electrode is an aluminum-silicon alloy.

7. The semiconductor device according to any one of claims 1 to 6, further comprising an interlayer insulating film provided on the upper surface of the semiconductor substrate, wherein contact holes are formed in the interlayer insulating film, and the average grain size is 20 times or more the width of the contact holes.

8. A method for manufacturing a semiconductor device comprising: a semiconductor substrate having an upper surface and a lower surface; and an upper surface electrode containing aluminum provided above the upper surface of the semiconductor substrate, wherein the temperature of the semiconductor substrate during the electrode formation step of forming the upper surface electrode is 440°C or higher and 480°C or lower.

9. In the electrode forming step, the upper electrode is formed by sputtering, and during the sputtering, the ultimate vacuum of a chamber containing the semiconductor substrate is 1×10 －4 The method according to claim 8, wherein the ρ is less than 1 Pa.

10. A manufacturing method as described in claim 8, wherein the electrode formation step includes a first sputtering step of forming a substrate-side electrode film of the upper surface electrode, and a second sputtering step of forming a surface-side electrode film of the upper surface electrode after the first sputtering step, and the sputtering power in the first sputtering step is greater than the sputtering power in the second sputtering step.

11. The manufacturing method according to claim 10, wherein the thickness of the substrate-side electrode film is greater than the thickness of the surface-side electrode film.

12. The manufacturing method according to any one of claims 8 to 11, wherein the upper electrode formed in the electrode formation step has an average grain size of 30 μm or more and a (111) orientation ratio of the crystal structure of 98% or more.

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