Solid-state imaging device and converter

Abstract

[Problem] To realize low power consumption and noise reduction. [Solution] This solid-state imaging device is provided with a pixel circuit, a first amplification circuit, an integration circuit, and a second amplification circuit. The pixel circuit performs photoelectric conversion on incident light and outputs a first voltage signal corresponding to an intensity. The first amplification circuit receives an input of the first voltage signal and a feedback signal, and outputs a current signal based on the magnitude of the first voltage signal. The integration circuit integrates the current signal and outputs a second voltage signal. The second amplification circuit amplifies and outputs the difference between the second voltage signal and a reference voltage signal.

Description

Solid-state imaging device and converter

[0001] The present disclosure relates to a solid-state imaging device and a converter.

[0002] To achieve low-noise circuits in image sensors, one method for efficiently reducing the noise bandwidth is to change the transistor connections in the comparator, which compares the ramp signal with the output signal from the pixel, and the amplifier, which amplifies the output of the comparator, by adjusting the timing. This method reduces the gain of the comparator to lower the input-equivalent noise floor, and increases the gate-source voltage of the amplifier input to raise the logic threshold, thereby reducing the noise bandwidth. While this implementation is useful in reducing the noise bandwidth, it also has the drawback of requiring time for counting the output signal from the photoelectrically converted pixel and for noise integration.

[0003] International Publication No. 2024 / 070740

[0004] Therefore, one of the non-limiting problems that the embodiments of the present disclosure aim to solve is to achieve low power consumption and low noise. The problem that the embodiments of the present disclosure aim to solve can also be, as some further non-limiting examples, a problem corresponding to the effects described in the embodiments. In other words, a problem that corresponds to at least one of the effects described in the description of the embodiments of the present disclosure can be the problem that the present disclosure aims to solve.

[0005] According to one embodiment, a solid-state imaging device includes a pixel circuit, a first amplifier circuit, an integration circuit, and a second amplifier circuit. The pixel circuit photoelectrically converts incident light and outputs a first voltage signal corresponding to the intensity. The first amplifier circuit receives the first voltage signal and a feedback signal and outputs a current signal based on the magnitude of the first voltage signal. The integration circuit integrates the current signal and outputs a second voltage signal. The second amplifier circuit amplifies the difference between the second voltage signal and a reference voltage signal and outputs the result.

[0006] The pixel circuits may be arranged in a two-dimensional array in a pixel array, and the pixel circuits belonging to the same column may share the first amplifier circuit, the integration circuit, and the second amplifier circuit.

[0007] The first amplifier circuit may include a first transistor having a first terminal to which the first voltage signal is applied and a second terminal to which the current signal is output, and a first capacitor having a first terminal connected to the integrating circuit, a first terminal to which the current output from the integrating circuit is input, and a second terminal connected to the gate of the first transistor.

[0008] The integrating circuit may include: a second capacitor having a first terminal connected to the second terminal of the first transistor; a second transistor having a first terminal connected to a positive power supply voltage line via a current source, a second terminal connected to the first terminal of the first capacitor, and a gate connected to the second terminal of the second capacitor; a resistor having a first terminal connected to the second terminal of the second transistor and a second terminal connected to a negative power supply voltage line; a third transistor having a first terminal connected to the positive power supply voltage line via a current source, outputting the second voltage signal from a second terminal, and a gate connected to the positive power supply voltage line via the second capacitor; a switch connected between the first terminal of the second transistor and the first terminal of the third transistor; and a fourth capacitor having a first terminal connected to the second terminal of the third transistor and a second terminal connected to a negative power supply voltage line.

[0009] The second amplifier circuit may have a non-inverting input terminal connected to the second terminal of the third transistor and the first terminal of the fourth capacitor, and an inverting input terminal to which the reference voltage signal is applied.

[0010] An initialization switch may be provided between the second terminal and the gate of the first transistor and between the first terminal and the gate of the second transistor.

[0011] An integral capacitance initialization switch may be provided between the first terminal and the second terminal of the fourth capacitor.

[0012] The resistor may be a variable resistor.

[0013] According to one embodiment, the converter includes a pixel circuit, a first amplifier circuit, an integrating circuit, and a second amplifier circuit. The pixel circuit outputs a first voltage signal corresponding to the intensity of incident light. The first amplifier circuit receives the first voltage signal and a feedback signal and outputs a current signal based on the magnitude of the first voltage signal. The integrating circuit integrates the current signal and outputs a second voltage signal. The second amplifier circuit amplifies the difference between the second voltage signal and a reference voltage signal and outputs the amplified signal.

[0014] 1 is a block diagram schematically showing an example of a solid-state imaging device according to an embodiment. FIG. 2 is a diagram schematically showing a semiconductor substrate on which a solid-state imaging device according to an embodiment is mounted. FIG. 3 is a diagram schematically showing a semiconductor substrate on which a solid-state imaging device according to an embodiment is mounted. FIG. 4 is a block diagram schematically showing an example of an ADC according to an embodiment. FIG. 5 is a circuit diagram schematically showing an example of an ADC according to an embodiment. FIG. 6 is a timing chart showing an example of the operation of an ADC according to an embodiment. FIG. 7 is a diagram showing the granularity of quantization according to an embodiment. FIG. 8 is a circuit diagram schematically showing an example of an ADC according to an embodiment. FIG. 9 is a diagram showing an example of a resistor according to an embodiment. FIG. 10 is a diagram showing an example of a resistor according to an embodiment. FIG. 11 is a circuit diagram schematically showing an example of an ADC according to an embodiment.

[0015] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. The drawings are used for explanation purposes, and the shape, size, and size ratio of each component in an actual device do not necessarily have to be the same as those shown in the drawings. Furthermore, since the drawings are simplified, components necessary for implementation other than those shown in the drawings are also assumed to be appropriately provided.

[0016] 1 is a diagram illustrating a portion of a solid-state imaging device (image sensor) according to one embodiment. The solid-state imaging device 1 includes at least a first driving circuit 10, a second driving circuit 12, a pixel array 14, an analog-to-digital conversion circuit (hereinafter referred to as ADC 16), and a logic circuit 18. The solid-state imaging device 1 may be configured without some of these components, or may include other necessary components as desired. For example, the solid-state imaging device 1 may include an input / output interface for inputting and outputting signals, and a memory circuit for temporarily or non-temporarily storing data.

[0017] The first drive circuit 10 is a circuit that selects which line of pixels 140 in the pixel array 14 should be set to a drivable state. The first drive circuit 10 applies signals that set the pixels 140 in each line to a drivable state via signal lines 100 arranged along the line direction.

[0018] The second drive circuit 12 is a circuit that controls which column of pixels 140 should be output from among the pixels 140 that belong to a line selected by the first drive circuit 10 provided in the pixel array 14. The solid-state imaging device 1 outputs from the pixels 140 that belong to a column specified by the second drive circuit 12 in a line that has been selected and is in a drivable state by the first drive circuit 10. The second drive circuit 12 applies signals that drive the pixels 140 that belong to each column to output pixel signals via signal lines 120 arranged along the column direction.

[0019] The pixel array 14 is an area in which pixels 140 are arranged. The pixels 140 are arranged in a two-dimensional array along the line direction and column direction within the pixel array 14. Each pixel 140 has a light receiving element, performs photoelectric conversion on light incident on the pixel 140, and outputs an analog signal based on the intensity of the incident light. Each pixel 140 has a pixel circuit that outputs a signal photoelectrically converted by the light receiving element.

[0020] The signal output from each pixel 140 is output to the ADC 16 via a signal line 160 arranged for each column or for each pixel, for example. That is, the ADC 16 may be a conversion circuit provided for each column or for each pixel. As another example, the ADC 16 may be a conversion circuit provided for each region other than a column in the pixel array 14.

[0021] The ADC 16 is a circuit that converts the analog signal output from the pixel 140 into a digital signal and outputs the digital signal. The ADC 16 converts the analog signal into a digital signal by, for example, comparing the analog signal output from the pixel 140 with a ramp signal that is a reference signal, and counting the time from when the ramp signal starts to be output to when the signal resulting from the comparison is inverted.

[0022] The digital signal generated by the ADC 16 is output to the logic circuit 18. The logic circuit 18 performs various processes on the digital signal and then outputs image data. The logic circuit 18 can also perform, for example, color adjustment, signal processing, image processing, and optionally machine learning processing to generate image data or perform recognition processing.

[0023] FIG. 2 is a diagram showing an example of the arrangement of a pixel array 14 and an ADC 16 according to an embodiment. The solid-state imaging device 1 may be formed as a semiconductor substrate 2 having a portion stacked thereon. As an example, the solid-state imaging device 1 is mounted on a semiconductor substrate 2 having a first substrate 20 and a second substrate 22 stacked thereon. Note that a stacked structure of three or more layers is not excluded. For example, other layers including a memory circuit or a logic circuit 18 may be stacked thereon. The logic circuit 18 may be arranged on the same layer as the ADC 16.

[0024] These substrates may be stacked by any method, such as chip-on-chip (CoC), chip-on-wafer (CoW), or wafer-on-wafer (WoW). Connection between layers may be made by any method, such as via holes or micro-dumps. The signal lines 160 connecting between layers may be made of, for example and without limitation, metals such as Cu, Ag, Au, and Al, or alloys or compounds of these or other materials.

[0025] The first substrate 20 includes at least a pixel array 14. The pixel array 14 outputs a signal based on the intensity of incident light output from each pixel circuit to a signal line 160 provided for each column, and the analog signal is propagated to the second substrate 22 via the signal line provided for each column.

[0026] The second substrate 22 includes at least the ADC 16. The ADC 16 can include a column ADC 162 for each signal line 160 for each column in the pixel array 14. Note that a configuration in which one column ADC 162 is provided for multiple columns, or a configuration in which multiple column ADCs 162 are provided for one column, may also be used.

[0027] The column ADC 162 converts analog signals output from the pixels 140 belonging to the column into digital signals and outputs them, and image data is formed in the subsequent logic circuit.

[0028] 3 is a diagram showing another example of the arrangement of a pixel array 14 and an ADC 16 according to an embodiment. The solid-state imaging device 1 is formed as a semiconductor substrate 2 in which a first substrate 20 and a second substrate 22 are stacked, as in FIG.

[0029] 3, the ADC 16 is configured to include a pixel ADC 164 provided for each pixel 140. The pixel ADC 164 converts the analog signal output via the signal line 160 for each corresponding pixel 140 into a digital signal and outputs the digital signal.

[0030] Although the above example shows a case where a column ADC and a pixel ADC are provided, the configuration of the solid-state imaging device 1 in the present disclosure is not limited to this. For example, the solid-state imaging device 1 may be configured such that the pixel array 14 is divided into multiple areas and an area ADC is provided for each area, or may be configured such that an ADC processes outputs from any number of pixels 140.

[0031] Next, a comparator that achieves low noise according to the present disclosure will be described with some non-limiting examples.

[0032] (First embodiment)

[0033] 4 is a block diagram illustrating an example of an ADC according to an embodiment. In the following description, for example, the ADC 16 includes a column ADC 162 provided for each column, but the same configuration can also be applied to other types of ADCs (for example, pixel ADCs 164, etc.).

[0034] The column ADC 162 includes, for example, a first amplifier circuit 30, an integration circuit 40, a second amplifier circuit 50, and a counter circuit 60. The signal Vsl is an output voltage signal from the pixel circuit of the pixel 140, and is, for example, a signal propagated from another stacked layer to the layer where the column ADC 162 is provided via the signal line 160. The reference voltage Vref is a voltage signal to be compared with an integration signal obtained from the signal Vsl (first voltage signal), and a digital signal corresponding to the value of the signal Vsl is generated depending on the timing at which the magnitude relationship between the integration signal and this reference voltage Vref changes.

[0035] In the case of an ADC provided for each column, signals from the pixels 140 are input to the column ADC 162 via signal lines 160 arranged for each column in the pixel array 14. In other words, pixel circuits belonging to the same column can share the first amplifier circuit 30, the integration circuit 40, the second amplifier circuit 50, and the counter circuit 60.

[0036] The first amplifier circuit 30 receives the signal Vsl and the feedback signal output from the integrator circuit 40, and outputs a current signal based on the magnitude of the signal Vsl. Specifically, the first amplifier circuit 30 receives the signal Vsl at its non-inverting input terminal and the feedback signal output from the integrator circuit 40 at its inverting input terminal.

[0037] The integrating circuit 40 is a circuit that integrates the current signal output from the first amplifier circuit 30 and outputs an integrated signal (second voltage signal) that is the integration result. The integrating circuit 40 also feeds back a voltage signal based on the current signal output by the first amplifier circuit 30 to the first amplifier circuit 30. This feedback signal is input to the inverting input terminal of the first amplifier circuit 30.

[0038] The integration circuit 40 integrates the current signal output from the first amplifier circuit 30, and outputs an integrated signal having a slope based on the signal Vsl output from the pixel circuit over time, in other words, a signal proportional to time having a coefficient based on the signal Vsl.

[0039] The second amplifier circuit 50 compares the integrated signal output from the integrating circuit 40 with a reference voltage Vref and outputs the result. The second amplifier circuit 50 operates as an amplifier that amplifies and outputs the difference between the integrated signal and the reference voltage Vref. Specifically, the reference voltage Vref is, for example, a predetermined value, and the second amplifier circuit 50 outputs a signal (second voltage signal) whose sign is reversed when the integrated signal becomes larger than the predetermined value.

[0040] The counter circuit 60 monitors the difference voltage (e.g., whether the difference voltage is positive or negative) between the integrated signal output by the second amplifier circuit 50 and the reference voltage Vref, and converts the analog signal output by each pixel 140 into a digital signal and outputs the digital signal. For example, the second amplifier circuit 50 performs correlated double sampling (CDS) using the time it takes for the integrated signal in the reset phase to exceed the reference voltage Vref and the time it takes for the integrated signal in the data readout phase to exceed the reference voltage Vref, thereby outputting a signal obtained by converting the analog signal Vsl into a digital signal.

[0041] The integrator circuit 40 outputs an integrated signal whose proportionality coefficient depends on the signal Vsl. Therefore, the second amplifier circuit 50 outputs a signal whose sign reverses at a timing dependent on the signal Vsl. The counter circuit 60 counts the time from initialization until the sign of the second voltage signal reverses, thereby obtaining a digital signal value based on the magnitude of the signal Vsl.

[0042] As described above, by converting the voltage signal output from the pixel circuit into a current and using a signal integrated based on this current, it is possible to achieve AD conversion after shortening the comparison time in the second amplifier circuit 50 in accordance with the signal Vsl output from the pixel circuit. By shortening the comparison time, it is possible to suppress the effects of noise that may occur during this time.

[0043] (Second embodiment)

[0044] In the following embodiments, several specific circuit examples will be described. Fig. 5 is a circuit diagram schematically showing a non-limiting example of an ADC according to an embodiment. Note that this circuit diagram does not show all the configurations.

[0045] The pixel circuit of pixel 140 is shown as a non-limiting example. Pixel 140 includes, for example, a photodiode as a light-receiving element, a transfer transistor TRG that transfers a signal photoelectrically converted in the photodiode to a floating diffusion region based on a signal applied to signal line 120, a reset transistor RST that initializes the floating diffusion region, an amplifier transistor AMP that amplifies the potential of the floating diffusion region, and a select transistor SEL that propagates the potential output by the amplifier transistor to signal line 160 based on a signal applied to signal line 100. However, the configuration of the pixel circuit is not limited to this and may include other components.

[0046] Although only one pixel circuit is shown in the figure, the pixel circuits are arranged in a two-dimensional array in the pixel array 14 and are each connected to a column ADC 162 via an appropriate signal line 160.

[0047] The pixel circuits are provided, for example, on the first substrate 20 and are electrically connected to a column ADC 162 on the second substrate 22 via appropriate connections, for example, signal lines 160 formed by connecting appropriate metal conductors between layers. Analog signals output from each pixel 140 via the signal lines 160 are output to the column ADC 162 located on the second substrate 22.

[0048] As a non-limiting example, the first amplifier circuit 30 includes a transistor M01, a capacitor C1, a current source I1, and a switch SWaz. The first amplifier circuit 30 converts a voltage signal output from the pixel 140, which is input via a signal line 160, into a current signal and outputs the current signal. In the following description, the semiconductor types of the respective transistors are set as a non-limiting example, but they may be different semiconductor types. In this case, the source and drain can be interpreted as appropriate according to the semiconductor type.

[0049] Voltages for driving the column ADC 162 are applied to the power supply voltage line VDD and the power supply voltage line VSS. For example, a power supply voltage Vdd is applied to the positive power supply voltage line VDD, and a power supply voltage Vss is applied to the negative power supply voltage line VSS. The power supply voltage Vss may typically be the ground potential Vgnd, but is not limited to this.

[0050] The transistor M01 is, for example, a p-type MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor). The transistor M01 has a source (first terminal) connected to the signal line 160, a drain (second terminal) connected to the power supply voltage line VSS via the current source I1, a gate connected to the capacitor C1, and outputs a signal from the drain to the integrating circuit 40. The transistor M01 passes a current corresponding to the magnitude of the voltage signal Vsl output from the pixel 140 and applied to the source of the transistor M01 to the integrating circuit 40 at the timing when the voltage signal Vsl output from the pixel 140 and applied to the source of the transistor M01 becomes larger than the voltage signal applied to the gate by the threshold voltage.

[0051] The capacitor C1 has one end connected to the integrating circuit 40 and the other end connected to the gate of the transistor M01. The capacitor C1 applies a voltage based on the current signal fed back from the integrating circuit 40 to the gate of the transistor M01.

[0052] The gate of transistor M01 and the other end of capacitor C1 are connected to the drain of transistor M01, i.e., the power supply voltage line VSS, via switch SWaz. When switch SWaz is turned on, the potentials of the drain and gate of transistor M01 and capacitor C1 are reset based on the power supply voltage Vss and the current flowing from current source I1. Note that switches SWaz exist in other locations as well, but these switches are turned on and off synchronously.

[0053] The integrating circuit 40 includes, as a non-limiting example, a transistor M02, a transistor M03, a resistor R, a capacitor C2, a capacitor C3, a capacitor C4, a current source I2, and a current source I3. The integrating circuit 40 integrates the current signal output from the first amplifying circuit 30 and outputs the result, and also outputs a feedback current to the first amplifying circuit 30.

[0054] One end of capacitor C2 is connected to the drain of transistor M01, and the other end is connected to the gate of transistor M02. Capacitor C2 sets a voltage based on the magnitude of the current signal output from transistor M01, i.e., the voltage signal Vsl output from pixel 140, and applies this voltage to the gate of transistor M02.

[0055] The transistor M02 is, for example, an n-type MOSFET, and has a drain connected to the power supply voltage line VDD via a current source I2, a source connected to the power supply voltage line VSS via a resistor R, and a gate connected to a capacitor C2. The transistor M02 applies a voltage formed by the current output from its source and the resistor R to one end of the capacitor C1, thereby causing the first amplifier circuit 30 to operate as a current-feedback comparison amplifier.

[0056] A switch SWaz is provided between the drain and gate of the transistor M02, and when the switch SWaz is turned on, the potential of the gate of the transistor M02 is reset.

[0057] The current source I2 is connected between the power supply voltage line VDD and the drain of the transistor M02. The current source I2 supplies a current Isig to the drain of the transistor M02 to read out a signal from the pixel 140, for example.

[0058] Resistor R is connected between the source of transistor M02 and the power supply voltage line VSS.

[0059] The transistor M03 is, for example, a p-type MOSFET, whose source is connected to the power supply voltage line VDD via a current source I3, whose drain is connected to the power supply voltage line VSS via a capacitor C4, and whose gate is connected to the power supply voltage line VDD via a capacitor C3. The gate of the transistor M03 is also connected to a voltage line that applies a reference voltage Viso via a switch SWaz.

[0060] Capacitor C3 controls the voltage applied to the gate of transistor M03 and is connected between the power supply voltage line VDD and the gate of transistor M03. When switch SWaz is turned on, the voltage of capacitor C3 is reset by the power supply voltage Vdd and voltage Viso.

[0061] The current source I3 is connected between the power supply voltage line VDD and the source of the transistor M03. The current source I3 supplies a current Idark to the source of the transistor M03 to read out, for example, a signal in a non-exposed state, i.e., a dark current.

[0062] The capacitor C4 is a capacitor for generating a voltage signal by integrating the current signal output from the first amplifier circuit 30. When the capacitor C4 is charged by the current signal output from the first amplifier circuit 30, an integrated signal (voltage signal) is generated in which a proportionality coefficient is set according to the current signal, and this integrated signal is output to the second amplifier circuit 50.

[0063] The switch SWi is a switch that is turned on while integrating the signal output from the first amplifier circuit 30. When the switch SWi is turned on, the drain of the transistor M02 and the source of the transistor M03 are connected. This connection allows a potential for reading out the signal output from the pixel 140 to be applied to the source of the transistor M03, and by causing a current based on this drain potential to flow through the capacitor C4, the integration circuit 40 can generate an integrated signal based on the signal output from the pixel 140 and output it to the second amplifier circuit 50.

[0064] The switch SWr acts as an integral capacitance initialization switch to reset the potential of the capacitor C4. When the switch SWr is turned on, the potential of the capacitor C4 is reset to the power supply voltage Vss, and carriers are accumulated in this reset capacitor C4 at the timing of reading out the signal for the next phase, forming an integral potential.

[0065] The second amplifier circuit 50 includes, as a non-limiting example, transistors M04, M05, M06, M07, and a capacitor C5. The second amplifier circuit 50 is configured as an amplifier in which the drain of the transistor M03 of the integrating circuit 40 is connected to the non-inverting input terminal, and a signal line for applying a reference voltage Vref is connected to the inverting input terminal.

[0066] The transistor M04 is, for example, a p-type MOSFET, and has a source connected to the source of the transistor M05 via a switch, a drain connected to the power supply voltage line VSS, and a gate connected to the drain of the transistor M03, i.e., an integration signal is applied to the gate.

[0067] The transistor M05 is, for example, a p-type MOSFET, and has a source connected to the source of the transistor M04 via a switch, a drain connected to the power supply voltage line VSS, and a gate connected to a signal line that applies a reference voltage Vref.

[0068] The transistor M06 is, for example, an n-type MOSFET, and has a drain connected to the power supply voltage line VDD via a current source I4, a source connected to the sources of the transistors M04 and M05 via a switch, and a gate connected to the power supply voltage line via a capacitor C5.

[0069] A capacitor C5 is connected between the power supply line and the gate of transistor M06, which together with capacitor C5 sets the appropriate potential for transistor M06, and supplies the appropriate power supply voltage to capacitor C5.

[0070] The transistor M07 is, for example, a p-type MOSFET, and its source is connected to the drain of the transistor M06, its drain is connected to one end of an XOR circuit that outputs the magnitude relationship between the integrated voltage and the reference voltage Vref, and an appropriate potential for driving is applied to its gate.

[0071] A switch SWaz is connected between the source of transistor M05 and the source of transistor M06, and when this switch SWaz is turned on, the potential of the source of transistor M06, i.e., the potential of the source of transistor M04 at the timing when readout begins, is reset. At this timing, a switch SWaz between capacitor C5 and the drain of transistor M06 is also turned on, and the potentials of the drain of transistor M06 and the source of transistor M07 are reset to a value based on the power supply voltage Vdd, the current of current source I4, and capacitor C5. Furthermore, the potential of the drain of transistor M07 is also reset to the power supply voltage Vss via switch SWaz.

[0072] A switch SWxaz is connected between the source of the transistor M04 and the source of the transistor M06. This switch SWxaz is a switch that is turned on / off exclusively with the switch SWaz, that is, a switch that is turned on at the timing of reading out a signal from the pixel 140.

[0073] The configuration of the second amplifier circuit 50 is shown as an example and is not limited thereto, and other types of comparators of the signature differential amplifier type, which have an integrated signal and a reference signal Vref as inputs, can be applied.

[0074] 6 is a timing chart showing an example of the operation of the column ADC 162 according to an embodiment. Using this timing chart, the operations of the first amplifier circuit 30, the integrating circuit 40, and the second amplifier circuit 50 will be described in detail.

[0075] As a preprocessing step before starting to measure signal values, all switches SWaz are turned on. Also, to reset the integration capacitance, switch SWr is turned on and switch SWi is turned off. At this timing, switch SWxaz is turned off. At the same time, the reset transistor RST is turned on and then off, resetting the floating diffusion region in the pixel circuit of pixel 140.

[0076] When the switch SWaz is turned on, each transistor and capacitor is reset. Also, the reset transistor RST is turned on, and the signal Vsl is output along with this reset. Depending on the connection status of each switch, the other signal values ​​converge to the reset value.

[0077] This operation allows the effects of transistor variations and the like to be held in the capacitance and canceled out. That is, the column ADC 162 is initialized with the current Isig flowing entirely through the resistor R. Also, the integrated potential is reset to the power supply voltage Vss.

[0078] Switch SWaz is turned off, then switch SWr is turned off and switch SWi is turned on to move on to readout of the reset potential. By switching these switches, the outputs of current sources I1 and I2 are shorted. At this timing, the value of signal Vsl corresponds to the reset potential of the floating diffusion region, that is, the level due to dark current, so current Isig flows entirely to resistor R, and current Idark flows to capacitor C4.

[0079] As a result, the integral capacitance increases proportionally to the elapsed time with a proportionality factor that depends on the reset potential of the floating diffusion region. The proportionality factor of the integral potential ramp at this timing can be expressed as follows:

[0080] Slope represents a proportionality coefficient, and C4 represents the capacitance of the capacitor C4. At the timing when the integrated potential according to this proportionality coefficient exceeds the reference voltage Vref, the sign of the signal output from the second amplifier circuit 50 is reversed, and the counter circuit 60 counts this timing and generates a count value Count _P The count values ​​have the following relationships:

[0081] τ r Count indicates the time it takes for the integrated potential to exceed the reference voltage Vref when the reset potential of the floating diffusion region is read out. _P After the acquisition is complete, the transfer transistor TRG is turned on and the switch SWr is turned on. This action transfers the light intensity signal converted by the photodetector to the floating diffusion region and resets the capacitance of the capacitor C4. When the light received by the photodetector is low intensity, the value of the signal Vsl remains at a higher potential than when the light is high intensity, as shown by the dotted line.

[0082] After the signal Vsl has stabilized, the switch SWr is turned off, and the process moves to reading out the data of the light received by the light receiving element. If the potential of the signal Vsl drops by ΔV from the increased value during the reset period of the integral capacitance (capacitor C4), the current flowing through the capacitor C4 increases by ΔI, where r is the resistance value of the resistor R, and the time τ for the integral potential of the capacitor C4 to reach the reference voltage Vref and the count value Count of this in the counter circuit 60 are calculated. _D can be expressed as follows:

[0083] τ dindicates the time it takes for the integrated potential to exceed the reference voltage Vref during the data read period. d When the intensity of the received light is high, the h and when the light intensity is low, τ l The counter circuit 60 calculates a count value that varies depending on the light intensity according to equation (5), as Count_ D Obtain as.

[0084] Here, the potential corresponding to the intensity of light transferred to the floating diffusion region is proportional to ΔI. Therefore, the voltage value of the light intensity, i.e., the luminance value of the pixel, can be calculated from the readout time of the reset period (reset phase) and the readout time of the data period (data phase) of the pixel circuit as follows:

[0085] K is a coefficient for calculating the signal strength from the reciprocal of the count value. This coefficient K can be calculated from the respective coefficients of the circuit elements in the pixel circuit and the column ADC 162. As a result, the column ADC 162 can calculate the value of equation (6) from the count value acquired from the counter circuit 60, thereby calculating a digital signal proportional to the strength of the input analog signal, that is, realizing AD conversion.

[0086] 7 is a diagram showing the quantization granularity in AD conversion according to one embodiment, where the circle plots show the relationship between the voltage signal output from the pixel and the quantization step according to the method according to this embodiment, and the triangle plots show the relationship according to a comparative example.

[0087] As shown in this graph, according to the method of this embodiment, the integration time is proportional to the reciprocal of the signal voltage Vsl, so the count values ​​in the reset phase and the data phase are large at low luminance. Therefore, compared to the comparative example, which has a constant quantization step for all output signal values, the time resolution is improved in the low luminance range, and even when AD conversion is performed at the same gradation at low luminance, the quantization step can be improved according to the luminance.

[0088] As a result, even when trying to achieve the same quantization error, a configuration using the current integration type ADC according to this embodiment can achieve this in a short conversion time, which can also contribute to lower power consumption.

[0089] As described above, the voltage signal that has been photoelectrically converted and buffered on the vertical signal line is converted into a current signal by configuring a voltage-current conversion circuit using a column amplifier that reuses current.By integrating the light-intensity-dependent current signal in a reset capacitor, a light-intensity-dependent ramp signal is generated for each column, and the light-intensity-dependent current signal is time-converted in a comparison circuit that compares it with a reference signal, and the time is counted, thereby achieving AD conversion.

[0090] Furthermore, by performing voltage-current conversion to make the light intensity proportional to the current, the slope of the ramp signal in the low-luminance region can be reduced, thereby lengthening the integration time. Since the integration time is roughly inversely proportional to the noise integration band, this results in reduced noise.

[0091] Furthermore, for a single-slope ADC, the time required to count the light intensity signal can be allocated to the integration time, which allows for low power consumption while achieving the low noise mentioned above.

[0092] Furthermore, considering the integration time of the reference signal up to the reference value, the voltage and count time are inversely proportional. This automatically improves the time resolution in low brightness states (where the output signal from the pixel is approximately 0) and reduces the ADC quantization error. This makes it possible to shorten the time required for a single ADC quantization error conversion when increasing the number of bits, thereby achieving low power consumption and low noise.

[0093] (Third embodiment)

[0094] 8 is a circuit diagram showing another example of a column ADC 162 according to an embodiment. The main difference is the configuration of the first amplifier circuit 30, which differs from the configuration of the column ADC 162 shown in FIG. 5. As shown in this figure, a commonly used amplifier circuit with a different configuration can be used.

[0095] The first amplifier circuit 30 may include, for example, a transistor M10, a transistor M11, a transistor M12, a transistor M13, a transistor M14, and a capacitor C6. The transistor M10 is a transistor that controls the input signal and may be, for example, an n-type MOSFET.

[0096] The transistors M11 and M12 are, for example, p-type MOSFETs and form a current mirror. The transistors M13 and M14 are, for example, n-type MOSFETs and form a differential input pair. The capacitor C6 is a capacitance connected between the gate of the transistor M13 and the drain of the transistor M10.

[0097] In Figure 5, the differential signal is formed by the gate-source voltage of transistor M01, but as shown in Figure 8, it can be configured as a comparator with the gates of transistors M13 and M14 as inputs. When configured in this way, the power supply potential of the differential circuit can be set arbitrarily by using an N-channel cascode connection.

[0098] However, the configuration of the first amplifier circuit 30 is not limited to these, and it may be any amplifier circuit that amplifies and outputs the comparison result.

[0099] (Fourth embodiment)

[0100] 9, 10, and 11 are circuit diagrams showing other implementation examples of the resistor R of the integrating circuit 40 according to an embodiment. The resistor R may be configured as a variable resistor that combines multiple resistors and multiple switches.

[0101] In FIG. 9, resistor R has a configuration including multiple resistors connected in series and switches between the terminals of the resistors and the output terminal connected to capacitor C1. For example, by turning on the top switch and turning off the other switches, resistor R can be formed with a resistance equal to the sum of all the resistance values. By turning on the top and second switches and turning off the other switches, resistor R can be formed with a resistance equal to the sum of the three resistance values ​​below. In this way, the resistance value can be changed by turning on the top switch and any of the switches.

[0102] Alternatively, the top switch may be turned off. In this case, the current fed back to the first amplifier circuit 30 can be proportionally divided according to the ratio of the connected resistance values.

[0103] 10, the resistors R are configured such that the nodes of the resistors R are connected via switches (the switches and resistors are configured in parallel). In this configuration, the current fed back to the first amplifier circuit 30 can be controlled by connecting the switches.

[0104] 11, the resistor R has a configuration (R-2R configuration) in which an additional resistor is connected in parallel to the configuration in FIG. 9. In this configuration as well, the resistance value can be controlled in the same way as in the configuration in FIG.

[0105] As described above, by making the resistor R variable, it is possible to achieve a configuration in which the dynamic range of the luminance value input as an analog signal can be made variable.

[0106] Note that instead of making the resistance value of the resistor R variable, the current Isig output from the current source I2 may be made variable. In this case as well, a configuration that enables switching of the dynamic range can be achieved. Furthermore, as shown in the following embodiment, it is also possible to switch the gain of the capacitance instead of the resistance value of the resistor R.

[0107] (Fifth embodiment)

[0108] 12 is a circuit diagram illustrating an example of an ADC according to an embodiment. As described above, instead of varying the resistance of resistor R, the relationship between the voltage value of input signal Vsl and the voltage value fed back from integration circuit 40 can be changed by switching the gain of the capacitance.

[0109] The first amplifier circuit 30 may include, for example, a capacitor C10 and a capacitor C11. The capacitor C10 is a capacitor that has the same connection as the capacitor C1 in Fig. 5. The capacitor C10 may have a variable capacitance (capacitance is c10).

[0110] The capacitor C11 is connected between one end of the capacitor C10 and the power supply voltage line VSS, and may be a variable capacitance capacitor (having a capacitance of c11).

[0111] When this capacitor is connected, the change amount ΔV of the voltage signal input via the signal line 160 is i and the change in the voltage signal fed back from the integrator circuit 40, ΔV o The relationship can be expressed as follows:

[0112] Therefore, by appropriately changing the capacitance of these capacitors, it is possible to switch the gain between the voltage value of the input signal Vsl and the voltage value of the feedback signal. As a result, as in each of the above-mentioned embodiments, it is possible to switch the gain, i.e., switch the dynamic range of the brightness value, without using the resistor R as a variable resistor.

[0113] Of course, in addition to implementing this variable capacitance, it is also possible to implement resistor R as a variable resistor.

[0114] The above-described embodiment may be modified as follows.

[0115] (1) A solid-state imaging device comprising: a pixel circuit that photoelectrically converts incident light and outputs a first voltage signal corresponding to the intensity; a first amplifier circuit that receives the first voltage signal and a feedback signal and outputs a current signal based on the magnitude of the first voltage signal; an integration circuit that integrates the current signal and outputs a second voltage signal; and a second amplifier circuit that amplifies and outputs the difference between the second voltage signal and a reference voltage signal.

[0116] (2) The solid-state imaging device according to (1), wherein the pixel circuits are arranged in a two-dimensional array in a pixel array, and the pixel circuits belonging to the same column share the first amplifier circuit, the integration circuit, and the second amplifier circuit.

[0117] (3) The solid-state imaging device described in (1) or (2), wherein the first amplifier circuit comprises: a first transistor having a first terminal to which the first voltage signal is applied and a second terminal to which the current signal is output; and a first capacitor having a first terminal connected to the integrating circuit, a first terminal to which the current output from the integrating circuit is input, and a second terminal connected to the gate of the first transistor.

[0118] (4) The solid-state imaging device according to (3), wherein the integrating circuit comprises: a second capacitor having a first terminal connected to the second terminal of the first transistor; a second transistor having a first terminal connected to a positive power supply voltage line via a current source, a second terminal connected to the first terminal of the first capacitor, and a gate connected to the second terminal of the second capacitor; a resistor having a first terminal connected to the second terminal of the second transistor and a second terminal connected to a negative power supply voltage line; a third transistor having a first terminal connected to the positive power supply voltage line via a current source, outputting the second voltage signal from a second terminal, and a gate connected to the positive power supply voltage line via the second capacitor; a switch connected between the first terminal of the second transistor and the first terminal of the third transistor; and a fourth capacitor having a first terminal connected to the second terminal of the third transistor and a second terminal connected to a negative power supply voltage line.

[0119] (5) The solid-state imaging device described in (4), wherein the second amplifier circuit has a non-inverting input terminal connected to the second terminal of the third transistor and the first terminal of the fourth capacitor, and the reference voltage signal is applied to an inverting input terminal.

[0120] (6) The solid-state imaging device according to (4) or (5), further comprising: an initialization switch between the second terminal and the gate of the first transistor; and between the first terminal and the gate of the second transistor.

[0121] (7) The solid-state imaging device according to any one of (4) to (6), further comprising: an integral capacitance initialization switch between the first terminal and the second terminal of the fourth capacitor.

[0122] (8) The solid-state imaging device according to any one of (4) to (7), wherein the resistor is a variable resistor.

[0123] (9) A converter comprising: a pixel circuit that outputs a first voltage signal corresponding to the intensity of incident light; a first amplifier circuit that receives the first voltage signal and a feedback signal and outputs a current signal based on the magnitude of the first voltage signal; an integration circuit that integrates the current signal and outputs a second voltage signal; and a second amplifier circuit that amplifies and outputs the difference between the second voltage signal and a reference voltage signal.

[0124] The aspects of the present disclosure are not limited to the above-described embodiments and include various conceivable modifications, and the effects of the present disclosure are not limited to the above-described contents. The components in each embodiment may be appropriately combined and applied. In other words, various additions, modifications, and partial deletions are possible within the scope of the conceptual idea and intent of the present disclosure, which is derived from the content defined in the claims and their equivalents.

[0125] 1: solid-state imaging device, 10: first drive circuit, 100: signal line, 12: second drive circuit, 120: signal line, 14: pixel array, 140: pixel, TRG: transfer transistor, RST: reset transistor, AMP: amplification transistor, SEL: selection transistor, 16: ADC, 160: signal line, 162: column ADC, 164: pixel ADC, VDD, VSS: power supply voltage line, 30: first amplifier circuit, M01: transistor, M10, M11, M12, M13, M14: transistor, C1: capacitor, C6: capacitor, SWaz: switch, I1: current source, C10, C11: capacitor, 40: integrator circuit, M02, M03: transistor, R: resistor, C2, C3, C4: capacitor, I2, I3: current source, SWi, SWr: switch, 50: second amplifier circuit, M04, M05, M06, M07: transistor, C5: capacitor, I4: current source, SWxaz: switch, 60: counter circuit, 18: logic circuit, 2: semiconductor substrate, 20: first substrate, 22: second substrate

Claims

1. A solid-state imaging device comprising: a pixel circuit that photoelectrically converts incident light and outputs a first voltage signal corresponding to the intensity; a first amplifier circuit that receives the first voltage signal and a feedback signal and outputs a current signal based on the magnitude of the first voltage signal; an integration circuit that integrates the current signal and outputs a second voltage signal; and a second amplifier circuit that amplifies and outputs the difference between the second voltage signal and a reference voltage signal.

2. The solid-state imaging device according to claim 1, wherein the pixel circuits are arranged in a two-dimensional array in a pixel array, and the pixel circuits belonging to the same column share the first amplifier circuit, the integration circuit, and the second amplifier circuit.

3. The solid-state imaging device of claim 1, wherein the first amplifier circuit comprises: a first transistor having a first terminal to which the first voltage signal is applied and a second terminal to which the current signal is output; and a first capacitor having a first terminal connected to the integrating circuit, a first terminal to which the current output from the integrating circuit is input, and a second terminal connected to the gate of the first transistor.

4. The solid-state imaging device of claim 3, wherein the integrating circuit comprises: a second capacitor having a first terminal connected to the second terminal of the first transistor; a second transistor having a first terminal connected to a positive power supply voltage line via a current source, a second terminal connected to the first terminal of the first capacitor, and a gate connected to the second terminal of the second capacitor; a resistor having a first terminal connected to the second terminal of the second transistor and a second terminal connected to a negative power supply voltage line; a third transistor having a first terminal connected to the positive power supply voltage line via a current source, outputting the second voltage signal from a second terminal, and a gate connected to the positive power supply voltage line via the second capacitor; a switch connected between the first terminal of the second transistor and the first terminal of the third transistor; and a fourth capacitor having a first terminal connected to the second terminal of the third transistor and a second terminal connected to a negative power supply voltage line.

5. The solid-state imaging device according to claim 4, wherein the second amplifier circuit has a non-inverting input terminal connected to the second terminal of the third transistor and the first terminal of the fourth capacitor, and an inverting input terminal to which the reference voltage signal is applied.

6. The solid-state imaging device according to claim 4, further comprising: an initialization switch between the second terminal and the gate of the first transistor; and an initialization switch between the first terminal and the gate of the second transistor.

7. The solid-state imaging device according to claim 4, further comprising: an integral capacitance initialization switch between the first terminal and the second terminal of the fourth capacitor.

8. The solid-state imaging device according to claim 4, wherein the resistor is a variable resistor.

9. A converter comprising: a pixel circuit that outputs a first voltage signal corresponding to the intensity of incident light; a first amplifier circuit that receives the first voltage signal and a feedback signal and outputs a current signal based on the magnitude of the first voltage signal; an integration circuit that integrates the current signal and outputs a second voltage signal; and a second amplifier circuit that amplifies and outputs the difference between the second voltage signal and a reference voltage signal.

Images