Display device and electronic device including display device

Abstract

This display device comprises: a pixel circuit layer including a pixel circuit; a first light-emitting element layer that is disposed on the pixel circuit layer and includes a first light-emitting element generating light of a first color and first conductive patterns spaced apart from the first light-emitting element on a plane; a second light-emitting element layer that is disposed on the first light-emitting element layer and includes a second light-emitting element generating light of a second color different from the first color and spaced apart from the first light-emitting element on a plane and second conductive patterns connected to the first conductive patterns; and a third light-emitting element layer that is disposed on the second light-emitting element layer and includes a third light-emitting element generating light of a third color different from the first color and the second color and spaced apart from the first light-emitting element and the second light-emitting element on a plane and third conductive patterns connected to the second conductive patterns.

Description

Display devices and electronic devices including display devices

[0001] The present invention relates to a display device. Specifically, the present invention relates to a display device, a method for manufacturing the display device, and an electronic device including the display device.

[0002] As interest in information displays has grown recently, research and development on display devices are continuously being conducted.

[0003] The problem to be solved by the present invention is to provide a display device with improved reliability and improved light emission efficiency.

[0004] A display device according to embodiments of the present invention includes a pixel circuit layer including a pixel circuit, a first light-emitting element layer disposed on the pixel circuit layer and including a first light-emitting element that generates light of a first color and first conductive patterns spaced apart from the first light-emitting element on a plane, a second light-emitting element layer disposed on the first light-emitting element layer and including a second light-emitting element that generates light of a second color different from the first color and spaced apart from the first light-emitting element on a plane, and second conductive patterns connected to the first conductive patterns, and a third light-emitting element layer disposed on the second light-emitting element layer and including a third light-emitting element that generates light of a third color different from the first color and the second color and spaced apart from the first light-emitting element and the second light-emitting element on a plane, and third conductive patterns connected to the second conductive patterns.

[0005] In one embodiment, each of the first conductive patterns is disposed between the first to third light-emitting elements on a plane without overlapping with the first to third light-emitting elements, the second conductive patterns overlap with the first conductive patterns on a plane, and the third conductive patterns overlap with the second conductive patterns on a plane, respectively.

[0006] In one embodiment, each of the first to third conductive patterns may include a connecting electrode and a reflective electrode covering at least a portion of the connecting electrode.

[0007] In one embodiment, the reflective electrode may cover a side of the connecting electrode.

[0008] In one embodiment, the connecting electrode may comprise at least one of copper and tungsten, and the reflective electrode may comprise at least one of aluminum and silver.

[0009] In one embodiment, the display device may further include a first conductive layer disposed between the first light-emitting element layer and the second light-emitting element layer, a second conductive layer disposed between the second light-emitting element layer and the third light-emitting element layer, and a third conductive layer disposed on the third light-emitting element layer.

[0010] In one embodiment, the first conductive layer may be in contact with the first light-emitting element, the first conductive patterns, and the second conductive patterns, the second conductive layer may be in contact with the second light-emitting element, the second conductive patterns, and the third conductive patterns, and the third conductive layer may be in contact with the third light-emitting element and the third conductive patterns.

[0011] In one embodiment, each of the first to third conductive layers may include indium tin oxide (ITO).

[0012] In one embodiment, the display device may further include a first connection pattern overlapping the second light-emitting element and connecting the pixel circuit layer and the second light-emitting element, and a second connection pattern overlapping the third light-emitting element and connecting the pixel circuit layer and the third light-emitting element.

[0013] In one embodiment, each of the first connection pattern and the second connection pattern may include at least one of copper and tungsten.

[0014] In one embodiment, the first conductive layer may include a first bridge pattern overlapping the second light-emitting element and in contact with the first connection pattern, and a second bridge pattern overlapping the third light-emitting element and in contact with the second connection pattern, and a first opening may be defined in the first conductive layer around the first bridge pattern, and a second opening may be defined in the first conductive layer around the second bridge pattern.

[0015] In one embodiment, the second conductive layer includes a third bridge pattern overlapping the third light-emitting element and in contact with the second connecting pattern, and a third opening can be defined in the second conductive layer around the third bridge pattern.

[0016] In one embodiment, the first light-emitting element layer may further include first bonding patterns connected to the pixel circuit layer, the first light-emitting element, the first connection pattern, and the second connection pattern.

[0017] In one embodiment, the second light-emitting element layer may further include a second bonding pattern connected to the first connection pattern and the second light-emitting element.

[0018] In one embodiment, the third light-emitting element layer may further include a third bonding pattern connected to the second connection pattern and the third light-emitting element.

[0019] In one embodiment, the display device may further include a lens layer disposed on the third light-emitting element layer and including lenses that overlap each of the first to third light-emitting elements.

[0020] A display device including first to fourth sub-pixel areas according to embodiments of the present invention includes a pixel circuit layer including a pixel circuit, first to fourth sub-pixels respectively disposed in the first to fourth sub-pixel areas, a first light-emitting element layer disposed on the pixel circuit layer and including a first light-emitting element disposed in the second sub-pixel area, a first light-emitting element disposed in the fourth sub-pixel area, and first conductive patterns disposed between the first to fourth sub-pixel areas, a second light-emitting element layer disposed on the first light-emitting element layer and including a third light-emitting element disposed in the third sub-pixel area and second conductive patterns disposed between the first to fourth sub-pixel areas and overlapping the first conductive patterns, and a third light-emitting element layer disposed on the second light-emitting element layer and including a third light-emitting element disposed in the first sub-pixel area and third conductive patterns disposed between the first to fourth sub-pixel areas and overlapping the first and second conductive patterns, respectively.

[0021] In one embodiment, the display device may further include a first conductive layer disposed between the first light-emitting element layer and the second light-emitting element layer and connected to the 1-1 light-emitting element, the 1-2 light-emitting element, the first conductive patterns and the second conductive patterns, a second conductive layer disposed between the second light-emitting element layer and the third light-emitting element layer and connected to the second light-emitting element, the second conductive patterns and the third conductive patterns, and a third conductive layer disposed on the third light-emitting element layer and connected to the third light-emitting element and the third conductive patterns.

[0022] In one embodiment, the first light-emitting element layer further includes a first-first connection pattern overlapping the third sub-pixel area, the second light-emitting element layer further includes a first-second connection pattern overlapping the third sub-pixel area and connected to the first-first connection pattern and the second light-emitting element, and the first-first connection pattern and the first-second connection pattern can be connected to each other through the first conductive layer.

[0023] In one embodiment, the first light-emitting element layer further includes a 2-1 connection pattern overlapping the first sub-pixel area, the second light-emitting element layer further includes a 2-2 connection pattern overlapping the first sub-pixel area and connected to the 2-1 connection pattern, the third light-emitting element layer further includes a 2-3 connection pattern overlapping the first sub-pixel area and connected to the 2-2 connection pattern and the third light-emitting element, and the 2-1 connection pattern and the 2-2 connection pattern are connected to each other through the first conductive layer, and the 2-2 connection pattern and the 2-3 connection pattern are connected to each other through the second conductive layer.

[0024] An electronic device according to embodiments of the present invention includes a processor for providing input image data; and a display device for displaying an image according to the input image data, wherein the display device includes a pixel circuit layer including a pixel circuit; a first light-emitting element layer disposed on the pixel circuit layer and including a first light-emitting element that generates light of a first color and first conductive patterns spaced apart from the first light-emitting element on a plane; a second light-emitting element layer disposed on the first light-emitting element layer and including a second light-emitting element that generates light of a second color different from the first color and spaced apart from the first light-emitting element on a plane and second conductive patterns connected to the first conductive patterns; and a third light-emitting element layer disposed on the second light-emitting element layer and including a third light-emitting element that generates light of a third color different from the first color and the second color and spaced apart from the first light-emitting element and the second light-emitting element on a plane and third conductive patterns connected to the second conductive patterns.

[0025] Specific details of other embodiments are included in the detailed description and drawings.

[0026] According to the above-described embodiment, the display device includes first to third light-emitting element layers each including light-emitting elements that generate different lights, and each of the first to third light-emitting element layers further includes conductive patterns having a mesh structure that are arranged entirely on the display panel and connected to each other, so that the voltage drop (IR Drop) phenomenon, in which the voltage drops due to resistance as it moves toward the center of the display area, can be reduced. As a result, the contact resistance can also be minimized.

[0027] Additionally, since each of the challenge patterns includes a reflective electrode on its side, light generated by the light-emitting elements can be reflected and emitted to the display surface of the display device. This can improve the light output efficiency of the display device.

[0028] The effects according to the embodiments are not limited to those exemplified above, and more diverse effects are included in this specification.

[0029] Figure 1 is a block diagram showing an embodiment of a display device.

[0030] FIG. 2 is a block diagram showing an embodiment of one of the sub-pixels of FIG. 1.

[0031] FIG. 3 is a plan view showing an embodiment of the display panel of FIG. 1.

[0032] FIG. 4 is a cross-sectional view showing an embodiment of the display panel of FIG. 3.

[0033] FIG. 5 is a cross-sectional view showing another embodiment of the display panel of FIG. 3.

[0034] Fig. 6 is a plan view showing an enlarged portion of a display area of ​​the display panel of Fig. 3.

[0035] Figure 7 is a cross-sectional view taken along line I-I' of Figure 6.

[0036] Fig. 8 is an enlarged cross-sectional view of the first light-emitting element of Fig. 7.

[0037] Fig. 9 is a plan view showing an enlarged portion of a non-display area of ​​the display panel of Fig. 3.

[0038] Fig. 10 is a cross-sectional view taken along line II-II' of Fig. 9.

[0039] Fig. 11 is a plan view showing an enlarged portion of a pad area of ​​the display panel of Fig. 3.

[0040] Fig. 12 is a cross-sectional view taken along line III-III' of Fig. 11.

[0041] Fig. 13 is a cross-sectional view showing another embodiment of Fig. 7.

[0042] Fig. 14 is a cross-sectional view showing another embodiment of Fig. 10.

[0043] Fig. 15 is a cross-sectional view showing another embodiment of Fig. 12.

[0044] FIGS. 16 to 46 are drawings showing a method for manufacturing a display device (display panel) according to one embodiment of the present invention.

[0045] FIG. 47 is a schematic block diagram illustrating an electronic device (1000) including a display device according to one embodiment.

[0046] FIG. 48 is a schematic diagram illustrating an embodiment in which the electronic device (1000) of FIG. 47 is a smartphone.

[0047] FIG. 49 is a schematic diagram illustrating an embodiment in which the electronic device (1000) of FIG. 47 is a tablet computer.

[0048] The present invention will now be described in more detail below with reference to the accompanying drawings, which illustrate various embodiments. However, the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Like reference numerals designate like elements throughout.

[0049] When an element is referred to as being "on" another element, it is understood that it is either directly on top of the other element, or that there may be intervening elements between them. Conversely, when an element is referred to as being "directly on" another element, there are no intervening elements.

[0050] Although the terms "first," "second," "third," etc. may be used to describe various elements, components, regions, layers, and / or sections, such elements, components, regions, layers, and / or sections should not be limited by such terms. These terms are used only to distinguish one element, component, region, layer, or section from another element, component, region, layer, or section. Thus, a "first element," "component," "region," "layer," or "section" discussed below could also be referred to as a second element, component, region, layer, or section without departing from the teachings of this disclosure.

[0051] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the terms "a" and "at least one" do not denote limitations on quantity and are intended to cover both the singular and the plural, unless the context clearly dictates otherwise. Thus, in the claims, a reference to "an" element followed by a reference to "the" element includes both the single element and the plural elements. For example, "an element" has the same meaning as "at least one element," unless the context clearly dictates otherwise. "At least one" should not be construed as limiting "an." "Or" means "and / or." As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. It will be further understood that the terms "comprises" and / or "comprising" or "includes" and / or "comprising" as used herein specify the presence of stated features, regions, integers, steps, operations, elements and / or components, but do not preclude the presence or addition of one or more other features, regions, integers, steps, operations, elements, components and / or groups thereof.

[0052] Additionally, relative terms such as "lower" or "bottom" and "upper" or "top" may be used to describe the relationship of one element to another as depicted in the drawings. It will be understood that relative terms are intended to encompass other orientations of the device in addition to the orientation depicted in the drawings. For example, if one device in the drawings is flipped, an element described as being on the "lower" side of another element is oriented on the "upper" side of the other element. Thus, the term "lower" may encompass both the "lower" and "upper" orientations depending on the particular orientation of the drawing. Similarly, if one device in the drawings is flipped, an element described as being "below" or "beneath" another element is oriented "above" the other element. Thus, the term "lower" or "beneath" may encompass both the above and below orientations.

[0053] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. Terms defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the relevant art and the context of this disclosure, and will not be interpreted in an idealized or overly formal sense unless explicitly defined herein.

[0054] Embodiments are described herein with reference to cross-sectional drawings, which are schematic drawings of idealized embodiments. Therefore, variations in the shapes of the drawings may occur, for example, as a result of manufacturing techniques and / or tolerances. Therefore, the embodiments described herein should not be construed as limited to the specific shapes of the regions described herein, but should encompass, for example, variations in shape resulting from manufacturing. For example, regions described or described as being flat may generally have rough and / or non-linear features. Furthermore, sharp angles depicted may be rounded. Therefore, the regions depicted in the drawings are schematic in nature, and their shapes are not intended to depict the precise shapes of the regions, nor are they intended to limit the scope of the present invention.

[0055] Figure 1 is a block diagram showing an embodiment of a display device.

[0056] Referring to FIG. 1, an embodiment of a display device (DD) may include a display panel (DP), a gate driver (120), a data driver (130), a voltage generator (140), and a controller (150).

[0057] The display panel (DP) includes sub-pixels (SP). The sub-pixels (SP) can be connected to a gate driver (120) through first to m-th gate lines (GL1 to GLm). The sub-pixels (SP) can be connected to a data driver (130) through first to n-th data lines (DL1 to DLn). Here, m and n are natural numbers greater than 1.

[0058] The sub-pixels (SP) can generate light of two or more colors. In one embodiment, for example, each of the sub-pixels (SP) can generate light of red, green, blue, cyan, magenta, yellow, etc.

[0059] Two or more sub-pixels among the sub-pixels (SP) may constitute or collectively define a pixel (PXL). In one embodiment, for example, the pixel (PXL) may be defined by four sub-pixels as illustrated in FIG. 1. In such an embodiment, the pixel (PXL) may emit light of various colors and various luminances depending on the combination of light emitted from the sub-pixels included therein.

[0060] The gate driver (120) is connected to the sub-pixels (SP) arranged in the row direction through the first to m-th gate lines (GL1 to GLm). The gate driver (120) can output gate signals to the first to m-th gate lines (GL1 to GLm) in response to a gate control signal (GCS). In one embodiment, the gate control signal (GCS) can include a start signal indicating the start of each frame, a horizontal synchronization signal, and the like.

[0061] In one embodiment, for example, the gate driver (120) may be disposed on one side of the display panel (DP). However, the embodiments are not limited thereto. In another embodiment, for example, the gate driver (120) may be divided into two or more drivers that are physically and / or logically separated, and such drivers may be disposed on one side of the display panel (DP) and on the other side of the display panel (DP) opposite to the one side. In these embodiments, the gate driver (120) may be disposed on the periphery of the display panel (DP) in various forms depending on the embodiments.

[0062] The data driver (130) is connected to the sub-pixels (SP) arranged in the column direction through the first to nth data lines (DL1 to DLn). The data driver (130) receives image data (DATA) and a data control signal (DCS) from the controller (150). The data driver (130) operates in response to the data control signal (DCS). In one embodiment, the data control signal (DCS) may include a source start signal, a source shift clock, a source output enable signal, etc.

[0063] The data driver (130) can receive voltages from the voltage generator (140). The data driver (130) can use the received voltages to apply data signals having grayscale voltages corresponding to image data (DATA) to the first to n-th data lines (DL1 to DLn). When a gate signal is applied to each of the first to m-th gate lines (GL1 to GLm), data signals corresponding to the image data (DATA) can be applied to the data lines (DL1 to DLn). Accordingly, the sub-pixels (SP) can generate light corresponding to the data signals, and the display panel (DP) can display an image.

[0064] In one embodiment, the gate driver (120) and data driver (130) may include complementary metal-oxide semiconductor (CMOS) circuit elements.

[0065] The voltage generator (140) can operate in response to a voltage control signal (VCS) from the controller (150). The voltage generator (140) is configured to generate a plurality of voltages and provide the generated voltages to components of the display device (DD), such as the gate driver (120), the data driver (130), and the controller (150). The voltage generator (140) can generate a plurality of voltages by receiving an input voltage from the outside of the display device (DD) and regulating the received voltage.

[0066] A voltage generator (140) can generate a first power voltage and a second power voltage. The generated first and second power voltages can be provided to the sub-pixels (SP) through power lines (PL). In another embodiment, at least one of the first and second power voltages can be provided from outside the display device (DD).

[0067] In addition, the voltage generator (140) can provide various voltages and / or signals. In one embodiment, for example, the voltage generator (140) can provide one or more initialization voltages applied to the sub-pixels (SP). In one embodiment, for example, during a sensing operation for sensing electrical characteristics of transistors and / or light-emitting elements of the sub-pixels (SP), a predetermined reference voltage can be applied to the first to n-th data lines (DL1 to DLn), and the voltage generator (140) can generate the reference voltage and transmit it to the data driver (130). In one embodiment, for example, during a display operation for displaying an image on the display panel (DP), common pixel control signals can be applied to the sub-pixels (SP), and the voltage generator (140) can generate the pixel control signals. In one embodiment, the voltage generator (140) can provide pixel control signals to the sub-pixels (SP) via pixel control lines (PXCL). FIG. 1 illustrates that the pixel control lines (PXCL) are connected between the voltage generator (140) and the display panel (DP), but embodiments are not limited thereto. In one embodiment, for example, the pixel control lines (PXCL) can be connected between the gate driver (120) and the display panel (DP). In such an embodiment, the pixel control signals can be transmitted from the voltage generator (140) to the pixel control lines (PXCL) via the gate driver (120).

[0068] The controller (150) controls all operations of the display device (DD). The controller (150) receives input image data (IMG) and a corresponding control signal (CTRL) from the outside. In response to the control signal (CTRL), the controller (150) can provide a gate control signal (GCS), a data control signal (DCS), and a voltage control signal (VCS).

[0069] The controller (150) can convert input image data (IMG) to be suitable for a display device (DD) or a display panel (DP) and output image data (DATA). In one embodiment, the controller (150) can output image data (DATA) by aligning the input image data (IMG) to be suitable for sub-pixels (SP) in a row unit.

[0070] Two or more components of the data driver (130), the voltage generator (140), and the controller (150) may be implemented in a single integrated circuit. In one embodiment, as illustrated in FIG. 1, the data driver (130), the voltage generator (140), and the controller (150) may be included in a driver integrated circuit (DIC). In this case, the data driver (130), the voltage generator (140), and the controller (150) may be functionally separate components within a single driver integrated circuit (DIC). In another embodiment, at least one of the data driver (130), the voltage generator (140), and the controller (150) may be provided as a separate component from the driver integrated circuit (DIC).

[0071] Fig. 2 is a block diagram showing an embodiment of one of the sub-pixels of Fig. 1. In Fig. 2, a sub-pixel (SPij) arranged in an ith row (i is an integer greater than or equal to 1 and less than or equal to m) and a jth column (j is an integer greater than or equal to 1 and less than or equal to n) among the sub-pixels (SP) of Fig. 1 is exemplarily illustrated.

[0072] Referring to FIG. 2, an embodiment of a sub-pixel (SPij) may include a sub-pixel circuit (SPC) and a light-emitting element (LD).

[0073] A light emitting element (LD) may be connected between a first power supply voltage node (VDDN) and a second power supply voltage node (VSSN). The first power supply voltage node (VDDN) may be connected to one of the power supply lines (PL) of FIG. 1 and may receive a first power supply voltage. The second power supply voltage node (VSSN) may be connected to another of the power supply lines (PL) of FIG. 1 and may receive a second power supply voltage. The first power supply voltage may have a higher voltage level than the second power supply voltage.

[0074] A light emitting element (LD) is connected between an anode electrode (AE) and a cathode electrode (CE). The anode electrode (AE) may be connected to a first power supply voltage node (VDDN) through a sub-pixel circuit (SPC). In one embodiment, for example, the anode electrode (AE) may be connected to the first power supply voltage node (VDDN) through one or more transistors included in the sub-pixel circuit (SPC). The cathode electrode (CE) may be connected to a second power supply voltage node (VSSN). The light emitting element (LD) is configured to emit light according to a current flowing from the anode electrode (AE) to the cathode electrode (CE).

[0075] The sub-pixel circuit (SPC) may be connected to the ith gate line (GLi) among the first to mth gate lines (GL1 to GLm) of FIG. 1 and to the jth data line (DLj) among the first to nth data lines (DL1 to DLn) of FIG. 1. In response to a gate signal received through the ith gate line (GLi), the sub-pixel circuit (SPC) controls the light-emitting element (LD) to emit light according to a data signal received through the jth data line (DLj). In one embodiment, the sub-pixel circuit (SPC) may be further connected to the pixel control lines (PXCL) of FIG. 1. In this embodiment, the sub-pixel circuit (SPC) may further control the light-emitting element (LD) in response to pixel control signals received through the pixel control lines (PXCL).

[0076] To perform these operations, a sub-pixel circuit (SPC) may include pixel circuits, for example transistors and one or more capacitors.

[0077] The transistors of the sub-pixel circuit (SPC) may include P-type transistors and / or N-type transistors. In one embodiment, the transistors of the sub-pixel circuit (SPC) may include MOSFETs (Metal Oxide Silicon Field Effect Transistors). In one embodiment, the transistors of the sub-pixel circuit (SPC) may include amorphous silicon semiconductors, monocrystalline silicon semiconductors, polycrystalline silicon semiconductors, oxide semiconductors, etc.

[0078] FIG. 3 is a plan view showing an embodiment of the display panel of FIG. 1.

[0079] Referring to FIG. 3, an embodiment of a display panel (DP) may include a display area (DA), a non-display area (NDA), and a pad area (PA). The display panel (DP) displays an image through the display area (DA). The pad area (PA) is spaced apart from the display area (DA) in a second direction (DR2). The non-display area (NDA) is arranged around the display area (DA).

[0080] A display panel (DP) includes sub-pixels (SP) in a display area (DA). The sub-pixels (SP) may be arranged along a first direction (DR1) and a second direction (DR2) intersecting the first direction (DR1) when viewed in a plan view or from a third direction (DR3). Here, the third direction (DR3) may be a direction perpendicular to the first direction (DR1) and the second direction (DR2) or a thickness direction of the display panel (DP). In one embodiment, for example, the sub-pixels (SP) may be arranged in a matrix form along the first direction (DR1) and the second direction (DR2). In another embodiment, for example, the sub-pixels (SP) may be arranged in a zigzag form along the first direction (DR1) and the second direction (DR2). The arrangement of the sub-pixels (SP) may vary depending on the embodiments. The first direction (DR1) may be a row direction, and the second direction (DR2) may be a column direction.

[0081] Among the plurality of sub-pixels (SP), two or more sub-pixels may constitute one pixel (PXL) or may be collectively defined. In FIG. 3, an embodiment in which a pixel (PXL) is defined by four sub-pixels (SP1 to SP4) is illustrated, but the embodiments are not limited thereto. In other embodiments, for example, a pixel (PXL) may include two or three sub-pixels. Hereinafter, for convenience of explanation, an embodiment in which a pixel (PXL) is defined by first to fourth sub-pixels (SP1 to SP4) will be mainly described.

[0082] Each of the first to fourth sub-pixels (SP1 to SP4) can generate light of one of various colors, such as red, green, blue, cyan, magenta, and yellow. Hereinafter, for convenience of explanation, embodiments in which the first sub-pixel (SP1) is configured to generate red color light, the second sub-pixel (SP2) and the fourth sub-pixel (SP4) are configured to generate green color light, and the third sub-pixel (SP3) generates blue color light will be mainly described below.

[0083] Each of the first to fourth sub-pixels (SP1 to SP4) may include at least one light-emitting element configured to generate light. In one embodiment, the light-emitting elements of the first to fourth sub-pixels (SP1 to SP4) may generate light of the same color. In one embodiment, for example, the light-emitting elements of the first to fourth sub-pixels (SP1 to SP4) may generate blue light. In another embodiment, the light-emitting elements of the first to fourth sub-pixels (SP1 to SP4) may generate light of different colors. In one embodiment, for example, the light-emitting elements of the first to fourth sub-pixels (SP1 to SP4) may generate red light, green light, blue light, and green light, respectively.

[0084] As a display panel (DP), a self-luminous display panel such as a light-emitting diode display panel (LED display panel) that uses micro-scale or nano-scale light-emitting diodes as light-emitting elements, or an organic light-emitting display panel (OLED panel) that uses organic light-emitting diodes as light-emitting elements, can be used.

[0085] In the non-display area (NDA), components for controlling sub-pixels (SP) and transmitting signals from pads (PD) may be arranged. In the non-display area (NDA), signal lines may be arranged, which are included in the power lines (PL) of FIG. 1 and which supply the second power voltage (VSSN) of FIG. 2, and which are respectively connected to the first to m-th gate lines (GL1 to GLm) and the first to n-th data lines (DL1 to DLn) of FIG. 1.

[0086] The common electrode (CME) can receive a second power supply voltage (VSSN) from some (for example, at least one) of the pads (PD) and supply the second power supply voltage (VSSN) to the N-type semiconductor layer of the light-emitting element, and some of the pads (PD) except for the pads (PD) that supply the second power supply voltage (VSSN) can supply the first power supply voltage (VDDN) to the P-type semiconductor layer of the light-emitting element. The light-emitting element can emit light due to the voltage difference between the first power supply voltage (VDDN) and the second power supply voltage (VSSN).

[0087] At least one of the gate driver (120), the data driver (130), the voltage generator (140), and the controller (150) of FIG. 1 may be disposed in a non-display area (NDA) of the display panel (DP). In one embodiment, the gate driver (120) may be disposed in the non-display area (NDA). In this embodiment, the data driver (130), the voltage generator (140), and the controller (150) may be implemented as a driver integrated circuit (DIC) of FIG. 1 that is separate from the display panel (DP), and the driver integrated circuit (DIC) may be connected to wires disposed in the non-display area (NDA) via pads (PD). In another embodiment, the gate driver (120) may be implemented as a single integrated circuit that is separate from the display panel (DP) together with the data driver (130), the voltage generator (140), and the controller (150).

[0088] In the pad area (PA), pads (PD) may be arranged, each connected to wires (e.g., common electrode (CME) and signal lines) arranged in the non-display area (NDA). The pads (PD) may be connected to a driver integrated circuit (DIC).

[0089] In one embodiment, the display area (DA) may have one of various shapes on the plane. The display area (DA) may have the shape of a closed loop including straight and / or curved edges. In one embodiment, for example, the display area (DA) may have one of various shapes on the plane, such as a polygon, a circle, a semicircle, or an ellipse.

[0090] In one embodiment, the display panel (DP) may have a flat display surface. In another embodiment, the display panel (DP) may have an at least partially rounded display surface. In one embodiment, the display panel (DP) may be bendable, foldable, or rollable. In such embodiments, the display panel (DP) and / or the substrate of the display panel (DP) may include materials having flexible properties.

[0091] FIG. 4 is a cross-sectional view showing an embodiment of the display panel of FIG. 3.

[0092] Referring to FIG. 4, an embodiment of a display panel (DP) may include a substrate (SUB), and a pixel circuit layer (PCL), a display element layer (DPL), and a light functional layer (or color conversion layer) (LFL) that are sequentially laminated on the substrate (SUB) in a thickness direction of the substrate (SUB) or in a third direction (DR3) intersecting the first and second directions (DR1, DR2).

[0093] The substrate (SUB) may be made of or include an insulating material such as glass or resin. In one embodiment, for example, the substrate (SUB) may include a glass substrate. In another embodiment, for example, the substrate (SUB) may include a polyimide (PI) substrate. In yet another embodiment, for example, the substrate (SUB) may include a silicon wafer substrate formed using a semiconductor process.

[0094] In one embodiment, the substrate (SUB) may be made of or include a flexible material that is bendable or foldable, and may have a single-layer structure or a multi-layer structure. In one embodiment, for example, the flexible material may include at least one of polystyrene, polyvinyl alcohol, polymethyl methacrylate, polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, triacetate cellulose, and cellulose acetate propionate. However, the embodiments are not limited thereto.

[0095] A pixel circuit layer (PCL) is disposed on a substrate (SUB). The pixel circuit layer (PCL) may include insulating layers and semiconductor electrodes and conductive electrodes disposed between the insulating layers. The conductive electrodes of the pixel circuit layer (PCL) may function as circuit elements, wirings, etc.

[0096] The circuit elements of the pixel circuit layer (PCL) may include a sub-pixel circuit (SPC, see FIG. 2) of each of the sub-pixels (SP) of FIG. 3. In other words, the circuit elements of the pixel circuit layer (PCL) may be provided as transistors and one or more capacitors of the sub-pixel circuit (SPC).

[0097] The wiring of the pixel circuit layer (PCL) may include wiring connected to sub-pixels (SP). The wiring of the pixel circuit layer (PCL) may include various signal lines and / or voltage lines necessary to drive the display element layer (DPL).

[0098] A display element layer (DPL) is arranged on a pixel circuit layer (PCL). The display element layer (DPL) may include light-emitting elements of sub-pixels (SP).

[0099] A light-functional layer (LFL) may be disposed on a display element layer (DPL). The light-functional layer (LFL) may include light-converting patterns having color-converting particles and / or scattering particles. In one embodiment, for example, the color-converting particles may include quantum dots. The quantum dots may change the wavelength (or color) of light emitted from the display element layer (DPL). The light-functional layer (LFL) may further include light-scattering patterns having scattering particles. In one embodiment, the light-converting patterns and the light-scattering patterns may be omitted.

[0100] The light function layer (LFL) may further include a color filter layer comprising color filters. The color filter may selectively transmit light of a specific wavelength (or color). In one embodiment, the color filter layer may be omitted.

[0101] A window may be provided on a light-functional layer (LFL) to protect an exposed surface (or upper surface) of a display panel (DP). The window may protect the display panel (DP) from external impact. The window may be bonded to the light-functional layer (LFL) via an optically transparent adhesive (or bonding) member. The window may have a multilayer structure selected from a glass substrate, a plastic film, and a plastic substrate. This multilayer structure may be formed through a continuous process or an bonding process using an adhesive layer. All or a portion of the window may be flexible.

[0102] FIG. 5 is a cross-sectional view showing another embodiment of the display panel of FIG. 3.

[0103] Referring to FIG. 5, an embodiment of a display panel (DP') may include a substrate (SUB), a pixel circuit layer (PCL), a display element layer (DPL), an input sensing layer (SSL), and a light function layer (LFL). The substrate (SUB), the pixel circuit layer (PCL), the display element layer (DPL), and the light function layer (LFL) may be substantially the same as the substrate (SUB), the pixel circuit layer (PCL), the display element layer (DPL), and the light function layer (LFL) described above with reference to FIG. 4, and a repetitive detailed description thereof may be omitted.

[0104] In one embodiment, the input sensing layer (SSL) can detect user input on the upper surface (or display surface) of the display panel (DP'). The input sensing layer (SSL) can include configurations suitable for detecting external objects, such as a user's hand, a pen, etc. In one embodiment, for example, the input sensing layer (SSL) can include touch electrodes.

[0105] Fig. 6 is a plan view showing an enlarged portion of a display area of ​​the display panel of Fig. 3.

[0106] Referring to Fig. 6, an embodiment of a display panel (DP) includes sub-pixels (SP) in a display area (DA). In one embodiment, the sub-pixels (SP) are arranged in a pentile shape in a zigzag shape along a fourth direction (DR4) between the first direction (DR1) and the second direction (DR2) and a fifth direction (DR5) orthogonal to the fourth direction (DR4). TM ) can be arranged in a structure.

[0107] The sub-pixels (SP) may include first to fourth sub-pixels (SP1, SP2, SP3, SP4). The first to fourth sub-pixels (SP1, SP2, SP3, SP4) may be arranged in the first to fourth sub-pixel areas (SPA1, SPA2, SPA3, SPA4), respectively.

[0108] Light-emitting elements (LD) may be arranged in each of the first to fourth sub-pixel areas (SPA1, SPA2, SPA3, and SPA4). Specifically, a third light-emitting element (LD3) may be arranged in the first sub-pixel area (SPA1), a first-first light-emitting element (LD1-1) may be arranged in the second sub-pixel area (SPA2), a second light-emitting element (LD2) may be arranged in the third sub-pixel area (SPA3), and a first-second light-emitting element (LD1-2) may be arranged in the fourth sub-pixel area (SPA4). Each of the first-first light-emitting element (LD1-1) and the first-second light-emitting element (LD1-2) may generate green light, the second light-emitting element (LD2) may generate blue light, and the third light-emitting element (LD3) may generate red light. However, the present invention is not limited thereto.

[0109] In one embodiment, the first to third light-emitting elements (LD1, LD2, LD3) may be spaced apart from each other when viewed in a plane or in a third direction (DR3). That is, the first to third light-emitting elements (LD1, LD2, LD3) may not overlap each other in the third direction (DR3).

[0110] In one embodiment, conductive patterns (CDP) may be arranged between the first to third light-emitting elements (LD1, LD2, LD3). The conductive patterns (CDP) may be arranged between the first to third light-emitting elements (LD1, LD2, LD3) on a plane without overlapping with the first to third light-emitting elements (LD1, LD2, LD3). In one embodiment, the conductive patterns (CDP) may surround the first to fourth sub-pixel areas (SPA1, SPA2, SPA3, SPA4) on a plane without overlapping with the first to fourth sub-pixel areas (SPA1, SPA2, SPA3, SPA4). That is, the conductive patterns (CDP) may be arranged between adjacent sub-pixel areas among the first to fourth sub-pixel areas (SPA1, SPA2, SPA3, SPA4).

[0111] The conductive patterns (CDP) may have a mesh structure. The conductive patterns (CDP) extend in the fourth direction (DR4) or the fifth direction (DR5) and may intersect each other. The conductive patterns (CDP) may be arranged throughout the display panel (DP) of FIG. 3 to transmit various signals including voltages.

[0112] Lenses (LS) may be respectively arranged on the first to third light-emitting elements (LD1, LD2, LD3). Each of the lenses (LS) can focus the light generated by each of the light-emitting elements (LD) to improve the straightness of the light and thereby improve brightness.

[0113] Fig. 7 is a cross-sectional view taken along line I-I' of Fig. 6. In particular, Fig. 7 is a cross-sectional view showing only a pixel circuit layer (PCL) and a display element layer (DPL) of a display panel (DP) corresponding to one pixel (PXL).

[0114] Referring to FIG. 7, in one embodiment, the pixel circuit layer (PCL) may include pixel circuits (PCC) corresponding to the sub-pixel circuit (SPC) of FIG. 2, and bonding electrodes (BDE).

[0115] In the display area (DA), pixel circuits (PCC) can be respectively arranged in the first to fourth sub-pixel areas (SPA1, SPA2, SPA3, SPA4) and can be spaced apart from each other. Bonding electrodes (BDE) can electrically connect the pixel circuits (PCC) and the display element layer (DPL), respectively. That is, since the pixel circuits (PCC) spaced apart from each other in the display area (DA) are insulated from each other, different voltages can be respectively transmitted to the display element layer (DPL) through the bonding electrodes (BDE).

[0116] A display element layer (DPL) may be arranged on a pixel circuit layer (PCL). The display element layer (DPL) may include a first light-emitting element layer (LDL1), a first conductive layer (CDL1), a second light-emitting element layer (LDL2), a second conductive layer (CDL2), a third light-emitting element layer (LDL3), a third conductive layer (CDL3), an insulating layer (ISL), and a lens layer (LSL). In addition, the conductive patterns (CDP) of FIG. 6 may include first conductive patterns (CDP1), second conductive patterns (CDP2), and third conductive patterns (CDP3).

[0117] A first light-emitting element layer (LDL1) may be disposed on a pixel circuit layer (PCL). The first light-emitting element layer (LDL1) may be connected to pixel circuits (PCC) via bonding electrodes (BDE) on the bonding electrodes (BDE).

[0118] The first light-emitting element layer (LDL1) may include first bonding patterns (BDP1), first reflective patterns (RFP1), at least one first light-emitting element (LD1), first conductive patterns (CDP1), a first-first connection pattern (CNP1-1), and a second-first connection pattern (CNP2-1).

[0119] Each of the first bonding patterns (BDP1) may be connected to a corresponding one of the bonding electrodes (BDE), the first light-emitting element (LD1), the first-first connection pattern (CNP1-1), and the second-first connection pattern (CNP2-1). The first bonding patterns (BDP1) may be arranged in the first to fourth sub-pixel areas (SPA1, SPA2, SPA3, SPA4), respectively. Each of the first bonding patterns (BDP1) may have a double-layer structure including titanium.

[0120] First reflective patterns (RFP1) may be respectively arranged on the first bonding patterns (BDP1). The first reflective patterns (RFP1) may each overlap the first bonding patterns (BDP1). The first reflective patterns (RFP1) may be made of or include a metal having a higher reflectivity than the first bonding patterns (BDP1). In one embodiment, for example, each of the first reflective patterns (RFP1) may include aluminum.

[0121] The first light-emitting element layer (LDL1) may include at least one first light-emitting element (LD1). Hereinafter, the structure of the first light-emitting element (LD1) will be described.

[0122] Fig. 8 is an enlarged cross-sectional view of the first light-emitting element of Fig. 7.

[0123] Referring to FIG. 8, an embodiment of a first light-emitting element (LD1) may include a first semiconductor layer (21), an active layer (22), a second semiconductor layer (23), and an auxiliary layer (25). The first light-emitting element (LD1) may be implemented as a vertical light-emitting laminate in which the second semiconductor layer (23), the active layer (22), the first semiconductor layer (21), and the auxiliary layer (25) are sequentially laminated along a third direction (DR3).

[0124] The first semiconductor layer (21) can provide electrons. The first semiconductor layer (21) may include, for example, at least one N-type semiconductor layer. In one embodiment, for example, the first semiconductor layer (21) may include at least one semiconductor material selected from gallium nitride (GaN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), aluminum nitride (AlN), and indium nitride (InN), and may be an N-type semiconductor layer doped with a first conductive dopant (or N-type dopant) such as silicon (Si), germanium (Ge), or tin (Sn). However, the material constituting the first semiconductor layer (21) is not limited thereto, and various other materials may constitute the first semiconductor layer (21). In one embodiment of the present invention, the first semiconductor layer (21) may include a gallium nitride (GaN) semiconductor material doped with a first conductive dopant (or N-type dopant). According to an embodiment, the first semiconductor layer (21) may form an N-type semiconductor layer together with the auxiliary layer (25).

[0125] The active layer (22) is disposed on the first semiconductor layer (21) and may be a region where electrons and holes recombine. As electrons and holes recombine in the active layer (22), they transition to a lower energy level, and light having a corresponding wavelength may be generated. The active layer (22) may be formed in a single or multiple quantum well structure. In an embodiment in which the active layer (22) is formed in a multiple quantum well structure, units including a barrier layer, a strain reinforcing layer, and a well layer may be repeatedly stacked to form the active layer (22). However, embodiments of the active layer (22) are not limited thereto.

[0126] The second semiconductor layer (23) is disposed on the active layer (22) and provides holes to the active layer (22). The second semiconductor layer (23) may include a semiconductor layer of a different type from the first semiconductor layer (21). In one embodiment, for example, the second semiconductor layer (23) may include at least one P-type semiconductor layer. In one embodiment, for example, the second semiconductor layer (23) may include at least one semiconductor material selected from gallium nitride (GaN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), aluminum nitride (AlN), and indium nitride (InN), and may be a P-type semiconductor layer doped with a second conductive dopant (or P-type dopant) such as magnesium (Mg), zinc (Zn), calcium (Ca), strontium (Sr), barium (Ba), or the like. However, the material constituting the second semiconductor layer (23) is not limited to this, and various other materials may also constitute the second semiconductor layer (23). In one embodiment of the present invention, the second semiconductor layer (23) may include a gallium nitride (GaN) semiconductor material doped with a second conductive dopant (or P-type dopant).

[0127] The bonding electrode (BDE) of Fig. 7 may be electrically connected to the second semiconductor layer (23). The bonding electrode (BDE) may include a eutectic metal.

[0128] The auxiliary layer (25) may include a gallium nitride (GaN) semiconductor material that is not doped with impurities, and may form an N-type semiconductor layer together with the first semiconductor layer (21).

[0129] The first light-emitting element (LD1) may further include an insulating film (26) covering the outer surface of the vertical light-emitting stack. The insulating film (26) can effectively prevent an electrical short circuit that may occur when the active layer (22) comes into contact with a conductive material other than the first and second semiconductor layers (21, 23). The insulating film (26) may include a transparent insulating material. In addition, the insulating film (26) is configured to expose the upper surface of the auxiliary layer (25) that will come into contact with the first conductive layer (CDL1).

[0130] The second light-emitting element (LD2) and the third light-emitting element (LD3) also have substantially the same structure as the first light-emitting element (LD1).

[0131] However, the present invention is not limited thereto, and in another embodiment, the first light-emitting element (LD1) may have a structure in which the structure of FIG. 8 is opposite in the third direction (DR3) (for example, a structure in which the first semiconductor layer (21) is disposed at the bottom and the second semiconductor layer (23) is disposed at the top).

[0132] Referring again to FIG. 7, the first light-emitting element layer (LDL1) may include a first-first light-emitting element (LD1-1) and a first-second light-emitting element (LD1-2).

[0133] The first-first light-emitting element (LD1-1) and the first-second light-emitting element (LD1-2) may be disposed on corresponding first reflective patterns (RFP1) among the first reflective patterns (RFP1). The first-first light-emitting element (LD1-1) may be disposed on the first reflective pattern (RFP1) overlapping the second sub-pixel area (SPA2), and the first-second light-emitting element (LD1-2) may be disposed on the first reflective pattern (RFP1) overlapping the fourth sub-pixel area (SPA4). However, the present invention is not limited thereto.

[0134] The first reflective pattern (RFP1) disposed below each of the first light-emitting element (LD1-1) and the first light-emitting element (LD1-2) can reflect light generated by the first light-emitting element (LD1-1) and the first light-emitting element (LD1-2) to emit the light to the display surface of the display panel (DP).

[0135] The first light-emitting element (LD1-1) and the first light-emitting element (LD1-2) can generate light of the same color. In one embodiment, for example, the first light-emitting element (LD1-1) and the first light-emitting element (LD1-2) can generate green color light. Since the first light-emitting element layer (LDL1) is disposed at the bottommost with respect to the upper surface of the display panel (DP), the first light-emitting element (LD1) that generates green color light with the highest brightness can be disposed in the first light-emitting element layer (LDL1). In addition, since the first light-emitting element layer (LDL1) is disposed at the bottommost with respect to the upper surface of the display panel (DP), two first light-emitting elements (LD1-1, LD1-2) can be disposed in the first light-emitting element layer (LDL1) corresponding to one pixel (PXL). However, the present invention is not limited thereto.

[0136] The bonding electrodes (BDE) overlapping the first-first light-emitting element (LD1-1) and the first-second light-emitting element (LD1-2) respectively can receive the first power voltage (VDDN) from the pads (PD) of FIG. 3 and supply the first power voltage (VDDN) to the P-type semiconductor layer side of the first light-emitting element (LD1).

[0137] The first conductive patterns (CDP1) may be arranged on the pixel circuit layer (PCL). The first conductive patterns (CDP1) may be spaced apart from the first light-emitting element (LD1) on a plane. In addition, the first conductive patterns (CDP1) may be spaced apart from the first bonding patterns (BDP1) and the first reflective patterns (RFP1) on a plane. The first conductive patterns (CDP1) may be arranged between two adjacent sub-pixel areas among the first to fourth sub-pixel areas (SPA1, SPA2, SPA3, SPA4). That is, the first conductive patterns (CDP1) may surround the first light-emitting element (LD1) on a plane. The first challenge patterns (CDP1) can overlap the first bonding patterns (BDP1), the first reflective patterns (RFP1), the first-first light-emitting element (LD1-1), and the first-second light-emitting element (LD1-2) in a horizontal direction orthogonal to the third direction (DR3).

[0138] Each of the first conductive patterns (CDP1) may include a connection electrode (CNE) and a reflective electrode (RFE). The connection electrode (CNE) may connect different electrodes, patterns, and layers to each other to transmit various signals including voltages. The connection electrode (CNE) may be made of or include a conductive metal. In one embodiment, for example, the connection electrode (CNE) may include at least one selected from copper and tungsten.

[0139] The reflective electrode (RFE) can cover at least a portion of the connection electrode (CNE). In one embodiment, for example, the reflective electrode (RFE) can cover a side surface of the connection electrode (CNE). In another example, the reflective electrode (RFE) can cover a side surface and a bottom surface of the connection electrode (CNE). Accordingly, the reflective electrode (RFE) can have a structure that surrounds the first light-emitting element (LD1). Accordingly, the reflective electrode (RFE) can improve light emission efficiency by reflecting light generated by the first light-emitting element (LD1) from the side surface.

[0140] The reflective electrode (RFE) may be made of or include a metal having a higher reflectivity than the connecting electrode (CNE). In one embodiment, for example, the reflective electrode (RFE) may include at least one of aluminum and silver.

[0141] A first-first connection pattern (CNP1-1) and a second-first connection pattern (CNP2-1) may be respectively arranged on the first reflective patterns (RFP1) on which the first light-emitting element (LD1) is not arranged. The first-first connection pattern (CNP1-1) may overlap (or be arranged) with the third sub-pixel area (SPA3), and the second-first connection pattern (CNP2-1) may overlap with the first sub-pixel area (SPA1). That is, the first-first connection pattern (CNP1-1) may be connected to the first bonding pattern (BDP1) and the first reflective pattern (RFP1) in the third sub-pixel area (SPA3), and the second-first connection pattern (CNP2-1) may be connected to the first bonding pattern (BDP1) and the first reflective pattern (RFP1) in the first sub-pixel area (SPA1). The first-first connection pattern (CNP1-1) and the second-first connection pattern (CNP2-1) can overlap the first conductive patterns (CDP1) in the horizontal direction orthogonal to the third direction (DR3).

[0142] Each of the first-first connection pattern (CNP1-1) and the second-first connection pattern (CNP2-1) may be made of or include the same material as the connection electrode (CNE). In one embodiment, for example, each of the first-first connection pattern (CNP1-1) and the second-first connection pattern (CNP2-1) may include at least one selected from copper and tungsten. However, the present invention is not limited thereto.

[0143] In addition, each of the first-first connection pattern (CNP1-1) and the second-first connection pattern (CNP2-1) may further include the same material as the reflective electrode (RFE) on at least one side. In one embodiment, for example, each of the first-first connection pattern (CNP1-1) and the second-first connection pattern (CNP2-1) may have the same structure as each of the first conductive patterns (CDP1). However, the present invention is not limited thereto, and in one embodiment, for example, the same material as the reflective electrode (RFE) disposed on the side of each of the first-first connection pattern (CNP1-1) and the second-first connection pattern (CNP2-1) may be omitted.

[0144] A first conductive layer (CDL1) may be disposed on a first light-emitting element layer (LDL1). The first conductive layer (CDL1) may be in contact with and connected to the first-first light-emitting element (LD1-1), the first-second light-emitting element (LD1-2), the first conductive patterns (CDP1), the first-first connection pattern (CNP1-1), and the second-first connection pattern (CNP2-1).

[0145] The first conductive layer (CDL1) may be made of or include a conductive material. In one embodiment, for example, the first conductive layer (CDL1) may include indium tin oxide (ITO).

[0146] The first conductive layer (CDL1) may include a first bridge pattern (BRP1) and may have a first opening (OP1) defined around the first bridge pattern (BRP1). The first opening (OP1) may have a ring shape surrounding the first bridge pattern (BRP1) on a plane. That is, the first bridge pattern (BRP1) may not be connected to other parts of the first conductive layer (CDL1) due to the first opening (OP1) and may be insulated from each other.

[0147] The first bridge pattern (BRP1) may overlap with the third sub-pixel area (SPA3) and the second light-emitting element (LD2). The first bridge pattern (BRP1) may be in contact with and connected to the first-first connection pattern (CNP1-1). The first bridge pattern (BRP1) may cover the entire upper surface of the first-first connection pattern (CNP1-1). That is, the area of ​​the first bridge pattern (BRP1) may be greater than or equal to the area of ​​the upper surface of the first-first connection pattern (CNP1-1). In one embodiment, since the first bridge pattern (BRP1) entirely covers the upper surface of the first-first connection pattern (CNP1-1), the first-first connection pattern (CNP1-1) is not exposed, so that corrosion of the first-first connection pattern (CNP1-1) is effectively prevented and a contact margin for a connection process with the first-second connection pattern (CNP1-2) described later can be secured.

[0148] In one embodiment, the first bridge pattern (BRP1) may be connected to the second light-emitting element (LD2). The second light-emitting element (LD2) is connected to the pixel circuit layer (PCL) through the first bridge pattern (BRP1) and the first-first connection pattern (CNP1-1), and may receive a signal from the pixel circuit (PCC).

[0149] The first conductive layer (CDL1) may include a second bridge pattern (BRP2) spaced apart from the first bridge pattern (BRP1) and may have a second opening (OP2) defined around the second bridge pattern (BRP2). The second opening (OP2) may have a ring shape surrounding the second bridge pattern (BRP2) on a plane. That is, the second bridge pattern (BRP2) may not be connected to other parts of the first conductive layer (CDL1) due to the second opening (OP2) and may be insulated from each other.

[0150] The second bridge pattern (BRP2) may overlap the first sub-pixel area (SPA1) and the third light-emitting element (LD3). The second bridge pattern (BRP2) may be in contact with and connected to the second-first connection pattern (CNP2-1). The second bridge pattern (BRP2) may cover the entire upper surface of the second-first connection pattern (CNP2-1). That is, the area of ​​the second bridge pattern (BRP2) may be greater than or equal to the area of ​​the upper surface of the second-first connection pattern (CNP2-1).

[0151] In one embodiment, the second bridge pattern (BRP2) may be electrically connected to the third light-emitting element (LD3). The third light-emitting element (LD3) is connected to the pixel circuit layer (PCL) through the second bridge pattern (BRP2) and the second-first connection pattern (CNP2-1), and may receive a signal from the pixel circuit (PCC).

[0152] The first conductive layer (CDL1) excluding the first bridge pattern (BRP1) and the second bridge pattern (BRP2) can be in contact with the first light-emitting element (LD1) and the first conductive patterns (CDP1). The first conductive layer (CDL1) excluding the first bridge pattern (BRP1) and the second bridge pattern (BRP2) can connect the first light-emitting element (LD1) and the first conductive patterns (CDP1) to each other and transmit a signal. The first conductive layer (CDL1) can be in contact with the first light-emitting element (LD1) through the first contact hole (CNT1). In one embodiment, the first conductive layer (CDL1) can receive a second power voltage (VSSN) from the common electrode (CME) of FIG. 3 and supply the second power voltage (VSSN) to the N-type semiconductor layer side of the first light-emitting element (LD1). Additionally, the first conductive layer (CDL1) can electrically connect the first light-emitting element layer (LDL1) and the second light-emitting element layer (LDL2) to each other through conductive patterns (CDP).

[0153] A second light-emitting element layer (LDL2) may be disposed on a first conductive layer (CDL1). The second light-emitting element layer (LDL2) may include a second bonding pattern (BDP2), a second reflective pattern (RFP2), a second light-emitting element (LD2), second conductive patterns (CDP2), a first-second connection pattern (CNP1-2), and a second-second connection pattern (CNP2-2).

[0154] The second bonding pattern (BDP2) may be connected to the first bridge pattern (BRP1), the second light-emitting element (LD2), and the first-second connection pattern (CNP1-2). The second bonding pattern (BDP2) may be arranged in the third sub-pixel area (SPA3). The second bonding pattern (BDP2) may have a double-layer structure including titanium.

[0155] A second reflective pattern (RFP2) may be arranged on the second bonding pattern (BDP2). The second reflective pattern (RFP2) may be made of or include a metal having a higher reflectivity than the second bonding pattern (BDP2). In one embodiment, for example, the second reflective pattern (RFP2) may include aluminum.

[0156] The second light-emitting element layer (LDL2) may include at least one second light-emitting element (LD2). In one embodiment, for example, the second light-emitting element layer (LDL2) corresponding to one pixel (PXL) may include one second light-emitting element (LD2).

[0157] The second light-emitting element (LD2) may overlap with the third sub-pixel area (SPA3) (or may be disposed in the third sub-pixel area (SPA3)). That is, the second light-emitting element (LD2) may be disposed at a position spaced apart from the first-first light-emitting element (LD1-1) and the first-second light-emitting element (LD1-2) on a plane. Since the second light-emitting element (LD2) does not overlap with the first light-emitting element (LD1), the light output efficiency may be further improved.

[0158] The second light-emitting element (LD2) may be disposed on the second reflective pattern (RFP2). The second light-emitting element (LD2) may be disposed on the second reflective pattern (RFP2) overlapping the third sub-pixel area (SPA3).

[0159] The second light-emitting element (LD2) can generate light of a different color than the color of light generated by the first light-emitting element (LD1). In one embodiment, for example, the second light-emitting element (LD2) can generate blue light.

[0160] The second conductive patterns (CDP2) may be arranged on the pixel circuit layer (PCL). The second conductive patterns (CDP2) may be spaced apart from the second light-emitting element (LD2) on a plane. In addition, the second conductive patterns (CDP2) may also be spaced apart from the second bonding pattern (BDP2) and the second reflective pattern (RFP2) that overlap with the second light-emitting element (LD2) on a plane.

[0161] The second conductive patterns (CDP2) may be arranged between two adjacent sub-pixel areas among the first to fourth sub-pixel areas (SPA1, SPA2, SPA3, SPA4). That is, the second conductive patterns (CDP2) may surround the second light-emitting element (LD2). The second conductive patterns (CDP2) may overlap the first conductive patterns (CDP1), respectively. In addition, the second conductive patterns (CDP2) may be in contact with the first conductive layer (CDL1) and may be electrically connected to the first conductive patterns (CDP1) through the first conductive layer (CDL1).

[0162] The second challenge patterns (CDP2) can overlap the second bonding pattern (BDP2), the second reflective pattern (RFP2), and the second light-emitting element (LD2) in the horizontal direction orthogonal to the third direction (DR3).

[0163] Each of the second conductive patterns (CDP2) may include a connection electrode (CNE) and a reflective electrode (RFE). That is, the second conductive patterns (CDP2) may have the same structure as the first conductive patterns (CDP1). Accordingly, the second conductive patterns (CDP2) may reflect the light generated by the second light-emitting element (LD2) from the side, thereby improving light emission efficiency.

[0164] The first-second connection pattern (CNP1-2) and the second-second connection pattern (CNP2-2) may be disposed on the first-first connection pattern (CNP1-1) and the second-first connection pattern (CNP2-1), respectively. The first-second connection pattern (CNP1-2) and the second-second connection pattern (CNP2-2) overlap with the first-first connection pattern (CNP1-1) and the second-first connection pattern (CNP2-1), respectively, and may be connected to the first-first connection pattern (CNP1-1) and the second-first connection pattern (CNP2-1), respectively. The first-second connection pattern (CNP1-2) may be in contact with the first bridge pattern (BRP1) in the third sub-pixel area (SPA3), and may be connected to the first-first connection pattern (CNP1-1) and the second light-emitting element (LD2). The second-second connection pattern (CNP2-2) can be connected to the second bridge pattern (BRP2) and the second-first connection pattern (CNP2-1) in the first sub-pixel area (SPA1).

[0165] The first-second connection pattern (CNP1-2) and the second-second connection pattern (CNP2-2) may be made of or include the same material as the first-first connection pattern (CNP1-1) and the second-first connection pattern (CNP2-1). In one embodiment, for example, each of the first-second connection pattern (CNP1-2) and the second-second connection pattern (CNP2-2) may include at least one selected from copper and tungsten. However, the present invention is not limited thereto.

[0166] In one embodiment, each of the first-second connection pattern (CNP1-2) and the second-second connection pattern (CNP2-2) may further include the same material as the reflective electrode (RFE) on at least one side. In one embodiment, for example, each of the first-second connection pattern (CNP1-2) and the second-second connection pattern (CNP2-2) may have the same structure as each of the second conductive patterns (CDP2). However, the present invention is not limited thereto, and in one embodiment, for example, the same material as the reflective electrode (RFE) disposed on the side of each of the first-second connection pattern (CNP1-2) and the second-second connection pattern (CNP2-2) may be omitted.

[0167] The first-first connection pattern (CNP1-1) and the first-second connection pattern (CNP1-2) may include the same material and may be connected to each other through a first conductive layer (CDL1), for example, a first bridge pattern (BRP1). The first-first connection pattern (CNP1-1) and the first-second connection pattern (CNP1-2) may constitute (or collectively define) one first connection pattern (CNP1). The first connection pattern (CNP1) may overlap the second light-emitting element (LD2) and connect the pixel circuit layer (PCL) and the second light-emitting element (LD2) to each other. That is, the first connection pattern (CNP1) may transmit a signal transmitted from the pixel circuit (PCC) to the second light-emitting element (LD2). In one embodiment, the first connection pattern (CNP1) in contact with the second light-emitting element (LD2) can receive the first power voltage (VDDN) from the pads (PD) and the pixel circuit layer (PCL) of FIG. 3 and supply the first power voltage (VDDN) to the P-type semiconductor layer side of the first light-emitting element (LD1).

[0168] A second conductive layer (CDL2) may be disposed on a second light-emitting element layer (LDL2). The second conductive layer (CDL2) may be in contact with and connected to the second light-emitting element (LD2), the second conductive patterns (CDP2), and the second-second connection pattern (CNP2-2).

[0169] The second conductive layer (CDL2) may be made of or include a conductive material. In one embodiment, for example, the second conductive layer (CDL2) may include indium tin oxide (ITO).

[0170] The second conductive layer (CDL2) may include a third bridge pattern (BRP3) and may have a third opening (OP3) defined around the third bridge pattern (BRP3). The third opening (OP3) may have a ring shape surrounding the third bridge pattern (BRP3) on a plane. That is, the third bridge pattern (BRP3) may not be connected to other parts of the third conductive layer (CDL3) due to the third opening (OP3), but may be insulated from each other.

[0171] The third bridge pattern (BRP3) may overlap the first sub-pixel area (SPA1) and the third light-emitting element (LD3). The third bridge pattern (BRP3) may be in contact with and connected to the second-second connection pattern (CNP2-2). The third bridge pattern (BRP3) may cover the entire upper surface of the second-second connection pattern (CNP2-2). That is, the area of ​​the third bridge pattern (BRP3) may be greater than or equal to the area of ​​the upper surface of the second-second connection pattern (CNP2-2).

[0172] In one embodiment, the third bridge pattern (BRP3) may be interconnected with the third light-emitting element (LD3). The third light-emitting element (LD3) may be connected to the pixel circuit layer (PCL) through the third bridge pattern (BRP3), the second-first connection pattern (CNP2-1), and the second-second connection pattern (CNP2-2), and may receive a signal from the pixel circuit (PCC).

[0173] The second conductive layer (CDL2) excluding the third bridge pattern (BRP3) can be in contact with the second light-emitting element (LD2) and the second conductive patterns (CDP2). The second conductive layer (CDL2) excluding the third bridge pattern (BRP3) can connect the second light-emitting element (LD2) and the second conductive patterns (CDP2) to each other and transmit a signal. The second conductive layer (CDL2) can be in contact with the second light-emitting element (LD2) through the second contact hole (CNT2). In one embodiment, the second conductive layer (CDL2) can receive the second power voltage (VSSN) from the common electrode (CME) of FIG. 3 and supply it to the N-type semiconductor layer side of the second light-emitting element (LD2). In addition, the second conductive layer (CDL2) can electrically connect the second light-emitting element layer (LDL2) and the third light-emitting element layer (LDL3) to each other through the conductive patterns (CDP).

[0174] A third light-emitting element layer (LDL3) may be disposed on a second conductive layer (CDL2). The third light-emitting element layer (LDL3) may include a third bonding pattern (BDP3), a third reflective pattern (RFP3), a third light-emitting element (LD3), third conductive patterns (CDP3), and a second-third connection pattern (CNP2-3).

[0175] The third bonding pattern (BDP3) may be connected to the third bridge pattern (BRP3), the third light-emitting element (LD3), and the second-second connection pattern (CNP2-2). The third bonding pattern (BDP3) may be arranged in the first sub-pixel area (SPA1). The third bonding pattern (BDP3) may have a double-layer structure including titanium.

[0176] A third reflective pattern (RFP3) may be arranged on the third bonding pattern (BDP3). The third reflective pattern (RFP3) may be made of or include a metal having a higher reflectivity than the third bonding pattern (BDP3). In one embodiment, for example, the third reflective pattern (RFP3) may include aluminum.

[0177] The third light-emitting element layer (LDL3) may include at least one third light-emitting element (LD3). In one embodiment, for example, the third light-emitting element layer (LDL3) may include one third light-emitting element (LD3).

[0178] The third light-emitting element (LD3) may overlap with the first sub-pixel area (SPA1). That is, the third light-emitting element (LD3) may be positioned at a position spaced apart from all of the first-first light-emitting element (LD1-1), the first-second light-emitting element (LD1-2), and the second light-emitting element (LD2) on a plane. Since the third light-emitting element (LD3) does not overlap with the first light-emitting element (LD1) and the second light-emitting element (LD2), the light output efficiency may be further improved.

[0179] The third light-emitting element (LD3) may be disposed on the third reflective pattern (RFP3). The third light-emitting element (LD3) may be disposed on the third reflective pattern (RFP3) overlapping the first sub-pixel area (SPA1).

[0180] The third light-emitting element (LD3) can generate light of a different color from the colors of light generated by the first light-emitting element (LD1) and the second light-emitting element (LD2). In one embodiment, for example, the third light-emitting element (LD3) can generate red light.

[0181] The third conductive patterns (CDP3) may be arranged on the pixel circuit layer (PCL). The third conductive patterns (CDP3) may be spaced apart from the third light-emitting element (LD3) on a plane. In addition, the third conductive patterns (CDP3) may also be spaced apart from the third bonding pattern (BDP3) and the third reflective pattern (RFP3) that overlap with the third light-emitting element (LD3) on a plane.

[0182] The third conductive patterns (CDP3) may be arranged between two adjacent sub-pixel areas among the first to fourth sub-pixel areas (SPA1, SPA2, SPA3, SPA4). That is, the third conductive patterns (CDP3) may surround the third light-emitting element (LD3) on a plane. The third conductive patterns (CDP3) may overlap the second conductive patterns (CDP2), respectively. In addition, the third conductive patterns (CDP3) may be in contact with the second conductive layer (CDL2) and may be electrically connected to the second conductive patterns (CDP2) through the second conductive layer (CDL2).

[0183] The third challenge patterns (CDP3) can overlap with the third bonding pattern (BDP3), the third reflective pattern (RFP3), and the third light-emitting element (LD3) in the horizontal direction orthogonal to the third direction (DR3).

[0184] Each of the third conductive patterns (CDP3) may include a connection electrode (CNE) and a reflective electrode (RFE). That is, the third conductive patterns (CDP3) may have the same structure as the first conductive patterns (CDP1). Accordingly, the third conductive patterns (CDP3) may reflect the light generated by the third light-emitting element (LD3) from the side, thereby improving light emission efficiency.

[0185] The second-third connection pattern (CNP2-3) may be arranged on the second-second connection pattern (CNP2-2). The second-third connection pattern (CNP2-3) may overlap with the second-first connection pattern (CNP2-1) and the second-second connection pattern (CNP2-2) and be connected to each other. The second-third connection pattern (CNP2-3) may be in contact with the third bridge pattern (BRP3) in the first sub-pixel area (SPA1) and may be connected to the second-second connection pattern (CNP2-2) and the third light-emitting element (LD3).

[0186] The second-third connection pattern (CNP2-3) may be made of or include the same material as the second-second connection pattern (CNP2-2). In one embodiment, for example, the second-third connection pattern (CNP2-3) may include at least one selected from copper and tungsten. However, the present invention is not limited thereto.

[0187] In one embodiment, the second-third connection pattern (CNP2-3) may further include the same material as the reflective electrode (RFE) on at least one side. In one embodiment, for example, the second-third connection pattern (CNP2-3) may have the same structure as each of the third conductive patterns (CDP3). However, the present invention is not limited thereto, and the same material as the reflective electrode (RFE) disposed on the side of the second-third connection pattern (CNP2-3) may be omitted.

[0188] The second-second connection pattern (CNP2-2) and the second-third connection pattern (CNP2-3) may include the same material and may be connected to each other through a second conductive layer (CDL2), for example, a third bridge pattern (BRP3). Similarly, the second-first connection pattern (CNP2-1) and the second-second connection pattern (CNP2-2) may include the same material and may be connected to each other through a first conductive layer (CDL1), for example, a second bridge pattern (BRP2). The second-first connection pattern (CNP2-1), the second-second connection pattern (CNP2-2), and the second-third connection pattern (CNP2-3) may constitute one second connection pattern (CNP2). The second connection pattern (CNP2) may overlap the third light-emitting element (LD3) and may connect the pixel circuit layer (PCL) and the third light-emitting element (LD3) to each other. That is, the second connection pattern (CNP2) can transmit a signal transmitted from the pixel circuit (PCC) to the third light-emitting element (LD3). In one embodiment, the second connection pattern (CNP2) in contact with the third light-emitting element (LD3) can receive the first power voltage (VDDN) from the pads (PD) and the pixel circuit layer (PCL) of FIG. 3 and supply the first power voltage (VDDN) to the P-type semiconductor layer side of the first light-emitting element (LD1).

[0189] A third conductive layer (CDL3) may be disposed on a third light-emitting element layer (LDL3). The third conductive layer (CDL3) may be in contact with and connected to the third light-emitting element (LD3) and the third conductive patterns (CDP3).

[0190] The third conductive layer (CDL3) may be made of or include a conductive material. In one embodiment, for example, the third conductive layer (CDL3) may include indium tin oxide (ITO).

[0191] In one embodiment, the third conductive layer (CDL3) does not have an insulated bridge pattern and can extend entirely over the display panel (DP).

[0192] The third conductive layer (CDL3) can transmit a signal by connecting the third light-emitting element (LD3) and the third conductive patterns (CDP3) to each other. The third conductive layer (CDL3) can contact the third light-emitting element (LD3) exposed through the third contact hole (CNT3) defined in the insulating layer (ISL). Specifically, the third conductive layer (CDL3) can receive the second power voltage (VSSN) from the common electrode (CME) of FIG. 3 and supply it to the N-type semiconductor layer side of the third light-emitting element (LD3).

[0193] An insulating layer (ISL) may be disposed between the pixel circuit layer (PCL), the light-emitting elements of the first to third light-emitting element layers (LDL1, LDL2, LDL3), the electrodes, and the patterns, respectively. In one embodiment, for example, the insulating layer (ISL) may include an oxide.

[0194] An insulating layer (ISL) may be disposed on the third conductive layer (CDL3), and a lens layer (LSL) may be disposed on the insulating layer (ISL). The lens layer (LSL) may include micro lenses (LS) having light-gathering characteristics. In one embodiment, the lens layer (LSL) may include lenses (LS) that overlap the first to fourth sub-pixel areas (SPA1, SPA2, SPA3, SPA4), respectively. That is, the lenses (LS) may overlap the first-first light-emitting element (LD1-1), the first-second light-emitting element (LD1-2), the second light-emitting element (LD2), and the third light-emitting element (LD3), respectively.

[0195] Each of the lenses (LS) may be formed into a hemispherical shape. However, embodiments of the present invention are not limited thereto. In one embodiment, each of the lenses (LS) may focus light emitted from the first to third light-emitting element layers (LDL3) below, thereby improving the straightness of the light. Accordingly, the brightness of the display device may be improved.

[0196] Fig. 9 is a plan view showing an enlarged portion of a non-display area of ​​the display panel of Fig. 3. Fig. 10 is a cross-sectional view taken along line II-II' of Fig. 9.

[0197] Referring to FIGS. 9 and 10, the non-display area (NDA) of the display panel (DP) is configured substantially identically to the display area (DA) of the display panel (DP) of FIG. 6, except for the pixel circuits (PCC), the first bonding patterns (BDP1), the first reflective patterns (RFP1), and the lens layer (LSL). Therefore, repetitive detailed descriptions of elements identical or similar to those described above may be omitted or simplified.

[0198] A display panel (DP) may include sub-pixels (SP) arranged across the entire area including a display area (DA), a non-display area (NDA), and a pad area (PA). Since the sub-pixels (SP), each including light-emitting elements, are arranged across the entire area, the difference in pattern and electrode density between each area is minimized during the manufacturing process of the display panel (DP), so that the degree of planarization can be consistent across the entire area. As a result, uniform quality can be secured across the entire area of ​​the display device even in a subsequent process following the planarization process.

[0199] Accordingly, in this embodiment, the display panel (DP) may include sub-pixels (SP) even in the non-display area (NDA). The sub-pixels (SP) arranged in the non-display area (NDA) may be arranged in the same manner as the sub-pixels (SP) arranged in the display area (DA). However, the present invention is not limited thereto, and in other embodiments, the sub-pixels (SP) may be omitted in the non-display area (NDA).

[0200] In the non-display area (NDA), the pixel circuit (PCC) included in the pixel circuit layer (PCL) can be integrally formed within the non-display area (NDA). Therefore, the pixel circuit (PCC) disposed in the non-display area (NDA) can transmit the same voltage to the display element layer (DPL) through the bonding electrodes (BDE). In one embodiment, for example, the pixel circuit (PCC) disposed in the non-display area (NDA) can include the common electrode (CME) of FIG. 3. Therefore, the pixel circuit (PCC) disposed in the non-display area (NDA) can transmit the second power voltage (VSSN) to the first to third light-emitting element layers (LDL1, LDL2, LDL3) and the first to third conductive layers (CDL1, CDL2, CDL3).

[0201] In the non-display area (NDA), the first bonding pattern (BDP1) included in the display element layer (DPL) and the first reflective pattern (RFP1) on the first bonding pattern (BDP1) can be integrally formed within the non-display area (NDA). Therefore, the first bonding pattern (BDP1) arranged in the non-display area (NDA) is connected to the first-first light-emitting element (LD1-1), the first-second light-emitting element (LD1-2), the first conductive patterns (CDP1), the first connection pattern (CNP1), and the second connection pattern (CNP2), and can transmit the same voltage to all of the first-first light-emitting element (LD1-1), the first-second light-emitting element (LD1-2), the first conductive patterns (CDP1), the first connection pattern (CNP1), and the second connection pattern (CNP2).

[0202] Through this, the same voltage is transmitted in the direction of the N-type semiconductor layer and the P-type semiconductor layer to each of the first light-emitting element (LD1-1), the first light-emitting element (LD1-2), the second light-emitting element (LD2), and the third light-emitting element (LD3), so that the first light-emitting element (LD1-1), the first light-emitting element (LD1-2), the second light-emitting element (LD2), and the third light-emitting element (LD3) arranged in the non-display area (NDA) may not emit light.

[0203] In one embodiment, the first bonding pattern (BDP1) and the first reflective pattern (RFP1) can transmit the second power voltage (VSSN) transmitted from the pixel circuit (PCC) to the first-first light-emitting element (LD1-1), the first-second light-emitting element (LD1-2), the first conductive patterns (CDP1), the first connection pattern (CNP1), and the second connection pattern (CNP2).

[0204] The second power supply voltage (VSSN) can be transmitted from the first bonding pattern (BDP1) and the first reflective pattern (RFP1) to the P-type semiconductor layer side of each of the first-first light-emitting element (LD1-1) and the first-second light-emitting element (LD1-2). In addition, since the first bonding pattern (BDP1) and the first reflective pattern (RFP1) and the first conductive layer (CDL1) are connected to each other through the first conductive patterns (CDP1), the second power supply voltage (VSSN) can be transmitted from the first conductive layer (CDL1) to the N-type semiconductor layer side of each of the first-first light-emitting element (LD1-1) and the first-second light-emitting element (LD1-2). Accordingly, since the same voltage is applied to each of the N-type semiconductor layer and the P-type semiconductor layer of the first-first light-emitting element (LD1-1) and the first-second light-emitting element (LD1-2), the first-first light-emitting element (LD1-1) and the first-second light-emitting element (LD1-2) may not emit light.

[0205] In one embodiment, the first conductive layer (CDL1) extends to the display area (DA) and can transmit the second power voltage (VSSN) to the N-type semiconductor layer side of each of the first-first light-emitting element (LD1-1) and the first-second light-emitting element (LD1-2) of the display area (DA).

[0206] In this embodiment, since the first bonding pattern (BDP1) and the first reflective pattern (RFP1) are connected to the first connection pattern (CNP1), the second power voltage (VSSN) can be transmitted to the P-type semiconductor layer side of the second light-emitting element (LD2) through the first connection pattern (CNP1). In addition, since the first conductive layer (CDL1) and the second conductive layer (CDL2) are connected to each other through the second conductive patterns (CDP2), the second power voltage (VSSN) can be transmitted from the second conductive layer (CDL2) to the N-type semiconductor layer side of the second light-emitting element (LD2). Therefore, since the same voltage is applied to each of the N-type semiconductor layer and the P-type semiconductor layer of the second light-emitting element (LD2), the second light-emitting element (LD2) may not emit light.

[0207] In one embodiment, the second conductive layer (CDL2) extends to the display area (DA) and can transmit a second power voltage (VSSN) to the N-type semiconductor layer side of the second light-emitting element (LD2) in the display area (DA).

[0208] In this embodiment, since the first bonding pattern (BDP1) and the first reflective pattern (RFP1) are connected to the second connection pattern (CNP2), the second power voltage (VSSN) can be transmitted to the P-type semiconductor layer side of the third light-emitting element (LD3) through the second connection pattern (CNP2). In addition, since the second conductive layer (CDL2) and the third conductive layer (CDL3) are connected to each other through the third conductive patterns (CDP3), the second power voltage (VSSN) can be transmitted from the third conductive layer (CDL3) to the N-type semiconductor layer side of the third light-emitting element (LD3). Therefore, since the same voltage is applied to each of the N-type semiconductor layer and the P-type semiconductor layer of the third light-emitting element (LD3), the third light-emitting element (LD3) may not emit light.

[0209] In one embodiment, the third conductive layer (CDL3) extends to the display area (DA) and can transmit the second power voltage (VSSN) to the N-type semiconductor layer side of the third light-emitting element (LD3) in the display area (DA).

[0210] Accordingly, a structure can be configured in which light emitting elements (LDs) are placed in a non-display area (NDA) to ensure uniform quality during the process, but light is not emitted from the non-display area (NDA).

[0211] Fig. 11 is a plan view showing an enlarged portion of a pad area of ​​the display panel of Fig. 3. Fig. 12 is a cross-sectional view taken along line III-III' of Fig. 11.

[0212] Referring to FIGS. 11 and 12, the pad area (PA) of the display panel (DP) is configured substantially identically to the non-display area (NDA) and pad electrode (PDE) of the display panel (DP) of FIGS. 9 and 10. Therefore, repetitive detailed descriptions of elements identical or similar to those described above may be omitted or simplified.

[0213] In one embodiment, the display panel (DP) may also include sub-pixels (SP) in the pad area (PA). The sub-pixels (SP) arranged in the pad area (PA) may be arranged in the same manner as the sub-pixels (SP) arranged in the display area (DA). However, the present invention is not limited thereto, and in another embodiment, the sub-pixels (SP) may not be arranged in the pad area (PA).

[0214] The pads (PD) of FIG. 3 may each be formed of or include a plurality of pad electrodes (PDE). The plurality of pad electrodes (PDE) may be arranged on the third conductive layer (CDL3) in the pad area (PA). Each of the plurality of pad electrodes (PDE) may be formed of a single layer or multiple layers.

[0215] In the pad area (PA), among the pad electrodes (PDE) arranged in the pad area (PA), the pad electrodes (PDE) supplying the first power voltage (VDDN) can transmit the first power voltage (VDDN) to the display element layer (DPL). Therefore, among the pad electrodes (PDE) arranged in the pad area (PA), the pad electrodes (PDE) supplying the first power voltage (VDDN) can transmit the first power voltage (VDDN) to the first to third light-emitting element layers (LDL1, LDL2, LDL3) and the first to third conductive layers (CDL1, CDL2, CDL3).

[0216] In the pad area (PA), the first bonding pattern (BDP1) included in the display element layer (DPL) and the first reflective pattern (RFP1) on the first bonding pattern (BDP1) may be integrally formed within the pad area (PA). At this time, the first bonding pattern (BDP1) disposed in the pad area (PA) may be spaced apart from and not connected to the first bonding pattern (BDP1) disposed in the non-display area (NDA).

[0217] Pad electrodes (PDE) arranged in a pad area (PA) and supplying a first power voltage (VDDN) are connected to a third conductive layer (CDL3), third conductive patterns (CDP3), and a third light-emitting element (LD3), and can transmit the first power voltage (VDDN) to the third conductive layer (CDL3), third conductive patterns (CDP3), and third light-emitting element (LD3).

[0218] Through this, the same voltage is transmitted in the direction of the N-type semiconductor layer and the P-type semiconductor layer to each of the first light-emitting element (LD1-1), the first light-emitting element (LD1-2), the second light-emitting element (LD2), and the third light-emitting element (LD3), so that the first light-emitting element (LD1-1), the first light-emitting element (LD1-2), the second light-emitting element (LD2), and the third light-emitting element (LD3) arranged in the pad area (PA) may not emit light.

[0219] In one embodiment, pad electrodes (PDE) arranged in a pad area (PA) and supplying a first power voltage (VDDN) can transmit the first power voltage (VDDN) to a third conductive layer (CDL3), third conductive patterns (CDP3), and a third light-emitting element (LD3).

[0220] In one embodiment, the first power supply voltage (VDDN) can be transmitted from the third conductive layer (CDL3) to the N-type semiconductor layer side of the third light-emitting element (LD3). In addition, since the third conductive layer (CDL3) and the second conductive layer (CDL2) are connected to each other through the third conductive patterns (CDP3), the first power supply voltage (VDDN) can be transmitted from the second conductive layer (CDL2) to the N-type semiconductor layer side of the second light-emitting element (LD2). In this embodiment, since the second conductive layer (CDL2) and the first conductive layer (CDL1) are connected to each other through the second conductive patterns (CDP2), the first power supply voltage (VDDN) can be transmitted from the first conductive layer (CDL1) to the N-type semiconductor layer side of each of the first-first light-emitting element (LD1-1) and the first-second light-emitting element (LD1-2).

[0221] In this embodiment, since the first conductive layer (CDL1), the first bonding pattern (BDP1), and the first reflective pattern (RFP1) are connected to each other through the first conductive patterns (CDP1), the first power supply voltage (VDDN) can be connected to the first-first light-emitting element (LD1-1), the first-second light-emitting element (LD1-2), the first connection pattern (CNP1), and the second connection pattern (CNP2) which are connected to the first bonding pattern (BDP1) and the first reflective pattern (RFP1). That is, the first power supply voltage (VDDN) can be transmitted to the P-type semiconductor layer side of each of the first-first light-emitting element (LD1-1), the first-second light-emitting element (LD1-2), the second light-emitting element (LD2), and the third light-emitting element (LD3). Accordingly, since the same voltage is applied to each of the N-type semiconductor layer and the P-type semiconductor layer of each of the first light-emitting element (LD1-1), the first-second light-emitting element (LD1-2), the second light-emitting element (LD2), and the third light-emitting element (LD3), the first-first light-emitting element (LD1-1), the first-second light-emitting element (LD1-2), the second light-emitting element (LD2), and the third light-emitting element (LD3) may not emit light.

[0222] In one embodiment, the first bonding pattern (BDP1) and the first reflective pattern (RFP1) can transmit a first power voltage (VDDN) to the pixel circuit layer (PCL). The pixel circuit layer (PCL) of the pad area (PA) is connected to the pixel circuit layer (PCL) of the display area (DA), and the first power voltage (VDDN) can be transmitted to the P-type semiconductor layer side of each of the first-first light-emitting element (LD1-1), the first-second light-emitting element (LD1-2), the second light-emitting element (LD2), and the third light-emitting element (LD3) through the pixel circuit layer (PCL) of the display area (DA). Accordingly, each of the first-first light-emitting element (LD1-1), the first-second light-emitting element (LD1-2), the second light-emitting element (LD2), and the third light-emitting element (LD3) of the display area (DA) receives the first power voltage (VDDN) from the P-type semiconductor layer side and the second power voltage (VSSN) from the N-type semiconductor layer side, and thus can generate light using the voltage difference.

[0223] Accordingly, a structure can be configured in which light emitting elements (LDs) are placed in the pad area (PA) to ensure uniform quality in the process, but light is not emitted from the pad area (PA).

[0224] In one embodiment, the display panel (DP) includes first to third light-emitting element layers (LDL1, LDL2, LDL3) each including light-emitting elements (LD) that generate different light, and the light-emitting elements (LD) are arranged to be spaced apart from each other on a plane, thereby improving the reliability of each light-emitting element (LD) and maximizing the aperture ratio of a sub-pixel area unit.

[0225] In this embodiment, since each of the first to third light-emitting element layers (LDL1, LDL2, LDL3) further includes conductive patterns (CDP) having a mesh structure that are arranged and connected to each other on the display panel (DP), the voltage drop (IR Drop) phenomenon, which occurs as the voltage decreases due to resistance as it moves toward the center of the display area (DA), can be reduced. As a result, the contact resistance can also be minimized.

[0226] In this embodiment, each of the conductive patterns (CDP) includes a reflective electrode (RFE) on its side, so that light generated by the light-emitting elements (LD) is reflected and emitted to the display surface of the display panel (DP). This can improve the light output efficiency of the display device.

[0227] Fig. 13 is a cross-sectional view showing another embodiment of Fig. 7.

[0228] The display panel (DP'') according to the present embodiment illustrated in FIG. 13 is substantially the same as the display panel (DP) described above in FIG. 7, except that the first to third bridge patterns (BRP1, BRP2, BRP3) of FIG. 7 are omitted or replaced with the fourth bonding pattern (BDP4) and the fourth reflective pattern (RFP4). Therefore, repetitive detailed descriptions of elements identical or similar to those described above may be omitted or simplified.

[0229] Referring to FIG. 13, in the display area DA, the second light-emitting element layer LDL2 may further include a fourth bonding pattern BDP4 and a fourth reflective pattern RFP4 disposed on the fourth bonding pattern BDP4. The fourth bonding pattern BDP4 and the fourth reflective pattern RFP4 may overlap with the first sub-pixel area SPA1, and may overlap with the second bonding pattern BDP2 and the second reflective pattern RFP2 in a horizontal direction orthogonal to the third direction DR3.

[0230] In one embodiment, the first conductive layer (CDL1) may not include the first and second bridge patterns (BRP1, BRP2) of FIG. 7, and may have a first opening (OP1) overlapping the third sub-pixel area (SPA3) and a second opening (OP2) overlapping the first sub-pixel area (SPA1). In this embodiment, the second conductive layer (CDL2) may not include the third bridge pattern (BRP3) of FIG. 7, and may have a third opening (OP3) overlapping the first sub-pixel area (SPA1). Accordingly, each of the first to third openings (OP1, OP2, OP3) may have a circular or rectangular shape rather than a ring shape on a plane.

[0231] The first-first connection pattern (CNP1-1) and the first-second connection pattern (CNP1-2) contact each other through the first opening (OP1) and can be directly connected.

[0232] Through the second opening (OP2), the second-first connection pattern (CNP2-1) and the second-second connection pattern (CNP2-2) can be in contact with each other and directly connected, and through the third opening (OP3), the second-second connection pattern (CNP2-2) and the second-third connection pattern (CNP2-3) can be in contact with each other and directly connected. In addition, the second-second connection pattern (CNP2-2) is divided into two parts and can be connected to each other by the fourth bonding pattern (BDP4) and the fourth reflection pattern (RFP4).

[0233] Fig. 14 is a cross-sectional view showing another embodiment of Fig. 10.

[0234] The display panel (DP'') according to the present embodiment illustrated in FIG. 14 is substantially the same as the display panel (DP) described above in FIG. 10, except that the first to third bridge patterns (BRP1, BRP2, BRP3) of FIG. 10 are omitted and the first to third bonding patterns (BDP1, BDP2, BDP3) and the first to third reflective patterns (RFP1, RFP2, RFP3) extend over the non-display area (NDA). Therefore, repetitive detailed descriptions of elements identical or similar to those described above may be omitted or simplified.

[0235] Referring further to FIG. 14, in the non-display area (NDA), the first bonding pattern (BDP1) and the first reflective pattern (RFP1) of the first light-emitting element layer (LDL1) may extend entirely, the second bonding pattern (BDP2) and the second reflective pattern (RFP2) of the second light-emitting element layer (LDL2) may extend entirely, and the third bonding pattern (BDP3) and the third reflective pattern (RFP3) of the third light-emitting element layer (LDL3) may extend entirely. That is, since the first to third bonding patterns (BDP1, BDP2, BDP3) and the first to third reflective patterns (RFP1, RFP2, RFP3) extend entirely over the non-display area (NDA), a signal (e.g., the second power voltage (VSSN)) transmitted from the pixel circuit layer (PCL) through the first to third bonding patterns (BDP1, BDP2, BDP3) and the first to third reflective patterns (RFP1, RFP2, RFP3) can be transmitted to the first to third light-emitting element layers (LDL1, LDL2, LDL3).

[0236] Fig. 15 is a cross-sectional view showing another embodiment of Fig. 12.

[0237] The display panel (DP'') according to the present embodiment illustrated in FIG. 15 is substantially the same as the display panel (DP) described above in FIG. 12, except that the first to third bridge patterns (BRP1, BRP2, BRP3) of FIG. 12 are omitted and the first to third bonding patterns (BDP1, BDP2, BDP3) and the first to third reflective patterns (RFP1, RFP2, RFP3) extend over the pad area (PA). Therefore, repetitive detailed descriptions of elements identical or similar to those described above may be omitted or simplified.

[0238] Referring further to FIG. 15, in the pad area (PA), the first bonding pattern (BDP1) and the first reflective pattern (RFP1) of the first light-emitting element layer (LDL1) may extend entirely, the second bonding pattern (BDP2) and the second reflective pattern (RFP2) of the second light-emitting element layer (LDL2) may extend entirely, and the third bonding pattern (BDP3) and the third reflective pattern (RFP3) of the third light-emitting element layer (LDL3) may extend entirely. That is, since the first to third bonding patterns (BDP1, BDP2, BDP3) and the first to third reflective patterns (RFP1, RFP2, RFP3) extend entirely over the pad area (PA), a signal (e.g., the first power voltage (VDDN)) transmitted from the pad electrodes (PDE) through the first to third bonding patterns (BDP1, BDP2, BDP3) and the first to third reflective patterns (RFP1, RFP2, RFP3) can be transmitted to the first to third light-emitting element layers (LDL1, LDL2, LDL3).

[0239] FIGS. 16 to 46 are drawings showing a method for manufacturing a display device (display panel) according to one embodiment of the present invention.

[0240] FIGS. 16 to 46 illustrate one embodiment of a method for manufacturing the display panel (DP) illustrated in FIGS. 1 to 8 . Specifically, FIGS. 16 to 46 may illustrate a method for manufacturing a display panel (DP) positioned in a display area (DA). Therefore, repetitive detailed descriptions of elements identical or similar to those described above may be omitted or simplified.

[0241] Referring to FIG. 16, in one embodiment of a method for manufacturing a display panel (DP), a pixel circuit layer (PCL) including pixel circuits (PCC) and bonding electrodes (BDE) may be formed. The bonding electrodes (BDE) may overlap with the first to fourth sub-pixel areas (SPA1, SPA2, SPA3, SPA4) respectively (or may be formed in the first to fourth sub-pixel areas (SPA1, SPA2, SPA3, SPA4) respectively) and may be connected to the pixel circuits (PCC) respectively on the pixel circuits (PCC). In addition, a first insulating layer (ISL1) may be formed around the pixel circuits (PCC) and the bonding electrodes (BDE). The first insulating layer (ISL1) may be formed of or include an oxide.

[0242] Referring to FIGS. 17 to 28, a first light-emitting element layer (LDL1) can be formed on a pixel circuit layer (PCL).

[0243] Referring to FIG. 17, in one embodiment, a first epi wafer substrate (EPW1) may be formed or prepared. The first epi wafer substrate (EPW1) may include a first silicon wafer (SW1), a first N-type base semiconductor layer (NBSC1) on the first silicon wafer (SW1), a first base active layer (BAL1) on the first N-type base semiconductor layer (NBSC1), a first P-type base semiconductor layer (PBSC1) on the first base active layer (BAL1), and a first reflective layer (RFL1) on the first P-type base semiconductor layer (PBSC1), and a first-second bonding layer (BDL1-2) may be further formed on the first reflective layer (RFL1), for example, on the first epi wafer substrate (EPW1).

[0244] The first silicon wafer (SW1) may be a base plate for growing a target material. In one embodiment, for example, the first silicon wafer (SW1) may be a wafer for epitaxial growth of a material. The first silicon wafer (SW1) may be an example of a silicon substrate, but the material for forming the first silicon wafer (SW1) is not limited thereto.

[0245] The first N-type base semiconductor layer (NBSC1) can be epitaxially grown on the first silicon wafer (SW1). The first N-type base semiconductor layer (NBSC1) can be formed of or include at least one selected from the materials constituting the first semiconductor layer (21) described above in FIG. 8. In one embodiment, for example, the first N-type base semiconductor layer (NBSC1) can include a gallium nitride (GaN) semiconductor material doped with a first conductive dopant (or n-type dopant).

[0246] The first base active layer (BAL1) can be epitaxially grown on the first N-type base semiconductor layer (NBSC1). The first base active layer (BAL1) can be formed in one of the structures corresponding to the aforementioned active layer (22) of FIG. 8.

[0247] The first P-type base semiconductor layer (PBSC1) can be epitaxially grown on the first base active layer (BAL1). The first P-type base semiconductor layer (PBSC1) can be formed of or include at least one selected from the materials constituting the second semiconductor layer (23) described above in FIG. 8. In one embodiment, for example, the first P-type base semiconductor layer (PBSC1) can include a gallium nitride (GaN) semiconductor material doped with a second conductive dopant (or P-type dopant).

[0248] The first reflective layer (RFL1) may be formed on the first P-type base semiconductor layer (PBSC1). The first reflective layer (RFL1) may be formed of or include aluminum.

[0249] The first-second bonding layer (BDL1-2) may be formed on the first reflective layer (RFL1). The first-second bonding layer (BDL1-2) may be formed of or include titanium.

[0250] Referring to FIG. 18, a first bonding layer (BDL1-1) may be formed on a pixel circuit layer (PCL). The first bonding layer (BDL1-1) may be formed of titanium.

[0251] Thereafter, the pixel circuit layer (PCL) and the first epi wafer substrate (EPW1) can be bonded such that the first-first bonding layer (BDL1-1) and the first-second bonding layer (BDL1-2) face each other. Accordingly, the first-first bonding layer (BDL1-1) and the first-second bonding layer (BDL1-2) can be bonded to each other to form a double-layered first bonding layer (BDL1).

[0252] A first epi wafer substrate (EPW1) can be bonded to a pixel circuit layer (PCL) in a structure in which a first-second bonding layer (BDL1-2), a first reflective layer (RFL1), a first P-type base semiconductor layer (PBSC1), a first base active layer (BAL1), a first N-type base semiconductor layer (NBSC1), and a first silicon wafer (SW1) are stacked in a third direction (DR3).

[0253] Referring to FIG. 19, a first base semiconductor layer (BSCL1) may be formed by removing (or patterning) a first silicon wafer (SW1) and a portion of a first N-type base semiconductor layer (NBSC1) from a first epi wafer substrate (EPW1). The first base semiconductor layer (BSCL1) may include a first P-type base semiconductor layer (PBSC1), a first base active layer (BAL1), and a first N-type base semiconductor layer (NBSC1).

[0254] In the display panel according to the present embodiment, which is a high-resolution display panel, the thickness of the first base semiconductor layer (BSCL1) can be formed to be about 1 micrometer or less.

[0255] Referring to FIGS. 20 to 22, a first base semiconductor layer (BSCL1) can be patterned to form a first light-emitting element (LD1).

[0256] Referring to FIG. 20, a first hard mask layer (HML1) may be formed on a first base semiconductor layer (BSCL1). The first hard mask layer (HML1) may be formed of or include the same material as the first insulating layer (ISL1). In one embodiment, the first hard mask layer (HML1) may be formed of or include an oxide.

[0257] First photoresist patterns (PRP1) may be formed on the first hard mask layer (HML1). The first photoresist patterns (PRP1) may be formed in the second sub-pixel area (SPA2) and the fourth sub-pixel area (SPA4), respectively.

[0258] Referring to FIG. 21, a first hard mask layer (HML1) can be patterned using first photoresist patterns (PRP1). Accordingly, first hard mask patterns (HM1) can be formed to overlap the second sub-pixel area (SPA2) and the fourth sub-pixel area (SPA4), respectively.

[0259] Referring to FIG. 22, the first base semiconductor layer (BSCL1) can be patterned using the first hard mask patterns (HM1). Accordingly, the first-first light-emitting element (LD1-1) and the first-second light-emitting element (LD1-2) can be formed to overlap the second sub-pixel area (SPA2) and the fourth sub-pixel area (SPA4), respectively.

[0260] Referring to FIG. 23, a photoresist layer (PRL) can be formed on the first reflective layer (RFL1) to cover the first hard mask patterns (HM1), the first-first light-emitting element (LD1-1), and the first-second light-emitting element (LD1-2).

[0261] Referring to FIG. 24, by exposing and developing the photoresist layer (PRL), second photoresist patterns (PRP2) can be formed that overlap the first sub-pixel area (SPA1) and the third sub-pixel area (SPA3) in which the first-first light-emitting element (LD1-1) and the first-second light-emitting element (LD1-2) are not formed.

[0262] Referring to FIG. 25, the first reflective layer (RFL1) and the first bonding layer (BDL1) can be patterned using the second photoresist patterns (PRP2), the first-first light-emitting element (LD1-1), and the first-second light-emitting element (LD1-2). Accordingly, the first bonding patterns (BDP1) and the first reflective patterns (RFP1) disposed on the first bonding patterns (BDP1) can be formed to overlap with and be spaced apart from each other in the first to fourth sub-pixel areas (SPA1, SPA2, SPA3, and SPA4), respectively. Accordingly, the first-first light-emitting element (LD1-1) and the first-second light-emitting element (LD1-2) can be disposed on the first bonding patterns (BDP1) and the first reflective patterns (RFP1) in the second and fourth sub-pixel areas (SPA2, SPA4), respectively.

[0263] Referring to FIG. 26, a first insulating layer (ISL1) may be further formed to cover the first bonding patterns (BDP1), the first reflective patterns (RFP1), the first-first light-emitting element (LD1-1), and the first-second light-emitting element (LD1-2). Since the first hard mask patterns (HM1) are formed of the same material as the first insulating layer (ISL1), they may be included in the first insulating layer (ISL1) without being removed.

[0264] The upper surface of the first insulating layer (ISL1) can be flattened so that the distance (t1) between the upper surface of each of the first-first light-emitting element (LD1-1) and the first-second light-emitting element (LD1-2) and the upper surface of the first insulating layer (ISL1) has a thickness of about 300 nm.

[0265] Referring to FIG. 27, first pattern openings (POP1) may be formed in a first insulating layer (ISL1) disposed on a pixel circuit layer (PCL). The first pattern openings (POP1) formed in the first insulating layer (ISL1) on the pixel circuit layer (PCL) may have a groove shape. The first pattern openings (POP1) may include first-first pattern openings (POP1-1) formed between the first to fourth sub-pixel areas (SPA1, SPA2, SPA3, SPA4) and first-second pattern openings (POP1-2) formed in the first and third sub-pixel areas (SPA1, SPA3). Accordingly, the first-first pattern openings (POP1-1) can be spaced apart from the first bonding patterns (BDP1), the first reflective patterns (RFP1), the first-first light-emitting element (LD1-1) and the first-second light-emitting element (LD1-2), and the first-second pattern openings (POP1-2) can expose the first reflective patterns (RFP1), respectively.

[0266] The first-first pattern openings (POP1-1) and the first-second pattern openings (POP1-2) may be formed in separate processes. However, the present invention is not limited thereto, and in another embodiment, the first-first pattern openings (POP1-1) and the first-second pattern openings (POP1-2) may be formed simultaneously.

[0267] Referring to FIG. 28, a reflective electrode (RFE) may be formed within each of the 1-1 pattern openings (POP1-1). The reflective electrode (RFE) may be deposited with a constant thickness within each of the 1-1 pattern openings (POP1-1). The reflective electrode (RFE) may be formed of or include at least one selected from aluminum and silver. In addition, a connection electrode (CNE) may be formed within each of the 1-1 pattern openings (POP1-1). The connection electrode (CNE) may be formed by filling the inside of the reflective electrode (RFE). The connection electrode (CNE) may be formed of or include at least one selected from copper and tungsten. The reflective electrode (RFE) and the connection electrode (CNE) are formed within each of the 1-1 pattern openings (POP1-1), and the upper surface may be planarized through a chemical mechanical polishing (CMP) process. Accordingly, first conductive patterns (CDP1) can be formed within each of the first-1 pattern openings (POP1-1).

[0268] In this embodiment, connection patterns (CNP1-1, CNP2-1) may be formed within the first-second pattern openings (POP1-2), respectively. The first-first connection pattern (CNP1-1) may be formed within the first-second pattern opening (POP1-2) overlapping the third sub-pixel area (SPA3), and the second-first connection pattern (CNP2-1) may be formed within the first-second pattern opening (POP1-2) overlapping the first sub-pixel area (SPA1). The first-first connection pattern (CNP1-1) and the second-first connection pattern (CNP2-1) may be formed of or include the same material as the connection electrode (CNE).

[0269] The first conductive patterns (CDP1) and the first-first connection pattern (CNP1-1) and the second-first connection pattern (CNP2-1) may be formed in separate processes. However, the present invention is not limited thereto, and the first conductive patterns (CDP1) and the first-first connection pattern (CNP1-1) and the second-first connection pattern (CNP2-1) may be formed simultaneously. In an embodiment in which the first conductive patterns (CDP1) and the first-first connection pattern (CNP1-1) and the second-first connection pattern (CNP2-1) are formed simultaneously, the first-first connection pattern (CNP1-1) and the second-first connection pattern (CNP2-1) may be formed with the same structure as the first conductive patterns (CDP1). That is, reflective electrodes may be further formed on the side and bottom surfaces of each of the first-first connection pattern (CNP1-1) and the second-first connection pattern (CNP2-1).

[0270] Through the steps described above, a first light-emitting element layer (LDL1) including first bonding patterns (BDP1), first reflective patterns (RFP1), at least one first light-emitting element (LD1), first conductive patterns (CDP1), a first-first connection pattern (CNP1-1), and a first-second connection pattern (CNP1-2) can be formed.

[0271] Referring to FIG. 29, first contact holes (CNT1) exposing the first light-emitting element (LD1-1) and the first light-emitting element (LD1-2) to the first insulating layer (ISL1) can be formed on the first light-emitting element (LD1-1) and the first light-emitting element (LD1-2), respectively.

[0272] A first conductive layer (CDL1) may be formed on a first light-emitting element layer (LDL1). The first conductive layer (CDL1) may contact the first-first light-emitting element (LD1-1) and the first-second light-emitting element (LD1-2) through the first contact holes (CNT1). In addition, the first conductive layer (CDL1) may also contact the first conductive patterns (CDP1) and cover the upper surface of each of the first conductive patterns (CDP1). The first conductive layer (CDL1) may be formed of or include indium tin oxide.

[0273] In addition, a first opening (OP1) overlapping with the third sub-pixel area (SPA3) and a second opening (OP2) overlapping with the first sub-pixel area (SPA1) may be formed in the first conductive layer (CDL1). In one embodiment, the first opening (OP1) may be formed in a ring shape on a plane, so that a first bridge pattern (BRP1) may be formed in the middle of the first opening (OP1) and spaced apart from a portion of another first conductive layer (CDL1). The first bridge pattern (BRP1) may cover the upper surface of the exposed first-first connection pattern (CNP1-1). In this embodiment, the second opening (OP2) may be formed in a ring shape on a plane, so that a second bridge pattern (BRP2) may be formed in the middle of the second opening (OP2) and spaced apart from a portion of another first conductive layer (CDL1). The second bridge pattern (BRP2) can cover the upper surface of the exposed second-1 connection pattern (CNP2-1).

[0274] Referring to FIG. 30, a second insulating layer (ISL2) may be formed on a first conductive layer (CDL1). A contact hole may be formed in the second insulating layer (ISL2) to overlap with a third sub-pixel area (SPA3) and expose at least a portion of the first bridge pattern (BRP1). A first-second connection pattern (CNP1-2) may be formed in the contact hole. Accordingly, the first-second connection pattern (CNP1-2) may be formed on the first bridge pattern (BRP1) and may be connected to the first bridge pattern (BRP1).

[0275] Referring to FIG. 31, a second-first bonding layer (BDL2-1) may be formed on a second insulating layer (ISL2). The second-first bonding layer (BDL2-1) may be formed of or include titanium. In addition, a second epi wafer substrate (EPW2) including a second silicon wafer (SW2), a second N-type base semiconductor layer (NBSC2), a second base active layer (BAL2), a second P-type base semiconductor layer (PBSC2), a second reflective layer (RFL2), and a second-second bonding layer (BDL2-2) may be formed or prepared.

[0276] Thereafter, the first light-emitting element layer (LDL1) and the second epi wafer substrate (EPW2) can be bonded such that the second-first bonding layer (BDL2-1) and the second-second bonding layer (BDL2-2) face each other. Accordingly, the second-first bonding layer (BDL2-1) and the second-second bonding layer (BDL2-2) can be bonded to each other to form a double-layered second bonding layer (BDL2).

[0277] Referring to FIG. 32, a second silicon wafer (SW2) and a portion of a second N-type base semiconductor layer (NBSC2) may be removed from a second epi wafer substrate (EPW2) to form a second base semiconductor layer (BSCL2). The second base semiconductor layer (BSCL2) may include a second P-type base semiconductor layer (PBSC2), a second base active layer (BAL2), and a second N-type base semiconductor layer (NBSC2).

[0278] A second hard mask pattern (HM2) may be formed on the second base semiconductor layer (BSCL2). The second hard mask pattern (HM2) may be formed of the same material as the second insulating layer (ISL2). In an embodiment, the second hard mask pattern (HM2) may be formed of or include an oxide.

[0279] Referring to FIG. 33, a second base semiconductor layer (BSCL2), a second reflective layer (RFL2), and a second bonding layer (BDL2) can be patterned using a second hard mask pattern (HM2). Accordingly, a second light-emitting element (LD2), a second reflective pattern (RFP2), and a second bonding pattern (BDP2) overlapping a third sub-pixel area (SPA3) can be formed.

[0280] Referring to FIG. 34, a second insulating layer (ISL2) may be further formed to cover the second bonding pattern (BDP2), the second reflective pattern (RFP2), and the second light-emitting element (LD2). Since the second hard mask pattern (HM2) is formed of the same material as the second insulating layer (ISL2), it may be included in the second insulating layer (ISL2) without being removed.

[0281] Referring to FIG. 35, second pattern openings (POP2) may be formed in a second insulating layer (ISL2) disposed on a first conductive layer (CDL1). The second pattern openings (POP2) may include 2-1 pattern openings (POP2-1) formed between the first to fourth sub-pixel areas (SPA1, SPA2, SPA3, SPA4) and 2-2 pattern openings (POP2-2) formed in the first sub-pixel area (SPA1). Accordingly, the 2-1 pattern openings (POP2-1) may be spaced apart from the second bonding pattern (BDP2), the second reflective pattern (RFP2), and the second light-emitting element (LD2), and the 2-2 pattern openings (POP2-2) may expose the second bridge pattern (BRP2).

[0282] Referring to FIG. 36, a reflective electrode (RFE) may be formed within each of the 2-1 pattern openings (POP2-1). In addition, a connection electrode (CNE) may be formed to fill the interior of the reflective electrode (RFE) within each of the 2-1 pattern openings (POP2-1). The reflective electrode (RFE) and the connection electrode (CNE) may be formed within each of the 2-1 pattern openings (POP2-1), and the upper surface may be planarized through a chemical mechanical polishing (CMP) process. Accordingly, second conductive patterns (CDP2) may be formed within each of the 2-1 pattern openings (POP2-1).

[0283] In one embodiment, a second-second connection pattern (CNP2-2) may be formed within a second-second pattern opening (POP2-2). The second-second connection pattern (CNP2-2) may be formed of or include the same material as the connection electrode (CNE).

[0284] Through the above steps, a second light-emitting element layer (LDL2) including a second bonding pattern (BDP2), a second reflective pattern (RFP2), a second light-emitting element (LD2), second conductive patterns (CDP2), and a second-second connection pattern (CNP2-2) can be formed.

[0285] Referring to FIG. 37, a second contact hole (CNT2) exposing the second light-emitting element (LD2) to the second insulating layer (ISL2) may be formed on the second light-emitting element (LD2).

[0286] A second conductive layer (CDL2) may be formed on the second light-emitting element layer (LDL2). The second conductive layer (CDL2) may be in contact with the second light-emitting element (LD2) through the second contact hole (CNT2). In addition, the second conductive layer (CDL2) may also be in contact with the second conductive patterns (CDP2) and may cover the upper surface of each of the second conductive patterns (CDP2).

[0287] In one embodiment, a third opening (OP3) overlapping the first sub-pixel area (SPA1) may be formed in the second conductive layer (CDL2). Since the third opening (OP3) is formed in a ring shape on a plane, a third bridge pattern (BRP3) may be formed in the middle of the third opening (OP3) and spaced apart from another portion of the third conductive layer (CDL3). The third bridge pattern (BRP3) may cover the upper surface of the exposed second-second connection pattern (CNP2-2).

[0288] Referring to FIG. 38, a third insulating layer (ISL3) may be formed on the second conductive layer (CDL2). A contact hole may be formed in the third insulating layer (ISL3) to overlap the first sub-pixel area (SPA1) and expose at least a portion of the third bridge pattern (BRP3). A second-third connection pattern (CNP2-3) may be formed in the contact hole. Accordingly, the second-third connection pattern (CNP2-3) may be formed on the third bridge pattern (BRP3) and connected to the third bridge pattern (BRP3).

[0289] Referring to FIG. 39, a third-first bonding layer (BDL3-1) may be formed on a third insulating layer (ISL3). In addition, a third epi wafer substrate (EPW3) including a third silicon wafer (SW3), a third N-type base semiconductor layer (NBSC3), a third base active layer (BAL3), a third P-type base semiconductor layer (PBSC3), a third reflective layer (RFL3), and a third-second bonding layer (BDL3-2) may be formed.

[0290] Thereafter, the second light-emitting element layer (LDL2) and the third epi wafer substrate (EPW3) can be bonded such that the third-first bonding layer (BDL3-1) and the third-second bonding layer (BDL3-2) face each other. Accordingly, the third-first bonding layer (BDL3-1) and the third-second bonding layer (BDL3-2) can be bonded to each other to form a double-layer third bonding layer (BDL3).

[0291] Referring to FIG. 40, a third silicon wafer (SW3) and a portion of a third N-type base semiconductor layer (NBSC3) may be removed from a third epi wafer substrate (EPW3) to form a third base semiconductor layer (BSCL3). The third base semiconductor layer (BSCL3) may include a third P-type base semiconductor layer (PBSC3), a third base active layer (BAL3), and a third N-type base semiconductor layer (NBSC3).

[0292] A third hard mask pattern (HM3) may be formed on the third base semiconductor layer (BSCL3). The third hard mask pattern (HM3) may be formed of the same material as the third insulating layer (ISL3). In one embodiment, the third hard mask pattern (HM3) may be formed of or include an oxide.

[0293] Referring to FIG. 41, a third base semiconductor layer (BSCL3), a third reflective layer (RFL3), and a third bonding layer (BDL3) can be patterned using a third hard mask pattern (HM3). Accordingly, a third light-emitting element (LD3), a third reflective pattern (RFP3), and a third bonding pattern (BDP3) overlapping the first sub-pixel area (SPA1) can be formed.

[0294] Referring to FIG. 42, a third insulating layer (ISL3) may be further formed to cover the third bonding pattern (BDP3), the third reflective pattern (RFP3), and the third light-emitting element (LD3). Since the third hard mask pattern (HM3) is formed of the same material as the third insulating layer (ISL3), it may be included in the third insulating layer (ISL3) without being removed.

[0295] Referring to FIG. 43, third pattern openings (POP3) may be formed in a third insulating layer (ISL3) disposed on a second conductive layer (CDL2). The third pattern openings (POP3) may be formed between the first to fourth sub-pixel areas (SPA1, SPA2, SPA3, SPA4). Accordingly, the third pattern openings (POP3) may be spaced apart from the third bonding pattern (BDP3), the third reflective pattern (RFP3), and the third light-emitting element (LD3).

[0296] Referring to FIG. 44, a reflective electrode (RFE) may be formed within each of the third pattern openings (POP3). In addition, a connection electrode (CNE) may be formed to fill the interior of the reflective electrode (RFE) within each of the third pattern openings (POP3). The reflective electrode (RFE) and the connection electrode (CNE) may be formed within each of the third pattern openings (POP3), and the upper surface may be planarized through a chemical mechanical polishing (CMP) process. Accordingly, third conductive patterns (CDP3) may be formed within each of the third pattern openings (POP3).

[0297] Through the above steps, a third light-emitting element layer (LDL3) including a third bonding pattern (BDP3), a third reflective pattern (RFP3), a third light-emitting element (LD3), and second conductive patterns (CDP2) can be formed.

[0298] Referring to FIG. 45, a third contact hole (CNT3) exposing the third light-emitting element (LD3) to the third insulating layer (ISL3) may be formed on the third light-emitting element (LD3).

[0299] A third conductive layer (CDL3) may be formed on a third light-emitting element layer (LDL3). The third conductive layer (CDL3) may be in contact with the third light-emitting element (LD3) through a third contact hole (CNT3). In addition, the third conductive layer (CDL3) may also be in contact with the third conductive patterns (CDP3) and may cover the upper surface of each of the third conductive patterns (CDP3).

[0300] Additionally, the third conductive layer (CDL3) can extend across the entire display panel.

[0301] Referring to Fig. 46, a fourth insulating layer (ISL) may be formed on a third conductive layer (CDL3). A lens layer (LSL) may be formed on the fourth insulating layer (ISL). The lens layer (LSL) may include lenses (LS) formed in each of the first to fourth sub-pixel areas (SPA1, SPA2, SPA3, SPA4).

[0302] FIG. 47 is a schematic block diagram illustrating an electronic device (1000) including a display device according to an embodiment. FIG. 48 is a schematic diagram illustrating an embodiment in which the electronic device (1000) of FIG. 47 is a smartphone. FIG. 49 is a schematic diagram illustrating an embodiment in which the electronic device (1000) of FIG. 47 is a tablet computer.

[0303] Referring to FIGS. 47 to 49, an embodiment of an electronic device (1000) may include a processor (1010), a memory device (1020), a storage device (1030), an input / output (I / O) device (1040), a power supply device (1050), and a display device (1060). The display device (1060) may be the display device (DD) of FIG. 1. The electronic device (1000) may additionally include various ports for communicating with a video card, a sound card, a memory card, a USB device, or other systems. As illustrated in FIG. 48, in one embodiment, the electronic device (1000) may be a smartphone. As illustrated in FIG. 49, in one embodiment, the electronic device (1000) may be a tablet computer. However, the examples mentioned above are illustrative, and the electronic device (1000) is not necessarily limited to the examples mentioned above. For example, in one embodiment, the electronic device (1000) may be a cellular phone, a video phone, a smart pad, a smart watch, a vehicle navigation device, a computer monitor, a laptop computer, a head-mounted display device, or the like.

[0304] The processor (1010) may perform a specific calculation or task. In one embodiment, the processor (1010) may include at least one of a central processing unit, an application processor, a graphics processing unit, a communication processor, an image signal processor, a controller, or the like. The processor (1010) may be connected to other components via an address bus, a control bus, a data bus, or the like. In one embodiment, the processor (1010) may be connected to an expansion bus, such as a peripheral component interconnect (PCI) bus. In one embodiment, the processor (1010) may provide input image data to the display device (1060). Accordingly, the display device (1060) may display an image based on the input image data provided from the processor (1010).

[0305] The memory device (1020) may store data for performing operations of the electronic device (1000). The memory device (1020) may function as a working memory and / or a buffer memory for the processor (1010). In one embodiment, for example, the memory device (1020) may include one or more volatile memory devices, such as a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, and a mobile DRAM device.

[0306] The storage device (1030) may store data in response to a control signal or data from the processor (1010). The storage device (1030) may include one or more non-volatile storages to maintain data even when the electronic device (1000) is powered off. In some embodiments, the storage device (1030) may include a solid state drive (SSD), a hard disk drive (HDD), a CD-ROM, or the like.

[0307] The I / O device (1040) may include input devices such as a keyboard, keypad, touchpad, touch screen, and mouse, and output devices such as speakers and printers. In an embodiment, a display device (1060) may be integrated with the I / O device (1040).

[0308] The power supply (1050) may supply power required to perform the operation of the electronic device (1000). In one embodiment, for example, the power supply (1050) may include a power management integrated circuit (PMIC). In one embodiment, the power supply (1050) may supply power to the display device (1060).

[0309] The display device (1060) can display an image in response to an image data signal and / or a control signal from the processor (1010). The display device (1060) can be connected to other components via a bus or other communication link.

[0310] The present invention should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the present invention to those skilled in the art.

[0311] While the present invention has been particularly shown and described with reference to exemplary embodiments, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit or scope of the invention as defined by the following claims.

Claims

1. A pixel circuit layer including a pixel circuit; A first light-emitting element layer disposed on the pixel circuit layer and including a first light-emitting element that generates light of a first color and first conductive patterns spaced apart from the first light-emitting element on a plane; A second light-emitting element layer disposed on the first light-emitting element layer, generating light of a second color different from the first color, and including a second light-emitting element spaced apart from the first light-emitting element on a plane, and second conductive patterns connected to the first conductive patterns; and A display device comprising: a third light-emitting element layer disposed on the second light-emitting element layer, generating light of a third color different from the first color and the second color, and including a third light-emitting element spaced apart from the first light-emitting element and the second light-emitting element on a plane, and third conductive patterns connected to the second conductive patterns; 2. In the first paragraph, each of the first conductive patterns is arranged between the first to third light-emitting elements on a plane without overlapping with the first to third light-emitting elements, The above second challenge patterns overlap with the above first challenge patterns on a plane, respectively, A display device in which the third challenge patterns overlap with the second challenge patterns on a plane.

3. In the first paragraph, each of the first to third challenge patterns, connecting electrodes; and A display device comprising a reflective electrode covering at least a portion of the above connecting electrode.

4. A display device according to claim 3, wherein the reflective electrode covers a side surface of the connecting electrode.

5. In the third paragraph, the connecting electrode includes at least one of copper and tungsten, A display device, wherein the reflective electrode comprises at least one of aluminum and silver.

6. In the first paragraph, a first conductive layer disposed between the first light-emitting element layer and the second light-emitting element layer; A second conductive layer disposed between the second light-emitting element layer and the third light-emitting element layer; and A display device further comprising a third conductive layer disposed on the third light-emitting element layer.

7. In the 6th paragraph, the first conductive layer is in contact with the first light-emitting element, the first conductive patterns and the second conductive patterns, The second conductive layer is in contact with the second light-emitting element, the second conductive patterns, and the third conductive patterns, A display device, wherein the third conductive layer is in contact with the third light-emitting element and the third conductive patterns.

8. A display device according to claim 6, wherein each of the first to third conductive layers comprises indium tin oxide (ITO).

9. In paragraph 6, A first connection pattern overlapping the second light-emitting element and connecting the pixel circuit layer and the second light-emitting element; and A display device further comprising a second connecting pattern overlapping the third light-emitting element and connecting the pixel circuit layer and the third light-emitting element.

10. A display device according to claim 9, wherein each of the first connection pattern and the second connection pattern includes at least one of copper and tungsten.

11. In the 9th paragraph, the first conductive layer is A first bridge pattern overlapping the second light-emitting element and in contact with the first connection pattern; and a second bridge pattern overlapping the third light-emitting element and in contact with the second connection pattern; A first opening is defined in the first conductive layer around the first bridge pattern, A display device, wherein a second opening is defined in the first conductive layer around the second bridge pattern.

12. In the 11th paragraph, the second conductive layer is a third bridge pattern overlapping the third light-emitting element and in contact with the second connection pattern; A display device, wherein a third opening is defined in the second conductive layer around the third bridge pattern.

13. In the 9th paragraph, the first light-emitting element layer, A display device further comprising first bonding patterns connected to the pixel circuit layer, the first light-emitting element, the first connection pattern, and the second connection pattern.

14. In the 13th paragraph, the second light emitting element layer, A display device further comprising a second bonding pattern connected to the first connection pattern and the second light-emitting element.

15. In the 14th paragraph, the third light-emitting element layer is A display device further comprising a third bonding pattern connected to the second connection pattern and the third light-emitting element.

16. In paragraph 1, A display device further comprising a lens layer disposed on the third light-emitting element layer and including lenses that overlap the first to third light-emitting elements, respectively.

17. In a display device including first to fourth sub-pixel areas, A pixel circuit layer including a pixel circuit; First to fourth sub-pixels arranged in the first to fourth sub-pixel areas, respectively; A first light-emitting element layer disposed on the pixel circuit layer, comprising a first light-emitting element disposed in the second sub-pixel area, a first light-emitting element disposed in the fourth sub-pixel area, and first conductive patterns disposed between the first to fourth sub-pixel areas; A second light-emitting element layer disposed on the first light-emitting element layer, including a second light-emitting element disposed in the third sub-pixel area and second conductive patterns disposed between the first to fourth sub-pixel areas and overlapping with the first conductive patterns respectively; and A display device comprising: a third light-emitting element layer disposed on the second light-emitting element layer, the third light-emitting element disposed in the first sub-pixel area, and third conductive patterns disposed between the first to fourth sub-pixel areas and overlapping the first and second conductive patterns, respectively; 18. In paragraph 17, A first conductive layer disposed between the first light-emitting element layer and the second light-emitting element layer and connected to the first-first light-emitting element, the first-second light-emitting element, the first conductive patterns, and the second conductive patterns; A second conductive layer disposed between the second light-emitting element layer and the third light-emitting element layer and connected to the second light-emitting element, the second conductive patterns, and the third conductive patterns; and A display device further comprising a third conductive layer disposed on the third light-emitting element layer and connected to the third light-emitting element and the third conductive patterns.

19. In the 18th paragraph, the first light-emitting element layer further includes a first-first connection pattern overlapping the third sub-pixel area, The second light-emitting element layer overlaps with the third sub-pixel area and further includes a first-second connection pattern connected to the first-first connection pattern and the second light-emitting element. A display device in which the first-first connection pattern and the first-second connection pattern are connected to each other through the first conductive layer.

20. In the 19th paragraph, the first light-emitting element layer further includes a second-1 connecting pattern overlapping the first sub-pixel area, The second light-emitting element layer further includes a second-second connection pattern overlapping the first sub-pixel area and connected to the second-first connection pattern, The third light-emitting element layer overlaps the first sub-pixel area and further includes a second-third connection pattern connected to the second-second connection pattern and the third light-emitting element, The above 2-1 connection pattern and the above 2-2 connection pattern are connected to each other through the first conductive layer, A display device in which the above-mentioned 2-2 connection pattern and the above-mentioned 2-3 connection pattern are connected to each other through the second conductive layer.

21. A processor providing input image data; and A display device for displaying an image according to the above input image data; The above display device, A pixel circuit layer including a pixel circuit; A first light-emitting element layer disposed on the pixel circuit layer and including a first light-emitting element that generates light of a first color and first conductive patterns spaced apart from the first light-emitting element on a plane; A second light-emitting element layer disposed on the first light-emitting element layer, generating light of a second color different from the first color, and including a second light-emitting element spaced apart from the first light-emitting element on a plane, and second conductive patterns connected to the first conductive patterns; and An electronic device comprising: a third light-emitting element layer disposed on the second light-emitting element layer, the third light-emitting element generating light of a third color different from the first color and the second color, and including a third light-emitting element spaced apart from the first light-emitting element and the second light-emitting element on a plane, and third conductive patterns connected to the second conductive patterns;

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