Address translation method and apparatus, and electronic device and storage medium

Abstract

Provided in the embodiments of the present disclosure are an address translation method and apparatus, and an electronic device and a storage medium. The address translation method is applied to an address translation apparatus, the apparatus comprising multiple sets of translation lookaside buffers, wherein each of the multiple sets of translation lookaside buffers is configured to store page table information for translating a virtual address into a physical address. The address translation method comprises: in response to obtaining a first virtual address translation request, determining a target translation lookaside buffer from multiple sets of translation lookaside buffers on the basis of a first mapping algorithm, wherein the first virtual address translation request comprises an object virtual address; and accessing page table information in the target translation lookaside buffer, in order to translate the object virtual address into an object physical address. The method further comprises: acquiring access frequency information for each of the multiple sets of translation lookaside buffers; on the basis of the access frequency information, determining whether the first mapping algorithm is required to be updated; and in response to the first mapping algorithm being required to be updated, updating the mapping algorithm to a second mapping algorithm.

Description

Address translation method and device, electronic device, and storage medium

[0001] This application claims priority to Chinese Patent Application No. 202411142514.0, filed on August 19, 2024, the disclosure of which is incorporated herein in its entirety as part of the present application. TECHNICAL FIELD

[0002] Embodiments of the present disclosure relate to an address translation method and device, an electronic device, and a storage medium. BACKGROUND

[0003] Currently, devices requiring virtual addressing, such as central processing unit (CPU) chips, graphics processing units (GPUs), etc., usually have specific address translation devices responsible for virtual address to physical address translation. For example, CPUs are responsible for virtual address to physical address translation by memory management units (MMUs). SUMMARY

[0004] At least one embodiment of the present disclosure provides an address translation method applied to an address translation device, the address translation device including a plurality of sets of translation buffers, each set of translation buffers including first page table information for converting a virtual address to a physical address, the method including: in response to obtaining a first virtual address translation request, determining a target translation buffer from the plurality of sets of translation buffers according to a first mapping algorithm, the first virtual address translation request including an object virtual address; and accessing the first page table information in the target translation buffer to convert the object virtual address to an object physical address, the method further including: obtaining access frequency information for each set of the plurality of sets of translation buffers; determining whether the first mapping algorithm needs to be updated according to the access frequency information; and in response to the first mapping algorithm needing to be updated, updating the first mapping algorithm to a second mapping algorithm.

[0005] For example, in the address translation method provided by some embodiments of the present disclosure, the address translation device further comprises a multi-level page table query module, the multi-level page table query module comprises second page table information, and the accessing the first page table information in the target translation buffer to convert the object virtual address into the object physical address comprises: accessing the first page table information in the target translation buffer to determine whether there is first target page table information matching the first virtual address translation request in the first page table information; in response to the first target page table information not existing in the target translation buffer, providing the first virtual address translation request to the multi-level page table query module; determining whether there is second target page table information matching the first virtual address translation request in the second page table information; and in response to the second target page table information not existing in the second page table information, converting the object virtual address into the object physical address based on the conversion information provided by the external memory.

[0006] For example, in the address translation method provided by some embodiments of the present disclosure, the first page table information comprises a plurality of page table entries, each page table entry corresponds to a physical page, the second page table information comprises a plurality of multi-level page tables, each multi-level page table comprises a plurality of page directory entries, each page directory entry is used to point to the physical address of the next level page table, and each page directory entry in the last level page table in the multi-level page table is used to point to the page table entry in the first page table information.

[0007] For example, in the address translation method provided by some embodiments of the present disclosure, the determining whether there is second target page table information matching the first virtual address translation request in the second page table information comprises: based on the object virtual address and the base address, obtaining a first page table read address of at least one level page table in the multi-level page table; and based on the first page table read address, determining whether there is second target page table information matching the first virtual address translation request in the second page table information.

[0008] For example, in the address conversion method provided by some embodiments of the present disclosure, in response to the second page table information not existing the second target page table information matched with the first virtual address conversion request, converting the object virtual address into the object physical address based on the conversion information provided by the external memory comprises: in response to the second page table information not existing the second target page table information matched with the first virtual address conversion request, judging whether the merge signal is valid; in response to the merge signal being valid, comparing whether the first page table read address is same as a second page table read address of a second virtual address conversion request located before the first virtual address conversion request; in response to the first page table read address being same as the second page table read address, merging the first virtual address conversion request with the second virtual address conversion request, waiting for the conversion information provided by the external memory in response to the second virtual address conversion request; and converting the object virtual address into the object physical address based on the conversion information.

[0009] For example, in the address conversion method provided by some embodiments of the present disclosure, in response to the second page table information not existing the second target page table information matched with the first virtual address conversion request, converting the object virtual address into the object physical address based on the conversion information provided by the external memory further comprises: in response to the first page table read address being different from the second page table read address, providing a page table read request based on the first virtual address conversion request to the external memory to acquire the conversion information from the external memory; and updating the merge signal to be invalid.

[0010] For example, in the address conversion method provided by some embodiments of the present disclosure, in response to the second page table information not existing the second target page table information matched with the first virtual address conversion request, converting the object virtual address into the object physical address based on the conversion information provided by the external memory further comprises: in response to the merge signal being invalid, providing a page table read request based on the first virtual address conversion request to the external memory to acquire the conversion information from the external memory; and updating the merge signal to be valid.

[0011] For example, in the address conversion method provided by some embodiments of the present disclosure, in response to the second page table information not existing the second target page table information matched with the first virtual address conversion request, converting the object virtual address into the object physical address based on the conversion information provided by the external memory further comprises: in response to the second page table information not existing the second target page table information matched with the first virtual address conversion request, judging whether the merge signal is valid; in response to the merge signal being valid, comparing whether the first page table read address is same as a second page table read address of a second virtual address conversion request located before the first virtual address conversion request; in response to the first page table read address being same as the second page table read address, merging the first virtual address conversion request with the second virtual address conversion request, waiting for the conversion information provided by the external memory in response to the second virtual address conversion request; and converting the object virtual address into the object physical address based on the conversion information.

[0012] For example, in the address conversion method provided by some embodiments of the present disclosure, the page table read request comprises a page table read address of the virtual address conversion request, an object virtual address, and an identification of a hardware access unit providing the virtual address conversion request, and the page table read address is obtained based on a base address and page directory entry data of at least one level of page table in the multi-level page table.

[0013] For example, in the address conversion method provided by some embodiments of the present disclosure, accessing the first page table information in the target conversion buffer to convert the object virtual address into the object physical address comprises: accessing the first page table information in the target conversion buffer, and determining whether there is a target page table entry matching the object virtual address conversion request in the first page table information; and in response to there being a target page table entry matching the object virtual address conversion request in the first page table information, determining the object physical address corresponding to the object virtual address based on the target page table entry and an offset within a page indicated by the object virtual address.

[0014] For example, in the address conversion method provided by some embodiments of the present disclosure, the conversion information comprises the target page table entry.

[0015] For example, in the address conversion method provided by some embodiments of the present disclosure, obtaining the access frequency information of each group of the plurality of groups of conversion buffers comprises: counting the number of accesses to each group of the plurality of groups of conversion buffers to obtain a count value of each group of the plurality of groups of conversion buffers within a preset time period.

[0016] For example, in the address conversion method provided by some embodiments of the present disclosure, determining whether the first mapping algorithm needs to be updated according to the access frequency information comprises: calculating an average access value of the count values of the plurality of groups of conversion buffers based on the count values of each group of the plurality of groups of conversion buffers; obtaining an allowed access deviation; calculating an effective access rate of the plurality of groups of conversion buffers based on the allowed access deviation and the average access value; and determining whether the first mapping algorithm needs to be updated based on the effective access rate.

[0017] For example, in the address conversion method provided by some embodiments of the present disclosure, based on the allowed access bias and the average access value, the effective access rate of the plurality of sets of translation buffers is calculated, including: based on the allowed access bias, calculating an access bias value of each set of the plurality of sets of translation buffers; based on the access bias value, calculating an effective utilization indication value of each set of the plurality of sets of translation buffers, for each set of the plurality of sets of translation buffers, in response to the sum of the access bias value and a count value being greater than or equal to the average access value, setting the effective utilization indication value of the translation buffer to a first preset value, and in response to the sum of the access bias value and the count value being less than the average access value, setting the effective utilization indication value of the translation buffer to a second preset value; and taking the average value of the effective utilization indication values of the plurality of sets of translation buffers as the effective access rate.

[0018] For example, in the address conversion method provided by some embodiments of the present disclosure, based on the effective access rate, it is determined whether the first mapping algorithm needs to be updated, including: in response to the effective access rate being greater than or equal to a preset access rate, it is determined that the first mapping algorithm does not need to be updated; and in response to the effective access rate being less than the preset access rate, it is determined that the first mapping algorithm needs to be updated.

[0019] For example, in the address conversion method provided by some embodiments of the present disclosure, the first mapping algorithm includes: determining the target translation buffer according to a first target bit of the object virtual address in the virtual address conversion request, and the second mapping algorithm includes: determining the target translation buffer according to a second target bit of the object virtual address in the virtual address conversion request, and the first target bit and the second target bit are different.

[0020] For example, in the address conversion method provided by some embodiments of the present disclosure, the first target bit includes a plurality of first bit positions in the object virtual address in series, and the second target bit includes a plurality of second bit positions in the object virtual address in series.

[0021] The address conversion device provided by some embodiments of the present disclosure comprises: an address conversion module comprising a plurality of sets of conversion buffers; an arbitration module configured to determine a target conversion buffer from the plurality of sets of conversion buffers according to a first mapping algorithm in response to obtaining a first virtual address conversion request, the first virtual address conversion request comprising an object virtual address; each set of the plurality of sets of conversion buffers is configured to store first page table information for converting the object virtual address into an object physical address; the address conversion module is configured to access the first page table information in the target conversion buffer to convert the object virtual address into the object physical address; the address conversion device further comprises an address conversion performance monitoring module configured to: obtain access frequency information of each set of the plurality of sets of conversion buffers; determine whether the first mapping algorithm needs to be updated according to the access frequency information; and in response to the first mapping algorithm needing to be updated, update the mapping algorithm to a second mapping algorithm.

[0022] For example, in the address conversion device provided by some embodiments of the present disclosure, further comprising: a multi-level page table query module comprising second page table information, the address conversion module is configured to: access the first page table information in the target conversion buffer to determine whether there is first target page table information matching the first virtual address conversion request in the first page table information; in response to the first target page table information not existing in the target conversion buffer, provide the first virtual address conversion request to the multi-level page table query module; the multi-level page table query module is configured to: receive the first virtual address conversion request provided by the address conversion module; determine whether there is second target page table information matching the first virtual address conversion request in the second page table information; and in response to the second target page table information not existing in the second page table information, obtain conversion information provided by an external memory, the conversion information being used to convert the object virtual address into the object physical address.

[0023] For example, in the address conversion device provided by some embodiments of the present disclosure, the first page table information comprises a plurality of page table entries, each page table entry corresponding to a physical page; the second page table information comprises a plurality of multi-level page tables, each multi-level page table comprising a plurality of page directory entries, each page directory entry being used to point to a physical address of a next-level page table; and each page directory entry in a last-level page table in the plurality of multi-level page tables is used to point to a page table entry in the first page table information.

[0024] For example, in the address conversion device provided by some embodiments of the present disclosure, the multi-level page table query module is configured to: based on the object virtual address and the base address, obtain a first page table read address of at least one page table in the multi-level page table; and based on the first page table read address, determine whether the second page table information exists second target page table information matching the first virtual address conversion request.

[0025] For example, in the address conversion device provided by some embodiments of the present disclosure, the multi-level page table query module includes a same read address merging unit and a conversion information cache unit, the same read address merging unit is configured to: in response to the second page table information not existing second target page table information matching the first virtual address conversion request, determine whether a merging signal is valid; in response to the merging signal being valid, compare whether the first page table read address and a second page table read address of a second virtual address conversion request located before the first virtual address conversion request are same; and in response to the first page table read address and the second page table read address being same, merge the first virtual address conversion request and the second virtual address conversion request, and wait for the conversion information provided by the external memory in response to the second virtual address conversion request, the conversion information cache unit is configured to: cache the conversion information, and in the case that the address conversion module is in an idle state, provide the conversion information to the address conversion module.

[0026] Some embodiments of the present disclosure also provide an electronic device, including: a processor; a memory including one or more computer program instructions; the one or more computer program instructions are stored in the memory and implemented by the processor to implement the address conversion method provided by any of the embodiments of the present disclosure.

[0027] For example, some embodiments of the present disclosure also provide a computer readable storage medium, which non-transitively stores computer readable instructions, when the computer readable instructions are executed by a processor, the address conversion method provided by any of the embodiments of the present disclosure is implemented. BRIEF DESCRIPTION OF DRAWINGS

[0028] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings described below only relate to some embodiments of the present disclosure, but not limit the present disclosure.

[0029] FIG. 1A shows a system schematic diagram of an address conversion device, a hardware access unit and an external memory connection;

[0030] FIG. 1B shows a schematic diagram of a 4-level page table structure;

[0031] FIG. 2A and FIG. 2B show a flowchart of the address conversion method provided by at least one embodiment of the present disclosure;

[0032] FIG. 3 shows a schematic block diagram of an address translation apparatus according to at least one embodiment of the present disclosure;

[0033] FIG. 4A shows a method flow diagram of step S202 in FIG. 2A according to at least one embodiment of the present disclosure;

[0034] FIG. 4B shows a schematic block diagram of an arbitration module in FIG. 3 according to at least one embodiment of the present disclosure;

[0035] FIG. 5 shows a schematic block diagram of an L2 TLB in FIG. 3 according to at least one embodiment of the present disclosure;

[0036] FIG. 6 shows a schematic diagram of a principle of querying a page table by a virtual address and a page table base address according to some embodiments of the present disclosure;

[0037] FIG. 7 shows a schematic block diagram of a multi-level page table querying module in FIG. 3 according to at least one embodiment of the present disclosure;

[0038] FIG. 8A shows a method flow diagram of step S204 in FIG. 2B according to at least one embodiment of the present disclosure;

[0039] FIG. 8B shows a schematic block diagram of an address translation performance monitoring module in FIG. 3 according to at least one embodiment of the present disclosure;

[0040] FIG. 8C shows a flow diagram of another address translation method according to at least one embodiment of the present disclosure;

[0041] FIG. 9 shows a schematic diagram of an address translation apparatus according to at least one embodiment of the present disclosure;

[0042] FIG. 10A is a schematic block diagram of an electronic device according to some embodiments of the present disclosure;

[0043] FIG. 10B is a schematic block diagram of another electronic device according to some embodiments of the present disclosure; and

[0044] FIG. 11 shows a schematic diagram of a storage medium according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0045] The technical solutions and advantages of the embodiments of the present disclosure will be described in detail below with reference to the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, rather than all the embodiments of the present disclosure. Based on the described embodiments of the present disclosure, all other embodiments obtained by a person of ordinary skill in the art without any inventive effort fall within the scope of protection of the present disclosure.

[0046] Unless otherwise defined, technical terms or scientific terms used in the present disclosure shall have the same meaning as commonly understood by one of ordinary skill in the art to which the present disclosure belongs. The terms "first", "second", and similar terms do not denote any order, quantity, or importance, but are used to distinguish different components. Also, the terms "one", "a", or "the" do not denote a quantity of particular mentioned elements, but rather denote the existence of at least one of the particular mentioned elements. The terms "include", "comprise", or "contain" or similar terms mean that the elements listed after the term encompass the elements recited therein and equivalent thereof, but do not exclude other elements. The terms "connected", "coupled", or similar terms do not limit to physical or mechanical connections or couplings, but can include electrical connections or couplings, whether direct or indirect. The terms "upper", "lower", "left", "right", and the like are used to indicate relative positions, and when the absolute positions of the described objects are changed, the relative positions can also be changed accordingly.

[0047] Fig. 1A shows a system diagram of an address translation apparatus, hardware access units and external memory connection; Fig. 1B shows a diagram of a 4-level page table structure.

[0048] As shown in Fig. 1A, the system includes an address translation apparatus 101, n hardware access units and an external memory 102. The address translation apparatus 101 is, for example, an MMU in a CPU. The n hardware access units include, for example, hardware access unit 1, hardware access unit 2,..., and hardware access unit n. The external memory 102 can include, for example, a physical memory.

[0049] An executing program can only use virtual memory addresses, and must be converted into physical memory addresses to access the corresponding data in the physical memory, and such conversion is necessary. Most mainstream address translation apparatuses complete the conversion of virtual addresses to physical addresses through a multi-level page table structure.

[0050] As shown in FIG. IB, the first three levels of page tables each store a page directory entry (PDE), which is used to obtain the physical address of the next level of page table. The first three levels of page tables include, for example, a first level page table PDE2, a second level page table PDE1, and a third level page table PDE0. The last level of page table (i.e., a fourth level page table PTE0) stores a page table entry (PTE). The PTE is used to obtain the actual physical address in memory. In this example, the complete address translation process requires reading four levels of page tables, and the page tables are usually stored in physical memory, so the entire address translation process has a large delay. Therefore, a translation lookaside buffer (TLB) is usually used by an address translation device to reduce the impact of read delay on performance. Each level of PDE and PTE in the multi-level page table structure has a corresponding TLB for storing the relevant page table information. If there is a PDE or PTE in the TLB that matches the virtual address translation request, it is called a “hit”, otherwise it is called a “miss”. If the TLB misses, the PDE or PTE information in the multi-level page table structure that matches the virtual address translation request needs to be read from the physical memory, and the TLB needs to be updated. If the TLB hits, the process of re-reading the PDE or PTE from the physical memory can be avoided, and the actual translation speed will be much faster. Therefore, the performance of the TLB is particularly important.

[0051] As shown in FIG. 1A, the address translation device 101 includes n first level (L1) TLBs, L1 TLB1, L1 TLB2, …, L1 TLBn, and a second level TLB (L2 TLB). The n first level TLBs and n hardware access units are one-to-one corresponding. The L2 TLB has a larger capacity than the L1 TLB, and can store more PTEs and PDEs. The address translation device 101 further includes a multi-level page table query module and a bus.

[0052] When any one of the hardware access units 1-n needs to do address translation, a virtual address translation request is sent to the corresponding L1 TLB. When the L1 TLB receives the virtual address translation request from the hardware access unit, it determines whether the L1 TLB is hit according to the virtual address in the virtual address translation request. If the L1 TLB is hit, the physical memory address is determined based on the physical address field in the hit L1 TLB and the offset of the corresponding virtual address, and then sent to the hardware access unit. If the L1 TLB is not hit, a page table read request is sent to the L2 TLB through the bus 121. If the L2 TLB is hit, it is transmitted to the L1 TLB through the bus 121, and then the physical memory address is determined by the L1 TLB according to the physical address field in the PTE and the offset of the corresponding virtual address, and then sent to the hardware access unit, while the L1 TLB is updated. If the L2 TLB is not hit, the virtual address and other information are sent to the multi-level page table query module 111. The multi-level page table query module 111 has M TLB modules for storing PDE and PTE information of an M-level page table structure, where M is an integer greater than or equal to 1. For example, for a 4-level page table structure, M = 4. When the multi-level page table query module 111 receives a virtual address translation request from the L2 TLB, it queries the PDE and PTE matching the virtual address translation request from the M TLB modules level by level. If there is no PDE or PTE information matching the virtual address translation request in the M TLB modules, a read request is sent to the external memory 102 to read the PDE or PTE information in the multi-level page table stored in the external memory 102, and the corresponding TLB is updated. When the PTE matching the virtual address translation request is found, the PTE is returned to the L2 TLB and the L1 TLB in turn, while the data of the L2 TLB and the L1 TLB is updated. The L1 TLB determines the physical memory address based on the physical address field in the matching PTE and the offset of the corresponding virtual address, and then sends it to the hardware access unit, thus ending the entire address translation process.

[0053] Currently, the data cached in the address translation device includes PTE and PDE. After the previous level TLB is not hit, it goes to the next level TLB to query level by level until the PTE matching the virtual address translation request is obtained. The physical memory page base address in the PTE is extracted, the corresponding offset in the virtual address is added, the actual physical address is obtained, and the physical address and other information are returned to the hardware access unit, while the data of the TLB not hit in the address translation device is updated.

[0054] The TLB capacity of the address translation apparatus 101 is limited. When a large number of threads are concurrently executed instantaneously, especially when the threads have irregular memory access patterns, the data stored in the TLB will be frequently replaced, and the hit rate of the TLB will be greatly reduced. In this case, the address translation apparatus 101 needs to frequently send a page table read request to the physical memory to read the PDE or PTE in the multi-level page table stored in the physical memory. A large number of read requests can cause serious congestion in the module between the address translation apparatus and the physical memory, and increase the delay of reading back the PDE or PTE. At this time, a faster processor core or higher physical memory can not help much, and increasing the TLB capacity of the address translation apparatus 101 can also cause problems such as increased chip area and increased power consumption.

[0055] Therefore, the current allocation of TLB cache resources is unreasonable, and when a large number of virtual address translation requests with irregular memory access patterns are encountered, the TLB resources cannot be fully utilized, the address translation efficiency is greatly reduced, the delay of the entire address translation process is increased, and the system performance is reduced.

[0056] The present disclosure provides an address translation method applied to an address translation apparatus. The address translation apparatus includes a plurality of sets of translation buffers, each set of translation buffers being configured to store first page table information used to convert a virtual address into a physical address. The method includes: in response to obtaining a first virtual address translation request, determining a target translation buffer from the plurality of sets of translation buffers according to a first mapping algorithm, the first virtual address translation request including an object virtual address; and accessing the first page table information in the target translation buffer to convert the object virtual address into an object physical address. The method further includes: obtaining access frequency information of each set of the plurality of sets of translation buffers; determining whether the first mapping algorithm needs to be updated according to the access frequency information; and in response to the first mapping algorithm needing to be updated, updating the mapping algorithm to a second mapping algorithm. The method can alleviate the uneven allocation of translation buffer resources for virtual address translation requests and improve the utilization rate of translation buffer resources.

[0057] FIGS. 2A and 2B show flowcharts of an address translation method provided by at least one embodiment of the present disclosure.

[0058] As shown in FIG. 2A, the address translation method includes steps S201 and S202. As shown in FIG. 2B, the address translation method includes steps S201 and S202, and further includes steps S203-S205. The address translation method shown in FIGS. 2A and 2B is applied to an address translation apparatus. The address translation apparatus includes a plurality of sets of translation buffers, each set of translation buffers including first page table information used to convert a virtual address into a physical address.

[0059] FIG. 3 shows a schematic block diagram of an address translation apparatus provided by at least one embodiment of the present disclosure.

[0060] As shown in FIG. 3, the address translation apparatus 300 includes an L2 TLB 310, for example, the L2 TLB 310 includes a plurality of sets of translation buffers. The address translation method shown in FIGS. 2A and 2B is applied to the address translation apparatus 300, for example, the address translation apparatus 300 can perform the address translation method shown in FIGS. 2A and 2B.

[0061] In some embodiments of the present disclosure, each set of the plurality of sets of translation buffers includes first page table information, for example, the first page table information includes a plurality of page table entries, each page table entry corresponds to a physical page. For example, the first page table information is the 4th level page table PTE0 shown in FIG. IB. The 4th level page table PTE0 includes a plurality of page table entries, each page table entry corresponds to an actual physical page. By querying the 4th level page table PTE0, a virtual address can be converted to an actual physical page.

[0062] Step S201: In response to obtaining a first virtual address translation request, determining a target translation buffer from the plurality of sets of translation buffers according to a first mapping algorithm, the first virtual address translation request includes an object virtual address.

[0063] Step S202: Accessing the first page table information in the target translation buffer to convert the object virtual address to an object physical address.

[0064] Step S203: Obtaining access frequency information of each set of the plurality of sets of translation buffers.

[0065] Step S204: According to the access frequency information, determining whether the first mapping algorithm needs to be updated.

[0066] Step S205: In response to the first mapping algorithm needing to be updated, updating the mapping algorithm to a second mapping algorithm.

[0067] The method enables the address translation apparatus to adaptively adjust the mapping algorithm when facing a large number of irregular virtual address translation requests, avoiding the situation that the virtual address translation request is only mapped to a single TLB, and ensuring the utilization rate of TLB resources.

[0068] For step S201, for example, the address translation apparatus 300 receives the first virtual address translation request provided by the hardware access unit 1 to the hardware access unit n.

[0069] The hardware access unit 1 to the hardware access unit n is, for example, a device in the CPU or GPU that needs to perform address translation, for example, can be a smart direct memory access controller (Smart Direct Memory Access, SDMA), a semaphore module (Semaphore, SEM), and a command processor extractor (Command Processor Fetcher, CPF), etc.

[0070] The first virtual address translation request comprises an object virtual address, which needs to be translated into an object physical address.

[0071] In some embodiments of the present disclosure, the first mapping algorithm is, for example, to determine the target translation buffer according to the object virtual address. The mapping algorithm for selecting the target translation buffer according to the object virtual address is calculated by taking a specified address range in the virtual address. For example, when the L2 TLB 310 contains 8 groups of translation buffers, the 26th-24th bits of the 48-bit virtual address can be used as the result of selecting the 8 groups of translation buffers. It should be noted that which 3 bits of the virtual address are selected as the selection bits of the target translation buffer can be changed according to the register configuration.

[0072] In some embodiments of the present disclosure, for example, a plurality of consecutive bits are selected as the selection bits of the target translation buffer, so that the plurality of groups of translation buffers can be uniformly queried.

[0073] As shown in FIG. 3, the address translation apparatus 300 further comprises an arbitration module 301. Step S201 is performed by the arbitration module 301, for example.

[0074] For step S202, the PTE in the target translation buffer is accessed to obtain the physical page corresponding to the object virtual address.

[0075] For example, step S202 comprises accessing the first page table information in the target translation buffer, determining whether there is a target page table entry in the first page table information that matches the object virtual address translation request; and in response to the target page table entry that matches the object virtual address translation request existing in the first page table information, determining the object physical address corresponding to the object virtual address based on the target page table entry and the page offset indicated by the object virtual address. For example, if there is a target page table entry (PTE) in the PTE0 in the target translation buffer that matches the object virtual address, the object physical address corresponding to the object virtual address is determined according to the target page table entry and the page offset indicated by the object virtual address. For example, some consecutive bits of the object virtual address indicate the page offset. For this embodiment, please refer to the description of FIG. 6.

[0076] For step S203, the access frequency information is represented by, for example, the number of accesses to the translation buffer within a preset time period. For example, the number of accesses to each group of the plurality of groups of translation buffers is counted to obtain the count value of each group of the plurality of groups of translation buffers within the preset time period.

[0077] For step S204, if the access frequency information indicates that the access frequencies of the multiple groups of translation buffers are quite different, the first mapping algorithm needs to be updated. For example, if the access frequency information indicates that the access frequencies of the multiple groups of translation buffers are not quite different, or the multiple groups of translation buffers are accessed uniformly, the first mapping algorithm does not need to be updated.

[0078] For step S205, if the first mapping algorithm needs to be updated, the first mapping algorithm is updated to the second mapping algorithm. The second mapping algorithm is different from the first mapping algorithm. For example, the first mapping algorithm and the second mapping algorithm have different specified address ranges. For example, the first mapping algorithm uses the 26th to 24th bits of a 48-bit virtual address to select 8 groups of translation buffers, while the second mapping algorithm uses the 24th to 22nd bits of the virtual address to select 8 groups of translation buffers.

[0079] As shown in FIG. 3, the address translation apparatus 300 further includes an address translation performance monitoring module 302. Steps S203 to S205 are performed by the address translation performance monitoring module 302, for example.

[0080] In some embodiments of the present disclosure, the address translation apparatus 300 further includes a multi-level page table query module 303. The multi-level page table query module 303 includes second page table information. The second page table information includes a multi-level page table, each level of the multi-level page table includes a plurality of page directory entries, and each page directory entry is used to point to a physical address of a next level of the multi-level page table. For example, the multi-level page table includes the first level page table PDE2, the second level page table PDE1, and the third level page table PDE0 shown in FIG. 1B. Each level of the multi-level page table includes a plurality of PDEs used to point to a physical address of a next level of the multi-level page table. Each page directory entry in the last level of the multi-level page table is used to point to a page table entry in the first page table information. For example, each page directory entry in the last level of the multi-level page table PDE0 is used to point to a page table entry in the first page table information PTE0.

[0081] In some embodiments of the present disclosure, the address translation apparatus 300 further includes a register configuration module 304. The register configuration module 304 is configured to perform register configuration on registers of the L2 TLB 310, the arbitration module 301, the multi-level page table query module, and the address translation performance monitoring module 302, for example, to provide register configuration values. For example, the register configuration module sets a value of a register configuration of the mapping algorithm of the arbitration module 301, so as to set the mapping algorithm to the second mapping algorithm. The register configuration module performs register configuration on a monitoring period in the address translation performance monitoring module 302, and the like.

[0082] FIG. 4A shows a method flowchart of step S202 in FIG. 2A according to at least one embodiment of the present disclosure.

[0083] As shown in FIG. 4A, step S202 can include steps S212-S242.

[0084] Step S212: Accessing the first page table information in the target translation buffer, and determining whether the first target page table information matching the first virtual address translation request exists in the first page table information.

[0085] Step S222: In response to the first target page table information not existing in the target translation buffer, providing the first virtual address translation request to the multi-level page table query module.

[0086] Step S232: Determining whether the second target page table information matching the first virtual address translation request exists in the second page table information.

[0087] Step S242: In response to the second target page table information not existing in the second page table information, converting the object virtual address into the object physical address based on the conversion information provided by the external memory.

[0088] For step S212, for example, accessing the PTE in the target translation buffer, and determining whether the object virtual address hits the PTE in the target translation buffer. If the object virtual address hits the PTE in the target translation buffer, the hit PTE is the first target page table information, i.e., the first target page table information indicates the physical page where the object virtual address is located. If the object virtual address does not hit the PTE in the target translation buffer, step S222 is performed.

[0089] For step S222, for example, if the object virtual address does not hit the PTE in the target translation buffer, the L2 TLB 310 provides the first virtual address translation request to the multi-level page table query module 303.

[0090] For step S232, for example, determining whether the object virtual address hits the 1st level page table PDE2, the 2nd level page table PDE1 and the 3rd level page table PDE0 in the multi-level page table query module 303.

[0091] In some embodiments of the present disclosure, step S232, for example, includes: based on the object virtual address and the base address, obtaining a first page table read address of at least one level page table in the multi-level page table; and based on the first page table read address, determining whether the second target page table information matching the first virtual address translation request exists in the second page table information.

[0092] The base address is configured, for example, by configuring the value of a base address register in the register configuration module 304. The base address in the register configuration module 304 specifies the starting address of the first level page table in the physical memory. The data field stored in the first level page table PDE2 (as the second level page table PDE1 page table physical base address) specifies the starting address of the second level page table PDE1 in the physical memory, the data field stored in the second level page table PDE1 (as the third level page table PDE0 page table physical base address) specifies the starting address of the third level page table PDE0 in the physical memory, the data field stored in the third level page table PDE0 (as the fourth level page table PTE0 page table physical base address) specifies the starting address of the fourth level page table PTE0 in the physical memory, and the data field stored in the fourth level page table specifies the starting address of the page pointed to by the PTE in the physical memory.

[0093] In some embodiments of the present disclosure, the level of the page table from which to start the query can also be configured by the register configuration module 304, i.e., the page table from which to start the query is configured. For example, the register configuration module 304 is set to start the query from the first level page table PDE2. For example, the multi-level page table query module 303 queries according to the register configured base address plus the 47th to 39th bits of the virtual address as the first level page table PDE2 read address to the PDE2 cache resource; if a match is successful, the 2nd level page table PDE1 page table read address is queried according to the matched first level page table PDE2 field (indicating the second level page table PDE1 physical address field) plus the 38th to 30th bits of the virtual address to the second level page table PDE1 cache resource. If a match is not successful in the first level page table PDE2 cache resource, the PDE2 data corresponding to the read address is read from the physical memory according to the first level page table PDE2 page table read address.

[0094] In the above example, the sum of the 47th to 39th bits of the object virtual address and the base address in the register configuration module 304 is used as the read address of the first level page table PDE2 (an example of the first page table read address). If the read address of the first level page table PDE2 does not hit the first level page table PDE2, it is determined that the second page table information does not exist that matches the second target page table information of the first virtual address conversion request. If the read address of the first level page table PDE2 hits the first level page table PDE2, it is queried whether it hits in the second level page table PDE1 cache resource according to the sum of the matched first level page table PDE2 field and the 38th to 30th bits of the virtual address as the second level page table PDE1 page table read address, and if it does not hit, it is determined that the second page table information does not exist that matches the second target page table information of the first virtual address conversion request. This is successively applied until the third level page table PDE0 is matched, it is determined that the second page table information exists that matches the second target page table information of the first virtual address conversion request, and the page table information in the third level page table PDE0 that matches the object virtual address is the second target page table information.

[0095] For step S242, if the object virtual address does not hit the multi-level page table query module 303, a first virtual address conversion request is provided to an external memory to obtain conversion information for converting the object virtual address into an object physical address from the external memory. The external memory is, for example, the physical memory shown in FIG. 3. For example, a complete 4-level page table is stored in the physical memory, and the 4-level page table is, for example, the structure shown in FIG. IB. The conversion information obtained by the physical memory in response to the first virtual address conversion request is, for example, a PTE that hits the object virtual address, i.e., a target page table entry that matches the object virtual address.

[0096] In some embodiments of the present disclosure, step S242 can obtain the conversion information according to whether the merge request signal is valid. For this embodiment, please refer to the description of the multi-level page table query module 303 in FIG. 7 below.

[0097] The following describes a specific implementation of the address conversion method provided by the present disclosure in combination with the embodiment of FIG. 3.

[0098] As shown in FIG. 3, the address conversion device 300 can process virtual address conversion requests of n hardware access units (for example, hardware access unit 1 to hardware access unit n), and the virtual address conversion request includes a virtual address, a hardware access unit identifier, and other key information. n is an integer greater than or equal to 1. In some embodiments of the present disclosure, n first-level TLBs can be arranged in each hardware conversion unit, as shown in FIG. 3. Hardware access unit 1 to hardware access unit n each include a first-level (L1) TLB. In other embodiments of the present disclosure, n first-level TLBs can be arranged in the address conversion device 300, as shown in the structure of FIG. 1A. Embodiments of the present disclosure do not limit the first-level TLB.

[0099] The arbitration module 301 is configured to receive the virtual address conversion requests from the n hardware access units into a cache inside the arbitration module 301, and sequentially process the virtual address conversion requests through an arbitration algorithm. The processing process includes determining which group (i.e., a target TLB) in the k groups of TLBs inside the L2 TLB 310 the virtual address conversion request maps to through a mapping algorithm, and determining a target TLB address index and comparison tag information according to the virtual address, and sending these information and the virtual address conversion request to the L2 TLB 310; after receiving the virtual address conversion result returned from the L2 TLB 310, sending the virtual address conversion result to the corresponding hardware access unit according to the hardware access unit identifier in the virtual address conversion result. n and k are integers greater than or equal to 1.

[0100] The arbitration module 301 selects the target TLB mapping algorithm based on the virtual address by calculating and obtaining a specified address range from the virtual address. For example, when the L2 TLB 310 contains 8 TLBs, bits 26 to 24 of the 48-bit virtual address can be used as the result of selecting 8 TLBs. Which 3 bits of the virtual address are selected can be changed according to the register configuration; selecting 3 consecutive bits of the address as the target TLB selection bits allows consecutive virtual addresses to be evenly queried from the 8 TLBs.

[0101] Arbitration module 301 obtains the index bit of the target TLB based on a specified address range in the virtual address. For example, when the target TLB depth is 64, bits 20 to 15 of the 48-bit virtual address can be used as the index bit of the target TLB. The selection of which 6 bits of the virtual address to use can be changed according to register configuration. The value of the index bit is used to query PTE data at the target TLB depth of index for matching. Whether a match is found is determined by tag comparison; arbitration module 301 obtains tag information based on a specified address range in the virtual address. For example, bits 47 to 12 of the 48-bit virtual address can be used as the tag value and sent to L2 TLB 310 for comparison with the tag value at the target TLB depth of index; if they are the same, the match is successful; otherwise, the match fails.

[0102] Figure 4B shows a schematic block diagram of an arbitration module in Figure 3 provided in at least one embodiment of the present disclosure.

[0103] As shown in Figure 4B, the arbitration module 301 includes a conversion request input arbitration module 311, a conversion result output arbitration module 321, n hardware input FIFO buffers, and n hardware output FIFO buffers. Each of the n hardware input FIFO buffers corresponds one-to-one with one of the n hardware access units, and each of the n hardware output FIFO buffers also corresponds one-to-one with one of the n hardware access units. For example, the n hardware input FIFO buffers include hardware input FIFO buffers 1 through n. Similarly, the n hardware output FIFO buffers include hardware output FIFO buffers 1 through n.

[0104] The hardware x input FIFO buffer is used to buffer virtual address translation requests from hardware access unit x, where x is an integer greater than or equal to 1 and less than or equal to n.

[0105] The conversion request input arbitration module 311 is configured to process the virtual address conversion request, for example, by using a Round-Robin scheduling algorithm to determine whether the n hardware input FIFO buffers are empty in sequence. If not, the virtual address conversion request (an example of the first virtual address conversion request) in the hardware input FIFO buffer is read for processing, the target TLB, tag, and index information corresponding to the virtual address are calculated through a virtual address and TLB mapping algorithm, and the above information and the virtual address conversion request are sent to the L2 TLB 310 module. The TLB mapping algorithm can be adjusted through the register configuration module 304. For details of the Round-Robin scheduling algorithm, please refer to the related materials in the art, which will not be described here. It should be noted that other scheduling algorithms in the art can also be used to determine whether the n hardware input FIFO buffers are empty in sequence. The present disclosure does not limit the scheduling algorithm, and a person skilled in the art can select a suitable scheduling algorithm according to the needs.

[0106] The conversion result output arbitration module 321 is configured to receive the virtual address conversion result from the L2 TLB 310, and send the virtual address conversion result to the corresponding hardware x output FIFO buffer through the hardware access unit identifier in the virtual address conversion result.

[0107] The hardware x output FIFO buffer is configured to buffer the virtual address conversion result of the hardware access unit x, and send the virtual address conversion result to the hardware access unit x when the hardware access unit x is in an "idle" state, where x is an integer greater than or equal to 1 and less than or equal to n.

[0108] FIG. 5 shows a schematic block diagram of the L2 TLB in FIG. 3 according to at least one embodiment of the present disclosure.

[0109] As shown in FIG. 5, the L2 TLB 310 includes k TLB input buffers, k sets of TLBs, a PTE checking unit 312, an address conversion unit 322, and a virtual address conversion result output buffer 332. The k TLB input buffers correspond to the k sets of TLBs one-to-one, and k is an integer greater than or equal to 1. The k TLB input buffers are respectively a TLB1 input buffer, a TLB2 input buffer,..., and a TLBk input buffer, and the k sets of TLBs include respectively a TLB1, a TLB2,..., and a TLBk.

[0110] The L2 TLB 310 includes, for example, k sets of TLBs, each of which is used to store PTE data in the last level of a M-level page table structure; where M and k are integers greater than or equal to 1; for example, if the M-level page table structure is a 3-level page table structure, then each of the k sets of TLBs stores PTE data in the third level of the page table structure; if the M-level page table structure is a 4-level page table structure, then each of the k sets of TLBs stores PTE data in the fourth level of the page table structure. Placing all the cache resources for storing PTEs in the L2 TLB module can improve the L2 TLB query hit rate, and such a design can more reasonably utilize PTE cache resources and improve address translation efficiency.

[0111] For example, the k sets of TLB input caches can adopt a set-associative cache structure or a full-associative cache structure. The set-associative cache structure and the full-associative cache structure can be referred to related materials in the art, and will not be described herein.

[0112] The TLBy input cache is used to cache a virtual address translation request from the arbitration module 301 and targeted at TLB y, where y is an integer greater than or equal to 1 and less than or equal to k. The virtual address translation request includes a virtual address, a hardware access unit identifier, target TLB information, index, and tag information, and the like.

[0113] The TLBy is used to take a virtual address translation request from the TLBy input cache and perform matching in the TLBy, where y is an integer greater than or equal to 1 and less than or equal to k. For example, the TLBy finds the tag saved in the index row in the TLBy according to the index in the virtual address translation request, and compares the tag with the tag in the virtual address translation request; if they are the same, the matching is successful, and the PTE data saved in the index row in the TLBy is sent to the PTE checking unit; if they are not the same, the TLBy is not hit, and the virtual address translation request is sent to the multi-level page table query module 303.

[0114] The PTE checking unit 312 is used to perform error checking on the PTE hit by the k sets of TLBs and the PTE returned from the multi-level page table query module 303. The PTE checking unit 312 determines whether the matched PTE can be used as a normal PTE by checking specific field information in the PTE. For example, if the valid bit (V bit) of the PTE is not valid, it means that the PTE is invalid and cannot be used as a normal PTE. In this case, the default address configured by the register is sent to the address translation unit as the physical address field of the PTE, and an error indication signal is pulled high to indicate that the virtual address translation result is problematic. If the V bit of the PTE is valid, the physical address field information of the PTE is sent to the address translation unit 322.

[0115] The address conversion unit 322 reads the physical address information in the PTE field from the PTE checking unit 312, adds the corresponding offset in the virtual address to the physical address information to obtain the physical memory address corresponding to the virtual address conversion request, and sends the physical memory address, the virtual address, and the hardware access unit identifier as the virtual address conversion result to the virtual address conversion result output buffer 332.

[0116] The virtual address conversion result output buffer 332 is used to store the virtual address conversion result. When the arbitration module 301 is in the "idle" state, the virtual address conversion result output buffer 332 sends the virtual address conversion result to the arbitration module 301.

[0117] For example, the L2 TLB 310 is used to receive the virtual address conversion request from the arbitration module 301, compare the tag in the virtual address conversion request with the tag information stored in the index row in the target TLB according to the target TLB, index, and tag information in the virtual address conversion request, and if the tag in the virtual address conversion request is the same as the tag information stored in the index row, a match is successful, the PTE data stored in the index row is read, and after the PTE data is checked, it is sent to the address conversion unit 322 in the L2 TLB 310. The address conversion unit 322 reads the physical address field in the PTE, adds the corresponding offset in the virtual address to obtain the physical memory address corresponding to the virtual address conversion request. The physical memory address, the virtual address, and the hardware access unit identifier are sent to the arbitration module 301 as the virtual address conversion result. If the tag in the virtual address conversion request is not the same as the tag information stored in the index row, a match is not successful, and the virtual address conversion request is sent to the multi-level page table query module 303. The multi-level page table query module 303 returns the PTE matched by the virtual address request, the virtual address, the hardware access unit identifier, the target TLB information, the index, and the tag information to the L2 TLB 310. The L2 TLB 310 updates the PTE data and the tag data in the index row in the target TLB according to the target TLB information and the index, and at the same time, the L2 TLB 310 sends the returned PTE data, the virtual address, and the hardware access unit identifier to the address conversion unit 322 after being checked by the PTE checking unit 312. The address conversion unit 322 calculates the physical memory address and sends it, together with the virtual address and the hardware access unit identifier, to the arbitration module 301 as the virtual address conversion result.

[0118] The multi-level page table query module 303 is configured to cache PDE data of other levels of page tables except the last level of page table in the M-level page table structure. For example, in the four-level page table structure shown in FIG. 1B, the multi-level page table query module 303 caches the data of PDE2, PDE1 and PDE0. When the multi-level page table query module 303 receives a virtual address translation request from the L2 TLB 310, it queries the PDE data cached in the module level by level. If no matching PDE data of the corresponding level is found, the multi-level page table query module 303 needs to determine the address of the target PDE in the physical memory based on the virtual address offset and the target level page table base address, read the target PDE from the physical memory, and update the TLB data based on the read PDE data. Until the PDE0 data is found, the multi-level page table query module 303 reads the PTE data from the physical memory based on the PTE table base address information in the PDE0 and the corresponding offset of the virtual address, and writes the PTE data back to the L2 TLB 310.

[0119] If M is an integer greater than or equal to 2, the multi-level page table query module 303 is further configured to determine whether the matched PDE item can be used as a PTE directly when querying the PDE data. For example, a bit of the PDE is selected as a flag bit. When the flag bit is valid, the PDE can be used as a PTE. If the flag bit is invalid, the next level of page table needs to be queried. When the PDE can be used as a PTE directly, the PDE is returned to the L2 TLB 310 as PTE data. The physical address in the PDE field is directly used as the physical memory page base address. The physical address obtained by adding the corresponding offset of the virtual address is the actual physical address after the virtual address translation.

[0120] It is considered that not all virtual address translation requests are based on the M-level page table for address translation even in the M-level page table structure. For example, M is 4. In the four-level page table structure shown in FIG. 1B, some requests are based on only the first level of page table structure, i.e., only the PTE page table in FIG. 1B for virtual address to physical address translation. In this case, when the L2 TLB 310 is not hit, it is not necessary to query the PDE page table in the multi-level page table query module 303. The multi-level page table query module 303 can directly send a physical memory read request to the physical memory to read the matching PTE data. Some requests are based on the second level of page table structure, i.e., only the PDE0 page table and the PTE page table in FIG. 1B. In this case, when the L2 TLB 310 is not hit, the multi-level page table query module 303 directly queries whether the PDE0 page table is cached in the TLB resource, and does not need to query the PDE2 page table and the PDE1 page table. The multi-level page table query module 303 can determine the level of the PDE page table (target level PDE page table) from which the query starts through register configuration.

[0121] FIG. 6 shows a schematic diagram of a principle of querying a page table through a virtual address and a page table base address in a four-level page table structure according to some embodiments of the present disclosure.

[0122] For example, in the four-level page table in FIG. 6, the PDE2 data is stored in the first-level page table, the PDE1 data is stored in the second-level page table, the PDE0 data is stored in the third-level page table, and the PTE data is stored in the fourth-level page table.

[0123] FIG. 6 shows the offset meanings represented by the fields of the virtual address under the four-level page table structure. The bits 47-39 of the virtual address represent the offset in the first-level page table in the four-level page table, the bits 38-30 represent the offset in the second-level page table in the four-level page table, the bits 29-21 represent the offset in the third-level page table in the four-level page table, the bits 20-12 represent the offset in the fourth-level page table in the four-level page table, and the bits 11-0 represent the intra-page offset of the page pointed to by the PTE. The field of the virtual address added in the address conversion unit in the L2 TLB 310 is the bits 11-0 of the virtual address, and the actual physical memory address is obtained.

[0124] If the register configuration requires querying from the PDE2 cache at this time, the multi-level page table querying module 303 queries in the PDE2 cache resource according to the register configured base address and the bits 47-39 of the virtual address as the PDE2 page table read address. If the PDE2 cache resource is matched successfully, the PDE1 page table read address is added to the PDE1 cache resource according to the PDE1 page table physical address field in the matched PDE2 field and the bits 38-30 of the virtual address. If the PDE2 cache resource is not matched successfully, the PDE2 data corresponding to the read address is read from the physical memory according to the PDE2 page table read address. The offset of the virtual address corresponding to the remaining page tables is used in a similar manner, which is not described herein. The register configured base address specifies the start address of the first-level page table in the physical memory, the PDE1 page table physical base address in the PDE2 data field stored in the first-level page table specifies the start address of the second-level page table in the physical memory, the PDE0 page table physical base address in the PDE1 data field stored in the second-level page table specifies the start address of the third-level page table in the physical memory, the PTB page table physical base address in the PDE0 data field stored in the third-level page table specifies the start address of the fourth-level page table in the physical memory, and the physical address field in the PTE data field stored in the fourth-level page table specifies the start address of the page pointed to by the PTE in the physical memory.

[0125] FIG. 7 shows a schematic block diagram of the multi-level page table querying module in FIG. 3 according to at least one embodiment of the present disclosure.

[0126] As shown in FIG. 7, the multi-level page table query module 303 includes a virtual address translation request cache module 313, a translation information cache module 323, a virtual address translation request query selection module 333, a PDE2 cache TLB, a PDE1 cache TLB, a PDE0 cache TLB, and a same read address merging module 343. The PDE2 cache TLB, the PDE1 cache TLB, and the PDE0 cache TLB are, for example, in a set-associative cache structure or in a fully-associative cache structure.

[0127] In some embodiments of the present disclosure, the multi-level page table query module 303 can merge, through the same read address merging module 343, page table read requests with the same read address sent to the physical memory, where the page table read request includes a page table read address of a virtual address translation request, a virtual address, and a hardware access unit identifier providing the virtual address translation request, etc. The hardware access unit identifier is, for example, a number of a hardware access unit. The page table read address is obtained based on a base address and page directory entry data of at least one level of page table in the multi-level page table. The page table read address is, for example, a sum of a register-configured base address and page directory entry data in the PDE2 of the first level page table. For another example, the page table read address is, for example, page directory entry data in the PDE1 obtained based on a sum of a register-configured base address and page directory entry data in the PDE2 of the first level page table.

[0128] Step S242 can obtain the translation information according to whether the merging request signal is valid. For example, in response to the second page table information not having the second target page table information matching the first virtual address translation request, it is determined whether the merging signal is valid; in response to the merging signal being valid, it is compared whether the first page table read address is the same as a second page table read address of a second virtual address translation request located before the first virtual address translation request; in response to the first page table read address being the same as the second page table read address, the first virtual address translation request is merged with the second virtual address translation request, and the address translation device waits for the translation information provided by the external memory in response to the second virtual address translation request; and the object virtual address is converted into the object physical address based on the translation information. This embodiment can effectively merge the same read address requests in the requests initiated by the address translation device to the physical memory, and optimize the congestion problem without reducing the hit rate of the virtual address translation request of the address translation device.

[0129] For example, if the second target page table information matching the object virtual address does not exist in the multi-level page table query module 303, it is determined whether the merging signal in the same read address merging module 343 is valid.

[0130] For example, after the multi-level page table query module 303 sends a page table read request to the physical memory, the same read address merging module 343 records the page table read address data, the virtual address, and the hardware access unit identifier corresponding to the read request, and makes the merging signal valid. When sending the next page table read request (an example of the first page table read address of the first virtual address conversion request) to the physical memory, if the merging signal is valid, the page table read address in the page table read request is compared with the page table read address in the previous page table read request (an example of the second page table read address of the second virtual address conversion request).

[0131] If the page table read request is consistent with the previous page table read address, the merging signal, the virtual address, and the hardware access unit identifier are sent to the virtual address conversion request query selection module 333, and the page table read request is no longer sent to the physical memory, and the conversion information provided by the physical memory in response to the second virtual address conversion request is waited for.

[0132] In some embodiments of the present disclosure, in response to the first page table read address and the second page table read address being different, the page table read request based on the first virtual address conversion request is provided to the external memory to obtain conversion information from the external memory; and the merging signal is updated to be invalid. For example, if the page table read request in the above embodiment is inconsistent with the previous page table read address, the page table read request is sent to the physical memory, and the merging signal is made invalid.

[0133] In some embodiments of the present disclosure, in response to the second page table information not existing the second target page table information matching the first virtual address conversion request, converting the object virtual address into the object physical address based on the conversion information provided by the external memory further includes: in response to receiving the conversion information provided by the external memory in response to the second virtual address conversion request, updating the merging signal to be invalid.

[0134] In this embodiment, for example, the merging signal is pulled low (i.e., updated to be invalid) as soon as data is fed back from the physical memory. Because when the data comes back, it is necessary to determine which requests are merged, and the read data is given to these merged requests, so that subsequent virtual address conversion requests can be issued.

[0135] For example, the PDE2 cache TLB in the multi-level page table query module 303 needs to send 3 same page table read addresses and 1 different page table read address to the physical memory through the same read address merging module 343. When the PDE2 cache TLB sends the first page table read request to the same read address merging module 343, the merging signal is invalid, at this time the same read address merging module 343 records the page table read address of the first page table read request and sends the page table read request to the physical memory, and makes the merging signal valid. When the PDE2 cache TLB sends the second page table read request to the same read address merging module 343, the same read address merging module 343 judges whether the merging signal is valid, at this time the merging signal is valid, then the same read address merging module 343 compares the page table read address of the request with the page table read address of the first page table read request, and finds that they are the same, then sends the merging signal, the virtual address and the hardware access unit identifier to the virtual address conversion request query selection module 333. If the PDE2 cache TLB sends the third page table read request to the same read address merging module before the first page table read request reads back the PDE or PTE data from the physical memory, the same read address merging module 343 judges whether the merging signal is valid at this time, and if valid, the merging signal is invalid. At this time, when the PDE2 cache TLB sends the third same page table read request to the same read address, since the merging signal is invalid, the page table read request is sent to the physical memory, and the address merging signal is valid. When the PDE2 cache TLB sends the fourth page table read request to the same read address merging module 343, since the merging signal is valid, at this time it is needed to judge whether the page table read request address is the same as the recorded page table read request address, and if not the same, the merging signal is invalid, and the page table read request is sent to the physical memory. If the PTE or PDE data has not been returned before the third page table read request is sent, the same read address merging module 343 merges the first page table read request, the second page table read request and the third page table read request.

[0136] The virtual address conversion request cache module 313 is used for caching the virtual address conversion request from the L2 TLB 310.

[0137] The virtual address translation request query selection module 333 is used to process the virtual address translation request. After obtaining the virtual address translation request data from the virtual address translation request, the virtual address translation request query selection module 333 determines, according to the register configuration, from which level of PDE cache TLB the virtual address translation request starts to match. Taking the PDE2 cache TLB as an example, the virtual address translation request query selection module 333 first obtains the PDE2 page table read address by adding the base address of the register configuration to the 47th to 39th bits of the virtual address; then obtains the index and tag of the PDE2 cache TLB according to the specified address range in the PDE2 page table read address. For example, when the depth of the target TLB is 128, the 12th to 6th bits of the 48-bit PDE2 read address can be used as the index of the PDE2 cache TLB, and the 47th to 6th bits can be used as the tag. The specific selection of which bits of the PDE2 read address as the index and tag can be changed according to the register configuration. After calculating the PDE2 read address, the index and the tag, the virtual address, and the hardware access unit identifier are sent to the PDE2 cache TLB. The virtual address translation request query selection module 333 receives the PDE2 data returned from the physical memory or the PDE2 data from the PDE2 cache TLB. If the virtual address translation request query selection module 333 receives the PDE2 data returned from the physical memory, the PDE2 data and the corresponding PDE2 cache TLB index and tag information are sent to the PDE2 cache TLB to update the data in the PDE2 cache TLB.

[0138] The virtual address translation request query selection module 333 determines whether the PDE2 data can be used as a PTE in response to receiving the PDE2 data returned from the PDE2 cache TLB or the physical memory. If the PDE2 data can be used as a PTE, the PDE2 data and the corresponding virtual address and hardware access unit identifier are sent to the translation information cache module 323. If the PDE2 data cannot be directly used, the PDE1 read address is obtained by adding the PDE1 page table physical base address field information in the PDE2 data to the 38th to 30th bits of the virtual address, and the index and tag of the PDE1 cache TLB corresponding to the virtual address translation request are calculated according to the PDE1 read address. The subsequent process is similar to the above process; until the PTE is read back from the physical memory, the PTE data and the virtual address and hardware access unit identifier matched with the PTE data (including the combined valid virtual address and hardware access unit identifier) are sent to the translation information cache module 323.

[0139] The PDE2 cache TLB, the PDE1 cache TLB and the PDE0 cache TLB are configured to receive PDE read requests and PDE write requests from the virtual address translation request query selection module 333. The PDE read requests include a PDE read address, an index, a tag, a virtual address, a hardware access unit identifier and the like. The index and the tag are matched in the cache TLB. If the matching is successful, the PDE data, the virtual address and the hardware access unit identifier are sent to the virtual address translation request query selection module 333. If the matching is unsuccessful, i.e., a miss, the page table read address, the virtual address and the hardware access unit identifier are sent to the same read address merging module 343. The PDE write requests are used to update the PDE cache TLB with the PDE data read from the physical memory in the case of a miss in the PDE cache TLB.

[0140] The same read address merging request module 343 is configured to determine whether the page table read requests from the PDE cache TLB can be merged. If the page table read requests can be merged, the merged virtual address and the hardware access unit identifier are sent to the virtual address translation request query selection module 333. If the page table read requests cannot be merged, the page table read requests are sent to the physical memory. In some embodiments of the present disclosure, the merging function can be enabled or disabled by a register, for example.

[0141] The translation information cache module 323 is configured to receive the PTE data and the corresponding virtual address, the hardware access unit identifier and the like queried by the virtual address translation request query selection module 333. When the L2 TLB 310 is in an "idle" state, the data are sent to the L2 TLB 310.

[0142] In some embodiments of the present disclosure, the multi-level page table query module comprises a same read address request merging module and a virtual address conversion request query selection module; after the multi-level page table query module sends a page table read request to the physical memory, the same read address merging module records the page table read address data and the virtual address corresponding to the read request, and the hardware access unit identifier, and makes the merging valid signal valid; when sending the next page table read request to the physical memory, if the merging valid signal is valid, the page table read request is compared with the previous page table read address. If the page table read request is consistent with the previous page table read address, the merging valid signal, the virtual address and the hardware access unit identifier are sent to the virtual address conversion request query selection module in the multi-level page table query module, and the page table read request is not sent to the physical memory; if the page table read address is not consistent with the previous page table read address, the page table read request is sent to the physical memory, and the merging valid signal is invalidated. After the matching PTE is read back from the physical memory, the virtual address conversion request arbitration module sends all virtual address conversion request information (including the merged virtual address conversion request) matching the PTE to the L2 TLB module, so that the same read address request in the request initiated by the address conversion module to the physical memory can be effectively merged, and the congestion problem is optimized without reducing the virtual address conversion request hit rate of the address conversion module.

[0143] It should be noted that in the above embodiment, the multi-level page table query module does not comprise a cache for storing the PTE page table, but a cache structure for storing the PTE page table can also be added to the multi-level page table query module as in the structure of FIG. 1A.

[0144] FIG. 8A shows a method flowchart of step S204 in FIG. 2B according to at least one embodiment of the present disclosure.

[0145] As shown in FIG. 8A, step S204 comprises steps S214-S244.

[0146] Step S214: based on the count value of each group of the multi-group conversion buffer, calculate the average access value of the count value of the multi-group conversion buffer.

[0147] Step S224: obtain the allowed access deviation.

[0148] Step S234: based on the allowed access deviation and the average access value, calculate the effective access rate of the multi-group conversion buffer.

[0149] Step S244: based on the effective access rate, determine whether the first mapping algorithm needs to be updated.

[0150] The method described in FIG. 8A will be described below in conjunction with FIG. 8B.

[0151] FIG. 8B shows a schematic block diagram of the address translation performance monitoring module of FIG. 3, according to at least one embodiment of the present disclosure.

[0152] The address translation performance monitoring module 302 is configured to record the number of accesses of each of the k TLBs of the L2 TLB module in a fixed clock period, and determine whether to adjust the TLB mapping algorithm in the arbitration module 301 according to an adjustment algorithm, and adaptively adjust the TLB mapping algorithm. The TLB mapping algorithm includes, for example, a first mapping algorithm and a second mapping algorithm.

[0153] As shown in FIG. 8B, the address translation performance monitoring module 302 includes k TLB access counters and a TLB mapping algorithm adjustment module 312. Each of the k TLB access counters is, for example, a 48-bit counter, or a counter of other bit number. The k TLB access counters include, for example, a TLB1 access counter, a TLB2 access counter, …, and a TLBk access counter.

[0154] The TLBx access counter is configured to record the access of the TLBx in the L2 TLB module, where x is less than or equal to k and greater than or equal to 1. For example, at the rising edge of each clock, if the TLBx access enable from the arbitration module 301 is valid, the TLBx access counter is incremented by 1.

[0155] In some embodiments of the present disclosure, other types of counters can be included in the address translation performance monitoring module, such as counters for address translation latency, specific PTE error types, TLB miss counters, etc.

[0156] For step S214, the k TLB access counters are used to count the accesses of the k TLBs, respectively, to obtain the count value of each of the k TLBs.

[0157] The TLB mapping algorithm adjustment module 312 is configured to determine whether to adjust the mapping algorithm according to the count value of the TLB access counter, and adaptively adjust the TLB mapping algorithm when the adjustment of the mapping algorithm is needed.

[0158] For example, the TLB mapping algorithm adjustment module 312 reads the count value of the k TLB access counters every F clocks, and calculates the average access value Ave_tlb of the k TLBs in the F clocks, while clearing the count value of the k TLB access counters. The average access value Ave_tlb can be calculated according to the following formula, for example.

[0159] Ave_tlb = (N TLB0 +N TLB1 +…+N TLBk ) / k, N TLBx represents the count value of the TLBx access counter.

[0160] For step S224, for example, the access allowance deviation is Δ, the access allowance deviation can be set by those skilled in the art as needed, and the disclosure does not limit the value of the access allowance deviation.

[0161] For step S234, for example, it includes: based on the access allowance deviation, calculating the access deviation value of each group of the plurality of groups of translation lookaside buffers; based on the access deviation value, calculating the effective utilization indication value of each group of the plurality of groups of translation lookaside buffers; and taking the average value of the effective utilization indication values of the plurality of groups of translation lookaside buffers as the effective access rate.

[0162] For example, the access deviation value n allowed for each group of TLB is calculated by the following formula: Δ n Δ = Ave_tlb x Δ

[0163] For example, for each group of the plurality of groups of translation lookaside buffers, in response to the sum of the access deviation value and the count value being greater than or equal to the average access value, the effective utilization indication value of the translation lookaside buffer is set to a first preset value, and in response to the sum of the access deviation value and the count value being less than the average access value, the effective utilization indication value of the translation lookaside buffer is set to a second preset value. For example, the first preset value is 1, and the second preset value is 0.

[0164] If N TLBx +n Δ ≥ Ave_tlb, then the effective utilization indication value E TLBx of the TLBx is 1, otherwise it is 0. Next, for example, the average value of the TLB effective utilization indication values can be calculated as the effective access rate TLB_usaget by the following formula. TLB_usaget = (E TLB0 +E TLB1 +…+E TLBk ) / k

[0165] For step S244, for example, in response to the effective access rate TLB_usaget being greater than or equal to a preset access rate, it is determined that the first mapping algorithm does not need to be updated; in response to the effective access rate TLB_usaget being less than the preset access rate, it is determined that the first mapping algorithm needs to be updated.

[0166] When TLB_usaget ≥ α, the first mapping algorithm does not need to be updated, and the arbitration module 301 still selects the target translation lookaside buffer according to the first mapping algorithm, α is a preset access rate, 0 < α ≤ 1, and different values can be set according to the value of k. When TLB_usaget < α, the first mapping algorithm needs to be updated to the second mapping algorithm, and the arbitration module 301 selects the target translation lookaside buffer according to the second mapping algorithm.

[0167] For example, the TLB mapping algorithm adjustment module 312 sends the mapping algorithm of the selected target register in the arbitration module 301 and the related register configuration adjustment information to the register configuration module 304.

[0168] In some embodiments of the present disclosure, the first mapping algorithm comprises determining the target translation buffer according to the first target bit of the object virtual address in the virtual address translation request, and the second mapping algorithm comprises determining the target translation buffer according to the second target bit of the object virtual address in the virtual address translation request, and the first target bit and the second target bit are different.

[0169] For example, the first target bit comprises a plurality of first bit positions in the object virtual address in succession, and the second target bit comprises a plurality of second bit positions in the object virtual address in succession. For example, the 26th-24th bit positions of the 48-bit virtual address are the plurality of first bit positions, and the 25th-23rd bit positions of the 48-bit virtual address are the plurality of second bit positions. The first target bit and the second target bit being a plurality of bit positions in succession can make the access to the plurality of groups of translation buffers uniform.

[0170] For example, k=8 and the arbitration module 301 selects the mapping result of 8 groups of TLB according to the 26th-24th bit positions of the 48-bit virtual address at this time. If the TLB_usaget result is less than 0.8 (the value of α is 0.8) after 109 clocks, the TLB mapping algorithm adjustment module 312 sends the 25th-23rd bit positions of the 48-bit virtual address as the register configuration adjustment information of the TLB mapping to the register configuration module 304, and then to the arbitration module to adjust the TLB mapping algorithm 314.

[0171] In some embodiments of the present disclosure, the first target bit or the second target bit can also be a plurality of bit positions in succession.

[0172] It should be noted that although in the above embodiments, the TLB mapping algorithm is adjusted for the target translation buffer of the mapping, the embodiments of the present disclosure are not limited thereto, and can also include an adaptive adjustment algorithm for the index and the tag.

[0173] Before the TLB mapping algorithm is adjusted, the virtual address translation request that acquires the target TLB information, tag information and index information through the arbitration module 301 still queries the L2 TLB module according to the information acquired before the adjustment. After the TLB mapping algorithm is adjusted, the virtual address translation request that is not input to the arbitration module 301 for conversion request processing will acquire new target TLB information, tag information and index information according to the new TLB mapping algorithm, and then query the L2 TLB module. It should be noted that after the arbitration module 301 receives the register configuration adjustment information from the register configuration module 314, the data in the k groups of TLBs in the L2 TLB will not change. After the TLB mapping algorithm is adjusted, the L2 TLB will update the data in the TLB through a virtual address translation request miss.

[0174] FIG. 8C shows a flowchart of another address translation method provided by at least one embodiment of the present disclosure.

[0175] As shown in FIG. 8C, the address translation method includes steps S801-S804.

[0176] Step S801: The arbitration module determines the target translation buffer, index and tag information mapped by the virtual address translation request according to the mapping algorithm.

[0177] For example, after the arbitration module receives the virtual address translation request from the hardware access unit, it selects the virtual address translation request to be processed through the polling algorithm, and determines the target TLB, index and tag information corresponding to the virtual address translation request according to the mapping algorithm and the virtual address. Then, it sends these information to the L2 TLB module together with the virtual address translation request. This step S801 is similar to step S201 in FIG. 2A, for example.

[0178] Step S802: Determine whether there is a PTE matching the virtual address translation request in the L2 TLB module. If there is no PTE matching the virtual address translation request in the L2 TLB, perform S803. If there is a PTE matching the virtual address translation request in the L2 TLB, perform S804. The specific implementation process of S802 can be to compare the target TLB information, index and tag information in the request with the tag information of the index row stored in the target TLB, so as to determine whether there is a PTE matching the virtual address translation request.

[0179] Step S803: Query the PDE cache from the multi-level page table query module level by level until the PTE matching the virtual address translation request is read back from the physical memory. After receiving the virtual address translation request from step S802, whether there is a PDE matching the virtual address translation request is found from the multi-level page table query module level by level until the PDE0 matching the virtual address translation request is obtained; after the PTE is read back from the physical memory according to the PTB physical base address in the PDE0 field and the corresponding offset in the virtual address field, step S804 is executed.

[0180] Step S804: Determine the physical memory address based on the offset of the physical address and the virtual address in the matched PTE field, and the virtual address to physical address translation is completed.

[0181] Steps S802-S804 are similar to step S202 in FIG. 2A, for example.

[0182] FIG. 9 shows a schematic diagram of an address translation device 900 provided by at least one embodiment of the present disclosure. The address translation device 900 includes an address translation module 901, an arbitration module 902, and an address translation performance monitoring module 903.

[0183] The arbitration module 902 is configured to determine a target translation buffer from the plurality of translation buffers according to a first mapping algorithm in response to obtaining a first virtual address translation request, the first virtual address translation request including an object virtual address. The arbitration module 902 is similar to the arbitration module 301 in FIG. 3 above, please refer to the description above. The arbitration module 902 performs step S201 in FIG. 2A, for example.

[0184] The address translation module 901 includes a plurality of translation buffers. Each of the plurality of translation buffers is configured to store first page table information for translating an object virtual address to an object physical address. The address translation module 901 is configured to access the first page table information in the target translation buffer to translate the object virtual address to the object physical address. The address translation module 901 is similar to the L2 TLB in FIG. 3 above, please refer to the description above. The address translation module 901 performs step S202 in FIG. 2A, for example.

[0185] The address translation performance monitoring module 903 is configured to obtain access frequency information of each of the plurality of translation buffers; determine whether the first mapping algorithm needs to be updated according to the access frequency information; and update the mapping algorithm to a second mapping algorithm in response to the first mapping algorithm needing to be updated. The address translation performance monitoring module 903 is similar to the address translation performance monitoring module 302 in FIG. 3 above, please refer to the description above. The address translation performance monitoring module 903 performs steps S203-S205 in FIG. 2B, for example.

[0186] The address conversion device 900 adaptively adjusts the TLB mapping algorithm when facing a large number of virtual address conversion requests with irregular memory access patterns, avoids the situation that the virtual address conversion request is only mapped to a single TLB, and ensures the utilization rate of the TLB resource.

[0187] In some embodiments of the present disclosure, as shown in FIG. 9, the address conversion device 900 further includes a multi-level page table query module 904, which includes second page table information.

[0188] The address conversion module 901 is configured to: access the first page table information in the target conversion buffer, determine whether the first target page table information matching the first virtual address conversion request exists in the first page table information; and in response to the first target page table information not existing in the target conversion buffer, provide the first virtual address conversion request to the multi-level page table query module 904. The multi-level page table query module 904 is configured to: receive the first virtual address conversion request provided by the address conversion module; determine whether the second target page table information matching the first virtual address conversion request exists in the second page table information; and in response to the second target page table information not existing in the second page table information, obtain the conversion information provided by the external memory, and the conversion information is used to convert the object virtual address into the object physical address.

[0189] For example, the first page table information includes a plurality of page table entries, each page table entry corresponds to a physical page, the second page table information includes a plurality of multi-level page tables, each level of the page table includes a plurality of page directory entries, each page directory entry is used to point to the physical address of the next level of the page table, and each page directory entry in the last level of the multi-level page table is used to point to the page table entry in the first page table information.

[0190] In some embodiments of the present disclosure, the multi-level page table query module is configured to: based on the object virtual address and the base address, obtain a first page table read address of at least one level of the multi-level page table; and based on the first page table read address, determine whether the second target page table information matching the first virtual address conversion request exists in the second page table information.

[0191] In some embodiments of the present disclosure, the multi-level page table query module 904 comprises a same read address merging unit and a translation information cache unit. The same read address merging unit is configured to: in response to the second page table information not existing the second target page table information matching the first virtual address translation request, determine whether a merging signal is valid; in response to the merging signal being valid, compare whether the first page table read address and a second page table read address of a second virtual address translation request located before the first virtual address translation request are same; in response to the first page table read address and the second page table read address being same, merge the first virtual address translation request with the second virtual address translation request, and wait for the translation information provided by the external memory in response to the second virtual address translation request. The translation information cache unit is configured to cache the translation information, and provide the translation information to the address translation module in the case that the address translation module is in an idle state.

[0192] Some embodiments of the present disclosure add a same read address merging module to the multi-level page table query module, merge the same read page table requests sent to the physical memory without affecting the L2 TLB module TLB data update and virtual address translation, and effectively reduce the congestion situation.

[0193] The multi-level page table query module 904 is similar to the multi-level page table query module 303 in FIG. 3, and please refer to the description above. The function and structure of the address translation apparatus 900 please refer to the function and structure of the address translation apparatus 300 in FIG. 3, and will not be repeated here.

[0194] For example, the address translation module 901, the arbitration module 902, the address translation performance monitoring module 903 and the multi-level page table query module 904 can be hardware, software, firmware and any feasible combination thereof. For example, the address translation module 901, the arbitration module 902, the address translation performance monitoring module 903 and the multi-level page table query module 904 can be special-purpose or general-purpose circuits, chips or apparatuses, etc., or can be a combination of a processor and a memory. The present embodiments do not limit the specific implementation forms of the above-mentioned units.

[0195] It should be noted that in the embodiments of the present disclosure, the units of the address translation apparatus 900 and the address translation apparatus 300 correspond to the steps of the address translation method, and the specific functions of the address translation apparatus 900 and the address translation apparatus 300 can be referred to the related description of the address translation method, which will not be repeated here. The components and structure of the address translation apparatus 900 shown in FIG. 9 are only exemplary, but not limiting, and the address translation apparatus 900 can also include other components and structures as needed.

[0196] At least one embodiment of the present disclosure also provides an electronic device including a processor and a memory including one or more computer program modules. The one or more computer program modules are stored in the memory and configured to be executed by the processor, and the one or more computer program modules include instructions for implementing the address translation method described above. The electronic device can alleviate uneven conversion buffer resource allocation of virtual address translation requests and improve the utilization rate of conversion buffer resources.

[0197] FIG. 10A is a schematic block diagram of an electronic device according to some embodiments of the present disclosure. As shown in FIG. 10A, the electronic device 1000 includes a processor 1010 and a memory 1020. The memory 1020 is configured to store non-transitory computer-readable instructions (e.g., one or more computer program modules). The processor 1010 is configured to execute the non-transitory computer-readable instructions, which, when executed by the processor 1010, can perform one or more steps of the address translation method described above. The memory 1020 and the processor 1010 can be interconnected by a bus system and / or other forms of connection mechanisms (not shown).

[0198] For example, the processor 1010 can be a central processing unit (CPU), a graphics processing unit (GPU), or other forms of processing units having data processing and / or program executing capabilities. For example, the central processing unit (CPU) can be of X86 or ARM architecture, etc. The processor 1010 can be a general purpose processor or a special purpose processor, and can control other components in the electronic device 1000 to perform desired functions.

[0199] For example, the memory 1020 can include any combination of one or more computer program products, which can include various forms of computer-readable storage media, for example, volatile memory and / or non-volatile memory. For example, the volatile memory can include random access memory (RAM), cache memory, etc. The non-volatile memory can include read-only memory (ROM), hard disk, erasable programmable read-only memory (EPROM), compact disc read-only memory (CD-ROM), USB memory, flash memory, etc. One or more computer program modules can be stored on the computer-readable storage media, and the processor 1010 can execute the one or more computer program modules to implement various functions of the electronic device 1000. Various application programs and various data used and / or generated by the application programs, etc. can also be stored in the computer-readable storage media.

[0200] It should be noted that in the embodiments of the present disclosure, the specific functions and technical effects of the electronic device 1000 can refer to the description of the address translation method above, which will not be described here again.

[0201] FIG. 10B is a schematic block diagram of another electronic device, according to some embodiments of the present disclosure. The electronic device 1100 is suitable for implementing the address translation method according to some embodiments of the present disclosure, for example. The electronic device 1100 can be a terminal device or the like. It should be noted that the electronic device 1100 shown in FIG. 10B is merely an example, and should not be taken as limiting the functionality or applicability in any way.

[0202] As shown in FIG. 10B, the electronic device 1100 can include a processing apparatus (e.g., a central processing unit, a graphics processing unit, or the like) 1110, which can perform various appropriate actions and processes according to programs stored in a read-only memory (ROM) 1120 or loaded from a storage apparatus 1180 into a random access memory (RAM) 1130. Various programs and data required for operation of the electronic device 1100 are also stored in the RAM 1130. The processing apparatus 1110, the ROM 1120, and the RAM 1130 are connected to each other through a bus 1140. An input / output (I / O) interface 1150 is also connected to the bus 1140.

[0203] Generally, the following apparatuses can be connected to the I / O interface 1150: input apparatuses 1160 including, for example, a touch screen, a touch pad, a keyboard, a mouse, a camera, a microphone, an accelerometer, a gyroscope, or the like; output apparatuses 1170 including, for example, a liquid crystal display (LCD), a speaker, a vibrator, or the like; storage apparatuses 1180 including, for example, a magnetic tape, a hard disk, or the like; and communication apparatuses 1190. The communication apparatuses 1190 can allow the electronic device 1100 to communicate wirelessly or via a wire with other electronic devices to exchange data. Although FIG. 10B shows the electronic device 1100 with various apparatuses, it should be understood that it is not required to implement or have all of the illustrated apparatuses, and the electronic device 1100 can instead implement or have more or less apparatuses.

[0204] For example, according to embodiments of the present disclosure, the address translation method described above can be implemented as a computer software program. For example, embodiments of the present disclosure include a computer program product comprising a computer program carried on a non-transitory computer-readable medium, the computer program comprising program code for performing the address translation method described above. In such embodiments, the computer program can be downloaded and installed from a network via the communication apparatuses 1190, or installed from the storage apparatuses 1180, or installed from the ROM 1120. When the computer program is executed by the processing apparatus 1110, the functions defined in the address translation method according to embodiments of the present disclosure can be implemented.

[0205] At least one embodiment of the present disclosure further provides a computer readable storage medium for storing non-transitory computer readable instructions which, when executed by a computer, can implement the address translation method described above. With the computer readable storage medium, the uneven allocation of virtual address translation request translation buffer resources can be alleviated, and the utilization rate of translation buffer resources can be improved.

[0206] FIG. 11 is a schematic diagram of a storage medium according to some embodiments of the present disclosure. As shown in FIG. 11, the storage medium 1200 is configured to store non-transitory computer readable instructions 1210. For example, when the non-transitory computer readable instructions 1210 are executed by a computer, one or more steps of the address translation method described above can be performed.

[0207] For example, the storage medium 1200 can be applied to the electronic device 1000 described above. For example, the storage medium 1200 can be the memory 1020 in the electronic device 1000 shown in FIG. 10A. For example, the relevant description of the storage medium 1200 can refer to the corresponding description of the memory 1020 in the electronic device 1000 shown in FIG. 10A, which will not be repeated here.

[0208] For the present disclosure, the following points need to be explained:

[0209] (1) In the drawings of the embodiments of the present disclosure, only the structures related to the embodiments of the present disclosure are involved, and other structures can refer to the general design.

[0210] (2) In the case of no conflict, the features in the same and different embodiments of the present disclosure can be combined with each other.

[0211] The above is only a specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited to this. Any person skilled in the art can easily think of changes or replacements within the technical range disclosed by the present disclosure, which should be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. An address translation method applied to an address translation apparatus, the address translation apparatus comprising a plurality of sets of translation buffers, each set of translation buffers comprising first page table information for translating a virtual address to a physical address, the method comprising: determining, in response to obtaining a first virtual address translation request, a target translation buffer from the plurality of sets of translation buffers according to a first mapping algorithm, wherein the first virtual address translation request comprises an object virtual address; and accessing the first page table information in the target translation buffer to translate the object virtual address to an object physical address, the method further comprising: obtaining access frequency information of each set of the plurality of sets of translation buffers; determining, according to the access frequency information, whether the first mapping algorithm needs to be updated; and in response to the first mapping algorithm needing to be updated, updating the first mapping algorithm to a second mapping algorithm. the address translation apparatus further comprising a multi-level page table query module, the multi-level page table query module comprising second page table information, accessing the first page table information in the target translation buffer to translate the object virtual address to the object physical address comprises: accessing the first page table information in the target translation buffer to determine whether there is first target page table information matching the first virtual address translation request in the first page table information; in response to there being no first target page table information matching the first virtual address translation request in the target translation buffer, providing the first virtual address translation request to the multi-level page table query module; determining whether there is second target page table information matching the first virtual address translation request in the second page table information; and in response to there being no second target page table information matching the first virtual address translation request in the second page table information, translating the object virtual address to the object physical address based on translation information provided by an external memory. the first page table information comprises a plurality of page table entries, each page table entry corresponding to a physical page, the second page table information comprises a plurality of multi-level page tables, each multi-level page table comprising a plurality of page directory entries, each page directory entry being used to point to a physical address of a next-level page table, wherein each page directory entry in a last-level page table in the plurality of multi-level page tables is used to point to a page table entry in the first page table information. determining whether there is second target page table information matching the first virtual address translation request in the second page table information comprises: obtaining a first page table read address of at least one multi-level page table in the plurality of multi-level page tables based on the object virtual address and a base address; and determining whether there is second target page table information matching the first virtual address translation request in the second page table information based on the first page table read address. in response to there being no second target page table information matching the first virtual address translation request in the second page table information, translating the object virtual address to the object physical address based on the translation information provided by the external memory comprises: in response to there being no second target page table information matching the first virtual address translation request in the second page table information, determining whether a merge signal is valid; and in response to the merge signal being valid, translating the object virtual address to the object physical address based on the translation information provided by the external memory. ​ 2. The method of claim 1, wherein, ​ ​ ​ ​ ​ ​ 3. The method of claim 2, wherein, ​ ​ ​ 4. The method of claim 3, wherein, ​ ​ ​ 5. The method of claim 4, wherein, ​ ​ in response to the merge signal being valid, comparing the first page table read address and a second page table read address of a second virtual address translation request located before the first virtual address translation request; in response to the first page table read address and the second page table read address being identical, merging the first virtual address translation request with the second virtual address translation request, and waiting for the translation information provided by the external memory in response to the second virtual address translation request; and converting the object virtual address into the object physical address based on the translation information.

6. The method of claim 5, wherein, in response to the second page table information not having the second target page table information matching the first virtual address translation request, converting the object virtual address into the object physical address based on the translation information provided by the external memory, further comprising: in response to the first page table read address and the second page table read address being different, providing a page table read request based on the first virtual address translation request to the external memory to obtain the translation information from the external memory; and updating the merge signal to be invalid.

7. The method of claim 5, wherein, in response to the second page table information not having the second target page table information matching the first virtual address translation request, converting the object virtual address into the object physical address based on the translation information provided by the external memory, further comprising: in response to the merge signal being invalid, providing a page table read request based on the first virtual address translation request to the external memory to obtain the translation information from the external memory; and updating the merge signal to be valid.

8. The method of claim 5, wherein, in response to the second page table information not having the second target page table information matching the first virtual address translation request, converting the object virtual address into the object physical address based on the translation information provided by the external memory, further comprising: in response to receiving the translation information provided by the external memory in response to the second virtual address translation request, updating the merge signal to be invalid.

9. The method of claim 6 or 7, wherein, the page table read request comprises a page table read address of the virtual address translation request, an object virtual address and a hardware access unit identifier providing the virtual address translation request, wherein the page table read address is obtained based on a base address and page directory entry data of at least one level page table in the multi-level page table.

10. The method of claim 3, wherein, accessing the first page table information in the target translation buffer to convert the object virtual address into the object physical address comprises: accessing the first page table information in the target translation buffer to determine whether the first page table information has a target page table entry matching the object virtual address translation request; in response to the first page table information having the target page table entry matching the object virtual address translation request, determining the object physical address corresponding to the object virtual address based on the target page table entry and an offset within a page indicated by the object virtual address.

11. The method of claim 10, wherein, the translation information comprises the target page table entry.

12. The method of any one of claims 1-11, wherein, obtaining access frequency information of each group of the plurality of groups of translation buffers comprises: Counting the number of accesses to each of the plurality of sets of translation buffers, to obtain a count value of each of the plurality of sets of translation buffers in a preset time period.

13. The method of claim 12, wherein, According to the access frequency information, it is determined whether the first mapping algorithm needs to be updated, including: Based on the count value of each of the plurality of sets of translation buffers, an average access value of the count value of the plurality of sets of translation buffers is calculated; An allowed access deviation is obtained; Based on the allowed access deviation and the average access value, an effective access rate of the plurality of sets of translation buffers is calculated; Based on the effective access rate, it is determined whether the first mapping algorithm needs to be updated.

14. The method of claim 13, wherein, Based on the allowed access deviation and the average access value, an effective access rate of the plurality of sets of translation buffers is calculated, including: Based on the allowed access deviation, an access deviation value of each of the plurality of sets of translation buffers is calculated; Based on the access deviation value, an effective utilization indication value of each of the plurality of sets of translation buffers is calculated, wherein for each of the plurality of sets of translation buffers, in response to the sum of the access deviation value and the count value being greater than or equal to the average access value, the effective utilization indication value of the translation buffer is set to a first preset value, and in response to the sum of the access deviation value and the count value being less than the average access value, the effective utilization indication value of the translation buffer is set to a second preset value; and The average value of the effective utilization indication values of the plurality of sets of translation buffers is taken as the effective access rate.

15. The method of claim 14, wherein, Based on the effective access rate, it is determined whether the first mapping algorithm needs to be updated, including: In response to the effective access rate being greater than or equal to a preset access rate, it is determined that the first mapping algorithm does not need to be updated; In response to the effective access rate being less than the preset access rate, it is determined that the first mapping algorithm needs to be updated.

16. The method of any one of claims 1-15, wherein, The first mapping algorithm includes determining the target translation buffer according to a first target bit of the object virtual address in the virtual address translation request, The second mapping algorithm includes determining the target translation buffer according to a second target bit of the object virtual address in the virtual address translation request, Wherein the first target bit and the second target bit are different.

17. The method of claim 16, wherein, The first target bit includes a plurality of first bit positions in the object virtual address in succession, and the second target bit includes a plurality of second bit positions in the object virtual address in succession.

18. An address translation device, comprising: An address translation module including a plurality of sets of translation buffers; An arbitration module configured to, in response to obtaining a first virtual address translation request, determine a target translation buffer from the plurality of sets of translation buffers according to a first mapping algorithm, wherein the first virtual address translation request includes an object virtual address; Wherein each of the plurality of sets of translation buffers is configured to store first page table information for converting the object virtual address into an object physical address, The address translation module is configured to access the first page table information in the target translation buffer to convert the object virtual address into an object physical address, The address translation device further comprises: An address translation performance monitoring module configured to: Obtain access frequency information of each of the plurality of sets of translation buffers; determine whether the first mapping algorithm needs to be updated according to the access frequency information; and update the first mapping algorithm to a second mapping algorithm in response to the first mapping algorithm needing to be updated.

19. Address translation apparatus according to claim 18, further comprising: a multi-level page table query module, the multi-level page table query module comprising second page table information, wherein the address translation module is configured to: access the first page table information in the target translation buffer to determine whether first target page table information matching the first virtual address translation request exists in the first page table information; in response to the first target page table information not existing in the target translation buffer, provide the first virtual address translation request to the multi-level page table query module; the multi-level page table query module is configured to: receive the first virtual address translation request provided by the address translation module; determine whether second target page table information matching the first virtual address translation request exists in the second page table information; and in response to the second target page table information not existing in the second page table information, obtain conversion information provided by an external memory, the conversion information being used to convert the object virtual address into the object physical address.

20. Address translation apparatus according to claim 19, wherein, the first page table information comprises a plurality of page table entries, each page table entry corresponding to a physical page, the second page table information comprises a plurality of page tables, each page table comprising a plurality of page directory entries, each page directory entry being used to point to a physical address of a next-level page table, wherein each page directory entry in a last-level page table in the plurality of page tables is used to point to a page table entry in the first page table information.

21. Address translation apparatus according to claim 20, wherein, the multi-level page table query module is configured to: obtain a first page table read address of at least one page table in the plurality of page tables based on the object virtual address and a base address; determine whether second target page table information matching the first virtual address translation request exists in the second page table information based on the first page table read address.

22. Address translation apparatus according to claim 21, wherein, the multi-level page table query module comprises a same read address merging unit and a conversion information cache unit, the same read address merging unit is configured to: in response to the second target page table information not existing in the second page table information, determine whether a merging signal is valid; in response to the merging signal being valid, compare the first page table read address with a second page table read address of a second virtual address translation request located before the first virtual address translation request; in response to the first page table read address and the second page table read address being the same, merge the first virtual address translation request with the second virtual address translation request, and wait for the conversion information provided by the external memory in response to the second virtual address translation request, the conversion information cache unit is configured to cache the conversion information, and provide the conversion information to the address translation module in a case where the address translation module is in an idle state.

23. An electronic device comprising: a processor; a memory comprising one or more computer program instructions; The one or more computer program instructions, when stored in the memory and executed by the processor, implement the address conversion method of any one of claims 1-17.

24. A computer-readable storage medium having non-transitorily stored thereon computer-readable instructions, wherein, The computer readable instructions, when executed by the processor, implement the address conversion method of any one of claims 1-17.

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