Semiconductor structure and forming method therefor

Abstract

Provided are a semiconductor structure and a forming method therefor. The semiconductor structure comprises: a semiconductor substrate (100), an epitaxial layer (110) being formed on the surface of the semiconductor substrate (100), and a contact doped region (120) being formed in the epitaxial layer (110); shielding doped regions (130), located in the epitaxial layer (110) on both sides of the contact doped region (120), the doping type of the shielding doped regions (130) being opposite to that of the contact doped region (120); a well region (140), located in the epitaxial layer (110) at the bottom of the contact doped region (120), the doping type of the well region (140) being opposite to that of the contact doped region (120), wherein the depth of the shielding doped regions (130) is greater than that of the well region (140) and that of the contact doped region (120); and trench gate structures (150), located on both sides of each of the shielding doped regions (130), penetrating through part of the shielding doped regions (130) and connected to the well region (140) and the contact doped region (120), wherein the depth of the trench gate structures (150) is greater than that of the well region (140) and less than that of the shielding doped regions (130). Thus, the problems of low reliability and low integration level in existing MOSFET cell structures can be solved.

Description

A semiconductor structure and its formation method Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for forming the same. Background Technology

[0002] A basic power MOSFET cell structure includes the following key components: the gate, which is the electrode that controls the conductive state of the device. In a power MOSFET, the gate is isolated from the trench by an insulating layer (usually silicon dioxide); the gate dielectric layer; and the gate dielectric layer. The MOSFET consists of: an oscillator (Oxide), an insulating layer beneath the gate that isolates the gate from the channel and stores charge when a gate voltage is applied; a channel, a semiconductor region located on and beneath the sidewalls of the gate dielectric layer that serves as the path for current flow; a source, the device's source current terminal, typically coinciding with the channel region and doped; a drain, the device's drain current terminal, located at the other end of the channel region, which is isolated from the source by a high-resistance P-type semiconductor before a conductive path is formed; a body, which in some MOSFET designs, especially where isolation is required, may be introduced as another terminal to electrically isolate it from the source, providing better noise suppression and stability; a contact doped region, typically a heavily doped N-type region formed beneath the source and drain to reduce contact resistance and provide better current collection; and a metallization layer, a metal layer formed on the top and / or back of the device to connect the gate, source, and drain and to connect the device to external circuitry. In practical power MOSFET designs, more complex structures may be included, such as multi-finger designs, which contain multiple parallel trench and source structures to improve the device's current carrying capacity.

[0003] The main shortcomings or potential optimization directions of existing power MOSFET cells are as follows: The P-type shielding doped region of the gate dielectric layer leads to low efficiency and unstable reliability, requiring further improvement to increase the channel density and reduce on-resistance. Simultaneously, the electric field shielding efficiency of the gate dielectric layer needs to be further improved to enhance gate reliability. The semiconductor mesa (the region between adjacent trench gate structures) with a specific shape defines the conductive path of the device, and this region is the active part during device operation. In existing power MOSFET cell structures, the physical size of this region is relatively large, and the characteristics of the device structure prevent the carrier enrichment effect from being achieved by reducing the mesa size, which affects its current carrying capacity. Further optimization of the MOSFET cell structure is needed, along with increasing the carrier density by reducing the Mesa size to achieve low on-resistance R. on and low diode forward voltage drop V sd In addition, another important goal in reducing the size of the power MOSFET unit (Mesa) is to increase the cell density of the device structure.

[0004] Summary of the Invention

[0005] The purpose of this invention is to solve the problems of low reliability and low integration of existing MOSFET cell structures, as well as the problem of low integration of body diodes. The technical solution of this invention provides a MOSFET cell structure that optimizes the MOSFET cell structure to improve its reliability and integration.

[0006] One aspect of this application provides a method for forming a semiconductor structure, comprising: providing a semiconductor substrate, wherein an epitaxial layer is formed on the surface of the semiconductor substrate; forming a contact doped region in the epitaxial layer; forming a shield doped region in the epitaxial layer on both sides of the contact doped region, wherein the doping type of the shield doped region is opposite to that of the contact doped region; forming a well region in the epitaxial layer, wherein the doping type of the well region is opposite to that of the contact doped region, wherein the depth of the shield doped region is greater than the depth of the well region is greater than the depth of the contact doped region, the well region surrounds the bottom and sidewalls of the contact doped region, and the well region is also located on the sidewalls of the shield doped region; and forming trench gate structures penetrating a portion of the shield doped region, the well region, and the contact doped region on both sides of the shield doped region, wherein the depth of the trench gate structure is greater than the depth of the well region but less than the depth of the shield doped region.

[0007] In some embodiments of this application, the spacing between the two trench gate structures on both sides of the contact doped region is 0.01 to 1 micrometer.

[0008] In some embodiments of this application, the method for forming the semiconductor structure further includes: forming a dielectric layer on the surface of the epitaxial layer that covers the trench gate structure, the shielding doped region, and the contact doped region; forming a plurality of contact vias that penetrate the dielectric layer and extend to a position between two adjacent trench gate structures; and filling the plurality of contact vias with conductive material to form a plurality of contact structures.

[0009] In some embodiments of this application, the depth of the plurality of contact structures is greater than the depth of the contact doped region but less than the depth of the well region.

[0010] In some embodiments of this application, the method for forming the semiconductor structure further includes: forming a front metal layer on the surface of the dielectric layer that covers the dielectric layer and electrically connects the plurality of contact structures; and forming a back metal layer on the surface of the semiconductor substrate opposite to the epitaxial layer.

[0011] Another aspect of this application provides a semiconductor structure, comprising: a semiconductor substrate, wherein an epitaxial layer is formed on the surface of the semiconductor substrate, and a contact doped region is formed in the epitaxial layer; a shielding doped region is located in the epitaxial layer on both sides of the contact doped region, wherein the doping type of the shielding doped region is opposite to that of the contact doped region; a well region is located in the epitaxial layer at the bottom of the contact doped region, wherein the doping type of the well region is opposite to that of the contact doped region, wherein the depth of the shielding doped region is greater than the depth of the well region is greater than the depth of the contact doped region; and a trench gate structure, wherein the shielding doped region is located on both sides of the shielding doped region and is connected to the well region and the contact doped region through a portion, wherein the depth of the trench gate structure is greater than the depth of the well region and less than the depth of the shielding doped region.

[0012] In some embodiments of this application, the spacing between the two trench gate structures on both sides of the contact doped region is 0.01 to 1 micrometer.

[0013] In some embodiments of this application, the semiconductor structure further includes: a dielectric layer located on the surface of the epitaxial layer covering the trench gate structure, the shielding doped region, and the contact doped region; a plurality of contact vias penetrating the dielectric layer and extending to a position between two adjacent trench gate structures; and a plurality of contact structures located in the plurality of contact vias.

[0014] In some embodiments of this application, the depth of the plurality of contact structures is greater than the depth of the contact doped region but less than the depth of the well region.

[0015] In some embodiments of this application, the semiconductor structure further includes: a front metal layer located on the surface of the dielectric layer, covering the dielectric layer and electrically connecting the plurality of contact structures; and a back metal layer located on the surface of the semiconductor substrate opposite to the epitaxial layer.

[0016] The beneficial effects of this application include, but are not limited to, the following:

[0017] By surrounding part of the trench gate structure with the shielded doped region, the area of ​​the gate dielectric layer exposed in the high electric field region in the trench gate structure is reduced. At the same time, there is no gate dielectric layer structure at the high electric field position of the JFET region formed by two adjacent shielded doped regions in this application, which reduces the electric field stress in the gate dielectric layer. These two aspects achieve higher device gate reliability.

[0018] This application enables two trench gate structures to be simultaneously shielded by a single shielded doped region, thus allowing a single repetitive power MOSFET unit to have two channels. This improves the channel integration density of the device, reduces the channel resistance, and consequently reduces the on-resistance R of the device. on .

[0019] Due to its structural features, this application achieves carrier enrichment through the fabrication of a narrow mesa structure. Under a positive gate bias voltage, the P-well and JFET regions of the MOSFET source have higher electron concentrations, resulting in lower channel resistance and JFET region resistance. Under a negative gate bias voltage, the diode source region has higher hole concentrations, leading to a lower on-state voltage drop V0. sd Therefore, the MOSFET structure of this application has a low on-resistance R. on and low diode V sd The advantages. Attached Figure Description

[0020] The following accompanying drawings describe in detail the exemplary embodiments disclosed in this application. The same reference numerals denote similar structures in several views of the drawings. Those skilled in the art will understand that these embodiments are non-limiting and exemplary, and the drawings are for illustrative purposes only and are not intended to limit the scope of this application. Other embodiments may similarly fulfill the inventive intent of this application. It should be understood that the drawings are not drawn to scale.

[0021] in:

[0022] Figures 1 to 12 are schematic diagrams of each step in the method for forming a semiconductor structure according to the embodiments of this application. Detailed Implementation

[0023] The following description provides specific application scenarios and requirements for this application, intended to enable those skilled in the art to make and use the content of this application. Various partial modifications to the disclosed embodiments will be apparent to those skilled in the art, and the general principles defined herein can be applied to other embodiments and applications without departing from the spirit and scope of this application. Therefore, this application is not limited to the embodiments shown, but rather to the widest scope consistent with the claims.

[0024] The technical solution of the present invention will be described in detail below with reference to the embodiments and accompanying drawings.

[0025] Figures 1 to 12 are schematic diagrams of each step in the method for forming a semiconductor structure according to the embodiments of this application. The method for forming a semiconductor structure according to the embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0026] Referring to Figure 1, a semiconductor substrate 100 is provided, and an epitaxial layer 110 is formed on the surface of the semiconductor substrate 100.

[0027] The semiconductor structure described in this application embodiment is, for example, a power MOSFET device. In some embodiments, the semiconductor substrate 100 is made of silicon carbide, and the epitaxial layer 110 is also made of silicon carbide.

[0028] In some embodiments of this application, the semiconductor substrate 100 may also be made of a semiconductor material other than silicon carbide, such as silicon. The epitaxial layer 110 may also be made of a semiconductor material other than silicon carbide, such as silicon.

[0029] In some embodiments of this application, the epitaxial layer 110 may contain doped ions, such as N-type doped ions. The doping concentration of the epitaxial layer 110 is, for example, 5E13 to 1E17 cm⁻¹. -3 The thickness of the epitaxial layer 110 is, for example, 2-200 micrometers.

[0030] Referring to Figure 2, a contact doped region 120 is formed in the epitaxial layer 110. The doping concentration of the contact doped region 120 is greater than the doping concentration of the epitaxial layer 110. The doping type of the contact doped region 120 is the same as that of the epitaxial layer 110, for example, N-type. The method for forming the contact doped region 120 is, for example, an ion implantation process.

[0031] In some embodiments of this application, the doping concentration of the contact doped region 120 is 1E18 to 1E21 cm⁻¹. -3 The depth of the contact doped region 120 is 0.1-2 micrometers.

[0032] Referring to Figure 3, shielding doped regions 130 are formed in the epitaxial layers 110 on both sides of the contact doped region 120. The doping type of the shielding doped regions 130 is opposite to that of the contact doped regions 120, for example, P-type. The shielding doped regions 130 are formed by, for example, an ion implantation process.

[0033] In some embodiments of this application, the doping concentration of the shielded doped region 130 is from 1E16 to 3E19 cm⁻¹. -3 The depth of the shielding doped region 130 is 1-200 micrometers.

[0034] Referring to Figure 4, a well region 140 is formed in the epitaxial layer 110. The well region 140 has the opposite doping type to the contact doped region 120, for example, p-type. The depth of the shielding doped region 130 is greater than the depth of the well region 140, which is greater than the depth of the contact doped region 120. The well region 140 surrounds the bottom and sidewalls of the contact doped region 120 and is also located on the sidewall of the shielding doped region 130. The well region 140 is formed, for example, by an ion implantation process.

[0035] In some embodiments of this application, the doping concentration of the well region 140 is 1E16 to 3E19 cm⁻¹. -3 The depth of the well region 140 is 0.2-4 micrometers.

[0036] The well region 140 is one of the key processes in semiconductor device manufacturing to realize specific functions of the device, and it has a significant impact on the performance and characteristics of the final device. The well region 140 and the contact doped region 120 form the MOSFET source region 141 (this MOSFET structure will be described later); the well region 140 forms the diode source region 142 in the shielded doped region 130 (the shielded doped region 130 and the epitaxial layer 110 constitute a PN junction diode).

[0037] In some embodiments of this application, the method for forming the semiconductor structure further includes performing a high-temperature annealing process on the surface of the epitaxial layer 110. The high-temperature annealing process is carried out at a temperature of 1600–1800 degrees Celsius for a time of 5–40 minutes. The high-temperature annealing process can activate ion-implanted impurities.

[0038] Referring to Figures 5 to 7, trench gate structures 150 are formed on both sides of the shielded doped region 130, penetrating the shielded doped region 130, the well region 140, and the contact doped region 120, respectively. The depth of the trench gate structure 150 is greater than the depth of the well region 140 and less than the depth of the shielded doped region 130.

[0039] Referring to Figure 5, an etching process is performed to form gate trenches 153 that penetrate the shielded doped region 130, the well region 140, and the contact doped region 120 on both sides of the shielded doped region 130. The depth of the gate trenches 153 is greater than the depth of the well region 140 and less than the depth of the shielded doped region 130.

[0040] Referring to Figure 6, a gate dielectric layer 151 is formed at the bottom and sidewalls of the gate trench 153. The material of the gate dielectric layer 151 includes low-k or high-k insulating dielectric materials such as silicon oxide or silicon nitride.

[0041] Referring to FIG7, a gate layer 152 is formed on the surface of the gate dielectric layer 151 to fill the gate trench 153, and the gate dielectric layer 151 and the gate layer 152 constitute the trench gate structure 150.

[0042] In some embodiments of this application, the material of the gate layer 152 is, for example, polysilicon. Methods for forming the gate layer 152 include chemical vapor deposition processes, etc.

[0043] In some embodiments of this application, after the gate layer 152 is deposited, the polycrystalline silicon material needs to undergo annealing. This is a high-temperature heat treatment process used to reduce lattice defects, increase grain size, and thereby improve the electrical properties of the material. The annealing process helps repair lattice damage that may occur during deposition and can promote the diffusion of dopant elements.

[0044] Referring to Figure 7, the MOSFET source region 141 formed by the well region 140 and the contact doped region 120, and the two adjacent trench gate structures 150 are all part of a repeatable basic power MOSFET unit 160.

[0045] Referring to Figure 7, in the technical solution of this application, the shielded doped region 130 surrounds part of the trench gate structure 150 (surrounding one sidewall and part of the bottom surface of each trench gate structure 150), reducing the area of ​​the gate dielectric layer 151 exposed in the high electric field region of the trench gate structure 150; at the same time, in this application, there is no gate dielectric layer structure at the high electric field position of the JFET region formed by two adjacent shielded doped regions 130, which reduces the electric field stress in the gate dielectric layer. These two aspects achieve higher device gate reliability.

[0046] Referring to Figure 7, in the technical solution of this application, a shielded doped region 130 simultaneously shields two adjacent trench gate structures 150, thereby enabling a repetitive power MOSFET unit 160 to have two channels. This improves the channel integration of the device, reduces the channel resistance, and thus reduces the on-resistance R of the device. on .

[0047] Referring to Figure 7, in some embodiments of this application, the spacing between the two trench gate structures 150 on both sides of the contact doped region 120 is 0.01 to 1 micrometer, for example, 0.02 to 0.9 micrometers, 0.05 to 0.7 micrometers, 0.1 to 0.5 micrometers, or 0.2 to 0.4 micrometers. The region between the two trench gate structures 150 on both sides of the contact doped region 120 is a semiconductor mesa. In the technical solution of this application, this region only includes the contact doped region 120 and the well region 140, with a simple and singular structure, thus allowing for a reduction in the size of this region.

[0048] In other words, due to its structural features, this application can achieve carrier enrichment by fabricating a narrow mesa structure. When the gate bias voltage is positive, the P-well and JFET regions of the MOSFET source region have higher electron concentrations, resulting in lower channel resistance and JFET region resistance. When the gate bias voltage is negative, the diode source region has higher hole concentrations, resulting in a lower on-state voltage drop V0. sd Therefore, the MOSFET structure of this application has a low on-resistance R. on and low diode V sd The advantages.

[0049] In some embodiments of this application, the method for forming the semiconductor structure further includes: referring to FIG8, forming a dielectric layer 170 covering the trench gate structure 150, the shielding doped region 130, and the contact doped region 120 on the surface of the epitaxial layer 110; referring to FIG9, forming a plurality of contact vias 171 penetrating the dielectric layer 170 and extending to a position between two adjacent trench gate structures 150; referring to FIG10, filling the plurality of contact vias 171 with conductive material to form a plurality of contact structures 180.

[0050] In some embodiments of this application, the depth of the plurality of contact structures 180 is greater than the depth of the contact doped region 120 and less than the depth of the well region 140 to short-circuit the contact doped region 120 and the well region 140.

[0051] In some embodiments of this application, the dielectric layer 170 is made of insulating dielectric materials such as silicon oxide or silicon nitride. The contact structure 180 is made of conductive metallic materials such as tungsten or copper.

[0052] The contact structure 180 forms an ohmic contact with the MOSFET source region 141 and the diode source region 142. An ohmic contact is a low-resistance electrical contact formed between a semiconductor and other conductive materials (usually metals). Ideally, the resistance of an ohmic contact is negligible compared to the resistance within the semiconductor material. This contact method follows Ohm's law, that is, current is proportional to voltage, with the proportionality constant being the resistance. In semiconductor devices, ohmic contacts are commonly used at the gate, source, and drain terminals to achieve good current collection and transport.

[0053] In some embodiments of this application, the method of forming the semiconductor structure further includes: referring to FIG11, forming a front metal layer 191 on the surface of the dielectric layer 170 that covers the dielectric layer 170 and electrically connects the plurality of contact structures 180; referring to FIG12, forming a back metal layer 192 on the surface of the semiconductor substrate 100 facing away from the epitaxial layer 110.

[0054] In some embodiments of this application, the materials of the front metal layer 191 and the back metal layer 192 include copper, aluminum, or tungsten, etc.

[0055] A front-side metal layer refers to the metal interconnects located on the surface of a wafer or the front side of a device. The front-side metal layer is used to form electrical connections within the device, such as connecting the source, drain, and gate of a transistor. In traditional IC design, most interconnect work is done on the front side, including multilayer interconnect technologies, where these layers are connected via vias. A back-side metal layer refers to the metal interconnects located on the back side of a wafer or the back side of a device. In some high-power or high-frequency applications, the back-side metal layer is used to provide additional electrical connections or as a heat dissipation path; for example, in this embodiment, the back-side metal layer 192 can serve as the drain of a transistor. The back-side metal layer can also be used to form the substrate of a device, providing mechanical support and electrical connections.

[0056] An embodiment of this application also provides a semiconductor structure, referring to FIG7, comprising: a semiconductor substrate 100, wherein an epitaxial layer 110 is formed on the surface of the semiconductor substrate 100, and a contact doped region 120 is formed in the epitaxial layer 110; a shielding doped region 130 located in the epitaxial layer 110 on both sides of the contact doped region 120, wherein the doping type of the shielding doped region 130 is opposite to that of the contact doped region 120; and a well region 140 located in the epitaxial layer 110 at the bottom of the contact doped region 120. The well region 140 has the opposite doping type to the contact doped region 120, wherein the depth of the shield doped region 130 is greater than the depth of the well region 140, which is greater than the depth of the contact doped region 120; the trench gate structure 150 is located on both sides of the shield doped region 130, penetrating the shield doped region 130 and connecting the shield doped region 130 to the sidewalls of the well region 140 and the contact doped region 120, and the depth of the trench gate structure 150 is greater than the depth of the well region 140, which is less than the depth of the shield doped region 130.

[0057] The semiconductor structure described in this application embodiment is, for example, a power MOSFET device. In some embodiments, the semiconductor substrate 100 is made of silicon carbide, and the epitaxial layer 110 is also made of silicon carbide.

[0058] In some embodiments of this application, the semiconductor substrate 100 may also be made of a semiconductor material other than silicon carbide, such as silicon. The epitaxial layer 110 may also be made of a semiconductor material other than silicon carbide, such as silicon.

[0059] In some embodiments of this application, the epitaxial layer 110 may contain doped ions, such as N-type doped ions. The doping concentration of the epitaxial layer 110 is, for example, 5E13 to 1E17 cm⁻¹. -3 The thickness of the epitaxial layer 110 is, for example, 2-200 micrometers.

[0060] In some embodiments of this application, the doping concentration of the contact doped region 120 is greater than the doping concentration of the epitaxial layer 110. The doping type of the contact doped region 120 is the same as that of the epitaxial layer 110, for example, N-type.

[0061] In some embodiments of this application, the doping concentration of the contact doped region 120 is 1E18 to 1E21 cm⁻¹. -3 The depth of the contact doped region 120 is 0.1-2 micrometers.

[0062] In some embodiments of this application, the doping type of the shielding doped region 130 is opposite to that of the contact doped region 120, for example, it is P-type.

[0063] In some embodiments of this application, the doping concentration of the shielded doped region 130 is from 1E16 to 3E19 cm⁻¹. -3 The depth of the shielding doped region 130 is 1-200 micrometers.

[0064] In some embodiments of this application, the well region 140 has the opposite doping type to the contact doped region 120, for example, P-type. The depth of the shielding doped region 130 is greater than the depth of the well region 140, which is greater than the depth of the contact doped region 120. The well region 140 surrounds the bottom and sidewalls of the contact doped region 120, and is also located on the sidewall of the shielding doped region 130.

[0065] In some embodiments of this application, the doping concentration of the well region 140 is 1E16-3E19 cm⁻¹. -3 The depth of the well region 140 is 0.2-4 micrometers.

[0066] The well region 140 is one of the key processes in semiconductor device manufacturing to realize specific functions of the device, and it has a significant impact on the performance and characteristics of the final device. Referring to Figure 4, the well region 140 and the contact doped region 120 form the MOSFET source region 141; the well region 140 forms the diode source region 142 (the PN junction diode formed by the shielded doped region 130 and the epitaxial layer 110) in the shielded doped region 130.

[0067] In some embodiments of this application, the trench gate structure 150 includes a gate layer 152 and a gate dielectric layer 151 covering the bottom and sidewalls of the gate layer 150. The gate dielectric layer 151 is made of a low-k or high-k insulating dielectric material such as silicon oxide or silicon nitride. The gate layer 152 is made of, for example, polysilicon.

[0068] Referring to Figure 7, the MOSFET source region 141 formed by the well region 140 and the contact doped region 120, and the two adjacent trench gate structures 150 are all part of a repeatable basic power MOSFET unit 160.

[0069] Referring to Figure 7, in the technical solution of this application, the shielded doped region 130 surrounds part of the trench gate structure 150 (surrounding one sidewall and part of the bottom surface of each trench gate structure 150), reducing the area of ​​the gate dielectric layer 151 exposed in the high electric field region of the trench gate structure 150; at the same time, in this application, there is no gate dielectric layer structure at the high electric field position of the JFET region formed by two adjacent shielded doped regions 130, which reduces the electric field stress in the gate dielectric layer. These two aspects achieve higher device gate reliability.

[0070] Referring to Figure 7, in the technical solution of this application, a shielded doped region 130 simultaneously shields two adjacent trench gate structures 150, thereby enabling a repetitive power MOSFET unit 160 to have two channels. This improves the channel integration of the device, reduces the channel resistance, and thus reduces the on-resistance R of the device. on .

[0071] Referring to Figure 7, in some embodiments of this application, the spacing between the two trench gate structures 150 on both sides of the contact doped region 120 is 0.01 to 1 micrometer, for example, 0.02 to 0.9 micrometers, 0.05 to 0.7 micrometers, 0.1 to 0.5 micrometers, or 0.2 to 0.4 micrometers. The region between the two trench gate structures 150 on both sides of the contact doped region 120 is a semiconductor mesa. In the technical solution of this application, this region only includes the contact doped region 120 and the well region 140, with a simple and singular structure, thus allowing for a reduction in the size of this region.

[0072] In other words, due to its structural features, this application can achieve carrier enrichment by fabricating a narrow mesa structure. When the gate bias voltage is positive, the P-well and JFET regions of the MOSFET source region have higher electron concentrations, resulting in lower channel resistance and JFET region resistance. When the gate bias voltage is negative, the diode source region has higher hole concentrations, resulting in a lower on-state voltage drop V0. sd Therefore, the MOSFET structure of this application has a low on-resistance R. on and low diode V sd The advantages.

[0073] Referring to FIG12, in some embodiments of this application, the semiconductor structure further includes: a dielectric layer 170 covering the trench gate structure 150, the shielding doped region 130 and the contact doped region 120; a plurality of contact vias 171 penetrating the dielectric layer 170 and extending to a position between two adjacent trench gate structures 150; and a plurality of contact structures 180 located in the plurality of contact vias 171.

[0074] In some embodiments of this application, the depth of the plurality of contact structures 180 is greater than the depth of the contact doped region 120 and less than the depth of the well region 140 to short-circuit the contact doped region 120 and the well region 140.

[0075] In some embodiments of this application, the dielectric layer 170 is made of insulating dielectric materials such as silicon oxide or silicon nitride. The contact structure 180 is made of conductive metallic materials such as tungsten or copper.

[0076] The contact structure 180 forms an ohmic contact with the MOSFET source region 141 and the diode source region 142.

[0077] Referring to FIG12, in some embodiments of this application, the semiconductor structure further includes: a front metal layer 191 covering the dielectric layer 170 and electrically connecting the plurality of contact structures 180; and a back metal layer 192 located on the surface of the semiconductor substrate 100 facing away from the epitaxial layer 110.

[0078] In some embodiments of this application, the materials of the front metal layer 191 and the back metal layer 192 include copper, aluminum, or tungsten, etc.

[0079] In summary, after reading this application, those skilled in the art will understand that the foregoing application content is presented by way of example only and is not restrictive. Although not explicitly stated herein, those skilled in the art will understand that this application is intended to encompass various reasonable changes, improvements, and modifications to the embodiments. These changes, improvements, and modifications are all within the spirit and scope of the exemplary embodiments of this application.

[0080] It should be understood that the term "and / or" as used in this embodiment includes any or all combinations of one or more of the associated listed items. It should be understood that when an element is referred to as "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or there may be an intermediate element.

[0081] Similarly, it should be understood that when an element such as a layer, region, or substrate is referred to as being "on" another element, it may be directly on that other element, or there may be intermediate elements present. Conversely, the term "directly" means without intermediate elements. It should also be understood that the terms "comprising," "including," "including," or "comprises," as used in this application, indicate the presence of the described features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof.

[0082] It should also be understood that although the terms first, second, third, etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Therefore, without departing from the teachings of this application, a first element in some embodiments may be referred to as a second element in other embodiments. The same reference numerals or the same reference signs denote the same elements throughout the specification.

[0083] Furthermore, this application specification describes exemplary embodiments by referring to idealized exemplary cross-sectional views and / or plan views and / or perspective views. Therefore, differences from the illustrated shapes are foreseeable due to factors such as manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but should include deviations in shape caused, for example, by manufacturing processes. For instance, etched areas shown as rectangular typically have circular or curved features. Therefore, the regions shown in the figures are substantially schematic, and their shapes are not intended to illustrate the actual shape of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: A semiconductor substrate is provided, wherein an epitaxial layer is formed on the surface of the semiconductor substrate; A contact doped region is formed in the epitaxial layer; A shielding doped region is formed in the epitaxial layer on both sides of the contact doped region, and the doping type of the shielding doped region is opposite to that of the contact doped region. A well region is formed in the epitaxial layer, the doping type of the well region being opposite to that of the contact doped region, wherein the depth of the shielding doped region is greater than the depth of the well region being greater than the depth of the contact doped region, the well region surrounds the bottom and sidewalls of the contact doped region, and the well region is also located on the sidewalls of the shielding doped region; A trench gate structure is formed on both sides of the shielded doped region, penetrating the shielded doped region, the well region, and the contact doped region, respectively. The depth of the trench gate structure is greater than the depth of the well region but less than the depth of the shielded doped region.

2. The method for forming a semiconductor structure as described in claim 1, characterized in that, The spacing between the two trench gate structures on both sides of the contact doped region is 0.01 to 1 micrometer.

3. The method for forming a semiconductor structure as described in claim 1, characterized in that, Also includes: A dielectric layer covering the trench gate structure, the shielding doped region, and the contact doped region is formed on the surface of the epitaxial layer; A plurality of contact vias are formed, penetrating the dielectric layer and extending to the location between two adjacent trench gate structures; Conductive material is filled into the plurality of contact holes to form a plurality of contact structures.

4. The method for forming a semiconductor structure as described in claim 3, characterized in that, The depth of the plurality of contact structures is greater than the depth of the contact doped region but less than the depth of the well region.

5. The method for forming a semiconductor structure as described in claim 3, characterized in that, Also includes: A front metal layer is formed on the surface of the dielectric layer, covering the dielectric layer and electrically connecting the plurality of contact structures; A back metal layer is formed on the surface of the semiconductor substrate opposite to the epitaxial layer.

6. A semiconductor structure, characterized in that, include: A semiconductor substrate, wherein an epitaxial layer is formed on the surface of the semiconductor substrate, and a contact doped region is formed in the epitaxial layer; A shielding doped region is located in the epitaxial layer on both sides of the contact doped region, and the doping type of the shielding doped region is opposite to that of the contact doped region. A well region is located in the epitaxial layer at the bottom of the contact doped region. The doping type of the well region is opposite to that of the contact doped region. The depth of the shielding doped region is greater than the depth of the well region, which is greater than the depth of the contact doped region. A trench gate structure is located on both sides of the shielded doped region, with the shielded doped region connected to the well region and the contact doped region. The depth of the trench gate structure is greater than the depth of the well region but less than the depth of the shielded doped region.

7. The semiconductor structure as described in claim 6, characterized in that, The spacing between the two trench gate structures on both sides of the contact doped region is 0.01 to 1 micrometer.

8. The semiconductor structure as described in claim 6, characterized in that, Also includes: A dielectric layer is located on the surface of the epitaxial layer, covering the trench gate structure, the shielding doped region, and the contact doped region; Several contact vias penetrate the dielectric layer and extend to the location between two adjacent trench gate structures; Several contact structures are located in the several contact through holes.

9. The semiconductor structure as described in claim 8, characterized in that, The depth of the plurality of contact structures is greater than the depth of the contact doped region but less than the depth of the well region.

10. The semiconductor structure as described in claim 8, characterized in that, Also includes: A front metal layer is located on the surface of the dielectric layer, covering the dielectric layer and electrically connecting the plurality of contact structures; A back metal layer is located on the surface of the semiconductor substrate opposite to the epitaxial layer.

Images