Intelligent identification method and system for compositional structure based on semiconductor memory chip

Abstract

The present application discloses an intelligent identification method and system for a compositional structure based on a semiconductor memory chip. The method comprises: acquiring a memory chip image of a semiconductor memory chip; constructing a noise probability distribution model of the memory chip image, constructing a denoising function of the memory chip image, and performing denoising on the memory chip image to obtain a denoised memory chip image; constructing an adaptive threshold segmentation model for a structure identification training image, and using the adaptive threshold segmentation model to perform segmentation on the structure identification training image to obtain a segmented training image; and constructing a deep learning network for the segmented training image, creating a compositional structure identification model for the denoised memory chip image, analyzing a structural composition of the denoised memory chip image, identifying an anomaly coefficient of the structural composition, and constructing a compositional structure analysis report for the semiconductor memory chip. The present application improves accuracy in identifying the compositional structure of semiconductor memory chips.

Description

Intelligent Identification Method and System for the Composition Structure of Semiconductor Memory Chips

[0001] This application claims priority to Chinese Patent Application No. 202411189104.1, filed on August 28, 2024, entitled "Intelligent Recognition Method and System for Composition Structure Based on Semiconductor Memory Chip", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of semiconductor technology, specifically to a method and system for intelligent identification of the composition structure of semiconductor memory chips. Background Technology

[0003] The statements herein are provided only as background information in connection with this application and do not necessarily constitute prior art.

[0004] Intelligent identification of the semiconductor memory chip structure utilizes computer vision and machine learning technologies to automatically analyze the chip's microstructure, enabling structural detection, classification, and defect identification. The benefits include improved production efficiency, reduced costs, enhanced product quality and reliability, while simultaneously driving technological innovation and enabling real-time production line monitoring and data-driven decision-making.

[0005] Currently, intelligent identification of the composition and structure of semiconductor memory chips mainly relies on operators inspecting the chips with a microscope or using preset rules and template matching techniques. This method is ill-suited to diverse defect types and structural variations, resulting in many defects going unidentified and thus leading to inaccurate identification of the composition and structure of semiconductor memory chips. Application content

[0006] The purpose of this application is to provide a method and system for intelligent identification of the composition structure of semiconductor memory chips, the main purpose of which is to improve the accuracy of identification of the composition structure of semiconductor memory chips.

[0007] The technical solution adopted in the embodiments of this application is:

[0008] On the one hand, a method for intelligent identification of the composition structure of semiconductor memory chips is provided, including:

[0009] The structural identification requirements of the semiconductor memory chip are determined. Based on the structural identification requirements, a microscope cluster for the semiconductor memory chip is constructed. Based on the microscope cluster, images of the semiconductor memory chip are acquired.

[0010] A noise probability distribution model of the memory chip image is constructed. Based on the noise probability distribution model, a denoising function of the memory chip image is constructed. Based on the denoising function, noise is removed from the memory chip image to obtain a denoised memory chip image.

[0011] Obtain a structural recognition training image of the semiconductor memory chip, construct an adaptive threshold segmentation model for the structural recognition training image, and use the adaptive threshold segmentation model to segment the structural recognition training image to obtain a segmented training image;

[0012] A deep learning network for segmenting training images is constructed, wherein the deep learning network includes a CNN network, an RNN network, and a GAN network. The CNN network is used to extract hierarchical features of the segmentation training images, the RNN network is used to analyze the temporal relationship of the corresponding image structure of the segmentation training images, and the GAN network is used to construct diversified training images of the segmentation training images.

[0013] Using the hierarchical features, the temporal relationships, and the diverse training images, a compositional structure recognition model for the denoised memory chip image is established. Based on the compositional structure recognition model, the structural composition of the denoised memory chip image is analyzed, and the abnormal coefficients of the structural composition are identified. Based on the structural composition and the abnormal coefficients, a compositional structure analysis report for the semiconductor memory chip is constructed.

[0014] On the other hand, a smart identification system for the composition structure of semiconductor memory chips is also provided, the system comprising:

[0015] A memory chip image acquisition module is used to determine the structural identification requirements of a semiconductor memory chip, construct a microscope cluster of the semiconductor memory chip based on the structural identification requirements, and acquire memory chip images of the semiconductor memory chip based on the microscope cluster.

[0016] The chip image noise removal module is used to construct a noise probability distribution model of the memory chip image, construct a denoising function for the memory chip image based on the noise probability distribution model, and remove noise from the memory chip image based on the denoising function to obtain a denoised memory chip image.

[0017] The training image segmentation module is used to acquire the structure recognition training image of the semiconductor memory chip, construct an adaptive threshold segmentation model for the structure recognition training image, and use the adaptive threshold segmentation model to segment the structure recognition training image to obtain a segmented training image.

[0018] The segmentation training image analysis module is used to construct a deep learning network for the segmentation training images. The deep learning network includes a CNN network, an RNN network, and a GAN network. The CNN network is used to extract hierarchical features of the segmentation training images, the RNN network is used to analyze the temporal relationship of the corresponding image structure of the segmentation training images, and the GAN network is used to construct diversified training images of the segmentation training images.

[0019] The composition structure analysis module is used to establish a composition structure recognition model of the denoised memory chip image by utilizing the hierarchical features, the temporal relationship, and the diverse training images; analyze the structural composition of the denoised memory chip image based on the composition structure recognition model; identify the abnormal coefficients of the structural composition; and construct a composition structure analysis report of the semiconductor memory chip based on the structural composition and the abnormal coefficients.

[0020] The beneficial effects of the intelligent identification method and system for the composition structure of semiconductor memory chips provided in this application are as follows: Based on the structural identification requirements, this application constructs a microscope cluster for the semiconductor memory chip, which can monitor the structural images of the semiconductor memory chip and provide a basis for subsequent structural analysis; Optionally, based on the microscope cluster, this application can acquire images of the semiconductor memory chip, which can improve the basic images for subsequent microstructural analysis of the chip; The noise probability distribution model of the memory chip image constructed by this application can provide a basis for the design of subsequent image denoising algorithms, thereby improving the reliability of image noise removal; Based on the noise probability distribution model, this application constructs a denoising function for the memory chip image, which can remove noise from the image, improve image quality and the accuracy of subsequent analysis. This application utilizes the adaptive threshold segmentation model to segment the structure recognition training images. The segmented training images can be used to train and optimize the structure recognition model, improving production efficiency and product quality. This application also utilizes the RNN network to analyze the temporal relationships of the image structures corresponding to the segmented training images, capturing the temporal dependencies in the image sequence, thereby improving the accuracy and reliability of chip structure composition recognition. Finally, based on the composition structure recognition model, this application analyzes the structural composition of the denoised memory chip image, leading to a better understanding of the memory chip's working principle and performance characteristics, thus better identifying the memory chip's composition structure. Based on the structural composition and the anomaly coefficients, a composition structure analysis report of the semiconductor memory chip can be constructed, further enhancing the understanding of the memory chip's working principle and performance characteristics. Therefore, this application can improve the accuracy of semiconductor memory chip composition structure recognition. Attached Figure Description

[0021] Figure 1 is a flowchart illustrating an intelligent identification method for the composition structure of a semiconductor memory chip according to an embodiment of this application;

[0022] Figure 2 is a functional block diagram of an intelligent identification system based on the composition structure of a semiconductor memory chip provided in an embodiment of this application;

[0023] Figure 3 is a schematic diagram of the structure of an electronic device for a semiconductor memory chip-based intelligent identification system according to an embodiment of this application;

[0024] The realization of the purpose, functional features and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0025] It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit this application.

[0026] This application provides a method for intelligent identification of the composition structure based on semiconductor memory chips. The executing entity of this method includes, but is not limited to, at least one of the following electronic devices that can be configured to execute the method provided in this application: a server, a terminal, etc. In other words, the method for intelligent identification of the composition structure based on semiconductor memory chips can be executed by software or hardware installed on a terminal device or a server device, and the software can be a blockchain platform. The server includes, but is not limited to, a single server, a server cluster, a cloud server, or a cloud server cluster. The server can be an independent server or a cloud server that provides basic cloud computing services such as cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communication, middleware services, domain name services, security services, content delivery networks (CDNs), and big data and artificial intelligence platforms.

[0027] Referring to Figure 1, a flowchart illustrating a method for intelligent identification of the composition structure of a semiconductor memory chip according to an embodiment of this application is shown. In this embodiment, the method for intelligent identification of the composition structure of a semiconductor memory chip includes:

[0028] S1. Determine the structural identification requirements of the semiconductor memory chip, construct a microscope cluster for the semiconductor memory chip based on the structural identification requirements, and acquire memory chip images of the semiconductor memory chip based on the microscope cluster.

[0029] This application, by identifying the structural identification requirements of semiconductor memory chips, can provide a basis for the construction of subsequent identification methods.

[0030] Specifically, the determination of the structural identification requirements for semiconductor memory chips includes:

[0031] Obtain the design drawings of the semiconductor memory chip;

[0032] Based on the design drawings, identify the key structural elements of the semiconductor memory chip;

[0033] Identify the structural element characteristics of the key structural elements;

[0034] The identification accuracy requirements of the semiconductor memory chip are analyzed based on the structural features described above.

[0035] Based on the aforementioned recognition accuracy requirements, the structural recognition requirements for semiconductor memory chips are determined.

[0036] The design drawings refer to the detailed design blueprints of semiconductor memory chips, usually existing in electronic form, containing all design details of the chip, such as circuit layout, device size, and connection methods. The key structural elements refer to the parts of the design drawings that are crucial to the chip's function. These parts include, but are not limited to, memory cells, circuit layout, registers, logic gates, and other electronic components. The structural element characteristics refer to the physical and electrical properties of the key structural elements, which may include features such as size, shape, and material. The recognition accuracy requirements refer to the level of accuracy that the structural recognition system must achieve to ensure the chip's function and performance, such as requirements for spatial resolution, feature accuracy, false detection and false negative rates. The structural recognition requirements refer to the specific requirements for the semiconductor memory chip structural recognition system, such as requirements for the list of structural elements, the recognition accuracy of structural elements, and the identification of structural anomalies.

[0037] Furthermore, the structural feature characteristics for identifying the key structural elements can be extracted through edge detection.

[0038] Based on the aforementioned structural identification requirements, this application constructs a microscope cluster for the semiconductor memory chip, which can monitor the structural images of the semiconductor memory chip and provide a basis for subsequent structural analysis. The microscope cluster refers to an integrated microscope system, including scanning electron microscopes, transmission electron microscopes, atomic force microscopes, optical microscopes, and other microscopes.

[0039] Specifically, the construction of the microscope cluster for the semiconductor memory chip based on the structural identification requirements includes:

[0040] Based on the aforementioned structural identification requirements, the microscopic parameters of the semiconductor memory chip are determined, wherein the microscopic parameters include resolution, magnification, and imaging speed.

[0041] Based on the design drawings corresponding to the structural identification requirements, the microscope layout of the semiconductor memory chip is constructed.

[0042] Based on the microscope indicators, configure the target microscope corresponding to the layout nodes of the microscope layout;

[0043] Construct a data transmission network for the target microscope;

[0044] The target microscope is calibrated through the data transmission network to obtain a calibrated microscope;

[0045] Construct the initial microscope cluster for the calibration microscope;

[0046] Analyze the synergy coefficient of the initial microscope cluster;

[0047] When the coordination coefficient meets the preset coordination threshold, the initial microscope cluster is taken as the microscope cluster.

[0048] The resolution refers to the smallest detail size that the microscope can clearly display, usually measured in nanometers (nm). The magnification refers to the magnification factor of the microscope, which affects the size of the observed detail. The imaging speed refers to the speed at which the microscope generates images, usually measured in frames per second (fps). The microscope layout refers to the physical arrangement and configuration of microscopes in a microscope cluster, including their distances, angles, and relative positions to the sample. The target microscope is the microscope selected for use in the cluster based on structural identification requirements and microscope specifications. The data transmission network refers to the network connecting the microscopes and subsequent processing systems (such as image analysis software) to ensure rapid transmission of image data. The calibration microscope refers to the microscope calibrated through the data transmission network to ensure the accuracy and consistency of its output images. The initial microscope cluster refers to the set of microscopes configured according to the microscope layout and the target microscope for initial analysis and testing. The synergy coefficient refers to the degree of synergy between the microscopes in the initial microscope cluster and with the subsequent processing system.

[0049] Furthermore, the data transmission network for constructing the target microscope can be implemented using communication protocol technology.

[0050] Further, the analysis of the synergy coefficient of the initial microscope cluster includes:

[0051] The initial microscope cluster was simulated, and the simulation results were obtained.

[0052] The simulation results are divided into normal operation results and abnormal operation results;

[0053] Based on the normal operation results, analyze the image quality, data transmission efficiency, and system response time of the initial microscope cluster in operation simulation;

[0054] Based on the results of the abnormal operation, the fault recovery parameters and maintainability coefficient of the initial microscope cluster are determined;

[0055] Based on the image quality, data transmission efficiency, system response time, fault recovery parameters, and maintainability coefficient, the coordination coefficient of the initial microscope cluster is calculated using the following formula: ,in This represents the coordination coefficient of the initial microscope cluster. Indicates image quality, Indicates data transmission efficiency. Indicates system response time. This indicates the fault detection speed corresponding to the fault recovery parameters. This indicates the fault response time corresponding to the fault recovery parameters. This indicates the fault handling time corresponding to the fault recovery parameters. This indicates the fault recovery parameters and the corresponding fault reconstruction time. This represents the maintainability factor.

[0056] The simulation results refer to the prediction of the microscope cluster's performance in actual production by simulating the actual working environment. The normal operation results refer to the operation results without any faults or abnormalities during the simulation, reflecting the performance of the microscope cluster under normal conditions. The abnormal operation results refer to the operation results with faults or abnormalities that occur during the simulation. The image quality refers to the overall image quality output by the microscope cluster. The data transmission efficiency refers to the transmission speed and stability of data from the microscope cluster to the subsequent processing system. The system response time refers to the response speed of the microscope cluster to operation commands. The maintainability coefficient refers to the ease of maintenance and upgrading of the microscope cluster. The fault detection speed refers to the speed at which the system detects a fault and issues an alarm. The fault response time refers to the time from fault detection to the start of action. The fault handling time refers to the time from the start of fault handling to the restoration of normal operation. The fault reconstruction time refers to the time from the completion of fault handling to the complete restoration of normal system operation.

[0057] This application utilizes the aforementioned microscope cluster to acquire images of the semiconductor memory chip, providing a foundation for subsequent microstructural analysis of the chip. Specifically, the memory chip image refers to an image obtained through high-resolution imaging of the semiconductor memory chip using the microscope cluster.

[0058] S2. Construct a noise probability distribution model for the memory chip image, construct a denoising function for the memory chip image based on the noise probability distribution model, and remove noise from the memory chip image based on the denoising function to obtain a denoised memory chip image.

[0059] The noise probability distribution model of the memory chip image constructed in this application can provide a basis for the design of subsequent image denoising algorithms, thereby improving the reliability of image noise removal.

[0060] Specifically, constructing the noise probability distribution model of the memory chip image includes:

[0061] Determine a suitable environment for noise analysis of the image of the memory chip;

[0062] By analyzing the noise in a suitable environment, the image of the memory chip is preprocessed to obtain a processed image of the memory chip.

[0063] Identify the noise type of the processed memory chip image;

[0064] Based on the noise type, the noise intensity of the processed memory chip image is analyzed;

[0065] Based on the noise intensity, a noise probability distribution model for the processed memory chip image is constructed.

[0066] The "suitable environment for noise analysis" refers to providing stable and consistent environmental conditions for the memory chip image during the noise analysis process, enabling accurate noise identification and analysis. The "processing the memory chip image" refers to preprocessing the original memory chip image to improve image quality and facilitate noise analysis and subsequent processing. Preprocessing may include steps such as adjusting brightness and contrast, and filtering for noise reduction. The "noise type" refers to the types of noise present in the memory chip image, such as Gaussian noise, salt-and-pepper noise, and impulse noise. The "noise intensity" refers to the strength or density of the noise, typically quantified by the mean and standard deviation. The "noise probability distribution model" refers to a constructed probability distribution model that accurately describes the noise characteristics in the memory chip image.

[0067] Further, the step of constructing a noise probability distribution model of the memory chip image based on the noise intensity includes:

[0068] Based on the noise intensity, determine the mean noise intensity and standard deviation of the noise intensity of the processed storage chip image;

[0069] Based on the noise intensity, the mean noise intensity, and the standard deviation of the noise intensity, the noise probability function for processing the image on the memory chip is constructed using the following formula: ,in, This represents the noise probability function. This indicates the noise level in the processed image of the memory chip. This represents the standard deviation of noise intensity for processing images on memory chips. This represents the mean noise intensity of the image processed from the memory chip. The base of the natural logarithm. Indicates noise intensity Approximately the mean noise intensity The degree;

[0070] Based on the noise probability function, a noise probability distribution model for the memory chip image is constructed.

[0071] Based on the aforementioned noise probability distribution model, this application constructs a denoising function for the memory chip image to remove noise from the image, thereby improving image quality and the accuracy of subsequent analysis. The model parameters refer to an algorithm or method designed to estimate the noise in the memory chip image based on the parameters of the noise probability distribution model (such as mean, variance, etc.), and subtract the noise from the original image to obtain the denoised image.

[0072] It should be explained that the denoised memory chip image refers to the memory chip image obtained after processing by a denoising function. Specifically, the noise removal of the memory chip image based on the denoising function means estimating the noise value of each pixel using the denoising function and subtracting that noise value from the original image to obtain the denoised image.

[0073] S3. Obtain the structure recognition training image of the semiconductor memory chip, construct an adaptive threshold segmentation model for the structure recognition training image, and use the adaptive threshold segmentation model to segment the structure recognition training image to obtain a segmented training image.

[0074] It should be explained that the structural recognition training images refer to images containing key structural features of memory chips. These images are used to train the structural recognition model, enabling it to accurately identify and classify different parts of the memory chip, such as memory cells, circuit connections, and defects. The structural recognition training images are typically acquired through methods such as laboratory sampling, production site sampling, historical data, and simulation generation.

[0075] In detail, the adaptive threshold segmentation model refers to a model that can automatically adjust the segmentation threshold based on image features. This model can adaptively segment training images of memory chips to accurately identify and classify different parts of the memory chip. The steps for building the adaptive threshold segmentation model include: designing the model architecture, training the model architecture using labeled structure recognition training images, evaluating the performance of the segmentation model after training, adjusting the model structure and parameters based on the evaluation results, performing iterative optimization, and finally integrating the trained adaptive threshold segmentation model into the production environment. Through these steps, an adaptive threshold segmentation model can be built for structure recognition and classification of memory chip images.

[0076] This application utilizes the adaptive threshold segmentation model to segment the structure recognition training image, and the resulting segmented training image can be used to train and optimize the structure recognition model, thereby improving production efficiency and product quality.

[0077] Specifically, the step of segmenting the structure recognition training image using the adaptive threshold segmentation model to obtain a segmented training image includes:

[0078] Analyze the HOG graphs of the structure recognition training images;

[0079] Based on the HOG image, the training image features of the structure recognition training image are identified;

[0080] Based on the features of the training image, the adaptive threshold segmentation model is used to determine the segmentation threshold of the corresponding pixel in the structure recognition training image;

[0081] Based on the segmentation threshold, the structure recognition training image is segmented to obtain the segmented training image.

[0082] The HOG image is obtained by calculating the gradient direction and intensity of each pixel in the image and statistically plotting the histogram of gradient values ​​in these directions. The training image features refer to the features extracted from the structure recognition training image, which can be used to train and recognize the model. The segmentation threshold is the threshold used to determine whether a pixel belongs to a segmentation region in the adaptive threshold segmentation model. The segmented training image refers to the image obtained after segmenting the structure recognition training image through the adaptive threshold segmentation model.

[0083] Furthermore, based on the HOG image, the recognition of training image features for the structure recognition training image can be performed using statistical methods (such as feature selection), model-based methods (such as regularization techniques), or visualization-based methods (such as feature visualization analysis) to obtain feature evaluation results. Based on these results, the most useful features are selected to obtain the training image features. This can be achieved by retaining the top n features, using feature selection algorithms (such as recursive feature elimination, model-based feature selection, etc.), or combining multiple strategies.

[0084] S4. Construct a deep learning network for the segmentation training images, wherein the deep learning network includes a CNN network, an RNN network, and a GAN network. The CNN network is used to extract hierarchical features of the segmentation training images, the RNN network is used to analyze the temporal relationship of the corresponding image structure of the segmentation training images, and the GAN network is used to construct diverse training images for the segmentation training images.

[0085] It should be explained that the CNN network refers to a deep learning network specifically designed for processing image data. It extracts local features of an image through convolutional layers and reduces the size of the feature maps through pooling layers, thereby reducing computational complexity. The RNN network refers to a deep learning network capable of processing sequential data. It maintains its internal state through recurrent units, enabling the model to handle sequential data of arbitrary length. The GAN network refers to a generative model composed of two neural networks: a generator and a discriminator. The generator attempts to generate images as realistic as possible, while the discriminator attempts to distinguish between generated and real images.

[0086] Specifically, the step of extracting hierarchical features from the segmentation training image using the CNN network includes:

[0087] The segmentation training images are standardized to obtain standard segmentation training images;

[0088] Determine the CNN network architecture for the standard segmentation training images;

[0089] The CNN network architecture is trained using the standard segmented training images to obtain a trained CNN network;

[0090] Identify the prediction loss of the trained CNN network;

[0091] Based on the predicted loss, the weights of the trained CNN network are adjusted using a preset backpropagation algorithm to obtain the target CNN network;

[0092] The hierarchical features of the segmentation training image are extracted based on the target CNN network, wherein the hierarchical features include low-level features and high-level features.

[0093] The standard segmentation training images refer to segmentation training images that have undergone standardization. Standardization typically includes normalization, scaling the pixel values ​​of the image to a specific range, such as between 0 and 1, to reduce differences between different images and make network training more stable and efficient. The CNN network architecture refers to the hierarchical structure of a CNN, including convolutional layers, pooling layers, and fully connected layers. The design of the network architecture affects the network's learning ability and performance. Training the CNN network refers to the process of training the CNN network using the segmentation training image dataset. The prediction loss refers to the difference between the network's prediction result and the actual label. The backpropagation algorithm is a method used to calculate the gradient of the network weights and adjust the network weights accordingly. The target CNN network refers to the optimized network obtained after adjusting the weights through the backpropagation algorithm. The low-level features refer to the features extracted by the early convolutional layers of the CNN network, which typically reflect low-level visual information of the image, such as edges and textures. The high-level features refer to the features extracted by the later convolutional layers of the CNN network, which typically reflect high-level visual information of the image, such as object and category features.

[0094] Furthermore, the prediction loss of the trained CNN network can be realized through a loss function, which is used to quantify the accuracy of the prediction. Commonly used loss functions include cross-entropy loss, mean squared error, and other functions.

[0095] This application utilizes the RNN network to analyze the temporal relationship of the image structure corresponding to the segmented training image, thereby capturing the temporal dependency in the image sequence and improving the accuracy and reliability of chip structure composition recognition.

[0096] In detail, the step of using the RNN network to analyze the temporal relationship of the image structure corresponding to the segmented training image includes:

[0097] The segmented training images are serialized to obtain sequential training images;

[0098] The RNN network architecture is trained using the standard segmented training images to obtain the trained RNN network;

[0099] When the performance of the trained RNN network meets the preset performance threshold, the trained RNN network is used as the target RNN network.

[0100] Based on the target RNN network, the hidden state and time-step output of the sequence training images are analyzed using the following formula: , ,in, Indicates time step The hidden state, Represents training images in sequence. Indicates time step The hidden state, This refers to LSTM (Long Short-Term Memory) or GRU (Gated Recurrent Unit) neural network units. Indicates time step Time step output, This represents a fully connected layer, which contains multiple neurons, each of which is connected to every neuron in the input layer;

[0101] Based on the hidden state and time step output, the temporal relationship of the image structure corresponding to the sequence training images is analyzed.

[0102] The training sequence images refer to a sequence of segmentation training images arranged chronologically. These images can represent the state of the chip at different time points or under different conditions. The trained RNN network refers to a network trained using the segmentation training image sequence. The performance threshold is a preset performance indicator used to determine whether the performance of the trained RNN network reaches the expected level. When the performance of the trained RNN network reaches or exceeds this threshold, it can be considered effective and used as the target RNN network. The target RNN network refers to the optimized network obtained through the training process. The weights of this network are adjusted to better adapt to the training data and improve the accuracy of prediction. The hidden state is an internal state maintained by the RNN network at time step t when processing sequential data. It contains information from all previous time steps and affects the output of the current time step. The time step output refers to the output of the RNN network at time step t, which is usually determined by the input of the current time step and the hidden state of the previous time step. The image structure refers to the chip structure in the segmentation training images, including storage units, circuit connections, defects, etc. The temporal relationship refers to the relationship between the image structure and time. Both of these units are designed to process and remember long-term dependencies in long sequences, and they are better able to handle the temporal span of sequence data compared to traditional RNN units. LSTM Unit: An LSTM unit contains three gates (input gate, forget gate, and output gate) and a cell state, which work together to control the flow and storage of information. GRU Unit: A GRU unit is a simpler RNN unit that combines the forget gate and input gate of an LSTM unit into a single gate and shares a hidden state, making GRU more efficient in certain situations. The fully connected layers in RNN networks are typically used to transform the hidden state of the last time step of the sequence into the final output, or to merge hidden state information from multiple time steps.

[0103] Furthermore, the step of analyzing the temporal relationship of the image structure corresponding to the sequence training images based on the hidden state and time step output includes: the hidden state is an internal state maintained by the RNN network at time step t when processing sequence data. It contains information from all previous time steps and affects the output of the current time step. In this way, the hidden state can integrate contextual information to help the network understand the temporal relationship in the sequence. The time step output is the output of the RNN network at time step t, which is usually determined by the input of the current time step and the hidden state of the previous time step. By analyzing the time step output, the structural changes of the images at different time points in the sequence can be understood, thereby modeling the temporal relationship. By analyzing the hidden state and the time step output, the trend and pattern of image structure changes over time can be understood, which helps to understand the dynamic behavior of the chip at different production stages or under different environmental conditions.

[0104] Optionally, the GAN network is used to construct diversified training images for the segmentation training images. These diversified training images refer to new images generated by the GAN network that are similar to the original segmentation training images but have different features. These images can be used to expand the training dataset and improve the model's generalization ability and robustness. Specifically, the GAN network consists of two main parts: a generator and a discriminator. The generator is responsible for generating new images, while the discriminator is responsible for determining whether the input image is generated by the generator or a real segmentation training image. During training, the generator continuously improves its ability to generate images, while the discriminator continuously improves its ability to distinguish between real and generated images.

[0105] S5. Using the hierarchical features, the temporal relationship, and the diverse training images, establish a compositional structure recognition model for the denoised memory chip image. Analyze the structural composition of the denoised memory chip image based on the compositional structure recognition model, identify the abnormal coefficients of the structural composition, and construct a compositional structure analysis report for the semiconductor memory chip based on the structural composition and the abnormal coefficients.

[0106] By utilizing the hierarchical features, temporal relationships, and diverse training images, a structural identification model for the denoised memory chip image is established. This model can accurately identify key structures within the memory chip, such as memory cells and circuit connections, thereby improving production efficiency and product quality. Specifically, the structural identification model refers to a model capable of identifying and classifying different parts of a memory chip. A training set is constructed using hierarchical features, temporal relationships, and diverse training images. This training set is then used to train the model. By adjusting the model parameters, the model can accurately identify key structures within the memory chip.

[0107] Based on the aforementioned structural identification model, this application analyzes the structural composition of the denoised memory chip image to better understand the working principle and performance characteristics of the memory chip, thereby better identifying the structural composition of the memory chip.

[0108] In detail, the analysis of the structural composition of the denoised memory chip image based on the structural composition recognition model can be achieved by providing the denoised memory chip image as input to the structural composition recognition model, which then analyzes the denoised memory chip image and outputs the structural composition of the denoised memory chip image. The structural composition includes memory cells, circuit layout, key connections, defect detection, performance indicators, and other components.

[0109] This application analyzes the structural composition of a denoised memory chip image by identifying anomaly coefficients in the structural composition, thereby identifying potential anomalies. The anomaly coefficient refers to the degree of anomaly present in the structural composition. Specifically, the anomaly coefficient can be analyzed by comparing it with a preset standard structural composition. This standard structural composition includes the layout of memory cells, connection methods, defect limitations, and other aspects.

[0110] Finally, based on the aforementioned structural composition and anomaly coefficients, this application constructs a structural composition analysis report for the semiconductor memory chip, which can better facilitate understanding of the chip's working principle and performance characteristics. The structural composition analysis report details the results of analyzing the semiconductor memory chip's structural composition using technical means, including analysis methods, structural composition analysis, anomaly detection, and evaluation.

[0111] Based on the aforementioned structural recognition requirements, this application constructs a microscope cluster for the semiconductor memory chip, which can monitor the structural images of the semiconductor memory chip and provide a foundation for subsequent structural analysis. Optionally, based on the microscope cluster, this application acquires images of the semiconductor memory chip, which can improve the basic images for subsequent microstructural analysis of the chip. This application constructs a noise probability distribution model for the memory chip images, which can provide a foundation for subsequent image denoising algorithm design, thereby improving the reliability of image noise removal. Based on the noise probability distribution model, this application constructs a denoising function for the memory chip images, which can remove noise from the image, improve image quality and the accuracy of subsequent analysis. This application utilizes the adaptive threshold segmentation model for the... Segmenting training images for structural recognition yields segmented training images that can be used to train and optimize the structural recognition model, improving production efficiency and product quality. This application utilizes the RNN network to analyze the temporal relationships of the corresponding image structures in the segmented training images, capturing the temporal dependencies in the image sequence, thereby improving the accuracy and reliability of chip structure composition recognition. Finally, based on the structural composition recognition model, this application analyzes the structural composition of the denoised memory chip image to better understand the working principle and performance characteristics of the memory chip, thus better identifying the composition structure of the memory chip. Based on the structural composition and the anomaly coefficients, a structural analysis report of the semiconductor memory chip is constructed, further enhancing the understanding of the memory chip's working principle and performance characteristics. Therefore, this application can improve the accuracy of semiconductor memory chip structural composition recognition.

[0112] Figure 2 shows a functional block diagram of an intelligent identification system for the composition structure of a semiconductor memory chip provided in an embodiment of this application.

[0113] The intelligent identification system 200 based on the composition structure of a semiconductor memory chip described in this application can be installed in an electronic device. Depending on the functions implemented, the intelligent identification system 200 based on the composition structure of a semiconductor memory chip may include a memory chip image acquisition module 201, a chip image noise removal module 202, a training image segmentation module 203, a segmentation training image analysis module 204, and a composition structure analysis module 205. The module described in this application can also be referred to as a unit, which refers to a series of computer program segments that can be executed by the processor of an electronic device and can perform a fixed function, and which are stored in the memory of the electronic device.

[0114] In this embodiment, the functions of each module / unit are as follows:

[0115] The memory chip image acquisition module 201 is used to determine the structural identification requirements of the semiconductor memory chip, construct a microscope cluster of the semiconductor memory chip based on the structural identification requirements, and acquire memory chip images of the semiconductor memory chip based on the microscope cluster.

[0116] The chip image noise removal module 202 is used to construct a noise probability distribution model of the memory chip image, construct a denoising function for the memory chip image based on the noise probability distribution model, and remove noise from the memory chip image based on the denoising function to obtain a denoised memory chip image.

[0117] The training image segmentation module 203 is used to acquire the structure recognition training image of the semiconductor memory chip, construct an adaptive threshold segmentation model for the structure recognition training image, and use the adaptive threshold segmentation model to segment the structure recognition training image to obtain a segmented training image.

[0118] The segmentation training image analysis module 204 is used to construct a deep learning network for the segmentation training image. The deep learning network includes a CNN network, an RNN network, and a GAN network. The CNN network is used to extract hierarchical features of the segmentation training image, the RNN network is used to analyze the temporal relationship of the corresponding image structure of the segmentation training image, and the GAN network is used to construct diversified training images of the segmentation training image.

[0119] The composition structure analysis module 205 is used to establish a composition structure recognition model of the denoised memory chip image using the hierarchical features, the temporal relationship, and the diverse training images; analyze the structural composition of the denoised memory chip image based on the composition structure recognition model; identify the abnormal coefficients of the structural composition; and construct a composition structure analysis report of the semiconductor memory chip based on the structural composition and the abnormal coefficients.

[0120] In detail, each module in the intelligent identification system 200 based on the composition structure of semiconductor memory chips described in the embodiments of this application adopts the same technical means as the intelligent identification method based on the composition structure of semiconductor memory chips described in the accompanying drawings, and can produce the same technical effect, which will not be repeated here.

[0121] One embodiment of this application provides an electronic device that implements a method for intelligent identification of the composition structure based on semiconductor memory chips.

[0122] Referring to Figure 3, the electronic device may include a processor 30, a memory 31, a communication bus 32, and a communication interface 33. It may also include a computer program stored in the memory 31 and capable of running on the processor 30, such as a program for intelligent identification of the composition structure based on semiconductor memory chips.

[0123] In some embodiments, the processor may be composed of integrated circuits, such as a single packaged integrated circuit or multiple integrated circuits with the same or different functions, including combinations of one or more central processing units (CPUs), microprocessors, digital processing chips, graphics processors, and various control chips. The processor is the control unit of the electronic device, connecting various components of the device via various interfaces and lines. It executes programs or modules stored in the memory (e.g., executing intelligent identification programs based on the semiconductor memory chip structure) and calls data stored in the memory to perform various functions and process data within the electronic device.

[0124] The memory includes at least one type of readable storage medium, including flash memory, portable hard drive, multimedia card, card-type memory (e.g., SD or DX memory), magnetic memory, magnetic disk, optical disk, etc. In some embodiments, the memory can be an internal storage unit of an electronic device, such as a portable hard drive. In other embodiments, the memory can be an external storage device of the electronic device, such as a plug-in portable hard drive, Smart Media Card (SMC), Secure Digital (SD) card, Flash Card, etc. Furthermore, the memory can include both internal and external storage units of the electronic device. The memory can be used not only to store application software and various types of data installed on the electronic device, such as code for intelligent identification programs based on the composition structure of semiconductor memory chips, but also to temporarily store data that has been output or will be output.

[0125] The communication bus can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. This bus can be divided into an address bus, a data bus, a control bus, etc. The bus is configured to enable communication between the memory and at least one processor, etc.

[0126] The communication interface is used for communication between the aforementioned electronic device and other devices, including a network interface and a user interface. Optionally, the network interface may include a wired interface and / or a wireless interface (such as a Wi-Fi interface, Bluetooth interface, etc.), typically used to establish communication connections between the electronic device and other electronic devices. The user interface may be a display, an input unit (such as a keyboard), and optionally, a standard wired or wireless interface. Optionally, in some embodiments, the display may be an LED display, a liquid crystal display, a touch-sensitive liquid crystal display, or an OLED (Organic Light-Emitting Diode) touchscreen, etc. The display may also be appropriately referred to as a screen or display unit, used to display information processed in the electronic device and to display a visual user interface.

[0127] For example, although not shown, the electronic device may also include a power supply (such as a battery) to power the various components. Preferably, the power supply can be logically connected to the at least one processor through a power management system, thereby enabling functions such as charging management, discharging management, and power consumption management through the power management system. The power supply may also include one or more DC or AC power supplies, recharging systems, power fault detection circuits, power converters or inverters, power status indicators, and other arbitrary components. The electronic device may also include various sensors, Bluetooth modules, Wi-Fi modules, etc., which will not be described in detail here.

[0128] It should be understood that the embodiments described are for illustrative purposes only and are not limited to this structure in the scope of the patent application.

[0129] The intelligent identification program based on the composition structure of a semiconductor memory chip stored in the memory of the electronic device is a combination of multiple instructions. When run in the processor, it can achieve the following:

[0130] The structural identification requirements of the semiconductor memory chip are determined. Based on the structural identification requirements, a microscope cluster for the semiconductor memory chip is constructed. Based on the microscope cluster, images of the semiconductor memory chip are acquired.

[0131] A noise probability distribution model of the memory chip image is constructed. Based on the noise probability distribution model, a denoising function of the memory chip image is constructed. Based on the denoising function, noise is removed from the memory chip image to obtain a denoised memory chip image.

[0132] Obtain a structural recognition training image of the semiconductor memory chip, construct an adaptive threshold segmentation model for the structural recognition training image, and use the adaptive threshold segmentation model to segment the structural recognition training image to obtain a segmented training image;

[0133] A deep learning network for segmenting training images is constructed, wherein the deep learning network includes a CNN network, an RNN network, and a GAN network. The CNN network is used to extract hierarchical features of the segmentation training images, the RNN network is used to analyze the temporal relationship of the corresponding image structure of the segmentation training images, and the GAN network is used to construct diversified training images of the segmentation training images.

[0134] Using the hierarchical features, the temporal relationships, and the diverse training images, a compositional structure recognition model for the denoised memory chip image is established. Based on the compositional structure recognition model, the structural composition of the denoised memory chip image is analyzed, and the abnormal coefficients of the structural composition are identified. Based on the structural composition and the abnormal coefficients, a compositional structure analysis report for the semiconductor memory chip is constructed.

[0135] Specifically, the processor's specific implementation method of the above instructions can be found in the description of the relevant steps in the corresponding embodiments of the accompanying drawings, and will not be repeated here.

[0136] Furthermore, if the modules / units integrated into the electronic device are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. The computer-readable storage medium can be volatile or non-volatile. For example, the computer-readable medium may include: any entity or system capable of carrying the computer program code, a recording medium, a USB flash drive, a portable hard drive, a magnetic disk, an optical disk, a computer memory, or a read-only memory (ROM).

[0137] This application also provides a computer-readable storage medium storing a computer program, which, when executed by a processor of an electronic device, can perform the following:

[0138] The structural identification requirements of the semiconductor memory chip are determined. Based on the structural identification requirements, a microscope cluster for the semiconductor memory chip is constructed. Based on the microscope cluster, images of the semiconductor memory chip are acquired.

[0139] A noise probability distribution model of the memory chip image is constructed. Based on the noise probability distribution model, a denoising function of the memory chip image is constructed. Based on the denoising function, noise is removed from the memory chip image to obtain a denoised memory chip image.

[0140] Obtain a structural recognition training image of the semiconductor memory chip, construct an adaptive threshold segmentation model for the structural recognition training image, and use the adaptive threshold segmentation model to segment the structural recognition training image to obtain a segmented training image;

[0141] A deep learning network for segmenting training images is constructed, wherein the deep learning network includes a CNN network, an RNN network, and a GAN network. The CNN network is used to extract hierarchical features of the segmentation training images, the RNN network is used to analyze the temporal relationship of the corresponding image structure of the segmentation training images, and the GAN network is used to construct diversified training images of the segmentation training images.

[0142] Using the hierarchical features, the temporal relationships, and the diverse training images, a compositional structure recognition model for the denoised memory chip image is established. Based on the compositional structure recognition model, the structural composition of the denoised memory chip image is analyzed, and the abnormal coefficients of the structural composition are identified. Based on the structural composition and the abnormal coefficients, a compositional structure analysis report for the semiconductor memory chip is constructed.

[0143] In the several embodiments provided in this application, it should be understood that the disclosed devices, systems, and methods can be implemented in other ways. For example, the system embodiments described above are merely illustrative; for instance, the division of modules is only a logical functional division, and other division methods may be used in actual implementation.

[0144] The modules described as separate components may or may not be physically separate. The components shown as modules may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0145] Furthermore, the functional modules in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or in the form of hardware plus software functional modules.

[0146] It will be apparent to those skilled in the art that this application is not limited to the details of the exemplary embodiments described above, and that this application can be implemented in other specific forms without departing from the spirit or essential characteristics of this application.

[0147] Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of this application is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be embraced within this application. No appended diagram markings in the claims should be construed as limiting the scope of the claims.

[0148] The embodiments of this application can acquire and process relevant data based on artificial intelligence technology. Artificial intelligence (AI) refers to the theories, methods, technologies, and application systems that use digital computers or machines controlled by digital computers to simulate, extend, and expand human intelligence, perceive the environment, acquire knowledge, and use that knowledge to obtain optimal results.

[0149] Furthermore, it is clear that the word "comprising" does not exclude other units or steps, and the singular does not exclude the plural. Multiple units or systems stated in a system claim may also be implemented by a single unit or system through software or hardware. The terms "first," "second," etc., are used to indicate names and do not indicate any specific order.

[0150] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application and are not intended to limit it. Although this application has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of this application without departing from the spirit and scope of the technical solutions of this application.

Claims

1. A method for intelligent identification of the composition structure of a semiconductor memory chip, characterized in that, The method includes: The structural identification requirements of the semiconductor memory chip are determined. Based on the structural identification requirements, a microscope cluster for the semiconductor memory chip is constructed. Based on the microscope cluster, images of the semiconductor memory chip are acquired. A noise probability distribution model of the memory chip image is constructed. Based on the noise probability distribution model, a denoising function of the memory chip image is constructed. Based on the denoising function, noise is removed from the memory chip image to obtain a denoised memory chip image. Obtain a structural recognition training image of the semiconductor memory chip, construct an adaptive threshold segmentation model for the structural recognition training image, and use the adaptive threshold segmentation model to segment the structural recognition training image to obtain a segmented training image; A deep learning network for segmenting training images is constructed, wherein the deep learning network includes a CNN network, an RNN network, and a GAN network. The CNN network is used to extract hierarchical features of the segmentation training images, the RNN network is used to analyze the temporal relationship of the corresponding image structure of the segmentation training images, and the GAN network is used to construct diversified training images of the segmentation training images. Using the hierarchical features, the temporal relationships, and the diverse training images, a compositional structure recognition model for the denoised memory chip image is established. Based on the compositional structure recognition model, the structural composition of the denoised memory chip image is analyzed, and the abnormal coefficients of the structural composition are identified. Based on the structural composition and the abnormal coefficients, a compositional structure analysis report for the semiconductor memory chip is constructed.

2. The intelligent identification method for the composition structure of semiconductor memory chips as described in claim 1, characterized in that, The requirement to determine the structure identification of semiconductor memory chips includes: Obtain the design drawings of the semiconductor memory chip; Based on the design drawings, identify the key structural elements of the semiconductor memory chip; Identify the structural element characteristics of the key structural elements; The identification accuracy requirements of the semiconductor memory chip are analyzed based on the structural features described above. Based on the aforementioned recognition accuracy requirements, the structural recognition requirements for semiconductor memory chips are determined.

3. The intelligent identification method for the composition structure of semiconductor memory chips as described in claim 2, characterized in that, The structural feature characteristics for identifying the key structural elements are extracted through edge detection.

4. The intelligent identification method for the composition structure of semiconductor memory chips as described in claim 1, characterized in that, The construction of the microscope cluster for the semiconductor memory chip based on the structural identification requirement includes: Based on the aforementioned structural identification requirements, the microscopic parameters of the semiconductor memory chip are determined, wherein the microscopic parameters include resolution, magnification, and imaging speed. Based on the design drawings corresponding to the structural identification requirements, the microscope layout of the semiconductor memory chip is constructed. Based on the microscope indicators, configure the target microscope corresponding to the layout nodes of the microscope layout; Construct a data transmission network for the target microscope; The target microscope is calibrated through the data transmission network to obtain a calibrated microscope; Construct the initial microscope cluster for the calibration microscope; Analyze the synergy coefficient of the initial microscope cluster; When the coordination coefficient meets the preset coordination threshold, the initial microscope cluster is taken as the microscope cluster.

5. The intelligent identification method for the composition structure of semiconductor memory chips as described in claim 4, characterized in that, The analysis of the synergy coefficient of the initial microscope cluster includes: The initial microscope cluster was simulated, and the simulation results were obtained. The simulation results are divided into normal operation results and abnormal operation results; Based on the normal operation results, analyze the image quality, data transmission efficiency, and system response time of the initial microscope cluster in operation simulation; Based on the results of the abnormal operation, the fault recovery parameters and maintainability coefficient of the initial microscope cluster are determined; Based on the image quality, data transmission efficiency, system response time, fault recovery parameters, and maintainability coefficient, the coordination coefficient of the initial microscope cluster is calculated using the following formula: ,in This represents the coordination coefficient of the initial microscope cluster. Indicates image quality, Indicates data transmission efficiency. Indicates system response time. This indicates the fault detection speed corresponding to the fault recovery parameters. This indicates the fault response time corresponding to the fault recovery parameters. This indicates the fault handling time corresponding to the fault recovery parameters. This indicates the fault recovery parameters and the corresponding fault reconstruction time. This represents the maintainability factor.

6. The intelligent identification method for the composition structure of semiconductor memory chips as described in claim 1, characterized in that, The construction of the noise probability distribution model for the image of the memory chip includes: Determine a suitable environment for noise analysis of the image of the memory chip; By analyzing the noise in a suitable environment, the image of the memory chip is preprocessed to obtain a processed image of the memory chip. Identify the noise type of the processed memory chip image; Based on the noise type, the noise intensity of the processed memory chip image is analyzed; Based on the noise intensity, a noise probability distribution model for the processed memory chip image is constructed.

7. The intelligent identification method for the composition structure of semiconductor memory chips as described in claim 6, characterized in that, The step of constructing a noise probability distribution model for the memory chip image based on the noise intensity includes: Based on the noise intensity, determine the mean noise intensity and standard deviation of the noise intensity of the processed storage chip image; Based on the noise intensity, the mean noise intensity, and the standard deviation of the noise intensity, the noise probability function for processing the image on the memory chip is constructed using the following formula: ,in, This represents the noise probability function. This indicates the noise level in the processed image of the memory chip. This represents the standard deviation of noise intensity for processing images on memory chips. This represents the mean noise intensity of the image processed from the memory chip. The base of the natural logarithm. Indicates noise intensity Approximately the average noise intensity The degree; Based on the noise probability function, a noise probability distribution model for the memory chip image is constructed.

8. The intelligent identification method for the composition structure of semiconductor memory chips as described in claim 1, characterized in that, The step of segmenting the structure recognition training image using the adaptive threshold segmentation model to obtain a segmented training image includes: Analyze the HOG graphs of the structure recognition training images; Based on the HOG image, the training image features of the structure recognition training image are identified; Based on the features of the training image, the adaptive threshold segmentation model is used to determine the segmentation threshold of the corresponding pixel in the structure recognition training image; Based on the segmentation threshold, the structure recognition training image is segmented to obtain the segmented training image.

9. The intelligent identification method for the composition structure of a semiconductor memory chip as described in claim 8, characterized in that, The steps for constructing the adaptive threshold segmentation model include: Design a model architecture, train the model architecture to recognize training images using the labeled structure, and evaluate the performance of the segmentation model after training; Adjust the model structure and parameters based on the evaluation results, and perform iterative optimization. Finally, the trained adaptive threshold segmentation model is integrated into the production environment.

10. The intelligent identification method for the composition structure of a semiconductor memory chip as described in claim 1, characterized in that, The step of extracting hierarchical features from the segmentation training image using the CNN network includes: The segmentation training images are standardized to obtain standard segmentation training images; Determine the CNN network architecture for the standard segmentation training images; The CNN network architecture is trained using the standard segmented training images to obtain a trained CNN network; Identify the prediction loss of the trained CNN network; Based on the predicted loss, the weights of the trained CNN network are adjusted using a preset backpropagation algorithm to obtain the target CNN network; The hierarchical features of the segmentation training image are extracted based on the target CNN network, wherein the hierarchical features include low-level features and high-level features.

11. The intelligent identification method for the composition structure of a semiconductor memory chip as described in claim 1, characterized in that, The step of analyzing the temporal relationship of the image structure corresponding to the segmented training image using the RNN network includes: The segmented training images are serialized to obtain sequential training images; The RNN network architecture is trained using the standard segmented training images to obtain the trained RNN network; When the performance of the trained RNN network meets the preset performance threshold, the trained RNN network is used as the target RNN network. Based on the target RNN network, the hidden state and time-step output of the sequence training images are analyzed using the following formula: ， ,in, Indicates time step The hidden state, Represents training images in sequence. Indicates time step The hidden state, This refers to LSTM (Long Short-Term Memory) or GRU (Gated Recurrent Unit) neural network units. Indicates time step Time step output, This represents a fully connected layer, which contains multiple neurons, each of which is connected to every neuron in the input layer; Based on the hidden state and time step output, the temporal relationship of the image structure corresponding to the sequence training images is analyzed.

12. A smart identification system for the composition structure of a semiconductor memory chip, characterized in that, The system is used to perform the intelligent identification method for the composition structure of semiconductor memory chips as described in any one of claims 1-11, the system comprising: A memory chip image acquisition module is used to determine the structural identification requirements of a semiconductor memory chip, construct a microscope cluster of the semiconductor memory chip based on the structural identification requirements, and acquire memory chip images of the semiconductor memory chip based on the microscope cluster. The chip image noise removal module is used to construct a noise probability distribution model of the memory chip image, construct a denoising function for the memory chip image based on the noise probability distribution model, and remove noise from the memory chip image based on the denoising function to obtain a denoised memory chip image. The training image segmentation module is used to acquire the structure recognition training image of the semiconductor memory chip, construct an adaptive threshold segmentation model for the structure recognition training image, and use the adaptive threshold segmentation model to segment the structure recognition training image to obtain a segmented training image. The segmentation training image analysis module is used to construct a deep learning network for the segmentation training images. The deep learning network includes a CNN network, an RNN network, and a GAN network. The CNN network is used to extract hierarchical features of the segmentation training images, the RNN network is used to analyze the temporal relationship of the corresponding image structure of the segmentation training images, and the GAN network is used to construct diversified training images of the segmentation training images. The composition structure analysis module is used to establish a composition structure recognition model of the denoised memory chip image by utilizing the hierarchical features, the temporal relationship, and the diverse training images; analyze the structural composition of the denoised memory chip image based on the composition structure recognition model; identify the abnormal coefficients of the structural composition; and construct a composition structure analysis report of the semiconductor memory chip based on the structural composition and the abnormal coefficients.

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