Chip control circuit, method and memory chip

Abstract

This application relates to a chip control circuit, method, and memory chip. The chip control circuit includes a signal detection trigger module and a circuit enable control module. The signal detection trigger module detects address level transition signals based on address signals and outputs a chip wake-up signal in combination with a chip select signal. Then, the circuit enable control module controls the working state of the chip auxiliary circuit based on the chip wake-up signal and the chip select signal, combined with the enable signal of the chip auxiliary circuit. This enables the chip auxiliary circuit to be woken up on demand, effectively reducing the ineffective power consumption of the chip in standby, low load, or no read / write operation scenarios. It solves the problem of high power consumption caused by the continuous operation of the chip detection circuit in the prior art, and can effectively improve the energy efficiency ratio of the chip and the battery life of the chip device.

Description

Technical Field

[0001] This application relates to the field of circuit technology, and more specifically, to a chip control circuit, method, and memory chip. Background Technology

[0002] NOR flash memory, a commonly used non-volatile memory chip, is widely used in various electronic systems such as consumer electronics, industrial control, and IoT devices. Address signals are used to accurately locate target memory cells, while chip select signals are used to activate specific NOR flash chips. The rapid and accurate detection of both is a core prerequisite for ensuring stable execution of data read and write operations.

[0003] Existing NOR FLASH address and chip select signal detection circuits generally adopt a continuous power-on operation design mode to pursue timely signal response. In this mode, regardless of whether the system has read / write needs, whether there is a valid signal input on the address bus, or whether the chip select signal is activated, read-related auxiliary circuits such as address decoding circuits and data buffer circuits are in a continuous working state.

[0004] This design causes the chip to generate a lot of unnecessary power consumption even in standby, low-load, or no-read / write scenarios, which severely restricts the battery life of portable devices, IoT terminals, and other products that rely on battery power. At the same time, the continuous operation of the circuit increases the chip's heat loss and reduces the stability of the system in long-term operation.

[0005] To address the aforementioned issues, existing technologies urgently need improvement. Summary of the Invention

[0006] The purpose of this application is to provide a chip control circuit, method, and memory chip to solve the problem of high power consumption caused by the continuous operation of the chip detection circuit in the prior art.

[0007] In a first aspect, this application provides a chip control circuit, including: a signal detection trigger module and a circuit enable control module; The signal detection trigger module is used to detect the address level transition signal based on the chip's address signal, and output the chip wake-up signal based on the address level transition signal and the chip select signal. The circuit enable control module is used to control the working state of the chip auxiliary circuit based on the chip wake-up signal and chip select signal, combined with the enable signal of the chip auxiliary circuit.

[0008] Through the above scheme, this application uses a signal detection trigger module to detect address level transition signals based on address signals and outputs a chip wake-up signal in combination with chip select signals. Then, the circuit enable control module controls the working state of the chip auxiliary circuit based on the chip wake-up signal and chip select signal, combined with the enable signal of the chip auxiliary circuit. This enables the chip auxiliary circuit to be woken up on demand, effectively reducing the ineffective power consumption of the chip in standby, low load, or no read / write operation scenarios. It solves the problem of high power consumption caused by the continuous operation of the chip detection circuit in the prior art, and can effectively improve the energy efficiency ratio of the chip and the battery life of the chip device.

[0009] Optionally, the signal detection trigger module includes: an address detection circuit submodule, a chip select detection circuit submodule, and a wake-up submodule; The address detection circuit submodule is used to detect the address level transition signal based on the address signal, and output the address detection signal to the wake-up submodule based on the address level transition signal. The chip select detection circuit submodule is used to detect the falling edge signal of the chip select signal based on the chip select signal, and output the chip select detection signal to the wake-up submodule based on the falling edge signal of the chip select signal. The wake-up submodule is used to output a chip wake-up signal to the circuit enable control module based on the address detection signal and the chip select detection signal.

[0010] Optionally, the address level transition signal includes an address rising edge signal and an address falling edge signal. The above address detection circuit submodule includes: an address rising edge detection branch, an address falling edge detection branch, and an address detection output unit. The address rising edge detection branch is used to detect the address rising edge signal based on the address signal and output the address rising edge detection signal corresponding to the address rising edge signal. The address falling edge detection branch is used to detect the address falling edge signal based on the address signal and output the address falling edge detection signal corresponding to the address falling edge signal. The address detection output unit includes: a first NOR gate and a first inverter; The first input terminal of the first NOR gate is electrically connected to the output terminal of the address rising edge detection branch, the second input terminal of the first NOR gate is electrically connected to the output terminal of the address falling edge detection branch, the output terminal of the first NOR gate is electrically connected to the input terminal of the first inverter, the output terminal of the first inverter is electrically connected to the output terminal of the address detection output unit, and the output terminal of the address detection output unit is used to output the address detection signal.

[0011] Optionally, the address rising edge detection branch includes: a second inverter, a first transistor, a second transistor, a first resistor, a third inverter, a first capacitor, and a second NOR gate; The input terminal of the second inverter, the first input terminal of the second NOR gate, and the input terminal of the address detection circuit submodule are electrically connected. The input terminal of the address detection circuit submodule is used to receive the address signal. The output terminal of the second inverter, the control terminal of the first transistor, and the control terminal of the second transistor are electrically connected. The first terminal of the first transistor is electrically connected to the power supply terminal of the address detection circuit submodule. The second terminal of the first transistor, the first terminal of the first resistor, the first terminal of the first capacitor, and the input terminal of the third inverter are electrically connected. The first terminal of the second transistor is electrically connected to the second terminal of the first resistor, and the second terminal of the second transistor and the second terminal of the first capacitor are respectively electrically connected to the reference ground terminal of the address detection circuit submodule. The output of the third inverter is electrically connected to the second input of the second NOR gate, and the output of the second NOR gate is electrically connected to the first terminal of the address detection output unit. The output of the second NOR gate is used to output the address rising edge detection signal. The address falling edge detection branch includes: a fourth inverter, a fifth inverter, a third transistor, a fourth transistor, a second resistor, a sixth inverter, a second capacitor, and a third NOR gate; The input terminal of the fourth inverter is electrically connected to the input terminal of the address detection circuit submodule, and the output terminal of the fourth inverter, the input terminal of the fifth inverter, and the first input terminal of the third NOR gate are electrically connected. The output terminal of the fifth inverter, the control terminal of the third transistor, and the control terminal of the fourth transistor are electrically connected. The first terminal of the third transistor is electrically connected to the power supply terminal of the address detection circuit submodule. The second terminal of the third transistor, the first terminal of the second resistor, the first terminal of the second capacitor, and the input terminal of the sixth inverter are electrically connected. The first terminal of the fourth transistor is electrically connected to the second terminal of the second resistor, and the second terminal of the fourth transistor and the second terminal of the second capacitor are respectively electrically connected to the reference ground terminal of the address detection circuit submodule. The output of the sixth inverter is electrically connected to the second input of the third NOR gate, and the output of the third NOR gate is electrically connected to the second terminal of the address detection output unit. The output of the third NOR gate is used to output the address falling edge detection signal.

[0012] The above scheme, through detailed circuit structure design, ensures accurate detection of address rising and falling edge signals, and improves the stability and anti-interference capability of address detection.

[0013] Optionally, the address detection output unit may further include: a first filter and a first flip-flop; The input terminal of the first filter is electrically connected to the output terminal of the first inverter, and the output terminal of the first filter is electrically connected to the input terminal of the first flip-flop. The output terminal of the first flip-flop serves as the output terminal of the address detection output unit. The first filter is used to filter the output signal of the first inverter and output the address detection filter signal. The first flip-flop is used to output an address detection signal based on the address detection filter signal and the chip's reset signal.

[0014] Optionally, the chip select detection circuit submodule includes: a chip select falling edge detection branch, a second filter, and a second flip-flop; The chip select falling edge detection branch is used to detect the chip select falling edge signal based on the chip select signal, and output the chip select falling edge detection signal corresponding to the chip select falling edge signal. The second filter is used to filter the chip select falling edge detection signal and output the chip select detection filter signal corresponding to the chip select falling edge detection signal to the second flip-flop. The second flip-flop is used to output a chip select detection signal based on the chip select detection filter signal and the chip's reset signal.

[0015] Optionally, the chip control circuit may also include: a reset circuit module; The reset circuit module is used to output a reset signal when the address detection circuit submodule does not detect an address level transition signal within a preset time and the chip select signal level is a preset invalid level.

[0016] Optionally, the chip auxiliary circuit includes a data buffer circuit and an address decoding circuit. The enable signals include a data buffer enable signal corresponding to the data buffer circuit and an address decoding enable signal corresponding to the address decoding circuit. The circuit enable control module includes: an operational amplifier, an eleventh inverter, a first AND gate, and a second AND gate. The first input terminal of the operational amplifier is electrically connected to the output terminal of the signal detection trigger module, and the output terminal of the operational amplifier is electrically connected to the input terminal of the eleventh inverter. The output of the eleventh inverter, the first input of the first AND gate, and the first input of the second AND gate are electrically connected. The second input of the first AND gate is used to receive the data buffer enable signal, and the second input of the second AND gate is used to receive the address decoding enable signal. The operational amplifier is used to output the op-amp output signal corresponding to the chip wake-up signal to the input terminal of the eleventh inverter under the control of the chip select signal, based on the chip wake-up signal and the preset reference voltage signal. The first AND gate is used to output a first enable signal based on the output signal of the eleventh inverter and the data buffer enable signal. The first enable signal is used to control the working state of the data buffer circuit. The second AND gate is used to output a second enable signal based on the output signal of the eleventh inverter and the address decoding enable signal. The second enable signal is used to control the working state of the address decoding circuit.

[0017] Secondly, this application provides a chip control method, wherein the chip includes a chip auxiliary circuit and the aforementioned chip control circuit, the method comprising: Detect address level transition signals based on the chip's address signals; Based on the address level transition signal and combined with the chip select signal, a chip wake-up signal is output. Based on the chip wake-up signal and chip select signal, combined with the enable signal of the chip auxiliary circuit, the working state of the chip auxiliary circuit is controlled.

[0018] Thirdly, this application provides a memory chip, including the chip control circuit described in any of the first aspects of this application above.

[0019] In summary, the chip control circuit, chip control method, and memory chip of this application, through a signal detection trigger module, detect address level transition signals based on the chip's address signals, and output a chip wake-up signal based on the address level transition signals and the chip select signal. This enables the circuit enable control module to control the working state of the chip auxiliary circuit based on the chip wake-up signal and the chip select signal, combined with the enable signal of the chip auxiliary circuit. In this way, the working state of the chip auxiliary circuit can be woken up as needed, effectively reducing the chip's ineffective power consumption in standby, low load, or no read / write operation scenarios, improving the chip's energy efficiency ratio and battery life. It has the advantages of effectively reducing the chip's ineffective power consumption in standby, low load, or no read / write operation scenarios, and improving the chip's energy efficiency ratio and battery life. Attached Figure Description

[0020] Figure 1 This is a schematic diagram of the structure of a chip control circuit provided in an embodiment of this application; Figure 2 A schematic diagram of the structure of a signal detection triggering module provided in an optional embodiment of this application; Figure 3 A schematic diagram of the circuit principle of an address detection circuit submodule provided for an optional embodiment of this application; Figure 4 A schematic diagram of the circuit principle of another address detection circuit submodule provided in an optional embodiment of this application; Figure 5 A schematic diagram of the circuit principle of a chip select detection circuit submodule provided for an optional embodiment of this application; Figure 6 A schematic diagram showing the connection between a reset circuit module, an address detection circuit submodule, and a chip select detection circuit submodule, provided as an optional embodiment of this application; Figure 7 A schematic diagram of the structure of a circuit enable control module provided in an optional embodiment of this application; Figure 8This is a flowchart illustrating the steps of a chip control method provided in an embodiment of this application.

[0021] Figure 9 This is a schematic diagram of the structure of a memory chip provided in an embodiment of this application.

[0022] Label Explanation: 100, Chip Control Circuit; 110, Detection Trigger Module; 120, Circuit Enable Control Module; 130, Chip Auxiliary Circuit; Addr, Address Signal; CS, Chip Select Signal; EN0, Chip Wake-up Signal; EN1, Enable Signal; EN11, Data Buffer Enable Signal; EN12, Address Decoding Enable Signal; 111, Address Detection Circuit Submodule; 112, Chip Select Detection Circuit Submodule; 113, Wake-up Submodule; OUT1, Address Detection Signal; OUT2, Chip Select Detection Signal; 310, Address Rising Edge Detection Branch; 320, Address Falling Edge Detection Branch; 330, Address Detection Output Unit; OR1, First NOR Gate; OR2, Second NOR Gate; OR3, Third NOR Gate; A1, First Inverter; A2, Second Inverter; A3, Third Inverter; A4, Fourth Inverter; A5, Fifth Inverter; A6, Sixth Inverter; A7, Seventh Inverter; A8, Eighth inverter; A9, Ninth inverter; A10, Tenth inverter; A11, Eleventh inverter; INb1, Output of the fourth inverter; M1, First transistor; M2, Second transistor; M3, Third transistor; M4, Fourth transistor; M5, Fifth transistor; M6, Sixth transistor; R1, First resistor; R2, Second resistor; R3, Third resistor; C1, First capacitor; C2, Second capacitor; C3, Third capacitor; VDD, Power supply terminal; 410, First filter; 420, First flip-flop; 510, Chip select falling edge detection branch; 520, Second filter; 530, Second flip-flop; AND1, First NAND gate; 610, Reset circuit module; OP, Operational amplifier; AND2, First AND gate; AND3, Second AND gate; Vref, Reference voltage signal; EN21, First enable signal; EN22, Second enable signal; 900, Memory chip. Detailed Implementation

[0023] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely represents selected embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0024] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, in the description of this application, terms such as "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0025] In the current field of electronic technology, especially for battery-powered portable devices, IoT terminals, and various embedded devices, non-volatile memory chips, such as NOR flash memory, play a crucial role. These chips are responsible for storing critical boot code and user data, and their stable and reliable operation is the foundation for the normal operation of the entire electronic device. To ensure that data can be read quickly and accurately, traditional NOR flash memory chips are designed with a series of auxiliary circuits, the most crucial of which are the address decoding circuit and the data buffer circuit. The function of the address decoding circuit is to accurately locate a specific cell among thousands of memory cells in the memory array based on the address signal provided by the external processor. The data buffer circuit is responsible for temporarily storing and shaping the data after it is read from the memory cell, ensuring that the data can be stably transmitted to the external data bus.

[0026] However, in pursuit of ultimate response speed, existing technologies generally employ a simple and direct design strategy: keeping these address decoding circuits and data buffer circuits constantly powered on. This means that regardless of whether the external processor actually needs to read or write, whether the signals on the address bus are changing, or whether the chip is selected by the chip select signal, these auxiliary circuits continuously consume power. This design generates a significant amount of wasted power when the device is idle, in standby, or under low load. For an IoT sensor node or a portable consumer electronics product, every milliamp of current is precious, and this continuous energy waste significantly shortens the device's battery life, becoming a bottleneck in product design. Simultaneously, continuously running circuits inevitably generate heat, increasing the overall heat dissipation of the chip. In the long run, this not only affects the chip's performance and lifespan but may also impose more stringent requirements on the thermal management design of the entire system, impacting long-term operational stability.

[0027] To address the aforementioned technical challenges, this application proposes a chip control circuit that can significantly reduce the power consumption of the memory chip in its non-operating state without sacrificing signal response speed. For example... Figure 1 As shown, the chip control circuit 100 includes a signal detection trigger module 110 and a circuit enable control module 120. The signal detection trigger module 110 detects address level transition signals based on the chip's address signal Addr, and outputs a chip wake-up signal EN0 based on the address level transition signal and the chip select signal CS. The circuit enable control module 120 controls the operating state of the chip auxiliary circuit 130 based on the chip wake-up signal EN0 and the chip select signal CS, combined with the enable signal EN1 of the chip auxiliary circuit 130.

[0028] In this embodiment, the chip's address signal Addr and chip select signal CS can be used as input signals to the signal detection trigger module 110. The signal detection trigger module 110 can detect address level transition signals based on the chip's address signal Addr, i.e., detect whether the effective level of the chip's address signal Addr has transitioned. When the effective level of the address signal Addr transitions, an address level transition signal is generated. Based on this address level transition signal, combined with the chip select signal CS, a chip wake-up signal EN0 is output to the circuit enable control module 120, allowing the circuit enable control module 120 to... The chip wake-up signal EN0 and the chip select signal CS, combined with the enable signal EN1 of the chip auxiliary circuit 130, control the working state of the chip auxiliary circuit 130. This allows the chip auxiliary circuit 130 to be woken up as needed, effectively reducing the ineffective power consumption of the chip in standby, low-load, or no-read / write operation scenarios. For example, in standby, low-load, or no-read / write operation scenarios, the chip auxiliary circuit 130 can be turned off by the circuit enable control module 120, causing the chip auxiliary circuit 130 to enter a sleep standby state. This solves the problem of high power consumption caused by the continuous operation of the chip detection circuit in the prior art, and can effectively improve the energy efficiency ratio of the chip and the battery life of the chip device.

[0029] Optionally, to more clearly illustrate the internal working mechanism of the signal detection trigger module 110, it can be further divided into three functionally independent sub-modules: address detection circuit sub-module 111, chip select detection circuit sub-module 112, and wake-up sub-module 113. This modular design makes the signal processing flow clearer and facilitates independent optimization of the functions of each part. Figure 2 As shown, the signal detection trigger module 110 includes: an address detection circuit submodule 111, a chip select detection circuit submodule 112, and a wake-up submodule 113. Specifically, the address detection circuit submodule 111 detects an address level transition signal based on the address signal Addr, and outputs an address detection signal OUT1 to the wake-up submodule 113 based on the address level transition signal; the chip select detection circuit submodule 112 detects a falling edge signal based on the chip select signal CS, and outputs a chip select detection signal OUT2 to the wake-up submodule 113 based on the falling edge signal; and the wake-up submodule 113 outputs a chip wake-up signal EN0 to the circuit enable control module 120 based on the address detection signal OUT1 and the chip select detection signal OUT2.

[0030] In an optional embodiment of this application, the address detection circuit submodule 111 can be a unit specifically responsible for monitoring the dynamics of the address bus. Its core task is to detect any changes in the address level in real time based on the input address signal Addr, and output an address detection signal OUT1 corresponding to the address signal Addr based on the address level change. Specifically, a change in the level of the address signal Addr from low to high, or from high to low, indicates that the external processor is changing the addressing target, which is a potential start signal for a read / write operation. Once the address detection circuit submodule 111 captures such an address level change signal, it immediately generates an internal address detection signal OUT1 and passes it to the wake-up submodule 113.

[0031] Meanwhile, the chip select detection circuit submodule 112 can focus on monitoring the chip select signal CS transmitted by the chip select signal CS line. In the design specifications of most memory chips, the chip select signal CS is active low, meaning that when the chip select signal CS line transitions from high to low, it indicates that the chip is selected and ready to receive instructions. Therefore, the chip select detection circuit submodule 112 can be designed specifically to detect the falling edge signal of the chip select signal CS. When this valid falling edge is detected, the chip select detection circuit submodule 112 generates a chip select detection signal OUT2, which is also sent to the wake-up submodule 113.

[0032] The wake-up submodule 113 acts as the final decision-maker, receiving the address detection signal OUT1 from the address detection circuit submodule 111 and the chip select detection signal OUT2 from the chip select detection circuit submodule 112. The internal logic circuitry of the wake-up submodule 113 comprehensively evaluates these two input signals. Only when there is activity on the address bus and the chip is officially selected is a valid operation request considered to have occurred. Based on this evaluation, the wake-up submodule 113 ultimately outputs a chip wake-up signal EN0 to the external circuit enable control module 120. This dual confirmation mechanism ensures that wake-up is triggered only when both the address and chip select signals CS are valid, avoiding erroneous wake-up of auxiliary circuits due to brief glitches on the address bus or misoperation of the chip select signal CS, further improving the accuracy of power consumption control.

[0033] To facilitate understanding of the embodiments of this application, further explanations and descriptions will be provided below in conjunction with the accompanying drawings and specific examples, but these examples do not constitute a limitation on the embodiments of this application.

[0034] As an example of this application, when the chip control circuit 100 is applied in a non-volatile storage environment in a smart wearable device, when the main controller of the smart wearable device initiates a data read request, the voltage on the address bus changes rapidly. The address detection circuit submodule 111 can sense the rising or falling edge of the address signal Addr in real time through its internal differentiating circuit. It can then generate an address level transition signal based on the rising or falling edge of the address signal Addr. Based on this address level transition signal, it can output a corresponding address detection signal OUT1 to the wake-up submodule 113. This allows the wake-up submodule 113 to output a wake-up signal to the circuit enable control module 120 based on the address detection signal OUT1, which serves as the chip wake-up signal EN0. The chip wake-up signal EN0 can then wake up the chip auxiliary circuit 130, enabling it to enter normal operation and achieve normal enabling of the chip auxiliary circuit 130.

[0035] In this embodiment, the address level transition signal refers to the signal generated on the chip's address bus by a logic level switch caused by an external processor changing the access target. This switch manifests as a potential transition from logic low to logic high, or from logic high to logic low. In hardware implementation, this transition can be identified by capturing the signal edge. The pulse width generated by the level transition can be determined by the internal delay chain of the circuit, representing the occurrence of an external addressing action and serving as the original physical event triggering the subsequent wake-up process.

[0036] In specific implementations, address level transitions include two basic cases: a rising edge from low to high and a falling edge from high to low. Optionally, the address level transition signals in this embodiment include a rising edge signal and a falling edge signal; wherein, the rising edge signal refers to the signal generated by the rising edge of the address signal Addr from low to high; and the falling edge signal refers to the signal generated by the falling edge of the address signal Addr from high to low.

[0037] In order to capture any address changes without omission, optional, such as Figure 3 As shown, the internal structure of the address detection circuit submodule 111 in this embodiment is designed to include an address rising edge detection branch 310, an address falling edge detection branch 320, and an address detection output unit 330. Specifically, the address detection circuit submodule 111 may include: an address rising edge detection branch 310, an address falling edge detection branch 320, and an address detection output unit 330.

[0038] The address rising edge detection branch 310 is used to detect the address rising edge signal based on the address signal Addr, that is, to perform address rising edge detection based on the address signal Addr, obtain the address rising edge signal, and output the address rising edge detection signal corresponding to the address rising edge signal. In other words, based on the address rising edge signal, the corresponding address rising edge detection signal is output to the address detection output unit 330. If the output terminal of the address rising edge detection branch 310 is electrically connected to the first input terminal of the address detection output unit 330, the address rising edge detection branch 310 can output the address rising edge detection signal to the first input terminal of the address detection output unit 330 through the output terminal, so that the address detection output unit 330 can output the address detection signal OUT1 to the wake-up submodule 113 based on the address rising edge detection signal.

[0039] The address falling edge detection branch 320 is used to detect the address falling edge signal based on the address signal Addr, perform address falling edge detection based on the address signal Addr, obtain the address falling edge signal, and output the address falling edge detection signal corresponding to the address falling edge signal. That is, based on the address falling edge signal, the corresponding address falling edge detection signal is output to the address detection output unit 330. If the output terminal of the address falling edge detection branch 320 is electrically connected to the second input terminal of the address detection output unit 330, the address falling edge detection branch 320 can output the address falling edge detection signal to the second input terminal of the address detection output unit 330 through the output terminal, so that the address detection output unit 330 can output the address detection signal OUT1 to the wake-up submodule 113 based on the address falling edge detection signal.

[0040] The address detection output unit 330 is used to output the address detection signal OUT1 to the wake-up submodule 113 based on the address rising edge detection signal and / or the address falling edge detection signal. In a specific implementation, the address detection output unit 330 can be implemented using a logic OR gate, or it can be implemented using a NOR gate and an inverter. For example, if it is implemented using a NOR gate and an inverter, the first input terminal of the NOR gate can be used as the first terminal of the address detection output unit 330, electrically connected to the output terminal of the address rising edge detection branch 310; the second input terminal of the NOR gate can be used as the second terminal of the address detection output unit 330, electrically connected to the output terminal of the address falling edge detection branch 320; the output terminal of the NOR gate can be electrically connected to the input terminal of the inverter; and the output terminal of the inverter can be used as the output terminal of the address detection output unit 330, electrically connected to the wake-up submodule 113, for outputting the address detection signal OUT1 to the wake-up submodule 113.

[0041] As can be seen, the internal structure of the address detection circuit submodule 111 in this embodiment is designed to include an address rising edge detection branch 310, an address falling edge detection branch 320, and an address detection output unit 330. The address rising edge detection branch 310 is a dedicated circuit path whose sole task is to detect the address rising edge signal based on the input address signal Addr. When the voltage of a bit on the address line rises from a low level corresponding to logic 0 to a high level corresponding to logic 1, this branch is triggered and outputs an address rising edge detection signal corresponding to that address rising edge signal. The address falling edge detection branch 320, operating in parallel, is responsible for detecting the falling edge of the address signal Addr. When the voltage of a bit on the address line changes from a high level to a low level, this branch generates an address falling edge detection signal. The address rising edge detection signals and address falling edge detection signals generated by these two branches are simultaneously sent to the address detection output unit 330. The core function of the address detection output unit 330 is to logically combine the two signals to output the address detection signal OUT1 based on the address rising edge detection signal and / or the address falling edge detection signal.

[0042] In an optional embodiment of this application, the address detection output unit 330 includes: a first NOR gate OR1 and a first inverter A1; the first input terminal of the first NOR gate OR1 is electrically connected to the output terminal of the address rising edge detection branch 310, the second input terminal of the first NOR gate OR1 is electrically connected to the output terminal of the address falling edge detection branch 320, the output terminal of the first NOR gate OR1 is electrically connected to the input terminal of the first inverter A1, the output terminal of the first inverter A1 is electrically connected to the output terminal of the address detection output unit 330, and the output terminal of the address detection output unit 330 is used to output the address detection signal OUT1.

[0043] As an example of this application, such as Figure 3As shown, the address detection output unit 330 consists of a first NOR gate OR1 and a first inverter A1. The output of the rising edge detection branch 310 is electrically connected to the first input of the first NOR gate OR1, and the output of the falling edge detection branch 320 is electrically connected to the second input of the first NOR gate OR1. The output of the first NOR gate OR1 is then connected to the input of the first inverter A1. This combination of an NOR gate and an inverter is logically equivalent to an OR gate, and its operation is as follows: regardless of whether the rising edge detection branch 310 or the falling edge detection branch 320 outputs a high-level pulse, at least one input of the first NOR gate OR1 will be high, thus causing its output to be low; after this low-level signal is inverted by the first inverter A1, a high-level address detection signal OUT1 will be generated at the final output of the address detection output unit 330. This design ensures that any level transition of the address signal Addr, whether rising or falling, will trigger a unified and effective address detection signal OUT1 to be output to the wake-up submodule 113, thereby guaranteeing the comprehensiveness and sensitivity of address change detection.

[0044] In an optional embodiment of this application, the address rising edge detection branch 310 includes: a second inverter A2, a first transistor M1, a second transistor M2, a first resistor R1, a third inverter A3, a first capacitor C1, and a second NOR gate OR2; the input terminal of the second inverter A2, the first input terminal of the second NOR gate OR2, and the input terminal of the address detection circuit submodule 111 are electrically connected, and the input terminal of the address detection circuit submodule 111 is used to input the address signal Addr; the output terminal of the second inverter A2, the control terminal of the first transistor M1, and the control terminal of the second transistor M2 are electrically connected, and the first terminal of the first transistor M1 is connected to the address detection circuit submodule 111. The power supply terminal VDD is electrically connected. The second terminal of the first transistor M1, the first terminal of the first resistor R1, the first terminal of the first capacitor C1, and the input terminal of the third inverter A3 are electrically connected. The first terminal of the second transistor M2 is electrically connected to the second terminal of the first resistor R1. The second terminal of the second transistor M2 and the second terminal of the first capacitor C1 are respectively electrically connected to the reference ground terminal of the address detection circuit submodule 111. The output terminal of the third inverter A3 is electrically connected to the second input terminal of the second NOR gate OR2. The output terminal of the second NOR gate OR2 is electrically connected to the first terminal of the address detection output unit 330. The output terminal of the second NOR gate OR2 is used to output the address rising edge detection signal.

[0045] Optionally, the address falling edge detection branch 320 in this embodiment includes: a fourth inverter A4, a fifth inverter A5, a third transistor M3, a fourth transistor M4, a second resistor R2, a sixth inverter A6, a second capacitor C2, and a third NOR gate OR3; the input terminal of the fourth inverter A4 is electrically connected to the input terminal of the address detection circuit submodule 111, and the output terminal INb1 of the fourth inverter A4, the input terminal of the fifth inverter A5, and the first input terminal of the third NOR gate OR3 are electrically connected; the output terminal of the fifth inverter A5, the control terminal of the third transistor M3, and the control terminal of the fourth transistor M4 are electrically connected, and the first terminal of the third transistor M3 is connected to the address detection circuit submodule 111. The power supply terminal VDD of the first inverter is electrically connected. The second terminal of the third transistor M3, the first terminal of the second resistor R2, the first terminal of the second capacitor C2, and the input terminal of the sixth inverter A6 are electrically connected. The first terminal of the fourth transistor M4 is electrically connected to the second terminal of the second resistor R2. The second terminal of the fourth transistor M4 and the second terminal of the second capacitor C2 are respectively electrically connected to the reference ground terminal of the address detection circuit submodule 111. The output terminal of the sixth inverter A6 is electrically connected to the second input terminal of the third NOR gate OR3. The output terminal of the third NOR gate OR3 is electrically connected to the second terminal of the address detection output unit 330. The output terminal of the third NOR gate OR3 is used to output the address falling edge detection signal.

[0046] As an example of this application, in order to achieve accurate capture of the edge of the address signal Addr, both the address rising edge detection branch 310 and the address falling edge detection branch 320 can adopt a sophisticated circuit design based on the combination of RC delay and logic gates, such as... Figure 3 As shown.

[0047] The address rising edge detection branch 310 comprises a second inverter A2, a first transistor M1, a second transistor M2, a first resistor R1, a third inverter A3, a first capacitor C1, and a second NOR gate OR2. The address signal Addr is first connected to the input terminal of the address detection circuit submodule 111, which is simultaneously connected to the input terminal of the second inverter A2 and the first input terminal of the second NOR gate OR2. The output terminal of the second inverter A2 is connected to the control terminals of the first transistor M1 and the second transistor M2. Here, the first transistor M1 is typically a P-channel metal-oxide-semiconductor field-effect transistor, with its first terminal connected to the power supply terminal VDD; the second transistor M2 is an N-channel metal-oxide-semiconductor field-effect transistor, with its second terminal connected to the reference ground terminal. These two transistors, together with the first resistor R1, form an inverter structure. The output node, i.e., the connection point between the second terminal of the first transistor M1 and the first terminal of the first resistor R1, is simultaneously connected to the first terminal of the first capacitor C1 and the input terminal of the third inverter A3. The second terminal of the first resistor R1 is connected to the first terminal of the second transistor M2, while the second terminal of the second transistor M2 and the second terminal of the first capacitor C1 are connected to the reference ground. Finally, the output terminal of the third inverter A3 is connected to the second input terminal of the second NOR gate OR2, and the output terminal of the second NOR gate OR2 is the output terminal of this branch, used to output the address rising edge detection signal. The working principle of the address rising edge detection branch 310 is as follows: When the address signal Addr undergoes a rising edge transition from low to high, the signal directly input to the first input terminal of the second NOR gate OR2 becomes high level; at the same time, this high level signal becomes low level after passing through the second inverter A2, and this low level is applied to the control terminals of the first and second transistors M2, causing the first transistor M1 to conduct and the second transistor M2 to be cut off; the power signal provided by the power supply terminal VDD of the address detection circuit submodule 111 starts to charge the first capacitor C1 through the conducting first transistor M1. The charging process is limited by the current of the first resistor R1, forming an RC delay; therefore, the voltage at the input terminal of the third inverter A3 will rise with a delay. At the instant the address signal Addr changes, the first input of the second NOR gate OR2 is already high, while its second input remains high due to the RC delay and the effect of the third inverter A3. When the capacitor charges to a certain extent, the third inverter A3 flips, and its output becomes low. At this point, the two inputs of the second NOR gate OR2 become one high and one low. Within a very short time after the address signal Addr changes, the inherent delay of the circuit can be used to design both inputs of the second NOR gate OR2 to be low for a brief moment, thus generating a short high-level pulse at its output. This pulse is the address rising edge detection signal.

[0048] The structure of the address falling edge detection branch 320 is similar to that of the rising edge detection branch, but to detect the falling edge, an inverter stage is added at the input. Specifically, it includes a fourth inverter A4, a fifth inverter A5, a third transistor M3, a fourth transistor M4, a second resistor R2, a sixth inverter A6, a second capacitor C2, and a third NOR gate OR3. The address signal Addr first enters the fourth inverter A4, whose output is connected to the input of the fifth inverter A5 and the first input of the third NOR gate OR3. The output of the fifth inverter A5 controls the third transistor M3 and the fourth transistor M4. The subsequent RC delay circuit, composed of the third transistor M3, the fourth transistor M4, the second resistor R2, the second capacitor C2, and the sixth inverter A6, operates on the same principle as the corresponding part in the rising edge detection branch. Finally, the output of the sixth inverter A6 is connected to the second input of the third NOR gate OR3, and the output of the third NOR gate OR3 is the address falling edge detection signal. By adding a fourth inverter A4 at the input, the entire circuit becomes sensitive to the falling edge of the address signal Addr, thereby generating a high-level pulse as the address falling edge detection signal when the address signal Addr transitions from high to low.

[0049] In real-world circuit environments, various noises and interferences inevitably exist along the signal transmission path. These interferences can create erroneous signal spikes, leading to misjudgments by the edge detection circuit. To improve the reliability and anti-interference capability of the address detection signal OUT1, the address detection output unit 330 can be equipped with filters and flip-flops. Anti-interference processing can be achieved through filters and flip-flops, such as filtering high-frequency spike signals and latching valid detection signals using D flip-flops, thereby avoiding false wake-ups caused by transient interference and ensuring the reliability of the circuit operation.

[0050] Optional, such as Figure 4 As shown, the address detection output unit 330 in this embodiment may include a first NOR gate OR1 and a first inverter A1, as well as a first filter 410 and a first flip-flop 420. The input terminal of the first filter 410 is electrically connected to the output terminal of the first inverter A1, and the output terminal of the first filter 410 is electrically connected to the input terminal of the first flip-flop 420. The output terminal of the first flip-flop 420 serves as the output terminal of the address detection output unit 330. The first filter 410 is used to filter the output signal of the first inverter A1 and output an address detection filtered signal. The first flip-flop 420 is used to output the address detection signal OUT1 based on the address detection filtered signal and the reset signal of the chip.

[0051] Specifically, the input of the first filter 410 is electrically connected to the output of the first inverter A1, and its output is connected to the input of the first flip-flop 420; the output of the first flip-flop 420 serves as the final output of the entire address detection output unit 330. The function of the first filter 410 is to filter the signal output by the first inverter A1. This filter can be a simple low-pass filter, designed to remove high-frequency noise and brief, unexpected pulse spikes from the signal. Only valid signal pulses whose width and amplitude meet preset conditions can pass through the filter, forming a cleaner and more stable address detection filter signal.

[0052] Subsequently, this address detection filter signal is sent to the first flip-flop 420, which can be a D-type flip-flop with latching functionality. When a valid address detection filter signal pulse arrives, it triggers the flip-flop to flip, causing its output to go high, and it remains in this state until a reset signal is received. In this way, a momentary pulse signal is converted into a stable and continuously valid address detection signal OUT1. This design not only completely eliminates the influence of glitches but also ensures the stability of the address detection signal OUT1 during subsequent circuit processing. Furthermore, the first flip-flop 420 can also be connected to a chip reset signal. When it is necessary to return to the initial state, a reset signal can clear the flip-flop, restoring the address detection signal OUT1 to an invalid low-level state, preparing for the next detection.

[0053] Similarly, to ensure the accuracy and reliability of the chip select signal CS detection, the chip select detection circuit submodule 112 also adopts a similar enhanced design, which internally includes a chip select falling edge detection branch 510, a second filter 520, and a second flip-flop 530, such as... Figure 5 As shown. Optionally, the chip select detection circuit submodule 112 in this embodiment includes: a chip select falling edge detection branch 510, a second filter 520, and a second flip-flop 530. The chip select falling edge detection branch 510 is used to detect the chip select falling edge signal based on the chip select signal CS, and output a chip select falling edge detection signal corresponding to the falling edge signal; the second filter 520 is used to filter the chip select falling edge detection signal and output a chip select detection filtered signal corresponding to the falling edge detection signal to the second flip-flop 530; the second flip-flop 530 is used to output the chip select detection signal OUT2 based on the chip select detection filtered signal and the chip's reset signal.

[0054] Specifically, the core function of the chip select falling edge detection branch 510 is to accurately detect the falling edge from high to low based on the input chip select signal CS, and output a corresponding chip select falling edge detection signal pulse. This process is similar to the principle of address falling edge detection. Next, this chip select falling edge detection signal is sent to the second filter 520. The function of the second filter 520 is the same as that of the first filter 410: to filter out noise and glitches in the signal, reshape and purify the original detection pulse, thereby outputting a clean chip select detection filtered signal to the second flip-flop 530. Finally, the second flip-flop 530 performs a latching operation based on the received chip select detection filtered signal. Once a valid chip select signal CS is detected, the second flip-flop 530 outputs a stable high-level chip select detection signal OUT2. This signal will also remain until a reset signal from the chip is received. Through this three-step processing flow of detection, filtering, and latching, the anti-interference capability and stability of the chip select detection signal OUT2 are greatly improved, providing a reliable decision basis for the wake-up submodule 113.

[0055] In a specific circuit implementation, the chip select falling edge detection branch 510 includes: a seventh inverter A7, a fifth transistor M5, a sixth transistor M6, a third resistor R3, an eighth inverter A8, a ninth inverter A9, a third capacitor C3, a first NAND gate AND1, and a tenth inverter A10. The input terminal of the seventh inverter A7 is electrically connected to the input terminal of the chip select detection circuit submodule 112. The output terminal INb2 of the seventh inverter A7, the control terminal of the fifth transistor M5, the control terminal of the sixth transistor M6, and the first input terminal of the first NAND gate AND1 are electrically connected. The input terminal of the chip select detection circuit submodule 112 is used to receive the chip select signal CS, so that the chip select detection circuit submodule 112 can detect the chip select falling edge signal based on the chip select signal CS through the fifth transistor M5, the sixth transistor M6, the third resistor R3, and the third capacitor C3, and output a corresponding chip select falling edge detection signal based on the detected chip select falling edge signal.

[0056] Specifically, the first terminal of the fifth transistor M5 is electrically connected to the power supply terminal VDD of the chip select detection circuit submodule 112; the second terminal of the fifth transistor M5, the first terminal of the third resistor R3, the first terminal of the third capacitor C3, and the input terminal of the eighth inverter A8 are electrically connected; the output terminal of the eighth inverter A8 is electrically connected to the input terminal of the ninth inverter A9; the first terminal of the sixth transistor M6 is electrically connected to the second terminal of the third resistor R3; the second terminal of the sixth transistor M6 and the second terminal of the third capacitor C3 are respectively electrically connected to the reference ground terminal of the chip select detection circuit submodule 112; the output terminal of the ninth inverter A9 is electrically connected to the second input terminal of the first NAND gate AND1; the output terminal of the first NAND gate AND1 is electrically connected to the input terminal of the tenth inverter A10; the output terminal of the tenth inverter A10 serves as the output terminal of the chip select falling edge detection branch 510, which is used to output the chip select falling edge detection signal. In this embodiment, the power supply terminal VDD of the chip select detection circuit submodule 112 and the power supply terminal VDD of the address detection circuit submodule 111 can be the same power supply terminal or two different power supply terminals. This application does not impose specific restrictions on this.

[0057] As an example of this application, such as Figure 5 As shown, the chip select falling edge detection branch 510 can be composed of a seventh inverter A7, a fifth transistor M5, a sixth transistor M6, a third resistor R3, an eighth inverter A8, a ninth inverter A9, a third capacitor C3, a first NAND gate AND1, and a tenth inverter A10. The chip select signal CS is first connected to the input terminal of the seventh inverter A7. Its output signal is directly sent to the first input terminal of the first NAND gate AND1, and is also used to control the fifth transistor M5 and the sixth transistor M6. The fifth transistor M5 is a P-channel MOSFET, and the sixth transistor M6 is an N-channel MOSFET. Together with the third resistor R3 and the third capacitor C3, they form an RC delay network. The output of this network is connected to the delay chain composed of the eighth and ninth inverters A9. The output terminal of the ninth inverter A9 is connected to the second input terminal of the first NAND gate AND1.

[0058] When the chip select signal CS experiences a falling edge transition, the output of the seventh inverter A7 generates a rising edge signal. This rising edge signal causes the first input of the first NAND gate AND1 to go high. Simultaneously, this rising edge signal passes through an RC delay network and an inverter chain, causing a change in the second input of the first NAND gate AND1 only after a short period. Utilizing this time difference, at the instant the falling edge of the chip select signal CS occurs, both inputs of the first NAND gate AND1 can be designed to be high for a brief period, thus outputting a low-level pulse. This low-level pulse is then inverted by the tenth inverter A10, resulting in a high-level chip select falling edge detection signal pulse. This circuit structure accurately converts the falling edge of the chip select signal CS into a narrow pulse signal for subsequent filtering and latching.

[0059] Optionally, to achieve intelligent sleep and reset of the entire control circuit, such as Figure 6 As shown, the chip control circuit 100 provided in this embodiment of the application further includes a reset circuit module 610. This reset circuit module 610 is the key to realizing the automatic power management closed loop. Its function is to actively output a reset signal when the address detection circuit submodule 111 does not detect any address level transition signal within a preset period of time, and the chip select signal CS is at a preset invalid level, usually a high level. Specifically, the reset circuit module 610 is used to output the reset signal when the address detection circuit submodule 111 does not detect the address level transition signal within a preset period of time, and the chip select signal CS is at a preset invalid level.

[0060] The preset time refers to the waiting threshold set by the timing unit inside the reset circuit module 610, which defines the critical point at which the bus transitions from an active state to a silent state. The reset circuit starts timing after the address detection circuit submodule 111 detects the last level transition. If the timing value reaches this threshold and no new level transition pulses are generated during this period, the current read / write cycle is considered to have completely ended. This time length can be adjusted according to the highest access frequency supported by the memory chip, typically set to several times the access cycle, thereby minimizing the time the circuit is in a high-power state while ensuring continuous data reading is not interrupted.

[0061] The logic behind this design is that when the address bus is silent for a long time and the chip is not selected, it can be safely determined that the current read / write cycle has ended or the chip is in an idle state. At this time, the reset circuit module 610 will be triggered, generating a global reset signal. This reset signal will be sent to the aforementioned first flip-flop 420 and second flip-flop 530, forcibly resetting them. After the flip-flops are reset, the address detection signal OUT1 and the chip select detection signal OUT2 will return to an invalid low-level state, so that the wake-up submodule 113 will no longer output the chip wake-up signal EN0. If the circuit enable control module 120 does not receive the chip wake-up signal EN0, it will automatically cut off the power supply to the chip auxiliary circuit 130 or put it into sleep mode, retaining only the low-power operating state of the signal detection trigger module 110. If the chip auxiliary circuit 130 includes an address decoding circuit and a data buffer circuit, the circuit enable control module 120 will automatically cut off the power supply to the address decoding circuit and the data buffer circuit when it does not receive the chip wake-up signal EN0, putting these chip auxiliary circuits 130 into a deep sleep mode, realizing a wake-up signal-free sleep mechanism. This automatic reset mechanism ensures that the chip can reliably return to the lowest power consumption state when idle, avoiding continuous energy waste.

[0062] Once the chip is successfully woken up, a high-efficiency circuit is needed to precisely control the start and stop of each auxiliary circuit. To address this, the circuit enable control module 120, under the control of the chip select signal CS, controls the operating state of the chip auxiliary circuit 130 based on the chip wake-up signal EN0 and the enable signal EN1 of the chip auxiliary circuit 130. This ensures that the chip auxiliary circuit 130 only starts working when a valid address signal Addr or a chip select activation signal is present, remaining in a sleep state at other times. This significantly reduces the chip's ineffective power consumption, making it particularly suitable for portable devices and IoT terminals with high battery life requirements.

[0063] In summary, the core working principle of the chip control circuit 100 provided in this application embodiment is to establish an intelligent power management mechanism for on-demand wake-up. Most of the time, the chip auxiliary circuits 130, such as the address decoding circuit and the data buffer circuit, are in deep sleep or power-off state, with extremely low power consumption. At this time, only the signal detection trigger module 110 continuously monitors the chip's address signal Addr and chip select signal CS in the background with extremely low power consumption. This signal detection trigger module 110 acts like a sensitive sentinel, always on alert. When an external processor needs to read data from the memory chip, it first sets the address of the target memory unit on the address bus, and then selects the chip by pulling the chip select signal CS line low. Changes in the level on the address bus, i.e., address level transition signals, are accurately captured by the signal detection trigger module 110. Once such a valid address signal Addr change is detected, and the chip select signal CS is also confirmed to be valid, the signal detection trigger module 110 immediately generates and outputs a chip wake-up signal EN0.

[0064] The chip wake-up signal EN0 is then sent to the circuit enable control module 120. Upon receiving the EN0 signal, the circuit enable control module 120 further combines it with the chip select signal CS and the enable signal of the chip auxiliary circuit 130 for comprehensive judgment. Only when all conditions are met—that is, the chip is woken up, selected, and the corresponding chip auxiliary circuit 130 is allowed to operate—will the circuit enable control module 120 immediately open the power path to the chip auxiliary circuit 130, or release it from its sleep state, allowing it to instantly enter full-speed operating mode, thus achieving real-time activation of the chip auxiliary circuit 130. After the chip auxiliary circuit 130 is activated, and the power paths to the address decoding circuit and data buffer circuit are connected, it can immediately perform routine read operations such as address decoding and data buffering, ensuring normal execution of read, write, and erase operations.

[0065] In its implementation, the control logic of the circuit enable control module 120 employs a multi-level enable verification mechanism to ensure that the high-power auxiliary circuit is activated only when the physical layer detects a valid action, the chip layer confirms selection, and the logic layer allows operation. For example, when the circuit enable control module 120 has an operational amplifier OP, it releases the operational amplifier OP from its sleep state via the received chip wake-up signal EN0. Then, it performs a bitwise AND operation between the operational amplifier OP's comparator output and the chip's internal auxiliary circuit enable signal, outputting the final enable signal to control the operating state of the chip's auxiliary circuit 130. This logic combination achieves gated control of the power supply path, eliminating static power consumption and limiting the ineffective flow of dynamic current through logic gates.

[0066] After a read / write operation is completed, the address bus returns to a quiet state, and the chip select signal CS returns to an invalid high-level state. If the signal detection trigger module 110 does not detect a new address level transition within a certain period, it determines that the operation is complete and then cancels the chip wake-up signal EN0. The circuit enable control module 120 then cuts off the power supply to the auxiliary circuits, returning them to a low-power sleep state, awaiting the next wake-up. Through this dynamic, event-driven control method, the chip's power-consuming auxiliary circuits 130, such as address decoding and data buffering, only operate for a very short time when read / write operations are actually needed, remaining completely silent the rest of the time. This fundamentally eliminates the large amount of invalid power consumption caused by continuous operation in existing technologies, greatly extending the battery life of battery-powered devices, reducing the chip's operating temperature, and improving overall reliability.

[0067] As an example of this application, assume that the chip auxiliary circuit 130 mainly includes a data buffer circuit and an address decoding circuit, each with a corresponding enable signal. For example, the enable signal for the data buffer circuit is the data buffer enable signal EN11, and the enable signal for the address decoding circuit is the address decoding enable signal EN12. That is, the enable signal EN1 of the chip auxiliary circuit 130 includes the data buffer enable signal EN11 for the data buffer circuit and the address decoding enable signal EN12 for the address decoding circuit. Optionally, such as Figure 7 As shown, the circuit enable control module 120 in this embodiment includes an operational amplifier OP, an eleventh inverter A11, a first AND gate AND2, and a second AND gate AND3. The operational amplifier OP, under the control of the chip select signal CS, outputs an operational amplifier output signal corresponding to the chip wake-up signal EN0 to the input terminal of the eleventh inverter A11 based on the chip wake-up signal EN0 and a preset reference voltage signal Vref. The first AND gate AND2 outputs a first enable signal EN21 based on the output signal of the eleventh inverter A11 and the data buffer enable signal EN11, and the first enable signal EN21 controls the operating state of the data buffer circuit. The second AND gate AND3 outputs a second enable signal EN22 based on the output signal of the eleventh inverter A11 and the address decoding enable signal EN12, and the second enable signal EN22 controls the operating state of the address decoding circuit.

[0068] Specifically, the first input terminal of the operational amplifier OP is electrically connected to the output terminal of the signal detection trigger module 110, and the output terminal of the operational amplifier OP is electrically connected to the input terminal of the eleventh inverter A11. The operational amplifier enable signal terminal of the operational amplifier OP is configured to receive the chip select signal CS, and the second input terminal of the operational amplifier OP is configured to receive the reference voltage signal Vref. This allows the operational amplifier OP, under the control of the chip select signal CS, to output the operational amplifier output signal corresponding to the chip wake-up signal EN0 to the input terminal of the eleventh inverter A11 based on the chip wake-up signal EN0 and the preset reference voltage signal Vref. The output terminal of the eleventh inverter A11, the first input terminal of the first AND gate AND2, and the second... The first input of AND gate AND3 is electrically connected, and the second input of the first AND gate AND2 is used to connect to the data buffer enable signal EN11, so that the first AND gate AND2 can output the first enable signal EN21 according to the output signal of the eleventh inverter A11 and the data buffer enable signal EN11, so as to control the working state of the data buffer circuit through the first enable signal EN21; the second input of the second AND gate AND3 is used to connect to the address decoding enable signal EN12, so that the second AND gate AND3 can output the second enable signal EN22 according to the output signal of the eleventh inverter A11 and the address decoding enable signal EN12, so as to control the working state of the address decoding circuit through the second enable signal EN22.

[0069] In this embodiment, the chip wake-up signal EN0 output by the signal detection trigger module 110 is connected to the first input terminal of the operational amplifier OP; the output terminal of the operational amplifier OP is electrically connected to the input terminal of the eleventh inverter A11; the output terminal of the eleventh inverter A11 is a key control node, which is simultaneously connected to the first input terminal of the first AND gate AND2 and the first input terminal of the second AND gate AND3; the second input terminal of the first AND gate AND2 is used to access the data buffer enable signal EN11, and the second input terminal of the second AND gate AND3 is used to access the address decoding enable signal EN12, so that after receiving the chip wake-up signal EN0, the circuit enable control module 120 will, based on the chip wake-up signal EN0, combine the chip select... The signal CS and the enable signal of the chip auxiliary circuit 130 are comprehensively judged to output the enable signal of the corresponding auxiliary circuit when all conditions are met. That is, when the chip is indeed woken up and selected, and the corresponding chip auxiliary circuit 130 is also allowed to work, the enable signal of the corresponding auxiliary circuit is immediately output to quickly start reading related circuits (including address decoding circuit, data buffer circuit, etc.), so that it switches from sleep state to working state. In conjunction with the address detection signal OUT1, the address is located. In conjunction with the chip select detection signal OUT2, the target chip is activated. That is, the power path to the address decoding circuit and the data buffer circuit is immediately opened, or its sleep state is released, so that it enters full-speed working mode in an instant to ensure normal execution of read and write operations.

[0070] As a specific implementation, the circuit enable control module 120 can employ a hybrid analog-digital design to achieve higher precision power consumption regulation. In this implementation, the operational amplifier OP is configured in high-speed voltage comparator mode, with its power supply VDD directly controlled by the chip select signal line. The chip select signal CS provided by the chip select signal line can be used as the operational amplifier OP's enable signal, thus enabling the operational amplifier OP through the chip select signal CS. For example, when the chip is not selected, the chip select signal CS is high, and the constant current source of the operational amplifier OP can be cut off by a transistor based on the chip select signal CS, causing its power consumption to return to zero. Once the chip select signal CS becomes effectively low, the operational amplifier OP immediately establishes its operating bias. The inverting input of the operational amplifier OP is connected to a reference voltage signal Vref generated by a bandgap reference source, while the non-inverting input is connected to the chip wake-up signal EN0. This design allows the output of the operational amplifier OP to achieve a nanosecond-level toggle response upon arrival of the wake-up pulse. The eleventh inverter A11 converts this analog pulse into a standard CMOS logic level and distributes it to the subsequent digital logic. One input of the first AND gate AND2 is connected to the logic signal, and the other input is connected to the firmware-defined data buffer enable signal EN11. The first enable signal EN21, controlling the operation of the data buffer circuit, is only output when both hardware wake-up and software authorization are present. Similarly, the second AND gate AND3 manages the address decoding circuit. This structure, based on the collaboration of hardware comparators and logic gates, can flexibly determine whether to enable only the address decoding circuit or simultaneously enable the data buffer circuit according to different access request types, such as reading only registers or reading large memory arrays, thereby optimizing power distribution at a finer granularity.

[0071] Specifically, during the control of the read circuit's operating state, the operational amplifier (OP) enable signal enables the OP. When pulled low, the OP operates, and its output depends on two input signals. When the OP enable signal goes high, the OP stops operating and outputs a high level. Since the data buffer circuit enable and address decoding circuit enable are always high (i.e., the data buffer enable signal EN11 connected to the second input of the first AND gate AND2 and the address decoding enable signal EN12 connected to the second input of the second AND gate AND3 are always high), when the OP enable signal goes low, the pulse of the chip wake-up signal EN0 is transmitted to the circuit, pulling the OP output low for one pulse width. Through the eleventh inverter A11, this makes the first enable signal EN21 output by the first AND gate AND2 a high-level signal. This high-level signal serves as the final enable signal for the data buffer circuit, allowing it to operate normally. Similarly, the second enable signal EN22 output by the second AND gate AND3 is also a high-level signal, which can also serve as the final enable signal for the data buffer circuit, enabling it to operate normally. When the op-amp enable signal goes high, the op-amp output is pulled high. Through the eleventh inverter A11, both the first enable signal EN21 output by the first AND gate AND2 and the second enable signal EN22 output by the second AND gate AND3 are low-level signals, causing the address decoding circuit and data buffer circuit to pause operation. Based on this principle, after the circuit enable control module 120 receives the chip wake-up signal EN0, it immediately outputs an enable signal, quickly activating the chip auxiliary circuit 130 (including the address decoding circuit, data buffer circuit, etc.) related to reading, switching it from sleep state to working state. This, combined with the address detection signal OUT1, completes address location, and with the chip select detection signal OUT2, activates the target chip, ensuring normal execution of read and write operations.

[0072] A sleep mechanism is implemented when there is no signal. That is, when the signal detection trigger module 110 does not detect the level change of the subsequent address signal Addr within a preset time and the op-amp enable signal returns to an invalid high level, it is determined that the current read / write operation has ended or is a false trigger. At this time, a reset signal can be output by the reset circuit module 610 to trigger the reset of each D flip-flop. The address detection signal OUT1 and the chip select detection signal OUT2 both become invalid. The circuit enable control module 120 shuts off the power supply to the read-related circuit or puts it into sleep mode, retaining only the low-power operating state of the signal detection trigger module 110.

[0073] In this circuit, the operational amplifier (OP) is used as a comparator with an enable input. Its enable signal is configured to connect to the chip select signal CS, while its second input is connected to a preset reference voltage signal Vref. When the chip select signal CS is valid, the operational amplifier OP is activated and begins comparing the chip wake-up signal EN0 with the reference voltage. Assuming the chip wake-up signal EN0 is a valid low-level pulse, when this low level is lower than the reference voltage, the output of the operational amplifier OP will output a low-level signal. This low-level signal is inverted by the eleventh inverter A11, becoming a high-level signal. This high-level signal output by the eleventh inverter A11 can be considered a general enable signal, which is simultaneously sent to the first AND gate AND2 and the second AND gate AND3. After receiving this high-level general enable signal, the first AND gate AND2 checks its other input, the data buffer enable signal EN11. Only when both inputs are high will the first AND gate AND2 output a high-level first enable signal EN21 to activate the data buffer circuit. Similarly, the second AND gate AND3 will also determine whether to output a high-level second enable signal EN22 to start the address decoding circuit based on the overall enable signal and the address decoding enable signal EN12. This design achieves independent and precise control of the data buffer circuit and the address decoding circuit, ensuring that they are only activated when the chip is woken up, selected, and allowed to operate. This effectively reduces chip power consumption while ensuring the accuracy and timeliness of address and chip select signal CS detection.

[0074] To address the high power consumption issue caused by the continuously powered-on design of chip detection circuits in existing technologies, embodiments of this application also provide a chip control method. For example... Figure 8 As shown, the chip control method provided in this application embodiment may specifically include the following steps: Step 810: Detect the address level transition signal based on the address signal of the chip; Step 820: Based on the address level transition signal and the chip select signal of the chip, output a chip wake-up signal; Step 830: Based on the chip wake-up signal and the chip select signal, and in conjunction with the enable signal of the chip auxiliary circuit, control the working state of the chip auxiliary circuit.

[0075] In specific implementations, the chip control method provided in this application embodiment can be applied to a chip, which serves as a computer-readable storage medium and may specifically include a chip auxiliary circuit 130 and a chip control circuit 100 as provided in any of the above embodiments. The chip control method provided in this application embodiment can be executed within the chip. By detecting address level transition signals based on the chip's address signals, and based on the detected address level transition signals combined with the chip select signal, a chip wake-up signal is output. Based on this chip wake-up signal and the chip select signal, combined with the enable signal of the chip auxiliary circuit itself, the operating state of the chip auxiliary circuit is dynamically controlled, enabling it to start when needed and sleep when idle. This achieves on-demand wake-up of the chip auxiliary circuit's operating state, effectively reducing the chip's ineffective power consumption in standby, low-load, or no-read / write operation scenarios, and improving the chip's energy efficiency and battery life.

[0076] Reference Figure 9 The diagram illustrates a structural schematic of a memory chip according to an embodiment of this application. Figure 9 As shown, the memory chip 900 provided in this application embodiment includes a chip control circuit 100, which is the chip control circuit provided in any of the circuit embodiments of this application.

[0077] It should be noted that the method and memory chip embodiments are basically similar to the chip control circuit embodiments, so the description is relatively simple. For relevant parts, please refer to the description of the chip control circuit embodiments.

[0078] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0079] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0080] The above description is merely an embodiment of this application and is not intended to limit the scope of protection of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A chip control circuit, characterized in that, include: Signal detection trigger module and circuit enable control module; The signal detection trigger module is used to detect the address level transition signal based on the chip's address signal, and output a chip wake-up signal based on the address level transition signal and the chip select signal of the chip. The circuit enable control module is used to control the working state of the chip auxiliary circuit based on the chip wake-up signal and the chip select signal, combined with the enable signal of the chip auxiliary circuit.

2. The chip control circuit according to claim 1, characterized in that, The signal detection triggering module includes: an address detection circuit submodule, a chip select detection circuit submodule, and a wake-up submodule; The address detection circuit submodule is used to detect the address level transition signal based on the address signal, and output the address detection signal to the wake-up submodule based on the address level transition signal. The chip select detection circuit submodule is used to detect the falling edge signal of the chip select based on the chip select signal, and output the chip select detection signal to the wake-up submodule based on the falling edge signal of the chip select. The wake-up submodule is used to output the chip wake-up signal to the circuit enable control module based on the address detection signal and the chip select detection signal.

3. The chip control circuit according to claim 2, characterized in that, The address level transition signal includes an address rising edge signal and an address falling edge signal, and the address detection circuit submodule includes: an address rising edge detection branch, an address falling edge detection branch, and an address detection output unit; The address rising edge detection branch is used to detect the address rising edge signal based on the address signal, and output the address rising edge detection signal corresponding to the address rising edge signal. The address falling edge detection branch is used to detect the address falling edge signal based on the address signal, and output the address falling edge detection signal corresponding to the address falling edge signal; The address detection output unit includes: a first NOR gate and a first inverter; The first input terminal of the first NOR gate is electrically connected to the output terminal of the address rising edge detection branch, the second input terminal of the first NOR gate is electrically connected to the output terminal of the address falling edge detection branch, the output terminal of the first NOR gate is electrically connected to the input terminal of the first inverter, the output terminal of the first inverter is electrically connected to the output terminal of the address detection output unit, and the output terminal of the address detection output unit is used to output the address detection signal.

4. The chip control circuit according to claim 3, characterized in that, The address rising edge detection branch includes: a second inverter, a first transistor, a second transistor, a first resistor, a third inverter, a first capacitor, and a second NOR gate; The input terminal of the second inverter, the first input terminal of the second NOR gate, and the input terminal of the address detection circuit submodule are electrically connected, and the input terminal of the address detection circuit submodule is used to receive the address signal; The output terminal of the second inverter, the control terminal of the first transistor, and the control terminal of the second transistor are electrically connected. The first terminal of the first transistor is electrically connected to the power supply terminal of the address detection circuit submodule. The second terminal of the first transistor, the first terminal of the first resistor, the first terminal of the first capacitor, and the input terminal of the third inverter are electrically connected. The first terminal of the second transistor is electrically connected to the second terminal of the first resistor, and the second terminal of the second transistor and the second terminal of the first capacitor are respectively electrically connected to the reference ground terminal of the address detection circuit submodule. The output terminal of the third inverter is electrically connected to the second input terminal of the second NOR gate, the output terminal of the second NOR gate is electrically connected to the first terminal of the address detection output unit, and the output terminal of the second NOR gate is used to output the address rising edge detection signal. The address falling edge detection branch includes: a fourth inverter, a fifth inverter, a third transistor, a fourth transistor, a second resistor, a sixth inverter, a second capacitor, and a third NOR gate; The input terminal of the fourth inverter is electrically connected to the input terminal of the address detection circuit submodule, and the output terminal of the fourth inverter, the input terminal of the fifth inverter, and the first input terminal of the third NOR gate are electrically connected. The output terminal of the fifth inverter, the control terminal of the third transistor, and the control terminal of the fourth transistor are electrically connected. The first terminal of the third transistor is electrically connected to the power supply terminal of the address detection circuit submodule. The second terminal of the third transistor, the first terminal of the second resistor, the first terminal of the second capacitor, and the input terminal of the sixth inverter are electrically connected. The first terminal of the fourth transistor is electrically connected to the second terminal of the second resistor, and the second terminal of the fourth transistor and the second terminal of the second capacitor are respectively electrically connected to the reference ground terminal of the address detection circuit submodule. The output terminal of the sixth inverter is electrically connected to the second input terminal of the third NOR gate, and the output terminal of the third NOR gate is electrically connected to the second terminal of the address detection output unit. The output terminal of the third NOR gate is used to output the address falling edge detection signal.

5. The chip control circuit according to claim 3, characterized in that, The address detection output unit further includes: a first filter and a first trigger; The input terminal of the first filter is electrically connected to the output terminal of the first inverter, the output terminal of the first filter is electrically connected to the input terminal of the first flip-flop, and the output terminal of the first flip-flop serves as the output terminal of the address detection output unit. The first filter is used to filter the output signal of the first inverter and output an address detection filter signal. The first trigger is used to output the address detection signal based on the address detection filter signal and the chip's reset signal.

6. The chip control circuit according to claim 2, characterized in that, The chip select detection circuit submodule includes: a chip select falling edge detection branch, a second filter, and a second flip-flop; The chip select falling edge detection branch is used to detect the chip select falling edge signal based on the chip select signal, and output the chip select falling edge detection signal corresponding to the chip select falling edge signal; The second filter is used to filter the chip select falling edge detection signal and output the chip select detection filter signal corresponding to the chip select falling edge detection signal to the second flip-flop. The second trigger is used to output the chip select detection signal based on the chip select detection filter signal and the chip reset signal.

7. The chip control circuit according to claim 6, characterized in that, The chip select falling edge detection branch includes: a seventh inverter, a fifth transistor, a sixth transistor, a third resistor, an eighth inverter, a ninth inverter, a third capacitor, a first NAND gate, and a tenth inverter; The input terminal of the seventh inverter is electrically connected to the input terminal of the chip select detection circuit submodule. The output terminal of the seventh inverter, the control terminal of the fifth transistor, the control terminal of the sixth transistor, and the first input terminal of the first NAND gate are electrically connected. The input terminal of the chip select detection circuit submodule is used to receive the chip select signal. The first terminal of the fifth transistor is electrically connected to the power supply terminal of the chip select detection circuit submodule. The second terminal of the fifth transistor, the first terminal of the third resistor, the first terminal of the third capacitor, and the input terminal of the eighth inverter are electrically connected. The output terminal of the eighth inverter is electrically connected to the input terminal of the ninth inverter. The first terminal of the sixth transistor is electrically connected to the second terminal of the third resistor, and the second terminal of the sixth transistor and the second terminal of the third capacitor are respectively electrically connected to the reference ground terminal of the chip select detection circuit submodule. The output terminal of the ninth inverter is electrically connected to the second input terminal of the first NAND gate, and the output terminal of the first NAND gate is electrically connected to the input terminal of the tenth inverter. The output terminal of the tenth inverter serves as the output terminal of the chip select falling edge detection branch, and the output terminal of the chip select falling edge detection branch is used to output the chip select falling edge detection signal.

8. The chip control circuit according to any one of claims 5 to 6, characterized in that, Also includes: Reset circuit module; The reset circuit module is configured to output the reset signal when the address detection circuit submodule does not detect the address level transition signal within a preset time and the chip select signal is at a preset invalid level. The chip auxiliary circuit includes a data buffer circuit and an address decoding circuit. The enable signal includes a data buffer enable signal corresponding to the data buffer circuit and an address decoding enable signal corresponding to the address decoding circuit. The circuit enable control module includes an operational amplifier, an eleventh inverter, a first AND gate, and a second AND gate. The first input terminal of the operational amplifier is electrically connected to the output terminal of the signal detection trigger module, and the output terminal of the operational amplifier is electrically connected to the input terminal of the eleventh inverter. The output terminal of the eleventh inverter, the first input terminal of the first AND gate, and the first input terminal of the second AND gate are electrically connected. The second input terminal of the first AND gate is used to receive the data buffer enable signal, and the second input terminal of the second AND gate is used to receive the address decoding enable signal. The operational amplifier is used to output the operational amplifier output signal corresponding to the chip wake-up signal to the input terminal of the eleventh inverter under the control of the chip select signal, based on the chip wake-up signal and a preset reference voltage signal. The first AND gate is used to output a first enable signal based on the output signal of the eleventh inverter and the data buffer enable signal. The first enable signal is used to control the working state of the data buffer circuit. The second AND gate is used to output a second enable signal based on the output signal of the eleventh inverter and the address decoding enable signal. The second enable signal is used to control the working state of the address decoding circuit.

9. A chip control method, characterized in that, The chip includes a chip auxiliary circuit and a chip control circuit as described in any one of claims 1 to 8, and the method includes: The address level transition signal is detected based on the address signal of the chip; Based on the address level transition signal and the chip select signal of the chip, a chip wake-up signal is output. Based on the chip wake-up signal and the chip select signal, combined with the enable signal of the chip auxiliary circuit, the working state of the chip auxiliary circuit is controlled.

10. A memory chip, characterized in that, The memory chip includes the chip control circuit as described in any one of claims 1-8.

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