Semiconductor structure and method for preparing same

Abstract

A semiconductor structure and a method for preparing same. The method for preparing the semiconductor structure comprises: providing a substrate and forming a stacked structure on the substrate, the stacked structure comprising first dielectric layers and second dielectric layers stacked in a vertical direction; forming through-holes passing through the stacked structure in the vertical direction, the through-holes comprising a first hole and a second hole, each through-hole exposing a portion of a surface of the substrate, and a bottom surface of each through-hole being flush with or lower than a top surface of the substrate; forming a sidewall protection layer on an inner wall of each through-hole; forming a bottom protection layer on the portion of the surface of the substrate exposed by each through-hole; filling each through-hole with an isolation layer; removing the isolation layer and a portion of the sidewall protection layer in the first hole, and forming a transistor structure in the first hole; and removing the isolation layer and a portion of the sidewall protection layer in the second hole, and forming a capacitor structure in the second hole, the capacitor structure being electrically connected to the transistor structure. The described method for preparing the semiconductor structure can improve the performance stability of the semiconductor structure.

Description

Semiconductor structure and its preparation method

[0001] Cross-referencing

[0002] This disclosure claims priority to Chinese invention patent application No. 202411195334.9, filed on August 27, 2024, entitled "Semiconductor Structure and Preparation Method Thereof", the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and its fabrication method. Background Technology

[0004] The development of dynamic memory (DRAM) pursues performance indicators such as high speed, high integration density, and low power consumption. As the size of semiconductor device structures shrinks, the technological barriers encountered by existing structures are becoming increasingly apparent. Therefore, developing more novel structures based on existing structures is a powerful means to break through existing technological barriers.

[0005] The emergence of three-dimensional dynamic random access memory (3D DRAM), especially 3D DRAM that includes multilayer horizontal cell (MHC), typically comprising multiple transistors and multiple capacitors stacked on a substrate, has met the above requirements.

[0006] However, during the fabrication of structures such as transistors and capacitors, etching processes can easily lead to substrate damage or the removal of impurities, thereby affecting the device performance of transistors and capacitors and reducing the stability of dynamic memory. Summary of the Invention

[0007] According to a first aspect of the present disclosure, a method for fabricating a semiconductor structure is provided, comprising: providing a substrate and forming a stacked structure on the substrate, the stacked structure including a first dielectric layer and a second dielectric layer stacked in a vertical direction; forming a through-hole penetrating the stacked structure in a vertical direction, the through-hole including a first hole and a second hole, the through-hole exposing a portion of the surface of the substrate, the bottom surface of the through-hole being flush with or lower than the top surface of the substrate; forming a sidewall protection layer on the inner wall of the through-hole; forming a bottom protection layer on the portion of the substrate surface exposed by the through-hole; filling an isolation layer in the through-hole; removing the isolation layer and a portion of the sidewall protection layer in the first hole, and forming a transistor structure in the first hole; removing the isolation layer and a portion of the sidewall protection layer in the second hole, and forming a capacitor structure in the second hole, the capacitor structure being electrically connected to the transistor structure.

[0008] In some embodiments, the bottom surface of the via is lower than the top surface of the substrate, and forming a bottom protective layer on the portion of the substrate exposed by the via includes: forming a monocrystalline silicon layer on the portion of the substrate exposed by the via using a first epitaxial growth process, wherein the top surface of the monocrystalline silicon layer is lower than the top surface of the substrate; and forming a silicon-germanium layer on the monocrystalline silicon layer using a second epitaxial growth process, wherein the thickness of the monocrystalline silicon layer is less than the thickness of the silicon-germanium layer.

[0009] In some embodiments, forming a transistor structure within a first hole includes: forming a channel layer on the sidewall of the first hole corresponding to a second dielectric layer; forming a gate dielectric layer covering the channel layer, the gate dielectric layer covering the top surface of a bottom protective layer at the bottom of the first hole; and forming a gate structure filling the first hole, the projection of the channel layer in the vertical direction being an annular shape surrounding the gate structure.

[0010] In some embodiments, forming a capacitor structure within a second hole includes: removing a portion of the second dielectric layer laterally along the second hole to form a capacitor groove; forming a lower electrode layer covering the inner wall of the capacitor groove; forming a capacitor dielectric layer covering the lower electrode layer, the capacitor dielectric layer covering a bottom protective layer at the bottom of the second hole; and forming an upper electrode layer covering the capacitor dielectric layer and filling the second hole.

[0011] In some embodiments, the vias include a plurality of via groups arranged along a second direction, each via group including a first hole and a second hole arranged along a first direction; the transistor structure in each first hole includes a plurality of transistor units spaced apart along a vertical direction; the capacitor structure in each second hole includes a plurality of capacitor units spaced apart along a vertical direction; the method further includes: forming a linear groove on one side of the via along the first direction; removing a portion of the second dielectric layer laterally along the linear groove to form a bit line groove; forming a bit line structure filling the bit line groove, the bit line structure extending along the second direction, and the plurality of bit line structures spaced apart along a vertical direction, each bit line structure being electrically connected to a plurality of transistor units located in the same layer.

[0012] According to a second aspect of the present disclosure, a semiconductor structure is provided, comprising: a substrate and a stacked structure located on the surface of the substrate, the stacked structure including a first dielectric layer and a second dielectric layer stacked in a vertical direction; a through-hole penetrating the stacked structure in a vertical direction, the through-hole including a first hole and a second hole; a bottom protective layer located at the bottom of the through-hole and a sidewall protective layer surrounding the bottom protective layer, the bottom protective layer being in contact with the substrate; a transistor structure located in the first hole; and a capacitor structure located in the second hole, the capacitor structure being electrically connected to the transistor structure.

[0013] In some embodiments, the vias include multiple via groups arranged along a second direction, each via group including a first hole and a second hole arranged along a first direction; the transistor structure in each first hole includes multiple transistor units spaced apart along a vertical direction; the capacitor structure in each second hole includes multiple capacitor units spaced apart along a vertical direction; the semiconductor structure also includes bit line structures extending along the second direction, and multiple bit line structures spaced apart along a vertical direction, each bit line structure being electrically connected to multiple transistor units located on the same layer.

[0014] In some embodiments, the transistor structure includes: a channel layer located on the sidewall of the first hole corresponding to the second dielectric layer; a gate dielectric layer covering the channel layer, the sidewall of the first hole corresponding to the second dielectric layer, and the top surface of the bottom protective layer; and a gate structure extending in a vertical direction and filling the first hole, wherein the projection of the channel layer in the vertical direction is annular around the gate structure.

[0015] In some embodiments, the capacitor structure includes: a lower electrode layer located on the sidewall of the second hole corresponding to the second dielectric layer, the projection of the lower electrode layer in the vertical direction being annular; a capacitor dielectric layer covering the bottom protective layer at the bottom of the second hole; and an upper electrode layer covering the capacitor dielectric layer and filling the second hole.

[0016] In some embodiments, the bottom protective layer includes a monocrystalline silicon layer and a silicon-germanium layer located on the monocrystalline silicon layer, the top surface of the monocrystalline silicon layer being lower than the top surface of the substrate, the top surface of the silicon-germanium layer being lower than the top surface of the first dielectric layer located closest to the substrate, and the thickness of the monocrystalline silicon layer being less than the thickness of the silicon-germanium layer.

[0017] In this embodiment, by providing a bottom protective layer and a sidewall protective layer at the bottom of the via, the substrate is protected by the bottom protective layer and the sidewall protective layer, avoiding damage to the substrate when removing the isolation layer, reducing the possibility of leakage current in the transistor structure and capacitor structure, thereby improving the performance stability of the semiconductor structure. Attached Figure Description

[0018] Figure 1 is a flowchart illustrating a method for fabricating a semiconductor structure according to an exemplary embodiment;

[0019] Figures 2-5 are schematic diagrams illustrating the semiconductor structure fabrication process for forming through-holes according to an exemplary embodiment;

[0020] Figures 6 and 7 are schematic diagrams illustrating the semiconductor structure fabrication process of forming a bottom protective layer and an isolation layer in a via according to an exemplary embodiment;

[0021] Figures 8-10 are schematic diagrams illustrating the semiconductor structure fabrication process of forming a bottom protective layer and an isolation layer in a via according to another exemplary embodiment;

[0022] Figures 11-13 are schematic diagrams illustrating the semiconductor structure fabrication process of forming a bottom protective layer and an isolation layer in a via according to yet another exemplary embodiment;

[0023] Figures 14-21 are schematic diagrams illustrating a semiconductor structure fabrication process in which transistor and capacitor structures are formed in vias, according to an exemplary embodiment.

[0024] Explanation of reference numerals in the attached figures: 10-Semiconductor structure; 110-Substrate; 110R-Substrate recess; 120-Stacked structure; 121-First dielectric layer; 122-Second dielectric layer; 130-Through hole; 131-First hole; 132-Second hole; 130G-Through hole group; 210-Sidewall protection material layer; 211-Sidewall protection layer; 311-Bottom protection layer; 311a-Single crystal silicon layer; 311b-Silicon germanium layer; 320-Isolation layer; 411-Mask layer; 411T-Line groove; 412-Bit line structure; 412T-Bit line groove; 413-Third dielectric layer; 510-Capacitor structure; 510C-Capacitor Unit; 510T - Capacitor trench; 511 - Lower electrode layer; 511a - Upper parallel portion; 511b - Lower parallel portion; 511c - Vertical portion; 512 - Capacitor dielectric layer; 513 - Upper electrode layer; 513a - First upper electrode layer; 513b - Second upper electrode layer; 610 - Transistor structure; 610C - Transistor unit; 611 - Channel layer; 612 - Gate dielectric layer; 613 - Gate structure; X - First direction; Y - Second direction; Z - Vertical direction. Detailed Implementation

[0025] The technical solutions of this disclosure will be further described in detail below with reference to the accompanying drawings and embodiments. Although exemplary embodiments of this disclosure are shown in the drawings, it should be understood that this disclosure can be implemented in various forms and should not be limited to the embodiments described herein. Rather, these embodiments are provided to enable a more thorough understanding of this disclosure and to fully convey the scope of this disclosure to those skilled in the art.

[0026] The present disclosure is described in more detail below by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will become clearer from the following description and claims. It should be noted that the drawings are in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present disclosure.

[0027] It is understood that the meanings of “on”, “above” and “above” in this disclosure should be interpreted in the broadest sense, such that “on” means not only that it is “on” something without any intervening feature or layer (i.e., directly on something), but also that it is “on” something with an intervening feature or layer.

[0028] In the embodiments of this disclosure, the terms "first," "second," "third," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0029] In embodiments of this disclosure, the term "layer" refers to a portion of material comprising a region having thickness. A layer may extend over the entirety of a lower or upper structure, or may have a range smaller than that of the lower or upper structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or a layer may be located between any horizontal faces at the top and bottom surfaces of the continuous structure. A layer may extend horizontally, vertically, and / or along an inclined surface. A layer may include multiple sublayers.

[0030] It should be noted that the technical solutions described in the embodiments of this disclosure can be combined arbitrarily without conflict.

[0031] In some embodiments, during the fabrication of structures such as transistors and capacitors on a substrate, a dielectric layer and a sacrificial material are formed on the substrate, and the sacrificial material in the dielectric layer is removed by an etching process to form vias exposing the substrate surface. However, the inventors of this application have discovered that in actual fabrication, because the sacrificial material needs to have high etch selectivity with the dielectric layer, the etch selectivity of the sacrificial material and the substrate are usually close. However, during the removal of the sacrificial material from the vias or the cleaning of the vias, there is a risk of substrate damage or the peeling off of impurities from the substrate sidewalls at the bottom of the vias. This can affect the device performance of transistors, capacitors, and other structures subsequently formed on the damaged substrate surface, and reduce the overall performance stability and structural stability of the semiconductor structure.

[0032] In view of this, in order to solve the above problems, this disclosure provides a method for preparing a semiconductor structure 10.

[0033] Figure 1 is a flowchart illustrating a method for fabricating a semiconductor structure according to an exemplary embodiment. Figures 2-7 and 14-21 are schematic diagrams illustrating a process for fabricating a semiconductor structure according to an exemplary embodiment. Figures 8-10 are schematic diagrams illustrating a process for fabricating a semiconductor structure according to another exemplary embodiment. Figures 11-13 are schematic diagrams illustrating a process for fabricating a semiconductor structure according to yet another exemplary embodiment. The semiconductor structure 10 and its fabrication process will be described below with reference to Figures 1 and 2 to 21.

[0034] It is understood that in Figures 2 to 21, the first direction X and the second direction Y are horizontal directions parallel to the plane where the substrate 110 is located, and the first direction X intersects the second direction Y. For example, the first direction X can be perpendicular to the second direction Y. The vertical direction Z is the direction that intersects with the plane where the substrate 110 is located. For example, the vertical direction Z is perpendicular to the plane where the substrate 110 is located.

[0035] Referring to Figure 1, the method for fabricating the semiconductor structure provided in this disclosure includes at least the following steps:

[0036] Step S101: Provide a substrate and form a stacked structure on the substrate, the stacked structure including a first dielectric layer and a second dielectric layer stacked in a vertical direction;

[0037] Step S102: Form a through hole that penetrates the stacked structure in a vertical direction. The through hole includes a first hole and a second hole. The through hole exposes part of the substrate surface. The bottom surface of the through hole is flush with or lower than the top surface of the substrate.

[0038] Step S103: Form a sidewall protective layer on the inner wall of the through hole;

[0039] Step S104: Form a bottom protective layer on the surface of the substrate portion exposed by the via;

[0040] Step S105: Fill the via with an isolation layer;

[0041] Step S106: Remove the isolation layer and part of the sidewall protective layer inside the first hole, and form a transistor structure inside the first hole;

[0042] Step S107: Remove the isolation layer and part of the sidewall protective layer inside the second hole, and form a capacitor structure inside the second hole. The capacitor structure is electrically connected to the transistor structure.

[0043] It should be understood that the steps shown in Figure 1 are not exclusive, and other steps may be performed before, after, or between any of the steps shown in the operation; the order of the steps shown in Figure 1 may be adjusted according to actual needs.

[0044] Referring to FIG2, a stacked structure 120 is formed on the substrate 110, the stacked structure 120 including a first dielectric layer 121 and a second dielectric layer 122 alternately stacked in the vertical direction. The material of the substrate 110 may include silicon, for example, monocrystalline silicon, polycrystalline silicon or amorphous silicon.

[0045] The first dielectric layer 121 and the second dielectric layer 122 are made of different materials, and can be two of the insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide. The first dielectric layer 121 and the second dielectric layer 122 can be formed alternately in sequence using a deposition process. The deposition process can include chemical vapor deposition (CVD), atomic layer deposition (ALD), plasma-enhanced ALD, physical vapor deposition (PVD), plasma-enhanced chemical vapor deposition (PECVD), or low-pressure chemical vapor deposition (LPCVD), etc. In one example, the first dielectric layer 121 covers the top surface of the substrate 110, that is, the bottom layer of the stacked structure 120 is the first dielectric layer 121, and the top layer of the stacked structure 120 can be the second dielectric layer 122.

[0046] Referring to FIG3, a through-hole 130 is formed through the stacked structure 120 in a vertical direction Z. The bottom of the through-hole 130 exposes a portion of the surface of the substrate 110, and the bottom surface of the through-hole 130 may be flush with the top surface of the substrate 110. In other examples, a portion of the substrate 110 may be removed so that the bottom surface of the through-hole 130 is lower than the top surface of the substrate 110.

[0047] The via 130 includes a first hole 131 and a second hole 132. The first hole 131 is used to form a transistor, and the second hole 132 is used to form a capacitor. The cross-section of the first hole 131 and the second hole 132 in the via 130 on the horizontal plane formed by the first direction X and the second direction Y can be circular, elliptical, or rectangular. Multiple first holes 131 can be arranged at intervals along the second direction Y, and multiple second holes 132 can be arranged at intervals along the second direction Y. In some examples, multiple first holes 131 can be arranged at equal intervals along the second direction Y, and multiple second holes 132 can be arranged at equal intervals along the second direction Y. The columns formed by the multiple first holes 131 and the columns formed by the multiple second holes 132 can be arranged at intervals along the first direction X. In one example, a first hole 131 and an adjacent second hole 132 along the first direction X may have the same central axis, and this central axis is parallel to the first direction X. A first hole 131 and an adjacent second hole 132 along the first direction X may constitute a through-hole group 130G, and multiple through-hole groups 130G are arranged at intervals along the second direction Y. The distance between the first hole 131 and the second hole 132 in a through-hole group 130G is smaller than the distance between two adjacent through-hole groups 130G.

[0048] In some embodiments, a patterned mask layer (not shown) may be formed on the stacked structure 120. Using the patterned mask layer as a mask, a dry etching process is used to partially remove the stacked structure 120 to simultaneously form the first hole 131 and the second hole 132. In other examples, the patterned first mask layer may be used to form the first hole 131 in the stacked structure 120, then the patterned first mask layer may be removed, and then a patterned second mask layer may be used to form the second hole 132 in the stacked structure 120.

[0049] Referring to Figures 4 and 5, a conformal sidewall protective material layer 210 is formed on the exposed surface of the stacked structure 120 with through-holes 130 using a deposition process. After removing portions of the sidewall protective material layer 210 located on the top surface of the stacked structure 120 and the bottom of the through-holes 130, the sidewall protective layer 211 located on the inner wall of the through-holes 130 is retained. The material of the sidewall protective layer 211 can be silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, or other insulating materials. The sidewall protective layer 211 is used to improve the uniformity of the material and contour of the inner wall of the through-holes 130 in subsequent processes and to reduce impurity spalling.

[0050] In some embodiments, referring to FIG6, a bottom protective layer 311 is formed on a portion of the substrate 110 exposed at the bottom of the via 130, and referring to FIG7, an isolation layer 320 is filled within the via 130. The thickness of the bottom protective layer 311 is less than the thickness of the first dielectric layer 121, that is, the top surface of the bottom protective layer 311 is lower than the top surface of the bottommost first dielectric layer 121. The bottommost first dielectric layer 121 is the first dielectric layer 121 closest to the substrate 110.

[0051] The bottom protective layer 311 can be formed by epitaxial growth or deposition. For example, if the substrate 110 is a single-crystal silicon layer, the bottom protective layer 311 can be a silicon-germanium layer (SiGe) formed by epitaxial growth of the single-crystal silicon layer. Epitaxial growth allows for selective formation of silicon-germanium layers on a portion of the exposed surface of the substrate 110, effectively reducing the amount and coverage area of ​​the silicon-germanium layer, thereby reducing germanium contamination caused by the silicon-germanium layer. Furthermore, the silicon-germanium layer formed by epitaxial growth has good adhesion to the single-crystal silicon layer, effectively preventing peeling off the silicon-germanium layer.

[0052] The isolation layer 320 covers the sidewall protection layer 211 and the bottom protection layer 311 and fills the via 130. A deposition process can be used to form the isolation material layer, and a chemical mechanical polishing process can be used to remove part of the isolation material layer on the top surface of the stacked structure 120, leaving only the isolation material layer in the via 130 as the isolation layer 320. The top surface of the isolation layer 320 can be flush with the top surface of the stacked structure 120. The material of the isolation layer 320 has high etch selectivity with the first dielectric layer 121, the second dielectric layer 122, the bottom protection layer 311, and the sidewall protection layer 211. For example, the material of the isolation layer 320 can be polysilicon. Polysilicon has similar etch selectivity to the substrate 110. If the isolation layer 320 is formed directly on the substrate 110, the removal of the isolation layer 320 may damage the substrate 110, causing a depression in the substrate 110 and increasing the risk of leakage.

[0053] In some other embodiments, referring to FIG8, when forming the via 130, a portion of the substrate 110 may be removed to form a substrate recess 110R on the surface of the substrate 110, i.e., the bottom surface of the via 130 is lower than the top surface of the substrate 110. The height of the substrate recess 110R may be less than the thickness of the first dielectric layer 121 or the second dielectric layer 122. Referring to FIG9, a bottom protective layer 311 is formed on the portion of the substrate 110 exposed at the bottom of the via 130. Referring to FIG10, an isolation layer 320 is filled into the via 130, and the top surface of the bottom protective layer 311 is lower than the top surface of the first dielectric layer 121.

[0054] In some other embodiments, referring to FIG11, when forming the via 130, a portion of the substrate 110 may be removed to form a substrate recess 110R on the surface of the substrate 110. The bottom surface of the via 130 is lower than the top surface of the substrate 110. Forming a bottom protective layer 311 on the exposed portion of the substrate 110 surface by the via 130 includes: forming a single-crystal silicon layer 311a on the exposed portion of the substrate 110 surface by a first epitaxial growth process, wherein the top surface of the single-crystal silicon layer 311a is lower than the top surface of the substrate 110. Referring to FIG12, a silicon-germanium layer 311b is formed on the single-crystal silicon layer 311a by a second epitaxial growth process. The thickness of the single-crystal silicon layer 311a is less than the thickness of the silicon-germanium layer 311b. For example, the thickness of the single-crystal silicon layer 311a ranges from 1 nm to 3 nm, and the thickness of the silicon-germanium layer 311b is 3 nm to 6 nm. A single-crystal silicon layer 311a and a silicon-germanium layer 311b constitute the bottom protective layer 311. The single-crystal silicon layer 311a helps improve the adhesion between the silicon-germanium layer 311b and the substrate 110, preventing the silicon-germanium layer 311b from peeling off. Referring to FIG13, an isolation layer 320 is filled in the via 130, and the isolation layer 320 covers the top surface of the silicon-germanium layer 311b. The semiconductor precursor gas used in the first epitaxial growth process can be a silane-based semiconductor precursor gas, such as silane or disilane. The precursor gas used in the second epitaxial growth process can be a germanium-containing semiconductor precursor gas, such as disilane and germanane.

[0055] In some embodiments, the bit line structure 412 may be formed first, followed by the transistor structure 610 and the capacitor structure 510; alternatively, the transistor structure 610 and the capacitor structure 510 may be formed first, followed by the bit line structure 412. This disclosure does not limit the order in which the bit line structure 412, the transistor structure 610, and the capacitor structure 510 are formed. Referring to Figures 2-7 and 14-21, this disclosure will illustrate the example of forming the bit line structure first, followed by the transistor structure and the capacitor structure.

[0056] Referring to FIG14, a patterned mask layer 411 is formed on the stacked structure 120. The patterned mask layer 411 has an etch opening. A portion of the stacked structure 120 is removed along the etch opening to form a linear groove 411T on one side of the via 130 along the first direction X. The linear groove 411T extends along the second direction Y, penetrates the stacked structure 120 along the vertical direction Z, and exposes a portion of the surface of the substrate 110.

[0057] Referring to Figure 15, a portion of the second dielectric layer 122 is removed laterally along the linear groove 411T to form a bit groove 412T. The bit groove 412T communicates with the linear groove 411T and can be located on both sides of the linear groove 411T along the first direction X. Multiple bit grooves 412T are spaced apart in the vertical direction Z, with a first dielectric layer 121 separating adjacent bit grooves 412T along the vertical direction Z. The sidewalls of the bit grooves 412T can expose the sidewall protective layer 211 located at one end of the inner wall of the first hole 131 in the through hole 130.

[0058] Referring to FIG16, a bit line structure 412 is formed to fill the bit line groove 412T. The bit line structure 412 extends along the second direction Y and is filled with a third dielectric layer 413 in the linear groove 411T. The material of the third dielectric layer 413 can be at least one of insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide.

[0059] In some embodiments, the bit line structure 412 may be made of a conductive material. The conductive material may include one or more of the following: metals (e.g., tungsten (W), titanium (Ti), molybdenum (Mo), niobium (Nb), vanadium (V), hafnium (Hf), tantalum (Ta), chromium (Cr), zirconium (Zr), iron (Fe), ruthenium (Ru), cobalt (Co), nickel (Ni)); alloys (e.g., Co-based alloys, Ti-based alloys, Co and Ni-based alloys, Fe and Co-based alloys); materials containing conductive metals (e.g., conductive metal nitrides, conductive metal silicides, conductive metal carbides, conductive metal oxides); and conductive doped semiconductor materials (e.g., conductive doped polysilicon, conductive doped silicon-germanium). The bit line structure 412 may be a single-layer or multi-layer structure. For example, the bit line structure 412 may be a multi-layer structure composed of a conductive metal silicide layer, a titanium nitride layer, and a tungsten layer, wherein the conductive metal silicide layer is configured to directly contact and connect with the sidewall protection layer 211 for subsequent reduction of the contact resistance between the bit line structure 412 and the transistor structure.

[0060] In some embodiments, referring to FIG17-20, a capacitor structure 510 is formed in the second hole 132, including: removing a portion of the second dielectric layer 122 laterally along the second hole 132 to form a capacitor groove 510T; forming a lower electrode layer 511 covering the inner wall of the capacitor groove 510T; forming a capacitor dielectric layer 512 covering the lower electrode layer 511, the capacitor dielectric layer 512 covering the bottom protective layer 311 at the bottom of the second hole 132; and forming an upper electrode layer 513 covering the capacitor dielectric layer 512 and filling the second hole 132.

[0061] Referring to Figure 17, after removing the mask layer 411, an etching process is used to remove the isolation layer 320 located in the second hole 132, exposing the sidewall protective layer 211 and the bottom protective layer 311 located in the second hole 132. The etching process includes a dry etching process or a wet etching process. In one example, the material of the isolation layer 320 is polycrystalline silicon, and an ammonia-ultrapure water mixture (ADM) and / or tetramethyl ammonium hydroxide (TMAH, (CH3)4NOH) is used to remove the isolation layer 320. Since the ammonia-ultrapure water mixture and tetramethyl ammonium hydroxide have low etching selectivity for silicon nitride, silicon oxide, silicon germanium, etc., the etching selectivity ratio of the isolation layer 320, the bottom protective layer 311, and the sidewall protective layer 211 are all greater than 10:1. Therefore, damage to the sidewall protective layer 211, the bottom protective layer 311, and the substrate 110 can be avoided during the removal of the isolation layer 320 in the second hole 132.

[0062] Referring to FIG18, a portion of the sidewall protective layer 211 within the second hole 132 is removed, leaving the portion of the sidewall protective layer 211 covered by the bottom protective layer 311. This exposes the first dielectric layer 121 and the second dielectric layer 122 within the second hole 132. A portion of the second dielectric layer 122 is removed laterally along the second hole 132 to form a capacitor tank 510T. The sidewalls of the capacitor tank 510T expose the sidewall protective layer 211 located at the other end of the inner wall of the first hole 131 in the through hole 130. The capacitor tanks 510T arranged along the second direction Y are isolated from each other.

[0063] Referring to FIG19, an initial lower electrode layer is formed covering the inner wall of the capacitor tank 510T. A lower electrode protective layer 521, covering the initial lower electrode and filling the capacitor tank 510T, is filled. A portion of the initial lower electrode layer is removed, leaving only the lower electrode layer 511 located on the inner wall of the capacitor tank 510T. Multiple lower electrode layers 511 are arranged at intervals in the vertical direction Z. The projection of the lower electrode layer 511 onto the substrate 110 is annular. The lower electrode layer 511 may include an upper parallel portion 511a, a lower parallel portion 511b, and a vertical portion 511c connecting the upper parallel portion 511a and the lower parallel portion 511b. The projections of the upper parallel portion 511a and the lower parallel portion 511b onto the substrate 110 are overlapping annular shapes. The vertical portion 511c connects the outer edges of the upper parallel portion 511a and the lower parallel portion 511b. The thickness of the upper parallel portion 511a and the lower parallel portion 511b in the vertical direction Z can be equal to the thickness of the vertical portion 511c in the horizontal direction. The vertical portion 511c is in contact with the sidewall protective layer 211 located in the first hole 131.

[0064] Referring to FIG20, the lower electrode protective layer 521 is removed, and a capacitor dielectric layer 512 covering the lower electrode layer 511 is formed by conformal deposition. The capacitor dielectric layer 512 covers the bottom protective layer 311 at the bottom of the second hole 132 and the retained sidewall protective layer 211. An upper electrode layer 513 covering the capacitor dielectric layer 512 and filling the second hole 132 is formed by conformal deposition. The upper electrode layer 513 may include a first upper electrode layer 513a and a second upper electrode layer 513b. The first upper electrode layer 513a conformally covers the capacitor dielectric layer 512, and the second upper electrode layer 513b covers the first upper electrode layer 513a and fills the second hole 132. The second upper electrode layer 513b may have a columnar portion extending along the vertical direction Z and a protrusion protruding horizontally along the sidewall of the columnar portion. The columnar portion penetrates the stacked structure 120, and the protrusion is embedded in the capacitor slot 510T. The lower electrode layer 511, the capacitor dielectric layer 512 and the upper electrode layer 513 located in each capacitor slot 510T together constitute a capacitor unit 510C. The capacitor structure 510 in each second hole 132 includes a plurality of capacitor units 510C arranged at intervals along the vertical direction Z.

[0065] The lower electrode layer 511, the first upper electrode layer 513a, and the second upper electrode layer 513b can be made of conductive materials. The first upper electrode layer 513a and the second upper electrode layer 513b can be different; for example, the second upper electrode layer 513b can be a conductive doped polycrystalline silicon layer or a conductive doped silicon-germanium layer. The capacitor dielectric layer 512 can be made of a high dielectric constant material. High dielectric constant materials can include one or more of the following: hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, etc.

[0066] In some embodiments, referring to FIG21, forming a transistor structure 610 in a first hole 131 includes: forming a channel layer 611 in the sidewall of the first hole 131 corresponding to the second dielectric layer 122; forming a gate dielectric layer 612 covering the channel layer 611, the gate dielectric layer 612 covering the top surface of the bottom protective layer 311 at the bottom of the first hole 131; and forming a gate structure 613 filling the first hole 131, the projection of the channel layer 611 in the vertical direction Z being an annular shape surrounding the gate structure 613.

[0067] Referring to Figures 20-21, an etching process is used to remove the isolation layer 320 located in the first hole 131, exposing the sidewall protective layer 211 and the bottom protective layer 311 located in the first hole 131. In one example, the isolation layer 320 is polycrystalline silicon, and an ammonia-ultrapure water mixture and / or tetramethylammonium hydroxide are used to remove the isolation layer 320. Since the ammonia-ultrapure water mixture and tetramethylammonium hydroxide have low etching selectivity for silicon nitride, silicon oxide, silicon germanium, etc., damage to the sidewall protective layer 211, the bottom protective layer 311, and the substrate 110 can be avoided during the removal of the isolation layer 320 in the first hole 131.

[0068] Referring to Figure 21, a portion of the sidewall protective layer 211 within the first hole 131 is removed, while the portion of the sidewall protective layer 211 covered by the bottom protective layer 311 is retained. The first hole 131 exposes the bit line structure 412 and the lower electrode layer 511 of the capacitor structure 510 located in the layer containing the second dielectric layer 122. The bit line structure 412 and the lower electrode layer 511 are located at opposite ends of the first hole 131 along the first direction X. A channel layer 611 is formed on the sidewall of the first hole 131. The channel layer 611, the gate dielectric layer 612, and the gate structure 613 together constitute a transistor structure 610. Each transistor structure 610 in the first hole 131 includes multiple transistor units 610C spaced apart along the vertical direction Z. The transistor units 610C and capacitor units 510C are electrically connected in a one-to-one correspondence to form a 1T1C (One-transistor, one-capacitor) horizontal memory cell.

[0069] In some embodiments, the channel layer 611 may completely cover the sidewall of the first hole 131.

[0070] In some embodiments, referring to FIG21, after depositing a channel material layer that completely covers the sidewalls of the first hole 131, it is necessary to remove a portion of the channel material layer located on the sidewall of the first hole 131 corresponding to the first dielectric layer 121. The remaining channel layer 611 is only located on the sidewall of the first hole 131 corresponding to the second dielectric layer 122, thereby reducing the coupling between adjacent transistor cells 610C in the vertical Z direction. In addition, the first hole 131 corresponding to the second dielectric layer 122 can be partially removed, so that the subsequently formed gate structure 613 has a sawtooth profile, that is, the size of the first portion of the gate structure 613 surrounded by the channel layer 611 is smaller than the size of the second portion between the first portions, and the second portion is not surrounded by the channel layer 611. This increases the facing area of ​​the gate structure 613 and the channel layer 611, thereby enhancing the control capability of the gate structure 613 over the channel layer 611.

[0071] In some embodiments, the gate dielectric layer 612 may also cover only the channel layer 611, or the gate dielectric layer 612 may cover the channel layer 611 and the sidewall of the first dielectric layer 121 exposed by the first via 131.

[0072] Based on the above-described method for fabricating the semiconductor structure 10, this disclosure also provides a semiconductor structure 10. Figure 21 is a schematic diagram of a semiconductor structure 10 according to an embodiment of this disclosure.

[0073] Referring to FIG21, the semiconductor structure 10 includes: a substrate 110 and a stacked structure 120 located on the surface of the substrate 110. The stacked structure 120 includes a first dielectric layer 121 and a second dielectric layer 122 stacked along the vertical direction Z; a through-hole 130 penetrating the stacked structure 120 along the vertical direction Z, the through-hole 130 including a first hole 131 and a second hole 132; a bottom protective layer 311 located at the bottom of the through-hole 130 and a sidewall protective layer 211 surrounding the bottom protective layer 311, the bottom protective layer 311 being in contact with the substrate 110; a transistor structure 610 located in the first hole 131; and a capacitor structure 510 located in the second hole 132, the capacitor structure 510 being electrically connected to the transistor structure 610.

[0074] By providing a bottom protective layer 311 at the bottom of the transistor structure 610 and the capacitor structure 510, and a sidewall protective layer 211 surrounding the bottom protective layer 311, leakage current between the transistor structure 610 and the capacitor structure 510 and the substrate can be effectively reduced, thereby improving the electrical stability of the semiconductor structure. Since the sidewall protective layer 211 of the bottom protective layer 311 is only located on a portion of the surface of the substrate 110 rather than on the entire surface of the substrate 110, it does not impose significant stress on the overall semiconductor structure and can prevent substrate over-etching damage and impurity stripping during the semiconductor structure formation process, thus improving the structural stability of the semiconductor structure.

[0075] In some embodiments, the top surface of the sidewall protective layer 211 is flush with or higher than the top surface of the bottom protective layer 311. The bottom protective layer 311 may be formed by an epitaxial growth process, and the material of the bottom protective layer 311 may include silicon germanium.

[0076] In some embodiments, as shown in FIG8 or FIG11, a substrate recess 110R is formed on the surface of the substrate 110, and a bottom protective layer 311 and a sidewall protective layer 211 are located on the substrate recess 110R.

[0077] In some embodiments, as shown in FIG13, the bottom protective layer 311 includes a monocrystalline silicon layer 311a and a silicon-germanium layer 311b located on the monocrystalline silicon layer 311a. The top surface of the monocrystalline silicon layer 311a is lower than the top surface of the substrate, and the top surface of the silicon-germanium layer 311b is lower than the top surface of the first dielectric layer 121 closest to the substrate 110. The thickness of the monocrystalline silicon layer 311a is less than the thickness of the silicon-germanium layer 311b. For example, the top surface of the bottom protective layer 311 is located at a height between 0.3 and 0.6 of the height of the first dielectric layer 121 closest to the substrate 110, which can ensure protection of the substrate 110 while avoiding spatial impact on the transistor structure 610 and the capacitor structure 510.

[0078] In some embodiments, as shown in FIG3 and FIG21, the via 130 includes a plurality of via groups 130G arranged along the second direction Y, and each via group 130G includes a first hole 131 and a second hole 132 arranged along the first direction X; the transistor structure 610 in each first hole 131 includes a plurality of transistor units 610C spaced apart along the vertical direction Z; the capacitor structure 510 in each second hole 132 includes a plurality of capacitor units 510C spaced apart along the vertical direction Z; the semiconductor structure 10 also includes a bit line structure 412, which extends along the second direction Y, and the plurality of bit line structures 412 are spaced apart along the vertical direction Z, and each bit line structure 412 is electrically connected to the plurality of transistor units 610C located on the same layer.

[0079] In some embodiments, referring to FIG21, the transistor structure 610 includes: a channel layer 611 located on the sidewall of the first hole 131 corresponding to the second dielectric layer 122; a gate dielectric layer 612 covering the channel layer, the sidewall of the first hole 131 corresponding to the second dielectric layer 122, and the top surface of the bottom protective layer 311; and a gate structure 613 extending along the vertical direction Z and filling the first hole 131, wherein the projection of the channel layer 611 in the vertical direction Z forms an annulus surrounding the gate structure 613.

[0080] The two ends of the channel layer 611 along the first direction X are electrically connected to the bit line structure 412 and the capacitor structure 510, respectively. The material of the channel layer 611 can be single-crystal silicon, polycrystalline silicon, germanium, silicon-germanium, and oxide semiconductor materials (e.g., zinc tin oxide (ZnO)). x Sn y O, commonly known as "ZTO"), indium zinc oxide (In x Zn y O, commonly known as "IZO"), zinc oxide (Zn) x O), Indium gallium zinc oxide (In x Ga y Zn z O, commonly known as "IGZO"), indium gallium silicon oxide (In xGa y Si z O, commonly known as "IGSO"), indium tin oxide (In) x Sn y O (commonly known as "ITO") and one or more other similar materials.

[0081] The transistor structure 610 in each first hole 131 includes a plurality of transistor units 610C spaced apart along the vertical direction Z. The plurality of transistor units 610C are respectively located in the layer containing the second dielectric layer 122 in the stacked structure 120. The gate structure 613 extends along the vertical direction Z and penetrates the stacked structure 120. The bottom surface of the gate structure 613 is lower than the top surface of the bottom first dielectric layer 121.

[0082] In some embodiments, referring to FIG21, the capacitor structure 510 includes: a lower electrode layer 511 located on the sidewall of the second hole 132 corresponding to the second dielectric layer 122, the projection of the lower electrode layer 511 in the vertical direction Z being annular; a capacitor dielectric layer 512 covering the bottom protective layer 311 at the bottom of the second hole 132; and an upper electrode layer 513 covering the capacitor dielectric layer 512 and filling the second hole 132.

[0083] Each second hole 132 contains a capacitor structure 510 including a plurality of capacitor units 510C spaced apart along the vertical direction Z. The plurality of capacitor units 510C are located in the layer where the second dielectric layer 122 is located in the stacked structure 120. The transistor unit 610C and the capacitor unit 510C are electrically connected in a one-to-one correspondence to form a 1T1C horizontal memory cell.

[0084] In some embodiments, as shown in FIG. 19, the projection of the lower electrode layer 511 onto the substrate 110 is annular. The lower electrode layer 511 may include an upper parallel portion 511a, a lower parallel portion 511b, and a vertical portion 511c connecting the upper parallel portion 511a and the lower parallel portion 511b. The projections of the upper parallel portion 511a and the lower parallel portion 511b onto the substrate 110 are annular and coincident. The vertical portion 511c connects the outer edges of the upper parallel portion 511a and the lower parallel portion 511b. The thickness of the upper parallel portion 511a and the lower parallel portion 511b in the vertical direction Z may be equal to the thickness of the vertical portion 511c in the horizontal direction. The vertical portion 511c contacts the channel layer 611 located in the first hole 131.

[0085] In some embodiments, a first upper electrode layer 513a conformally covers the capacitor dielectric layer 512, and a second upper electrode layer 513b covers the first upper electrode layer 513a and fills the second hole 132. The second upper electrode layer 513b may have a columnar portion extending in the vertical direction Z and a protrusion protruding horizontally along the sidewall of the columnar portion. The columnar portion penetrates the stacked structure 120, and the protrusion is embedded in the capacitor slot 510T. The bottom surface of the second upper electrode layer 513b is lower than the top surface of the bottommost first dielectric layer 121.

[0086] In some embodiments, the semiconductor structure 10 includes a memory, which may be a dynamic random access memory, such as a three-dimensional memory, 3D DRAM, or a memory known in the art, such as a phase-change memory or a ferroelectric memory.

[0087] It should be noted that the active pillar in the embodiments of this disclosure can be located in the array region and / or the peripheral region. When the active pillar is located in the array region, the transistor and memory structure including the active pillar together constitute the memory cell. When the active pillar is located in the peripheral region, the transistor including the active pillar and electronic components such as capacitors and resistors constitute the peripheral circuit.

[0088] The various semiconductor structures illustrated in this specific embodiment can be used in electronic devices with storage functions. These electronic devices can be terminal devices, such as mobile phones, tablets, and smart bracelets, or personal computers (PCs), servers, workstations, etc. The storage function in these electronic devices can be implemented using the following types of memory: Dynamic Random Access Memory (DRAM), Ferroelectric Random Access Memory (FRAM), Phase Change Memory (PCM), Magnetic Random Access Memory (MRAM), or Resistive Random Access Memory (RRAM).

[0089] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A method for fabricating a semiconductor structure, comprising: A substrate (110) is provided and a stacked structure (120) is formed on the substrate (110), the stacked structure (120) including a first dielectric layer (121) and a second dielectric layer (122) stacked in a vertical direction (Z); A through-hole (130) is formed through the stacked structure (120) along the vertical direction (Z). The through-hole (130) includes a first hole (131) and a second hole (132). The through-hole (130) exposes a portion of the surface of the substrate (110). The bottom surface of the through-hole (130) is flush with or lower than the top surface of the substrate (110). A sidewall protective layer (211) is formed on the inner wall of the through hole (130); A bottom protective layer (311) is formed on a portion of the substrate (110) exposed by the through hole (130); An insulating layer (320) is filled into the through hole (130); Remove the isolation layer (320) and part of the sidewall protective layer (211) inside the first hole (131), and form a transistor structure (610) inside the first hole (131); Remove the isolation layer (320) and part of the sidewall protective layer (211) inside the second hole (132), and form a capacitor structure (510) inside the second hole (132), the capacitor structure (510) being electrically connected to the transistor structure (610).

2. The preparation method according to claim 1, wherein, The stacked structure (120) includes a first dielectric layer (121) and a second dielectric layer (122) alternately stacked along the vertical direction (Z). The bottom layer of the stacked structure (120) is the first dielectric layer (121), and the top layer of the stacked structure (120) is the second dielectric layer (122).

3. The preparation method according to claim 1, wherein, Forming a through hole (130) penetrating the stacked structure (120) along the vertical direction (Z) includes: The stacked structure (120) is partially removed using a dry etching process to simultaneously form the first hole (131) and the second hole (132).

4. The preparation method according to claim 1, wherein, When forming a through hole (130) penetrating the stacked structure (120) along the vertical direction (Z), the following is included: A portion of the substrate (110) is removed to form a substrate recess (110R) on the surface of the substrate (110), wherein the bottom surface of the via (130) is lower than the top surface of the substrate (110).

5. The preparation method according to claim 1, wherein, The bottom surface of the through-hole (130) is lower than the top surface of the substrate (110), and the formation of a bottom protective layer (311) on the portion of the substrate (110) exposed by the through-hole (130) includes: A single-crystal silicon layer (311a) is formed on a portion of the substrate (110) exposed by the via (130) using a first epitaxial growth process, wherein the top surface of the single-crystal silicon layer (311a) is lower than the top surface of the substrate (110). A silicon-germanium layer (311b) is formed on the single-crystal silicon layer (311a) using a second epitaxial growth process, wherein the thickness of the single-crystal silicon layer (311a) is less than the thickness of the silicon-germanium layer (311b).

6. The preparation method according to claim 1, wherein, The formation of the transistor structure (610) within the first hole (131) includes: A channel layer (611) is formed on the sidewall of the first hole (131) corresponding to the second dielectric layer (122); A gate dielectric layer (612) is formed covering the channel layer (611), and the gate dielectric layer (612) covers the top surface of the bottom protective layer (311) at the bottom of the first hole (131); A gate structure (613) is formed to fill the first hole (131), and the projection of the channel layer (611) in the vertical direction (Z) is annular around the gate structure (613).

7. The preparation method according to claim 1, wherein, The formation of the capacitor structure (510) within the second hole (132) includes: A portion of the second dielectric layer (122) is removed laterally along the second hole (132) to form a capacitor groove (510T); A lower electrode layer (511) is formed covering the inner wall of the capacitor tank (510T); A capacitor dielectric layer (512) is formed covering the lower electrode layer (511), and the capacitor dielectric layer (512) covers the bottom protective layer (311) at the bottom of the second hole (132); An upper electrode layer (513) is formed that covers the capacitor dielectric layer (512) and fills the second hole (132).

8. The preparation method according to claim 1, wherein, The via (130) includes a plurality of via groups (130G) arranged along a second direction (Y), each via group (130G) including a first hole (131) and a second hole (132) arranged along a first direction (X); the transistor structure (610) in each first hole (131) includes a plurality of transistor units (610C) spaced apart along the vertical direction (Z); the capacitor structure (510) in each second hole (132) includes a plurality of capacitor units (510C) spaced apart along the vertical direction (Z); the method further includes: A linear groove (411T) is formed on one side of the through hole (130) along the first direction (X); A portion of the second dielectric layer (122) is removed laterally along the linear groove (411T) to form a bit groove (412T); A bit line structure (412) is formed to fill the bit line slot (412T). The bit line structure (412) extends along the second direction (Y), and a plurality of the bit line structures (412) are arranged at intervals along the vertical direction (Z). Each bit line structure (412) is electrically connected to a plurality of transistor units (610C) located on the same layer.

9. The preparation method according to claim 1, wherein, The spacing between the first hole (131) and the second hole (132) in a through-hole group (130G) is less than the spacing between two adjacent through-hole groups (130G).

10. A semiconductor structure comprising: The substrate (110) and the stacked structure (120) located on the surface of the substrate (110), the stacked structure (120) including a first dielectric layer (121) and a second dielectric layer (122) stacked along the vertical direction (Z); A through hole (130) extending through the stacked structure (120) along the vertical direction (Z), the through hole (130) including a first hole (131) and a second hole (132); A bottom protective layer (311) located at the bottom of the through hole (130) and a sidewall protective layer (211) surrounding the bottom protective layer (311), the bottom protective layer (311) being in contact with the substrate (110); A transistor structure (610) located in the first hole (131); A capacitor structure (510) is located in the second hole (132), and the capacitor structure (510) is electrically connected to the transistor structure (610).

11. The semiconductor structure according to claim 10, wherein, The through hole (130) includes a plurality of through hole groups (130G) arranged along the second direction (Y), and each through hole group (130G) includes a first hole (131) and a second hole (132) arranged along the first direction (X); The transistor structure (610) in each of the first holes (131) includes a plurality of transistor units (610C) spaced apart along the vertical direction (Z); Each of the second holes (132) contains a capacitor structure (510) comprising a plurality of capacitor units (510C) spaced apart along the vertical direction (Z); The semiconductor structure further includes a bit line structure (412) extending along a second direction (Y), and a plurality of bit line structures (412) are arranged at intervals along the vertical direction (Z), each bit line structure (412) being electrically connected to a plurality of transistor units (610C) located on the same layer.

12. The semiconductor structure according to claim 11, wherein, The transistor structure (610) includes: The channel layer (611) is located on the sidewall of the first hole (131) corresponding to the second dielectric layer (122); A gate dielectric layer (612) covers the channel layer (611), the first via (131) corresponds to the sidewall of the second dielectric layer (122), and the top surface of the bottom protective layer (311); A gate structure (613) extends along the vertical direction (Z) and fills the first hole (131), and the projection of the channel layer (611) in the vertical direction (Z) is annular around the gate structure (613).

13. The semiconductor structure according to claim 10, wherein, The capacitor structure (510) includes: The lower electrode layer (511) is located on the sidewall of the second hole (132) corresponding to the second dielectric layer (122), and the projection of the lower electrode layer (511) in the vertical direction (Z) is annular; A capacitor dielectric layer (512) covers the bottom protective layer (311) at the bottom of the second hole (132); The upper electrode layer (513) covers the capacitor dielectric layer (512) and fills the second hole (132).

14. The semiconductor structure according to claim 10, wherein, The bottom protective layer (311) includes a monocrystalline silicon layer (311a) and a silicon-germanium layer (311b) located on the monocrystalline silicon layer (311a). The top surface of the monocrystalline silicon layer (311a) is lower than the top surface of the substrate (110), and the top surface of the silicon-germanium layer (311b) is lower than the top surface of the first dielectric layer (121) located closest to the substrate (110). The thickness of the monocrystalline silicon layer (311a) is less than the thickness of the silicon-germanium layer (311b).

15. The semiconductor structure according to claim 14, wherein, The thickness of the single-crystal silicon layer (311a) ranges from 1 nm to 3 nm, and the thickness of the silicon-germanium layer (311b) ranges from 3 nm to 6 nm.

16. The semiconductor structure according to claim 13, wherein, The lower electrode layer (511) includes an upper parallel portion (511a), a lower parallel portion (511b), and a vertical portion (511c) connecting the upper parallel portion (511a) and the lower parallel portion (511b), the vertical portion (511c) being in contact with the transistor structure (610) located in the first hole (131).

17. The semiconductor structure according to claim 10, wherein, A substrate recess (110R) is formed on the surface of the substrate (110), and the bottom protective layer (311) and the sidewall protective layer (211) are located on the substrate recess (110R).

18. The semiconductor structure according to claim 12, wherein, The size of the first portion of the gate structure (613) surrounded by the channel layer (611) is smaller than the size of the second portion of the gate structure (613) between the first portions.

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