Ferroelectric memory, three-dimensional ferroelectric memory and three-dimensional ferroelectric storage apparatus

Abstract

A ferroelectric memory, a three-dimensional ferroelectric memory and a three-dimensional ferroelectric memory apparatus. The ferroelectric memory comprises a first word line (103), a first bit line (101), a first transistor (102) and a first ferroelectric capacitor pair (106), wherein the first ferroelectric capacitor pair (106) comprises a first ferroelectric capacitor (104) and a second ferroelectric capacitor (105), and the first ferroelectric capacitor (104) and the second ferroelectric capacitor (105) extend in a first direction; and a control terminal of the first transistor (102) is connected to the first word line (103), a second terminal of the first transistor (102) is connected to the first bit line (101), and a first terminal of the first transistor (102) is connected to an upper electrode plate of the first ferroelectric capacitor pair (106). The first ferroelectric capacitor pair (106) is stacked on the first transistor (102), which can improve the storage density and increase the storage capacity of the ferroelectric memory; the first ferroelectric capacitor (104) and the second ferroelectric capacitor (105) extend in the first direction, and the storage capacities of the ferroelectric capacitors can be adjusted by adjusting the lengths in the first direction, which solves the problem of a sensing margin; moreover, a sufficient footprint is provided for the first transistor (102), which is conducive to optimizing the drive capability of the first transistor (102).

Description

Ferroelectric memory, three-dimensional ferroelectric memory and three-dimensional ferroelectric storage device

[0001] Cross-referencing

[0002] This disclosure claims priority to Chinese Patent Application No. 202411183485.2, filed on August 26, 2024, entitled "Ferroelectric memory, three-dimensional ferroelectric memory and three-dimensional ferroelectric memory device", the entire contents of which are incorporated herein by reference. Technical Field

[0003] This application relates to the field of integrated circuit technology, and in particular to a ferroelectric memory, a three-dimensional ferroelectric memory, and a three-dimensional ferroelectric storage device containing the three-dimensional ferroelectric memory. Background Technology

[0004] The development of information technology has placed demands on memory for low latency and high capacity. Low latency helps improve data processing speed, while high capacity helps increase storage density and reduce memory manufacturing costs.

[0005] Ferroelectric memories are a novel type of memory that has attracted widespread attention due to their non-volatile data storage and high access speed. However, most current ferroelectric memories are planar in structure. Due to the limitations of device physical size and characteristics, the scaling speed of planar ferroelectric memories is gradually slowing down, making it difficult to further increase storage density. Therefore, improving the storage density and capacity of ferroelectric memories is currently a major challenge in their development. Summary of the Invention

[0006] Based on this, embodiments of this application provide a ferroelectric memory, a three-dimensional ferroelectric memory, and a three-dimensional ferroelectric storage device containing the three-dimensional ferroelectric memory, which has a high storage density.

[0007] In a first aspect, according to some embodiments, this application provides a ferroelectric memory, characterized in that it comprises:

[0008] First word line, first bit line, first transistor, first ferroelectric capacitor pair;

[0009] The first ferroelectric capacitor pair includes a first ferroelectric capacitor and a second ferroelectric capacitor, which extend in a first direction.

[0010] The control terminal of the first transistor is connected to the first word line, the second terminal of the first transistor is connected to the first bit line, and the first terminal of the first transistor is connected to the upper electrode plate of the first ferroelectric capacitor pair.

[0011] In some embodiments, the upper electrode plate includes a first upper electrode plate and a second upper electrode plate;

[0012] The first lower electrode of the first ferroelectric capacitor extends along a first direction, a first ferroelectric dielectric layer is disposed on the surface of the first lower electrode, and a first upper electrode plate is disposed on the surface of the first ferroelectric dielectric layer.

[0013] The second lower electrode of the second ferroelectric capacitor extends along the first direction, the second ferroelectric dielectric layer is disposed on the surface of the second lower electrode, and the second upper electrode plate is disposed on the surface of the second ferroelectric dielectric layer.

[0014] In some embodiments, the first upper electrode plate is in contact with the second upper electrode plate, and the first end of the first transistor is in contact with and connected to the first upper electrode plate and the second upper electrode plate.

[0015] In some embodiments, the first upper electrode plate and the second upper electrode plate are not in contact, and the first terminal of the first transistor is in contact with the first upper electrode plate and the second upper electrode plate respectively through a connection portion.

[0016] In some embodiments, the ferroelectric memory further includes a second word line, a second bit line, and a second transistor;

[0017] The control terminal of the second transistor is connected to the second word line, and the second terminal of the second transistor is connected to the second bit line.

[0018] The first upper electrode plate and the second upper electrode plate are not in contact. The first terminal of the first transistor is in contact with the first upper electrode plate. The first terminal of the second transistor is in contact with the second upper electrode plate.

[0019] In some embodiments, the upper electrode plate further includes a third upper electrode plate;

[0020] The third lower electrode of the first ferroelectric capacitor extends along the first direction, and the fourth lower electrode of the second ferroelectric capacitor extends along the first direction. The third lower electrode and the fourth lower electrode are connected by an insulating part.

[0021] A third ferroelectric dielectric layer is disposed on the surfaces of the third lower electrode and the fourth lower electrode, and a third upper electrode plate is disposed on the surface of the third ferroelectric dielectric layer.

[0022] In some embodiments, the ferroelectric memory further includes a first wire connected to the lower electrode of the first ferroelectric capacitor;

[0023] The second wire is connected to the lower electrode of the second ferroelectric capacitor.

[0024] Secondly, according to some embodiments, this application also provides a three-dimensional ferroelectric memory, characterized in that it includes:

[0025] Substrate;

[0026] A plurality of first bit lines, a plurality of first word lines, and a plurality of first transistors are located on the substrate;

[0027] The plurality of first bit lines extend along a first direction and are arranged along a second direction; the plurality of first word lines extend along a second direction and are arranged along a first direction; the plurality of transistors are arranged along a first direction and a second direction; the first direction and the second direction intersect.

[0028] Multiple first ferroelectric capacitor pairs, each first ferroelectric capacitor pair including a first ferroelectric capacitor and a second ferroelectric capacitor, the first ferroelectric capacitor and the second ferroelectric capacitor extending along a first direction and arranged along a third direction, the first direction, the second direction and the third direction intersecting each other;

[0029] The control terminal of the first transistor is connected to the first word line, the second terminal of the first transistor is connected to the first bit line, and the first terminal of the first transistor is connected to the upper electrode plate of the first ferroelectric capacitor pair.

[0030] In some embodiments, the upper electrode plate includes a first upper electrode plate and a second upper electrode plate;

[0031] The first lower electrode of the first ferroelectric capacitor extends along a first direction, a first ferroelectric dielectric layer is disposed on the surface of the first lower electrode, and a first upper electrode plate is disposed on the surface of the first ferroelectric dielectric layer.

[0032] The second lower electrode of the second ferroelectric capacitor extends along the first direction, the second ferroelectric dielectric layer is disposed on the surface of the second lower electrode, and the second upper electrode plate is disposed on the surface of the second ferroelectric dielectric layer.

[0033] In some embodiments, the upper electrode plate further includes a third upper electrode plate;

[0034] The first upper electrode plate is in contact with the second upper electrode plate, and the first end of the first transistor is in contact with and connected to the first upper electrode plate and the second upper electrode plate.

[0035] In some embodiments, the first upper electrode plate and the second upper electrode plate are not in contact, and the first terminal of the first transistor is in contact with the first upper electrode plate and the second upper electrode plate respectively through a connection portion.

[0036] In some embodiments, the three-dimensional ferroelectric memory further includes a second word line, a second bit line, and a second transistor;

[0037] The control terminal of the second transistor is connected to the second word line, and the second terminal of the second transistor is connected to the second bit line.

[0038] The first upper electrode plate and the second upper electrode plate are not in contact. The first terminal of the first transistor is in contact with the first upper electrode plate. The first terminal of the second transistor is in contact with the second upper electrode plate.

[0039] In some embodiments, the third lower electrode of the first ferroelectric capacitor extends along a first direction, and the fourth lower electrode of the second ferroelectric capacitor extends along the first direction, wherein the third lower electrode and the fourth lower electrode are connected by an insulating portion.

[0040] A third ferroelectric dielectric layer is disposed on the surfaces of the third lower electrode and the fourth lower electrode, and a third upper electrode plate is disposed on the surface of the third ferroelectric dielectric layer.

[0041] In some embodiments, the three-dimensional ferroelectric memory further includes a plurality of first wires, the plurality of first wires being respectively connected to the lower electrode of the first ferroelectric capacitor;

[0042] A plurality of second wires are provided, each of which is connected to the lower electrode of the second ferroelectric capacitor.

[0043] Thirdly, according to some embodiments, this application also provides a three-dimensional ferroelectric storage device, characterized in that it includes:

[0044] A three-dimensional ferroelectric memory, wherein the three-dimensional ferroelectric memory is the three-dimensional ferroelectric memory provided in the second aspect;

[0045] Peripheral device wafer, which is coupled to the three-dimensional ferroelectric memory.

[0046] The semiconductor structure and its fabrication method provided in this application have at least the following beneficial effects:

[0047] The ferroelectric memory, three-dimensional ferroelectric memory, and three-dimensional ferroelectric memory device provided in this application have a first ferroelectric capacitor pair stacked on a transistor, which can increase the storage density and improve the storage capacity of the ferroelectric memory. Extending in a first direction, the storage capacity of the ferroelectric capacitor can be adjusted by adjusting the length along the first direction, solving the sensing margin problem. At the same time, it provides sufficient floor space for the first transistor, which helps to optimize the driving capability of the first transistor. Attached Figure Description

[0048] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0049] Figure 1 is a schematic diagram of a ferroelectric memory provided in an embodiment of this application;

[0050] Figure 2 is a schematic diagram of a ferroelectric memory provided in an embodiment of this application;

[0051] Figure 3 is a schematic diagram of a ferroelectric memory provided in an embodiment of this application;

[0052] Figure 4 is a schematic diagram of a ferroelectric memory provided in an embodiment of this application;

[0053] Figure 5 is a schematic diagram of another ferroelectric memory provided in an embodiment of this application;

[0054] Figure 6 is a schematic diagram of another ferroelectric memory provided in an embodiment of this application;

[0055] Figure 7 is a schematic diagram of another ferroelectric memory provided in an embodiment of this application;

[0056] Figure 8 is a schematic diagram of another ferroelectric memory provided in an embodiment of this application;

[0057] Figure 9 is a schematic diagram of a three-dimensional ferroelectric memory provided in an embodiment of this application;

[0058] Figure 10 is a schematic diagram of a three-dimensional ferroelectric memory provided in an embodiment of this application;

[0059] Figure 11 is a schematic diagram of a three-dimensional ferroelectric memory provided in an embodiment of this application;

[0060] Figure 12 is a schematic diagram of a three-dimensional ferroelectric memory provided in an embodiment of this application;

[0061] Figure 13 is a schematic diagram of another three-dimensional ferroelectric memory provided in an embodiment of this application;

[0062] Figure 14 is a schematic diagram of the structure of a three-dimensional ferroelectric memory device provided in an embodiment of this application;

[0063] Explanation of reference numerals in the attached figures: 100: Substrate; 101: First bit line (second bit line); 102: First transistor; 103: First word line; 104: First ferroelectric capacitor; 105: Second ferroelectric capacitor; 106: First ferroelectric capacitor pair; 107: First conductor; 108: Second conductor; 109: Connector; 110: Insulating portion; 202: Second transistor; 203: Second word line; 1041: First lower electrode; 1042: First ferroelectric dielectric layer; 1043: First upper electrode plate; 1044: Third lower electrode; 1051: Second lower electrode; 1052: Second ferroelectric dielectric layer; 1053: Second upper electrode plate; 1054: Fourth lower electrode; 1062: Third ferroelectric dielectric layer; 1063: Third upper electrode plate; 300: Peripheral device wafer. Detailed Implementation

[0064] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate preferred embodiments of the application. However, this application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0065] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0066] It should be understood that when an element or layer is referred to as "on," "adjacent to," or "connected to," it may be directly on, adjacent to, or connected to other elements or layers, or there may be intervening elements or layers. It should be understood that although the terms first, second, etc., may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of this application, the first element, component, region, layer, doping type, or portion discussed below may be referred to as a second element, component, region, layer, or portion; for example, a first doped region may be referred to as a second doped region, and similarly, a second doped region may be referred to as a first doped region; the first doped region and the second doped region are different doped regions.

[0067] Spatial relation terms such as “on top of” can be used herein to describe the relationship of one element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientation shown in the figures, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figures is flipped, the element or feature described as “on top of” will be oriented “below” other elements or features. Therefore, the exemplary term “on top of” can include both upper and lower orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0068] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that when the terms “comprise” and / or “comprising” are used in this specification, the presence of the stated feature, integer, step, operation, element, and / or part is established, but the presence or addition of one or more other features, integers, steps, operations, elements, parts, and / or groups is not excluded. Meanwhile, when used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0069] Embodiments of the invention are described herein with reference to cross-sectional views that serve as schematic diagrams of preferred embodiments (and intermediate structures) of this application, thus allowing for the anticipation of variations in the shown shapes due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of this application should not be limited to the specific shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing techniques. The regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of regions of the device, nor do they limit the scope of this application.

[0070] Figure 1 is a schematic diagram of a ferroelectric memory provided in an embodiment of this application. In some embodiments, the ferroelectric memory includes a first word line 103, a first bit line 101, a first transistor 102, and a first ferroelectric capacitor pair 106. The first ferroelectric capacitor pair 106 includes a first ferroelectric capacitor 104 and a second ferroelectric capacitor 105, which extend along a first direction. The first transistor 102 includes a first terminal, a second terminal, and a control terminal. The control terminal of the first transistor 102 is connected to the first word line 103, the second terminal of the first transistor 102 is connected to the first bit line, and the first terminal of the first transistor 102 is connected to the upper electrode plate of the first ferroelectric capacitor pair. The first ferroelectric capacitor 104 and the second ferroelectric capacitor 105 extend along the first direction, and the storage capacity of the ferroelectric capacitors can be adjusted by adjusting their length along the first direction, solving the perception margin problem and providing sufficient floor space for the first transistor 102, which helps to optimize the driving capability of the first transistor 102.

[0071] In some embodiments of this application, the first transistor in the ferroelectric memory can be an NMOS (N-channel metal oxide semiconductor) or a PMOS (P-channel metal oxide semiconductor). For example, in the memory cell shown in FIG1, the first transistor is an NMOS transistor. In this case, when a high voltage is applied to the first word line, the first transistor is turned on, and when a low voltage is applied to the first word line, the first transistor is turned off. In other embodiments, the first transistor can be a gate all around, a triple gate, a double gate, or a vertical single gate. It can also be a planar transistor, a recessed transistor, or a buried transistor. The channel material of the first transistor 102 can be one or more of semiconductor materials such as silicon (Si), polycrystalline silicon (p-Si), amorphous silicon (a-Si), indium gallium zinc oxide (In-Ga-Zn-O, IGZO), zinc oxide (ZnO), ITO, titanium dioxide (TiO2), and molybdenum disulfide (MoS2). This application does not impose specific limitations on this. In this embodiment, only the first transistor 102 is a vertical dual-gate transistor as an example for illustration.

[0072] Referring again to Figure 1, in some embodiments, the control terminal of the first transistor 102 is called the gate, and one of the drain or source terminals of the MOS transistor is called the first terminal, and the corresponding other terminal is called the second terminal. For example, the first terminal of the first transistor can be the source and the second terminal can be the drain; or the first terminal can be the drain and the second terminal can be the source. The control terminal of the first transistor 102 is connected to the first word line 103, and the second terminal of the first transistor 102 is connected to the first bit line 101. The materials of the first bit line 101 and the first word line 103 are materials with conductive properties, such as at least one of the following materials: titanium nitride (TiN), tungsten (W), nickel (Ni), platinum (Pt), titanium (Ti), tungsten nitride (WN), ruthenium (Ru), and ruthenium oxide (RuO). x ), iridium (Ir), iridium oxide (IrO) x Materials used include tantalum nitride (TaN), cobalt (Co), aluminum (Al), copper (Cu), polycrystalline silicon (Si), and metal silicides. The materials of the first letter line 103 and the first digit line 101 can be the same or different.

[0073] Referring again to FIG1, in some embodiments, the ferroelectric memory further includes a first ferroelectric capacitor pair 106, which includes a first ferroelectric capacitor 104 and a second ferroelectric capacitor 105. The first ferroelectric capacitor 104 and the second ferroelectric capacitor 105 include a lower electrode, a ferroelectric dielectric layer, and an upper electrode plate. The first lower electrode 1041 of the first ferroelectric capacitor extends along a first direction. The first ferroelectric dielectric layer 1042 is disposed on the surface of the first lower electrode 1041. The first upper electrode plate 1043 is disposed on the surface of the first ferroelectric dielectric layer 1042. The first ferroelectric dielectric layer 1042 is located between the first lower electrode 1041 and the first upper electrode plate 1043, thereby insulating the first lower electrode 1041 and the first upper electrode plate 1043. The second lower electrode 1051 of the second ferroelectric capacitor 105 extends along the first direction, the second ferroelectric dielectric layer 1052 is disposed on the surface of the second lower electrode 1051, the second upper electrode plate 1503 is disposed on the surface of the second ferroelectric dielectric layer 1052, the second ferroelectric dielectric layer 1052 is located between the second lower electrode 1051 and the second upper electrode plate 1053, so that the second lower electrode 1051 and the second upper electrode plate 1053 are insulated from each other. The materials of the first ferroelectric dielectric layer 1042 and the second ferroelectric dielectric layer 1052 may include perovskite structure materials such as a mixture of lead zirconate (PbZrO3) and lead titanate (PbTiO3), Pb(Zr,Ti)O3, and barium titanate (BaTiO3), or HfO2-based ferroelectric materials doped with at least one element selected from zirconium (Zr), silicon (Si), lanthanum (La), yttrium (Y), strontium (Sr), gadolinium (Gd), and aluminum (Al). This application does not limit the materials and manufacturing processes of the ferroelectric film layers.

[0074] Referring again to Figure 1, in some embodiments, the materials of the first lower electrode 1041, the second lower electrode 1051, the first upper electrode plate 1043, and the second upper electrode plate 1053 are conductive materials, such as at least one of the following: titanium nitride (TiN), tungsten (W), nickel (Ni), platinum (Pt), titanium (Ti), tungsten nitride (WN), ruthenium (Ru), and ruthenium oxide (RuO). x ), iridium (Ir), iridium oxide (IrO) xMaterials used include tantalum nitride (TaN), cobalt (Co), aluminum (Al), copper (Cu), polycrystalline silicon (Si), and metal silicides. The materials of the first lower electrode 1041, the second lower electrode 1051, the first upper electrode plate 1043, and the second upper electrode plate 1053 can be the same or different. The first upper electrode plate 1043 is in contact with the second upper electrode plate 1053, and the first end of the first transistor 102 is connected to the first upper electrode plate 1043 and the second upper electrode plate 1053. Similarly, referring to Figure 5, there can be multiple first ferroelectric capacitor pairs 106. Each first ferroelectric capacitor pair 106 is stacked along a third direction (away from the transistor), and the first upper electrode plate 1043 and the second upper electrode plate 1053 of each first ferroelectric capacitor pair 106 are in contact, connected as a whole, and connected to the first end of the first transistor 102. Stacking multiple first ferroelectric capacitor pairs 106 along a third direction and connecting them together to the first transistor 102 can reduce the number of transistors and increase storage density. In addition, each of the first ferroelectric capacitors is in contact with the first upper electrode plate 1043 and the second upper electrode plate 1053 of the first ferroelectric capacitor, which can make the upper electrode plate integrally formed, reducing the difficulty of the manufacturing process, reducing the manufacturing time, improving production efficiency and saving production costs.

[0075] Referring again to Figure 1, in some embodiments, the ferroelectric memory further includes a first wire 107 and a second wire 108. The first wire 107 is connected to a first lower electrode 1041, and the second wire 108 is connected to a second lower electrode 1051. The materials of the first wire 107 and the second wire 108 are conductive materials, such as at least one of the following: titanium nitride (TiN), tungsten (W), nickel (Ni), platinum (Pt), titanium (Ti), tungsten nitride (WN), ruthenium (Ru), and ruthenium oxide (RuO). x ), iridium (Ir), iridium oxide (IrO) x Materials used include tantalum nitride (TaN), cobalt (Co), aluminum (Al), copper (Cu), polycrystalline silicon (Si), and metal silicides. The materials of the first conductor 107 and the second conductor 108 can be the same or different.

[0076] Figure 2 is a schematic diagram of a ferroelectric memory provided in an embodiment of this application. In some embodiments, the first ferroelectric capacitor pair 106 includes a first ferroelectric capacitor 104 and a second ferroelectric capacitor 105. The first ferroelectric capacitor 104 and the second ferroelectric capacitor 105 include a lower electrode, a ferroelectric dielectric layer, and an upper electrode plate. The first lower electrode 1041 of the first ferroelectric capacitor extends along a first direction. The first ferroelectric dielectric layer 1042 is disposed on the surface of the first lower electrode 1041. The first upper electrode plate 1043 is disposed on the surface of the first ferroelectric dielectric layer 1042. The first ferroelectric dielectric layer 1042 is located between the first lower electrode 1041 and the first upper electrode plate 1043, thereby insulating the first lower electrode 1041 and the first upper electrode plate 1043. The second lower electrode 1051 of the second ferroelectric capacitor 105 extends along the first direction, the second ferroelectric dielectric layer 1052 is disposed on the surface of the second lower electrode 1051, the second upper electrode plate 1503 is disposed on the surface of the second ferroelectric dielectric layer 1052, the second ferroelectric dielectric layer 1052 is located between the second lower electrode 1051 and the second upper electrode plate 1053, so that the second lower electrode 1051 and the second upper electrode plate 1053 are insulated from each other. The first upper electrode plate 1043 and the second upper electrode plate 1053 are not in direct contact. A connecting portion 109 is provided on the first end of the first transistor. The connecting portion 109 is connected to the first upper electrode plate 1043 and the second electrode plate 1053 respectively. The cross-sectional shape of the connecting portion can be elliptical, rectangular, bench-shaped, or other shapes that allow the first upper electrode plate 1043 and the second upper electrode plate 1053, which are not connected to each other, to connect to the first transistor 102. The material of the connecting portion 109 is a material with conductive properties, such as at least one of the following materials: titanium nitride (TiN), tungsten (W), nickel (Ni), platinum (Pt), titanium (Ti), tungsten nitride (WN), ruthenium (Ru), and ruthenium oxide (RuO). x ), iridium (Ir), iridium oxide (IrO) x ), tantalum nitride (TaN), cobalt (Co), aluminum (Al), copper (Cu), polycrystalline silicon (Si), metal silicides, etc.

[0077] Referring again to Figure 2, in some embodiments, the first upper electrode plate 1043 and the second upper electrode plate 1053 do not contact each other, but are connected to the first transistor 102 via the connecting portion 109. This reduces crosstalk between the first capacitor 104 and the second capacitor 105, improving the performance of the ferroelectric memory. Similarly, referring to Figure 6, there can be multiple first ferroelectric capacitor pairs 106. Each first ferroelectric capacitor pair 106 is stacked along a third direction. The first upper electrode plate 1043 and the second upper electrode plate 1053 of each first ferroelectric capacitor pair 106 do not contact each other, but multiple first upper electrode plates 1043 are stacked together and connected to the first end of the first transistor 102 via the connecting portion 109. Multiple second upper electrode plates 1053 are stacked together and connected to the first end of the first transistor 102. The stacking of multiple first ferroelectric capacitor pairs 106 along a third direction and their common connection to the first transistor 102 can reduce the number of transistors and increase the storage density. Furthermore, each of the first ferroelectric capacitors does not contact the first upper electrode plate 1043 and the second upper electrode plate 1053 of the first ferroelectric capacitor 106, and can be prepared separately, which increases the process preparation window, reduces the difficulty of the preparation process, and improves production efficiency.

[0078] Figure 3 is a schematic diagram of a ferroelectric memory provided in an embodiment of this application. In some embodiments, the ferroelectric memory further includes a second transistor 202, a second word line 203, and a second bit line 101 (the second bit line and the first bit line can be shared or separated). The control terminal of the second transistor 202 is connected to the second word line 203, the second terminal of the second transistor 202 is connected to the second bit line 101, and the first terminal of the second transistor 202 and the first terminal of the first transistor 102 are respectively connected to the upper electrode plate of the ferroelectric capacitor. They are identical and have the same function, and will not be described in detail here. In some embodiments, the first ferroelectric capacitor pair 106 includes a first ferroelectric capacitor 104 and a second ferroelectric capacitor 105. The first ferroelectric capacitor 104 and the second ferroelectric capacitor 105 include a lower electrode, a ferroelectric dielectric layer, and an upper electrode plate. The first lower electrode 1041 of the first ferroelectric capacitor extends along a first direction. The first ferroelectric dielectric layer 1042 is disposed on the surface of the first lower electrode 1041. The first upper electrode plate 1043 is disposed on the surface of the first ferroelectric dielectric layer 1042. The first ferroelectric dielectric layer 1042 is located between the first lower electrode 1041 and the first upper electrode plate 1043, thereby insulating the first lower electrode 1041 and the first upper electrode plate 1043. The second lower electrode 1051 of the second ferroelectric capacitor 105 extends along the first direction, the second ferroelectric dielectric layer 1052 is disposed on the surface of the second lower electrode 1051, the second upper electrode plate 1503 is disposed on the surface of the second ferroelectric dielectric layer 1052, the second ferroelectric dielectric layer 1052 is located between the second lower electrode 1051 and the second upper electrode plate 1053, so that the second lower electrode 1051 and the second upper electrode plate 1053 are insulated from each other.

[0079] Referring again to Figure 3, in some embodiments, the first upper electrode plate 1043 and the second upper electrode 1053 are not in contact. The first upper electrode 1043 is connected to the first end of the first transistor 102, and the second upper electrode plate 1053 is connected to the second end of the second transistor 202. The first bit line 101, the first transistor 102, the first word line 103, and the first capacitor 104 form a basic ferroelectric memory cell structure. The second bit line 101, the second transistor 202, the second word line 203, and the second capacitor 105 form a basic ferroelectric memory cell structure. Each basic ferroelectric memory cell structure can be controlled independently, which can reduce mutual crosstalk. Similarly, referring to Figure 7, there can be multiple first ferroelectric capacitor pairs 106. Each first ferroelectric capacitor pair 106 is stacked along a third direction. The first upper electrode plate 1043 and the second upper electrode plate 1053 of each first ferroelectric capacitor pair 106 do not contact each other. However, multiple first upper electrode plates 1043 are stacked together and connected to the first terminal of the first transistor 102, and multiple second upper electrode plates 1053 are stacked together and connected to the first terminal of the second transistor 202. The compact stacking of multiple first ferroelectric capacitor pairs 106 along a third direction can reduce the number of transistors and increase storage density. In addition, the first ferroelectric capacitor 104 and the second ferroelectric capacitor 105 of each first ferroelectric capacitor pair 106 are individually connected to the first transistor 102 and the second transistor 202, respectively, forming an individual basic memory cell structure. This can reduce crosstalk, achieve precise control, and reduce energy consumption.

[0080] Figure 4 is a schematic diagram of a ferroelectric memory provided in an embodiment of this application. In some embodiments, the first ferroelectric capacitor pair 106 includes a first ferroelectric capacitor 104 and a second ferroelectric capacitor 105. The third lower electrode 1044 of the first ferroelectric capacitor 104 extends along a first direction, and the fourth lower electrode 1054 of the second ferroelectric capacitor extends along the first direction. The third lower electrode 1044 and the fourth lower electrode 1054 do not contact each other but are connected by an insulating part 110. The third lower electrode 1044, the fourth lower electrode 1054, and the insulating part 110 are collinear in the first direction. The other end of the third lower electrode 1044 is connected to the first wire 107, and the other end of the fourth lower electrode 1054 is connected to the second wire 108. The materials of the third lower electrode 1044 and the fourth lower electrode 1054 are materials with conductive properties, such as at least one of the following materials: titanium nitride (TiN), tungsten (W), nickel (Ni), platinum (Pt), titanium (Ti), tungsten nitride (WN), ruthenium (Ru), and ruthenium oxide (RuO). x ), iridium (Ir), iridium oxide (IrO) xMaterials used include tantalum nitride (TaN), cobalt (Co), aluminum (Al), copper (Cu), polycrystalline silicon (Si), and metal silicides. The materials of the third lower electrode 1044 and the fourth lower electrode 1054 can be the same or different. The insulating portion 110 is made of a material with insulating properties, such as at least one of the following: silicon nitride, silicon oxide, silicon oxynitride, etc. In some other embodiments, the insulating portion 110 can also be a low dielectric constant material or air, which can reduce the parasitic effect between the third lower electrode 1044 and the fourth lower electrode 1054. A third ferroelectric dielectric layer 1062 is disposed on the surface of the third lower electrode 1044, the insulating portion 110, and the fourth lower electrode 1054. A third upper electrode plate 1063 is disposed on the surface of the third ferroelectric dielectric layer 1062, and the third ferroelectric dielectric layer 1062 is located between the third lower electrode 1044, the fourth lower electrode 1054, and the third upper electrode plate 1063, thus insulating the third lower electrode 1044, the fourth lower electrode 1054, and the third upper electrode plate 1063. The material of the third ferroelectric dielectric layer 1062 may include perovskite structure materials such as a mixture of lead zirconate (PbZrO3) and lead titanate (PbTiO3), Pb(Zr,Ti)O3, barium titanate (BaTiO3), etc., or HfO2-based ferroelectric materials doped with at least one element selected from zirconium (Zr), silicon (Si), lanthanum (La), yttrium (Y), strontium (Sr), gadolinium (Gd), and aluminum (Al). This material may be the same as or different from the first ferroelectric dielectric layer 1042 and the second ferroelectric dielectric layer 1052, and is not limited herein. The material of the third upper electrode plate 1063 is a conductive material, for example, it may be at least one of the following: titanium nitride (TiN), tungsten (W), nickel (Ni), platinum (Pt), titanium (Ti), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO2). x ), iridium (Ir), iridium oxide (IrO) x Materials used include tantalum nitride (TaN), cobalt (Co), aluminum (Al), copper (Cu), polycrystalline silicon (Si), and metal silicides. The third lower electrode 1044 and the fourth lower electrode 1054 can be fabricated simultaneously, and the third ferroelectric dielectric layer 1062 and the third upper electrode plate 1063 are each a single unit, which simplifies the fabrication process and reduces production costs.

[0081] Figure 8 is a schematic diagram of another ferroelectric memory provided in an embodiment of this application. In some embodiments, multiple first ferroelectric capacitor pairs 106 are stacked along a third direction, and a third upper electrode plate 1063 is interconnected. The thickness of the third upper electrode plate 1063 can be adjusted to achieve compact stacking along the third direction, thereby increasing storage density. The third upper electrode plate 1063 being connected along the third direction allows for the integral molding of multiple first ferroelectric capacitor pairs, reducing process steps, lowering production costs, and improving production efficiency.

[0082] Figure 9 is a schematic diagram of a three-dimensional ferroelectric memory structure provided in an embodiment of this application. The schematic diagram in Figure 9 can be obtained from the ferroelectric memory arrays of Figures 1 and 5, with each ferroelectric memory being identical. Figure 9 includes a three-dimensional ferroelectric memory structure with three rows arranged along the second direction and three layers of first ferroelectric capacitor pairs stacked along the third direction. In other embodiments, the array may include more ferroelectric memory structures arranged along the first and second directions, and each ferroelectric memory structure may include more first ferroelectric capacitor pairs stacked along the third direction. These first directions (e.g., the X direction), second directions (e.g., the Y direction), and third directions (Z direction) are perpendicular to each other to form a three-dimensional storage array and improve storage density.

[0083] Referring again to FIG9, in some embodiments, the three-dimensional ferroelectric memory includes a substrate 100, a first bit line 101, a first transistor 102, and a first word line 103 located on the substrate. The first bit line 101 extends along a first direction (e.g., the X direction) and is arranged along a second direction (e.g., the Y direction). The first word line extends along the second direction (e.g., the Y direction) and is arranged along the first direction (e.g., the X direction). The first transistor extends along a third direction (Z direction) and is arranged in an array along the first direction (e.g., the X direction) and the second direction (e.g., the Y direction). A plurality of first ferroelectric capacitor pairs 106 are stacked along a third direction (e.g., the Z direction) and arranged along the second direction (e.g., the Y direction). Each first ferroelectric capacitor pair 106 includes a first ferroelectric capacitor 104 and a second ferroelectric capacitor 105, which extend along the first direction (e.g., the X direction). The control terminal of the first transistor 102 is connected to the first word line 103, the second terminal of the first transistor is connected to the first bit line 101, and the first terminal of the first transistor is connected to the upper electrode plate of the first ferroelectric capacitor pair. Multiple first ferroelectric capacitors 106 are stacked along a third direction (e.g., the Z direction), which can reduce the occupied area and increase the storage density. The first ferroelectric capacitor 104 and the second ferroelectric capacitor 105 extend along a first direction (e.g., the X direction). The storage capacity of the ferroelectric capacitors can be adjusted by adjusting the length along the first direction (e.g., the X direction), which solves the sensing margin problem. At the same time, it provides sufficient footprint for the first transistor 102, which helps to optimize the driving capability of the first transistor 102.

[0084] Referring again to Figure 9, in some embodiments, the substrate 100 can be a single-crystal silicon substrate, a polycrystalline silicon substrate, a germanium-silicon substrate, a silicon-on-insulator substrate, a germanium-on-insulator substrate, a glass substrate, a III-V compound substrate (e.g., silicon nitride or gallium arsenide), an oxide semiconductor substrate, or a substrate on which semiconductor devices are formed. In some embodiments, the first transistor in the ferroelectric memory can be an NMOS (N-channel metal oxide semiconductor) or a PMOS (P-channel metal oxide semiconductor). For example, in the memory cell shown in Figure 9, the first transistor is an NMOS transistor. In this case, when a high voltage is applied to the first word line, the first transistor is turned on, and when a low voltage is applied to the first word line, the first transistor is turned off. In other embodiments, the first transistor can be a gate all around, a triple-gate, a dual-gate, or a vertical single-gate transistor; it can also be a planar transistor, a recessed transistor, or a buried transistor. The channel material of the first transistor 102 can be one or more of the following semiconductor materials: silicon (Si), polycrystalline silicon (p-Si), amorphous silicon (a-Si), indium gallium zinc oxide (In-Ga-Zn-O, IGZO) multi-component compound, zinc oxide (ZnO), ITO, titanium dioxide (TiO2), molybdenum disulfide (MoS2), etc. This application does not impose specific limitations on this. This application only uses a vertical dual-gate transistor as an example for illustration.

[0085] Referring again to Figure 9, in some embodiments, the control terminal of the first transistor 102 is called the gate, and one of the drain or source terminals of the MOS transistor is called the first terminal, and the corresponding other terminal is called the second terminal. For example, the first terminal of the first transistor can be the source and the second terminal can be the drain; or the first terminal can be the drain and the second terminal can be the source. The control terminal of the first transistor 102 arranged along a second direction (e.g., the Y direction) is connected to the first word line 103, and the second terminal of the first transistor 102 arranged along a first direction (e.g., the X direction) is connected to the first bit line 101. The materials of the first bit line 101 and the first word line 103 are materials with conductive properties, such as at least one of the following materials: titanium nitride (TiN), tungsten (W), nickel (Ni), platinum (Pt), titanium (Ti), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO). x ), iridium (Ir), iridium oxide (IrO) xMaterials used include tantalum nitride (TaN), cobalt (Co), aluminum (Al), copper (Cu), polycrystalline silicon (Si), and metal silicides. The materials of the first letter line 103 and the first digit line 101 can be the same or different.

[0086] Referring again to FIG9, in some embodiments, the first ferroelectric capacitor pair 106 includes a first ferroelectric capacitor 104 and a second ferroelectric capacitor 105. The first ferroelectric capacitor 104 and the second ferroelectric capacitor 105 include a lower electrode, a ferroelectric dielectric layer and an upper electrode plate. The first lower electrode 1041 of the first ferroelectric capacitor extends along a first direction. The first ferroelectric dielectric layer 1042 is disposed on the surface of the first lower electrode 1041. The first upper electrode plate 1043 is disposed on the surface of the first ferroelectric dielectric layer 1042. The first ferroelectric dielectric layer 1042 is located between the first lower electrode 1041 and the first upper electrode plate 1043, thereby insulating the first lower electrode 1041 and the first upper electrode plate 1043. The second lower electrode 1051 of the second ferroelectric capacitor 105 extends along the first direction, the second ferroelectric dielectric layer 1052 is disposed on the surface of the second lower electrode 1051, the second upper electrode plate 1503 is disposed on the surface of the second ferroelectric dielectric layer 1052, the second ferroelectric dielectric layer 1052 is located between the second lower electrode 1051 and the second upper electrode plate 1053, so that the second lower electrode 1051 and the second upper electrode plate 1053 are insulated from each other. The materials of the first ferroelectric dielectric layer 1042 and the second ferroelectric dielectric layer 1052 may include perovskite structure materials such as a mixture of lead zirconate (PbZrO3) and lead titanate (PbTiO3), Pb(Zr,Ti)O3, and barium titanate (BaTiO3), or HfO2-based ferroelectric materials doped with at least one element selected from zirconium (Zr), silicon (Si), lanthanum (La), yttrium (Y), strontium (Sr), gadolinium (Gd), and aluminum (Al). This application does not limit the materials and manufacturing processes of the ferroelectric film layers.

[0087] Referring again to Figure 9, in some embodiments, the materials of the first lower electrode 1041, the second lower electrode 1051, the first upper electrode plate 1043, and the second upper electrode plate 1053 are conductive materials, such as at least one of the following: titanium nitride (TiN), tungsten (W), nickel (Ni), platinum (Pt), titanium (Ti), tungsten nitride (WN), ruthenium (Ru), and ruthenium oxide (RuO). x ), iridium (Ir), iridium oxide (IrO) xMaterials used include tantalum nitride (TaN), cobalt (Co), aluminum (Al), copper (Cu), polycrystalline silicon (Si), and metal silicides. The materials of the first lower electrode 1041, the second lower electrode 1051, the first upper electrode plate 1043, and the second upper electrode plate 1053 can be the same or different. The first upper electrode plate 1043 is in contact with the second upper electrode plate 1053, and the first end of the first transistor 102 is connected to the first upper electrode plate 1043 and the second upper electrode plate 1053. Multiple first ferroelectric capacitor pairs 106 are stacked along a third direction and connected to the first transistor 102, which reduces the number of transistors and increases storage density. Furthermore, since each first ferroelectric capacitor pair 106 is in contact with both the first upper electrode plate 1043 and the second upper electrode plate 1053, the upper electrode plate can be integrally formed, reducing the difficulty of the fabrication process, reducing the fabrication time, improving production efficiency, and saving production costs.

[0088] Referring again to Figure 9, in some embodiments, the three-dimensional ferroelectric memory further includes a first wire 107 and a second wire 108. The first wire 107 and the second wire 108 extend along a second direction (e.g., the Y direction) and are arranged along a third direction (e.g., the Z direction), respectively. The first wire 107 is connected to a first lower electrode 1041 arranged along the second direction (e.g., the Y direction) on the same horizontal plane as the third direction (e.g., the Z direction). The second wire 108 is connected to a second lower electrode 1051 arranged along the second direction (e.g., the Y direction) on the same horizontal plane as the third direction (e.g., the Z direction). This reduces the number of first wires 107 and second wires 108, saves space, and increases storage density. The first wire 107 and the second wire 108 are made of conductive materials, such as at least one of the following: titanium nitride (TiN), tungsten (W), nickel (Ni), platinum (Pt), titanium (Ti), tungsten nitride (WN), ruthenium (Ru), and ruthenium oxide (RuO). x ), iridium (Ir), iridium oxide (IrO) x Materials used include tantalum nitride (TaN), cobalt (Co), aluminum (Al), copper (Cu), polycrystalline silicon (Si), and metal silicides. The materials of the first conductor 107 and the second conductor 108 can be the same or different.

[0089] Figure 10 is a schematic diagram of a three-dimensional ferroelectric memory provided in an embodiment of this application. In some embodiments, the first ferroelectric capacitor pair 106 includes a first ferroelectric capacitor 104 and a second ferroelectric capacitor 105. The first ferroelectric capacitor 104 and the second ferroelectric capacitor 105 include a lower electrode, a ferroelectric dielectric layer and an upper electrode plate. The first lower electrode 1041 of the first ferroelectric capacitor extends along a first direction. The first ferroelectric dielectric layer 1042 is disposed on the surface of the first lower electrode 1041. The first upper electrode plate 1043 is disposed on the surface of the first ferroelectric dielectric layer 1042. The first ferroelectric dielectric layer 1042 is located between the first lower electrode 1041 and the first upper electrode plate 1043, so that the first lower electrode 1041 and the first upper electrode plate 1043 are insulated from each other. The second lower electrode 1051 of the second ferroelectric capacitor 105 extends along the first direction, the second ferroelectric dielectric layer 1052 is disposed on the surface of the second lower electrode 1051, the second upper electrode plate 1503 is disposed on the surface of the second ferroelectric dielectric layer 1052, the second ferroelectric dielectric layer 1052 is located between the second lower electrode 1051 and the second upper electrode plate 1053, so that the second lower electrode 1051 and the second upper electrode plate 1053 are insulated from each other. The first upper electrode plate 1043 and the second upper electrode plate 1053 are not in direct contact. A connection portion 109 is provided on the first terminal of the first transistor. The connection portion 109 is connected to the first upper electrode plate 1043 and the second electrode plate 1053 respectively. The interface shape of the connection portion can be elliptical, rectangular, bench-shaped, or other shapes that allow the first upper electrode plate 1043 and the second upper electrode plate 1053 to be connected to the first transistor 102 without being connected to each other. The material of the connection portion 109 is a material with conductive properties, such as at least one of the following materials: titanium nitride (TiN), tungsten (W), nickel (Ni), platinum (Pt), titanium (Ti), tungsten nitride (WN), ruthenium (Ru), and ruthenium oxide (RuO). x ), iridium (Ir), iridium oxide (IrO) x Materials used include tantalum nitride (TaN), cobalt (Co), aluminum (Al), copper (Cu), polycrystalline silicon (Si), and metal silicides. The first upper electrode plate 1043 and the second upper electrode plate 1053 are not in contact, but are connected to the first transistor 102 via the connecting part 109, which reduces crosstalk between the first capacitor 104 and the second capacitor 105, improving the performance of the ferroelectric memory. Furthermore, since each first ferroelectric capacitor pair 106 has a non-contact first upper electrode plate 1043 and second upper electrode plate 1053, they can be fabricated separately, increasing the fabrication window, reducing the fabrication process difficulty, and improving production efficiency.

[0090] Figure 11 is a schematic diagram of a three-dimensional ferroelectric memory provided in an embodiment of this application. In some embodiments, the ferroelectric memory further includes a second transistor 202, a second word line 203, and a second bit line 101 (the second bit line and the first bit line can be shared or separated). The control terminal of the second transistor 202 is connected to the second word line 203, and the second end of the second transistor 202 is connected to the second bit line 101. The first end of the second transistor 202 and the first end of the first transistor 102 are respectively connected to the upper electrode plate of the ferroelectric capacitor. They are identical and have the same function, so they will not be described in detail here. In some embodiments, the first ferroelectric capacitor pair 106 includes a first ferroelectric capacitor 104 and a second ferroelectric capacitor 105. The first ferroelectric capacitor 104 and the second ferroelectric capacitor 105 include a lower electrode, a ferroelectric dielectric layer, and an upper electrode plate. The first lower electrode 1041 of the first ferroelectric capacitor extends along a first direction. The first ferroelectric dielectric layer 1042 is disposed on the surface of the first lower electrode 1041. The first upper electrode plate 1043 is disposed on the surface of the first ferroelectric dielectric layer 1042. The first ferroelectric dielectric layer 1042 is located between the first lower electrode 1041 and the first upper electrode plate 1043, thereby insulating the first lower electrode 1041 and the first upper electrode plate 1043. The second lower electrode 1051 of the second ferroelectric capacitor 105 extends along the first direction, the second ferroelectric dielectric layer 1052 is disposed on the surface of the second lower electrode 1051, the second upper electrode plate 1503 is disposed on the surface of the second ferroelectric dielectric layer 1052, the second ferroelectric dielectric layer 1052 is located between the second lower electrode 1051 and the second upper electrode plate 1053, so that the second lower electrode 1051 and the second upper electrode plate 1053 are insulated from each other.

[0091] Referring again to Figure 11, in some embodiments, the first upper electrode plate 1043 and the second upper electrode 1053 are not in contact. The first upper electrode 1043 is connected to the first end of the first transistor 102, and the second upper electrode plate 1053 is connected to the second end of the second transistor 202. The first bit line 101, the first transistor 102, the first word line 103, and the first capacitor 104 form a basic ferroelectric memory cell structure. The second bit line 101, the second transistor 202, the second word line 203, and the second capacitor 105 form a basic ferroelectric memory cell structure. Each basic ferroelectric memory cell structure can be controlled independently, which can reduce crosstalk, achieve precise control, and reduce energy consumption.

[0092] Figure 12 is a schematic diagram of a three-dimensional ferroelectric memory provided in an embodiment of this application. In some embodiments, the first ferroelectric capacitor pair 106 includes a first ferroelectric capacitor 104 and a second ferroelectric capacitor 105. The third lower electrode 1044 of the first ferroelectric capacitor 104 extends along a first direction, and the fourth lower electrode 1054 of the second ferroelectric capacitor extends along the first direction. The third lower electrode 1044 and the fourth lower electrode 1054 do not contact each other but are connected by an insulating part 110. The third lower electrode 1044, the fourth lower electrode 1054, and the insulating part 110 are collinear in the first direction. The other end of the third lower electrode 1044 is connected to the first wire 107, and the other end of the fourth lower electrode 1054 is connected to the second wire 108. The materials of the third lower electrode 1044 and the fourth lower electrode 1054 are materials with conductive properties, such as at least one of the following materials: titanium nitride (TiN), tungsten (W), nickel (Ni), platinum (Pt), titanium (Ti), tungsten nitride (WN), ruthenium (Ru), and ruthenium oxide (RuO). x ), iridium (Ir), iridium oxide (IrO) xMaterials used include tantalum nitride (TaN), cobalt (Co), aluminum (Al), copper (Cu), polycrystalline silicon (Si), and metal silicides. The materials of the third lower electrode 1044 and the fourth lower electrode 1054 can be the same or different. The insulating portion 110 is made of a material with insulating properties, such as at least one of the following: silicon nitride, silicon oxide, silicon oxynitride, etc. In some other embodiments, the insulating portion 110 can also be a low dielectric constant material or air, which can reduce the parasitic effect between the third lower electrode 1044 and the fourth lower electrode 1054. A third ferroelectric dielectric layer 1062 is disposed on the surface of the third lower electrode 1044, the insulating portion 110, and the fourth lower electrode 1054. A third upper electrode plate 1063 is disposed on the surface of the third ferroelectric dielectric layer 1062, and the third ferroelectric dielectric layer 1062 is located between the third lower electrode 1044, the fourth lower electrode 1054, and the third upper electrode plate 1063, thus insulating the third lower electrode 1044, the fourth lower electrode 1054, and the third upper electrode plate 1063. The material of the third ferroelectric dielectric layer 1062 may include perovskite structure materials such as a mixture of lead zirconate (PbZrO3) and lead titanate (PbTiO3), Pb(Zr,Ti)O3, barium titanate (BaTiO3), etc., or HfO2-based ferroelectric materials doped with at least one element selected from zirconium (Zr), silicon (Si), lanthanum (La), yttrium (Y), strontium (Sr), gadolinium (Gd), and aluminum (Al). This material may be the same as or different from the first ferroelectric dielectric layer 1042 and the second ferroelectric dielectric layer 1052, and is not limited herein. The material of the third upper electrode plate 1063 is a conductive material, for example, it may be at least one of the following: titanium nitride (TiN), tungsten (W), nickel (Ni), platinum (Pt), titanium (Ti), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO2). x ), iridium (Ir), iridium oxide (IrO) x Materials used include tantalum nitride (TaN), cobalt (Co), aluminum (Al), copper (Cu), polycrystalline silicon (Si), and metal silicides. The third lower electrode 1044 and the fourth lower electrode 1054 can be fabricated simultaneously, and the third ferroelectric dielectric layer 1062 and the third upper electrode plate 1063 are each a single unit, which simplifies the fabrication process and reduces production costs.

[0093] Figure 13 is a schematic diagram of another three-dimensional ferroelectric memory provided in an embodiment of this application. In some embodiments, the three-dimensional ferroelectric memory includes a substrate 100, a first ferroelectric capacitor pair 106 located on the substrate, a first word line 103, a first transistor 102, and a first bit line 101 located on the first ferroelectric capacitor pair 106. Multiple first ferroelectric capacitor pairs 106 are stacked along a third direction (e.g., the Z direction) and arranged along a second direction (e.g., the Y direction). Each first ferroelectric capacitor pair 106 includes a first ferroelectric capacitor 104 and a second ferroelectric capacitor 105, which extend along a first direction (e.g., the X direction). The first bit line 101 extends along the first direction (e.g., the X direction) and is arranged along the second direction (e.g., the Y direction). The first word line extends along the second direction (e.g., the Y direction) and is arranged along the first direction (e.g., the X direction). The first transistor extends along a third direction (Z direction) and is arranged in an array along the first direction (e.g., the X direction) and the second direction (e.g., the Y direction). The control terminal of the first transistor 102 is connected to the first word line 103, the second terminal of the first transistor is connected to the first bit line 101, and the first terminal of the first transistor is connected to the upper electrode plate of the first ferroelectric capacitor pair. The first ferroelectric capacitor pair 106, the first word line 103, the first transistor 102, and the first bit line 101 are no different from those in the previous embodiments and have the same function, so they will not be described again here.

[0094] Figure 14 is a schematic diagram of the structure of a three-dimensional ferroelectric memory device provided in an embodiment of this application. This disclosure also provides a three-dimensional ferroelectric memory device, as shown in Figure 14, in which a back-end connection (not shown) is provided on the memory cell. The back-end connection is located above the three-dimensional memory and is connected to the first word line 103 and the first bit line 101, respectively. The back-end connection is made of a conductive material, such as at least one of the following materials: titanium nitride (TiN), tungsten (W), nickel (Ni), platinum (Pt), titanium (Ti), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO). x ), iridium (Ir), iridium oxide (IrO) x Materials used include tantalum nitride (TaN), cobalt (Co), aluminum (Al), copper (Cu), polycrystalline silicon (Si), and metal silicides. The materials of the back-end interconnects and the first word line 103 and the second bit line 101 can be the same or different. In some embodiments, the three-dimensional ferroelectric memory device further includes a peripheral device wafer 300, which has various peripheral circuit devices, such as driver devices, decoder devices, error correction devices, and other devices. The peripheral device wafer 300 is connected to the back-end interconnects and bonded to the wafer containing the ferroelectric memory.

[0095] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0096] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A ferroelectric memory, comprising: First word line (103), first bit line (101), first transistor (102), first ferroelectric capacitor pair (106); The first ferroelectric capacitor pair (106) includes a first ferroelectric capacitor (104) and a second ferroelectric capacitor (105), the first ferroelectric capacitor (104) and the second ferroelectric capacitor (105) extending along a first direction; The control terminal of the first transistor (102) is connected to the first word line (103), the second terminal of the first transistor (102) is connected to the first bit line (101), and the first terminal of the first transistor (102) is connected to the upper electrode plate of the first ferroelectric capacitor pair (106).

2. The ferroelectric memory according to claim 1, wherein, The upper electrode plate includes a first upper electrode plate (1043) and a second upper electrode plate (1053); The first lower electrode (1041) of the first ferroelectric capacitor (104) extends along the first direction, the first ferroelectric dielectric layer (1042) is disposed on the surface of the first lower electrode (1041), and the first upper electrode plate (1043) is disposed on the surface of the first ferroelectric dielectric layer (1042). The second lower electrode (1051) of the second ferroelectric capacitor (105) extends along the first direction, the second ferroelectric dielectric layer (1052) is disposed on the surface of the second lower electrode (1051), and the second upper electrode plate (1053) is disposed on the surface of the second ferroelectric dielectric layer (1052).

3. The ferroelectric memory according to claim 2, wherein, The first upper electrode plate (1043) is in contact with the second upper electrode plate (1053), and the first end of the first transistor (102) is in contact with and connected to the first upper electrode plate (1043) and the second upper electrode plate (1053).

4. The ferroelectric memory according to claim 2 or 3, wherein, The first upper electrode plate (1043) and the second upper electrode plate (1053) are not in contact. The first end of the first transistor (102) is in contact with the first upper electrode plate (1043) and the second upper electrode plate (1053) respectively through the connecting part (109).

5. The ferroelectric memory according to any one of claims 2-4, further comprising: Second word line (203), second bit line (101), second transistor (202); The control terminal of the second transistor (202) is connected to the second word line (203), and the second terminal of the second transistor (202) is connected to the second bit line (101). The first upper electrode plate (1043) and the second upper electrode plate (1053) are not in contact. The first end of the first transistor (102) is in contact with the first upper electrode plate (1043); the first end of the second transistor (202) is in contact with the second upper electrode plate (1053).

6. The ferroelectric memory according to any one of claims 1-5, wherein, The upper electrode plate also includes a third upper electrode plate (1063); The third lower electrode (1044) of the first ferroelectric capacitor (104) extends along the first direction, and the fourth lower electrode (1054) of the second ferroelectric capacitor (105) extends along the first direction. The third lower electrode (1044) and the fourth lower electrode (1054) are connected by an insulating part (110). The third ferroelectric dielectric layer (1062) is disposed on the surface of the third lower electrode (1044) and the fourth lower electrode (1054), and the third upper electrode plate (1063) is disposed on the surface of the third ferroelectric dielectric layer (1062).

7. The ferroelectric memory according to any one of claims 1-6, further comprising: A first wire (107) is connected to the lower electrode of the first ferroelectric capacitor (104); The second wire (108) is connected to the lower electrode of the second ferroelectric capacitor (105).

8. A three-dimensional ferroelectric memory, comprising: Substrate (100); A plurality of first bit lines (101), a plurality of first word lines (103), and a plurality of first transistors (102) are located on the substrate (100); The plurality of first bit lines (101) extend along a first direction and are arranged along a second direction, the plurality of first word lines (103) extend along a second direction and are arranged along a first direction, the plurality of transistors are arranged along a first direction and a second direction, and the first direction and the second direction intersect. A plurality of first ferroelectric capacitor pairs (106), each first ferroelectric capacitor pair (106) including a first ferroelectric capacitor (104) and a second ferroelectric capacitor (105), the first ferroelectric capacitor (104) and the second ferroelectric capacitor (105) extending along a first direction and arranged along a third direction, the first direction, the second direction and the third direction intersecting each other; The first word line (103) extending along the first direction is connected to the control terminal of the first transistor (102) arranged along the first direction, the first bit line (101) extending along the second direction is connected to the second end of the first transistor (102) arranged along the second direction, and the first end of the first transistor (102) is connected to the upper electrode plate of the first ferroelectric capacitor pair (106).

9. The three-dimensional ferroelectric memory according to claim 8, wherein, The upper electrode plate includes a first upper electrode plate (1043) and a second upper electrode plate (1053); The first lower electrode (1041) of the first ferroelectric capacitor (104) extends along the first direction, the first ferroelectric dielectric layer (1042) is disposed on the surface of the first lower electrode (1041), and the first upper electrode plate (1043) is disposed on the surface of the first ferroelectric dielectric layer (1042). The second lower electrode (1051) of the second ferroelectric capacitor (105) extends along the first direction, the second ferroelectric dielectric layer (1052) is disposed on the surface of the second lower electrode (1051), and the second upper electrode plate (1053) is disposed on the surface of the second ferroelectric dielectric layer (1052).

10. The three-dimensional ferroelectric memory according to claim 9, wherein, The first upper electrode plate (1043) is in contact with the second upper electrode plate (1053), and the first end of the first transistor (102) is in contact with and connected to the first upper electrode plate (1043) and the second upper electrode plate (1053).

11. The three-dimensional ferroelectric memory according to claim 9 or 10, wherein, The first upper electrode plate (1043) and the second upper electrode plate (1053) are not in contact. The first end of the first transistor (102) is in contact with the first upper electrode plate (1043) and the second upper electrode plate (1053) respectively through the connecting part (109).

12. The three-dimensional ferroelectric memory according to any one of claims 9-11, further comprising: Second word line (203), second bit line (101), second transistor (202); The control terminal of the second transistor (202) is connected to the second word line (203), and the second terminal of the second transistor (202) is connected to the second bit line (101). The first upper electrode plate (1043) and the second upper electrode plate (1053) are not in contact. The first end of the first transistor (102) is in contact with the first upper electrode plate (1043); the first end of the second transistor (202) is in contact with the second upper electrode plate (1053).

13. The three-dimensional ferroelectric memory according to any one of claims 8-12, wherein, The upper electrode plate includes a first upper electrode plate (1043) and a second upper electrode plate (1053); The third lower electrode (1044) of the first ferroelectric capacitor (104) extends along the first direction, and the fourth lower electrode (1054) of the second ferroelectric capacitor (105) extends along the first direction. The third lower electrode (1044) and the fourth lower electrode (1054) are connected by an insulating part (110). The third ferroelectric dielectric layer (1062) is disposed on the surface of the third lower electrode (1044) and the fourth lower electrode (1054), and the third upper electrode plate (1063) is disposed on the surface of the third ferroelectric dielectric layer (1062).

14. The three-dimensional ferroelectric memory according to any one of claims 8-13, further comprising: A plurality of first wires (107) are respectively connected to the lower electrode of the first ferroelectric capacitor (104); A plurality of second wires (108) are connected to the lower electrode of the second ferroelectric capacitor (105).

15. A three-dimensional ferroelectric storage device, comprising: A three-dimensional ferroelectric memory, wherein the three-dimensional ferroelectric memory is the three-dimensional ferroelectric memory as described in any one of claims 8 to 14; A peripheral device wafer (300) is coupled to the three-dimensional ferroelectric memory.

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