Display panel and display apparatus

Abstract

The present application provides a display panel and a display apparatus, which solve the problem in the prior art of how to make full use of the wiring space in a display panel. The display panel comprises: a substrate; a first element portion located on the substrate; a second element portion located on the substrate; a third element portion located on the substrate, wherein the third element portion and the first element portion are arranged in different layers, and the third element portion and the second element portion are arranged in different layers; a first via hole exposing at least part of the surface of the third element portion away from the substrate, at least part of the surface of the first element portion away from the substrate, and at least part of the surface of the second element portion away from the substrate; and a first connecting portion filling the first via hole, wherein the first connecting portion is electrically connected to the third element portion, the first element portion, and the second element portion.

Description

Display panel and display device

[0001] Cross-reference to related applications

[0002] This application claims priority to Chinese Patent Application No. 2024111951235, entitled “Display Panel and Display Device”, filed on August 28, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This application relates to the field of display technology, specifically to a display panel and a display device.

[0004] Background of the Invention

[0005] With the development of display technology, the industry's requirements for the thickness and resolution of display products are constantly increasing, leading to increasingly tight wiring space. Summary of the Invention

[0006] In view of this, embodiments of this application provide a display panel and a display device, which solves the problem of how to make full use of the wiring space within the display panel in the prior art.

[0007] This application provides a display panel in a first aspect. The display panel includes a substrate; a first element portion located on the substrate; a second element portion located on the substrate; a third element portion located on the substrate, wherein the third element portion and the first element portion are disposed in different layers, and the third element portion and the second element portion are disposed in different layers; a first via exposing at least a portion of the surface of the third element portion away from the substrate, at least a portion of the surface of the first element portion away from the substrate, and at least a portion of the surface of the second element portion away from the substrate; and a first connecting portion filling the first via, wherein the first connecting portion is electrically connected to the third element portion, the first element portion, and the second element portion.

[0008] A second aspect of this application provides another display panel, comprising: a substrate; a first element portion located on the substrate; a second element portion located on the substrate; a third element portion located on the substrate, wherein the third element portion and the first element portion are disposed in different layers; a plurality of first vias, wherein at least one first via exposes at least a portion of the surface of the third element portion away from the substrate, at least a portion of the surface of the first element portion away from the substrate, and at least a portion of the surface of the third element portion away from the substrate, and at least a portion of the surface of the second element portion away from the substrate; a plurality of first connecting portions filling corresponding first vias, wherein the first connecting portions electrically connecting the third element portion and the first element portion are spaced apart from the first connecting portions electrically connecting the third element portion and the second element portion.

[0009] A third aspect of this application provides a display device, including the display panel provided in any of the above embodiments.

[0010] According to the display panel and display device provided in the embodiments of this application, the first element part and the second element part are respectively connected to the third element part by using the first via. Compared with the layout of related technologies that requires three vias to realize electrical connection, the wiring space of the display panel is saved, which makes it possible to realize high-resolution display.

[0011] Brief description of the attached figures

[0012] Figure 1 is a partial cross-sectional structural diagram of the display panel provided in the first embodiment of this application.

[0013] Figure 2 is a partial top view of the display panel shown in Figure 1 provided in the first embodiment of this application.

[0014] Figure 3 is a partial top view of the display panel shown in Figure 1 provided in the second embodiment of this application.

[0015] Figure 4a is a partial cross-sectional structural diagram of the display panel provided in the second embodiment of this application.

[0016] Figure 4b is a partial top view of the display panel shown in Figure 4a.

[0017] Figure 5a is a partial cross-sectional structural diagram of the display panel provided in the third embodiment of this application.

[0018] Figure 5b is a partial cross-sectional structural diagram of the display panel provided in the fourth embodiment of this application.

[0019] Figure 5c is a partial cross-sectional structural diagram of the display panel provided in the fifth embodiment of this application.

[0020] Figure 6a is a partial top view of the display panel provided in the sixth embodiment of this application.

[0021] Figure 6b is a schematic diagram of a partial cross-sectional structure of the display panel shown in Figure 6a along the N7N8 line.

[0022] Figure 7a is a partial top view of the display panel provided in the seventh embodiment of this application.

[0023] Figure 7b is a schematic diagram of a partial cross-sectional structure of the display panel shown in Figure 7a along the N9N10 line.

[0024] Figure 8 is a first layout of a display panel provided in an embodiment of this application.

[0025] Figure 9a is the routing diagram of the active layer in the layout shown in Figure 8.

[0026] Figure 9b is the wiring diagram of the first conductive layer in the layout shown in Figure 8.

[0027] Figure 9c is a schematic diagram of the stacked structure of the active layer and the first conductive layer in the layout shown in Figure 8.

[0028] Figure 9d is a schematic diagram of the via arrangement in the layout shown in Figure 8.

[0029] Figure 9e is a schematic diagram of the stacked structure of vias, active layer and first conductive layer in the layout shown in Figure 8.

[0030] Figure 9f is a schematic diagram of the stacked structure of the second conductive layer in the layout shown in Figure 8.

[0031] Figure 9g is a schematic diagram of the stacked structure of the active layer, the first conductive layer and the second conductive layer in the layout shown in Figure 8.

[0032] Figure 10 is a circuit diagram of the pixel circuits included in the layout shown in Figure 8.

[0033] Figure 11 is a second layout of a display panel provided in an embodiment of this application.

[0034] Figure 12 is a wiring diagram of the first conductive layer in the layout shown in Figure 8, provided by another embodiment of this application.

[0035] Figure 13 is a cross-sectional structural diagram of a display panel including the layout shown in Figure 8, provided in an embodiment of this application.

[0036] Figure 14 shows the driving timing of a pixel circuit provided in an embodiment of this application.

[0037] Figure 15a is a circuit diagram of a pixel circuit provided in another embodiment of this application.

[0038] Figure 15b is a third layout of a display panel provided in an embodiment of this application.

[0039] Figure 16 is a fourth layout of a display panel provided in an embodiment of this application.

[0040] Figure 17 is a fifth layout of a display panel provided in an embodiment of this application.

[0041] Figure 18 is a sixth layout of a display panel provided in an embodiment of this application.

[0042] Figure 19 is a seventh layout of a display panel provided in an embodiment of this application.

[0043] Figure 20 is an eighth layout of a display panel provided in an embodiment of this application.

[0044] Figure 21 is a ninth layout of a display panel provided in an embodiment of this application.

[0045] Figure 22 is a circuit diagram of a pixel circuit provided in another embodiment of this application.

[0046] Figure 23 is a circuit diagram of a pixel circuit provided in another embodiment of this application.

[0047] Figure 24a is a partial top view of the display panel provided in another embodiment of this application.

[0048] Figure 24b is a partial cross-sectional structural diagram of a display panel provided in another embodiment of this application.

[0049] Figure 24c is a tenth layout of a display panel provided in an embodiment of this application.

[0050] Figure 25 is a schematic diagram of the structure of a display device provided in an embodiment of this application.

[0051] Methods of implementing the present invention

[0052] As mentioned in the background section, with the development of display technology, the industry's requirements for the thickness and resolution of display products are constantly increasing, leading to increasingly tight wiring space. The inventors discovered that one reason for this problem is that in related technologies, to simultaneously connect the electrodes (e.g., drain or source) of two transistors to the reference voltage signal line Vref, three conductive vias are required. On the one hand, these three conductive vias significantly occupy the wiring space of the second conductive layer; on the other hand, the wiring width of the reference voltage signal line Vref needs to be compressed to accommodate the three conductive vias, increasing the resistance of the reference voltage signal line Vref.

[0053] In view of this, embodiments of this application provide a display panel, a substrate, and a display device that save wiring space by merging three conductive vias into one.

[0054] In the accompanying drawings, the dimensions of layers and regions may be exaggerated for clarity. It is understood that when a structure is referred to as being "on" or "below" another structure, the structure may be directly on or below the other structure, or there may be intermediate structures. The same reference numerals always indicate the same structure. Structures referred to herein include any of the following: membrane, element, device, component, assembly.

[0055] When a structure is referred to as being “connected” to another structure, it can be directly connected to the other structure or indirectly connected to the other structure by means of one or more intermediate structures placed between them.

[0056] The terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0057] This application provides a display panel in a first aspect. FIG1 is a partial cross-sectional structural schematic diagram of the display panel provided in the first embodiment of this application. As shown in FIG1, the display panel includes a substrate 11, a first element portion 12, a second element portion 13, a third element portion 14, a first via H1, and a first connecting portion 15. The first element portion 12 is located on the substrate 11. The second element portion 13 is located on the substrate 11. The third element portion 14 is located on the substrate 11. The third element portion 14 and the first element portion 12 are disposed in different layers; for example, an insulating layer is disposed between the film layer containing the third element portion 14 and the film layer containing the first element portion 12. The third element portion 14 and the second element portion 13 are disposed in different layers; for example, an insulating layer is disposed between the film layer containing the third element portion 14 and the film layer containing the second element portion 13. The first via H1 exposes at least a portion of the surface of the third element portion 14 away from the substrate 11, at least a portion of the surface of the first element portion 12 away from the substrate 11, and at least a portion of the surface of the second element portion 13 away from the substrate 11. The first connecting portion 15 fills the first via H1. The first connecting part 15 is electrically connected to the third element part 14, the first element part 12, and the second element part 13, for example, through electrical contact.

[0058] For example, the first connection portion 15 covers at least a portion of the surface of the third element portion 14 exposed by the first via H1 away from the substrate 11, at least a portion of the surface of the first element portion 12 away from the substrate 11, and at least a portion of the surface of the second element portion 13 away from the substrate 11.

[0059] For example, the first element portion 12 and the second element portion 13 are disposed in the same layer, for example, by patterning the same film layer to obtain the first element portion 12 and the second element portion 13. For example, the third element portion 14 may extend along the first direction x, for example, it may extend along the first direction x in a straight line, a broken line, a curve, a dendritic shape, an irregular shape, etc. For example, the orthographic projection of the first element portion 12 on the substrate 11 and the orthographic projection of the second element portion 13 on the substrate 11 may be located on opposite sides of the orthographic projection of the third element portion 14 on the substrate 11 along the second direction y. The second direction y intersects the first direction x, for example, the second direction y is perpendicular to the first direction x.

[0060] For example, as shown in FIG1, the film layer containing the third element portion 14 is located on the side away from the substrate 11 of the film layer containing the first element portion 12 and the film layer containing the second element portion 13. Alternatively, the film layer containing the third element portion 14 is located on the side closer to the substrate 11 of the film layer containing the first element portion 12 and the film layer containing the second element portion 13.

[0061] For example, the display panel further includes a second connecting portion 16 connected between the first element portion 12 and the second element portion 13. The overlapping area of ​​the orthographic projection of the second connecting portion 16 on the substrate 11 and the orthographic projection of the third element portion 14 on the substrate 11 overlaps with the orthographic projection of the first connecting portion 12 on the substrate 11. For example, the first element portion 12, the second element portion 13, and the second connecting portion 16 are disposed on the same layer. The first element portion 12, the second element portion 13, and the second connecting portion 16 are located on the same active layer, which may include materials such as polysilicon or metal oxide. The metal oxide may include indium gallium zinc oxide (IGZO). The third element portion 14 is located on the gate layer.

[0062] For example, the display panel further includes a first insulating layer 17 located between the film layer containing the third element portion 14 and the film layer containing the first element portion 13, for example, the first element portion 12 and the second element portion 13 are disposed in the same layer or in different layers. A first via H1 penetrates the first insulating layer 17 along the thickness direction z of the substrate 11, exposing at least a portion of the surface of the first element portion 12 away from the substrate 11 and at least a portion of the surface of the second element portion 13 away from the substrate 11. For example, the first insulating layer 17 may be a gate insulating layer.

[0063] For example, the display panel may further include a second insulating layer 18 located on the side of the film layer containing the third element portion 14 and the first insulating layer 17 away from the substrate 11. A first via H1 penetrates the second insulating layer 18 to expose at least a portion of the surface of the third element portion 14 away from the substrate 11. The first via H1 penetrates the first insulating layer 17 and the second insulating layer 18 to expose at least a portion of the surface of the first element portion 12 away from the substrate 11 and at least a portion of the surface of the second element portion 13 away from the substrate 11. For example, the second insulating layer may include a capacitor dielectric layer and / or an interlayer insulating layer.

[0064] According to the display panel provided in this embodiment, the first element part 12 and the second element part 13 are connected to the third element part 14 by using a single via, namely the first via H1. Compared with the layout of related technologies that requires three vias to achieve electrical connection, this saves the wiring space of the display panel and makes it possible to realize high-resolution display.

[0065] Figure 2 is a partial top view of the display panel shown in Figure 1 according to the first embodiment of this application. The cross-sectional view of the display panel shown in Figure 1 can be the cross-sectional view corresponding to the cross-sectional lines N1 and N2 in Figure 2. In this embodiment, the third element part 14 is a first trace, which includes a first trace segment 141 and a second trace segment 142 arranged along the extension direction of the first trace. The overlapping area of ​​the orthographic projection of the second connecting part 16 on the substrate 11 and the orthographic projection of the first trace segment 141 on the substrate 11 overlaps with the orthographic projection of the first connecting part 15 on the substrate 11. The width of the first trace segment 141 is equal to the width of the second trace segment 142.

[0066] For example, the first trace is the initialization signal line Ref.

[0067] For example, the orthographic projection of the first connecting portion 15 onto the substrate 11 is rectangular. For example, the orthographic projection of the first via H1 onto the substrate 11 is rectangular.

[0068] For example, at least a portion of the width of the first routing segment 141 is less than or equal to the width of the second routing segment 142.

[0069] Figure 3 is a partial top view of the display panel shown in Figure 1 according to the second embodiment of this application. The cross-sectional view of the display panel shown in Figure 1 can be the cross-sectional view corresponding to cross-sectional lines N3 and N4 in Figure 3. The difference between the display panel shown in Figure 3 and the display panel shown in Figure 2 is that, in this embodiment, at least a portion of the width of the first trace segment 141 is smaller than the width of the second trace segment 142. This further reduces the layout space occupied.

[0070] For example, the first trace segment 141 has a notch G on one or both sides of its own width direction (e.g., parallel to the second direction Y), and the orthogonal projection of the notch G on the substrate overlaps with the orthogonal projection of the first via H1 on the substrate.

[0071] Figure 4a is a partial cross-sectional structural schematic diagram of the display panel provided in the second embodiment of this application. Figure 4b is a partial top view structural schematic diagram of the display panel shown in Figure 4a. The cross-sectional view shown in Figure 4a can be the cross-sectional view corresponding to cross-sectional lines N5 and N6 in Figure 4b. The difference between the display panel shown in Figures 4a and 4b and the display panel shown in Figure 1 is that, in this embodiment, there is a first gap Q between the first element portion 12 and the second element portion 13, and the orthographic projection of the first gap Q on the substrate 11 overlaps with the orthographic projection of the third element portion 14 on the substrate 11. The first element portion 12 and the second element portion 13 are located in the same active layer, for example, the active layer may include materials such as polysilicon or metal oxide. The third element portion 14 is located in the gate layer.

[0072] For example, the orthographic projection of the first via H1 on the substrate 11 is located within the orthographic projection of the active layer where the first element part 12 is located on the substrate 11, or the orthographic projection of the first via H1 on the substrate is located within the orthographic projection of the active layer where the second element part 13 is located on the substrate 11.

[0073] Figure 5a is a partial cross-sectional structural diagram of the display panel provided in the third embodiment of this application. Figure 5b is a partial cross-sectional structural diagram of the display panel provided in the fourth embodiment of this application. Figure 5c is a partial cross-sectional structural diagram of the display panel provided in the fifth embodiment of this application. The difference between the display panels shown in Figures 5a, 5b, and 5c and the display panel shown in Figure 2 is that, in the display panels shown in Figures 5a, 5b, and 5c, the first element portion 12 and the second element portion 13 are disposed in different layers.

[0074] For example, as shown in FIG5a, the film layer containing the third element portion 14 is located on the side of the film layer containing the first element portion 12 and the film layer containing the second element portion 13 that is away from the substrate 11. For example, in the direction away from the substrate 11, the film layer containing the second element portion 13, the film layer containing the first element portion 12, and the film layer containing the third element portion 14 are stacked sequentially. As another example, in the direction away from the substrate 11, the film layer containing the first element portion 12, the film layer containing the second element portion 13, and the film layer containing the third element portion 14 are stacked sequentially.

[0075] For example, an insulating layer is provided between any two adjacent elements in the film layer where the second element 13 is located, the film layer where the first element 12 is located, and the film layer where the third element 14 is located.

[0076] For example, as shown in FIG5b, the film layer containing the third element portion 14 is located on the side of the film layer containing the first element portion 12 and the film layer containing the second element portion 13 closer to the substrate 11. For example, in the direction away from the substrate 11, the film layer containing the third element portion 14, the film layer containing the second element portion 13, and the film layer containing the first element portion 12 are stacked sequentially. As another example, in the direction away from the substrate 11, the film layer containing the third element portion 14, the film layer containing the first element portion 12, and the film layer containing the second element portion 13 are stacked sequentially.

[0077] For example, as shown in FIG5c, the film layer containing the third element portion 14 is located between the film layer containing the first element portion 12 and the film layer containing the second element portion 13. For example, in the direction away from the substrate 11, the film layer containing the first element portion 12, the film layer containing the third element portion 14, and the film layer containing the second element portion 13 are stacked sequentially. As another example, in the direction away from the substrate 11, the film layer containing the second element portion 13, the film layer containing the third element portion 14, and the film layer containing the first element portion 12 are stacked sequentially.

[0078] For example, the orthographic projection of the first element portion 12 on the substrate 11 and the orthographic projection of the second element portion 13 on the substrate 11 are located on one or both sides of the orthographic projection of the third element portion 14 on the substrate 11 along the second direction y.

[0079] Figure 6a is a partial top view of the display panel provided in the sixth embodiment of this application. Figure 6b is a partial cross-sectional view of the display panel shown in Figure 6a along line N7N8. The difference between the display panels shown in Figures 6a and 6b and the display panels provided in any of the embodiments in Figures 1-5c is that, in this embodiment, the orthographic projection of the first element portion 12 on the substrate 11 and the orthographic projection of the second element portion 13 on the substrate 11 are located on one side of the orthographic projection of the third element portion 14 on the substrate 11 along the second direction y.

[0080] Figure 7a is a partial top view of the display panel provided in the seventh embodiment of this application. Figure 7b is a partial cross-sectional view of the display panel shown in Figure 7a along the N9N10 line. Referring to Figures 7a and 7b, the difference between the display panel provided in this embodiment and the display panel provided in any of the above embodiments is that, in this embodiment, the third element portion 14 is provided with a break D. The orthographic projection of the break D on the substrate 11 overlaps with the orthographic projection of the first via H1 on the substrate 11. For example, the third element portion 14 is a first trace; exemplarily, the first trace is an initialization signal line. The first trace is provided with a break D. The orthographic projection of the break D on the substrate 11 overlaps with the orthographic projection of the second connection portion 16 (and / or the first via H1) on the substrate 11. By providing the break, the obstruction of the second connection portion is reduced, thereby improving the connection effect and reducing the connection impedance. At least a portion of the second connection is exposed by the break point D, so that the doping concentration of the conductive particles in at least a portion of the second connection is increased, for example, equal to the doping concentration of the conductive particles in the source or drain region of the first transistor T4 and / or the source or drain region of the second transistor T7, and the same as the conductivity of the source or drain region of the first transistor T4 and / or the source or drain region of the second transistor T7.

[0081] Figure 8 is a first layout of a display panel according to an embodiment of this application. Figure 9a is a wiring diagram of the active layer in the layout shown in Figure 8. Figure 9b is a wiring diagram of the first conductive layer in the layout shown in Figure 8. Figure 9c is a schematic diagram of the stacked structure of the active layer and the first conductive layer in the layout shown in Figure 8. Figure 9d is a schematic diagram of the via arrangement in the layout shown in Figure 8. Figure 9e is a schematic diagram of the stacked structure of vias, the active layer, and the first conductive layer in the layout shown in Figure 8. Figure 9f is a schematic diagram of the stacked structure of the second conductive layer in the layout shown in Figure 8. Figure 9g is a schematic diagram of the stacked structure of the active layer, the first conductive layer, and the second conductive layer in the layout shown in Figure 8.

[0082] Referring to Figures 8 and 9a-9g, the display panel includes a first transistor T4, and a first element portion 12 is the active portion of the first transistor T4. And / or, the display panel also includes a second transistor T7, and a second element portion 13 is the active portion of the second transistor T7.

[0083] For example, the active portion of the first transistor T4 and the active portion of the second transistor T7 are disposed in different layers. For example, the active portions of the first transistor T4 and the active portions of the second transistor T7 are made of different or the same materials. For example, one of the active portions of the first transistor T4 and the active portions of the second transistor T7 comprises polysilicon, and the other comprises metal oxide.

[0084] The active portion of the first transistor T4 and the active portion of the second transistor T7 are disposed on the same layer, for example, the active portions of the first transistor T4 and the active portions of the second transistor T7 are made of the same material. For example, the gate of the first transistor T4, the gate of the second transistor T7, and the third element portion 14 are disposed on the same layer to reduce the number of film layers, simplify the process, and reduce costs.

[0085] For example, the first transistor T4 and the second transistor T7 may be initialization transistors.

[0086] For example, the pixel circuit 20 includes a first transistor T4 and a second transistor T7. The first element portion 12 is the active portion of the first transistor T4, and the second element portion 13 is the active portion of the second transistor T7. The first transistor T4 and the second transistor T7 have different functions.

[0087] For example, the pixel circuit 20 further includes a driving transistor T1. A first transistor T4 is used to initialize the gate, source, or drain of the driving transistor T1. For example, the first transistor T4 may be electrically connected to the gate, source, or drain of the driving transistor T1. And / or, the display panel also includes a light-emitting device (OLED). A second transistor T7 is used to initialize the first electrode of the light-emitting device OLED. For example, the light-emitting device OLED is located on the side of the pixel circuit opposite to the substrate 11.

[0088] For example, the display panel further includes a second connecting portion 16, which is connected between the first element portion 12 and the second element portion 13. The overlapping area of ​​the orthographic projection of the second connecting portion 16 on the substrate 11 and the orthographic projection of the third element portion 13 on the substrate 11 overlaps with the orthographic projection of the first connecting portion 15 on the substrate 11. The first element portion 12, the second element portion 13, and the second connecting portion 16 are located in the same active layer 19.

[0089] For example, the doping concentration of conductive particles in the second connection portion 16 is less than the doping concentration of conductive particles in the source or drain region of the active portion of the first transistor T4. And / or, the conductivity of the second connection portion 16 is less than the conductivity of the source or drain region of the active portion of the first transistor T4. Due to the obstruction of the third element portion 13, the doping concentration of conductive particles in the second connection portion 16 is lower than the doping concentration of conductive particles in the source or drain region of the active portion of the first transistor T4. The conductivity of the second connection portion 16 is less than the conductivity of the source or drain region of the active portion of the first transistor T4. If the first via H1 and the first connection portion 15 are not provided, the connection impedance between the active portion of the first transistor T4 and the active portion of the second transistor T7 will be large. Therefore, by providing the first via H1 and the first connection portion 15, the active portion of the first transistor T4 and the active portion of the second transistor T7 are electrically connected to the third element portion 14 (i.e., the first trace, the initialization signal line), and the electrical connection impedance is reduced.

[0090] For example, the doping concentration of the conductive particles in the second connection portion 16 is lower than the doping concentration of the conductive particles in the source or drain region of the active portion of the second transistor T7. And / or, the conductivity of the second connection portion 16 is lower than the conductivity of the source or drain region of the active portion of the second transistor T7. Due to the shielding of the third element portion 13, the doping concentration of the conductive particles in the second connection portion 16 is lower than the doping concentration of the conductive particles in the source or drain region of the active portion of the second transistor T7, and the conductivity of the second connection portion 16 is lower than the conductivity of the source or drain region of the active portion of the second transistor T7.

[0091] For example, in the same transistor, the part where the scan line overlaps with the active part can be the gate, and the part where the active part overlaps with the scan line can be the channel region. The source region and / or drain region are located on both sides of the channel region.

[0092] Figure 10 is a circuit diagram of the pixel circuits included in the layout shown in Figure 8. In conjunction with Figures 8, 9a-9g, and 10, the display panel also includes a plurality of pixel circuits 20 arranged in an array, each pixel circuit 20 including a first element section 12 and a second element section 13.

[0093] For example, in two adjacent pixel circuits 20 located in the same column, a first element portion 12 in one pixel circuit 20 and a second element portion 13 in the other pixel circuit 20 are electrically connected to a third element portion 14 via a first connection portion 15 (e.g., via a first via H1 and the first connection portion 15). The third element portion 14 extends along the row direction, and the row direction (which may be parallel to the first direction x) and the column direction (which may be parallel to the second direction y) intersect.

[0094] For example, the third element section 14 is the initialization signal line Ref.

[0095] For example, the pixel circuit also includes a data write transistor T2. The data write transistor T2 is connected between the data line Data and the first terminal of the drive transistor T1. The gates of the second transistor T7 and the data write transistor T2 are electrically connected to the first scan line S3.

[0096] For example, the first scan line S3 and the initialization signal line Ref are set on the same layer; and / or, the data line Data and the first connection part 15 are set on the same layer.

[0097] For example, two structures set in the same layer can be obtained by patterning the same film layer, which simplifies the process and the number of film layers.

[0098] For example, the first scan line S3 and the initialization signal line Ref extend along the first direction x.

[0099] For example, each signal line can extend along the corresponding direction in a straight line, a broken line, a curve, a tree-like shape, an irregular shape, or other similar manner.

[0100] For example, the gate of the first transistor T4 is electrically connected to the second scan line S1, for instance, the second scan line S1 is set on the same layer as the initialization signal line Ref.

[0101] For example, the second scan line S1 and the initialization signal line Ref extend along the first direction x.

[0102] For example, the initialization signal line Ref is located between the first scan line S3 and the second scan line S1.

[0103] For example, the gate of the driving transistor T1 is located on the same layer as the initialization signal line Ref.

[0104] For example, the pixel circuit also includes a storage capacitor C, and the gate of the driving transistor T1 is reused as the first plate of the storage capacitor C.

[0105] For example, the display panel also includes a light emission control signal line Em. The first scan line S3 is located between the light emission control signal line Em and the initialization signal line Ref. For example, the light emission control signal line Em is located on the side of the first scan line S3 away from the initialization signal line Ref.

[0106] For example, the pixel circuit also includes a first light-emitting control transistor T6, connected between the second electrode of the driving transistor T1 and the first electrode of the light-emitting device OLED. The gate of the first light-emitting control transistor T6 is electrically connected to the light-emitting control signal line Em.

[0107] For example, the data write transistor T2 is turned on during a write frame to transmit the data voltage on the data line Data to the drive transistor T1; and turned on during a hold frame to transmit the bias voltage on the data line Data to the drive transistor T1.

[0108] For example, the pixel circuit also includes a threshold compensation transistor T3 connected between the gate and the second terminal of the driving transistor T1. The gate of the threshold compensation transistor T3 is electrically connected to the third scan line S2.

[0109] For example, the second scan line S1 is located between the initialization signal line Ref and the third scan signal line S2.

[0110] For example, the display panel also includes a first power line VDD, which is disposed on the same layer as the first connection portion 15. The first power line VDD extends along the second direction y. By providing a first via H1, the film layer space occupied by the first connection portion 15 is reduced, thereby ensuring the width of the first power line VDD on the same layer as the first connection portion 15, or it is beneficial to increase the width of the first power line VDD, reduce the line impedance of the first power line VDD, and thus improve the display uniformity.

[0111] For example, the first power line VDD is electrically connected to the pixel circuit 20.

[0112] For example, in the first direction x, the first power line VDD and the first connection portion 15 are arranged alternately.

[0113] For example, at least a portion of the first power line VDD is multiplexed as the second plate of the storage capacitor C. For instance, a capacitor dielectric layer may be disposed between the first and second plates of the storage capacitor C. The orthographic projections of the first and second plates of the storage capacitor C onto the substrate overlap.

[0114] For example, the data line Data extends along the second direction y, and the first power line VDD and the data line Data are arranged alternately along the first direction x. For example, at least one of the first power line VDD and the data line Data can extend along the second direction y in a straight line, a broken line, a curve, a tree-like shape, an irregular shape, etc.

[0115] For example, in the first direction x, the first connection portion 15 is located between the first power line VDD and the data line Data.

[0116] For example, the pixel circuit further includes a second light-emitting control transistor T6, which is connected between the first terminal of the driving transistor T1 and the first power supply line VDD. The gate of the second light-emitting control transistor T6 is electrically connected to the light-emitting control signal line Em, which is disposed on the same layer as the third element section 14.

[0117] For example, the light emission control signal line Em and the third element portion 14 extend along the first direction x.

[0118] For example, as shown in FIG9a, the active portion T4_S of the first transistor and the active portion T3_S of the threshold compensation transistor are connected in the orthographic projection of the substrate to form a groove shape, and the bottom and opening of the groove shape are arranged along the first direction x.

[0119] For example, the first transistor T4 includes at least two first sub-transistors connected in series. For instance, the first transistor T4 may be a dual-gate transistor, including first sub-transistors T4-1 and T4-2 connected in series. And / or, the threshold compensation transistor T3 includes at least two second sub-transistors connected in series. For instance, the threshold compensation transistor T3 may be a dual-gate transistor, including second sub-transistors T3-1 and T3-2 connected in series. This configuration reduces leakage current at the gate of the driving transistor, improving low-frequency flicker.

[0120] For example, as shown in Figures 8, 9a-9g, and 10, the display panel further includes a second via H2 that exposes the first terminal of the data writing transistor T2. The data line Data fills the second via H2 and contacts the first terminal of the data writing transistor T2, for example, through an electrical contact. The display panel also includes a first scan line S3 electrically connected to the gate of the data writing transistor T2. The orthographic projection of the second via H2 onto the substrate 11 lies between the orthographic projection of the first scan line S3 onto the substrate 11 and the orthographic projection of the initialization signal line Ref onto the substrate 11. For example, the second terminal of the data writing transistor T2 is electrically connected to the first terminal of the driving transistor T1.

[0121] For example, as shown in Figures 8, 9a-9g, and 10, the display panel further includes a third via H3 that exposes the second electrode of the first light-emitting control transistor T6. The display panel also includes a third connection portion 17 that fills the third via H3. For example, the third connection portion 17 is on the same layer as the power signal line VDD. The third connection portion 17 connects to the first electrode of the light-emitting device OLED, such as the anode. The orthogonal projection of the third via H3 onto the substrate 11 lies between the orthogonal projection of the first scan line S3 onto the substrate 11 and the orthogonal projection of the light-emitting control signal line Em onto the substrate 11. For example, the first electrode of the first light-emitting control transistor T6 may be electrically connected to the second electrode of the driving transistor T1.

[0122] For example, as shown in Figures 8, 9a-9g, and 10, the display panel further includes a fourth via H4 that exposes the first terminal of the second light-emitting control transistor T5. The power signal line VDD fills the fourth via H4 and contacts the first terminal of the second light-emitting control transistor T5. The orthogonal projection of the fourth via H4 onto the substrate 11 lies between the orthogonal projection of the first scan line S3 onto the substrate 11 and the orthogonal projection of the light-emitting control signal line Em onto the substrate 11. For example, the second terminal of the second light-emitting control transistor T5 is electrically connected to the first terminal of the driving transistor T1.

[0123] For example, as shown in Figures 8, 9a-9g, and 10, the display panel further includes a fifth via H5 and a sixth via H6. The fifth via H5 exposes the second terminal of the data writing transistor T2, and the sixth via H6 exposes the first terminal of the driving transistor T1. The display panel also includes a fourth connection portion 18, which fills the fifth via H5 and the sixth via H6 to connect the second terminal of the data writing transistor T2 and the first terminal of the driving transistor T1. For example, the fourth connection portion 18 is on the same layer as the power signal line VDD. The orthographic projection of the fifth via H5 on the substrate 11 is located between the orthographic projection of the first scan line S3 on the substrate 11 and the orthographic projection of the light emission control signal line Em on the substrate 11. The orthographic projection of the sixth via H6 on the substrate 11 is located on the side of the orthographic projection of the light emission control signal line Em on the substrate 11 away from the orthographic projection of the first scan line S3 on the substrate 11.

[0124] For example, referring to Figures 8, 9a-9g, and 10, the first scan line S3 includes a third trace segment S31 and a fourth trace segment S32 arranged along the extension direction of the first scan line S3. The distance D1 between the third trace segment S31 and the initialization signal line Ref is less than the distance D2 between the fourth trace segment S32 and the initialization signal line Ref, and / or, the distance D3 between the third trace segment S31 and the light emission control signal line Em is greater than the distance D4 between the fourth trace segment S32 and the light emission control signal line Em.

[0125] For example, the first via H1 is directly opposite the third trace segment S31.

[0126] For example, the orthographic projection of the second via H2 on the substrate 11 is located between the orthographic projection of the fourth trace segment S32 on the substrate 11 and the orthographic projection of the initialization signal line Ref on the substrate 11.

[0127] For example, the orthographic projection of the third via H3 on the substrate 11 is located between the orthographic projection of the third trace segment S31 on the substrate 11 and the orthographic projection of the light emission control signal line Em on the substrate 11.

[0128] For example, the orthographic projection of the fourth via H4 on the substrate 11 is located between the orthographic projection of the third trace segment S31 on the substrate 11 and the orthographic projection of the light emission control signal line Em on the substrate 11.

[0129] For example, the orthographic projection of the fifth via H5 on the substrate 11 is located between the orthographic projection of the fourth trace segment S32 on the substrate 11 and the orthographic projection of the light emission control signal line Em on the substrate 11.

[0130] For example, along the extension direction of the initialization signal line Ref, for example, the third via H3, the fourth via H4 and the fifth via H5 are arranged sequentially along the first direction x.

[0131] Figure 11 is a second layout of a display panel provided in an embodiment of this application. Comparing Figure 11 and Figure 8, it can be seen that the display panel provided in this embodiment further includes a first scanning circuit 40 based on the display panel shown in Figure 8. The first scanning circuit 40 includes multiple levels of first shift registers 41, and the output terminal of at least one of the first shift registers 41 is electrically connected to the gate of the corresponding first transistor T4 and the gate of the threshold compensation transistor T3. For example, the multiple levels of first shift registers 41 can be cascaded.

[0132] For example, the first transistor T4 and the threshold compensation transistor T3, which are electrically connected to the same first shift register 41, are located in different pixel circuits 20.

[0133] For example, in two adjacent rows of pixel circuits 20, the first transistor T4 in one row of pixel circuits 20 and the threshold compensation transistor T3 in the other row of pixel circuits 20 are electrically connected to the same first shift register 41.

[0134] For example, the first transistor T4 and the threshold compensation transistor T3 in the same pixel circuit 20 are electrically connected to different first shift registers 41.

[0135] Optionally, the display panel may also include a second scanning circuit electrically connected to the gate of the data writing transistor T2. The second scanning circuit may include multiple stages of second shift registers.

[0136] Figure 12 is a wiring diagram of the first conductive layer in the layout shown in Figure 8, provided by another embodiment of this application. Comparing Figure 12 and Figure 9b, it can be seen that the difference between the wiring of the first conductive layer provided in this embodiment and the wiring of the first conductive layer provided in Figure 9b is that, in this embodiment, the initialization signal line Ref is provided with a break D. Referring to Figures 12 and 9a, 9c-9g, the orthogonal projection of the break D on the substrate 11 overlaps with the orthogonal projection of the first via H1 (or the first connection portion 15) on the substrate 11.

[0137] Figure 13 is a cross-sectional structural diagram of a display panel including the layout shown in Figure 8 according to an embodiment of this application. Referring to Figures 13 and 8, the display panel typically includes various electrically connected signal lines, pixel circuits 20, and an OLED light-emitting device. The signal lines provide driving signals to the pixel circuits, and the pixel circuits 20 drive the OLED light-emitting device to emit light at a predetermined brightness under the action of the driving signals. From the perspective of the film layer structure, the display panel includes: a substrate 11; and an active layer 19, a first insulating layer 17, a first conductive layer M1 (which may be a metal layer), a second insulating layer 18, and a second conductive layer M2 (which may be a metal layer) sequentially stacked on the substrate 11. The OLED light-emitting device is located on the side of the second conductive layer M2 facing away from the substrate 11. The first conductive layer M1 (which may be a metal layer) may include a first scan line S3, a second scan line S1, a third scan line S2, a light emission control signal line Em, an initialization signal line Ref, the gate of a driving transistor T1, etc. The second conductive layer M2 may include a first power supply line VDD, a data line Data, etc.

[0138] In some embodiments, substrate 11 may be a rigid substrate, such as a glass substrate, or substrate 11 may be a flexible substrate, such as an organic material including polyimide.

[0139] In some embodiments, substrate 11 may comprise an organic resin material such as epoxy resin, triazine, silicone resin, or polyimide. For example, substrate 11 may be an FR4 type printed circuit board (PCB) or a flexible PCB that is easily deformable.

[0140] In some embodiments, substrate 11 may include a ceramic material such as silicon nitride, aluminum nitride, or aluminum oxide, or may include a metal or metal compound. For example, substrate 11 may be a metal core PCB (MCPCB) or a metal-base copper-clad laminate (MCCL).

[0141] The first insulating layer 17 and the second insulating layer 18 may be made of the same or different materials. For example, at least one of the first insulating layer 17 and the second insulating layer 18 may be made of at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0142] The first conductive layer M1 and the second conductive layer M2 may be made of the same or different materials. For example, the first conductive layer M1 may be made of molybdenum. The second conductive layer M2 may have a Ti / Al / Ti triple-layer structure.

[0143] OLEDs can be organic light-emitting diodes (OLEDs), micro light-emitting diodes (Micro LEDs), quantum dot light-emitting diodes (QLEDs), etc. OLEDs can also emit light in various colors, such as red (R), green (G), and blue (B).

[0144] As shown in Figure 13, the OLED light-emitting device includes a first electrode 21, a light-emitting layer 22, and a second electrode 23 sequentially stacked along a direction gradually moving away from the substrate 11. Exemplarily, the first electrode 21 is the anode, and the second electrode 23 is the cathode. Alternatively, the first electrode 21 is the cathode, and the second electrode 23 is the anode. Exemplarily, the OLED may further include at least one of a hole injection layer, a hole transport layer, and an electron blocking layer located between the anode and the light-emitting layer 22, and at least one of an electron injection layer, an electron transport layer, and a hole blocking layer located between the cathode and the light-emitting layer 22. Exemplarily, one or more of the hole injection layer, hole transport layer, electron blocking layer, electron transport layer, and electron injection layer in all OLED light-emitting devices may be common layers connected together, and the light-emitting layers of adjacent OLEDs may have a small overlap or may be isolated from each other.

[0145] In some embodiments, as shown in FIG13, the display panel further includes a third insulating layer 33 and a pixel defining layer 34. The third insulating layer 33 is located between the second conductive layer M2 and the light-emitting device OLED. The pixel defining layer 34 is located on the side of the second conductive layer M2 facing away from the substrate 11, and the pixel defining layer 34 encloses a pixel opening. At least a portion of the light-emitting device OLED is located within the pixel opening. For example, the pixel opening exposes a portion of the first electrode 21, the light-emitting layer 22 is located within the pixel opening, and the second electrode 22 is a common layer.

[0146] Figure 14 shows the driving timing of a pixel circuit according to an embodiment of this application. As shown in Figure 14, the driving process of the display panel includes writing frames and holding frames.

[0147] The write frame includes:

[0148] In the first reset phase t1, such as the gate reset phase, the light emission control signal em is at the off level, such as a high level; the second scan signal s2 and the third scan signal s3 are both at the off level, such as a high level; and the first scan signal s1 is at the on level, such as a low level, which turns on the first transistor T1. The data writing transistor T2, the threshold compensation transistor T3, the first transistor T4, the second light emission control transistor T5, the first light emission control transistor T6, and the second transistor T7 are all turned off, so that the gate of the driving transistor T1 can be reset using the initialization signal Vref.

[0149] In the data writing phase t2, the second reset phase (e.g., the anode reset phase) may overlap with the data writing phase. The first scan signal s1 becomes off (e.g., high level), and the second scan signal s2 and the third scan signal s3 become on (e.g., low level), turning on the data writing transistor T2, the threshold compensation transistor T3, and the second transistor T7, while turning off the first transistor T1, the first transistor T4, the second light-emitting control transistor T5, and the first light-emitting control transistor T6. Specifically, during the data writing phase, the data writing transistor T2 and the threshold compensation transistor T3 are on, used to compensate the threshold voltage of the driving transistor T1 to the data signal after the data signal in the data line Data passes through the on-state driving transistor and threshold compensation transistor T3, so that the threshold-compensated data signal is written to the gate of the driving transistor T1. In the second reset phase, the second transistor T7 is on, used to reset the first electrode (e.g., the anode) of the OLED using the initialization signal Vref. The second reset phase of the written frame may not overlap with the data writing phase. The second reset phase of the written frame may also overlap with or not overlap with the first reset phase.

[0150] During the light-emitting stage t3, the second scan signal s2 and the third scan signal s3 become off level, for example, high level, and the light-emitting control signal em becomes on level, for example, low level, causing the data writing transistor T2, the threshold compensation transistor T3, the first transistor T4 and the second transistor T7 to be turned off, and the second light-emitting control transistor T5 and the first light-emitting control transistor T6 to be turned on, which are used to control the driving current generated by the driving transistor T1 to drive the light-emitting device to emit light.

[0151] Hold frames include:

[0152] In the third reset phase t4, the light emission control signal em, the first scan signal s1, and the second scan signal s2 are all at off levels (e.g., high level), while the third scan signal s3 is at on level (e.g., low level), turning on the data writing transistor T2 and the second transistor T7. The first transistor T1, threshold compensation transistor T3, first transistor T4, second light emission control transistor T5, and first light emission control transistor T6 are all off. During this third reset phase, the data writing transistor T2 is turned on to transmit the bias voltage Vref3 in the data line Data to the driving transistor T1, thereby improving stress in the driving transistor. In the second reset phase (which can overlap with the third reset phase of the hold frame), the second transistor T7 is turned on to reset the first electrode (e.g., the anode) of the OLED using the initialization signal Vref. The second reset phase of the hold frame may also not overlap with the third reset phase.

[0153] The light-emitting phase t5 of the holding frame is the same as or similar to the light-emitting phase of the writing frame, and will not be described in detail here.

[0154] Figure 15a is a circuit diagram of a pixel circuit provided in another embodiment of this application. Figure 15b is a third layout diagram of a display panel provided in an embodiment of this application. As shown in Figure 15b, the display panel further includes a plurality of pixel circuits 20 arranged in an array, each pixel circuit 20 including a first element portion 12 and / or a second element portion 13. Exemplarily, the first element portion 12 is the active portion of a first transistor T4, and the second element portion 13 is the active portion of a second transistor T7.

[0155] In two adjacent pixel circuits 20 located in the same column, a first element portion 12 in one pixel circuit 20 and a second element portion 13 in the other pixel circuit 20 are electrically connected to a third element portion 14 via a first connection portion 15 (e.g., via a first via H1 and the first connection portion 15). The third element portion 14 extends along the row direction, intersecting the row and column directions. The first element portion 12 in one pixel circuit 20 and the second element portion 13 in the other pixel circuit 20 have the same function. For example, the third element portion 14 is an initialization signal line Ref, which may include a first initialization signal line Ref1 and a second initialization signal line Ref2. In this case, the third element portion 14 can be either the first initialization signal line Ref1 or the second initialization signal line Ref2. For example, the first initialization signal line Ref1 can be used to transmit a first initialization voltage Vref1. For example, the second initialization signal line Ref2 can be used to transmit a second initialization voltage Vref2.

[0156] For example, the pixel circuit 20 includes a first transistor T4, at least one second element portion 13 and at least one first element portion 12 are active portions of the first transistor T4 in different pixel circuits 20, and the pixel circuit 20 also includes a driving transistor T1, the first transistor T4 being used to initialize the gate, source or drain of the driving transistor T1.

[0157] For example, the display panel includes multiple first pixel circuit sub-units, each of which includes two adjacent pixel circuits 20 located in the same column. Within the same first pixel circuit sub-unit, a first transistor T4 in one pixel circuit 20 and a first transistor T4 in another pixel circuit 20 are electrically connected to a third element section 14 (e.g., a first initialization signal line Ref1) via a first connection portion 15 (e.g., via a first via H1 and the first connection portion 15), as shown in FIG15b.

[0158] The difference between the layout shown in Figure 15b and the layout shown in Figure 8 is that, in this embodiment, the active layers of two adjacent pixel circuits 20 located in the same column are arranged in a mirror-symmetric manner. For example, a pixel circuit 20 includes seven transistors, which are denoted as Ti, and i is 1 to 7. The active portions of the i-th transistor in two adjacent pixel circuits 20 located in the same column are arranged in a mirror-symmetric manner. For example, in two adjacent pixel circuits 20 located in the same column, the active portions of the first transistor T1 in one pixel circuit 20 and the active portions of the first transistor T1 in the other pixel circuit 20 are arranged in a mirror-symmetric manner; the active portions of the second transistor T2 in one pixel circuit 20 and the active portions of the second transistor T2 in the other pixel circuit 20 are arranged in a mirror-symmetric manner, and so on, for other transistors.

[0159] For example, the pixel circuit 20 includes a first transistor T4 and a second transistor T7. The first element portion 12 is the active portion of the first transistor T4, and the second element portion 13 is the active portion of the second transistor T7. The active portions of the first transistor T4 and the active portions of the second transistor T7 are electrically connected to the same initialization signal line, or different initialization signal lines.

[0160] For example, as shown in FIG15b, the initialization signal line Ref includes a first initialization signal line Ref1 and a second initialization signal line Ref2 that are isolated from each other and alternately arranged along the column direction (which may be parallel to the second direction y). The active part of the first transistor T4 is electrically connected to the first initialization signal line Ref1, and the active part of the second transistor T7 is electrically connected to the second initialization signal line Ref2. The voltages of the first initialization signal line Ref1 and the second initialization signal line Ref2 may be different.

[0161] Figure 16 is a fourth layout of a display panel provided in an embodiment of this application. The difference between the layout shown in Figure 16 and the layout shown in Figure 15b is that, in this embodiment, the pixel circuit 20 includes a second transistor T7, and at least one second element portion 13 and at least one first element portion 12 are active portions of the second transistor T7 in different pixel circuits 20. The display panel also includes a light-emitting device (OLED), and the second transistor T7 is used to initialize the first electrode of the OLED.

[0162] For example, the display panel includes multiple second pixel circuit sub-units, each including two adjacent pixel circuits 20 located in the same column. Within the same second pixel circuit sub-unit, a second transistor T7 in one pixel circuit 20 and a second transistor T7 in another pixel circuit 20 are electrically connected to a third element section 14 (e.g., a second initialization signal line Ref2) via a first connection portion 15 (e.g., via a first via H1 and the first connection portion 15), as shown in FIG16.

[0163] Figure 17 is a fifth layout of a display panel provided in an embodiment of this application. The difference between the layout shown in Figure 17 and the layouts shown in Figures 16 and 15b is that, in this embodiment, among the three adjacent pixel circuits 20 located in the same column, the first transistor T4 in the pixel circuit 20 on one side and the first transistor T4 in the middle pixel circuit 20 are electrically connected to the third element section 14 (e.g., the first initialization signal line Ref1) through a first connection portion 15 (e.g., through the first via H1 and the first connection portion 15); the second transistor T7 in the pixel circuit 20 on the other side and the second transistor T7 in the middle pixel circuit 20 are electrically connected to the third element section 14 (e.g., the second initialization signal line Ref2) through the first connection portion 15 (e.g., through the first via H1 and the first connection portion 15), as shown in Figure 17.

[0164] Figure 18 is a sixth layout of a display panel according to an embodiment of this application. The difference between the display panel shown in Figure 18 and the display panel shown in Figure 8 is that, in this embodiment, the display panel includes multiple pixel circuit groups 201, and each pixel circuit group includes two adjacent pixel circuits located in the same row. Within the same pixel circuit group, the first element portion 12 of one pixel circuit 20 and the second element portion 13 of another pixel circuit 20 have the same function and are electrically connected to the third element portion 14 via a first connection portion 15 (e.g., via a first via H1 and the first connection portion 15).

[0165] For example, pixel circuit 20 includes a first transistor T4, at least one second element portion 13 and at least one first element portion 12 being active portions of the first transistor T4 in different pixel circuits 20.

[0166] Specifically, in two adjacent pixel circuits located in the same row within the same pixel circuit group, the active portion of the first transistor T4 in one pixel circuit 20 and the active portion of the first transistor T4 in the other pixel circuit 20 are electrically connected to the third element portion 14 (e.g., the first initialization signal line Ref1) via the first connection portion 15 (e.g., via the first via H1 and the first connection portion 15), as shown in FIG18.

[0167] For example, the pixel circuit 20 includes a second transistor T7, and at least one second element portion 13 and at least one first element portion 12 are active portions of the second transistor T7 in different pixel circuits 20.

[0168] Specifically, in two adjacent pixel circuits located in the same row within the same pixel circuit group, the active portion of the second transistor T7 in one pixel circuit 20 and the active portion of the second transistor T7 in the other pixel circuit 20 are electrically connected to the third element portion 14 (e.g., the second initialization signal line Ref2) through the first connection portion 15 (e.g., through the first via H1 and the first connection portion 15), as shown in FIG18.

[0169] In some embodiments, the active layers of two adjacent pixel circuits 20 located in the same row are arranged in a mirror-symmetric configuration.

[0170] In some embodiments, the active portion of the first transistor T4 and the active portion of the second transistor T7 are electrically connected to the same initialization signal line, or to different initialization signal lines Ref.

[0171] Figure 19 is a seventh layout of a display panel according to an embodiment of this application. The difference between the layout shown in Figure 19 and the layout shown in Figure 8 is that, in this embodiment, the display panel includes multiple pixel circuit groups, and each pixel circuit group includes two adjacent pixel circuits 20 located in the same row. Within the same pixel circuit group, a first element portion 12 in one pixel circuit 20 and a second element portion 13 in another pixel circuit 20 are electrically connected to a third element portion via a first connection portion 15 (e.g., via a first via H1 and the first connection portion 15). Two adjacent pixel circuit groups located in the same column are electrically connected to the same third element portion located between the two pixel circuit groups via the same first connection portion 15 (e.g., via the same first via H1 and the same first connection portion 15).

[0172] For example, pixel circuit 20 includes a first transistor T4. Second element portion 13 and first element portion 12 are active portions of the first transistor T4 in different pixel circuits 20. For example, a display panel includes one or more first pixel circuit units, each comprising two adjacent pixel circuit groups located in the same column. In the same first pixel circuit unit, the active portions of four first transistors T4 in two adjacent pixel circuit groups located in the same column are electrically connected to the same third element portion (e.g., a first initialization signal line Ref1) via the same first connection portion 15 (e.g., via the same first via H1 and the same first connection portion 15).

[0173] Figure 20 is an eighth layout of a display panel according to an embodiment of this application. The difference between the layout shown in Figure 20 and the layout shown in Figure 19 is that, in this embodiment, the pixel circuit 20 includes a second transistor T7. The second element portion 13 and the first element portion 12 are active portions of the second transistor T7 in different pixel circuits 20. For example, the display panel includes one or more second pixel circuit units, each including two adjacent pixel circuit groups located in the same column. In the same second pixel circuit unit, the active portions of four second transistors T7 in two adjacent pixel circuit groups located in the same column are electrically connected to the same third element portion (e.g., the second initialization signal line Ref2) through the same first connection portion 15 (e.g., through the same first via H1 and the same first connection portion 15).

[0174] For example, in two adjacent pixel circuit groups located in the same column, the active portions of the two first transistors T4 and the active portions of the two second transistors T7 are electrically connected to the same third element portion (e.g., initialization signal line) located between the two pixel circuit groups through the same first connection portion 15 (e.g., through the same first via H1 and the same first connection portion 15).

[0175] Figure 21 is a ninth layout of a display panel provided in an embodiment of this application. The difference between the layout shown in Figure 21 and the layouts shown in Figures 20 and 19 is that, in this embodiment, in three adjacent pixel circuit groups in the column direction, the first transistor T4 of the adjacent pixel circuit 20 in the pixel circuit group on one side and the first transistor T4 of the pixel circuit 20 in the middle pixel circuit group are electrically connected to the third element section 14 (e.g., the first initialization signal line Ref1) through the first connection portion 15 (e.g., through the first via H1 and the first connection portion 15); the second transistor T7 of the pixel circuit 20 in the pixel circuit group on the other side and the second transistor T7 of the pixel circuit 20 in the middle pixel circuit group are electrically connected to the same third element section 14 (e.g., the second initialization signal line Ref2) through the same first connection portion 15 (e.g., through the same first via H1 and the same first connection portion 15).

[0176] The enlarged top and cross-sectional views of the first connecting portion 15 in Figures 8, 11, 15b to 17, and 19 to 21 can be found in Figures 1 to 5c, 7a, and 7b. The enlarged top and cross-sectional views of the first connecting portion 15 in Figure 18 can be found in Figures 6a and 6b.

[0177] Optionally, the pixel circuit may include one or more of a first initialization transistor Ta, a second initialization transistor Tb, and a third initialization transistor Tc, as shown in Figures 22 and 23. The first initialization transistor Ta may be electrically connected to the gate of the driving transistor T1 and may be connected to a first initialization voltage Vref1. The first initialization transistor Ta can be used to initialize the gate of the driving transistor T1. The second initialization transistor Tb may be electrically connected to the first terminal (e.g., the source) of the driving transistor T1 and may be connected to a second initialization voltage Vref2. The second initialization transistor Tb can be used to initialize the first terminal (e.g., the source) of the driving transistor T1. The third initialization transistor Tc may be electrically connected to the second terminal (e.g., the drain) of the driving transistor T1 and may be connected to a third initialization voltage Vref3. The third initialization transistor Tc can be used to initialize the second terminal (e.g., the drain) of the driving transistor T1. For example, one or more first transistors T4 may be the first initialization transistor Ta. And / or, one or more first transistors T4 may be the second initialization transistor Tb. And / or, one or more first transistors T4 may be the third initialization transistor Tc. And / or, for example, one or more second transistors T7 can be the first initialization transistor Ta. And / or, for example, one or more second transistors T7 can be the second initialization transistor Tb. And / or, for example, one or more second transistors T7 can be the third initialization transistor Tc. And / or, for example, one or more initialization signal lines ref can be used to transmit the first initialization voltage Vref1. And / or, for example, one or more initialization signal lines ref can be used to transmit the second initialization voltage Vref2. And / or, for example, one or more initialization signal lines ref can be used to transmit the third initialization voltage Vref3. And / or, for example, the first initialization signal line ref1 can be used to transmit one of the first initialization voltage Vref1, the second initialization voltage Vref2, and the third initialization voltage Vref3, and the second initialization signal line ref2 can be used to transmit the other one of the first initialization voltage Vref1, the second initialization voltage Vref2, and the third initialization voltage Vref3. The connection method between the transistors and the scan lines, as well as the channel type of the transistors, can be set as needed. For example, the first initialization transistor Ta can be an N-type transistor or a P-type transistor. For example, the second initialization transistor Tb can be an N-type transistor or a P-type transistor. For example, the third initialization transistor Tc can be an N-type transistor or a P-type transistor.

[0178] The second aspect of this application provides another display panel. FIG24c is a tenth layout of a display panel provided in an embodiment of this application. The cross-sectional view of the display panel shown in FIG24b can be the cross-sectional view corresponding to the cross-sectional lines N11 and N12 in FIG24a. The difference between the display panel shown in FIG24c and the display panel provided in any of the above embodiments is that, in this embodiment, referring to FIG24a, 24b, and 24c, the display panel includes a plurality of first vias H1 and a plurality of first connecting portions 15. At least one first via H1 exposes at least a portion of the surface of the third element portion 14 away from the substrate 11 and at least a portion of the surface of the first element portion 12 away from the substrate 11. At least one first via H1 exposes at least a portion of the surface of the third element portion 14 away from the substrate 11 and at least a portion of the surface of the second element portion 13 away from the substrate 11. The plurality of first connecting portions 15 fill the corresponding first vias H1, and the first connecting portions 15 electrically connecting the third element portion 14 and the first element portion 12 are spaced apart from the first connecting portions 15 electrically connecting the third element portion 14 and the second element portion 13.

[0179] In some embodiments, the display panel further includes a plurality of pixel circuits 20 arranged in an array, wherein the pixel circuits 20 include a first element portion 12 and / or a second element portion 13.

[0180] In some embodiments, the display panel includes a plurality of pixel circuit groups, each pixel circuit group including two adjacent pixel circuits 20 located in the same row. Within the same pixel circuit group, a first element portion 12 in one pixel circuit 20 and a second element portion 13 in another pixel circuit 20 are electrically connected to a third element portion 14 via a first connection portion 15 (e.g., via a first via H1 and the first connection portion 15). The third element portion 14 extends along the row direction, and the row direction intersects with the column direction.

[0181] In some embodiments, the pixel circuit 20 includes a first transistor T4, and at least one second element portion 13 and at least one first element portion 12 are active portions of the first transistor T4 in different pixel circuits 20. The pixel circuit 20 also includes a driving transistor T1, and the first transistor T4 is used to initialize the gate, source, or drain of the driving transistor T1.

[0182] And / or, the pixel circuit 20 includes a second transistor T7, at least one second element portion 13 and at least one first element portion 12 being active portions of the second transistor T7 in different pixel circuits 20. The display panel also includes a light-emitting device (OLED), and the second transistor T7 is used to initialize the first electrode of the light-emitting device OLED.

[0183] In some embodiments, the third element 14 is an initialization signal line Ref.

[0184] In some embodiments, the initialization signal line Ref is located at the gate layer of the first transistor T4 and / or the gate layer of the second transistor T7.

[0185] In some embodiments, the active layers of two adjacent pixel circuits 20 located in the same row are arranged in a mirror-symmetric configuration.

[0186] In some embodiments, the active portion of the first transistor T4 and the active portion of the second transistor T7 are electrically connected to the same initialization signal line Ref, or different initialization signal lines Ref.

[0187] In some embodiments, the initialization signal line Ref includes a first initialization signal line Ref1 and a second initialization signal line Ref2 that are isolated from each other and alternately arranged in the column direction. The active portion of the first transistor T4 is electrically connected to the first initialization signal line Ref1, and the active portion of the second transistor T7 is electrically connected to the second initialization signal line Ref2.

[0188] For example, in the same pixel circuit group, the active part of the first transistor T4 in one pixel circuit 20 and the active part of the first transistor T4 in another pixel circuit 20 are electrically connected to the third element part 14 (e.g., the first initialization signal line Ref1) through two first connection parts 15 (e.g., through two first vias H1 and two first connection parts 15), as shown in FIG24c.

[0189] For example, in the same pixel circuit group, the active part of the second transistor T7 in one pixel circuit 20 and the active part of the second transistor T7 in another pixel circuit 20 are electrically connected to the third element part 14 (e.g., the second initialization signal line Ref2) through two first connection parts 15 (e.g., through two first vias H1 and two first connection parts 15), as shown in FIG24c.

[0190] The display panel provided in this embodiment and the display panels provided in any of the above embodiments belong to the same inventive concept. Technical details not described in this embodiment can be found in the relevant embodiments described above, and will not be repeated here. This embodiment can be combined with some or all of the features in the above embodiments, and will not be repeated here.

[0191] This application provides a substrate. Referring to FIG1, the substrate includes a substrate 11, a first element portion 12, a second element portion 13, a third element portion 14, a first via H1, and a first connection portion 15. The first element portion 12 is located on the substrate 11. The second element portion 13 is located on the substrate 11. The third element portion 14 is located on the substrate 11. The third element portion 14 and the first element portion 12 are disposed in different layers, and the third element portion 14 and the second element portion 13 are disposed in different layers. The first via H1 exposes at least a portion of the surface of the third element portion 14 away from the substrate 11, at least a portion of the surface of the first element portion 12 away from the substrate 11, and at least a portion of the surface of the second element portion 13 away from the substrate 11. The first connection portion 15 fills the first via H1. The first connection portion 15 is electrically connected to the third element portion 14 and the second element portion 13.

[0192] The substrate provided in this application embodiment can be any of the display panels provided in the above embodiments, or it can be other substrates with circuit structures. This embodiment can be combined with some or all of the features in the above embodiments, which will not be repeated here.

[0193] This embodiment can be combined with some or all of the technical features in the above embodiments, and will not be repeated here. This application provides a display device. Figure 25 is a schematic diagram of the structure of a display device provided in an embodiment of this application. As shown in Figure 25, the display device 1300 includes a display panel or substrate provided in any embodiment of this application.

[0194] The display device is a product with image display capabilities. For example, display device 1300 can be used to display static images, such as pictures or photographs. Display device 1300 can also be used to display dynamic images, such as videos.

[0195] Display device 1300 may be a laptop computer, mobile phone, handheld or portable computer, camera, camcorder, in-vehicle smart central control screen, calculator, smartwatch, GPS navigator, electronic photo, electronic billboard or sign, projector, etc.

[0196] In addition, the display device 1300 can also perform functions such as taking photos, recording videos, fingerprint recognition, and facial recognition. Accordingly, the display device 1300 also includes at least one functional module for implementing the above functions, such as an under-display camera or an under-display fingerprint recognition sensor.

[0197] The above description has been given for purposes of illustration and description. Furthermore, this description is not intended to limit the embodiments of this application to the forms disclosed herein. Although numerous exemplary aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, alterations, additions, and sub-combinations thereof.

Claims

1. A display panel, comprising: Substrate; The first element is located on the substrate; The second element is located on the substrate; A third element portion is located on the substrate, and the third element portion and the first element portion are disposed in different layers, and the third element portion and the second element portion are disposed in different layers; A first via exposes at least a portion of the surface of the third element portion away from the substrate, at least a portion of the surface of the first element portion away from the substrate, and at least a portion of the surface of the second element portion away from the substrate; The first connecting portion fills the first through hole, and the first connecting portion is electrically connected to the third element portion, the first element portion, and the second element portion.

2. The display panel according to claim 1, wherein, The first element section and the second element section are arranged on the same layer or on different layers.

3. The display panel according to claim 1, wherein, The third element extends along the first direction; The orthographic projection of the first element portion on the substrate and the orthographic projection of the second element portion on the substrate are located on one or both sides of the orthographic projection of the third element portion on the substrate along the second direction, and the first direction and the second direction intersect.

4. The display panel according to claim 1, wherein, It also includes a second connecting portion, connecting the first element portion and the second element portion, wherein the overlapping area of ​​the orthographic projection of the second connecting portion on the substrate and the orthographic projection of the third element portion on the substrate overlaps with the orthographic projection of the first connecting portion on the substrate. The first component portion, the second component portion, and the second connecting portion are disposed on the same layer; The first element portion, the second element portion, and the second connection portion are located in the same active layer, and the third element portion is located in the gate layer; The third component is a first trace, which includes a first trace segment and a second trace segment arranged along the extension direction of the first trace. The overlapping area of ​​the orthographic projection of the second connection portion on the substrate and the orthographic projection of the first trace segment on the substrate overlaps with the orthographic projection of the first connection portion on the substrate. The width of at least a portion of the first trace segment is less than or equal to the width of the second trace segment.

5. The display panel according to claim 4, wherein, The first trace segment has a notch on one or both of its opposite sides along its width direction, and the orthographic projection of the notch on the substrate overlaps with the orthographic projection of the first via on the substrate. And / or, the first trace is provided with a break, and the orthographic projection of the break on the substrate overlaps with the orthographic projection of the first via on the substrate; The orthographic projection of the fracture on the substrate overlaps with the orthographic projection of the second connection portion on the substrate; The first trace is the initialization signal line.

6. The display panel according to claim 1, wherein, A first gap exists between the first element portion and the second element portion, and the orthographic projection of the first gap on the substrate overlaps with the orthographic projection of the third element portion on the substrate; The first element portion and the second element portion are located in the same active layer, and the third element portion is located in the gate layer; The third element portion is a first trace, which includes a first trace segment and a second trace segment arranged along the extension direction of the first trace. The overlapping area of ​​the orthographic projection of the first gap on the substrate and the orthographic projection of the first trace segment on the substrate overlaps with the orthographic projection of the first connection portion on the substrate. The width of at least a portion of the first trace segment is less than or equal to the width of the second trace segment. The first trace segment has a notch on one or both sides of its opposite sides along its width direction, and the orthographic projection of the notch on the substrate overlaps with the orthographic projection of the first via on the substrate.

7. The display panel according to claim 1, wherein, The film layer containing the third element is located on the side of the film layer containing the first element and the film layer containing the second element that is away from the substrate; Alternatively, the film layer containing the third element portion is located on the side of the film layer containing the first element portion and the film layer containing the second element portion closer to the substrate; Alternatively, the film layer containing the third element portion may be located between the film layer containing the first element portion and the film layer containing the second element portion.

8. The display panel according to claim 1, wherein, The display panel further includes a first transistor; the first element portion is the active portion of the first transistor; The display panel further includes a second transistor; the second element portion is the active portion of the second transistor; The active portions of the first transistor and the second transistor are disposed on different layers; or, the active portions of the first transistor and the second transistor are disposed on the same layer, and the gates of the first transistor, the gates of the second transistor, and the third element portion are disposed on the same layer. The display panel further includes a second connecting portion connected between the first element portion and the second element portion. The overlapping area of ​​the orthographic projection of the second connecting portion on the substrate and the orthographic projection of the third element portion on the substrate overlaps with the orthographic projection of the first connecting portion on the substrate. The first element portion, the second element portion, and the second connecting portion are located in the same active layer. The conductivity of the second connection portion is less than the conductivity of the source or drain region of the active portion of the first transistor, or the doping concentration of the conductive particles in the second connection portion is less than the doping concentration of the conductive particles in the source or drain region of the active portion of the first transistor; and / or, the conductivity of the second connection portion is less than the conductivity of the source or drain region of the active portion of the second transistor, or the doping concentration of the conductive particles in the second connection portion is less than the doping concentration of the conductive particles in the source or drain region of the active portion of the second transistor.

9. The display panel according to claim 1, wherein, The orthographic projection of the first connecting portion onto the substrate is rectangular; And / or, the orthographic projection of the first via on the substrate is rectangular; And / or, the third element is an initialization signal line; And / or, the first connection portion covers at least a portion of the surface of the third element portion exposed by the first via that is away from the substrate, at least a portion of the surface of the first element portion that is away from the substrate, and at least a portion of the surface of the second element portion that is away from the substrate; And / or, the display panel includes a first insulating layer located between the film layer containing the third element portion and the film layer containing the first element portion, the first element portion and the second element portion being disposed in the same layer, and the first via penetrating the first insulating layer to expose at least a portion of the surface of the first element portion away from the substrate and at least a portion of the surface of the second element portion away from the substrate; And / or, the display panel includes a second insulating layer located on the side of the film layer containing the third element portion and the first insulating layer away from the substrate, the first via penetrating the second insulating layer to expose at least a portion of the surface of the third element portion away from the substrate; the first via penetrating the first insulating layer and the second insulating layer to expose at least a portion of the surface of the first element portion away from the substrate and at least a portion of the surface of the second element portion away from the substrate; And / or, the orthographic projection of the first via on the substrate is located within the orthographic projection of the active layer containing the first element portion on the substrate, or, the orthographic projection of the first via on the substrate is located within the orthographic projection of the active layer containing the second element portion on the substrate.

10. The display panel according to claim 1, wherein, It also includes multiple pixel circuits arranged in an array, each pixel circuit comprising a first element portion and a second element portion; In two adjacent pixel circuits located in the same column, the first element portion in one pixel circuit and the second element portion in the other pixel circuit are electrically connected to the third element portion through the first connection portion. The third element portion extends along the row direction, and the row direction intersects with the column direction. The pixel circuit includes a first transistor and a second transistor, wherein the first element portion is the active portion of the first transistor, and the second element portion is the active portion of the second transistor. The first transistor and the second transistor have different functions; The third component is an initialization signal line; The initialization signal line is located in the gate layer of the first transistor and / or the gate layer of the second transistor; The pixel circuit further includes a driving transistor, wherein the first transistor is used to initialize the gate, source, or drain of the driving transistor. And / or, the display panel further includes a light-emitting device, wherein the second transistor is used to initialize the first electrode of the light-emitting device.

11. The display panel according to claim 1, wherein, It also includes multiple pixel circuits arranged in an array, each pixel circuit comprising the first element portion and / or the second element portion. In two adjacent pixel circuits located in the same column, the first element part in one pixel circuit and the second element part in the other pixel circuit have the same function and are electrically connected to the third element part through the first connection part. The third element part extends along the row direction, and the row direction intersects with the column direction. Alternatively, the display panel may include multiple pixel circuit groups, each pixel circuit group including two adjacent pixel circuits located in the same row. In the same pixel circuit group, the first element portion of one pixel circuit and the second element portion of the other pixel circuit have the same function and are electrically connected to the third element portion through the first connection portion.

12. The display panel according to claim 11, wherein, The pixel circuit includes a first transistor, at least one second element portion and at least one first element portion being active portions of the first transistor in different pixel circuits. The pixel circuit also includes a driving transistor, the first transistor being used to initialize the gate, source, or drain of the driving transistor. And / or, the pixel circuit includes a second transistor, at least one second element portion and at least one first element portion are active portions of the second transistor in different pixel circuits, and the display panel further includes a light-emitting device, the second transistor being used to initialize the first electrode of the light-emitting device; The third component is an initialization signal line; The initialization signal line is located in the gate layer of the first transistor and / or the gate layer of the second transistor; The active layers of two adjacent pixel circuits located in the same column are mirror-symmetrically arranged; and / or, the active layers of two adjacent pixel circuits located in the same row are mirror-symmetrically arranged; The active portions of the first transistor and the active portions of the second transistor are electrically connected to the same initialization signal line, or to different initialization signal lines; Alternatively, the initialization signal line includes a first initialization signal line and a second initialization signal line that are insulated and alternately arranged along the column direction, wherein the active portion of the first transistor is electrically connected to the first initialization signal line, and the active portion of the second transistor is electrically connected to the second initialization signal line. And / or, in two adjacent pixel circuit groups located in the same column, they are electrically connected via the same first connection portion to the same third element portion located between the two pixel circuit groups.

13. The display panel according to claim 1, wherein, It also includes multiple pixel circuits arranged in an array, each pixel circuit comprising the first element portion and / or the second element portion. In two adjacent pixel circuits located in the same column, the first element part in one pixel circuit and the second element part in the other pixel circuit have the same function and are electrically connected to the third element part through the first connection part. The third element part extends along the row direction, and the row direction intersects with the column direction. The display panel includes multiple pixel circuit groups, each pixel circuit group including two adjacent pixel circuits located in the same row. In the same pixel circuit group, the first element part in one pixel circuit and the second element part in another pixel circuit have the same function and are electrically connected to the third element part through the first connection part. The pixel circuit includes a first transistor, at least one second element portion and at least one first element portion being active portions of the first transistor in different pixel circuits. The pixel circuit also includes a driving transistor, the first transistor being used to initialize the gate, source, or drain of the driving transistor. And / or, the pixel circuit includes a second transistor, at least one second element portion and at least one first element portion are active portions of the second transistor in different pixel circuits, and the display panel further includes a light-emitting device, the second transistor being used to initialize the first electrode of the light-emitting device; The third component is an initialization signal line; The initialization signal line is located in the gate layer of the first transistor and / or the gate layer of the second transistor; The active layers of two adjacent pixel circuits located in the same column are mirror-symmetrically arranged; and / or, the active layers of two adjacent pixel circuits located in the same row are mirror-symmetrically arranged; The active portions of the first transistor and the active portions of the second transistor are electrically connected to the same initialization signal line, or to different initialization signal lines; Alternatively, the initialization signal line includes a first initialization signal line and a second initialization signal line that are insulated and alternately arranged along the column direction, wherein the active portion of the first transistor is electrically connected to the first initialization signal line, and the active portion of the second transistor is electrically connected to the second initialization signal line. And / or, in two adjacent pixel circuit groups located in the same column, they are electrically connected via the same first connection portion to the same third element portion located between the two pixel circuit groups.

14. The display panel according to any one of claims 10-13, wherein, The pixel circuit further includes a data writing transistor, which is connected between the data line and the first terminal of the driving transistor, and the gate of the second transistor and the gate of the data writing transistor are electrically connected to the first scan line. The first scan line is disposed on the same layer as the initialization signal line; and / or, the data line is disposed on the same layer as the first connection portion. The first scan line and the initialization signal line extend along a first direction; The gate of the first transistor is electrically connected to the second scan line, and the second scan line is disposed on the same layer as the initialization signal line; The second scan line and the initialization signal line extend along the first direction; The initialization signal line is located between the first scan line and the second scan line; The gate of the driving transistor is disposed on the same layer as the initialization signal line; The pixel circuit also includes a storage capacitor, and the gate of the driving transistor is reused as the first plate of the storage capacitor; The display panel further includes a light emission control signal line, and the first scan line is located between the light emission control signal line and the initialization signal line; The pixel circuit further includes a first light-emitting control transistor connected between the second electrode of the driving transistor and the first electrode of the light-emitting device, and the gate of the first light-emitting control transistor is electrically connected to the light-emitting control signal line; The data write transistor is turned on during a write frame to transmit the data voltage on the data line to the drive transistor, and turned on during a hold frame to transmit the bias voltage on the data line to the drive transistor. The pixel circuit further includes a threshold compensation transistor connected between the gate and the second electrode of the driving transistor, and the gate of the threshold compensation transistor is electrically connected to the third scan line. The second scan line is located between the initialization signal line and the third scan signal line.

15. The display panel according to claim 1, wherein, The display panel further includes a first power cord, which is disposed on the same layer as the first connecting portion and extends along a second direction. In the first direction, the first power line and the first connection portion are arranged alternately; The display panel further includes a pixel circuit, and the first power line is electrically connected to the pixel circuit. The pixel circuit includes a storage capacitor, and at least a portion of the first power line is multiplexed as the second plate of the storage capacitor. The data line extends along a second direction, and the first power line and the data line are arranged alternately along a first direction; In the first direction, the first connection portion is located between the first power line and the data line; The pixel circuit includes a driving transistor and a second light-emitting control transistor. The second light-emitting control transistor is connected between the first electrode of the driving transistor and the first power supply line. The gate of the second light-emitting control transistor is electrically connected to the light-emitting control signal line, and the light-emitting control signal line is disposed on the same layer as the third element. The light emission control signal line extends along a first direction with the third element, and the first direction intersects with the second direction.

16. The display panel according to claim 14, wherein, The display panel further includes a first scanning circuit, which includes multiple levels of first shift registers. The output of each of the first shift registers is electrically connected to the gate of the corresponding first transistor and the gate of the threshold compensation transistor. The first transistor and the threshold compensation transistor, which are electrically connected to the same first shift register, are located in different pixel circuits; In two adjacent rows of pixel circuits, the first transistor in one row of pixel circuits and the threshold compensation transistor in the other row of pixel circuits are electrically connected to the same first shift register; The active portion of the first transistor and the active portion of the threshold compensation transistor are connected in the orthographic projection of the substrate to form a groove, and the bottom and opening of the groove are arranged along a first direction. The first transistor includes at least two first sub-transistors connected in series; And / or, the threshold compensation transistor includes at least two second sub-transistors connected in series.

17. The display panel according to claim 1, wherein, The third element is an initialization signal line; the display panel also includes a first scan line, the first scan line including a third trace segment and a fourth trace segment arranged along the extension direction of the first scan line, the distance between the third trace segment and the initialization signal line is smaller than the distance between the fourth trace segment and the initialization signal line; The first via is directly opposite the third trace segment; The pixel circuit further includes a data writing transistor, the gate of which is electrically connected to the first scan line; the display panel further includes a second via, the second via exposing a portion of the first electrode of the data writing transistor; the orthographic projection of the second via on the substrate is located between the orthographic projection of the initialization signal line on the substrate and the orthographic projection of the first scan line on the substrate; The display panel further includes a light emission control signal line located on the side of the first scan line away from the initialization signal line; the display panel further includes a third via, a fourth via, and a fifth via, the orthographic projections of the third via, the fourth via, and the fifth via on the substrate are all located between the light emission control signal line and the first scan line; The orthographic projections of the third via and the fourth via on the substrate are both located between the orthographic projection of the third trace segment on the substrate and the orthographic projection of the light-emitting control signal line on the substrate; The orthographic projection of the fifth via on the substrate is located between the orthographic projection of the fourth trace segment on the substrate and the orthographic projection of the light-emitting control signal line on the substrate; The pixel circuit further includes a first light-emitting control transistor; the display panel further includes a third connection portion, the third via exposes the second electrode of the first light-emitting control transistor, and the third connection portion fills the third via. The display panel also includes a light-emitting device located on the side of the pixel circuit away from the substrate, and the first electrode of the light-emitting device is electrically connected to the third connecting portion; The pixel circuit further includes a second light-emitting control transistor; the display panel further includes a power signal line, the fourth via exposes the first electrode of the second light-emitting control transistor, and the power signal line fills the fourth via; The pixel circuit also includes a data writing transistor and a driving transistor; The display panel further includes a fourth connection portion, the fifth via exposes the second terminal of the data writing transistor, and the sixth via exposes the first terminal of the driving transistor; the fourth connection portion fills the fifth via and the sixth via; The third via, the fourth via, and the fifth via are arranged sequentially along the first direction; The orthogonal projection of the sixth via on the substrate is located on the side of the orthogonal projection of the light emission control signal line on the substrate that is far from the orthogonal projection of the first scan line on the substrate.

18. A display panel, comprising: Substrate; The first element is located on the substrate; The second element is located on the substrate; A third element portion is located on the substrate, and the third element portion and the first element portion are disposed in different layers, and the third element portion and the second element portion are disposed in different layers; A plurality of first vias, at least one of the first vias exposing at least a portion of the surface of the third element portion away from the substrate, at least a portion of the surface of the first element portion away from the substrate, at least one of the first vias exposing at least a portion of the surface of the third element portion away from the substrate, and at least a portion of the surface of the second element portion away from the substrate; Multiple first connecting portions fill the corresponding first through holes, and the first connecting portions that electrically connect the third element portion and the first element portion are spaced apart from the first connecting portions that electrically connect the third element portion and the second element portion.

19. The display panel according to claim 18, wherein, It also includes multiple pixel circuits arranged in an array, each pixel circuit comprising the first element portion and / or the second element portion. The display panel includes multiple pixel circuit groups, each pixel circuit group including two adjacent pixel circuits located in the same row. In the same pixel circuit group, the first element part in one pixel circuit and the second element part in another pixel circuit have the same function and are electrically connected to the third element part through the first connection part. The third element part extends along the row direction, and the row direction intersects with the column direction. The pixel circuit includes a first transistor, at least one second element portion and at least one first element portion being active portions of the first transistor in different pixel circuits. The pixel circuit also includes a driving transistor, the first transistor being used to initialize the gate, source, or drain of the driving transistor. And / or, the pixel circuit includes a second transistor, at least one second element portion and at least one first element portion are active portions of the second transistor in different pixel circuits, and the display panel further includes a light-emitting device, the second transistor being used to initialize the first electrode of the light-emitting device; The third component is an initialization signal line; The initialization signal line is located in the gate layer of the first transistor and / or the gate layer of the second transistor; The active layers of two adjacent pixel circuits located in the same row are mirror-symmetrically arranged; The active portions of the first transistor and the active portions of the second transistor are electrically connected to the same initialization signal line, or to different initialization signal lines; Alternatively, the initialization signal line includes a first initialization signal line and a second initialization signal line that are insulated and alternately arranged along the column direction, wherein the active portion of the first transistor is electrically connected to the first initialization signal line, and the active portion of the second transistor is electrically connected to the second initialization signal line.

20. A display device comprising a display panel according to any one of claims 1-19.

Images