Semiconductor device and method for producing semiconductor device

Abstract

A semiconductor device 10 is provided with a semiconductor chip 12, and a temperature-sensitive element layer 14 including a temperature-sensitive element 14A that senses the temperature in the vicinity of the semiconductor chip 12.

Description

Semiconductor device and manufacturing method thereof

[0001] The technology disclosed in this specification relates to a semiconductor device in which temperature is sensed and a method for manufacturing the semiconductor device.

[0002] A conventionally known semiconductor device is described in Patent Document 1. The modulation device (semiconductor device) described in Patent Document 1 includes a substrate, a modulation unit disposed on the substrate, data lines disposed on the substrate and electrically connected to the modulation unit, and scanning lines disposed on the substrate and having overlapping regions that overlap with the data lines and non-overlapping regions that do not overlap with the data lines, wherein in a first direction, the scanning lines have a first width in the overlapping region and a second width in the non-overlapping region, the first width being smaller than the second width.

[0003] US Patent Application Publication No. 2023 / 0238390

[0004] (Problem to be Solved by the Invention) In the modulation device described in the above-mentioned Patent Document 1, a varactor diode is exemplified as a modulation section, and the capacitance of the varactor diode is modulated to a value corresponding to the potential supplied from the data line. However, the modulation device described in Patent Document 1 has a problem in that even if the temperature of the modulation device rises due to heat generation from a chip provided on a substrate, the temperature cannot be sensed.

[0005] The technology described in this specification was developed based on the above circumstances, and aims to sense temperature.

[0006] (Means for Solving the Problems) (1) A semiconductor device according to the technology described in this specification includes a semiconductor chip and a temperature sensing element layer including a temperature sensing element that senses the temperature near the semiconductor chip.

[0007] (2) In addition to the above (1), the semiconductor device may also be such that a plurality of the semiconductor chips are arranged side by side, and a plurality of the temperature-sensing elements are arranged overlapping each of the plurality of semiconductor chips.

[0008] (3) In addition to the above (2), the semiconductor device may further include a plurality of switching elements connected to a plurality of the temperature sensitive elements in the temperature sensitive element layer.

[0009] (4) In addition to (3) above, the semiconductor device may also be arranged such that the temperature-sensing element and the switching element are arranged in a matrix pattern in a plane along a first direction and a second direction intersecting the first direction.

[0010] (5) In addition to (4), the semiconductor device may further include a plurality of first wirings in the thermosensitive element layer, the first wirings extending along the first direction and connected to the plurality of switching elements aligned along the first direction, and spaced apart in the second direction; a plurality of second wirings extending along the second direction and connected to the plurality of switching elements aligned along the second direction, and spaced apart in the first direction; a signal supply unit connected to the plurality of first wirings; and a signal detection unit connected to the plurality of second wirings, wherein the signal supply unit sequentially supplies scanning signals to the plurality of first wirings for driving the plurality of switching elements, and the signal detection unit detects output signals output from the plurality of thermosensitive elements to the plurality of second wirings via the driven plurality of switching elements.

[0011] (6) In addition to any one of (3) to (5), the semiconductor device may be such that the switching element has a semiconductor portion made of an oxide semiconductor material.

[0012] (7) In addition to any one of (1) to (6), the semiconductor device may be such that a plurality of the temperature sensing elements are arranged in a superimposed manner on one of the semiconductor chips.

[0013] (8) In addition to any one of (1) to (7), the semiconductor device may be such that the temperature sensitive element includes a resistance temperature sensor.

[0014] (9) In addition to any one of (1) to (8), the semiconductor device may further include a rewiring layer including rewiring connected to the semiconductor chip.

[0015] (10) In addition to the above (9), the semiconductor device may be configured such that the rewiring layer is disposed above the temperature sensitive element layer and below the semiconductor chip.

[0016] (11) In addition to any one of (1) to (10), the semiconductor device may also include a substrate having a first main surface and a second main surface, and the semiconductor chip and the temperature-sensitive element layer may be provided on the first main surface of the substrate.

[0017] (12) In addition to any of (1) to (11) above, the semiconductor device may further include a cooling unit that is thermally connected to the semiconductor chip and capable of cooling the semiconductor chip, and a control unit that is electrically connected to the temperature-sensing element and the cooling unit, and the control unit may control the cooling state by the cooling unit based on information related to the temperature sensed by the temperature-sensing element.

[0018] (13) In addition to the above (12), the semiconductor device may further include a cooling unit that includes a heat sink thermally connected to the semiconductor chip and a cooling fan capable of blowing air to the heat sink, and the control unit that controls the blowing state of the cooling fan.

[0019] (14) In addition to the semiconductor device described above in (12), the cooling unit may have a Peltier element thermally connected to the semiconductor chip, and the control unit may control the electrical conduction state of the Peltier element.

[0020] (15) In addition to the above (12), the semiconductor device may further include a cooling unit that has a heat dissipation member thermally connected to the semiconductor chip and a refrigerant pipe thermally connected to the heat dissipation member, and the control unit that controls the flow of refrigerant in the refrigerant pipe.

[0021] (16) A method for manufacturing a semiconductor device according to the technology described in this specification provides a temperature sensitive element layer including a temperature sensitive element, and provides a semiconductor chip near the temperature sensitive element.

[0022] (17) In addition to the above (16), the method for manufacturing a semiconductor device may further include providing the photosensitive element layer so that a plurality of the photosensitive elements are arranged, and providing a plurality of the semiconductor chips so as to overlap the plurality of the photosensitive elements.

[0023] (18) In addition to (17), the manufacturing method of the semiconductor device may further include a cooling unit that is thermally connected to a plurality of the semiconductor chips and is capable of cooling the plurality of the semiconductor chips, and a control unit that is electrically connected to the temperature sensor and the cooling unit and is capable of controlling the cooling state of the cooling unit based on information related to the temperature sensed by the temperature sensor.

[0024] EFFECT OF THE INVENTION According to the technology described in this specification, temperature sensing can be performed.

[0025] FIG. 2 is a schematic perspective view of a semiconductor device according to embodiment 1, showing the arrangement of semiconductor chips; FIG. 3 is a plan cross-sectional view of the semiconductor device according to embodiment 1, cutting a partition member therethrough; FIG. 2 is a cross-sectional view of the semiconductor device according to embodiment 1, showing the outline of the semiconductor device; 8 is an enlarged plan view showing the vicinity of an element and a TFT; FIG. 8 is a cross-sectional view taken along line ix-ix of FIG. 8 in the semiconductor device according to embodiment 2; FIG. 9 is a cross-sectional view taken along the same cutting position as FIG. 6, showing a state in which laser light is irradiated after a semiconductor chip is mounted, in the manufacturing process of the semiconductor device according to embodiment 3; FIG. 10 is a cross-sectional view taken along the same cutting position as FIG. 6, showing a process in which a substrate is peeled, in the manufacturing process of the semiconductor device according to embodiment 3; FIG. 11 is a cross-sectional view taken along the same cutting position as FIG. 6, showing a state in which solder balls are provided on the temperature-sensitive element layer, in the manufacturing process of the semiconductor device according to embodiment 3;

[0026] First Embodiment A first embodiment will be described with reference to Fig. 1 to Fig. 7. In this embodiment, a semiconductor device 10 will be illustrated. Note that the description of the up-down direction is based on Fig. 2 and Fig. 6.

[0027] As shown in FIG. 1 , the semiconductor device 10 according to this embodiment uses chiplet technology and includes multiple semiconductor chips 12 mounted on a single substrate 11. Note that in FIG. 1 , a cooling unit 16 (described later) is not shown in order to illustrate the arrangement of the semiconductor chips 12. Examples of chiplet technology include "System in Package (SiP)," which combines multiple semiconductor chips 12 into a single package; "2.5-dimensional packaging," which connects multiple semiconductor chips 12 via a connecting semiconductor chip; and "3-dimensional packaging," which stacks and connects the semiconductor chips 12 in a three-dimensional manner. The multiple semiconductor chips 12 may include, for example, logic semiconductors, memories such as dynamic random access memories (DRAMs) and flash memories, analog integrated circuits (ICs), radio frequency integrated circuits (RFICs), and power semiconductors.

[0028] In this embodiment, the multiple semiconductor chips 12 include three types of chips of different sizes, as shown in FIG. 1 . Hereinafter, when distinguishing between the semiconductor chips 12, the large semiconductor chip 12 will be referred to as the "first semiconductor chip" and will be given a suffix α, the medium-sized semiconductor chip 12 will be referred to as the "second semiconductor chip" and will be given a suffix β, and the small semiconductor chip 12 will be referred to as the "second semiconductor chip" and will be given a suffix γ. When referring to the chips 12 collectively without distinction, the suffix will not be given to the reference numerals. The large first semiconductor chip 12α has an area covering approximately half of the substrate 11. The medium-sized second semiconductor chip 12β has an area covering approximately one-quarter of the substrate 11. The small third semiconductor chip 12γ has an area covering approximately one-eighth of the substrate 11, and the two chips are arranged side by side. The sum of the areas of the two third semiconductor chips 12γ is approximately one-quarter of the area of ​​the substrate 11, i.e., corresponds to the area of ​​the second semiconductor chip 12β and approximately half the area of ​​the first semiconductor chip 12α. As shown in Figures 2 and 3, the semiconductor device 10 includes a cooling unit 16 for cooling the semiconductor chip 12. The detailed configuration of the cooling unit 16 will be described later.

[0029] As shown in FIG. 3 , the substrate 11 included in the semiconductor device 10 has a first main surface 11A facing the front side (upper side in FIG. 3 ) and a second main surface 11B facing the back side (lower side in FIG. 3 ). A rewiring layer 13, to which the semiconductor chip 12 is connected, is provided on the first main surface 11A of the substrate 11. A temperature sensing element layer 14 is provided on the first main surface 11A of the substrate 11. In this embodiment, the temperature sensing element layer 14 is disposed on the first main surface 11A of the substrate 11 as an underlying layer and is disposed below the rewiring layer 13. The rewiring layer 13 is located above the temperature sensing element layer 14 and below the semiconductor chip 12. The semiconductor chip 12 is flip-chip mounted to the rewiring layer 13 on the first main surface 11A of the substrate 11. Electrodes (not shown) and solder balls (solder bumps) 12A connected to the electrodes are provided on the surface of the semiconductor chip 12 facing the redistribution layer 13, and the solder balls 12A are connected to the redistribution layer 13. A semiconductor device 10 including such a redistribution layer 13 can be efficiently manufactured using fan-out wafer level packaging (FOWLP) or fan-out panel level packaging (FOPLP). The semiconductor device 10 includes a molded portion 21 for fixing the semiconductor chip 12 on the first main surface 11A of the substrate 11. The molded portion 21 is made of a synthetic resin with excellent insulating properties and is molded to seal the semiconductor chip 12 mounted on the upper layer side of the redistribution layer 13. The molded portion 21 is formed to be lower than the top surface of the semiconductor chip 12 (the surface facing the heat sink 16A described below).

[0030] As shown in FIG. 6 , the rewiring layer 13 includes rewirings 13A and interlayer insulating material (build-up film) 13B. The rewiring layer 13 includes multiple rewirings 13A and multiple interlayer insulating material 13B, with the rewirings 13A and the interlayer insulating material 13B alternately stacked. The rewirings 13A are made of a metal material (e.g., copper) and are formed into a predetermined wiring pattern by, for example, plating the surface of the interlayer insulating material 13B. Therefore, the thickness of the rewirings 13A is, for example, approximately 10 μm. The multiple rewirings 13A are arranged in different layers, one above the other, with the interlayer insulating material 13B interposed between them. Multiple rewirings 13A may be provided in the same layer as different (electrically independent) wiring patterns. The rewirings 13A located in the top layer of the multiple rewirings 13A are connected to solder balls 12A of the semiconductor chip 12. Among the multiple rewirings 13A, the rewirings 13A located in the lowest layer include those connected to solder balls 15, which will be described later. The interlayer insulating material 13B is made of an insulating resin material and is in the form of a film. The interlayer insulating material 13B has multiple through holes (vias) 13B1 formed at predetermined positions. The multiple through holes 13B1 are arranged in positions overlapping the rewirings 13A within the main surface of the interlayer insulating material 13B. The rewirings 13A are also formed within the through holes 13B1. Therefore, the two rewirings 13A arranged above and below the interlayer insulating material 13B are connected to each other through the through holes 13B1. The through holes 13B1 are formed, for example, by laser processing the interlayer insulating material 13B.

[0031] The substrate 11 is made of, for example, a glass material, and has a plurality of through holes 11C formed at predetermined positions, as shown in FIG. 6 . A portion of the rewirings 13A located in the lowest layer among the plurality of rewirings 13A described above is formed within the through holes 11C. A plurality of solder balls 15 are provided on the second main surface 11B of the substrate 11 at positions overlapping the plurality of through holes 11C. The solder balls 15 are connected to the rewirings 13A within the through holes 11C. The solder balls 15 are arranged, for example, in a grid pattern on the second main surface 11B of the substrate 11. Thus, the semiconductor device 10 according to this embodiment is a package known as a "BGA (Ball Grid Array)."

[0032] Next, the configuration of the temperature sensing element layer 14 will be described in detail. The temperature sensing element layer 14 is formed on the substrate 11 using a known photolithography method, using the first main surface 11A as a base, as shown in FIG. 6 . The temperature sensing element layer 14 includes a temperature sensing element 14A for sensing the temperature near the semiconductor chip 12. The temperature sensing element 14A includes, for example, a resistance temperature sensor whose resistance changes depending on the temperature. In other words, the temperature sensing element 14A can be considered a type of variable resistor. Examples of the resistance temperature sensor include a resistance temperature detector (RTD) and a thermistor. When a resistance temperature detector (RTD) or a PTC (positive temperature coefficient) type thermistor is used as the resistance temperature sensor, the temperature sensing element 14A has a characteristic that its resistance value increases with increasing temperature. When a NTC (negative temperature coefficient) type resistance temperature sensor is used, the temperature sensing element 14A has a characteristic that its resistance value decreases with increasing temperature.

[0033] As shown in Figure 6, the thermosensitive element layer 14 includes a TFT (Thin Film Transistor: switching element) 14B connected to a thermosensitive element 14A. The TFT 14B has a gate electrode 14B1, a source electrode 14B2, a drain electrode 14B3, and a semiconductor portion 14B4. By appropriately driving the TFT 14B, it is possible to selectively sense temperature using the thermosensitive element 14A connected to the driven TFT 14B.

[0034] The cross-sectional structure of the thermosensitive element layer 14 will now be described in detail. As shown in FIG. 6 , the thermosensitive element layer 14 includes a buffer insulating film 17, a gate insulating film 18, a first interlayer insulating film 19, and a second interlayer insulating film 20 in addition to the thermosensitive element 14A and TFT 14B described above. The buffer insulating film 17 is made of an inorganic resin material such as silicon nitride or silicon oxide, and is disposed in contact with the first main surface 11A of the substrate 11. The gate electrode 14B1 of the TFT 14B and other components are disposed above the buffer insulating film 17. The gate electrode 14B1 is formed by photolithographically patterning a first metal film deposited on the buffer insulating film 17. The first metal film is a single-layer film made of one type of metal material selected from copper, titanium, aluminum, molybdenum, tungsten, etc., or a laminated film or alloy made of different types of metal materials, and its thickness is, for example, approximately several tens to several hundreds of nanometers. In other words, the thickness of the first metal film is much smaller than the thickness of the redistribution wiring 13A. The gate insulating film 18 is made of an inorganic resin material such as silicon nitride or silicon oxide, and is disposed above the gate electrode 14B1. The semiconductor portion 14B4 of the TFT 14B is disposed above the gate insulating film 18. The semiconductor portion 14B4 is disposed so as to overlap the gate electrode 14B1 with the gate insulating film 18 interposed therebetween in a plan view. The semiconductor portion 14B4 is formed by patterning a semiconductor film formed on the gate insulating film 18 by photolithography.

[0035] The semiconductor film constituting the semiconductor portion 14B4 of the TFT 14B is made of an oxide semiconductor material. The semiconductor film may contain at least one metal element selected from the group consisting of In, Ga, and Zn, and may be, for example, an In—Ga—Zn—O-based semiconductor (e.g., indium gallium zinc oxide). Here, the In—Ga—Zn—O-based semiconductor is a ternary oxide of In (indium), Ga (gallium), and Zn (zinc). The ratio (composition ratio) of In, Ga, and Zn is not particularly limited, and may include, for example, In:Ga:Zn=2:2:1, In:Ga:Zn=1:1:1, In:Ga:Zn=1:1:2, etc. The In—Ga—Zn—O-based semiconductor used in the semiconductor film may be amorphous or crystalline. The semiconductor film may contain other oxide semiconductors instead of the In—Ga—Zn—O-based semiconductor. For example, an In—Sn—Zn—O-based semiconductor (e.g., In ２ O ３ -SnO ２In—Sn—Zn—O based semiconductors may contain In (indium), Sn (tin), and Zn (zinc). Alternatively, the oxide semiconductor layer may include an In—W—Zn—O-based semiconductor containing W (tungsten), an In—W—Sn—Zn—O-based semiconductor, an In—Al—Zn—O-based semiconductor, an In—Al—Sn—Zn—O-based semiconductor, a Zn—O-based semiconductor, an In—Zn—O-based semiconductor, a Zn—Ti—O-based semiconductor, a Cd—Ge—O-based semiconductor, a Cd—Pb—O-based semiconductor, CdO (cadmium oxide), an Mg—Zn—O-based semiconductor, an In—Ga—Sn—O-based semiconductor, an In—Ga—O-based semiconductor, a Zr—In—Zn—O-based semiconductor, an Hf—In—Zn—O-based semiconductor, an Al—Ga—Zn—O-based semiconductor, a Ga—Zn—O-based semiconductor, or an In—Ga—Zn—Sn—O-based semiconductor. The oxide semiconductor material of the semiconductor film has a higher resistance value when no voltage is applied (off state), i.e., a lower off-leak current, compared to polysilicon semiconductor material. This reduces noise, thereby improving the temperature sensing sensitivity of the temperature sensor 14A. Furthermore, the oxide semiconductor material of the semiconductor film has a higher electron mobility than amorphous silicon semiconductor material. The film thickness of the semiconductor film is, for example, approximately several tens to several hundreds of nanometers. In other words, the thickness of the semiconductor film is much smaller than the thickness of the rewiring 13A.

[0036] As shown in FIG. 6 , the TFT 14B according to this embodiment is a bottom-gate type in which the gate electrode 14B1 is located below the semiconductor portion 14B4. A source electrode 14B2 and a drain electrode 14B3 are disposed above the semiconductor portion 14B4. The source electrode 14B2 is connected to one end of the semiconductor portion 14B4. The drain electrode 14B3 is connected to the other end of the semiconductor portion 14B4 (the side opposite the source electrode 14B2). The source electrode 14B2 and the drain electrode 14B3 are disposed at a predetermined distance on the semiconductor portion 14B4. The source electrode 14B2 and the drain electrode 14B3 are formed by photolithographically patterning a second metal film formed on the semiconductor portion 14B4. The second metal film is a single layer made of one metal material selected from copper, titanium, aluminum, molybdenum, tungsten, etc., or a laminated film or alloy made of different metal materials, with a thickness of, for example, several tens to several hundred nanometers. In other words, the thickness of the second metal film is much smaller than the thickness of the rewiring 13A. The TFT 14B configured as described above is driven by supplying a potential higher than the threshold voltage to the gate electrode 14B1. When the TFT 14B is driven, a channel region is generated in the semiconductor portion 14B4, allowing charge to move between the source electrode 14B2 and the drain electrode 14B3 via the channel region.

[0037] The first interlayer insulating film 19 is made of an inorganic resin material such as silicon nitride or silicon oxide and is disposed above the source electrode 14B2 and the drain electrode 14B3, as shown in FIG. 6 . A first connection electrode 14C and a second connection electrode 14D are disposed above the first interlayer insulating film 19. The first connection electrode 14C overlaps a portion of the source electrode 14B2 (more specifically, a portion that does not overlap the semiconductor portion 14B4). A first contact hole H1 is formed in the first interlayer insulating film 19 at a position overlapping both the source electrode 14B2 and the first connection electrode 14C. The first connection electrode 14C is connected to the source electrode 14B2 through the first contact hole H1. The first connection electrode 14C and the second connection electrode 14D are spaced apart from each other and overlap both ends of the temperature sensing element 14A, which will be described later. The first connection electrode 14C and the second connection electrode 14D are formed by photolithography patterning a third metal film formed on the first interlayer insulating film 19. The third metal film is a single-layer film made of one type of metal material selected from copper, titanium, aluminum, molybdenum, tungsten, etc., or a laminated film or alloy made of different types of metal materials, and its film thickness is, for example, approximately several tens to several hundreds of nanometers. In other words, the thickness of the third metal film is much smaller than the thickness of the rewiring 13A.

[0038] As shown in FIG. 6 , a temperature sensor 14A is disposed on the upper layer of the third metal film constituting the first connection electrode 14C and the second connection electrode 14D. The temperature sensor 14A is formed by patterning a temperature sensor film formed on the third metal film using photolithography. When the temperature sensor 14A is a resistance temperature sensor, the temperature sensor film contains a metal material such as platinum, nickel, or copper. When the temperature sensor 14A is a thermistor, the temperature sensor film contains an oxide semiconductor ceramic made of manganese, nickel, or cobalt. As shown in FIG. 5 , one end of the temperature sensor 14A overlaps the first connection electrode 14C, and the other end overlaps the second connection electrode 14D, with the portion between the two ends extending in a repeated, meandering pattern. The second interlayer insulating film 20 is made of an inorganic resin material such as silicon nitride or silicon oxide, and is disposed on the upper layer side of the temperature sensing element film that constitutes the temperature sensing element 14A, as shown in Fig. 6. The temperature sensing element 14A and the TFT 14B are covered from above by the second interlayer insulating film 20.

[0039] 6, through holes H2 that communicate with predetermined through holes 11C in the substrate 11 are formed through the buffer insulating film 17, the gate insulating film 18, the first interlayer insulating film 19, and the second interlayer insulating film 20. A portion of the rewiring 13A located in the lowest layer among the plurality of rewirings 13A included in the rewiring layer 13 is formed in the through hole H2 and in the through hole 11C that communicates with the through hole H2. The rewiring 13A formed across the through hole H2 and the through hole 11C that communicates with the through hole H2 is connected to a solder ball 15 provided on the second main surface 11B of the substrate 11. A plurality of through holes H2 and a plurality of through holes 11C that communicate with each other are provided, and a rewiring 13A is formed inside each of them.

[0040] Next, the circuit configuration of the thermosensitive elements 14A and TFTs 14B included in the thermosensitive element layer 14 will be described in detail. As shown in FIG. 4, the thermosensitive element layer 14 includes a plurality of thermosensitive elements 14A and a plurality of TFTs 14B. In FIG. 4, the thermosensitive elements 14A are illustrated with the circuit symbol "variable resistor." Specifically, the thermosensitive elements 14A and the TFTs 14B are arranged in a matrix (row and column) on the first main surface 11A of the substrate 11. In the following description, the left-right direction of the paper in FIGS. 4 and 5 will be referred to as the "first direction," and the up-down direction of the paper will be referred to as the "second direction." In this embodiment, the thermosensitive elements 14A and the TFTs 14B are arranged with four spaced apart in the first direction and four spaced apart in the second direction, for a total of 16 thermosensitive elements 14A and TFTs 14B arranged in a matrix. The 16 thermosensitive elements 14A are arranged so as to overlap each other in a plan view on the four heat sinks 16A. In this way, by driving the plurality of TFTs 14B arranged in a matrix on a plane and using the temperature information sensed by the plurality of thermosensitive elements 14A, it is possible to obtain a two-dimensional temperature distribution.

[0041] In the following, when distinguishing between the temperature-sensing elements 14A, the temperature-sensing element 14A superimposed on the first heat sink 16Aα will be referred to as the "first temperature-sensing element" and will be given the suffix α to its symbol, the temperature-sensing element 14A superimposed on the second heat sink 16Aβ will be referred to as the "second temperature-sensing element" and will be given the suffix β to its symbol, the temperature-sensing element 14A superimposed on the third heat sink 16Aγ will be referred to as the "third temperature-sensing element" and will be given the suffix γ to its symbol, and the temperature-sensing element 14A superimposed on the fourth heat sink 16Aδ will be referred to as the "fourth temperature-sensing element" and will be given the suffix δ to its symbol; and when referring to them collectively without distinction, no suffix will be given to the symbol. Furthermore, in the following, when distinguishing between TFTs 14B, the TFT 14B connected to the first thermosensitive element 14Aα will be referred to as the "first TFT" and will have the suffix α added to its reference symbol, the TFT 14B connected to the second thermosensitive element 14Aβ will be referred to as the "second TFT" and will have the suffix β added to its reference symbol, the TFT 14B connected to the third thermosensitive element 14Aγ will be referred to as the "third TFT" and will have the suffix γ added to its reference symbol, and the TFT 14B connected to the fourth thermosensitive element 14Aδ will be referred to as the "fourth TFT" and will have the suffix δ added to its reference symbol; when referring to them collectively without distinction, no suffix will be added to the reference symbol.

[0042] As shown in Figure 4, the 16 temperature sensing elements 14A include four each of the first temperature sensing elements 14Aα, second temperature sensing elements 14Aβ, third temperature sensing elements 14Aγ, and fourth temperature sensing elements 14Aδ. Each of the four first temperature sensing elements 14Aα and four second temperature sensing elements 14Aβ is arranged to overlap the first semiconductor chip 12α in a planar view. Each of the four third temperature sensing elements 14Aγ is arranged to overlap the second semiconductor chip 12β in a planar view. Of the four fourth temperature sensing elements 14Aδ, two fourth temperature sensing elements 14Aδ are arranged to overlap one third semiconductor chip 12γ in a planar view, and the remaining two fourth temperature sensing elements 14Aδ are arranged to overlap the other third semiconductor chip 12γ in a planar view.

[0043] As shown in FIG. 4 , the thermosensitive element layer 14 includes a scanning line (first line) 14E, a detection line (second line) 14F, a common line (third line, reference potential line) 14G, a signal supply unit 14H, and a signal detection unit 14I. Of these, the scanning line 14E extends along the first direction and is connected to the gate electrodes 14B1 of the four TFTs 14B aligned along the first direction. The four scanning lines 14E are arranged in the second direction at predetermined intervals (e.g., approximately ¼ of the length of the substrate 11 in the second direction). The number of scanning lines 14E corresponds to the number of TFTs 14B aligned in the second direction. The scanning lines 14E are formed from a separate portion of the first metal film from the gate electrodes 14B1 of the TFTs 14B, and are formed together with the gate electrodes 14B1 by patterning the first metal film during the manufacturing process of the semiconductor device 10 (see FIG. 6 ). In the following, when distinguishing between the scanning wirings 14E, the scanning wiring 14E located at the top of FIG. 4 will be referred to as the "first scanning wiring" and will be given a subscript α to its symbol, the scanning wiring 14E located second from the top of FIG. 4 will be referred to as the "second scanning wiring" and will be given a subscript β to its symbol, the scanning wiring 14E located third from the top of FIG. 4 will be referred to as the "third scanning wiring" and will be given a subscript γ to its symbol, and the scanning wiring 14E located at the bottom of FIG. 4 will be referred to as the "fourth scanning wiring" and will be given a subscript δ to its symbol; and when referring to the scanning wirings 14E collectively without distinction, no subscripts will be given to the symbols.

[0044] As shown in FIG. 4 , the detection wiring 14F extends along the second direction and is arranged so as to intersect with the four scanning wirings 14E arranged at intervals in the second direction. The detection wiring 14F is connected to the drain electrodes 14B3 of the four TFTs 14B arranged along the first direction. The TFTs 14B are arranged near the intersections of the scanning wirings 14E and the detection wirings 14F. The four detection wirings 14F are arranged at predetermined intervals in the first direction (e.g., intervals of approximately ¼ of the length of the substrate 11 in the first direction). The number of detection wirings 14F matches the number of TFTs 14B arranged in the first direction. The detection line 14F is formed from a portion of the second metal film that is separate from the source electrode 14B2 and the drain electrode 14B3 of the TFT 14B, and is formed together with the source electrode 14B2 and the drain electrode 14B3 by patterning the second metal film during the manufacturing process of the semiconductor device 10 (see FIG. 6). Therefore, the detection line 14F is connected directly to the drain electrode 14B3, which is also made of the second metal film. In addition, a gate insulating film 18 is interposed between the detection line 14F and the scanning line 14E that intersects with the detection line 14F, thereby preventing short-circuiting with the scanning line 14E (see FIG. 6).

[0045] As shown in FIG. 4 , the common wiring 14G extends in the second direction and is arranged so as to intersect with the four scanning wirings 14E arranged at intervals in the second direction. As shown in FIGS. 4 and 5 , the common wiring 14G is connected to the four thermosensitive elements 14A arranged in the first direction via second connection electrodes 14D. The common wiring 14G is arranged at a predetermined interval in the first direction (e.g., an interval slightly smaller than the interval between two adjacent detection wirings 14F in the first direction) from the detection wirings 14F connected to the same thermosensitive elements 14A via TFTs 14B. The thermosensitive elements 14A and TFTs 14B to be connected are sandwiched between the common wiring 14G and the detection wirings 14F. The temperature sensing element 14A is arranged such that, from one end overlapping the first connection electrode 14C to the other end overlapping the second connection electrode 14D, portions extending in the first direction and portions extending in the second direction are alternately connected to form a generally meandering planar shape. Four common wirings 14G are arranged at predetermined intervals in the first direction (e.g., intervals of approximately 1 / 4 of the length of the substrate 11 in the first direction). The number of common wirings 14G corresponds to the number of temperature sensing elements 14A arranged in the first direction. The common wiring 14G is formed from a portion of the third metal film separate from the first connection electrode 14C and the second connection electrode 14D, and is formed together with the first connection electrode 14C and the second connection electrode 14D by patterning the third metal film during the manufacturing process of the semiconductor device 10 (see FIG. 6 ). Therefore, the common wiring 14G is connected in a manner that directly connects to the second connection electrode 14D made of the same third metal film. In addition, the common wiring 14G is prevented from short-circuiting with the scanning wiring 14E by the gate insulating film 18 and the first interlayer insulating film 19 interposed between the common wiring 14G and the scanning wiring 14E that intersects with it (see FIG. 6).

[0046] As shown in FIG. 4 , the signal supply unit 14H is disposed near an end of the substrate 11 in the first direction and is formed in a strip-like area extending in the second direction. Two signal supply units 14H are arranged side by side along the second direction. Each of the two signal supply units 14H is connected to two scanning lines 14E arranged side by side along the second direction. The signal supply unit 14H supplies scanning signals to the connected scanning lines 14E and is monolithically formed on the substrate 11 using metal films, semiconductor films, etc. The signal supply unit 14H is a so-called Gate Driver Monolithic (GDM) circuit. The signal supply unit 14H includes a shift register circuit that outputs scanning signals at a predetermined timing and a buffer circuit that amplifies the scanning signals. The scanning signals are supplied from the signal supply unit 14H to the multiple scanning lines 14E in a predetermined order. The scanning signals supplied from the signal supply unit 14H to the scanning lines 14E include a potential higher than the threshold voltage of the TFT 14B.

[0047] As shown in FIG. 4 , the signal detection unit 14I is disposed near an end of the substrate 11 in the second direction and is formed in a strip-shaped area extending along the first direction. Two signal detection units 14I are disposed side by side along the first direction. Each of the two signal detection units 14I is connected to two detection wirings 14F and two common wirings 14G arranged side by side along the first direction. The signal detection unit 14I detects output signals output from the connected detection wirings 14F and is monolithically provided on the substrate 11 using metal films, semiconductor films, or the like. The signal detection unit 14I can also supply a common potential signal (reference potential signal) to the common wiring 14G.

[0048] As shown in FIG. 4 , a flexible substrate 22 is attached to the substrate 11 on which the temperature-sensing element layer 14 including the circuit configuration described above is provided. The flexible substrate 22 is configured by forming multiple wiring patterns on a base material made of an insulating and flexible synthetic resin material (e.g., polyimide resin). One end of the flexible substrate 22 is attached to an end of the substrate 11 in the second direction (a position closer to the end than the signal detection unit 14I), and the other end is attached to an external circuit board. A driver 23 is mounted on the flexible substrate 22 using a COF (chip-on-film) method. The driver 23 is an LSI chip with an internal drive circuit. The driver 23 processes various signals transmitted by the flexible substrate 22. The driver 23 controls the operation of the signal supply unit 14H and the signal detection unit 14I. A control unit 24 is connected to the driver 23 via the flexible substrate 22. The control unit 24 may be provided, for example, on the circuit board to which the flexible substrate 22 is connected. The control unit 24 will be described in detail later. The substrate 11 is provided with terminals connected to the flexible substrate 22, wiring for connecting the terminals to the signal supply unit 14H and the signal detection unit 14I, and the like, by using various metal films or the like.

[0049] Next, the configuration of the cooling unit 16 will be described in detail. As shown in FIGS. 2 and 3 , the cooling unit 16 includes a heat sink 16A thermally connected to the semiconductor chip 12 and a cooling fan 16B capable of blowing air to the heat sink 16A. The heat sink 16A and the cooling fan 16B form a single cooling unit. The heat sink 16A includes a flat base 16A1 and a plurality of protrusions 16A2 rising from the base 16A1. The base 16A1 is disposed on the main surface of the semiconductor chip 12 opposite the surface facing the rewiring layer 13, and has an area covering approximately one-quarter of the area of ​​the substrate 11. The base 16A1 is thermally connected to the semiconductor chip 12 via a heat dissipation material (heat transfer material) 16C. The heat dissipation material 16C is sandwiched between the semiconductor chip 12 and the base 16A1, contacting the main surface of the semiconductor chip 12 opposite the surface facing the redistribution layer 13 and the surface of the base 16A1 facing the semiconductor chip 12. The heat dissipation material 16C is made of, for example, a thermal interface material (TIM), specifically, a silicon-based grease containing a thermally conductive filler. The heat dissipation material 16C efficiently transfers heat generated by the semiconductor chip 12 to the base 16A1 of the heat sink 16A. The protrusions 16A2 are columnar and rise from the base 16A1 toward the side opposite the semiconductor chip 12. A plurality of the protrusions 16A2 are arranged in a matrix on the main surface of the base 16A1. The heat sink 16A has an increased surface area due to the presence of the multiple protrusions 16A2, thereby enabling efficient heat dissipation.

[0050] As shown in FIG. 2, the cooling unit 16 includes four heat sinks 16A configured as described above, each disposed on one of the semiconductor chips 12α to 12γ. Hereinafter, when distinguishing between the heat sinks 16A, one of the two heat sinks 16A disposed on the first semiconductor chip 12α will be referred to as the "first heat sink" and will be given the subscript α, the other of the two heat sinks 16A disposed on the first semiconductor chip 12α will be referred to as the "second heat sink" and will be given the subscript β, the heat sink 16A disposed on the second semiconductor chip 12β will be referred to as the "third heat sink" and will be given the subscript γ, and the heat sink 16A disposed on the two third semiconductor chips 12γ will be referred to as the "fourth heat sink" and will be given the subscript δ. When referring to the heat sinks 16A collectively without distinction, the subscripts will not be added to the reference symbols. The first heat sink 16Aα is disposed over approximately half of the first semiconductor chip 12α. The second heat sink 16Aβ is arranged to overlap approximately half of the remaining area of ​​the first semiconductor chip 12α, the third heat sink 16Aγ is arranged to overlap almost the entire area of ​​the second semiconductor chip 12β, and the fourth heat sink 16Aδ is arranged to straddle the two third semiconductor chips 12γ and overlap almost the entire areas of them.

[0051] As shown in Fig. 2, the cooling fan 16B is rotated by the drive of the motor, thereby being able to blow air toward the heat sink 16A. When air is blown from the cooling fan 16B toward the heat sink 16A, the amount of heat dissipated from the surface of the heat sink 16A increases, thereby accelerating the cooling of the semiconductor chip 12. The cooling unit 16 includes four cooling fans 16B, each capable of blowing air toward one of the four heat sinks 16A. In other words, the cooling unit 16 according to this embodiment has four cooling units, each consisting of four heat sinks 16A and four cooling fans 16B. In the following description, when distinguishing between the cooling fans 16B, the cooling fan 16B capable of blowing air to the first heat sink 16Aα will be referred to as the "first cooling fan" and will be given the suffix α, the cooling fan 16B capable of blowing air to the second heat sink 16Aβ will be referred to as the "second cooling fan" and will be given the suffix β, the cooling fan 16B capable of blowing air to the third heat sink 16Aγ will be referred to as the "third cooling fan" and will be given the suffix γ, and the cooling fan 16B capable of blowing air to the fourth heat sink 16Aδ will be referred to as the "fourth cooling fan" and will be given the suffix δ. When referring to the cooling fans 16B collectively without distinction, the suffixes will not be given to the suffixes. The first cooling fan 16Bα is disposed laterally (upper side in FIG. 2 ) with respect to the first heat sink 16Aα and can blow air at least into the spaces between the multiple protrusions 16A2 of the first heat sink 16Aα (the spaces above the base 16A1). The second cooling fan 16Bβ is disposed laterally (lower in FIG. 2) with respect to the second heat sink 16Aβ and can send air at least to the spaces between the plurality of protrusions 16A2 of the second heat sink 16Aβ. The third cooling fan 16Bγ is disposed laterally (upper in FIG. 2) with respect to the third heat sink 16Aγ and can send air at least to the spaces between the plurality of protrusions 16A2 of the third heat sink 16Aγ. The fourth cooling fan 16Bδ is disposed laterally (lower in FIG. 2) with respect to the fourth heat sink 16Aδ and can send air at least to the spaces between the plurality of protrusions 16A2 of the fourth heat sink 16Aδ.

[0052] 2 and 3, the cooling unit 16 has a partition member 16D for separating the four heat sinks 16A. The partition member 16D has four side walls 16D1 that form a cross shape in a plan view and an upper wall 16D2 that connects to the upper ends of the four side walls 16D1. As shown in FIG. 3, the four side walls 16D1 include a side wall 16D1 that separates the first heat sink 16Aα from the second heat sink 16Aβ, a side wall 16D1 that separates the first heat sink 16Aα from the third heat sink 16Aγ, a side wall 16D1 that separates the third heat sink 16Aγ from the fourth heat sink 16Aδ, and a side wall 16D1 that separates the second heat sink 16Aβ from the fourth heat sink 16Aδ. The top wall 16D2 is disposed above (opposite the semiconductor chip 12) the four heat sinks 16A. The partition member 16D thus configured divides the space above the semiconductor chip 12 into four separate heat sinks 16A. Each of these four separate spaces has two openings, opening laterally along the normal to the surface of each side wall 16D1. One of the two openings in each separate space faces the cooling fan 16B and serves as an intake port 16E that introduces air blown by the cooling fan 16B into the separate space. The other of the two openings in each separate space does not face the cooling fan 16B and serves as an exhaust port 16F that exhausts air from the separate space to the outside. The air introduced into the compartment from the intake port 16E is guided to the exhaust port 16F by the base 16A1 of the heat sink 16A and the side wall 16D1 and top wall 16D2 that constitute the partition member 16D. In this way, the partition member 16D can straighten the air blown into the compartment from the cooling fan 16B.

[0053] As shown in FIG. 4 , the control unit 24 according to this embodiment is connected to each cooling fan 16B constituting the cooling unit 16 via a motor, and is capable of controlling the operation (air-blowing state) of each cooling fan 16B. In this embodiment, the semiconductor device 10 includes a temperature sensor layer 14 including a temperature sensor 14A. Therefore, even if the amount of heat generated by the semiconductor chip 12 fluctuates depending on the type of semiconductor chip 12, the operating status of the semiconductor chip 12, or the like, the temperature sensor 14A included in the temperature sensor layer 14 can sense the temperature near the semiconductor chip 12, thereby enabling the amount of heat generated by the semiconductor chip 12 to be properly determined. The control unit 24 controls the operation of the cooling unit 16 based on the temperature information sensed by the temperature sensor 14A, thereby enabling the semiconductor chip 12 to be properly cooled. The following describes in detail the operation of the configuration according to this embodiment.

[0054] 4, the control unit 24 outputs various signals to the driver 23. The driver 23 processes the various signals output from the control unit 24 and outputs the processed signals to the signal supply unit 14H and the signal detection unit 14I. The signal detection unit 14I supplies a common potential signal to a plurality of common wirings 14G based on the signal output from the control unit 24. The common potential signal supplied to the common wirings 14G is a predetermined common potential (reference potential) that serves as a reference, and the common potential may always be constant or may periodically reverse polarity.

[0055] As shown in FIG. 4, the signal supply unit 14H sequentially supplies scanning signals to the multiple scanning lines 14E in a predetermined order based on signals input from the control unit 24. The multiple TFTs 14B connected to the scanning lines 14E are driven collectively by applying scanning signals to their gate electrodes 14B1. A common potential signal is then supplied from the common line 14G to the thermosensitive element 14A via the second connection electrode 14D. The common potential signal is then transmitted from the source electrode 14B2 of the TFT 14B to the drain electrode 14B3 via a channel region generated in the semiconductor portion 14B4, and output as an output signal to the detection line 14F via the first connection electrode 14C (see FIGS. 5 and 6). The signal detection unit 14I detects the output signal output to the detection line 14F. The output signal detected by the signal detection unit 14I is processed by the control unit 24.

[0056] Here, a potential difference may occur between the potential of the output signal from the signal detection unit 14I processed by the control unit 24 and a common potential depending on the resistance value of the temperature sensor 14A. The resistance value of the temperature sensor 14A reflects the temperature near the semiconductor chip 12, i.e., the amount of heat generated by the semiconductor chip 12. As shown in FIG. 6, heat generated in the semiconductor chip 12 is efficiently transmitted to the temperature sensor layer 14 via the rewiring 13A connected to the semiconductor chip 12, improving the sensitivity of the temperature sensor 14A to detect temperature and increasing the responsiveness of the resistance value of the temperature sensor 14A to changes in the amount of heat generated by the semiconductor chip 12. The control unit 24 can obtain temperature information near the semiconductor chip 12 by comparing the potential of the output signal with a reference common potential. In this way, since the temperature near the semiconductor chip 12 can be detected by the temperature sensor 14A, the control unit 24 can control the driving state of each motor that rotates the multiple cooling fans 16B provided in the cooling unit 16 according to the amount of heat generated by the multiple semiconductor chips 12. The number of rotations per unit time of the cooling fan 16B, i.e., the airflow state, is adjusted according to the driving state of the motor, and the heat dissipation efficiency of the heat sink 16A that receives the air from the cooling fan 16B is also adjusted. Therefore, for example, the higher the temperature sensed by the temperature sensing element 14A, the greater the amount of air blown from the cooling fan 16B is controlled by the control unit 24, thereby increasing the amount of heat dissipated from the surface of the heat sink 16A.

[0057] More specifically, scanning signals are supplied from the signal supply unit 14H to the four scanning lines 14Eα to 14Eδ in order from the top in FIG. 4. When a scanning signal is supplied to the first scanning line 14Eα, which is located at the top of FIG. 4, the first TFTs 14Bα and the third TFTs 14Bγ, which are connected to the first scanning line 14Eα and located in the top row, are driven. Then, output signals are output to the four detection lines 14F from the first thermosensitive elements 14Aα and the third thermosensitive elements 14Aγ, which are connected to the first TFTs 14Bα and the third TFTs 14Bγ, which are located in the top row, respectively. The signal detection unit 14I detects the output signals from the four detection lines 14F in synchronization with the timing at which the scanning signal is supplied to the first scanning line 14Eα. Based on the detected output signals, the control unit 24 can obtain temperature information sensed by the first and third temperature sensing elements 14Aα and 14Aγ, which are located in the uppermost row. This allows the control unit 24 to determine the amount of heat generated from the uppermost quarter of the first semiconductor chip 12α in FIG. 4 and the amount of heat generated from the upper half of the second semiconductor chip 12β in FIG. 4. Based on the determined information on the amount of heat generated, the control unit 24 controls the airflow state of the first cooling fan 16Bα and the third cooling fan 16Bγ, thereby efficiently cooling the first semiconductor chip 12α and the second semiconductor chip 12β.

[0058] When a scanning signal is supplied to the second scanning line 14Eβ, which is the second from the top in FIG. 4 , the first TFTs 14Bα and the third TFTs 14Bγ, which are connected to the second scanning line 14Eβ and located in the second row from the top, are driven. Then, output signals are output to the four detection lines 14F from the first thermosensitive elements 14Aα and the third thermosensitive elements 14Aγ, which are connected to the first TFTs 14Bα and the third TFTs 14Bγ, respectively, located in the second row from the top in FIG. The signal detection unit 14I detects the output signals from the four detection lines 14F in synchronization with the timing at which the scanning signal is supplied to the second scanning line 14Eβ. Based on the detected output signals, the control unit 24 can obtain temperature information sensed by the first thermosensitive elements 14Aα and the third thermosensitive elements 14Aγ, which are located in the second row from the top. This makes it possible to grasp the amount of heat generated from the second top quarter of the first semiconductor chip 12α in Fig. 4 and the amount of heat generated from the bottom half of the second semiconductor chip 12β in Fig. 4. Based on the grasped information on the amount of heat generated, the control unit 24 controls the airflow state of the first cooling fan 16Bα and the third cooling fan 16Bγ, thereby enabling efficient cooling of the first semiconductor chip 12α and the second semiconductor chip 12β.

[0059] When a scanning signal is supplied to the third scanning line 14Eγ, which is the third line from the top in FIG. 4 , the second TFTs 14Bβ and the fourth TFTs 14Bδ, which are connected to the third scanning line 14Eγ and located in the third row from the top, are driven. Then, output signals are output to the four detection lines 14F from the second thermosensitive elements 14Aβ and the fourth thermosensitive elements 14Aδ, which are connected to the second TFTs 14Bβ and the fourth TFTs 14Bδ, which are located in the third row from the top in FIG. 4 . The signal detection unit 14I detects the output signals from the four detection lines 14F in synchronization with the timing at which the scanning signal is supplied to the third scanning line 14Eγ. Based on the detected output signals, the control unit 24 can obtain temperature information sensed by the second thermosensitive elements 14Aβ and the fourth thermosensitive elements 14Aδ, which are located in the third row from the top. This makes it possible to grasp the amount of heat generated from the third quarter portion from the top of the first semiconductor chip 12α in Fig. 4 and the amount of heat generated from each of the upper half portions of the two third semiconductor chips 12γ in Fig. 4. Based on the grasped information on the amount of heat generated, the control unit 24 controls the airflow state of the second cooling fan 16Bβ and the fourth cooling fan 16Bδ, thereby enabling efficient cooling of the first semiconductor chip 12α and the third semiconductor chip 12γ.

[0060] When a scan signal is supplied to the fourth scan line 14Eδ, which is located at the bottom of FIG. 4 , the second TFTs 14Bβ and the fourth TFTs 14Bδ, which are connected to the fourth scan line 14Eδ and located in the bottom row, are driven. Then, output signals are output to the four detection lines 14F from the second thermosensitive elements 14Aβ and the fourth thermosensitive elements 14Aδ, which are connected to the second TFTs 14Bβ and the fourth TFTs 14Bδ, respectively, which are located in the bottom row. The signal detection unit 14I detects the output signals from the four detection lines 14F in synchronization with the timing at which the scan signal is supplied to the fourth scan line 14Eδ. Based on the detected output signals, the control unit 24 can obtain temperature information sensed by the second thermosensitive elements 14Aβ and the fourth thermosensitive elements 14Aδ, which are located in the bottom row. This makes it possible to grasp the amount of heat generated from the lowermost quarter of the first semiconductor chip 12α in Fig. 4 and the amount of heat generated from each of the lower half of the two third semiconductor chips 12γ in Fig. 4. Based on the grasped information on the amount of heat generated, the control unit 24 controls the airflow state of the second cooling fan 16Bβ and the fourth cooling fan 16Bδ, thereby enabling efficient cooling of the first semiconductor chip 12α and the third semiconductor chip 12γ.

[0061] In this embodiment, four first temperature sensors 14Aα and four second temperature sensors 14Aβ are superimposed on the large first semiconductor chip 12α, resulting in a total of eight temperature sensors 14Aα and 14Aβ arranged in a matrix on the main surface of the first semiconductor chip 12α. Therefore, by sequentially supplying scanning signals to the four scanning lines 14Eα to 14Eδ as described above and detecting output signals from each of the four first temperature sensors 14Aα and four second temperature sensors 14Aβ using the signal detector 14I, the planar temperature distribution on the main surface of the first semiconductor chip 12α can be obtained. Based on this temperature distribution on the first semiconductor chip 12α, the controller 24 feedback-controls the airflow state of the first cooling fan 16Bα and the second cooling fan 16Bβ, thereby efficiently cooling the first semiconductor chip 12α. For example, if the temperature sensed by the four first temperature sensing elements 14Aα is higher than the temperature sensed by the four second temperature sensing elements 14Aβ, the control unit 24 feedback-controls the airflow state of the first cooling fan 16Bα and 16Bβ so that the airflow rate of the first cooling fan 16Bα is greater than the airflow rate of the second cooling fan 16Bβ. This promotes cooling of the upper half of the first semiconductor chip 12α (see FIG. 4 ) more than the lower half. As a result, the power required to operate the first cooling fan 16Bα and the second cooling fan 16Bβ is reduced, and cooling of the first semiconductor chip 12α is more efficient. As described above, by utilizing temperature information sensed by the multiple temperature sensing elements 14Aα and 14Aβ arranged superimposed on one first semiconductor chip 12α, it is possible to detect local temperature increases that may occur in one first semiconductor chip 12α.

[0062] Four third temperature sensing elements 14Aγ are superimposed on the medium-sized second semiconductor chip 12β, and the four third temperature sensing elements 14Aγ are arranged in a matrix on the main surface of the second semiconductor chip 12β. Therefore, as described above, by sequentially supplying scanning signals to the first scanning wiring 14Eα and the second scanning wiring 14Eβ and detecting output signals from the four third temperature sensing elements 14Aγ using the signal detection unit 14I, the planar temperature distribution on the main surface of the second semiconductor chip 12β can be obtained. The control unit 24 can efficiently cool the second semiconductor chip 12β by feedback-controlling the airflow state of the third cooling fan 16Bγ based on this temperature distribution on the second semiconductor chip 12β. For example, by monitoring the time change in the sum of the temperatures sensed by the four third temperature sensing elements 14Aγ, the time change in the amount of heat generated by the second semiconductor chip 12β can be accurately determined. The control unit 24 can feedback-control the airflow state of the third cooling fan 16Bγ to increase or decrease the amount of airflow from the third cooling fan 16Bγ in response to an increase or decrease in the amount of heat generated from the second semiconductor chip 12β. As a result, even if a change occurs in the amount of heat generated from the second semiconductor chip 12β, the airflow state of the third cooling fan 16Bγ is feedback-controlled in response to that change, thereby reducing the power required to operate the third airflow fan 16Bγ and improving the efficiency of cooling the second semiconductor chip 12β. Similarly to the above, it is also possible to accurately grasp the time change in the amount of heat generated from the first semiconductor chip 12α by monitoring the time change in the sum of the temperatures sensed by the four first temperature sensing elements 14Aα and the four second temperature sensing elements 14Aβ, and feed this information back into the control of the airflow state of the first cooling fan 16Bα and the second cooling fan 16Bβ.

[0063] Furthermore, two fourth thermosensors 14Aδ are arranged superimposed on each of the two small third semiconductor chips 12γ. Therefore, as described above, by sequentially supplying scanning signals to the third scanning wiring 14Eγ and the fourth scanning wiring 14Eδ and detecting output signals from the four fourth thermosensors 14Aδ using the signal detection unit 14I, it is possible to obtain planar temperature distributions within each main surface of the two third semiconductor chips 12γ. The control unit 24 can efficiently cool the two third semiconductor chips 12γ by feedback-controlling the airflow state of the fourth cooling fan 16Bδ based on the temperature distributions associated with the two third semiconductor chips 12γ. For example, by monitoring the time change in the sum of the temperatures sensed by the four third thermosensors 14Aγ, it is possible to accurately grasp the time change in the sum of the heat values ​​from the two third semiconductor chips 12γ. The control unit 24 can feedback-control the airflow state of the fourth cooling fan 16Bδ so as to increase or decrease the amount of airflow from the fourth cooling fan 16Bδ in accordance with an increase or decrease in the sum of the amounts of heat generated by the two third semiconductor chips 12γ. As a result, even if a change occurs in the sum of the amounts of heat generated by the two third semiconductor chips 12γ, the airflow state of the fourth cooling fan 16Bδ is feedback-controlled in accordance with the change, thereby reducing the power required to operate the fourth cooling fan 16Bδ and improving the efficiency of cooling the third semiconductor chips 12γ.

[0064] Furthermore, according to this embodiment, the semiconductor device 10 includes a rewiring layer 13 including rewiring 13A connected to the semiconductor chip 12. This reduces the problems associated with increasing the size of the substrate 11, compared to the problem of via positional fluctuations due to thermal expansion and contraction of the substrate when connecting the chip and circuit elements through vias provided in the substrate as in the conventional case. This is advantageous for increasing the size of the substrate 11. Increasing the size of the substrate 11 is also advantageous for reducing manufacturing costs. Furthermore, the thickness of the metal film or semiconductor film formed by photolithography to form the temperature sensor 14A, TFT 14B, etc. included in the temperature sensor layer 14 is much smaller than the thickness of the rewiring 13A. Therefore, even when the substrate 11 is increased in size, warping of the substrate 11 is unlikely to occur, which is also advantageous for increasing the size of the substrate 11.

[0065] This embodiment has the above-described structure, and a method for manufacturing the semiconductor device 10 will now be described. As shown in Figure 7, the semiconductor device 10 is manufactured through a substrate formation process S1, a temperature sensor layer formation process S2, a rewiring layer formation process S3, a semiconductor chip mounting process S4, a molding process S5, and a cooling unit installation process S6. In the substrate formation process S1, a substrate 11 made of a glass material is formed by a known method. Through holes 11C are opened and formed in predetermined positions in the substrate 11.

[0066] The term "patterning" refers to film processing based on a general photolithography method. Specifically, the processing of the film to be processed, i.e., patterning, is performed by forming a photoresist film on the film to be processed, exposing the photoresist film using an exposure device through a photomask having a predetermined opening pattern, developing the photoresist film, and then etching the developed photoresist film.

[0067] In the thermosensitive element layer forming process S2, as shown in FIG. 6 , a buffer insulating film 17 is first formed on the first main surface 11A of the substrate 11. Then, a first metal film is formed on the buffer insulating film 17 and then patterned by a typical photolithography method. This forms the gate electrode 14B1, scanning line 14E, and other components of the TFT 14B. Next, a gate insulating film 18 is formed on the gate electrode 16A, the gate electrode 14B1, the scanning line 14E, and other components. Then, a semiconductor film is formed on the gate insulating film 18 and then patterned by a typical photolithography method. This forms the semiconductor portion 14B4 and other components of the TFT 14B. Next, a second metal film is formed on the semiconductor portion 14B4 and other components, and then patterned by a typical photolithography method. This forms the source electrode 14B2, the drain electrode 14B3, the detection line 14F, and other components of the TFT 14B. Next, a first interlayer insulating film 19 is formed on the upper side of the source electrode 14B2, the drain electrode 14B3, the detection wiring 14F, etc., and then patterned by a typical photolithography method. This forms a first contact hole H1 in the first interlayer insulating film 19. Next, a third metal film is formed on the upper side of the first interlayer insulating film 19, and then patterned by a typical photolithography method. This forms the first connection electrode 14C, the second connection electrode 14D, the common wiring 14G, etc. Next, a temperature sensing element film is formed on the upper side of the first connection electrode 14C, the second connection electrode 14D, the common wiring 14G, etc., and then patterned by a typical photolithography method. This forms the temperature sensing element 14A. Thereafter, the second interlayer insulating film 20 is formed on the upper layer side of the temperature sensitive element 14A, and then the second interlayer insulating film 20 is patterned by a general photolithography method. At this time, the buffer insulating film 17, the gate insulating film 18, and the first interlayer insulating film 19 are also patterned by using a photoresist film for patterning the second interlayer insulating film 20 as a mask. As a result, a communication hole H2 is opened and formed in the buffer insulating film 17, the gate insulating film 18, the first interlayer insulating film 19, and the second interlayer insulating film 20.In this way, the temperature sensing element layer 14 including the temperature sensing elements 14A is formed on the first main surface 11A of the substrate 11. The temperature sensing elements 14A included in the temperature sensing element layer 14 are arranged side by side on the first main surface 11A.

[0068] In the rewiring layer formation process S3, as shown in FIG. 6 , rewirings 13A located in the bottom layer are formed on the thermosensitive element layer 14 by a plating process or other method. The multiple rewirings 13A formed at this time include rewirings 13A formed inside the through holes H2 and the through holes 11C that communicate with each other. An interlayer insulating material 13B is then formed on the bottom rewirings 13A. Through holes 13B1 are formed at predetermined positions by laser processing the formed interlayer insulating material 13B. A second layer of rewirings 13A from the bottom is then formed by plating or other method on the surface of the formed interlayer insulating material 13B. The rewirings 13A formed at this time include rewirings 13A connected to the bottom rewirings 13A through the through holes 13B1. The interlayer insulating material 13B and the rewirings 13A are then alternately formed, and the top layer of rewirings 13A is formed, thereby forming a rewiring layer 13 on the first main surface 11A of the substrate 11.

[0069] In the semiconductor chip mounting process S4, as shown in FIG. 6 , multiple semiconductor chips 12 are placed on the rewiring layer 13, and solder balls 12A provided on the surface of each semiconductor chip 12 facing the rewiring layer 13 are brought into contact with the rewirings 13A located in the uppermost layer of the rewiring layer 13. In this state, the solder balls 12A are bonded to the rewirings 13A located in the uppermost layer. This connects each semiconductor chip 12 to the rewirings 13A. In this manner, multiple semiconductor chips 12 are provided on the first main surface 11A of the substrate 11 near the multiple temperature sensing elements 14A. The multiple semiconductor chips 12 are arranged so as to overlap the multiple temperature sensing elements 14A.

[0070] 3, the molded portion 21 is formed by molding. The molded portion 21 is formed by disposing a molded resin material so as to seal the semiconductor chip 12 connected to the rewiring 13A, and then hardening the molded resin material.

[0071] In the cooling unit installation process S6, as shown in FIG. 3, a heat dissipation material 16C is first formed on the semiconductor chip 12 and the molded portion 21. Then, multiple heat sinks 16A are attached to the heat dissipation material 16C. The multiple heat sinks 16A are arranged so as to overlap the multiple semiconductor chips 12 (see FIG. 2) and are thermally connected to the multiple semiconductor chips 12 via the heat dissipation material 16C. Then, a partition member 16D is attached to cover the multiple heat sinks 16A. The multiple heat sinks 16A are housed in multiple partitioned spaces defined by side walls 16D1 of the partition member 16D. Before or after the attachment of the partition member 16D, multiple cooling fans 16B are attached. At this time, the multiple cooling fans 16B are positioned to face the multiple air intakes 16E. Meanwhile, as shown in FIG. 4, the control unit 24 is connected to a driver 23 via a flexible substrate 22 and to the multiple cooling fans 16B via motors.

[0072] As described above, the semiconductor device 10 of this embodiment includes the semiconductor chip 12 and the temperature sensing element layer 14 including the temperature sensing element 14A that senses the temperature near the semiconductor chip 12 .

[0073] The amount of heat generated by the semiconductor chip 12 may vary depending on the type of semiconductor chip 12, the operating conditions of the semiconductor chip 12, etc. In this regard, by sensing the temperature near the semiconductor chip 12 using the temperature sensor 14A included in the temperature sensor layer 14, it becomes possible to properly grasp the amount of heat generated by the semiconductor chip 12. Based on the temperature information sensed by the temperature sensor 14A, it becomes possible to take measures such as controlling the cooling of the semiconductor chip 12.

[0074] Furthermore, a plurality of semiconductor chips 12 are arranged side by side, and a plurality of temperature sensors 14A are arranged overlapping each of the plurality of semiconductor chips 12. The plurality of temperature sensors 14A can sense the temperatures near the plurality of semiconductor chips 12. Based on the temperature information sensed by the plurality of temperature sensors 14A, it is possible to take measures such as controlling the cooling of the plurality of semiconductor chips 12.

[0075] The thermosensitive element layer 14 also includes a plurality of TFTs (switching elements) 14B connected to the plurality of thermosensitive elements 14A. By appropriately driving the plurality of TFTs 14B, it is possible to selectively sense the temperature by the thermosensitive element 14A connected to the driven TFT 14B.

[0076] The temperature sensing elements 14A and the TFTs 14B are arranged in a matrix in a plane, with multiple elements arranged in a first direction and a second direction intersecting the first direction. By driving the multiple TFTs 14B arranged in a matrix and using the temperature information sensed by the multiple temperature sensing elements 14A, it is possible to obtain a two-dimensional temperature distribution.

[0077] The thermosensitive element layer 14 also includes a plurality of scanning lines (first lines) 14E extending in the first direction, connected to the plurality of TFTs 14B aligned in the first direction, and spaced apart in the second direction, a plurality of detection lines (second lines) 14F extending in the second direction, connected to the plurality of TFTs 14B aligned in the second direction, and spaced apart in the first direction, a signal supply unit 14H connected to the plurality of scanning lines 14E, and a signal detection unit 14I connected to the plurality of detection lines 14F, the signal supply unit 14H sequentially supplies scanning signals to the plurality of scanning lines 14E to drive the plurality of TFTs 14B, and the signal detection unit 14I detects output signals output from the plurality of thermosensitive elements 14A to the plurality of detection lines 14F via the driven plurality of TFTs 14B. When the scanning signals are supplied from the signal supply unit 14H to the scanning lines 14E, the plurality of TFTs 14B connected to the scanning lines 14E are driven. Output signals from the plurality of temperature sensitive elements 14A are output to the plurality of detection wirings 14F via the plurality of driven TFTs 14B. The output signals output from the plurality of temperature sensitive elements 14A to the plurality of detection wirings 14F are detected by the signal detection unit 14I. By sequentially supplying scanning signals from the signal supply unit 14H to the plurality of scanning wirings 14E, output signals from the plurality of temperature sensitive elements 14A arranged along the first direction are sequentially detected by the signal detection unit 14I via the plurality of detection wirings 14F. This makes it possible to efficiently detect temperature information sensed by the plurality of temperature sensitive elements 14A arranged in a planar matrix.

[0078] The TFT 14B also has a semiconductor portion 14B4 made of an oxide semiconductor material. This reduces the off-leak current of the TFT 14B compared to when amorphous silicon or polysilicon is used as the semiconductor material. This reduces noise, thereby improving the temperature sensing sensitivity of the thermosensitive element 14A.

[0079] Furthermore, multiple temperature sensing elements 14A are arranged overlapping one semiconductor chip 12. By utilizing the temperature information sensed by the multiple temperature sensing elements 14A arranged overlapping one semiconductor chip 12, it becomes possible to detect local temperature increases that may occur in one semiconductor chip 12.

[0080] The temperature-sensing element 14A also includes a resistance temperature sensor, the resistance of which changes depending on the temperature, so that when a reference potential is applied to one end of the resistance temperature sensor, the potential of the signal output from the other end of the resistance temperature sensor can be compared with the reference potential to obtain temperature information.

[0081] The semiconductor device 10 also includes a rewiring layer 13 including rewiring 13A connected to the semiconductor chip 12. The rewiring 13A included in the rewiring layer 13 is connected to the semiconductor chip 12. Therefore, problems associated with an increase in size of the semiconductor device 10 are less likely to occur compared to the conventional case where the chip and the circuit element are connected through vias provided in the substrate.

[0082] The rewiring layer 13 is disposed above the temperature sensing element layer 14 and below the semiconductor chip 12. Heat generated in the semiconductor chip 12 disposed above the rewiring layer 13 is transferred to the connected rewiring 13A. The heat transferred to the rewiring 13A is then efficiently transferred to the temperature sensing element 14A of the temperature sensing element layer 14 disposed below the rewiring layer 13. This improves the sensitivity of the temperature sensing element 14A.

[0083] The device also includes a substrate 11 having a first main surface 11A and a second main surface 11B, and the semiconductor chip 12 and the temperature sensing element layer 14 are provided on the first main surface 11A of the substrate 11. Both the semiconductor chip 12 and the temperature sensing element layer 14 are provided on the first main surface 11A of the substrate 11. Therefore, heat generated in the semiconductor chip 12 on the first main surface 11A can be efficiently sensed by the temperature sensing element 14A included in the temperature sensing element layer 14 on the first main surface 11A. This improves the sensitivity of temperature sensing by the temperature sensing element 14A.

[0084] The semiconductor chip 12 also includes a cooling unit 16 thermally connected to the semiconductor chip 12 and capable of cooling the semiconductor chip 12, and a control unit 24 electrically connected to the temperature sensor 14A and the cooling unit 16, and the control unit 24 controls the cooling state of the cooling unit 16 based on information related to the temperature sensed by the temperature sensor 14A. By being cooled by the cooling unit 16, the semiconductor chip 12 is less likely to suffer from problems such as thermal runaway. The cooling state of the semiconductor chip 12 by the cooling unit 16 is controlled by the control unit 24, and information related to the temperature sensed by the temperature sensor 14A is fed back. This allows the semiconductor chip 12 to be cooled efficiently, which is advantageous for achieving low power consumption, etc.

[0085] The cooling unit 16 also includes a heat sink 16A thermally connected to the semiconductor chip 12 and a cooling fan 16B capable of blowing air to the heat sink 16A, and the control unit 24 controls the airflow state of the cooling fan 16B. Heat generated in the semiconductor chip 12 is transferred to the heat sink 16A and dissipated from the surface of the heat sink 16A. When air is blown from the cooling fan 16B to the heat sink 16A, the amount of heat dissipated from the surface of the heat sink 16A increases, thereby accelerating the cooling of the semiconductor chip 12. The control unit 24 controls the airflow state of the cooling fan 16B, thereby adjusting the cooling state of the semiconductor chip 12 by the heat sink 16A. The control unit 24 controls the cooling fan 16B based on feedback information related to the temperature sensed by the temperature sensor 14A, allowing the semiconductor chip 12 to be cooled efficiently.

[0086] Furthermore, in the method for manufacturing the semiconductor device 10 of this embodiment, the temperature sensing element layer 14 including the temperature sensing element 14A is provided, and the semiconductor chip 12 is provided in the vicinity of the temperature sensing element 14A.

[0087] The amount of heat generated by the semiconductor chip 12 may vary depending on the type of semiconductor chip 12, the operating conditions of the semiconductor chip 12, etc. In this regard, if a temperature sensor layer 14 including a temperature sensor 14A is provided and then the semiconductor chip 12 is provided near the temperature sensor 14A, the temperature sensor 14A included in the temperature sensor layer 14 can be used to sense the temperature near the semiconductor chip 12, thereby making it possible to appropriately grasp the amount of heat generated by the semiconductor chip 12. Based on the temperature information sensed by the temperature sensor 14A, it becomes possible to take measures such as controlling the cooling of the semiconductor chip 12.

[0088] Furthermore, the photosensitive element layer 14 is provided so that a plurality of photosensitive elements 14A are arranged, and a plurality of semiconductor chips 12 are provided so as to overlap the plurality of photosensitive elements 14A. The plurality of temperature sensitive elements 14A can sense the temperatures near the plurality of semiconductor chips 12, respectively. Based on the temperature information sensed by the plurality of temperature sensitive elements 14A, it is possible to take measures such as controlling the cooling of the plurality of semiconductor chips 12.

[0089] In addition, a cooling unit 16 is provided that is thermally connected to the plurality of semiconductor chips 12 and capable of cooling the plurality of semiconductor chips 12, and a control unit 24 is provided that is electrically connected to the temperature sensor 14A and the cooling unit 16 and is capable of controlling the cooling state of the cooling unit 16 based on information related to the temperature sensed by the temperature sensor 14A. By cooling the plurality of semiconductor chips 12 by the cooling unit 16, problems such as thermal runaway are less likely to occur. The cooling state of the plurality of semiconductor chips 12 by the cooling unit 16 is controlled by the control unit 24, and information related to the temperatures sensed by the plurality of temperature sensor 14A is fed back. This allows the plurality of semiconductor chips 12 to be cooled efficiently, which is advantageous for achieving low power consumption, etc.

[0090] <Embodiment 2> Embodiment 2 will be described with reference to Figures 8 to 10. In this embodiment 2, a case where the circuit configuration related to the temperature sensor 114A included in the temperature sensor layer 114 is changed is shown. Note that a redundant description of the structure, action, and effect similar to those of embodiment 1 will be omitted.

[0091] 8 and 9, the thermosensitive element layer 114 according to this embodiment does not include the TFTs 14B, scanning lines 14E, and signal supply units 14H described in the first embodiment (see FIG. 4). In other words, the thermosensitive element layer 114 includes a thermosensitive element 114A, a first connection electrode 114C, a second connection electrode 114D, a detection line 114F, a common line 114G, and a signal detection unit 114I.

[0092] As shown in FIG. 8 , the detection wiring 114F is individually associated with each thermosensitive element 114A. The number of detection wirings 114F is the same as the number of thermosensitive elements 114A, specifically 16. The detection wirings 114F extending along the second direction are arranged in groups with a gap in the first direction between them and the common wiring 114G, the number of which is equal to the number of thermosensitive elements 114A arranged in the second direction (specifically, four). The grouped four detection wirings 114F are arranged side by side with a small gap in the first direction to avoid mutual short-circuiting. The grouped four detection wirings 114F are individually connected to the four thermosensitive elements 114A arranged in the second direction. All detection wirings 114F are connected to the signal detector 114I. As shown in FIG. 9 , the detection wirings 114F are connected to the thermosensitive elements 114A via first connection electrodes 114C. On the other hand, the common wiring 114G is connected to the four thermosensors 114A arranged in the second direction via second connection electrodes 114D, as in the first embodiment.

[0093] In the following, when distinguishing between the detection wirings 114F, the detection wiring 114F connected to the first temperature sensitive element 114Aα located in the upper left of Fig. 8 will be referred to as the "first detection wiring" and will be given a subscript α1 to its reference symbol, the detection wiring 114F connected to the first temperature sensitive element 114Aα located in the lower left of Fig. 8 will be referred to as the "second detection wiring" and will be given a subscript α2 to its reference symbol, the detection wiring 114F connected to the second temperature sensitive element 114Aβ located in the upper left of Fig. 8 will be referred to as the "third detection wiring" and will be given a subscript β1 to its reference symbol, and the detection wiring 114F connected to the second temperature sensitive element 114Aβ located in the lower left of Fig. 8 will be referred to as the "fourth detection wiring" and will be given a subscript β2 to its reference symbol. The detection wiring 114F connected to the first temperature sensing element 114Aα located in the upper right of Fig. 8 is designated as the "fifth detection wiring" and has a subscript α3 added to its reference numeral, the detection wiring 114F connected to the first temperature sensing element 114Aα located in the lower right of Fig. 8 is designated as the "sixth detection wiring" and has a subscript α4 added to its reference numeral, the detection wiring 114F connected to the second temperature sensing element 114Aβ located in the upper right of Fig. 8 is designated as the "seventh detection wiring" and has a subscript β3 added to its reference numeral, and the detection wiring 114F connected to the second temperature sensing element 114Aβ located in the lower right of Fig. 8 is designated as the "eighth detection wiring" and has a subscript β4 added to its reference numeral. The detection wiring 114F connected to the third temperature sensitive element 114Aγ located in the upper left of Fig. 8 is designated as the "ninth detection wiring" and given a subscript γ1, the detection wiring 114F connected to the third temperature sensitive element 114Aγ located in the lower left of Fig. 8 is designated as the "tenth detection wiring" and given a subscript γ2, the detection wiring 114F connected to the fourth temperature sensitive element 114Aδ located in the upper left of Fig. 8 is designated as the "eleventh detection wiring" and given a subscript δ1, and the detection wiring 114F connected to the fourth temperature sensitive element 114Aδ located in the lower left of Fig. 8 is designated as the "twelfth detection wiring" and given a subscript δ2. The detection wiring 114F connected to the third temperature sensing element 114Aγ located in the upper right of Figure 8 is designated as the "13th detection wiring" and its symbol is given the suffix γ3, and the detection wiring 114F connected to the third temperature sensing element 114Aγ located in the lower right of Figure 8 is designated as the "14th detection wiring" and its symbol is given the suffix γ4.The detection wiring 114F connected to the fourth temperature sensing element 114Aδ located at the top right of Fig. 8 is designated as the "15th detection wiring" and has the subscript δ3 added to its reference numeral, and the detection wiring 114F connected to the fourth temperature sensing element 114Aδ located at the bottom right of Fig. 8 is designated as the "16th detection wiring" and has the subscript δ4 added to its reference numeral. When the detection wirings 114F are referred to collectively without distinction, no subscript is added to the reference numeral.

[0094] 10, the temperature sensitive element layer 114 does not include the gate insulating film 18 and the first interlayer insulating film 19 described in the first embodiment, nor does it include the first metal film, the semiconductor film, and the second metal film that constitute the TFT 14B (see FIG. 6). In this embodiment, the detection wiring 114F is formed from a portion of the third metal film that is separate from the first connection electrode 114C, the second connection electrode 114D, and the common wiring 114G. Therefore, the detection wiring 114F is directly connected to the first connection electrode 114C to be connected.

[0095] In this embodiment, as shown in FIGS. 8 and 9 , a common potential signal supplied from the common wiring 114G to the temperature sensing element 114A via the second connection electrode 114D is constantly output as an output signal to the detection wiring 114F via the first connection electrode 114C. Therefore, the signal detector 114I can, for example, periodically detect the output signal output to the detection wiring 114F at predetermined intervals. Furthermore, in this embodiment, the detection wirings 114Fα1 to 114Fδ4 are individually connected to the temperature sensing elements 114A to 114Aδ, and therefore the output signals from each detection wiring 114Fα1 to 114Fδ4 reflect the temperature information sensed by each of the temperature sensing elements 114Aα to 114Aδ. In this embodiment, as in the first embodiment, a two-dimensional temperature distribution can be obtained by utilizing the temperature information sensed by the multiple temperature sensing elements 114A.

[0096] 11 to 13. In this embodiment, the configuration and manufacturing method of the semiconductor device 110 are changed from those of the above-described embodiment 1. Note that redundant descriptions of the structure, operation, and effects similar to those of the above-described embodiment 1 will be omitted.

[0097] As shown in FIGS. 11 to 13 , the semiconductor device 210 according to this embodiment does not include a substrate 211 because the substrate 211 is removed by peeling (lift-off) during the manufacturing process. A brief description of the manufacturing method for the semiconductor device 210 follows. In this embodiment, as shown in FIG. 11 , after a semiconductor chip 212 is mounted on a first main surface 211A of the substrate 211, laser light is irradiated onto the substrate 211 from the second main surface 211B side (the lower side in FIG. 11 ). In the step of forming the temperature sensor layer 214 (temperature sensor layer forming step S2), which is performed prior to the formation of the semiconductor chip 212 and the rewiring layer 213, a peeling layer (not shown) is provided between the first main surface 211A of the substrate 211 and the buffer insulating film 217 of the temperature sensor layer 214. In addition, in this embodiment, in the process of forming the substrate 211 (substrate formation process S1) which is carried out prior to the formation of the temperature-sensitive element layer 214, the through hole 11C (see Figure 6) as described in embodiment 1 is not formed in the substrate 211.

[0098] When the peeling layer is irradiated with laser light, the substrate 211 becomes easy to peel from the temperature sensitive element layer 214, so as shown in Fig. 12, the substrate 211 is peeled off from the temperature sensitive element layer 214. After the substrate 211 has been peeled off, as shown in Fig. 13, solder balls 215 are provided on the lower surface of the buffer insulating film 217 of the temperature sensitive element layer 214 at positions that overlap the through holes H202. This allows the solder balls 215 to be connected to the rewiring 213A provided in the through holes H202.

[0099] As described above, according to this embodiment, the temperature sensing element layer 214, the rewiring layer 213, and the semiconductor chip 212 are provided on the first main surface 211A of the substrate 211 having the first main surface 211A and the second main surface 211B, and then the substrate 211 is peeled off. After the semiconductor chip 212 is provided, the substrate 211 is peeled off to obtain the semiconductor device 210. This is advantageous in terms of, for example, reducing the thickness of the semiconductor device 210.

[0100] Other Embodiments The technology disclosed in this specification is not limited to the embodiments described above with reference to the drawings, and the following embodiments, for example, are also included in the technical scope.

[0101] (1) The number of thermosensitive elements 14A, 114A arranged on the substrate 11, 211 (the number arranged in the first direction and the number arranged in the second direction) and their planar arrangement can be changed as appropriate, other than those shown in the drawings. In the configurations described in the first and third embodiments, the number of TFTs 14B arranged and their planar arrangement can be changed in accordance with the change in the number of thermosensitive elements 14A arranged on the substrate 11, 211 and their planar arrangement.

[0102] (2) The number of thermosensitive elements 14A, 114A installed on the semiconductor chip 12, 212 (the number of elements overlapping the semiconductor chip 12, 212) and their planar arrangement can be changed as appropriate, other than those shown in the drawings. In the configurations described in the first and third embodiments, the number of TFTs 14B installed and their planar arrangement can be changed in accordance with the change in the number of thermosensitive elements 14A installed on the semiconductor chip 12, 212 and their planar arrangement.

[0103] (3) When applying the above (1) and (2), the configuration described in embodiment 2 is particularly advantageous because it allows for greater flexibility in the number of temperature-sensing elements 114A to be installed and their planar arrangement. For example, it is possible to individually arrange the temperature-sensing elements 114A on each semiconductor chip 12. In addition, the number of temperature-sensing elements 114A superimposed on each semiconductor chip 12 and the planar arrangement of the temperature-sensing elements 114A on each semiconductor chip 12 can be changed with a high degree of freedom. Note that even in the configurations described in embodiments 1 and 3 (configurations including TFTs 14B, etc.), if the size of the semiconductor chips 12, 212 or their arrangement on the substrate 11, 211 is changed, it is also possible to individually arrange the temperature-sensing elements 14A on each semiconductor chip 12, 212.

[0104] (4) The temperature sensitive elements 14A, 114A may be arranged in a staggered pattern on a plane.

[0105] (5) The temperature sensing elements 14A and 114A may be thermocouples, linear resistors, or the like, other than resistance temperature detectors and thermistors.

[0106] (6) In the configurations described in the first and third embodiments, the common wiring 14G may extend along the first direction and be connected to the signal supply unit 14H. In this case, the signal supply unit 14H may supply a common potential signal to the common wiring 14G.

[0107] (7) In the configurations described in the first and third embodiments, the number of the signal supply units 14H and the signal detection units 14I may be one or three or more. In the configuration described in the second embodiment, the number of the signal detection units 14I may be one or three or more.

[0108] (8) In the configurations described in the first and third embodiments, the TFT 14B may be a top gate type or a double gate type in addition to a bottom gate type.

[0109] (9) The signal supply unit 14H and the signal detection unit 14I, 114I do not have to be included in the temperature sensitive element layer 14, 114, 214. In that case, for example, IC chips may be mounted on the substrate 11, 211 as the signal supply unit 14H and the signal detection unit 14I, 114I.

[0110] (10) The temperature sensitive element layer 14, 114, 214 does not need to include the first connection electrode 14C, 114C and the second connection electrode 14D, 114D. In this case, the temperature sensitive element 14A, 114A may be directly connected to the common wiring 14G, 114G or the source electrode 14B2 (the detection wiring 114F in the second embodiment).

[0111] (11) The number of heat sinks 16A and cooling fans 16B provided in the cooling unit 16, their arrangement on the board 11, 211, and their size in a plan view can be changed as appropriate to those not shown in the drawings.

[0112] (12) The heat sinks 16A may be individually superimposed on each semiconductor chip 12, 212. In this case, the size of the heat sinks 16A in plan view can be adapted to the size of the superimposed semiconductor chips 12, 212. Specifically, one large heat sink 16A can be superimposed on the large first semiconductor chip 12α. The cooling fans 16B can be installed for each heat sink 16A, and in this case, the heat sinks 16A can be individually partitioned by the partition members 16D. Specifically, when one large heat sink 16A is superimposed on the large first semiconductor chip 12α, the side walls 16D1 of the partition members 16D can be formed to ensure a partitioned space in which the large heat sink 16A can be accommodated.

[0113] (13) The cooling fans 16B do not have to be individually arranged for each heat sink 16A. For example, it is also possible to arrange one cooling fan 16B corresponding to two heat sinks 16A that overlap the first semiconductor chip 12, 212. In this case, the partition member 16D may be configured to have one partitioned space that accommodates the two heat sinks 16A. Alternatively, it is also possible to arrange one large heat sink 16A overlapping the large first semiconductor chip 12, 212, and arrange multiple cooling fans 16B corresponding to the one large heat sink 16A.

[0114] (14) The cooling unit 16 may include a heat spreader interposed between the heat sink 16A and the semiconductor chip 12, 212. The heat spreader may be made of a material with excellent thermal conductivity and may be thermally connected to the heat sink 16A and the semiconductor chip 12, 212 via heat dissipation materials.

[0115] (15) The specific configuration of the partition member 16D may be modified as appropriate beyond that shown in the drawings. For example, the partition member 16D may not have the top wall 16D2. Furthermore, the side wall 16D1 may be long enough to partially separate the heat sink 16A.

[0116] (16) The cooling unit 16 may include a Peltier element 25 thermally connected to the semiconductor chip 12, 212, instead of the heat sink 16A and the cooling fan 16B. Specifically, as shown in FIG. 14 , the Peltier element 25 is disposed above the semiconductor chip 12-1, with a heat dissipation material 16C-1 interposed therebetween, and is thermally connected to the semiconductor chip 12-1 via the heat dissipation material 16C-1. The control unit 24 can adjust the cooling state of the semiconductor chip 12-1 by the Peltier element 25 by controlling the power supply state of the Peltier element 25 based on temperature information sensed by the temperature sensing element 14A, 114A.

[0117] (17) Instead of the heat sink 16A and the cooling fan 16B, the cooling unit 16 may include a heat dissipation member 26 thermally connected to the semiconductor chip 12, 212 and a refrigerant pipe 27 thermally connected to the heat dissipation member 26. Specifically, as shown in FIG. 15 , the heat dissipation member 26 is disposed above the semiconductor chip 12-2 via a heat dissipation material 16C-2, and is thermally connected to the semiconductor chip 12-2 via the heat dissipation material 16C-2. The heat dissipation member 26 is a heat sink or heat spreader. The refrigerant pipe 27 is thermally connected to the upper side of the heat dissipation member 26 in direct contact with the heat dissipation member 26. The refrigerant pipe 27 is filled with a predetermined refrigerant 28 in a flowable state. The control unit 24 can adjust the cooling state of the semiconductor chip 12-2 by the heat dissipation member 26 by controlling the flow of the refrigerant 28 in the refrigerant pipe 27 based on temperature information sensed by the temperature sensor 14A, 114A.

[0118] (18) As a manufacturing method for the semiconductor devices 10, 110, 210, it is also possible to provide a temperature-sensitive element layer 14, 114, 214 and a rewiring layer 13, 213 on a mother substrate including a plurality of substrates 11, 211, mount the semiconductor chips 12, 212, and then divide each substrate 11, 211 to manufacture a plurality of semiconductor devices 10, 110, 210 in a batch.

[0119] (19) It is also possible to omit the driver 23 and integrate its functions into the control unit 24.

[0120] (20) The material of the substrate 11, 211 may be other than glass, for example, glass epoxy resin material.

[0121] (21) The material of the semiconductor film may be an amorphous silicon material, a polycrystalline silicon material, or a microcrystalline silicon material.

[0122] (22) The number of semiconductor chips 12, 212 provided in the semiconductor device 10, 110, 210 and the planar arrangement of the semiconductor chips 12, 212 on the substrate 11, 211 may be changed as appropriate to other than those shown in the drawings.

[0123] 10,110,210...semiconductor device, 11,211...substrate, 11A,211A...first main surface, 11B,211B...second main surface, 12,12-1,12-2,212...semiconductor chip, 13,213...rewiring layer, 13A,213A...rewiring, 14,114,214...thermosensitive element layer, 14A,114A...thermosensitive element, 14B...TFT (switching element), 14B4...semiconductor section, 14E,114E...scanning wiring (first wiring), 14F,114F...detection wiring (second wiring), 14H...signal supply section, 14I,114I...signal detection section, 16...cooling section, 16A...heat sink 16B...cooling fan, 24...control section, 25...Peltier element, 26...heat dissipation member, 27...refrigerant pipe, 28...refrigerant

Claims

1. A semiconductor device comprising: a semiconductor chip; and a temperature-sensing element layer including a temperature-sensing element that senses the temperature near the semiconductor chip.

2. The semiconductor device according to claim 1, wherein a plurality of said semiconductor chips are arranged side by side, and a plurality of said thermosensors are arranged so as to overlap with each of said plurality of semiconductor chips.

3. The semiconductor device according to claim 2, wherein said thermosensitive element layer includes a plurality of switching elements connected to a plurality of said thermosensitive elements.

4. The semiconductor device according to claim 3, wherein the temperature sensitive elements and the switching elements are arranged in a matrix on a plane in a first direction and a second direction intersecting the first direction.

5. The semiconductor device according to claim 4, wherein the thermosensitive element layer includes: a plurality of first wirings extending along the first direction and connected to a plurality of the switching elements lined up along the first direction, and spaced apart in the second direction; a plurality of second wirings extending along the second direction and connected to a plurality of the switching elements lined up along the second direction, and spaced apart in the first direction; a signal supply unit connected to a plurality of the first wirings; and a signal detection unit connected to a plurality of the second wirings, wherein the signal supply unit sequentially supplies scanning signals to a plurality of the first wirings for driving a plurality of the switching elements, and the signal detection unit detects output signals output from a plurality of the thermosensitive elements to a plurality of the second wirings via a plurality of the driven switching elements.

6. The semiconductor device according to any one of claims 3 to 5, wherein the switching element has a semiconductor portion made of an oxide semiconductor material.

7. The semiconductor device according to any one of claims 1 to 5, wherein a plurality of the thermosensitive elements are arranged in a superimposed manner on one of the semiconductor chips.

8. A semiconductor device according to any one of claims 1 to 5, wherein the temperature sensitive element includes a resistance temperature sensor.

9. The semiconductor device according to any one of claims 1 to 5, further comprising a rewiring layer including rewiring connected to the semiconductor chip.

10. The semiconductor device according to claim 9, wherein the rewiring layer is disposed above the temperature sensitive element layer and below the semiconductor chip.

11. A semiconductor device according to any one of claims 1 to 5, comprising a substrate having a first main surface and a second main surface, wherein the semiconductor chip and the temperature sensing element layer are provided on the first main surface of the substrate.

12. A semiconductor device as described in any one of claims 1 to 5, comprising: a cooling unit thermally connected to the semiconductor chip and capable of cooling the semiconductor chip; and a control unit electrically connected to the temperature sensor and the cooling unit, wherein the control unit controls the cooling state of the cooling unit based on information related to the temperature sensed by the temperature sensor.

13. The semiconductor device according to claim 12, wherein the cooling unit has a heat sink thermally connected to the semiconductor chip and a cooling fan capable of blowing air to the heat sink, and the control unit controls the airflow state of the cooling fan.

14. The semiconductor device according to claim 12, wherein the cooling section has a Peltier element thermally connected to the semiconductor chip, and the control section controls the energization state of the Peltier element.

15. A semiconductor device according to claim 12, wherein the cooling unit has a heat dissipation member thermally connected to the semiconductor chip and a refrigerant pipe thermally connected to the heat dissipation member, and the control unit controls the flow of refrigerant in the refrigerant pipe.

16. A method for manufacturing a semiconductor device, comprising providing a temperature sensing element layer including a temperature sensing element, and providing a semiconductor chip in the vicinity of the temperature sensing element.

17. The method for manufacturing a semiconductor device according to claim 16, wherein the photosensitive element layer is provided so that a plurality of the photosensitive elements are arranged, and a plurality of the semiconductor chips are provided so as to overlap the plurality of the photosensitive elements.

18. A method for manufacturing a semiconductor device as described in claim 17, further comprising providing a cooling unit that is thermally connected to a plurality of said semiconductor chips and is capable of cooling said plurality of semiconductor chips, and providing a control unit that is electrically connected to said temperature sensor and said cooling unit and is capable of controlling the cooling state of said cooling unit based on information related to the temperature sensed by said temperature sensor.

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