Photodetector and electronic equipment

Abstract

A photodetector according to one embodiment of the present disclosure comprises a first substrate and a second substrate. The first substrate has a first photoelectric conversion element including a first photoelectric conversion portion that generates a first charge by photoelectrically converting light, a first pad including a first bonding surface along a first plane, and a first via extending in a first direction intersecting the first plane. The second substrate has a second pad including a second bonding surface bonded to the first bonding surface, and a second via electrically connected to the second pad and extending in the first direction from the second pad. The first photoelectric conversion element and the first pad are electrically connected through the first via. The entirety of a first pad occupation region occupied by the first pad on the first plane overlaps in the first direction with a first via occupation region occupied by the first via on the first plane.

Description

Photodetector and electronic equipment

[0001] The present disclosure relates to photodetector devices and electronic devices having multiple semiconductor layers stacked on top of one another.

[0002] For example, Non-Patent Document 1 discloses a CMOS image sensor having a three-layer structure in which a top wafer including a photodiode, a transfer gate, etc., a mid-wafer including pixel transistors, and a bottom wafer including a logic circuit are stacked.

[0003] Gwi-Deok Ryan Lee et al., “A 0.5μm Pixel 3-layer Stacked CMOS Image Sensor with Deep Contact and In-pixel Cu-Cu Bonding Technology”, 2023 International Electron Devices Meeting (IEDM).

[0004] Such photodetectors are required to be highly integrated without impairing the photodetection performance.

[0005] Therefore, it is desirable to provide a photodetector and electronic equipment that can achieve both improved performance and high integration.

[0006] A first photodetector according to an embodiment of the present disclosure includes a first substrate and a second substrate. The first substrate has a first opposing surface along a first plane, a first photoelectric conversion element including a first photoelectric conversion unit that generates a first charge by photoelectrically converting light, a first pad including a first bonding surface included in the first opposing surface, and a first via extending in a first direction intersecting the first plane. The second substrate has a second opposing surface opposite the first opposing surface, a second pad including a second bonding surface included in the second opposing surface and bonded to the first bonding surface, and a second via electrically connected to the second pad and extending from the second pad in the first direction. The first photoelectric conversion element and the first pad are electrically connected via the first via. A first pad occupation area occupied by the first pad in the first plane entirely overlaps a first via occupation area occupied by the first via in the first plane in the first direction.

[0007] A first electronic device according to an embodiment of the present disclosure includes the first photodetector according to the embodiment.

[0008] In the first photodetector and the first electronic device according to the embodiment of the present disclosure, the entire first pad-occupied area in the first plane, which is occupied by the first pad, overlaps in the first direction with the first via-occupied area in the first plane, which is occupied by the first via, thereby reducing parasitic capacitance between the first via and the semiconductor or conductor surrounding the first via, thereby improving the photoelectric conversion efficiency of the first photoelectric conversion element.

[0009] A second photodetector according to an embodiment of the present disclosure includes a first substrate, a second substrate, and a via. The first substrate includes a first opposing surface along a first plane, and a first photoelectric conversion element is provided thereon. The second substrate includes a second opposing surface bonded to the first opposing surface, and a first semiconductor element is provided thereon. The via extends in a first direction intersecting the first plane in the first substrate and the second substrate so as to penetrate both the first opposing surface and the second opposing surface. Here, the first photoelectric conversion element and the first semiconductor element are electrically connected via the via.

[0010] A second electronic device according to an embodiment of the present disclosure includes the second photodetector according to the embodiment.

[0011] In a second photodetector and a second electronic device according to an embodiment of the present disclosure, the first substrate and the second substrate are provided with vias extending in a first direction intersecting the first plane so as to penetrate both the first bonding surface and the second bonding surface. This reduces parasitic capacitance between the vias and the semiconductors or conductors surrounding the vias. As a result, the photoelectric conversion efficiency of the first photoelectric conversion element is improved. Furthermore, in the second photodetector and the second electronic device, the vias penetrate both the first opposing surface and the second opposing surface. This reduces variations in resistance due to manufacturing errors, etc., compared to when vias are provided in both the first substrate and the second substrate and the vias of the first substrate are bonded directly or via pads.

[0012] 6A is a block diagram illustrating an example of a functional configuration of an imaging device according to a first embodiment of the present disclosure. FIG. 6B is an equivalent circuit diagram of a pixel shared unit illustrated in FIG. 1. FIG. 6C is a schematic diagram illustrating a process following FIG. 6D. FIG. 6E is a schematic diagram illustrating a process following FIG. 6F. FIG. 6G is a schematic diagram illustrating a process following FIG. 6H. FIG. 6I is a schematic diagram illustrating a process following FIG. 6J. 6K. FIG. 6L. FIG. 6M. FIG. 6N. FIG. 6O. FIG. 6P ... FIG. 13 is a schematic diagram illustrating an example of a cross-sectional layer configuration of an imaging device as a seventh modified example of the second embodiment.12A is a schematic diagram showing an example of a laminated cross-sectional configuration of an imaging device as an eighth modified example of the second embodiment. FIG. 13 is a schematic diagram showing an example of a horizontal cross-sectional configuration of an imaging device as a ninth modified example of the second embodiment. FIG. 14 is a block diagram showing an example of a configuration of an electronic device having the imaging device shown in FIG. 1. FIG. 15 is a schematic diagram showing an example of the overall configuration of an optical detection system using the imaging device shown in FIG. 1 etc.. FIG. 16 is a diagram showing an example of a circuit configuration of the optical detection system shown in FIG. 12A. FIG. 17 is a diagram showing an example of a schematic configuration of an endoscopic surgery system. FIG. 18 is a block diagram showing an example of the functional configuration of a camera head and a CCU. FIG. 19 is a block diagram showing an example of a schematic configuration of a vehicle control system. FIG. 19 is an explanatory diagram showing an example of the installation positions of an outside-vehicle information detection unit and an imaging unit.

[0013] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. The description will be made in the following order: 1. First embodiment 2. Second embodiment 3. Application example 4. Application example

[0014] 1. First Embodiment Functional Configuration of Imaging Device 1 FIG. 1 is a block diagram showing an example of the overall configuration of an imaging device 1 as a specific example of a light detection device according to a first embodiment of the present disclosure. The imaging device 1 is a device that receives incident light and performs photoelectric conversion. The imaging device 1 photoelectrically converts the received light to generate a signal. The imaging device 1 captures incident light (image light) from a subject via, for example, an optical lens system. The imaging device 1 is, for example, a CMOS (Complementary Metal Oxide Semiconductor) image sensor, and captures an image of the subject.

[0015] The imaging device 1 has a pixel array section 240 in which a plurality of pixels P are arranged in a matrix. That is, the pixel array section 240 is a region in which the pixels P are repeatedly arranged in an array. Each of the plurality of pixels P has a photoelectric conversion section. The imaging device 1 has, in a peripheral region of the pixel array section 240, for example, an input section 210, a row driving section 220, a timing control section 230, a column signal processing section 250, an image signal processing section 260, and an output section 270.

[0016] In the imaging device 1, pixel-sharing units 40 each including a plurality of pixels P are repeatedly arranged in an array. More specifically, pixel-sharing units 40 each including a plurality of pixels P are arranged as a repeating unit in both the row and column directions. In the example shown in FIG. 1 , the pixel-sharing unit 40 includes four pixels (pixel Pa, pixel Pb, pixel Pc, and pixel Pd). The pixels Pa to Pd are arranged in, for example, two rows and two columns. Each of the pixels Pa to Pd has, for example, a photodiode PD as a photoelectric conversion unit.

[0017] In the imaging device 1, a readout circuit 45 (see FIG. 2 , described below) is provided for each pixel-shared unit 40. The readout circuit includes semiconductor elements such as an amplifier transistor and a reset transistor. The readout circuit outputs a pixel signal based on the charge photoelectrically converted by the photoelectric conversion unit of each pixel P. The pixel-shared unit 40 is a unit that shares one readout circuit, and multiple pixels P (pixels Pa to Pd in ​​FIG. 1 ) of the pixel-shared unit 40 share one readout circuit. In the pixel array section 240, one readout circuit is provided for every four pixels (pixels Pa to Pd). The pixel signals of each of the pixels Pa to Pd are read out by operating the readout circuit in a time-division manner.

[0018] As shown in FIG. 1 , the imaging device 1 is provided with a plurality of row drive signal lines Lread (row selection lines, reset control lines, etc.) and a plurality of vertical signal lines (column readout lines) Lsig. For example, in the pixel array section 240, a row drive signal line Lread is wired for each pixel row made up of a plurality of pixels P lined up in the horizontal direction (row direction). In addition, in the pixel array section 240, a vertical signal line Lsig is wired for each pixel column made up of a plurality of pixels P lined up in the vertical direction (column direction). The row drive signal line Lread transmits, for example, a signal that drives each transistor in the pixel sharing unit 40. Pixel signals can be read out from each of the pixels Pa to Pd included in the pixel sharing unit 40 onto the vertical signal line Lsig.

[0019] The row driver 220 is configured with a shift register, an address decoder, etc. The row driver 220 generates drive signals for driving the pixels P and outputs the drive signals to each pixel sharing unit 40 of the pixel array section 240 via a row drive signal line Lread. The row driver 220 generates, for example, a signal TRGs that controls a transfer transistor, a signal SELs that controls a selection transistor, and a signal RSTs that controls a reset transistor, and outputs the signals TRGs, SELs, and RSTs to each pixel sharing unit 40 via the row drive signal line Lread.

[0020] As described above, the row drive signal line Lread transmits drive signals (such as signals TRGs, SELs, and RSTs) from the pixels P. The row drive unit 220 is a row address control unit that selects and scans each pixel P in the pixel array unit 240, and drives, for example, a plurality of pixels P arranged in the pixel array unit 240 on a row-by-row basis. The pixel signals of each pixel P selected and scanned by the row drive unit 220 are output to the column signal processing unit 250 via vertical signal lines Lsig connected to the respective pixels P.

[0021] The column signal processing unit 250 has, for example, a load circuit unit connected to the vertical signal line Lsig. The load circuit unit configures a source follower circuit together with an amplification transistor of the readout circuit. The column signal processing unit 250 may also have an amplifier circuit unit that amplifies pixel signals read out from the pixel sharing unit 40 via the vertical signal line Lsig. The column signal processing unit 250 may also have a noise processing unit that removes noise components from the pixel signals.

[0022] The column signal processing unit 250 also includes an analog-to-digital converter (ADC). The ADC includes, for example, a comparator unit and a counter unit. The comparator unit compares an analog signal to be converted with a reference signal to be compared with the analog signal. The counter unit measures the time until the comparison result of the comparator unit is inverted.

[0023] The ADC of the column signal processing unit 250 converts the pixel signals, which are analog signals output from the pixel sharing units 40, into digital signals. The ADC may perform A / D conversion on pixel signals before noise processing by the noise processing unit, or may perform A / D conversion on pixel signals after noise processing by the noise processing unit. The column signal processing unit 250 may include a horizontal scanning circuit unit that controls scanning of the readout columns.

[0024] The timing control unit 230 supplies signals for controlling timing to the row driving unit 220 and the column signal processing unit 250 based on, for example, a reference clock signal and a timing control signal input from outside to the imaging device 1. The timing control signals are, for example, a vertical synchronization signal and a horizontal synchronization signal. The timing control unit 230 has, for example, a timing generator that generates various timing signals, and performs drive control of the row driving unit 220, the column signal processing unit 250, etc. based on the various generated timing signals.

[0025] The image signal processing unit 260 is a circuit that performs various signal processing on pixel signals. The image signal processing unit 260 may include a processor and memory. For example, the image signal processing unit 260 performs signal processing on the AD-converted pixel signals, such as black level adjustment and tone curve correction processing for adjusting gradation. Note that characteristic data of the tone curve indicating the amount of gradation correction may be stored in advance in the internal memory of the image signal processing unit 260.

[0026] The input unit 210 and the output unit 270 exchange signals with the outside. For example, the above-mentioned reference clock signal, timing control signal, characteristic data, etc. are input to the input unit 210 from outside the imaging device 1. The output unit 270 can output, to the outside, for example, pixel signals after signal processing by the image signal processing unit 260 or pixel signals before signal processing by the image signal processing unit.

[0027] FIG. 2 is an equivalent circuit diagram showing an example configuration of a pixel-shared unit 40 of an imaging device 1 according to an embodiment of the present disclosure. The pixel-shared unit 40 includes a plurality of pixels P (Pa to Pd), one readout circuit 45 connected to the plurality of pixels P, and a vertical signal line Lsig connected to the readout circuit 45. Below, an example will be described in which four pixels P (Pa to Pd) share one readout circuit 45, as shown in FIGS. 1 and 2 . Each of the four pixels Pa to Pd has a photoelectric conversion element 112 (112a to 112d). The photoelectric conversion element 112 (112a to 112d) has a photodiode PD (PD1 to PD4) that serves as a photoelectric conversion unit, a transfer transistor TR (TR1 to TR4), and a floating diffusion FD (FD1 to FD4).

[0028] The readout circuit 45 includes, for example, a reset transistor RST, an FD conversion gain switching transistor FDG, an amplification transistor AMP, and a selection transistor SEL. The pixel-sharing unit 40 operates one readout circuit 45 in a time-division manner to sequentially output pixel signals from each of the four pixels Pa to Pd included in the pixel-sharing unit 40 to the vertical signal line Lsig. In this manner, one readout circuit 45 is connected to the four pixels Pa to Pd, and the pixel signals of the four pixels Pa to Pd are output by the single readout circuit 45 in a time-division manner, which is referred to as a state in which a plurality of pixels P share one readout circuit 45.

[0029] The photodiodes PD1 to PD4, which are photoelectric conversion units, convert incident light into electric charges. The photodiodes PD1 to PD4 perform photoelectric conversion and generate electric charges according to the amount of light received. The cathodes of the photodiodes PD1 to PD4 are electrically connected to the sources of the transfer transistors TR1 to TR4, and the anodes of the photodiodes PD1 to PD4 are electrically connected to a reference potential line (e.g., ground GND).

[0030] The transfer transistors TR1 to TR4 are electrically connected to the photodiodes PD1 to PD4. The transfer transistors TR1 to TR4 are, for example, n-type CMOS (Complementary Metal Oxide Semiconductor) transistors. The drains of the transfer transistors TR1 to TR4 are electrically connected to the floating diffusions FD1 to FD4, and the gates of the transfer transistors TR1 to TR4 are electrically connected to drive signal lines. These drive signal lines are part of the multiple row drive signal lines Lread (see FIG. 1) connected to one pixel sharing unit 40. The transfer transistors TR1 to TR4 are controlled by signals TRG1 to TRG4, respectively, and transfer the charges photoelectrically converted and accumulated in the photodiodes PD1 to PD4 to the floating diffusions FD1 to FD4.

[0031] The floating diffusions FD1 to FD4 are n-type diffusion layer regions formed in a p-type semiconductor layer. The floating diffusions FD1 to FD4 are charge holding units that hold the charges transferred from the photodiodes PD1 to PD4. The floating diffusions FD1 to FD4 can also be considered charge storage units that accumulate the charges transferred from the photodiodes PD1 to PD4. The floating diffusions FD1 to FD4 accumulate the transferred charges and convert them into voltages that correspond to the capacitance of the floating diffusions FD1 to FD4. The charges converted by the photodiodes PD1 to PD4 are transferred to the floating diffusions FD1 to FD4 by the transfer transistors TR1 to TR4, respectively, and converted into voltages that correspond to the capacitance of the floating diffusions FD1 to FD4.

[0032] The four floating diffusions FD1 to FD4 included in one pixel-shared unit 40 are electrically connected to each other and to the gate of the amplification transistor AMP and the source of the FD conversion gain switching transistor FDG. The drain of the FD conversion gain switching transistor FDG is connected to the source of the reset transistor RST, and the gate of the FD conversion gain switching transistor FDG is connected to a drive signal line. This drive signal line is part of the multiple row drive signal lines Lread connected to one pixel-shared unit 40. The drain of the reset transistor RST is connected to a power supply line VDD, and the gate of the reset transistor RST is connected to the drive signal line. This drive signal line is part of the multiple row drive signal lines Lread connected to one pixel-shared unit 40. The gate of the amplification transistor AMP is connected to the floating diffusions FD1 to FD4, the drain of the amplification transistor AMP is connected to the power supply line VDD, and the source of the amplification transistor AMP is connected to the drain of the selection transistor SEL. The source of the selection transistor SEL is connected to a vertical signal line 543, and the gate of the selection transistor SEL is connected to a drive signal line. This drive signal line is part of a plurality of row drive signal lines Lread connected to one pixel sharing unit 40.

[0033] When the transfer transistors TR1 to TR4 are turned on, they transfer the charges in the photodiodes PD1 to PD4 to the floating diffusions FD1 to FD4. The reset transistor RST resets the potentials of the floating diffusions FD1 to FD4 to a predetermined potential. When the reset transistor RST is turned on, the potentials of the floating diffusions FD1 to FD4 are reset to the potential of the power supply line VDD. The selection transistor SEL controls the output timing of pixel signals from the readout circuit 45. The amplification transistor AMP generates, as pixel signals, voltage signals corresponding to the level of the charges held in the floating diffusions FD1 to FD4. The amplification transistor AMP is connected to the vertical signal line Lsig via the selection transistor SEL. In the column signal processing unit 250, the amplification transistor AMP forms a source follower together with a load circuit connected to the vertical signal line Lsig. When the selection transistor SEL is turned on, the amplification transistor AMP outputs the voltages of the floating diffusions FD1 to FD4 via the vertical signal line Lsig to the column signal processing unit 250. The reset transistor RST, the amplification transistor AMP, and the selection transistor SEL are, for example, N-type CMOS transistors.

[0034] The FD conversion gain switching transistor FDG is used to change the gain of charge-to-voltage conversion in the floating diffusions FD1 to FD4. Generally, pixel signals are small when capturing images in dark locations. Based on Q = CV, if the capacitance (FD capacitance C) of the floating diffusions FD1 to FD4 is large during charge-to-voltage conversion, the V when converted to a voltage by the amplifier transistor AMP will be small. On the other hand, in bright locations, pixel signals are large, so if the FD capacitance C is not large, the floating diffusions FD1 to FD4 will not be able to fully accept the charge from the photodiodes PD1 to PD4. Furthermore, it is desirable to have a large FD capacitance C so that the V when converted to a voltage by the amplifier transistor AMP does not become too large (in other words, to make it small). Taking these factors into consideration, when the FD conversion gain switching transistor FDG is turned on, the gate capacitance of the FD conversion gain switching transistor FDG increases, increasing the overall FD capacitance C. On the other hand, when the FD conversion gain switching transistor FDG is turned off, the overall FD capacitance C decreases. In this way, by switching the FD conversion gain switching transistor FDG on and off, it is possible to change the FD capacitance C and switch the conversion efficiency. The FD conversion gain switching transistor FDG is, for example, an N-type CMOS transistor.

[0035] It is also possible to configure the circuit 45 without the FD conversion gain switching transistor FDG. In this case, for example, the readout circuit 45 is configured with three transistors, for example, an amplification transistor AMP, a selection transistor SEL, and a reset transistor RST. The readout circuit 45 has at least one pixel transistor, for example, the amplification transistor AMP, the selection transistor SEL, the reset transistor RST, and the FD conversion gain switching transistor FDG.

[0036] The select transistor SEL may be provided between the power supply line VDD and the amplifier transistor AMP. In this case, the drain of the reset transistor RST is electrically connected to the power supply line VDD and the drain of the select transistor SEL. The source of the select transistor SEL is electrically connected to the drain of the amplifier transistor AMP, and the gate of the select transistor SEL is electrically connected to the row drive signal line Lread. The source of the amplifier transistor AMP (the output terminal of the readout circuit 45) is electrically connected to the row drive signal line Lread, and the gate of the amplifier transistor AMP is electrically connected to the source of the reset transistor RST. Note that the number of pixels P sharing one readout circuit 45 may be other than four. For example, two or eight pixels p may share one readout circuit 45.

[0037] [Schematic Configuration of Imaging Device 1] FIG. 3 is a cross-sectional view of a layer structure illustrating an example of the schematic configuration of the imaging device 1. FIG. 3 is a schematic view for easily understanding the positional relationships of the components, and may differ from the actual cross section. The imaging device 1 has a structure in which three substrates, namely, a first substrate 101, a second substrate 102, and a third substrate 103, are stacked in this order. The first substrate 101, the second substrate 102, and the third substrate 103 each include a semiconductor substrate such as a silicon (Si) substrate. Note that in this specification, the stacking direction of the first substrate 101, the second substrate 102, and the third substrate 103 is referred to as the Z-axis direction. The Z-axis direction coincides with the direction of incidence of light from the subject. The left-right direction on the page perpendicular to the Z-axis direction is referred to as the X-axis direction, and the direction perpendicular to the Z-axis and X-axis is referred to as the Y-axis direction. In the following figures, directions may be indicated based on the direction of the arrow in FIG. 3.

[0038] The first substrate 101 has a light-receiving layer 110 and a wiring portion 111. The second substrate 102 has a semiconductor layer 120, a wiring portion 121, and a wiring portion 122. The third substrate 103 has a semiconductor layer 130 and a wiring portion 131. The light-receiving layer 110, the semiconductor layer 120, and the semiconductor layer 130 have first surfaces 11S1, 12S1, and 13S1 and second surfaces 11S2, 12S2, and 13S2. The first surfaces 11S1, 12S1, and 13S1 and the second surfaces 11S2, 12S2, and 13S2 all extend along the XY plane.

[0039] Each of the first surfaces 11S1, 12S1, and 13S1 is an element formation surface on which a semiconductor element such as a transistor is provided. For example, a gate electrode, a gate oxide film, a source / drain region, etc. of the transistor are provided on each of the first surfaces 11S1, 12S1, and 13S1. For example, a transfer transistor TR, a floating diffusion FD, etc. are provided on the first surface 11S1 of the light-receiving layer 110. Furthermore, an amplifier transistor AMP, a select transistor SEL, etc. are provided on the first surface 12S1 of the semiconductor layer 120.

[0040] In the first substrate 101, a photodiode PD is provided in the light-receiving layer 110. A wiring section 111 is laminated on the first surface 11S1 of the light-receiving layer 110. In the second substrate 102, a wiring section 121 is laminated on the first surface 12S1 of the semiconductor layer 120, and a wiring section 122 is laminated on the second surface 12S2 of the second substrate 102. Furthermore, in the third substrate 103, a wiring section 131 is laminated on the first surface 13S1 of the semiconductor layer 130. The wiring sections 111, 121, 122, and 131 each include, for example, a conductor film and an insulating film, and have multiple wirings, vias, and the like. Each of the wiring sections 111, 121, 122, and 131 includes, for example, two or more layers of wiring. Each of the wiring sections 122 and 131 may include three or more layers of wiring.

[0041] The wiring portions 111, 121, 122, and 131 each have a configuration in which, for example, one or more wiring layers are stacked with an interlayer insulating film between them. Specifically, in the wiring portion 111, for example, wiring layers 11M1, 11M2, and 11M3 are stacked in order from the opposing surface 101S1 (described later) side and embedded in the interlayer insulating film 11Z. In addition, in the wiring portion 121, for example, wiring layers 21M1, 21M2, and 21M3 are stacked in order from the opposing surface 102S1 (described later) side and embedded in the interlayer insulating film 21Z. In addition, in the wiring portion 122, for example, wiring layers 22M1 and 22M2 are stacked in order from the opposing surface 102S2 (described later) side and embedded in the interlayer insulating film 22Z. Furthermore, in the wiring portion 131, for example, wiring layers 31M1, 31M2, 31M3, 31M4, and 31M5 are laminated in this order from the opposing surface 103S1 (described later) side and are embedded in an interlayer insulating film 31Z. Note that in this specification, the wiring layers included in the wiring portions 111, 121, 122, and 131 may be collectively referred to as wiring layers M. Also, in this specification, the interlayer insulating films included in the wiring portions 111, 121, 122, and 131 may be collectively referred to as interlayer insulating films Z.

[0042] Each wiring layer M of the wiring portions 111, 121, 122, and 131 is formed using, for example, aluminum (Al), copper (Cu), tungsten (W), polysilicon (Poly-Si), etc. Each interlayer insulating film Z of the wiring portions 111, 121, 122, and 131 is formed, for example, by a single layer film made of one type of silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), etc., or a stacked film made of two or more types of these.

[0043] The first substrate 101 and the second substrate 102 are stacked such that a first surface 11S1, which is an element formation surface on which elements such as transistors are formed, and a second surface 12S2 opposite the element formation surface face each other by bonding between electrodes. That is, the first substrate 101 and the second substrate 102 are bonded such that the front surface of the first substrate 101 and the back surface of the second substrate 102 face each other. This bonding method is called face-to-back bonding. Specifically, a facing surface 101S1, which is the front surface of the first substrate 101 and is the surface of the wiring portion 111 opposite the light receiving layer 110, is bonded to a facing surface 102S2, which is the back surface of the second substrate 102 and is the surface of the wiring portion 122 opposite the semiconductor layer 120. The first substrate 101 and the second substrate 102 may also be bonded to each other by so-called hybrid bonding. That is, the wiring layer 11M1 as an electrode exposed on the opposing surface 101S1 and the wiring layer 22M1 as an electrode exposed on the opposing surface 102S2 are bonded, and the interlayer insulating film 11Z exposed on the opposing surface 101S1 and the interlayer insulating film 22Z exposed on the opposing surface 102S2 are bonded. When the wiring layer 11M1 and the wiring layer 22M1 are both made of copper (Cu), the bond between the wiring layer 11M1 and the wiring layer 22M1 is sometimes called a Cu-Cu bond. Note that the electrodes used for the bond may be made of a metal material other than copper (Cu), such as nickel (Ni), cobalt (Co), or tin (Sn), or may be made of other materials. Furthermore, a metal oxide film containing a metal element such as Ta (tantalum), Hf (hafnium), W (tungsten), or Al (aluminum) may be provided as an anti-reflection film or a light-shielding film on the second surface 12S2, which is, for example, the back surface of the semiconductor layer 120. Note that the opposing surface 101S1 is a specific example corresponding to an embodiment of the "first opposing surface" of the present disclosure, and the opposing surface 102S2 is a specific example corresponding to an embodiment of the "second opposing surface" of the present disclosure.

[0044] Meanwhile, the second substrate 102 and the third substrate 103 are stacked such that the first surfaces 12S1 and 13S1, on which elements such as transistors are formed, face each other by bonding between the electrodes. That is, the second substrate 102 and the third substrate 103 are bonded such that their respective surfaces face each other. This bonding method is called face-to-face bonding. Specifically, a facing surface 102S1, which is the surface of the second substrate 102 that is the surface of the wiring portion 121 opposite the semiconductor layer 120, is bonded to a facing surface 103S1, which is the surface of the third substrate 103 that is the surface of the wiring portion 131 opposite the semiconductor layer 130. The second substrate 102 and the third substrate 103 may also be bonded to each other by so-called hybrid bonding. That is, the wiring layer 21M1 as an electrode exposed on the opposing surface 102S1 and the wiring layer 31M1 as an electrode exposed on the opposing surface 103S1 are bonded, and the interlayer insulating film 21Z exposed on the opposing surface 102S1 and the interlayer insulating film 31Z exposed on the opposing surface 103S1 are bonded. When the wiring layer 21M1 and the wiring layer 31M1 are both made of copper (Cu), the bond between the wiring layer 21M1 and the wiring layer 31M1 is sometimes called a Cu-Cu bond. Note that the electrodes used for the bond may be made of a metal material other than copper (Cu), such as nickel (Ni), cobalt (Co), or tin (Sn), or may be made of other materials.

[0045] In the imaging device 1, the photodiode PD, transfer transistor TR, and floating diffusion FD described above are disposed on the first substrate 101, and the readout circuit 45 is disposed on the second substrate 102. Because the photodiode PD and the readout circuit 45 are disposed on separate substrates, the photodiode PD can be made sufficiently large compared to when the photodiode PD and the readout circuit 45 are disposed on the same substrate. This enables images with a wide dynamic range to be acquired. The first substrate 101 may have a color filter CF, for example, on the light incident side of the photodiode PD, i.e., on the side opposite the wiring unit 111 as viewed from the photodiode PD. Furthermore, an on-chip lens OCL may be provided on the second surface 11S2 of the first substrate 101. The third substrate 103 may be disposed with, for example, the row driver 220, timing controller 230, column signal processor 250, and image signal processor 260 described above. The input unit 210 and output unit 270 described above may also be disposed on the third substrate 103.

[0046] The first substrate 101 has an opposing surface 101S1 along the XY plane, a photoelectric conversion element 12 including a photodiode PD and the like, a first pad P1, and a first via V1. The first pad P1 includes a first bonding surface S1 included in the opposing surface 101S1. The first via V1 extends in the Z-axis direction. The photoelectric conversion element 112 and the first pad P1 are electrically connected via the first via V1. More specifically, the floating diffusions FD (FD1 to FD4) of the four photoelectric conversion elements 112 (112a to 112d) are electrically connected to the first pad P1 via the first via V1. In other words, the first pad P1 and the first via V1 are shared by the four photoelectric conversion elements 112 (112a to 112d). 3, the first via V1 and the floating diffusion FD are connected via the wiring layer 11M3 or the like, but the first via V1 may also electrically connect the floating diffusion FD of the photoelectric conversion element 12 directly to the first pad P1. Furthermore, the first substrate 101 has a wiring layer 11M2 as a first wiring layer disposed between the opposing surface 101S1 and the photoelectric conversion element 12 in the Z-axis direction, and the first via V1 penetrates the wiring layer 11M2 in the Z-axis direction.

[0047] 3, the floating diffusion FD of the first substrate 101 is electrically connected to the amplification transistor AMP and the like of the readout circuit 45 of the second substrate 102 via wiring layers 11M1 to 11M3 of the wiring unit 111 and a wiring layer 22M1 of the wiring unit 122. The charge photoelectrically converted by the photodiode PD of the first substrate 101 is output to the floating diffusion FD and the readout circuit 45 of the second substrate 102 via the transfer transistor TR.

[0048] The second substrate 102 also has an opposing surface 102S2 opposing the opposing surface 101S1, a second pad P2, and a second via V2. The second pad P2 includes a second bonding surface S2 included in the opposing surface 102S2. The second via V2 is electrically connected to the second pad P2 and extends from the second pad P2 in the Z-axis direction. The wiring layer 21M3 and the second pad P2 are electrically connected via the second via V2. In the imaging device 1, a through via composed of a first via V1, a first pad P1, a second pad P2, and a second via V2 is provided for each pixel P or for each set of pixels P. The second via V2 penetrates the semiconductor layer 120 in the Z-axis direction. The upper end of the second via V2 is connected to the second pad P2, and the lower end of the second via V2 is connected to the wiring layer 21M3. Therefore, the second pad P2 and the wiring layer 21M3 are electrically connected via the second via V2. Furthermore, the wiring layer 21M3 is connected to the gate electrode AMPG (described later) of the amplification transistor AMP via a via 21V. In the imaging device 1, a second via V2, a second pad P2, a first via V1, and a first pad P1 are arranged for each readout circuit 45 or for each of multiple readout circuits 45. The readout circuit 45 provided on the second substrate 102 is electrically connected to the floating diffusion FD via the second via V2, the second pad P2, the first via V1, and the first pad P1. The first via V1 and the second via V2 are made of, for example, tungsten (W), aluminum (Al), cobalt (Co), molybdenum (Mo), ruthenium (Ru), or the like. Note that the through-via TSV may be formed of other metal materials.

[0049] [Detailed Configuration of Imaging Device 1] FIG. 4A is a first schematic cross-sectional view showing an enlarged view of a part of the imaging device 1 shown in FIG.

[0050] 4A , in the imaging device 1, the entire region RP1 occupied by the first pad P1 in the XY plane overlaps in the Z-axis direction with the region RV1 occupied by the first via V1 in the XY plane. For example, it is preferable that the position and size of the region RP1 in the XY plane match the position and size of the region RV1 in the XY plane. Furthermore, the maximum dimension H1 of the first pad P1 in the Z-axis direction is greater than the maximum dimension W1 of the first pad P1 along the XY plane.

[0051] The entire region RP2 occupied by the second pad P2 in the XY plane overlaps in the Z-axis direction with the region RV2 occupied by the second via V2 in the XY plane. For example, the position and size of region RP2 in the XY plane may be the same as the position and size of region RV2 in the XY plane. Furthermore, the maximum dimension H2 of second pad P2 in the Z-axis direction is greater than the maximum dimension W2 of second pad P2 along the XY plane. Note that FIG. 4A illustrates a case in which the position and size of region RP1 in the XY plane are the same as the position and size of region RP2 in the XY plane. However, the position and size of region RP1 in the XY plane may be different from the position and size of region RP2 in the XY plane. Also, FIG. 4A illustrates a case in which the maximum dimension W1 is the same as the maximum dimension W2, and the maximum dimension H1 is the same as the maximum dimension H2. However, the maximum dimension W1 is the same as the maximum dimension W2, and the maximum dimension H1 is the same as the maximum dimension H2.

[0052] 4A , a first surface 12S1, which is an element formation surface of the semiconductor layer 120, is provided with semiconductor elements, such as an amplifier transistor AMP and a select transistor SEL. The semiconductor layer 120 is provided with a through-hole 23K that penetrates the semiconductor layer 120 in the Z-axis direction. A second via V2 is inserted in the through-hole 23K in the Z-axis direction. The upper end of the second via V2 is connected to a second pad P2 that is part of the wiring layer 22M1. A second bonding surface S2 of the second pad P2 is included in the opposing surface 102S2 and is bonded to a first bonding surface S1 of the first pad P1 that is included in the opposing surface 101S1.

[0053] The semiconductor layer 120 includes a semiconductor region 23p of a first conductivity type (e.g., p-type) and a well region 23nw of a second conductivity type (n-type) surrounding the second via V2. The well region 23nw includes a high-concentration region 23n+ having a higher n-type impurity concentration than the surrounding area. The amplifier transistor AMP and the select transistor SEL each include, for example, an n-type source / drain region S / D near the first surface 12S1. Furthermore, the amplifier transistor AMP and the select transistor SEL each include a gate electrode AMPG, SELG. The wiring layer 22M2 includes at least a portion of a connection portion 24 electrically connecting the high-concentration region 23n+ of the well region 23nw to the source / drain region S / D of the amplifier transistor AMP.

[0054] More specifically, the connection portion 24 includes a first pillar 24P1, a second pillar 24P2, and a beam 24B. The first pillar 24P1 is connected to the source / drain region S / D of the amplifier transistor AMP and extends in the Z-axis direction from the source / drain region S / D of the amplifier transistor AMP to at least the second surface 12S2, which is the back surface opposite the first surface 12S1 of the semiconductor layer 120. The second pillar 24P2 is connected to the high-concentration region 23n+ of the well region 23nw and extends in the Z-axis direction from the high-concentration region 23n+ of the well region 23nw to at least the second surface 12S2 of the semiconductor layer 23. The wiring layer 22M2 includes, as part of the connection portion 24, a beam 24B extending along the opposing surface 102S2 to electrically connect the first pillar 24P1 and the second pillar 24P2. Therefore, in FIG. 4A, the beam 24B of the connection portion 24 is provided in a layer different from the layer in which the wiring layer 22M1 is provided.

[0055] In the connection portion 24, the constituent materials of the beam 24B, the constituent materials of the first pillar 24P1, and the constituent materials of the second pillar 24P2 are the same. The constituent materials of the beam 24B, the constituent materials of the first pillar 24P1, and the constituent materials of the second pillar 24P2 are, for example, tungsten (W), aluminum (Al), cobalt (Co), molybdenum (Mo), ruthenium (Ru), etc., similar to the constituent materials of the through-via TSV. However, the beam 24B, the first pillar 24P1, and the second pillar 24P2 may be formed of other metal materials.

[0056] The beam 24B, the first pillar 24P1, and the second pillar 24P2 in the connection portion 24 may be integrally formed. That is, the connection portion 24 may be formed collectively from the same type of material.

[0057] The second substrate 102 further includes insulating layers 23Z1, 23Z2, and 23Z3. The insulating layer 23Z1 is interposed in the gap between the first pillar 24P1 and the semiconductor region 23p surrounding the first pillar 24P1. The insulating layer 23Z2 is interposed in the gap between the second pillar 24P2 and the well region 23nw surrounding the second pillar 24P2. Furthermore, the insulating layer 23Z3 is interposed in the gap between the second via V2 and the well region 23nw surrounding the second via V2.

[0058] As described above, the second substrate 102 further includes the wiring layer 21M3 on the side opposite to the opposing surface 102S2 when viewed from the semiconductor layer 120. The wiring layer 21M3 electrically connects the second via V2 and the gate electrode AMPG of the amplification transistor AMP.

[0059] 4B is a second schematic cross-sectional view showing an enlarged portion of the imaging device 1 shown in FIG. 4B. As shown in FIG. 4B, in the imaging device 1, the first substrate 101 may further include a third pad P3 including a third bonding surface S3 included in the opposing surface 101S1. The third pad P3 includes, for example, a first portion P3-1 and a second portion P3-2. Here, the region RP3-1 occupied by the first portion P3-1 in the XY plane is larger than the region RP3-2 occupied by the second portion P3-2 in the XY plane.

[0060] Furthermore, in the imaging device 1, the second substrate 102 may further include a fourth pad P4 that is included in the opposing surface 102S2 and includes a fourth bonding surface S4 that is bonded to the third bonding surface S3, and a fourth via V4 that is electrically connected to the fourth pad P4 and extends from the fourth pad P4 in the Z-axis direction. The fourth pad P4 includes, for example, a first portion P4-1 and a second portion P4-2 that connects the first portion P4-1 and the fourth via V4. Here, the entire region RP4-2 occupied by the second portion P4-2 in the XY plane may overlap in the Z-axis direction with the region RV4 occupied by the fourth via V4 in the XY plane, and the region RP4-1 occupied by the first portion P4-1 in the XY plane may be larger than the region RP4-2.

[0061] The third pad P3, the fourth pad P4, and the fourth via V4 constitute part of the power supply wiring for supplying voltage to semiconductor elements such as the amplifier transistor AMP and the select transistor SEL. In this way, the third pad P3 and the fourth pad P4 have regions RP3-1 and RP4-1, respectively, which are larger than the region RV4 occupied by the fourth via V4, and therefore the wiring resistance of the power supply wiring can be reduced.

[0062] Furthermore, the layout of the imaging device 1 along the XY plane is shown in Figures 5A and 5B. Figures 5A to 5B correspond to horizontal cross sections at positions Lv1 and Lv2 in the Z-axis direction shown in Figure 3, respectively. However, the example configuration of the stacked cross section in Figure 3 does not strictly match the example configuration of the horizontal cross section shown in Figures 5A to 5B. Figures 5A to 5B show a state in which pixel sharing units 40, each consisting of four pixels Pa to Pd, are arranged two by two in both the X-axis direction and the Y-axis direction.

[0063] 5A, photodiodes PD1 to PD4 of each pixel P are provided in an active region surrounded by a pixel isolation portion 51. Transfer transistors TR1 to TR4 are provided in the active region so as to overlap the photodiodes PD1 to PD4 in the Z-axis direction. A first via V1 connected to each of the floating diffusions FD1 to FD4 is arranged at the center position of the four pixels Pa to Pd.

[0064] As shown in FIG. 5B , wiring layers 11M1 and 22M1 are provided on the bonding surface between the first substrate 101 and the second substrate 102 so as to surround the active regions of the four pixels Pa to Pd. A second via V2 is disposed at the center of the four pixels Pa to Pd. The second via V2 is electrically connected to the first via V1, also shown in FIG. 5A , via a second pad P2 serving as the wiring layer 22M1 and a first pad P1 serving as the wiring layer 11M1. A well region 23nw is also provided so as to surround the second via V2. Furthermore, a connection portion 24 (a beam 24B is shown in FIG. 5B ) is provided that electrically connects a high-concentration region 23n+ (not shown in FIG. 5B ) of the well region 23nw to a source / drain region S / D (not shown in FIG. 5B ) of the amplifier transistor AMP provided in the semiconductor region 23p.

[0065] [Method for Manufacturing Image Capturing Device 1] Next, a method for manufacturing the image capturing device 1 will be described with reference to FIGS. 6A to 6Q.

[0066] First, the second substrate 102 and the third substrate 103 are prepared. However, at this stage, the second substrate 102 has the wiring portion 121 provided in the semiconductor layer 120, but does not have the wiring portion 122 provided therein. Furthermore, the second via V2 has not been formed. Then, as shown in FIG. 6A , the opposing surface 102S1 of the second substrate 102 and the opposing surface 103S1 of the third substrate 103 are hybrid-bonded. At this time, the wiring layer 21M1 and the wiring layer 31M1 are bonded together, and the interlayer insulating film 21Z and the interlayer insulating film 31Z are also bonded together.

[0067] Next, the second surface 12S2 of the semiconductor layer 120 is polished as necessary to adjust the thickness of the semiconductor layer 120 to, for example, 3 μm or less, and then, as shown in Fig. 6B, an interlayer insulating film 22Z is ​​formed so as to cover the second surface 12S2 of the semiconductor layer 120. Thereafter, the connection portion 24 is formed, and then a second via V2 and a fourth via V4 that penetrate the semiconductor layer 120 are formed by a CVD method or the like.

[0068] 6C, a photoresist layer PR1 is selectively formed on the interlayer insulating film 22Z. Openings K1 to K4 are formed in the photoresist layer PR1 at locations where the wiring layer 22M1 is to be formed. At this stage, no openings are formed in locations where the second pads P2 are to be formed; these locations are covered with the photoresist layer PR1.

[0069] Thereafter, as shown in FIG. 6D, portions of the interlayer insulating film 22Z corresponding to the openings K1 to K4 are dug down by etching using the photoresist layer PR1 as a mask, thereby forming recesses U1 to U4.

[0070] 6E, the photoresist layer PR1 is removed by, for example, an ashing process in an oxygen atmosphere, after which the surface of the interlayer insulating film 22Z may be cleaned with an organic solvent.

[0071] Next, as shown in FIG. 6F, the upper portions of the second via V2 and the fourth via V4 exposed on the surface of the interlayer insulating film 22Z are removed by etching. ６ The metal material such as tungsten (W) constituting the second via V2 and the fourth via V4 is selectively removed by reactive ion etching (RIE) using an etching gas such as tungsten (W). As a result, a recess U5 is formed above the second via V2 in the interlayer insulating film 22Z. Furthermore, a recess 6 is formed above the fourth via V4 in the bottom of the recess U3, and a recess 7 is formed above the fourth via V4 in the bottom of the recess U4.

[0072] 6G, a predetermined metal material such as Cu (copper) or a copper alloy is filled into the recesses U1 to U7 to form the wiring layer 22M1 including the second pad P2. The upper surface is then planarized by CMP to form the opposing surface 102S2, completing the second substrate 102. As a result, a structure 1023 is obtained in which the second substrate 102 is bonded to the third substrate 103.

[0073] 6H , first substrate 101 is prepared, in which wiring portion 111 is provided in light-receiving layer 110. However, at this stage, first substrate 101 has wiring portion 111 provided in light-receiving layer 110, but first via V1 is not yet formed in wiring portion 111.

[0074] 6I, the first via V1 is formed so as to penetrate through the layer in which the wiring layer 11M1 is provided and reach the wiring layer 11M3.

[0075] 6J, a photoresist layer PR2 is selectively formed to cover the opposing surface 101S1. Openings K5 and K6 are formed in the photoresist layer PR2 at predetermined positions. At this stage, no openings are formed in the areas where the first pads P1 will be formed; these areas are covered with the photoresist layer PR2.

[0076] 6K, portions of the interlayer insulating film 11Z corresponding to the openings K5 and K6 are dug down by etching using the photoresist layer PR2 as a mask, forming recesses U8 and U9. After the recesses U8 and U9 are formed, the photoresist layer PR3 and the planarizing film PP are removed by, for example, RIE. Note that portions of the interlayer insulating film 11Z are left at the bottoms of the recesses U8 and U9 so that the wiring layer 11M2 is not exposed.

[0077] After the recesses U8 to U9 are formed, a planarizing film PP is formed to fill the recesses U8 to U9, and a photoresist layer PR3 is selectively formed to cover the planarizing film PP, as shown in Fig. 6L. Openings K7 to K10 are formed in the photoresist layer PR3 at predetermined positions.

[0078] Thereafter, as shown in FIG. 6M, portions of the interlayer insulating film 11Z corresponding to the openings K7 to K10 are dug down by etching using the photoresist layer PR3 as a mask, thereby forming recesses U8 to U11.

[0079] After the recesses U8 to U11 are formed, the photoresist layer PR3 and the planarization film PP are removed by, for example, RIE, as shown in Fig. 6N. At this time, an etching stopper is used to prevent the wiring layer 11M2 buried in the interlayer insulating film 11Z from being exposed.

[0080] Next, as shown in FIG. 6O, the upper portion of the first via V1 exposed on the surface of the interlayer insulating film 11Z is removed by etching. ６ The metal material such as tungsten (W) constituting the first via V1 is selectively removed by reactive ion etching (RIE) using an etching gas such as SiO 2 or the like. As a result, a recess U12 is formed above the first via V1 in the interlayer insulating film 11Z.

[0081] 6P, the interlayer insulating film 11Z present at the bottom of the recesses U8 and U9 is removed by etching or the like, and then a predetermined metal material such as Cu (copper) or a copper alloy is filled into the recesses U8 to U12 as shown in FIG. 6Q to form the wiring layer 11M1 including the first pad P1. Thereafter, the upper surface is planarized by CMP to form the opposing surface 101S1, and the first substrate 101 is completed.

[0082] Finally, the opposing surface 102S2 of the structure 1023 in which the second substrate 102 is bonded to the previously prepared third substrate 103 is hybrid-bonded to the opposing surface 101S1 of the first substrate 101, and the imaging device 1 is completed by creating a color filter CF, an on-chip lens OCL, etc.

[0083] [Effects of the Image Capturing Device 1] In the image capturing device 1 of the present embodiment, the entire region RP1 occupied by the first pad P1 in the XY plane overlaps in the Z-axis direction with the region RV1 occupied by the first via V1 in the XY plane, thereby reducing the parasitic capacitance between the first via V1 and the semiconductor or conductor around the first via V1. As a result, the photoelectric conversion efficiency of the photoelectric conversion element 12 is improved.

[0084] Furthermore, when the size and position of the region RP1 are substantially the same as the size and position of the region RV1, the variation in parasitic capacitance can be further reduced and the resistance can be lowered. Such a structure, i.e., a structure in which the size and position of the region RP1 are substantially the same as the size and position of the region RV1, can be manufactured by, for example, replacing a part of the first via V1 in the Z-axis direction with the first pad P1, as described in the manufacturing method above.

[0085] Furthermore, in the imaging device 1, the wiring layers 22M1 and 22M2 are provided on the second substrate 102 on the side opposite the first surface 12S1, which is the element formation surface, as viewed from the semiconductor layer 120. This reduces congestion in the wiring layers M on the first surface 12S1 side. This improves the degree of freedom in the planar layout of each wiring layer M, facilitating high integration of the readout circuit 45 and other components. Furthermore, the high-concentration region 23n+ in the well region 23nw surrounding the second via V2 in the semiconductor layer 120 can be electrically connected to the amplification transistor AMP via the beam 23B included in the wiring layer 22M2. This reduces parasitic capacitance between the second via V2 and the well region 23nw surrounding the second via V2 due to the mirror effect. As a result, the photoelectric conversion efficiency of the photodiodes PD1 to PD4 is improved in the imaging device 1, resulting in high photodetection performance. Therefore, the imaging device 1 of this embodiment can achieve both improved imaging performance and high integration. In particular, in the imaging device 1, the first pillar 24P1 and the second pillar 24P2 extending in the Z-axis direction are used to electrically connect the high-concentration region 23n+ around the second via V2 to the source-drain region S / D of the amplification transistor AMP, which prevents an increase in the occupied area in the XY plane and is advantageous for high integration.

[0086] [Modification of Image Capturing Device 1] Next, an image capturing device 1A as a modification of the image capturing device 1 of the first embodiment will be described. FIG. 7 is a schematic diagram illustrating an enlarged portion of the stacked cross section of the image capturing device 1A, corresponding to FIG. 4B illustrating the image capturing device 1 of the first embodiment. In the image capturing device 1A, the first substrate 101 further includes a third pad P3. The third pad P3 includes a third bonding surface S3 included in the opposing surface 101S1. The third pad P3 is electrically connected to, for example, a well contact provided on the first substrate 101. In the image capturing device 1A, the second substrate 102 further includes a fourth pad P4 and a fourth via V4. The fourth pad P4 includes a fourth bonding surface S4 included in the opposing surface 102S2 and bonded to the third bonding surface S3. The fourth via V4 is electrically connected to the fourth pad P4 and extends from the fourth pad P4 in the Z-axis direction. In the imaging device 1A, a part of the fourth via V4 is embedded in the fourth pad P4.

[0087] 2. Second Embodiment [Configuration of Image Capturing Device 2] Next, an image capturing device 2 according to a second embodiment of the present disclosure will be described with reference to FIG. 8 . FIG. 8 is a layer cross-sectional view illustrating an example of a schematic configuration of the image capturing device 2. The image capturing device 2 is configured by replacing the first via V1, the first pad P1, the second pad P2, and the second via V2 in the image capturing device 1 described in the first embodiment with a single through-via TSV. Except for this point, the configuration of the image capturing device 2 is substantially the same as that of the image capturing device 1. The through-via TSV forms wiring connected to the floating diffusion FD. The upper end of the through-via TSV extends in the Z-axis direction so as to reach the layer in which the floating diffusion FD is provided. The floating diffusion FD is electrically connected by contacting the side surface of the through-via TSV. The horizontal cross-sectional shape of the through-via TSV is, for example, circular or elliptical.

[0088] The through-via TSV has a first end connected to the photoelectric conversion element 12 and a second end located on the opposite side of the first end in the Z-axis direction. The second end abuts the wiring layer 21M3. In the imaging device 2, well contacts WC are formed in the light-receiving layer 110 of the first substrate 101. Some of the third pads P3 are connected to the well contacts WC via the wiring layers 11M2, 11M3, etc.

[0089] [Method for Manufacturing Image Capturing Device 2] Next, a method for manufacturing the image capturing device 2 will be described with reference to FIGS. 9A to 9E.

[0090] First, as in the imaging device 1 of the first embodiment, the first substrate 101, the second substrate 102, and the third substrate 103 are bonded together as shown in Fig. 9A. However, the first via V1, the first pad P1, the second pad P2, and the second via V2 are not formed. Also, an insulating layer 23Z3 is formed in advance at a predetermined position on the semiconductor layer 120.

[0091] 9B , through holes TH are formed in the first substrate 101 and the second substrate 102. The through holes TH are formed from the surface 101S2 opposite to the opposing surface 101S1 of the first substrate 101, through the light receiving layer 110, the interlayer insulating film 11Z, the opposing surfaces 101S1 and 102S2, the insulating layer 23Z3 of the semiconductor layer 120, and the interlayer insulating film 21Z, and reach the wiring layer 21M3.

[0092] 9C, a metal material such as W (tungsten) is formed to fill the through hole TH, thereby forming a through via TSV.

[0093] Next, as shown in FIG. 9D, the upper end portion of the through-via TSV filling the through hole TH, specifically the portion of the through-via TSV above the floating diffusion FD, is removed to form an opening H21.

[0094] Finally, as shown in FIG. 9E, the opening H21 is filled with SiO ２ The insulating layer Z21 is formed by filling the gap with an insulating material such as the above. Thereafter, the color filter CF, the on-chip lens OCL, and the like are formed, and the imaging device 2 is completed.

[0095] [Effects of the Imaging Device 2] In the imaging device 2 of this embodiment, the first substrate 101 and the second substrate 102 are provided with through-via TSVs extending in the Z-axis direction intersecting the XY plane so as to penetrate both the first opposing surface and the second opposing surface. This allows for a wider gap between the through-via TSV and the semiconductor or conductor surrounding the through-via TSV, thereby reducing parasitic capacitance generated around the through-via TSV. As a result, the photoelectric conversion efficiency of the photoelectric conversion element 12 is improved. Furthermore, in the imaging device 2, the through-via TSVs penetrate both the opposing surface 101S1 and the opposing surface 102S2. This allows for reduced variation in the resistance value of the wiring layer due to manufacturing errors, etc., compared to when the first substrate 101 and the second substrate 102 are provided with a first via V1 and a second via V2, respectively, and the first via V1 and the second via V2 are directly bonded or bonded via the first pad P1 and the second pad P2. Furthermore, in the imaging device 2, the through-vias TSV are not provided in the absorption layer 110 but are replaced with the insulating layer Z21, which reduces the parasitic capacitance that occurs between the through-vias TSV and the surrounding semiconductor regions that constitute the absorption layer 110. As a result, it is possible to avoid a decrease in photoelectric conversion efficiency.

[0096] [Modifications of Image Capture Device 2] The following describes first to ninth modifications of the second embodiment. In each of the modifications, the same reference numerals are used to designate components that are common to the above embodiment.

[0097] (2-1. First Modification) Although FIG. 8 illustrates a structure in which so-called face-to-back bonding is performed, the imaging device 2 of this embodiment may have a structure in which face-to-face bonding is performed.

[0098] (2-2. Second Modification) In the imaging device 2, the material constituting the through-via TSV is not limited to a metal material such as W (tungsten). The material constituting the through-via TSV may be a conductive material other than a metal, such as polysilicon. Examples of conductive materials other than a metal include transparent oxide materials such as InO and nitride materials such as TiN.

[0099] (2-3. Third variant) In the imaging device 2 shown in Figure 8, the amplification transistor AMP and the through via TSV are connected via a wiring layer 21M3 or the like, but the amplification transistor AMP and the through via TSV may also be directly connected.

[0100] 8, the amplifier transistor AMP and the through via TSV are connected via a wiring layer 21M3 or the like, but as in the image pickup device 2A shown in Fig. 10A, a contact layer 51 made of polysilicon may be provided on the first surface 12S, and the amplifier transistor AMP and the through via TSV may be connected via the contact layer. Fig. 10A is a cross-sectional view schematically showing the configuration of the image pickup device 2A as a fourth modified example.

[0101] 10B schematically illustrates a cross-sectional stacked configuration of an image pickup device 2B as a fifth modified example. The image pickup device 2B has embedded wiring 52 embedded in an insulating layer 23Z of a semiconductor layer 120. The embedded wiring 52 is made of a metal material such as Cu (copper).

[0102] 10C schematically shows the cross-sectional stacked structure of an image pickup device 2C as a sixth modified example. In the image pickup device 2C, the lower ends of the through-via TSVs are located on the first surface 12S1 of the semiconductor layer 120, and the through-via TSVs and the wiring layer 21M3 are connected by contact layers 53. The diameter of the contact layers 53 is equal to or smaller than the diameter of the through-via TSVs.

[0103] 10D is a schematic diagram showing the cross-sectional stacked structure of an image pickup device 2D as a seventh modification. The image pickup device 2D has a structure in which part of the pixel separation wall in the light receiving layer 110 of the first substrate 101 is replaced with a partition wall 54 made of polysilicon rather than an insulating material. By providing such a conductive partition wall 54, it is possible to apply a negative bias to the partition wall 54, for example.

[0104] (2-8. Eighth Modification) FIG. 10E schematically shows the cross-sectional stacked structure of an imaging device 2E as an eighth modification. The imaging device 2E further includes a through via TSV2 adjacent to the through via TSV. The through via TSV2 also penetrates both the opposing surface 101S1 and the opposing surface 102S2. In this modification, there is no need to provide pads around the through via TSV, which makes it possible to reduce unnecessary parasitic capacitance.

[0105] 10F is a schematic diagram showing the horizontal cross-sectional configuration of an image pickup device 2F as a ninth modified example. In the image pickup device 2F, the through-via TSV has a rectangular horizontal cross-sectional shape. Note that the side surface of the floating diffusion FD is in contact with the photodiode PD.

[0106] In addition, the structure of the pixel separation wall provided between the pixels is not particularly limited.

[0107] 3. Application Examples Application Example 1 The imaging device 1 and the like can be applied to any type of electronic device equipped with an imaging function, for example, a camera system such as a digital still camera or a video camera, a mobile phone with an imaging function, etc. Fig. 11 shows a schematic configuration of an electronic device 1000.

[0108] The electronic device 1000 includes, for example, a lens group 1001, an imaging device 1, a DSP (Digital Signal Processor) circuit 1002, a frame memory 1003, a display unit 1004, a recording unit 1005, an operation unit 1006, and a power supply unit 1007, which are interconnected via a bus line 1008.

[0109] The lens group 1001 captures incident light (image light) from a subject and forms an image on the imaging surface of the imaging device 1. The imaging device 1 converts the amount of incident light formed on the imaging surface by the lens group 1001 into an electrical signal on a pixel-by-pixel basis and supplies the signal as a pixel signal to the DSP circuit 1002.

[0110] The DSP circuit 1002 is a signal processing circuit that processes signals supplied from the imaging device 1. The DSP circuit 1002 outputs image data obtained by processing the signals from the imaging device 1. The frame memory 1003 temporarily stores the image data processed by the DSP circuit 1002 on a frame-by-frame basis.

[0111] The display unit 1004 is composed of a panel-type display device such as a liquid crystal panel or an organic EL (Electro Luminescence) panel, and records image data of moving images or still images captured by the imaging device 1 on a recording medium such as a semiconductor memory or a hard disk.

[0112] The operation unit 1006, in response to a user's operation, outputs operation signals for various functions of the electronic device 1000. The power supply unit 1007 supplies various types of power to the DSP circuit 1002, frame memory 1003, display unit 1004, recording unit 1005, and operation unit 1006 as needed.

[0113] (Application Example 2) Fig. 12A is a schematic diagram illustrating an example of the overall configuration of a light detection system 2000 including an imaging device 1. Fig. 12B is a diagram illustrating an example of the circuit configuration of the light detection system 2000. The light detection system 2000 includes a light emitting device 2001 serving as a light source unit that emits infrared light L2, and a light detecting device 2002 serving as a light receiving unit having a photoelectric conversion element. The imaging device 1 described above can be used as the light detecting device 2002. The light detection system 2000 may further include a system control unit 2003, a light source driving unit 2004, a sensor control unit 2005, a light source side optical system 2006, and a camera side optical system 2007.

[0114] The photodetector 2002 can detect light L1 and light L2. Light L1 is external ambient light reflected by the object (measurement target) 2100 ( FIG. 12A ). Light L2 is light emitted by the light-emitting device 2001 and then reflected by the object 2100. Light L1 is, for example, visible light, and light L2 is, for example, infrared light. Light L1 can be detected by a photoelectric conversion unit in the photodetector 2002, and light L2 can be detected by a photoelectric conversion region in the photodetector 2002. Image information of the object 2100 can be obtained from light L1, and distance information between the object 2100 and the photodetector system 2000 can be obtained from light L2. The photodetector system 2000 can be installed in, for example, an electronic device such as a smartphone or a mobile object such as a car. The light-emitting device 2001 can be configured, for example, by a semiconductor laser, a surface-emitting semiconductor laser, or a vertical-cavity surface-emitting laser (VCSEL). The method of detecting the light L2 emitted from the light-emitting device 2001 by the photodetector 2002 can be, for example, an iTOF method, but is not limited to this. In the iTOF method, the photoelectric conversion unit can measure the distance to the subject 2100, for example, by using the time-of-flight (TOF) of light. The method of detecting the light L2 emitted from the light-emitting device 2001 by the photodetector 2002 can also be, for example, a structured light method or a stereo vision method. For example, in the structured light method, a predetermined pattern of light is projected onto the subject 2100, and the distance between the photodetector system 2000 and the subject 2100 can be measured by analyzing the distortion of the pattern. In addition, in the stereo vision method, for example, two or more cameras are used to acquire two or more images of the subject 2100 viewed from two or more different viewpoints, thereby measuring the distance between the photodetector system 2000 and the subject. The light emitting device 2001 and the light detecting device 2002 can be controlled synchronously by a system control unit 2003 .

[0115] 4. Application Example Application Example to an Endoscopic Surgery System The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be applied to an endoscopic surgery system.

[0116] FIG. 13 is a diagram showing an example of a schematic configuration of an endoscopic surgery system to which the technology according to the present disclosure (the present technology) can be applied.

[0117] 13 shows an operator (doctor) 11131 performing surgery on a patient 11132 on a patient bed 11133 using an endoscopic surgery system 11000. As shown in the figure, the endoscopic surgery system 11000 is composed of an endoscope 11100, other surgical tools 11110 such as an insufflation tube 11111 and an energy treatment tool 11112, a support arm device 11120 that supports the endoscope 11100, and a cart 11200 on which various devices for endoscopic surgery are mounted.

[0118] The endoscope 11100 is composed of a lens barrel 11101, a region of a predetermined length from the tip of which is inserted into a body cavity of a patient 11132, and a camera head 11102 connected to the base end of the lens barrel 11101. In the example shown, the endoscope 11100 is configured as a so-called rigid scope having a rigid lens barrel 11101, but the endoscope 11100 may also be configured as a so-called flexible scope having a flexible lens barrel.

[0119] An opening into which an objective lens is fitted is provided at the tip of the lens barrel 11101. A light source device 11203 is connected to the endoscope 11100, and light generated by the light source device 11203 is guided to the tip of the lens barrel by a light guide extending inside the lens barrel 11101, and is irradiated via the objective lens toward an object to be observed inside the body cavity of the patient 11132. The endoscope 11100 may be a direct-viewing endoscope, an oblique-viewing endoscope, or a side-viewing endoscope.

[0120] An optical system and an image sensor are provided inside the camera head 11102, and light reflected from the object of observation (observation light) is collected onto the image sensor by the optical system. The observation light is photoelectrically converted by the image sensor to generate an electrical signal corresponding to the observation light, i.e., an image signal corresponding to the observed image. The image signal is sent to a camera control unit (CCU) 11201 as RAW data.

[0121] The CCU 11201 is configured with a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), etc., and comprehensively controls the operations of the endoscope 11100 and the display device 11202. Furthermore, the CCU 11201 receives an image signal from the camera head 11102 and performs various types of image processing on the image signal, such as development processing (demosaic processing), to display an image based on the image signal.

[0122] Under the control of the CCU 11201, the display device 11202 displays an image based on an image signal that has been subjected to image processing by the CCU 11201.

[0123] The light source device 11203 is composed of a light source such as an LED (light emitting diode), and supplies irradiation light to the endoscope 11100 when photographing the surgical site, etc.

[0124] The input device 11204 is an input interface for the endoscopic surgery system 11000. A user can input various information and instructions to the endoscopic surgery system 11000 via the input device 11204. For example, the user inputs an instruction to change the imaging conditions (type of irradiation light, magnification, focal length, etc.) of the endoscope 11100.

[0125] The treatment tool control device 11205 controls the driving of the energy treatment tool 11112 for cauterizing tissue, incising, sealing blood vessels, etc. The insufflation device 11206 inflates the body cavity of the patient 11132 through the insufflation tube 11111 in order to ensure a clear field of view for the endoscope 11100 and a working space for the surgeon. The recorder 11207 is a device capable of recording various types of information related to the surgery. The printer 11208 is a device capable of printing various types of information related to the surgery in various formats such as text, images, or graphs.

[0126] The light source device 11203, which supplies illumination light to the endoscope 11100 when photographing the surgical site, can be configured from a white light source, such as an LED, a laser light source, or a combination of these. When the white light source is configured from a combination of RGB laser light sources, the output intensity and output timing of each color (each wavelength) can be controlled with high precision, allowing the light source device 11203 to adjust the white balance of the captured image. In this case, it is also possible to time-share images corresponding to each RGB by irradiating the object of observation with laser light from each RGB laser light source and controlling the drive of the image sensor of the camera head 11102 in synchronization with the irradiation timing. According to this method, color images can be obtained without providing a color filter to the image sensor.

[0127] Furthermore, the light source device 11203 may be controlled to change the intensity of light it outputs at predetermined time intervals. By controlling the driving of the image sensor of the camera head 11102 in synchronization with the timing of the change in light intensity to acquire images in a time-division manner and combining the images, it is possible to generate an image with a high dynamic range that is free from so-called blocked-up shadows and blown-out highlights.

[0128] The light source device 11203 may also be configured to provide light in a predetermined wavelength range compatible with special light observation. Special light observation, for example, utilizes the wavelength dependence of light absorption in body tissues to irradiate light with a narrower band than the light irradiated during normal observation (i.e., white light), thereby capturing high-contrast images of specific tissues, such as blood vessels on the surface of mucous membranes, known as narrow-band imaging. Alternatively, special light observation may involve fluorescence observation, in which images are obtained using fluorescence generated by irradiating excitation light onto the body tissue. Fluorescence observation can involve irradiating excitation light onto the body tissue and observing the fluorescence from the tissue (autofluorescence observation), or by locally injecting a reagent such as indocyanine green (ICG) into the body tissue and irradiating the tissue with excitation light corresponding to the fluorescent wavelength of the reagent to obtain a fluorescent image. The light source device 11203 may be configured to provide narrow-band light and / or excitation light compatible with such special light observation.

[0129] FIG. 14 is a block diagram showing an example of the functional configuration of the camera head 11102 and the CCU 11201 shown in FIG.

[0130] The camera head 11102 has a lens unit 11401, an imaging unit 11402, a drive unit 11403, a communication unit 11404, and a camera head control unit 11405. The CCU 11201 has a communication unit 11411, an image processing unit 11412, and a control unit 11413. The camera head 11102 and the CCU 11201 are connected to each other via a transmission cable 11400 so that they can communicate with each other.

[0131] The lens unit 11401 is an optical system provided at the connection portion with the lens barrel 11101. Observation light taken in from the tip of the lens barrel 11101 is guided to the camera head 11102 and enters the lens unit 11401. The lens unit 11401 is composed of a combination of multiple lenses including a zoom lens and a focus lens.

[0132] The imaging unit 11402 may include one imaging element (a so-called single-chip type) or multiple imaging elements (a so-called multi-chip type). When the imaging unit 11402 is configured as a multi-chip type, for example, each imaging element may generate an image signal corresponding to each of RGB, and a color image may be obtained by combining these signals. Alternatively, the imaging unit 11402 may be configured to have a pair of imaging elements for acquiring image signals for the right eye and the left eye corresponding to a 3D (dimensional) display. The 3D display allows the surgeon 11131 to more accurately grasp the depth of the biological tissue at the surgical site. Note that when the imaging unit 11402 is configured as a multi-chip type, multiple lens units 11401 may be provided corresponding to each imaging element.

[0133] Furthermore, the imaging unit 11402 does not necessarily have to be provided in the camera head 11102. For example, the imaging unit 11402 may be provided inside the lens barrel 11101, immediately after the objective lens.

[0134] The driving unit 11403 is configured by an actuator, and moves the zoom lens and focus lens of the lens unit 11401 by a predetermined distance along the optical axis under the control of the camera head control unit 11405. This allows the magnification and focus of the image captured by the imaging unit 11402 to be adjusted appropriately.

[0135] The communication unit 11404 is configured by a communication device for transmitting and receiving various types of information to and from the CCU 11201. The communication unit 11404 transmits the image signal obtained from the imaging unit 11402 to the CCU 11201 via the transmission cable 11400 as RAW data.

[0136] Furthermore, the communication unit 11404 receives a control signal for controlling the driving of the camera head 11102 from the CCU 11201 and supplies the control signal to the camera head control unit 11405. The control signal includes information on the imaging conditions, such as information specifying the frame rate of the captured image, information specifying the exposure value at the time of imaging, and / or information specifying the magnification and focus of the captured image.

[0137] The image capturing conditions such as the frame rate, exposure value, magnification, and focus may be appropriately specified by the user, or may be automatically set by the control unit 11413 of the CCU 11201 based on the acquired image signal. In the latter case, the endoscope 11100 is equipped with a so-called AE (Auto Exposure) function, AF (Auto Focus) function, and AWB (Auto White Balance) function.

[0138] The camera head control unit 11405 controls the driving of the camera head 11102 based on a control signal received from the CCU 11201 via the communication unit 11404 .

[0139] The communication unit 11411 is configured by a communication device for transmitting and receiving various information to and from the camera head 11102. The communication unit 11411 receives an image signal transmitted from the camera head 11102 via the transmission cable 11400.

[0140] Furthermore, the communication unit 11411 transmits to the camera head 11102 a control signal for controlling the driving of the camera head 11102. The image signal and the control signal can be transmitted by electrical communication, optical communication, or the like.

[0141] The image processing unit 11412 performs various image processing operations on the image signal, which is RAW data transmitted from the camera head 11102 .

[0142] The control unit 11413 performs various controls related to the imaging of the surgical site, etc. by the endoscope 11100 and the display of the captured image obtained by imaging the surgical site, etc. For example, the control unit 11413 generates a control signal for controlling the driving of the camera head 11102.

[0143] Furthermore, the control unit 11413 displays the captured image showing the surgical site, etc., on the display device 11202 based on the image signal subjected to image processing by the image processing unit 11412. At this time, the control unit 11413 may recognize various objects in the captured image using various image recognition technologies. For example, the control unit 11413 can recognize surgical tools such as forceps, specific biological parts, bleeding, mist generated when using the energy treatment tool 11112, etc., by detecting the shape and color of the edges of objects included in the captured image. When displaying the captured image on the display device 11202, the control unit 11413 may use the recognition results to superimpose various surgical support information on the image of the surgical site. By superimposing the surgical support information and presenting it to the surgeon 11131, the burden on the surgeon 11131 can be reduced and the surgeon 11131 can proceed with the surgery reliably.

[0144] The transmission cable 11400 connecting the camera head 11102 and the CCU 11201 is an electrical signal cable for electrical signal communication, an optical fiber for optical communication, or a composite cable of these.

[0145] In the illustrated example, communication is performed wired using a transmission cable 11400, but communication between the camera head 11102 and the CCU 11201 may also be performed wirelessly.

[0146] The above describes an example of an endoscopic surgery system to which the technology according to the present disclosure can be applied. The technology according to the present disclosure can be applied to the imaging unit 11402 among the components described above. By applying the technology according to the present disclosure to the imaging unit 11402, detection accuracy is improved.

[0147] Although an endoscopic surgery system has been described as an example here, the technology according to the present disclosure may also be applied to other systems, such as a microsurgery system.

[0148] (Application Example to Mobile Object) The technology according to the present disclosure can be applied to various products. For example, the technology according to the present disclosure may be realized as a device mounted on any type of mobile object, such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, personal mobility, an airplane, a drone, a ship, a robot, construction machinery, or agricultural machinery (tractor).

[0149] FIG. 15 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile object control system to which the technology according to the present disclosure can be applied.

[0150] The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in Fig. 15, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside-vehicle information detection unit 12030, an inside-vehicle information detection unit 12040, and an integrated control unit 12050. Also shown as functional components of the integrated control unit 12050 are a microcomputer 12051, an audio / video output unit 12052, and an in-vehicle network I / F (interface) 12053.

[0151] The drivetrain control unit 12010 controls the operation of devices related to the drivetrain of the vehicle in accordance with various programs. For example, the drivetrain control unit 12010 functions as a control device for a drive force generating device for generating a drive force of the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating a braking force of the vehicle.

[0152] The body system control unit 12020 controls the operation of various devices equipped in the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as headlamps, backup lamps, brake lamps, turn signals, and fog lamps. In this case, radio waves transmitted from a portable device that serves as a key or signals from various switches can be input to the body system control unit 12020. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock device, power window device, lamps, etc.

[0153] The outside-vehicle information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the outside-vehicle information detection unit 12030. The outside-vehicle information detection unit 12030 causes the imaging unit 12031 to capture images outside the vehicle and receives the captured images. The outside-vehicle information detection unit 12030 may perform object detection processing or distance detection processing for people, cars, obstacles, signs, characters on the road surface, etc. based on the received images.

[0154] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0155] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, a driver state detection unit 12041 that detects the state of the driver is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 may calculate the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing off.

[0156] The microcomputer 12051 can calculate control target values ​​for the driving force generating device, steering mechanism, or braking device based on the information inside and outside the vehicle acquired by the outside-vehicle information detection unit 12030 or the inside-vehicle information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an ADAS (Advanced Driver Assistance System), including vehicle collision avoidance or impact mitigation, following driving based on the distance between vehicles, maintaining vehicle speed, vehicle collision warning, vehicle lane departure warning, etc.

[0157] In addition, the microcomputer 12051 can perform cooperative control for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation, by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about the surroundings of the vehicle obtained by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040.

[0158] Furthermore, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information outside the vehicle acquired by the outside information detection unit 12030. For example, the microcomputer 12051 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the outside information detection unit 12030, and perform cooperative control aimed at preventing glare, such as switching from high beams to low beams.

[0159] The audio / video output unit 12052 transmits at least one of audio and video output signals to an output device capable of visually or audibly notifying information to vehicle occupants or the outside of the vehicle. In the example of Fig. 13, the output devices are exemplified by an audio speaker 12061, a display unit 12062, and an instrument panel 12063. The display unit 12062 may include, for example, at least one of an on-board display and a head-up display.

[0160] FIG. 16 is a diagram showing an example of the installation position of the imaging unit 12031.

[0161] In FIG. 16, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0162] The imaging units 12101, 12102, 12103, 12104, and 12105 are provided, for example, at positions such as the front nose, side mirrors, rear bumper, back door, and the top of the windshield inside the vehicle cabin of the vehicle 12100. The imaging unit 12101 provided on the front nose and the imaging unit 12105 provided on the top of the windshield inside the vehicle cabin mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 provided on the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 provided on the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 provided on the top of the windshield inside the vehicle cabin is mainly used to detect preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, etc.

[0163] 16 shows an example of the imaging ranges of the imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of the imaging unit 12104 provided on the rear bumper or back door. For example, by overlaying the image data captured by the imaging units 12101 to 12104, an overhead image of the vehicle 12100 viewed from above can be obtained.

[0164] At least one of the image capturing units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the image capturing units 12101 to 12104 may be a stereo camera made up of multiple image capturing elements, or may be an image capturing element having pixels for phase difference detection.

[0165] For example, based on the distance information obtained from the imaging units 12101 to 12104, the microcomputer 12051 can calculate the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and the change in this distance over time (relative speed with respect to the vehicle 12100), thereby extracting as a preceding vehicle, in particular, the three-dimensional object that is the closest three-dimensional object on the path of the vehicle 12100 and traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (e.g., 0 km / h or higher). Furthermore, the microcomputer 12051 can set a vehicle-to-vehicle distance to be maintained in advance in front of the preceding vehicle, and perform automatic braking control (including follow-up stop control), automatic acceleration control (including follow-up start control), etc. In this way, cooperative control can be performed for the purpose of autonomous driving, which runs autonomously without relying on driver operation.

[0166] For example, the microcomputer 12051 classifies and extracts three-dimensional object data regarding three-dimensional objects into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on distance information obtained from the imaging units 12101 to 12104, and can use the data for automatic obstacle avoidance. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines a collision risk that indicates the risk of collision with each obstacle, and when the collision risk is equal to or greater than a set value and a collision is possible, the microcomputer 12051 can provide driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or avoidance steering via the drive system control unit 12010.

[0167] At least one of the image capturing units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether a pedestrian is present in the images captured by the image capturing units 12101 to 12104. Such pedestrian recognition is performed, for example, by extracting feature points from the images captured by the image capturing units 12101 to 12104 as infrared cameras and performing pattern matching on a series of feature points that indicate the outline of an object to determine whether the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the image capturing units 12101 to 12104 and recognizes the pedestrian, the audio / image output unit 12052 controls the display unit 12062 to superimpose a rectangular outline on the recognized pedestrian for emphasis. The audio / image output unit 12052 may also control the display unit 12062 to display an icon or the like indicating the pedestrian at a desired position.

[0168] The foregoing has described an example of a mobile object control system to which the technology according to the present disclosure can be applied. The technology according to the present disclosure can be applied to the imaging unit 12031 of the above-described configuration. Specifically, the imaging devices according to the above-described embodiment and its variants 1 to 4 can be applied to the imaging unit 12031. By applying the technology according to the present disclosure to the imaging unit 12031, it is possible to obtain high-resolution captured images with little noise, thereby enabling high-precision control using the captured images in the mobile object control system.

[0169] The present disclosure has been described above by giving several embodiments and their modified examples 1 to 9, application examples, and applied examples. However, the present disclosure is not limited to the above-described embodiments, and various modifications are possible. Note that the effects described in this specification are merely examples. The effects of the present disclosure are not limited to the effects described in this specification. The present disclosure may have effects other than those described in this specification.

[0170] Furthermore, for example, the present disclosure can be configured as follows. In a photodetector having the following configuration, the parasitic capacitance between the first via (via) and the semiconductor or conductor surrounding the first via (via) is reduced. As a result, the photoelectric conversion efficiency of the first photoelectric conversion element is improved. Therefore, it is possible to achieve both improved performance and high integration. <1> A photodetector comprising: a first substrate having a first opposing surface along a first plane, a first photoelectric conversion element including a first photoelectric conversion unit that generates a first charge by photoelectrically converting light, a first pad including a first bonding surface included in the first opposing surface, and a first via extending in a first direction intersecting the first plane, and a second substrate having a second opposing surface opposite the first opposing surface, a second pad including a second bonding surface included in the second opposing surface and bonded to the first bonding surface, and a second via electrically connected to the second pad and extending from the second pad in the first direction, wherein the first photoelectric conversion element and the first pad are electrically connected via the first via, and a first pad occupation area occupied by the first pad in the first plane entirely overlaps in the first direction with a first via occupation area occupied by the first via in the first plane. <2> The photodetector according to <1> above, wherein a maximum dimension of the first pad in the first direction is greater than a maximum dimension of the first pad along the first plane. <3> The photodetector according to <1> or <2> above, wherein a second pad occupation area occupied by the second pad on the first plane entirely overlaps a second via occupation area occupied by the second via on the first plane in the first direction. <4> The photodetector according to <3> above, wherein a maximum dimension of the second pad in the first direction is greater than a maximum dimension of the second pad along the first plane. <5> The photodetector according to any one of <1> to <4> above, wherein the first substrate further has a first wiring layer disposed between the first opposing surface and the first photoelectric conversion element in the first direction, and the first via penetrates the first wiring layer in the first direction. <6> The photodetector according to any one of <1> to <5> above, wherein the first via electrically and directly connects the first photoelectric conversion element and the first pad.<7> The photodetector according to any one of <1> to <6>, wherein the first photoelectric conversion element further includes a first charge accumulation unit that accumulates the first charge generated by the first photoelectric conversion unit, and the first charge accumulation unit and the first pad are electrically connected via the first via. <8> The photodetector according to any one of <1> to <7>, wherein the second substrate further includes a semiconductor layer extending along the first plane, and the second via penetrates the semiconductor layer. <9> The photodetector according to <8>, wherein the semiconductor layer includes a through-hole that penetrates in the first direction, and the second via is inserted into the through-hole. <10> The photodetector according to <9>, wherein the semiconductor layer includes an element formation surface located on the opposite side to the second junction surface, and a semiconductor element included in a readout circuit that outputs a first signal based on the first charge is provided on the element formation surface. <11> The photodetector according to <8> or <9>, wherein the semiconductor layer includes a semiconductor region of a first conductivity type and a well region of a second conductivity type different from the first conductivity type and surrounding the second via, and the semiconductor element includes a gate electrode provided in the semiconductor region and electrically connected to the second via. <12> The photodetector according to any one of <1> to <11>, wherein the first substrate further includes a second photoelectric conversion element including a second photoelectric conversion unit that generates a second charge in accordance with an amount of received light and that is arranged adjacent to the first photoelectric conversion element, and the second photoelectric conversion element and the first pad are electrically connected via the first via. <13> The photodetector according to <12>, wherein the second photoelectric conversion element further includes a second charge accumulation unit that accumulates the second charge generated by the second photoelectric conversion unit, and the second charge accumulation unit and the first pad are electrically connected via the first via.<14> The photodetector according to any one of <1> to <13>, wherein the first substrate further has a third pad including a third bonding surface included in the first opposing surface, the second substrate further has a fourth pad including a fourth bonding surface included in the second opposing surface and bonded to the third bonding surface, and a fourth via electrically connected to the fourth pad and extending from the fourth pad in the first direction, the fourth pad having a first portion and a second portion connecting the first portion and the fourth via, a second partial occupation area occupied by the second portion in the first plane entirely overlapping in the first direction with a fourth via occupation area occupied by the fourth via in the first plane, and a first partial occupation area occupied by the first portion in the first plane being larger than the second partial occupation area. <15> The photodetector according to any one of <1> to <14>, wherein the first substrate further includes a third pad including a third bonding surface and a third via electrically connected to the third pad and extending from the third pad in the first direction, the second substrate further includes a fourth pad including a fourth bonding surface bonded to the third bonding surface and a fourth via electrically connected to the fourth pad and extending from the fourth pad in the first direction, and a portion of the fourth via is embedded in the fourth pad. <16> A photodetector comprising: a first substrate including a first opposing surface along a first plane and having a first photoelectric conversion element provided thereon; a second substrate including a second opposing surface bonded to the first opposing surface and having a first semiconductor element provided thereon; and a via extending through the first substrate and the second substrate in a first direction intersecting the first plane so as to penetrate both the first opposing surface and the second opposing surface, wherein the first photoelectric conversion element and the first semiconductor element are electrically connected via the via. <17> The photodetector device according to <16>, wherein the second substrate further has a conductive layer, and the via includes a first end connected to the first photoelectric conversion element, and a second end located opposite the first end in the first direction and abutting the conductive layer.<18> An electronic device comprising: a photodetector, the photodetector comprising: a first substrate having: a first photoelectric conversion element including a first photoelectric conversion unit that generates a first charge by photoelectrically converting light; a first pad including a first bonding surface along a first plane; and a first via extending in a first direction intersecting the first plane; a second substrate having: a second pad including a second bonding surface bonded to the first bonding surface; and a second via electrically connected to the second pad and extending from the second pad in the first direction; the first photoelectric conversion element and the first pad are electrically connected via the first via; and a first pad occupation area occupied by the first pad on the first plane entirely overlaps in the first direction with a first via occupation area occupied by the first via on the first plane. <19> An electronic device comprising: a photodetector, the photodetector comprising: a first substrate including a first bonding surface along a first plane and having a first photoelectric conversion element provided thereon; a second substrate including a second bonding surface bonded to the first bonding surface and having a first semiconductor element provided thereon; and a via extending in a first direction intersecting the first plane so as to penetrate both the first bonding surface and the second bonding surface in the first substrate and the second substrate; and the first photoelectric conversion element and the first semiconductor element being electrically connected to each other through the via.

[0171] This application claims priority based on Japanese Patent Application No. 2024-145520, filed on August 27, 2024, in the Japan Patent Office, the entire contents of which are incorporated herein by reference.

[0172] Those skilled in the art will recognize that various modifications, combinations, subcombinations, and variations may occur depending on design requirements and other factors, and are intended to be within the scope of the appended claims and their equivalents.

Claims

1. A photodetector comprising: a first substrate having a first opposing surface along a first plane, a first photoelectric conversion element including a first photoelectric conversion unit that generates a first charge by photoelectrically converting light, a first pad including a first bonding surface included in the first opposing surface, and a first via extending in a first direction intersecting the first plane; and a second substrate having a second opposing surface opposite the first opposing surface, a second pad including a second bonding surface included in the second opposing surface and bonded to the first bonding surface, and a second via electrically connected to the second pad and extending from the second pad in the first direction, wherein the first photoelectric conversion element and the first pad are electrically connected via the first via, and a first pad occupation area occupied by the first pad on the first plane entirely overlaps in the first direction with a first via occupation area occupied by the first via on the first plane.

2. The photodetector device according to claim 1, wherein the maximum dimension of said first pad in said first direction is greater than the maximum dimension of said first pad along said first plane.

3. A photodetector device as described in claim 1, wherein the entire second pad occupation area occupied by the second pad in the first plane overlaps in the first direction with the second via occupation area occupied by the second via in the first plane.

4. A photodetector device according to claim 3, wherein the maximum dimension of said second pad in said first direction is greater than the maximum dimension of said second pad along said first plane.

5. A photodetector device as described in claim 1, wherein the first substrate further has a first wiring layer arranged between the first opposing surface and the first photoelectric conversion element in the first direction, and the first via penetrates the first wiring layer in the first direction.

6. The photodetector according to claim 1, wherein the first via directly connects the first photoelectric conversion element and the first pad electrically.

7. The photodetector device according to claim 1, wherein the first photoelectric conversion element further has a first charge accumulation section that accumulates the first charge generated by the first photoelectric conversion section, and the first charge accumulation section and the first pad are electrically connected via the first via.

8. The photodetector device according to claim 1, wherein the second substrate further comprises a semiconductor layer extending along the first plane, and the second via penetrates the semiconductor layer.

9. The photodetector according to claim 8, wherein the semiconductor layer includes a through-hole penetrating in the first direction, and the second via is inserted into the through-hole.

10. A photodetector according to claim 9, wherein the semiconductor layer includes an element formation surface located on the opposite side to the second junction surface, and the element formation surface is provided with a semiconductor element included in a readout circuit that outputs a first signal based on the first charge.

11. A photodetector device according to claim 8, wherein the semiconductor layer includes a semiconductor region of a first conductivity type and a well region of a second conductivity type different from the first conductivity type and surrounding the second via, and the semiconductor element includes a gate electrode provided in the semiconductor region and electrically connected to the second via.

12. The photodetector device of claim 1, wherein the first substrate further comprises a second photoelectric conversion element including a second photoelectric conversion section that generates a second charge in accordance with the amount of received light and that is arranged adjacent to the first photoelectric conversion element, and the second photoelectric conversion element and the first pad are electrically connected via the first via.

13. The photodetector device according to claim 12, wherein the second photoelectric conversion element further has a second charge accumulation section that accumulates the second charge generated by the second photoelectric conversion section, and the second charge accumulation section and the first pad are electrically connected via the first via.

14. The photodetector device of claim 1, wherein the first substrate further has a third pad including a third bonding surface included in the first opposing surface, the second substrate further has a fourth pad including a fourth bonding surface included in the second opposing surface and bonded to the third bonding surface, and a fourth via electrically connected to the fourth pad and extending from the fourth pad in the first direction, the fourth pad having a first portion and a second portion connecting the first portion and the fourth via, the entire second portion-occupied area occupied by the second portion in the first plane overlaps in the first direction with a fourth via-occupied area occupied by the fourth via in the first plane, and the first portion-occupied area occupied by the first portion in the first plane is larger than the second portion-occupied area.

15. The photodetector device of claim 1, wherein the first substrate further has a third pad including a third bonding surface, the second substrate further has a fourth pad including a fourth bonding surface bonded to the third bonding surface, and a fourth via electrically connected to the fourth pad and extending from the fourth pad in the first direction, and a portion of the fourth via is embedded in the fourth pad.

16. A photodetector comprising: a first substrate including a first opposing surface along a first plane and having a first photoelectric conversion element provided thereon; a second substrate including a second opposing surface bonded to the first opposing surface and having a first semiconductor element provided thereon; and vias extending in a first direction intersecting the first plane so as to penetrate both the first opposing surface and the second opposing surface in the first substrate and the second substrate, wherein the first photoelectric conversion element and the first semiconductor element are electrically connected via the vias.

17. A photodetector device as described in claim 16, wherein the second substrate further has a conductive layer, and the via includes a first end connected to the first photoelectric conversion element and a second end located opposite the first end in the first direction and abutting the conductive layer.

18. An electronic device comprising a photodetector, wherein the photodetector comprises: a first substrate having a first photoelectric conversion element including a first photoelectric conversion unit that generates a first charge by photoelectrically converting light; a first pad including a first bonding surface along a first plane; and a first via extending in a first direction intersecting the first plane; a second substrate having a second pad including a second bonding surface bonded to the first bonding surface; and a second via electrically connected to the second pad and extending from the second pad in the first direction; the first photoelectric conversion element and the first pad are electrically connected via the first via; and a first pad occupation area occupied by the first pad on the first plane entirely overlaps in the first direction with a first via occupation area occupied by the first via on the first plane.

19. An electronic device comprising a photodetector, the photodetector comprising: a first substrate including a first bonding surface along a first plane and having a first photoelectric conversion element provided thereon; a second substrate including a second bonding surface bonded to the first bonding surface and having a first semiconductor element provided thereon; and vias extending in a first direction intersecting the first plane so as to penetrate both the first bonding surface and the second bonding surface in the first substrate and the second substrate, the first photoelectric conversion element and the first semiconductor element being electrically connected via the vias.

Images