Computational design of soft matter computers

Abstract

Organic field-effect transistors (OFETs) have some advantages over inorganic transistors, for example, due to being physically flexible and lightweight. Additionally, OFETs can cover large-areas and can potentially be mass-produced at a low cost. It is recognized herein, however, that a technical challenge related to OFET design is evaluating effects at multiple length scales during the design process.

Description

202321959COMPUTATIONAL DESIGN OF SOFT MATTER COMPUTERSGOVERNMENT RIGHTS

[0001] This invention was made with the government support under contract number FA8750-20-C-0542 awarded by the Defense Advanced Research Projects Agency (DARPA). The government has certain rights in this invention.BACKGROUND

[0002] Organic semiconductors (OSCs), for instance organic field-effect transistors (OFETs) have some advantages over inorganic transistors, for example, due to being physically flexible and lightweight. For example, OFETs can cover large-areas and can potentially be mass- produced at a low cost. It is recognized herein, however, that a technical challenge related to OSC design, such as OFET design, is evaluating effects at multiple length scales during the design process.SUMMARY

[0003] Methods and systems are disclosed herein for generating designs for various organic semiconductors (OSCs), such as organic field-effect transistors (OFETs). In particular, for example, designs and arrangements of OSCs can be generated in device so as to generate power performance area (PPA) optimized circuits for given functional requirements. A computational design computing system can be configured to generate designs for OFETs while integrating simulations and knowledge at each length scale relevant to the design and functioning of the OFET.

[0004] In an example aspect, a computational design computing system includes a memory storing instructions that, when executed by the processor, cause the processor to perform various operations. For example, the system can obtain design requirements corresponding to a power performance area. The system can perform a plurality of first simulations to determine respective outputs associated with a plurality of organic field effect transistors. Based on the respective outputs of the plurality of first simulations, the system can perform a plurality of second simulations to determine respective outputs associated with respective arrangements of202321959 select ones of the plurality of organic field effect transistors. Based on the respective outputs of the plurality of second simulations, the system can generate a circuit design that behaves in accordance with the power performance area. The circuit design can include at least one of the plurality of organic field effect transistors. In an example, the system can perform the plurality of first simulations on the plurality of organic field effect transistors at different lengths, such that multiple length scales of transistors are simulated. In another example, the system can perform the plurality of first simulations at a molecular level, so as to determine material characteristics associated with the plurality of organic field transistors. Further still, the system can perform the plurality of first simulations at a device level, so as to determine performance characteristics associated with the plurality of organic field transistors that are composed of multiple materials. In various examples, the system can perform the plurality of second simulations at a circuit level, so as to determine performance characteristics associated with the respective arrangements of plurality of organic field transistors.BRIEF DESCRIPTION OF THE DRAWINGS

[0005] The foregoing and other aspects of the present invention are best understood from the following detailed description when read in connection with the accompanying drawings. For the purpose of illustrating the invention, there is shown in the drawings embodiments that are presently preferred, it being understood, however, that the invention is not limited to the specific instrumentalities disclosed. Included in the drawings are the following Figures:

[0006] FIG. 1 is a block diagram of an example computation design computing system according to an example embodiment.

[0007] FIG. 2 shows an example of a computing environment within which embodiments of this disclosure may be implemented.DETAILED DESCRIPTION

[0008] As an initial matter, factors that affect the behavior of organic semiconductors (OSCs), for instance organic field-effect transistors (OFETs) include, but are not limited to, the relevant chemical identities of the molecules involved, the arrangement of materials, and the processing conditions. In some cases, to adequately model the phenomena represented by these factors, simulations at length scales ranging from angstrom to centimeters are required. At the angstrom to nanometer (nm) length-scales, the chemical structure of the molecules controls the ability of the material to behave as a semiconductor as well as partially influences how the molecules will assemble to form microstructures. It recognized herein that at202321959 nanometer to micrometer length scales, the processing conditions (in conjunction with the chemical structure) influence the molecular packing and the resulting microstructures of the material which dictate the OFET performance. Further, at length scales of nanometers to centimeters, the ordering and connections of different materials (device-scale arrangements) control the overall device behavior of the transistor or series of transistors. OFETs are used herein for purposes of example, but it will be understood that embodiments can be implemented with alternative OSCs, and all such OSCs are contemplated as being within the scope of this disclosure.

[0009] It is further recognized herein that evaluating various considerations in the development of OFETs (e.g., molecular design, efficient synthesis, novel polymerization, thin film microstructures, crystal structures, self-assembly, transistor fabrication, device physics) present various technical challenges. Further still, it is recognized herein that current approaches to designing OFETs are performed in a fragmented manner. Additionally, current simulation tools at each of the length scales are generally computationally intensive and have limited and varying accuracy. With respect to inorganic semi-conductors, the considerations at the molecular length scale (angstrom to nanometers) and at the system level can be enough for an integrated simulation environment. With respect to OFETs, however, additional considerations for the intermediate microstructure and molecular packing are important, as existing design environments do not take into account the overall contribution of each component to the design of the system. Thus, embodiments described herein define a multilength scale simulation and design environment that accounts for the complex design requirements in OFETs.

[0010] To the extent current approaches relate to the design of soft matter computing, those approaches generally only focus on the production of a single working example or demonstration of the scientific principal of a subsection of the whole system, or are based on scientific knowledge of a specific set of molecular chemistries or simulations at a single length scale, typically device-scale arrangements. It is recognized herein, however, that there is a need for system that performs design and simulation at multiple scales of an entire system. For example, current simulation and design environments for transistor systems address traditional silicon and metal transistors. Embodiments described herein, however, account for the behavior of soft matter organic materials, for instance their self-assembly, while also integrating the results from simulations at different scales for design.

[0011] Referring now to FIG. 1 , in accordance with various embodiments, a computational design computing system 100 can be configured to generate designs for organic202321959 semiconductors (OSCs), for instance organic field-effect transistors (OFETs), that achieve system design requirements while integrating simulations, data, and physics knowledge at each relevant length scale. The computation design computing system 100 can include one or more processors and memory having stored thereon applications, agents, and computer program modules including, for example, a machine learning module 102, a multi-scale simulation module 104 (which can consist of multiple modules), and a system design module 106.

[0012] It will be appreciated that the program modules, applications, computer-executable instructions, code, or the like depicted in FIG. 1 are merely illustrative and not exhaustive, and that processing described as being supported by any particular module may alternatively be distributed across multiple modules or performed by a different module. In addition, various program module(s), script(s), plug-in(s), Application Programming Interface(s) (API(s)), or any other suitable computer-executable code may be provided to support functionality provided by the program modules, applications, or computer-executable code depicted in FIG. 1 and / or additional or alternate functionality. Further, functionality may be modularized differently such that processing described as being supported collectively by the collection of program modules depicted in FIG. 1 may be performed by a fewer or greater number of modules, or functionality described as being supported by any particular module may be supported, at least in part, by another module. In addition, program modules that support the functionality described herein may form part of one or more applications executable across any number of systems or devices in accordance with any suitable computing model such as, for example, a client-server model, a peer-to-peer model, and so forth. In addition, any of the functionality described as being supported by any of the program modules depicted in FIG. 1 may be implemented, at least partially, in hardware and / or firmware across any number of devices.

[0013] Still referring to FIG. 1 , in various examples, the computational design computing system 100 can meet specific design requirements for power performance area (PPA) optimized circuits for given functional requirements. To design an optimized circuit containing one or more OFETs, the system design module 106 can use machine learning modules 102 to integrate the information from multi-scale simulation modules 104 (and other available experimental data), and then use an optimizer to meet design requirements. An example of the information to be connected in FIG. 1 in the machine learning module 102 follows. In an example, the design requirements set the power performance area (PPA) metrics for optimized circuits, then circuit-level simulations (e.g., using Simulation Program with Integrated Circuit Emphasis, SPICE, for the circuit simulations) evaluate the performance of the OFET(s) in a circuit. The properties of the OFET are obtained through device-level simulations (e.g., using a202321959 drift-diffusion model to simulate the charge transport in the device), where the devices are made up of multiple materials. The material characteristics are determined by the molecular-level simulations (e.g., molecular dynamics (MD) simulations, which can simulate molecular packing and microstructure of the material; as well as quantum mechanics (QM) simulations, which simulate the electronic properties of the molecules), which capture the details of the molecular chemistry and processing conditions. As an example of the machine learning modules 102, neural networks can be built for each simulation level to predict the simulation outputs based (relevant material properties for the level of simulation) on the simulation inputs (the details required for the simulations, such as the chemical structures, conditions, and the results from different levels of simulations), as well as neural networks linking each level of simulation to the final performance metrics. By using neural networks in this manner, the connections linking all levels of simulations are fully differentiable, which enables the use of optimization methods such as gradient-based methods (e.g., Adam optimizer) as a computationally efficient optimizer in the system design module 106. This optimizer can determine optimal inputs for any level of simulation and as such optimize the design performance.

[0014] In various examples, the multi-scale module 104 can perform simulations at each length scale. These simulations can be computationally intensive. To integrate the simulations into a single computational framework (e.g., computational design computing system 100), machine learning surrogate models can be built. Furthermore, machine learning increase the speed of simulations so as to enable larger scale simulations with higher computational efficiency (e.g., machine learning potentials that enable near quantum-level accuracy in molecular dynamics simulations). The machine learning module 102 can combine experimental results, domain knowledge, and simulation results (at different length scales and different fidelities) in hierarchical, physics aware, multi-fidelity models. Linear or non-linear multi-fidelity Gaussian Process models can enable fusion of information between different fidelity models, for example high fidelity physical experiments and detailed simulations, with physics-based estimations and other computationally efficient models. These types of models can also be built through a system of neural networks for each level of simulation and between levels of simulation. Such neural networks can include physics-informed neural networks (PINNS) to incorporate physics and Bayesian neural networks to enable hierarchical and multi-fidelity models.

[0015] In some cases, such as with respect to a multi-fidelity Gaussian process model, optimization of the design can be performed with a focus on a specific scale (e.g., focusing on any of the simulation levels such as by optimizing the arrangement of materials or the chemical202321959 structure of the molecules), and additional experiments or simulations can be scheduled depending on their cost and how much they would improve the machine learning model (e.g., using the uncertainty estimate from the Gaussian Process model to perform Bayesian optimization).

[0016] The multi-scale module 104 can perform various simulations, such as molecular dynamics simulations to determine the overall microstructure of the material (e.g., polymer selfassembly into lamellar layers of specific sizes) and the effects of different processing methods and conditions (such as temperature, solvent choices, and solvent drying rates). The molecular dynamics simulations can take the chemical structures of the molecules and the process conditions to determine the resulting microstructures. Furthermore, quantum level simulations (e.g., DFT) can determine properties (for example and without limitation, conductivity and band gap at the atomistic level) of a few molecules. The quantum mechanics simulations take the conditions (such as temperature) and the chemical structures of the molecules to determine relevant electrical properties. Due to the quantum-level simulations only being able to handle a smaller number of molecules, the calculations can be integrated, through machine learning (e.g., build a neural network that determines electrical properties for a given atomic environment), with the microstructures determined through molecular dynamics simulations to evaluate the properties of the entire material. The combination of the quantum level simulations and the molecular dynamics simulations can determine the electrical properties of the material. Next, the device-level simulations (e.g., using a drift-diffusion model), can simulate the charge transport in the device where the devices are made up of multiple materials, to determine the current-voltage behaviors of the device. Lastly, circuit-level simulations (e.g., SPICE) can make use of the current-voltage behaviors to determine the effect of device arrangements on the power performance area (PPA) behavior of the system. The system design module 106 organizes the effects of the different levels of simulations for OFETs to develop logic circuits that are optimized to meet specifications, such as cost, space, and performance requirements.

[0017] Still referring to FIG. 1 , the machine learning module 102 can perform design and optimization of the OFETs to meet specific requirements. For example, the machine learning module 102 can perform multi-fidelity modeling that incorporates simulation and experimental results. By combining these sources of information in a multi-fidelity model, a more accurate model can be generated. Consequently, in some cases, various cost and time requirements are improved, for example, because the simulations do not necessarily have to be developed to be quantitatively accurate (which can be very costly and time consuming, requiring adjustment for many different systems) and fewer experiments might be performed. For example, in some202321959 cases, the experiments might be cost and time intensive and the simulation results might not be quantitatively accurate (but still are qualitatively accurate, being able to mostly capture the overall trends between different values of input variables). The multi-scale modeling can incorporate the relevant information from the different scales. In some examples, the machine learning module 106 generates a multi-fidelity model if the information from different scales have varying degrees of accuracy, so as to build a more robust model in predicting the material characteristics that can integrate different simulation results from the multi-scale simulations module 104 to reduce overall experimental costs.

[0018] The machine-learning module 102 can generate physics aware models that take into account well-established theory and results to reduce the data requirements of training the model, thereby improving the model generalizability and model accuracy. Additionally, inverse modeling can include the previous techniques, so as to determine whether input variables will meet the material property requirements. For example, if the forward prediction models described above are fully differentiable, the machine learning module 102 can perform gradientbased methods to determine the inputs such as the molecular structure, processing conditions, and other system details to meet required material properties. Thus, the multi-scale simulation module 104 can incorporate various forward modeling from the machine learning module 102, for instance from multi fidelity, multi scale, and physics aware models. Additionally, the machine learning module 102 can perform inverse modeling (such as gradient-based methods) to determine the molecular structure, processing conditions, and other system details to meet required material properties.

[0019] In various examples, the computational design computing system process requirements and integrates the requirements into a system design. Processing requirements can include setting target property ranges and determining the limitations and boundaries of variables. As an example, a requirement might define a system that can act as a full adder with optimized PPA using materials from a specific set of chemistries. The requirements can be used with the system design to set up a design with variable chemistry, processing conditions, and system arrangements of the different components. The system design module 106 can determine where additional information can be acquired from experiments and simulations, for example by using a multi-fidelity Gaussian Process model. The experiments or simulations can be scheduled, and the results of the experiments and simulations can be integrated into the system design within an allocated budget.

[0020] The system 100 can enable the combination of relevant simulation results (even with some degree of inaccuracy), domain knowledge, and experimental results to design a system to202321959 meet requirements. The system 100 can perform optimization and can flexibly include / exclude different levels of detail as required so as to focus on optimizing throughout the system or a single component of the system. Thus, embodiments result in efficient use of data and while bringing together domain expertise to the design of a system, thereby conserving resources such as time and money.

[0021] Thus, as described herein, a computational design computing system includes a memory storing instructions that, when executed by the processor, cause the processor to perform various operations. For example, the system can obtain design requirements corresponding to a power performance area. The system can perform a plurality of first simulations to determine respective outputs associated with a plurality of organic field effect transistors. Based on the respective outputs of the plurality of first simulations, the system can perform a plurality of second simulations to determine respective outputs associated with respective arrangements of select ones of the plurality of organic field effect transistors. Based on the respective outputs of the plurality of second simulations, the system can generate a circuit design that behaves in accordance with the power performance area. The circuit design can include at least one of the plurality of organic field effect transistors. In an example, the system can perform the plurality of first simulations on the plurality of organic field effect transistors at different lengths, such that multiple length scales of transistors are simulated. In another example, the system can perform the plurality of first simulations at a molecular level, so as to determine material characteristics associated with the plurality of organic field transistors. Further still, the system can perform the plurality of first simulations at a device level, so as to determine performance characteristics associated with the plurality of organic field transistors that are composed of multiple materials. In various examples, the system can perform the plurality of second simulations at a circuit level, so as to determine performance characteristics associated with the respective arrangements of plurality of organic field transistors.

[0022] FIG. 2 illustrates an example of a computing environment within which embodiments of the present disclosure may be implemented. A computing environment 300 includes a computer system 310 that may include a communication mechanism such as a system bus 321 or other communication mechanism for communicating information within the computer system 310. The computer system 310 further includes one or more processors 320 coupled with the system bus 321 for processing the information.

[0023] The processors 320 may include one or more central processing units (CPUs), graphical processing units (GPUs), or any other processor known in the art. More generally, a202321959 processor as described herein is a device for executing machine-readable instructions stored on a computer readable medium, for performing tasks and may comprise any one or combination of, hardware and firmware. A processor may also comprise memory storing machine-readable instructions executable for performing tasks. A processor acts upon information by manipulating, analyzing, modifying, converting or transmitting information for use by an executable procedure or an information device, and / or by routing the information to an output device. A processor may use or comprise the capabilities of a computer, controller or microprocessor, for example, and be conditioned using executable instructions to perform special purpose functions not performed by a general purpose computer. A processor may include any type of suitable processing unit including, but not limited to, a central processing unit, a microprocessor, a Reduced Instruction Set Computer (RISC) microprocessor, a Complex Instruction Set Computer (CISC) microprocessor, a microcontroller, an Application Specific Integrated Circuit (ASIC), a Field-Programmable Gate Array (FPGA), a System-on-a-Chip (SoC), a digital signal processor (DSP), and so forth. Further, the processor(s) 320 may have any suitable microarchitecture design that includes any number of constituent components such as, for example, registers, multiplexers, arithmetic logic units, cache controllers for controlling read / write operations to cache memory, branch predictors, or the like. The microarchitecture design of the processor may be capable of supporting any of a variety of instruction sets. A processor may be coupled (electrically and / or as comprising executable components) with any other processor enabling interaction and / or communication there-between. A user interface processor or generator is a known element comprising electronic circuitry or software or a combination of both for generating display images or portions thereof. A user interface comprises one or more display images enabling user interaction with a processor or other device.

[0024] The system bus 321 may include at least one of a system bus, a memory bus, an address bus, or a message bus, and may permit exchange of information (e.g., data (including computer-executable code), signaling, etc.) between various components of the computer system 310. The system bus 321 may include, without limitation, a memory bus or a memory controller, a peripheral bus, an accelerated graphics port, and so forth. The system bus 321 may be associated with any suitable bus architecture including, without limitation, an Industry Standard Architecture (ISA), a Micro Channel Architecture (MCA), an Enhanced ISA (EISA), a Video Electronics Standards Association (VESA) architecture, an Accelerated Graphics Port (AGP) architecture, a Peripheral Component Interconnects (PCI) architecture, a PCI-Express202321959 architecture, a Personal Computer Memory Card International Association (PCMCIA) architecture, a Universal Serial Bus (USB) architecture, and so forth.

[0025] Continuing with reference to FIG. 2, the computer system 310 may also include a system memory 330 coupled to the system bus 321 for storing information and instructions to be executed by processors 320. The system memory 330 may include computer readable storage media in the form of volatile and / or nonvolatile memory, such as read only memory (ROM) 331 and / or random access memory (RAM) 332. The RAM 332 may include other dynamic storage device(s) (e.g., dynamic RAM, static RAM, and synchronous DRAM). The ROM 331 may include other static storage device(s) (e.g., programmable ROM, erasable PROM, and electrically erasable PROM). In addition, the system memory 330 may be used for storing temporary variables or other intermediate information during the execution of instructions by the processors 320. A basic input / output system 333 (BIOS) containing the basic routines that help to transfer information between elements within computer system 310, such as during start-up, may be stored in the ROM 331 . RAM 332 may contain data and / or program modules that are immediately accessible to and / or presently being operated on by the processors 320. System memory 330 may additionally include, for example, operating system 334, application modules 335, and other program modules 336. Application modules 335 may include aforementioned modules described for FIG. 1 and may also include a user portal for development of the application program, allowing input parameters to be entered and modified as necessary.

[0026] The operating system 334 may be loaded into the memory 330 and may provide an interface between other application software executing on the computer system 310 and hardware resources of the computer system 310. More specifically, the operating system 334 may include a set of computer-executable instructions for managing hardware resources of the computer system 310 and for providing common services to other application programs (e.g., managing memory allocation among various application programs). In certain example embodiments, the operating system 334 may control execution of one or more of the program modules depicted as being stored in the data storage 340. The operating system 334 may include any operating system now known or which may be developed in the future including, but not limited to, any server operating system, any mainframe operating system, or any other proprietary or non-proprietary operating system.

[0027] The computer system 310 may also include a disk / media controller 343 coupled to the system bus 321 to control one or more storage devices for storing information and instructions, such as a magnetic hard disk 341 and / or a removable media drive 342 (e.g., floppy202321959 disk drive, compact disc drive, tape drive, flash drive, and / or solid state drive). Storage devices 340 may be added to the computer system 310 using an appropriate device interface (e.g., a small computer system interface (SCSI), integrated device electronics (IDE), Universal Serial Bus (USB), or FireWire). Storage devices 341 , 342 may be external to the computer system 310.

[0028] The computer system 310 may include a user input interface or graphical user interface (GUI) 361 , which may comprise one or more input devices, such as a keyboard, touchscreen, tablet and / or a pointing device, for interacting with a computer user and providing information to the processors 320.

[0029] The computer system 310 may perform a portion or all of the processing steps of embodiments of the invention in response to the processors 320 executing one or more sequences of one or more instructions contained in a memory, such as the system memory 330. Such instructions may be read into the system memory 330 from another computer readable medium of storage 340, such as the magnetic hard disk 341 or the removable media drive 342. The magnetic hard disk 341 and / or removable media drive 342 may contain one or more data stores and data files used by embodiments of the present disclosure. The data store 340 may include, but are not limited to, databases (e.g., relational, object-oriented, etc.), file systems, flat files, distributed data stores in which data is stored on more than one node of a computer network, peer-to-peer network data stores, or the like. Data store contents and data files may be encrypted to improve security. The processors 320 may also be employed in a multi-processing arrangement to execute the one or more sequences of instructions contained in system memory 330. In alternative embodiments, hard-wired circuitry may be used in place of or in combination with software instructions. Thus, embodiments are not limited to any specific combination of hardware circuitry and software.

[0030] As stated above, the computer system 310 may include at least one computer readable medium or memory for holding instructions programmed according to embodiments of the invention and for containing data structures, tables, records, or other data described herein. The term “computer readable medium” as used herein refers to any medium that participates in providing instructions to the processors 320 for execution. A computer readable medium may take many forms including, but not limited to, non-transitory, non-volatile media, volatile media, and transmission media. Non-limiting examples of non-volatile media include optical disks, solid state drives, magnetic disks, and magneto-optical disks, such as magnetic hard disk 341 or removable media drive 342. Non-limiting examples of volatile media include dynamic memory, such as system memory 330. Non-limiting examples of transmission media include coaxial202321959 cables, copper wire, and fiber optics, including the wires that make up the system bus 321 . Transmission media may also take the form of acoustic or light waves, such as those generated during radio wave and infrared data communications.

[0031] Computer readable medium instructions for carrying out operations of the present disclosure may be assembler instructions, instruction-set-architecture (ISA) instructions, machine instructions, machine dependent instructions, microcode, firmware instructions, statesetting data, or either source code or object code written in any combination of one or more programming languages, including an object oriented programming language such as Smalltalk, C++ or the like, and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The computer readable program instructions may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection may be made to an external computer (for example, through the Internet using an Internet Service Provider). In some embodiments, electronic circuitry including, for example, programmable logic circuitry, field-programmable gate arrays (FPGA), or programmable logic arrays (PLA) may execute the computer readable program instructions by utilizing state information of the computer readable program instructions to personalize the electronic circuitry, in order to perform aspects of the present disclosure.

[0032] Aspects of the present disclosure are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the disclosure. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, may be implemented by computer readable medium instructions.

[0033] The computing environment 300 may further include the computer system 310 operating in a networked environment using logical connections to one or more remote computers, such as remote computing device 380. The network interface 370 may enable communication, for example, with other remote devices 380 or systems and / or the storage devices 341 , 342 via the network 371 . Remote computing device 380 may be a personal computer (laptop or desktop), a mobile device, a server, a router, a network PC, a peer device or other common network node, and typically includes many or all of the elements described above relative to computer system 310. When used in a networking environment, computer202321959 system 310 may include modem 372 for establishing communications over a network 371 , such as the Internet. Modem 372 may be connected to system bus 321 via user network interface 370, or via another appropriate mechanism.

[0034] Network 371 may be any network or system generally known in the art, including the Internet, an intranet, a local area network (LAN), a wide area network (WAN), a metropolitan area network (MAN), a direct connection or series of connections, a cellular telephone network, or any other network or medium capable of facilitating communication between computer system 310 and other computers (e.g., remote computing device 380). The network 371 may be wired, wireless or a combination thereof. Wired connections may be implemented using Ethernet, Universal Serial Bus (USB), RJ-6, or any other wired connection generally known in the art. Wireless connections may be implemented using Wi-Fi, WiMAX, and Bluetooth, infrared, cellular networks, satellite or any other wireless connection methodology generally known in the art. Additionally, several networks may work alone or in communication with each other to facilitate communication in the network 371 .

[0035] It should be appreciated that the program modules, applications, computerexecutable instructions, code, or the like depicted in FIG. 2 as being stored in the system memory 330 are merely illustrative and not exhaustive and that processing described as being supported by any particular module may alternatively be distributed across multiple modules or performed by a different module. In addition, various program module(s), script(s), plug-in(s), Application Programming Interface(s) (API(s)), or any other suitable computer-executable code hosted locally on the computer system 310, the remote device 380, and / or hosted on other computing device(s) accessible via one or more of the network(s) 371 , may be provided to support functionality provided by the program modules, applications, or computer-executable code depicted in FIG. 2 and / or additional or alternate functionality. Further, functionality may be modularized differently such that processing described as being supported collectively by the collection of program modules depicted in FIG. 2 may be performed by a fewer or greater number of modules, or functionality described as being supported by any particular module may be supported, at least in part, by another module. In addition, program modules that support the functionality described herein may form part of one or more applications executable across any number of systems or devices in accordance with any suitable computing model such as, for example, a client-server model, a peer-to-peer model, and so forth. In addition, any of the functionality described as being supported by any of the program modules depicted in FIG. 2 may be implemented, at least partially, in hardware and / or firmware across any number of devices.202321959

[0036] It should further be appreciated that the computer system 310 may include alternate and / or additional hardware, software, or firmware components beyond those described or depicted without departing from the scope of the disclosure. More particularly, it should be appreciated that software, firmware, or hardware components depicted as forming part of the computer system 310 are merely illustrative and that some components may not be present or additional components may be provided in various embodiments. While various illustrative program modules have been depicted and described as software modules stored in system memory 330, it should be appreciated that functionality described as being supported by the program modules may be enabled by any combination of hardware, software, and / or firmware. It should further be appreciated that each of the above-mentioned modules may, in various embodiments, represent a logical partitioning of supported functionality. This logical partitioning is depicted for ease of explanation of the functionality and may not be representative of the structure of software, hardware, and / or firmware for implementing the functionality. Accordingly, it should be appreciated that functionality described as being provided by a particular module may, in various embodiments, be provided at least in part by one or more other modules. Further, one or more depicted modules may not be present in certain embodiments, while in other embodiments, additional modules not depicted may be present and may support at least a portion of the described functionality and / or additional functionality. Moreover, while certain modules may be depicted and described as sub-modules of another module, in certain embodiments, such modules may be provided as independent modules or as sub-modules of other modules.

[0037] Although specific embodiments of the disclosure have been described, one of ordinary skill in the art will recognize that numerous other modifications and alternative embodiments are within the scope of the disclosure. For example, any of the functionality and / or processing capabilities described with respect to a particular device or component may be performed by any other device or component. Further, while various illustrative implementations and architectures have been described in accordance with embodiments of the disclosure, one of ordinary skill in the art will appreciate that numerous other modifications to the illustrative implementations and architectures described herein are also within the scope of this disclosure. In addition, it should be appreciated that any operation, element, component, data, or the like described herein as being based on another operation, element, component, data, or the like can be additionally based on one or more other operations, elements, components, data, or the like. Accordingly, the phrase “based on,” or variants thereof, should be interpreted as “based at least in part on.”202321959

[0038] The flowchart and block diagrams in the Figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of instructions, which comprises one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the block may occur out of the order noted in the Figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and / or flowchart illustration, and combinations of blocks in the block diagrams and / or flowchart illustration, can be implemented by special purpose hardware-based systems that perform the specified functions or acts or carry out combinations of special purpose hardware and computer instructions.

Claims

202321959CLAIMSWhat is claimed is:1 . A computational design computing system, comprising: a memory storing instructions that, when executed by the processor, cause the processor to: obtain design requirements corresponding to a power performance area; perform a plurality of first simulations to determine respective outputs associated with a plurality of organic field effect transistors; based on the respective outputs of the plurality of first simulations, perform a plurality of second simulations to determine respective outputs associated with respective arrangements of select ones of the plurality of organic field effect transistors; and based on the respective outputs of the plurality of second simulations, generate a circuit design that behaves in accordance with the power performance area, the circuit design including at least one of the plurality of organic field effect transistors.

2. The system as recited in claim 1 , the memory further storing instructions that, when executed by the processor, cause the processor to: perform the plurality of first simulations on the plurality of organic field effect transistors at different lengths, such that multiple length scales of transistors are simulated.

3. The system as recited in claim 1 , the memory further storing instructions that, when executed by the processor, cause the processor to: perform the plurality of first simulations at a molecular level, so as to determine material characteristics associated with the plurality of organic field transistors.

4. The system as recited in claim 1 , the memory further storing instructions that, when executed by the processor, cause the processor to: perform the plurality of first simulations at a device level, so as to determine performance characteristics associated with the plurality of organic field transistors that are composed of multiple materials.2023219595. The system as recited in claim 1 , the memory further storing instructions that, when executed by the processor, cause the processor to: perform the plurality of second simulations at a circuit level, so as to determine performance characteristics associated with the respective arrangements of plurality of organic field transistors.

6. A method performed by a computational design computing system, the method comprising: obtaining design requirements corresponding to a power performance area; performing a plurality of first simulations to determine respective outputs associated with a plurality of organic field effect transistors; based on the respective outputs of the plurality of first simulations, performing a plurality of second simulations to determine respective outputs associated with respective arrangements of select ones of the plurality of organic field effect transistors; and based on the respective outputs of the plurality of second simulations, generating a circuit design that behaves in accordance with the power performance area, the circuit design including at least one of the plurality of organic field effect transistors.

7. The method as recited in claim 6, the method further comprising: performing the plurality of first simulations on the plurality of organic field effect transistors at different lengths, such that multiple length scales of transistors are simulated.

8. The method as recited in claim 6, the method further comprising: performing the plurality of first simulations at a molecular level, so as to determine material characteristics associated with the plurality of organic field transistors.

9. The method as recited in claim 6, the method further comprising: performing the plurality of first simulations at a device level, so as to determine performance characteristics associated with the plurality of organic field transistors that are composed of multiple materials.

10. The method as recited in claim 6, the method further comprising:202321959 performing the plurality of second simulations at a circuit level, so as to determine performance characteristics associated with the respective arrangements of plurality of organic field transistors.

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