Display panel and display device

Abstract

A display panel and a display device. A second display area (AA2) of the display panel is located on at least one side of a first display area (AA1) in a first direction (X). A display area (AA) comprises a plurality of data lines (11) extending in a second direction (Y); first data lines (111) are arranged in the first display area (AA1); and second data lines (112) are arranged in the second display area (AA2). A non-display area (NA) comprises a plurality of demultiplexers (13). The display area (AA) further comprises a plurality of auxiliary wires (12). Each demultiplexer (13) comprises N switching elements (T), and first ends of the switching elements (T) of a same demultiplexer (13) are electrically connected to an input end of the demultiplexer (13). N first data lines (111) are electrically connected to second ends of N switching elements (T) in a same first demultiplexer (131) in a one-to-one correspondence manner; N auxiliary wires (12) are electrically connected to second ends of N switching elements (T) in a same second demultiplexer (132) in a one-to-one correspondence manner; and the ratio of the number of first demultiplexers (131) to the number of second demultiplexers (132) ranges from 0.8 to 1.5.

Description

Display panel and display device

[0001] The present application claims priority to the Chinese patent application No. 202411244810.1, filed on September 5, 2024, to the Chinese Patent Office, the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] The present application relates to the technical field of display, for example, to a display panel and a display device. BACKGROUND

[0003] With the development of display technology, the screen-to-body ratio of display panels is getting larger and larger, and the narrow frame technology is getting more and more attention.

[0004] In some display panels, a plurality of distribution circuits and peripheral circuits such as fan-out wires are arranged in the frame area of the display panel to provide signals for the display area circuit of the display panel. However, as the size of the display panel increases, the plurality of distribution circuits and fan-out wires will occupy a large frame area, which is not conducive to the development of narrow frame.

[0005] SUMMARY

[0006] The embodiments of the present application provide a display panel and a display device to further realize the narrow frame design of the display panel.

[0007] In a first aspect, the embodiments of the present application provide a display panel, comprising: a display area and a non-display area at least partially surrounding the display area;

[0008] The display area comprises a first display area and a second display area; the second display area is located at least one side of the first display area along a first direction; the display area further comprises a plurality of data lines arranged along the first direction and extending along a second direction; the first direction and the second direction intersect; the data lines comprise first data lines and second data lines; the first data lines are arranged in the first display area; the second data lines are arranged in the second display area; the display area further comprises a plurality of auxiliary wires;

[0009] The non-display area comprises a plurality of multiplexers; the auxiliary wires transmit signals output by the multiplexers to the second data lines;

[0010] Each of the multiplexers comprises N switching elements; the first ends of the switching elements of the same multiplexer are electrically connected to the input end of the multiplexer;

[0011] The plurality of distributors include a first plurality of distributors and a second plurality of distributors; along the first direction, the N first data lines are electrically connected one by one with the second ends of the N switch elements in the same first plurality of distributors; along the first direction, the N auxiliary wires are electrically connected one by one with the second ends of the N switch elements in the same second plurality of distributors; N is an integer greater than 1; wherein the ratio of the number of the first plurality of distributors to the number of the second plurality of distributors ranges from 0.8 to 1.5.

[0012] In a second aspect, the embodiments of the present application further provide a display device, which comprises the display panel provided by any of the embodiments of the present application. BRIEF DESCRIPTION OF DRAWINGS

[0013] FIG. 1 is a structural schematic diagram of a display panel provided by an embodiment of the present application;

[0014] FIG. 2 is a structural schematic diagram of another display panel provided by an embodiment of the present application;

[0015] FIG. 3 is a partial structural schematic diagram of a display panel provided by an embodiment of the present application;

[0016] FIG. 4 is a partial structural schematic diagram of another display panel provided by an embodiment of the present application;

[0017] FIG. 5 is a schematic diagram of a film layer structure of a plurality of distributors of the display panel in FIG. 4;

[0018] FIG. 6 is a schematic diagram of another film layer structure of the plurality of distributors of the display panel in FIG. 4;

[0019] FIG. 7 is a schematic diagram of a film layer structure of the plurality of distributors of a display panel provided by an embodiment of the present application;

[0020] FIG. 8 is a schematic diagram of a film layer structure of the plurality of distributors of another display panel provided by an embodiment of the present application;

[0021] FIG. 9 is a schematic diagram of a cross-sectional structure of a display panel provided by an embodiment of the present application;

[0022] FIG. 10 is a schematic diagram of a cross-sectional structure of another display panel provided by an embodiment of the present application;

[0023] FIG. 11 is a schematic diagram of a cross-sectional structure of another display panel provided by an embodiment of the present application;

[0024] FIG. 12 is a partial structural schematic diagram of another display panel provided by an embodiment of the present application;

[0025] FIG. 13 is a partial structural schematic diagram of another display panel provided by an embodiment of the present application;

[0026] FIG. 14 is a schematic view of a partial structure of another display panel according to an embodiment of the present application;

[0027] FIG. 15 is a schematic view of a partial enlarged structure of an S1 region of the display panel of FIG. 12;

[0028] FIG. 16 is a schematic view of a partial structure of another display panel according to an embodiment of the present application;

[0029] FIG. 17 is a schematic view of a partial structure of another display panel according to an embodiment of the present application;

[0030] FIG. 18 is a schematic view of a partial structure of another display panel according to an embodiment of the present application;

[0031] FIG. 19 is a schematic view of a partial structure of another display panel according to an embodiment of the present application;

[0032] FIG. 20 is a schematic view of a partial structure of another display panel according to an embodiment of the present application;

[0033] FIG. 21 is a timing chart of a control signal line according to an embodiment of the present application;

[0034] FIG. 22 is a schematic view of a partial structure of another display panel according to an embodiment of the present application;

[0035] FIG. 23 is a schematic view of a film layer structure of a display panel according to an embodiment of the present application;

[0036] FIG. 24 is a schematic view of a film layer structure of another display panel according to an embodiment of the present application;

[0037] FIG. 25 is a schematic view of a structure of a display device according to an embodiment of the present application. DETAILED DESCRIPTION

[0038] The present application will be described in detail below with reference to the accompanying drawings and embodiments. It can be understood that the specific embodiments described herein are merely intended for explaining the present application, but not limiting the present application. In addition, for the convenience of description, only parts related to the present application are shown in the accompanying drawings, but not all structures.

[0039] FIG. 1 is a structural schematic diagram of a display panel provided by an embodiment of the present application. The display panel includes a display area AA' and a non-display area NA'. The display area AA' includes data lines 11' extending along a direction Y' and arranged along a direction X'. The non-display area NA' is provided with peripheral wires and peripheral circuits. The non-display area NA' of a lower step area of the display panel includes fan-out wires 16' and a binding area 15'. The data lines 11' are electrically connected to corresponding binding terminals of the binding area 15' through the fan-out wires 16', and are configured to transmit signals of the binding terminals to the data lines 11'. Although the binding area 15' can be bent to the back of the display panel to reduce the width of the lower frame, the fan-out wires 16' occupy a large amount of space of the lower frame, the width of the lower frame is B1', and the R corner area 17' also needs to be designed with the fan-out wires 16', which hinders the design of a narrow frame.

[0040] The present embodiment adopts a technology of arranging part of the fan-out wires in the display area (Fanout in AA, FIAA). The metal wires in the display area are increased as FIAA wires, which reduces the number of fan-out wires arranged in the lower R corner, reduces the width of the lower R corner and the lower frame, and at the same time, the number of multi-way distribution circuits corresponding to the FIAA wires is arranged, which reduces the number of pins of the driving chip required, saves the cost of the driving chip, and reduces the number of signals required to be provided by the driving chip. The reduction of the number of signals can enhance the signal quality output by the driving chip, and improve the charging efficiency of the pixel circuit of the display panel. The present embodiment provides a display panel. As shown in FIG. 2 and FIG. 3, FIG. 2 is a structural schematic diagram of another display panel provided by an embodiment of the present application, and FIG. 3 is a partial structural schematic diagram of a display panel provided by an embodiment of the present application. The display panel includes a display area AA and a non-display area NA surrounding at least part of the display area AA.

[0041] The display area AA includes a first display area AA1 and a second display area AA2; the second display area AA2 is located at least one side of the first display area AA1 along a first direction X; the display area AA includes a plurality of data lines 11 arranged along the first direction X and extending along a second direction Y; the first direction X and the second direction Y intersect; the data lines 11 include first data lines 111 and second data lines 112; the first data lines 111 are located in the first display area AA1; the second data lines 112 are located in the second display area AA2; and the display area AA includes a plurality of auxiliary wires 12.

[0042] The non-display area NA includes a plurality of multi-way distributors 13; and the auxiliary wires 12 transmit signals output by the multi-way distributors 13 to the second data lines 112.

[0043] Each multi-way distributor 13 includes N switching elements T; the first ends of the switching elements T of the same multi-way distributor 13 are electrically connected to the input end of the multi-way distributor 13;

[0044] The plurality of distributors 13 include a first plurality of distributors 131 and a second plurality of distributors 132; the N first data lines 111 are electrically connected one by one to the second ends of N switch elements T in the same first plurality of distributors 131; the N auxiliary wires 12 are electrically connected one by one to the second ends of N switch elements T in the same second plurality of distributors 132; N is an integer greater than 1; and the ratio of the number of the first plurality of distributors 131 to the number of the second plurality of distributors 132 ranges from 0.8 to 1.5.

[0045] In the embodiments of the present application, the display panel includes a first display area and a second display area arranged on at least one side of the first display area along a first direction. The first display area includes first data lines extending along a second direction; and the second display area includes second data lines. The non-display area includes a plurality of distributors, and the display area further includes auxiliary wires to transmit signals output by the distributors to the second data lines. Along the first direction, N first data lines are connected one by one to the second ends of N switch elements in the first plurality of distributors, and N auxiliary wires are connected one by one to the second ends of N switch elements in the second plurality of distributors. The ratio of the number of the first plurality of distributors to the number of the second plurality of distributors ranges from 0.8 to 1.5. That is, in the embodiments, the auxiliary wires are used to replace part of the fan-out wires in the non-display area of the panel in the related art to transmit data signals to the second data lines, thereby reducing the occupied space of the lower frame of the display panel and achieving narrow-frame design of the display panel. Moreover, the number of the second plurality of distributors connected to the auxiliary wires in the non-display area is close to the number of the first plurality of distributors connected to the first data lines or the difference is small, so that the second plurality of distributors are arranged in the lower frame to reduce the occupied space of the second plurality of distributors in the lower R corner, thereby further achieving narrow-frame design of the lower R corner and leaving layout space for other wires in the lower R corner.

[0046] The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of the present application.

[0047] The display panel comprises a display area AA and a non-display area NA surrounding the display area AA. The non-display area NA can be arranged around the display area AA, or arranged around part of the display area AA. In this embodiment, the non-display area NA is arranged around the display area AA. The display area AA is provided with data lines 11 extending along the second direction Y and arranged along the first direction X, wherein the first direction X and the second direction Y intersect, and optionally, the first direction X and the second direction Y can be perpendicular to each other. The data lines 11 can be divided into first data lines 111 and second data lines 112. Optionally, the display area AA can be divided into a first display area AA1 and a second display area AA2 according to the classification of the data lines. The first display area AA1 is provided with the first data lines 111, and the second display area AA2 is provided with the second data lines 112. As shown in FIG. 2, along the first direction X, the second display area AA2 is located on at least one side of the first display area AA1. As shown in FIG. 2, the display area AA can comprise two second display areas AA2, and the two second display areas AA2 are respectively arranged on opposite sides of the first display area AA1. The display area AA can also only comprise one second display area AA2, and the second display area AA2 is arranged on one side of the first display area AA1. In summary, the second display area AA2 is close to the edge of the display panel relative to the first display area AA1. Referring to the R corner area 17 in FIG. 2, the second display area AA2 is arranged close to the R corner area 17 relative to the first display area AA1.

[0048] The non-display area NA further includes a plurality of demultipulators 13. Optionally, the non-display area NA further includes a binding area 15, the binding area 15 is located on a side of the demultipulators 13 away from the display area AA, and an input end of the demultipulator 13 is electrically connected to a corresponding binding terminal 151 of the binding area 15. As shown in FIG. 3, the non-display area NA of the lower step area of the display panel can be provided with a demultiplication circuit area 14 and a binding area 15. The demultiplication circuit area 14 includes a plurality of demultipulators 13, and the binding area 15 includes a plurality of binding terminals 151. The binding terminal 151 is electrically connected to the input end of the corresponding demultipulator 13 through a fan-out wire 16, and the output end of the demultipulator 13 is electrically connected to the corresponding data line 11, so that the signal obtained by the binding terminal 151 can be finally transmitted to the corresponding data line 11. The demultipulator 13 includes a first demultipulator 131 and a second demultipulator 132. The first demultipulator 131 is configured to transmit the signal obtained by the binding terminal 151 to the first data line 111, and the second demultipulator 132 is configured to transmit the signal obtained by the binding terminal 151 to the second data line 112. It should be noted that the display area AA further includes a plurality of auxiliary wires 12, the auxiliary wires 12 are connected between the second demultipulator 132 and the second data line 112 and are configured to transmit the signal output by the second demultipulator 132 to the second data line 112. In the embodiment, the auxiliary wires 12 are arranged in the display area AA, and the second data line 112 of the second display area AA2 close to the R corner area 17 is connected to the demultipulator 13 through the auxiliary wires 12, without the need to arrange the fan-out wire, in other words, the position of the fan-out wire of the second data line 112 is moved to the display area AA, thereby reducing the space occupation of the non-display area of the lower step, for example, as shown in FIG. 2, the lower frame width is B1. Compared with the lower frame width B1' of the display panel in FIG. 1, the width occupied by the fan-out wire is effectively shortened in the embodiment, and the narrow frame design of the display panel is further realized. It can be understood that, in order to distinguish the auxiliary wires 12 and the data lines 11, the auxiliary wires 12 in the embodiment are represented by dashed lines, and the data lines 11 are represented by solid lines.

[0049] Referring to FIG. 3, the specific structure of each multiplexer 13 includes N switch elements T, N being an integer greater than 1. The switch element T includes a control end (optionally, a gate), a first end, and a second end. The switch element T can be controlled to turn on or turn off by adjusting the control signal of the control end of the switch element T. For example, when the control signal is high, the switch element T turns on; when the control signal is low, the switch element T turns off. Alternatively, when the control signal is high, the switch element T turns off; when the control signal is low, the switch element T turns on. The first ends of the N switch elements T of the same multiplexer 13 are electrically connected to the input end of the multiplexer 13, and the second ends are respectively N output ends of the multiplexer 13. As shown in FIG. 2, along the first direction X, the second ends of the N switch elements T of the same multiplexer 13 are electrically connected to the N data lines 11 one by one, so as to transmit signals to the corresponding data lines 11. In this embodiment, the second ends of the N switch elements T of the first multiplexer 131 are electrically connected to the N first data lines 111 one by one; the second ends of the N switch elements T of the second multiplexer 132 are electrically connected to the N auxiliary wires 12 one by one, and the N auxiliary wires 12 are electrically connected to the N second data lines 112 one by one. In addition, optionally, the non-display area NA further includes N switch control lines; the control ends of the N switch elements T of the same multiplexer 13 are electrically connected to the switch control lines one by one. The corresponding multiplexer 13 can be provided with N control signal lines, and the N control signal lines are arranged one by one with the control ends of the N switch elements T, so as to turn on the N switch elements T in time. Optionally, in this embodiment, the value of N can be set according to the size of the display panel and the number of data lines. As shown in FIG. 2, when the number of data lines is small, each multiplexer 13 can include 2 switch elements T, and the display panel is provided with 2 control signal lines MUX1 and MUX2. FIG. 4 is a schematic view of a partial structure of another display panel provided in this embodiment. As shown in FIG. 4, when the number of data lines is large, each multiplexer 13 includes 4 switch elements T, and the display panel is provided with 4 control signal lines MUX1, MUX2, MUX3, and MUX4. Wherein, N can have other values, which are not listed one by one here.

[0050] Optionally, in order to distinguish the first and second multiplexers 131 and 132, the switch element T of the first multiplexer 131 is referred to as the first switch element T1, and the switch element T of the second multiplexer 132 is referred to as the second switch element T2. In the embodiment, the ratio of the number of the first multiplexers 131 to the number of the second multiplexers 132 ranges from 0.8 to 1.5. Then, the difference between the number of the first multiplexers 131 and the number of the second multiplexers 132 is small. In the embodiment, the number of the auxiliary wires 12 is increased, and the number of the auxiliary wires 12 is effectively controlled, that is, the number ratio of the first data lines 111 to the second data lines 112 is controlled to range from 0.8 to 1.5. In the meantime, the setting position of the multiplexer 13 is effectively controlled, so that the multiplexer 13 is set away from the R-angle area and is concentrated in the middle area of the lower frame, thereby further reducing the frame width of the R-angle area, realizing the narrow frame design of the R-angle, and leaving layout space for other wires in the lower R-angle area. It can be understood that when the number ratio of the first multiplexers 131 to the second multiplexers 132 is less than 0.8, the width of the lower frame of the display panel along the first direction is relatively wide. When the binding area is bent away from the light-emitting surface of the display panel, the width of the lower frame of the display panel affects the assembly effect of the display panel module. When the number ratio of the first multiplexers 131 to the second multiplexers 132 is greater than 1.5, the number of the second data lines is relatively large, which affects the layout of the display area and the pixel circuit in the middle display area.

[0051] Optionally, along the first direction X, the adjacent N first data lines 111 can be electrically connected one by one to the second ends of the N switch elements T in the same first multiplexer 131. Along the first direction X, the adjacent N auxiliary wires 12 can be electrically connected one by one to the second ends of the N switch elements T in the same second multiplexer 132.

[0052] Continuing to refer to FIG. 3, the N data lines 11 connected with the same multiplexer 13 in the embodiment can be N adjacent data lines 11 along the first direction X. The adjacent N first data lines 111 are electrically connected with the second ends of the N first switch elements T1 in the same first multiplexer 131 one by one; the adjacent N second data lines 112 are electrically connected with the adjacent N auxiliary wires 12 one by one; and the adjacent N auxiliary wires 12 are electrically connected with the second ends of the N second switch elements T2 in the same second multiplexer 132 one by one. As shown in FIG. 3 and FIG. 4, when the adjacent N first data lines 111 are connected with the same first multiplexer 131, the first connecting leads 161 connecting the first data lines 111 and the second ends of the first switch elements T1 can be set to be short, so as to reduce the path resistance value for the first data lines 111 to transmit signals, and improve the display accuracy of the display panel. Moreover, the adjacent two first connecting leads 161 are not prone to cross each other, for example, along the first direction, the wth first data line 111 in the adjacent N first data lines 111 is electrically connected with the wth first switch element T1 of the first multiplexer 131, and w is a positive integer less than or equal to N. All the first connecting leads 161 can be arranged in the same layer, thereby saving the manufacturing process of the display panel and improving the manufacturing efficiency of the display panel. It can be understood that when the adjacent N auxiliary wires 12 are connected with the same second multiplexer 132, the second connecting leads 162 connecting the auxiliary wires 12 and the second ends of the second switch elements T2 can be set to be short, so as to reduce the path resistance value for the second data lines 112 to transmit signals, and improve the display accuracy of the display panel. Moreover, the adjacent two second connecting leads 162 are not prone to cross each other, and all the second connecting leads 162 can be arranged in the same layer, thereby saving the manufacturing process of the display panel and improving the manufacturing efficiency of the display panel. Optionally, when the first connecting leads are arranged in the same layer and the second connecting leads are arranged in the same layer, and the first connecting leads and the second connecting leads are located in different metal film layers, the materials of the first connecting leads connected with the plurality of first data lines can be the same, and the materials of the second connecting leads connected with the plurality of second data lines can also be the same, which is beneficial to the display effect.

[0053] Optionally, the ratio of the number of the first multiplexers 131 to the number of the second multiplexers 132 ranges from 1 to 1.25. The embodiment controls the number of the first multiplexers 131 to be greater than or equal to the number of the second multiplexers 132 while keeping the difference between the number of the first multiplexers 131 and the number of the second multiplexers 132 small, so as to ensure that there is enough space in the first display area AA1 to arrange the auxiliary wires 12, avoid the setting density of the auxiliary wires 12 in the first display area AA1 being greater than the setting density of the second display area AA2, ensure that the setting density of the auxiliary wires 12 in the first display area AA1 and the second display area AA2 is uniform, and improve the display uniformity of the display panel. Moreover, the second data lines 112 in the second display area AA2 do not need to be provided with corresponding fan-out wires, but are electrically connected to the multiplexers 13 through the auxiliary wires 12, which effectively reduces the frame width of the R-angle area and is conducive to the narrow-frame design of the display panel.

[0054] Optionally, the auxiliary wires 12 can include first auxiliary wires 121 extending along the first direction X and second auxiliary wires 122 extending along the second direction Y; the first auxiliary wires 121 are provided to connect the corresponding second data lines 112 and the second auxiliary wires 122; and the second auxiliary wires 122 are electrically connected to the second ends of the switch elements T in the second multiplexers 132.

[0055] Referring to FIG. 3 and FIG. 4, the auxiliary wire 12 includes a first auxiliary wire 121 and a second auxiliary wire 122 electrically connected. The first auxiliary wire 121 extends along the first direction X and is electrically connected with the corresponding second data line 112. The second auxiliary wire 122 is electrically connected with the corresponding second switch element T2 of the corresponding second multiplexer 132. Referring to FIG. 2, in the embodiment, the display area AA can include pixel driving circuits 31 arranged in an array. The data line 11 and the auxiliary wire 12 are arranged in the gap between adjacent pixel driving circuits 31. For example, the pixel driving circuits 31 are arranged in rows along the first direction X and in columns along the second direction Y. The first auxiliary wire 121 is arranged in the gap between adjacent two rows of pixel driving circuits 31. The second auxiliary wire 122 is arranged in the gap between adjacent two columns of pixel driving circuits 31. Optionally, the display panel further includes an auxiliary line segment 12a. Because the second auxiliary wire 122 does not extend to the entire display area AA along the second direction Y, the auxiliary line segment 12a can fill the space of the display area AA which is not extended by the second auxiliary wire 122. The auxiliary line segment 12a is disconnected from the second auxiliary wire 122. The auxiliary line segment 12a can be connected with a power signal or other reference signal, so as to reduce the voltage drop of the power signal or the reference signal. In the plane parallel to the entire display panel, the auxiliary line segment 12a and the second auxiliary wire 122 are uniformly distributed in the display area, so as to improve the uniformity of the layout of the auxiliary wire 12 and the auxiliary line segment 12a in the display area AA, thereby improving the uniformity of the display of the display panel. Optionally, in the embodiment, the first display area AA1 and the second display area AA2 are both provided with the auxiliary line segment 12a extending along the second direction Y, so as to form a grid shape of the auxiliary wire 12 and the auxiliary line segment 12a in the entire display area AA, reduce the energy loss of the power signal or other reference signal, avoid the influence of the auxiliary wire 12 arranged in part of the area on the signals of the data line and other part of the wire, avoid the problem of uneven display brightness in different areas of the display panel, and improve the display effect of the display panel.

[0056] Optionally, the non-display area can include a multiplexer area 14. The multiplexer area 14 is provided with the multiplexer 13. It should be noted that in the embodiment, the fan-out area is formed between the display area AA and the binding area 15. The fan-out area includes the connection lead (the first connection lead 161 and the second connection lead 162) connecting the data line 11 and the multiplexer 13, the multiplexer 13, and the fan-out wire 16 connecting the multiplexer 13 and the binding terminal 151. In the embodiment, the multiplexer area 14 is provided with the multiplexer 13. In the embodiment, the multiplexer 13 is concentratedly arranged in the lower frame area and away from the R corner area by the auxiliary wire 12.

[0057] Optionally, in the first display area AA1, the second auxiliary wires 122 along the virtual extension line of the second direction Y can have an overlapping area with the second multiplexers 132 to which the second auxiliary wires 122 are connected. Referring to FIG. 4, the second auxiliary wires 122 connected to the second multiplexers 132 are all arranged in the first display area AA1. In this embodiment, the positions of the second multiplexers 132 can be controlled so that the second auxiliary wires 122 along the virtual extension line of the second direction Y can have an overlapping area with the second multiplexers 132 to which the second auxiliary wires 122 are connected, and then the second multiplexers 132 are connected to the second data lines 112 in proximity, the second connection leads 162 have a relatively short length, the second data lines 112 are directly connected to the corresponding second switching elements T2, the resistance of the transmission path of the second data lines 112 is reduced, the signal transmission loss is reduced, the circuit complexity of the fan-out area is further reduced by the shorter second connection leads 162, the circuit layout space of the fan-out area is reasonably utilized by adjusting the positions of the second multiplexers 132, and the width of the lower bezel is further reduced. Similarly, in the first display area AA1, the first data lines 111 along the virtual extension line of the second direction Y can have an overlapping area with the first multiplexers 131 to which the first data lines 111 are connected, the first multiplexers 131 are connected to the first data lines 111 in proximity, the first connection leads 161 have a relatively short length, the resistance of the transmission path of the first data lines 111 is reduced, the circuit complexity of the fan-out area is further reduced, and this is conducive to the design of a narrow bezel.

[0058] With continuous reference to FIG. 4, optionally, the non-display area NA can include a multiplexer area 14, the multiplexer area 14 is provided with multiplexers 13, and the second data lines 112 along the virtual extension line of the second direction Y do not overlap the multiplexer area 14. The second data lines 112 are arranged in the second display area AA2, and in this embodiment, the starting position of the multiplexer area 14 along the first direction X can be aligned with or only have a small distance from the starting position of the first data lines 111. Then, the multiplexer area 14 is arranged in the lower bezel area corresponding to the first display area AA1, and does not overlap the second data lines 112 along the virtual extension line of the second direction Y. In this embodiment, the multiplexer area 14 is close to the first display area AA1, and then the multiplexers 13 can be connected to the second auxiliary wires 122 or the first data lines 111 in the first display area AA1 in proximity, the area of the fan-out area occupied by the connection leads is further reduced, and thus the narrow bezel design of the display panel is realized.

[0059] In this embodiment, in order to reduce the arrangement of the connection leads as much as possible, a plurality of rows of switching elements T extending along the first direction X and arranged along the second direction Y can be formed in the fan-out area. Then, each row of switching elements T can be connected to the corresponding second auxiliary wires 122 or first data lines 111 in proximity, the width of the lower bezel occupied by the connection leads is reduced, and the narrow bezel design of the display panel is realized. In this embodiment, the switching elements T can be divided into a plurality of rows according to different principles.

[0060] The first one is shown in FIG. 5, which is a schematic diagram of a film layer structure of the multiplexer of the display panel of FIG. 4. FIG. 6 is another schematic diagram of a film layer structure of the multiplexer of the display panel of FIG. 4. As shown in FIGS. 4-6, the first multiplexer 131 can include N first switching elements T1 arranged in the first direction X in sequence. The second multiplexer 132 can include N second switching elements T2 arranged in the first direction X in sequence. The switching element T includes an active layer 21. The active layer 21 of the switching element T of the first multiplexer 131 is located on the side of the active layer 21 of the switching element T of the second multiplexer 132 away from the display area AA. In the first direction X, the i-th first switching element T1 of the first multiplexer 131 shares a gate 22 with the i-th second switching element T2 of the second multiplexer 132. 1≤i≤N. i is a positive integer.

[0061] In this embodiment, the second multiplexer 132 is arranged between the first multiplexer 131 and the first display area AA1, thereby reducing the length of the second connection lead 162. Because the signal transmission path of the second data line 112 has the auxiliary trace 12 added thereto, the signal loss degree of the signal transmission path of the second data line 112 is greater than that of the signal transmission path of the first data line 111, and the length of the second connection lead 162 in the signal transmission path of the second data line 112 is reduced, as shown in FIG. 5. The second data line 112 is connected to the second switching element T2 through the shorter second connection lead 162, thereby effectively reducing the length of the signal transmission path of the second data line 112. In this embodiment, the signal loss degree of the signal transmission path of the second data line 112 is equivalent to that of the signal transmission path of the first data line 111, thereby improving the picture display uniformity of the display panel. Optionally, the side of the second multiplexer 132 close to the display area is provided with a bus vref2 of a second reference voltage signal. The second reference voltage signal is a signal for providing a reset signal to the anode of the pixel driving circuit. The bus vref2 of the second reference voltage signal extending in the first direction X can effectively reduce the voltage drop of the second reference voltage in the transmission process.

[0062] The display panel can be sequentially provided with a substrate and a driving circuit layer in a direction perpendicular to the thickness of the film layer. The switching element T is provided on the driving circuit layer, and the switching element T can be sequentially provided with an active layer 21, a gate 22 (control end) and a source-drain electrode (first end 231 and second end 232) in a direction away from the substrate. The film layer of FIG. 6 omits the structure of the source-drain electrode metal layer with respect to the film layer of FIG. 5, so as to facilitate understanding of the structure of the active layer 21 and the gate 22. In the embodiment, the plurality of distributors 13 are divided into two rows, the second plurality of distributors 132 are arranged close to the display area AA, and the first plurality of distributors 131 are arranged away from the display area AA. The first plurality of distributors 131 include N first switching elements T1 arranged in the first direction X in sequence, and the second plurality of distributors 132 include N second switching elements T2 arranged in the first direction X in sequence. In the first direction X, the first end 231 of two adjacent switching elements T can be shared. In the embodiment, the active layer 21 of the second switching element T2 is arranged on the side of the active layer 21 of the first switching element T1 close to the first display area AA1. Because the number of the first switching elements T1 is equal to the number of the second switching elements T2, and N switching elements T in each plurality of distributors 13 are respectively connected to the corresponding control signal lines. In the embodiment, the i-th first switching element T1 of the first plurality of distributors 131 and the i-th second switching element T2 of the second plurality of distributors 132 can share the gate 22, and are connected to the corresponding control signal line through the shared gate 22, so that the gate 22 can be a strip extending in the second direction Y, reducing the circuit complexity of the plurality of distributors 13, and improving the manufacturing efficiency and reliability of the display panel. In the embodiment, because the second plurality of distributors 132 are arranged close to the display area AA, the second end 232 of the second switching element T2 is connected to the second auxiliary wire 122, and the first end 231 of the second switching element T2 is connected to the fan-out wire 16. The second end 232 of the first switching element T1 is connected to the first data line through the connection lead (not shown in FIG. 5) of other film layers, and the first end 231 of the second switching element T2 is connected to the fan-out wire 16.

[0063] Optionally, FIG. 7 is a schematic diagram of a film layer structure of a multiplexer of a display panel according to an embodiment of the present application, and FIG. 8 is a schematic diagram of another film layer structure of a multiplexer of a display panel according to an embodiment of the present application. Optionally, the multiplexer 13 can include a first element group 133 and a second element group 134. The first element group 133 and the second element group 134 each include a plurality of switching elements T arranged in sequence along a first direction X. The switching element T includes an active layer 21. The active layer 21 of the switching element T of the second element group 134 is located on a side of the active layer 21 of the switching element T of the first element group 133 away from a display area AA. Along the first direction X, a p th switching element T of the first element group 133 shares a first terminal with an e th switching element T of the second element group 134. 1≤p≤N; 1≤e≤N; p and e are positive integers.

[0064] At this time, along the first direction X, each multiplexer 13 is divided into two rows. Whether it is the first multiplexer 131 or the second multiplexer 132, it can include the first element group 133 and the second element group 134. In the same multiplexer 13, the number of switching elements T in the first element group 133 can be N1, and the number of switching elements T in the second element group 134 can be N2, and the sum of N1 and N2 is N. The first element group 133 and the second element group 134 each include a plurality of switching elements T arranged in sequence along the first direction X. The first element group 133 is arranged on a side of the second element group 134 close to the display area AA. As shown in FIG. 7, the switching element T can be sequentially provided with the active layer 21, the gate 22 (control terminal), and the source-drain electrode (the first terminal 231 and the second terminal 232) in a direction away from the substrate. FIG. 8 omits the source-drain electrode film layer relative to FIG. 7, so as to facilitate understanding of the structure of the active layer 21 and the gate 22. The active layer 21 of the switching element T of the first element group 133 is located on a side of the active layer 21 of the switching element T of the second element group 134 close to the display area AA. The first element group 133 of each multiplexer 13 is arranged in a row close to the display area AA, and the second element group 134 of each multiplexer 13 is arranged in a row away from the display area AA. Referring to FIG. 7, the p th switching element T of the first element group 133 shares the first terminal 231 with the e th switching element T of the second element group 134, and is connected to the fan-out wire 16 through the shared first terminal 231. In this embodiment, the first terminal 231 can be a strip extending along the second direction Y, which reduces the circuit complexity of the multiplexer 13 and improves the manufacturing efficiency and reliability of the display panel. Optionally, N1 can be equal to N2, and the p th switching element T of the first element group 133 can share the first terminal 231 with the p th switching element T of the second element group 134. Then, all the first terminals 231 form a strip extending along the second direction Y, so as to further reduce the circuit complexity of the multiplexer 13 and improve the manufacturing efficiency of the display panel.

[0065] With reference to FIG. 7, alternatively, the first multiplexers 131 and the second multiplexers 132 can be arranged alternately along the first direction X. Since each multiplexer 13 is arranged in two rows along the second direction Y, and the first data lines and the second auxiliary lines in the first display area AA1 are arranged alternately, the first multiplexers 131 and the second multiplexers 132 can be arranged alternately along the first direction X in the embodiment, so that the multiplexers 13 can be connected to the corresponding second auxiliary lines 122 or the first data lines 111 in the first display area AA1 in proximity, further reducing the area of the fan-out area occupied by the connection leads, so as to realize the narrow frame design of the display panel. In addition, the arrangement principle of arranging the multiplexers 13 in proximity reduces the resistance of the transmission path of the first data lines 111 and the resistance of the transmission path of the second data lines 112, thereby reducing the loss of the signal in the transmission process and improving the accuracy of the signal provided by the data lines to the pixel driving circuit.

[0066] In the embodiment, the display panel can adopt a low temperature poly-silicon (LTPS) technology, so that the display panel can be made thinner, smaller and lower in power consumption. In addition, the display panel can also adopt a low temperature polycrystalline oxide (LTPO) technology, which combines the LTPS technology and an indium gallium zinc oxide (IGZO) technology, has a higher mobility and a lower leakage current, thereby realizing lower power consumption and more excellent display effect. The embodiment takes the LTPO display panel as an example to illustrate the film layers of the display panel. As shown in FIG. 9 and FIG. 10, FIG. 9 is a schematic diagram of a cross-sectional structure of a display panel according to an embodiment of the present application, and FIG. 10 is a schematic diagram of a cross-sectional structure of another display panel according to an embodiment of the present application. Alternatively, the switching element T can include a double-gate structure; the double-gate structure can include a first gate structure 221 and a second gate structure 222; the first gate structure 221 and the second gate structure 222 are arranged on different film layers.

[0067] FIG. 9 shows a partial structure of an LTPS display panel, and FIG. 10 shows a partial structure of an LTPO display panel. In either panel, a double-gate structure can be provided in the present embodiment. That is, a gate structure is provided in each film layer, and the gate structures in different film layers are connected to the same control signal. Referring to FIGS. 9 and 10, the double-gate structure can include a first gate structure 221 and a second gate structure 222, which are provided in different metal layers, respectively. The provision of the first gate structure 221 and the second gate structure 222 can effectively increase the transmission efficiency of the control signal and accelerate the on and off speed of the gate of the switching element T. In addition, the gate structures in different film layers can be electrically connected to each other, so as to further reduce the resistance of the gate structure, reduce the loss of the control signal on the gate structure, and improve the control accuracy of the switching element T.

[0068] With continued reference to FIG. 9, the display panel can include at least: a substrate 41; a shielding metal layer 40 located on the substrate 41; the shielding metal layer 40 includes the first gate structure 221 of the switching element T; a first active layer 43 located on a side of the shielding metal layer 40 away from the substrate 11; the first active layer 43 includes the active layer 21 of the switching element T; a first gate layer 44 provided on a side of the first active layer 43 away from the substrate 11; the first gate layer 44 includes the second gate structure 222 of the switching element T; an intermediate metal layer 45 provided on a side of the first gate layer 44 away from the substrate 11; a source-drain layer 46 provided on a side of the intermediate metal layer 45 away from the substrate 11; the source-drain layer 46 includes the first end 231 and the second end 232 of the switching element T.

[0069] The display panel generally comprises a substrate 11, and a driving circuit layer and a light emitting element layer arranged on one side of the substrate 11 in sequence. The driving circuit layer is provided with a plurality of pixel driving circuits, and the light emitting element layer is provided with an array of light emitting elements, and the pixel driving circuit can provide working current for the corresponding light emitting element. As shown in FIG. 9, only the structure of the driving circuit layer is shown in FIG. 9, and the light emitting element layer is not shown. It can be understood that the pixel driving circuit is electrically connected with the corresponding light emitting element to provide working current for the light emitting element. When the process of the display panel is LTPS, the display panel can comprise a substrate 41 and a shielding metal layer 40, a first active layer 43, a first gate layer 44, an intermediate metal layer 45 and a source-drain layer 46 arranged on the substrate 41 in sequence. The substrate 41 can comprise a multi-layer stacked structure, for example, comprising polyethylene terephthalate, polyether ether ketone, polystyrene and the like. The shielding metal layer 40 is arranged on the substrate 41, and it should be noted that “on the substrate” in the embodiment represents a positional relationship, and the shielding metal layer 40 is arranged on the side of the substrate 11 close to the light emitting element. Optionally, other film layers such as inorganic insulating layers can be arranged between the shielding metal layer 40 and the substrate 41. The shielding metal layer 40 comprises a first gate structure 221 of a switching element T, the first active layer 43 comprises an active layer 21 of the switching element T, and a buffer layer 42 can be arranged between the shielding metal layer 40 and the first active layer 43. The first gate layer 44 comprises a second gate structure 222 of the switching element T, the intermediate metal layer 45 is generally arranged as a capacitor plate, and the source-drain layer 46 comprises a first end 231 and a second end 232 of the switching element T. In the embodiment, the first gate structure 221 and the second gate structure 222 simultaneously provide control signals for the switching element T, thereby improving the control accuracy of the switching element T.

[0070] With reference to FIG. 9, the shielding metal layer 40 can further comprise a shielding portion 401 of the display area AA; the shielding portion 401 at least partially overlaps the driving transistor T3 of the display area AA; the shielding portion 401 is connected to a preset potential; and the preset potential is a first power signal, a second power signal or a reference voltage signal.

[0071] The driving transistor T3 in the display area AA of the display panel and the switching element T can be formed by the same process. The gate of the driving transistor T3 is arranged on the first gate layer 44, the active layer of the driving transistor T3 is arranged on the first active layer 43, and the source and the drain of the driving transistor T3 are arranged on the source-drain layer 46. In addition, the first plate of the capacitor in the pixel driving circuit is arranged on the first gate layer 44, and the second plate is arranged on the intermediate metal layer 45. It should be noted that the display area AA is provided with a shielding portion 401 arranged in the same layer as the first gate structure 221 and arranged on the shielding metal layer 40. In the plane parallel to the substrate, the shielding portion 401 and the driving transistor T3 at least partially overlap in the embodiment, the shielding portion 401 is connected to a preset potential with a fixed value, which is used to keep the potential of the driving transistor T3 stable when it is turned on and turned off, improve the accuracy of the output current of the pixel driving circuit, and thus improve the display effect of the display panel. In addition, because the first power signal PVDD, the second power signal PVEE or the reference voltage signal VREF and other fixed potentials are required during the working process of the pixel driving circuit, the above-mentioned any signal can be multiplexed as the preset potential in the embodiment, without the need to additionally add a signal terminal, which reduces the complexity of the pixel driving circuit and effectively saves the working energy consumption of the display panel.

[0072] FIG. 11 is a schematic diagram of a cross-sectional structure of another display panel provided by an embodiment of the present application. Referring to FIGS. 10 and 11, the display panel can at least include: a substrate 41; and a first active layer 43, a first gate layer 44, an intermediate metal layer 45, a second active layer 47, a second gate layer 48 and a source-drain layer 46 arranged on the substrate 41 in sequence; the active layer 21 of the switching element T is located on the first active layer 43 and / or the second active layer 47; as shown in FIG. 11, the first gate structure 221 of the switching element T is located on the first gate layer 44; the second gate structure 222 of the switching element T is located on the second gate layer 48; or, as shown in FIG. 10, the first gate structure 221 of the switching element T is located on the intermediate metal layer 45; and the second gate structure of the switching element T is located on the second gate layer 48.

[0073] The specific film layers of the driving transistor T3 in the display area are also shown in FIG. 11. The gate of the driving transistor T3 is provided in the first gate layer 44, the active layer of the driving transistor T3 is provided in the first active layer 43, and the source and the drain of the driving transistor T3 are provided in the source-drain layer 46. The display area can also include other transistors, the gate of the other transistors can be provided in the second gate layer 48, the active layer is provided in the second active layer 47, and the source and the drain of the driving transistor T3 are provided in the source-drain layer 46. If the first active layer 43 includes a low-temperature polysilicon material and the second active layer 47 includes an oxide semiconductor (which can be indium gallium zinc oxide), the display panel in this embodiment is an LTPO display panel. For the LTPO display panel, the active layer 22 of the switching element T can be provided in the first active layer 43 or the second active layer 47. Optionally, in this embodiment, part of the active layer 22 of the switching element T is provided in the first active layer 43, and part of the active layer 22 of the switching element T is provided in the second active layer 47. This embodiment is described by taking the active layer 22 of the switching element T provided in the second active layer 47 as an example. When the active layer 22 of the switching element T is provided in the second active layer 47, the second gate structure 222 of the switching element T in the double-gate structure is located in the second gate layer 48, and the first gate structure 221 of the switching element T can be provided in the first gate layer 44 or the intermediate metal layer 45. In this embodiment, the first gate structure 221 and the second gate structure 222 simultaneously provide control signals for the switching element T, reduce the voltage drop of the control signals on the gate structure, and improve the control accuracy of the switching element T.

[0074] In addition, in another example of this embodiment, the first active layer 43 and the second active layer 47 can both include an oxide semiconductor. Then the driving transistor T3 and the switching element T form a laminated thin film transistor. Optionally, in the first active layer 43 and the second active layer 47, the components of the oxide semiconductor are different, or the proportions of the components are different. For example, the first active layer 43 includes indium, gallium, zinc, tin, and oxygen elements, and the second active layer 47 only includes indium, gallium, zinc, and oxygen elements. For another example, the components of the first active layer 43 and the second active layer 47 both include indium, gallium, zinc, tin, and oxygen elements, but the content ratio of gallium to indium in the second active layer 47 is higher than that in the first active layer 43, and the content ratio of zinc to indium in the second active layer 47 is higher than that in the first active layer 43. In this embodiment, the material composition or the material ratio of the first active layer 43 and the second active layer 47 is adjusted differently, so that the driving transistor T3 and the switching element T have different conduction performances.

[0075] With reference back to FIG. 2, optionally, the display area AA can include a plurality of pixel driving circuit columns 31 extending along the second direction Y and arranged along the first direction X; each column of pixel driving circuit 31 is electrically connected with one data line 11. In the embodiment, each column of pixel driving circuit 31 is electrically connected with one data line 11 arranged along the second direction Y, and the embodiment forms a single data line (Single Data Line, DDL) layout. As shown in FIG. 2, optionally, in the first display area AA1, a second auxiliary wire 122 can be included between adjacent first data lines 111. Then along the first direction X, the number of first data lines 111 and the number of second auxiliary wires 122 in the first display area AA1 are substantially the same, so that the number ratio of the first multiplexer 131 and the second multiplexer 132 tends to 1:1, which facilitates the first multiplexer 131 to be connected to the first data line 111 in proximity, and facilitates the second multiplexer 132 to be connected to the second auxiliary wire 122 in proximity, reduces the setting length of the first connection lead 161 and the second connection lead 162, is conducive to reducing the width of the fan-out area, and realizes the narrow frame design of the lower frame of the display panel. In addition, the principle of proximity setting is conducive to making the multiplexer 13 closer to the first display area AA1, and the T corner area 17 is no longer provided with the multiplexer and the fan-out wire, which is conducive to realizing the narrow frame design of the R corner area. It should be noted that in order to make the auxiliary wire 12 evenly arranged on the display panel and improve the display uniformity of the panel, in the second display area AA2, a second auxiliary wire 122 can be included between adjacent second data lines 112.

[0076] Fig. 12 is a schematic structural view of a partial display panel provided by an embodiment of the present application. Optionally, in the first display area AA1, two first data lines 111 can be included between two adjacent second auxiliary wires 122. For the LTPO display panel, the layout of the two adjacent pixel driving circuits 31 can be symmetrically arranged. As shown in Fig. 12, in the first display area AA1, along the first direction X, there are two cases: one is that no auxiliary wire 12 and data line 11 are arranged between the two adjacent pixel driving circuits 31, and the other is that two first data lines 111 are arranged between the two adjacent pixel driving circuits 31. At this time, if one second auxiliary wire 122 is arranged corresponding to each column of pixel driving circuits 31, the second auxiliary wire 122 can be arranged outside the two first data lines 111, thereby forming a structure in which two first data lines 111 can be included between two adjacent second auxiliary wires 122. As can be seen from Fig. 12, in the first display area AA1, the number ratio of the second auxiliary wire 122 to the first data line 111 is 1:1, which is convenient for the first multiplexer 131 to connect the first data line 111 nearby and for the second multiplexer 132 to connect the second auxiliary wire 122 nearby, thereby reducing the setting length of the first connection lead 161 and the second connection lead 162, which is conducive to reducing the width of the fan-out area and realizing the narrow-frame design of the lower frame of the display panel. Similarly, in order to make the auxiliary wire 12 evenly arranged on the display panel, in the second display area AA2, two first data lines 111 can be included between two adjacent second auxiliary wires 122.

[0077] Fig. 13 is a schematic structural view of a partial display panel provided by an embodiment of the present application. Optionally, when the layout of the two adjacent pixel driving circuits 31 can be symmetrically arranged, in the first display area AA1, two second auxiliary wires 122 can be included between two adjacent first data lines 111, which can also make the first multiplexer 131 connect the first data line 111 nearby and make the second multiplexer 132 connect the second auxiliary wire 122 nearby. In addition, in the second display area AA2, two second auxiliary wires 122 can be included between two adjacent first data lines 111.

[0078] Fig. 14 is a schematic view of a partial structure of another display panel provided by the embodiment of the present application. Optionally, when the layout of the two adjacent pixel driving circuits 31 can be symmetrically arranged, in the first display area AA1, a second auxiliary trace 122 can be included between the adjacent first data lines 111. Then the longitudinal wiring density in the first display area AA1 along the second direction Y is smaller, so as to reduce the signal interference between the parallel first data lines 111 and the second auxiliary trace 122, and when the longitudinal wiring density is smaller, the process difficulty of the driving circuit layer is effectively reduced, and the yield of the display panel is improved. In addition, in the second display area AA2, a second auxiliary trace 122 can be included between the adjacent first data lines 111, so that the layout of the second auxiliary trace 122 on the whole display panel is uniform.

[0079] Fig. 15 is a schematic view of a partial enlarged view of the S1 area in the display panel in Fig. 12. Referring to Figs. 12 and 15, optionally, the display area can further include: arrayed sub-pixels (not shown in Fig. 14); the plurality of pixel driving circuit columns 31 include first pixel driving circuit columns 32 and second pixel driving circuit columns 33 arranged alternately; the first pixel driving circuit columns 32 include first pixel driving circuits 311 and second pixel driving circuits 312 arranged alternately along the second direction Y; the second pixel driving circuit columns 33 include third pixel driving circuits 313; the first pixel driving circuits 311 are electrically connected with first color sub-pixels; the second pixel driving circuits 312 are electrically connected with second color sub-pixels; the third pixel driving circuits 313 are electrically connected with third color sub-pixels; along the first direction X, the qth second auxiliary trace 122 is electrically connected with the first pixel driving circuit columns 32; the q+1th second auxiliary trace 122 is electrically connected with the second pixel driving circuit columns 33; 1≤q

[0080] As shown in FIG. 15, the display panel includes a plurality of pixel driving circuits 31 arranged in an array, and different pixel driving circuits 31 drive different color sub-pixels (light emitting elements). Optionally, the sub-pixels in the embodiment can include first color sub-pixels capable of emitting first color light, second color sub-pixels capable of emitting second color light, and third color sub-pixels capable of emitting third color light. For example, the first color sub-pixels can be red sub-pixels, the second color sub-pixels can be blue sub-pixels, and the third color sub-pixels can be green sub-pixels. The embodiment can refer to the pixel driving circuit driving the first color sub-pixel to emit light as a first pixel driving circuit 311, refer to the pixel driving circuit driving the second color sub-pixel to emit light as a second pixel driving circuit 312, and refer to the pixel driving circuit driving the third color sub-pixel to emit light as a third pixel driving circuit 313. Along the first direction X, the first pixel driving circuit column 32 and the second pixel driving circuit column 33 are arranged alternately, wherein the first pixel driving circuit column 32 includes the first pixel driving circuit 311 and the second pixel driving circuit 312 arranged alternately along the second direction Y, and the second pixel driving circuit column 33 is provided with only the third pixel driving circuit 313. In order to facilitate understanding of the specific positions of different pixel driving circuits, the embodiment represents the first pixel driving circuit 311, the second pixel driving circuit 312, and the third pixel driving circuit 313 by different fill patterns. As shown in FIG. 12, in the first display area AA1, along the first direction X, in the adjacent N second auxiliary wires 122, the qth second auxiliary wire 122 is electrically connected with the first pixel driving circuit column 32, and the q+1th second auxiliary wire 122 is electrically connected with the second pixel driving circuit column 33, that is, every two adjacent second auxiliary wires 122 are provided with one pixel driving circuit 31 connected with the first pixel driving circuit column 32 and another pixel driving circuit 31 connected with the second pixel driving circuit column 33. Then, along the first direction X, the arrangement sequence of the second data line 112 is the same as the arrangement sequence of the second auxiliary wire 122 connected therewith, facilitating the wiring of the second auxiliary wire 122, avoiding the interlacing of the auxiliary wires 12, reducing the complexity of the auxiliary wires 12, and maintaining the same connection sequence of the switch elements T of all the multiplexers and the control signal lines. For example, as shown in FIG. 2, along the first direction X, the connection sequence of the switch elements T of each multiplexer 13 and the control signal lines is MUX1, MUX2 in turn, facilitating the wiring of the gate of the switch element T.

[0081] Fig. 16 is a schematic view of a partial structure of another display panel provided by the embodiment of the present application. Optionally, the display area AA can further include a first power signal line VDD extending along the second direction Y and arranged along the first direction X; a first gap region S2 is included between adjacent first data lines 111; the first gap region S2 is provided with a second auxiliary trace 122 and a first power signal line VDD; and the second auxiliary trace 122 and the first power signal line VDD are symmetrically arranged about the first gap region S2.

[0082] Referring to Fig. 16, for the case that each column of pixel driving circuits is electrically connected to a data line, if the two adjacent columns of pixel driving circuits 31 of the display panel of the embodiment can be symmetrically arranged, then a first gap region S2 is included between adjacent first data lines 111, and the first gap region S2 is provided with a second auxiliary trace 122 and a first power signal line VDD; and the second auxiliary trace 122 and the first power signal line VDD are symmetrically arranged about the first gap region S2 along the central axis φ of the first gap region S2 extending along the second direction Y. The first power signal line VDD can reduce the capacitance between the second auxiliary trace 122 and the first data line 111 to some extent, and can maintain the voltage on the second auxiliary trace 122 and the first data line 111, thereby reducing the voltage drop (IR drop) of the second auxiliary trace 122 and the first data line 111 with the increase of length.

[0083] Fig. 17 is a schematic view of a partial structure of another display panel provided by the embodiment of the present application. Optionally, the data line can include a third data line 113 and a fourth data line 114; the display area AA includes a plurality of columns of pixel driving circuits 31 extending along the second direction Y and arranged along the first direction X; the pixel driving circuits 31 of the odd rows of each column of pixel driving circuits 31 are electrically connected to the third data line 113; the pixel driving circuits 31 of the even rows of each column of pixel driving circuits 31 are electrically connected to the fourth data line 114; and the third data line 113 and the fourth data line 114 are respectively arranged on opposite sides of a column of pixel driving circuits 31.

[0084] In the embodiment, each column of pixel driving circuit 31 is provided with two data lines: third data line 113 and fourth data line 114. In the embodiment, whether it is the first display area AA1 or the second display area AA2, the pixel driving circuit column therein is provided with third data line 113 and fourth data line 114, then the first data line 111 includes third data line 113 and fourth data line 114, and the second data line 112 includes third data line 113 and fourth data line 114. Along the second direction Y, the pixel driving circuit 31 of the odd rows of each column of pixel driving circuit 31 is connected with third data line 113, and the pixel driving circuit 31 of the even rows of each column of pixel driving circuit 31 is connected with fourth data line 114. In the embodiment, in order to reduce the cost, the Double Data Line (DDL) technology is added to the display panel process, so as to realize the frequency conversion technology of the display panel by lower cost. And the embodiment can realize the halving of the number of data signals provided by the driving chip of the display panel through the 1:4 multiplexer, and further reduce the width of the R corner area and the lower frame in combination with the FIAA technology. In summary, the embodiment combines the DDL technology and the FIAA technology and applies them in the LTPO panel, thereby realizing low-cost frequency conversion and further reducing the frame width of the display panel.

[0085] With reference to FIG. 17, optionally, in the first display area AA1, the second gap area S3 can be included between the third data line 113 and the fourth data line 114; the second gap area S3 is provided with a second auxiliary trace 122. In the embodiment, the third data line 113 and the fourth data line 114 can be provided with only one second auxiliary trace 122, and then each column of pixel driving circuit 31 is correspondingly inserted with one second auxiliary trace 122. In the embodiment, the display area AA is provided with a second auxiliary trace 122 with a small setting density, thereby reducing the signal interference between the parallel first data line 111 and the second auxiliary trace 122.

[0086] FIG. 18 is a schematic view of a partial structure of another display panel provided by an embodiment of the present application. Optionally, in the first display area AA1, a second auxiliary trace 122 can be arranged between the adjacent third data line 113 and the fourth data line 114. In a direction perpendicular to the display panel, the second auxiliary trace 122 at least partially overlaps the third data line 113, or the second auxiliary trace 122 at least partially overlaps the fourth data line 114. In this embodiment, if the data line 11 and the second auxiliary trace 122 are arranged in the same layer, the second auxiliary trace 122 can be arranged in the second gap region S3 between the adjacent third data line 113 and the fourth data line 114. If the data line 11 and the second auxiliary trace 122 are arranged in different layers, in a plane parallel to the substrate, the second auxiliary trace 122 can overlap the third data line 113 or the fourth data line 114. In FIG. 18, the second auxiliary trace 122 is taken as an example to overlap the third data line 113, and the case where the second auxiliary trace 122 overlaps the third data line 113 is shown in FIG. 18. In this embodiment, the overlapping region is arranged between the second auxiliary trace 122 and the data line 11, so as to save the layout space in a plane parallel to the substrate, avoid the problem that the driving circuit layer layout is limited due to the large number of longitudinal wires extending along the second direction Y, and reduce the complexity of the driving circuit layer.

[0087] FIG. 19 is a schematic view of a partial structure of another display panel provided by an embodiment of the present application. Optionally, in the first display area AA1, the second gap region S3 can be arranged between the adjacent third data line 113 and the fourth data line 114. The second gap region S3 is provided with two second auxiliary traces 122. In this embodiment, the second gap region S3 between the third data line 113 and the fourth data line 114 is provided with two second auxiliary traces 122, and two second auxiliary traces 122 are inserted for each column of pixel driving circuit 31. In the first display area AA1, the number of second auxiliary traces 122 is the same as the number of first data lines, so the number of first multiplexers 131 and the number of second multiplexers 132 are the same, and the first multiplexers 131 and the second multiplexers 132 can be centrally arranged in the lower frame of the first display area AA1, so as to reduce the width of the R-angle region. The first multiplexers 131 are connected to the corresponding data lines in proximity, and the second multiplexers 132 are connected to the corresponding second auxiliary traces 122 in proximity, so as to reduce the space of the fan-out region and realize the narrow-frame design of the lower frame.

[0088] Figure 20 is a schematic view of a partial structure of another display panel provided by an embodiment of the present application. Optionally, in the first display area AA1, two second auxiliary wires 122 can be arranged between the adjacent third data line 113 and the fourth data line 114. In the direction perpendicular to the display panel, one of the second auxiliary wires 122 at least partially overlaps the third data line 113, and the other of the second auxiliary wires 122 at least partially overlaps the fourth data line 114. In this embodiment, when two second auxiliary wires 122 are inserted between the adjacent third data line 113 and the fourth data line 114, in the plane parallel to the substrate, there is an overlapping area between one of the second auxiliary wires 122 and the third data line 113, and there is an overlapping area between the other of the second auxiliary wires 122 and the fourth data line 114. Optionally, as shown in Figure 20, the third data line 113 and one of the second auxiliary wires 122 coincide, and the fourth data line 114 and the other of the second auxiliary wires 122 coincide. This embodiment can save the layout space of the display panel in the plane parallel to the substrate, avoid the problem that the driving circuit layer layout is limited due to the large number of longitudinal wires extending along the second direction Y, and reduce the complexity of the driving circuit layer. It should be noted that because the second auxiliary wires 122 in Figure 20 substantially coincide with the data lines, this embodiment needs to emphasize that the first auxiliary wire 121 is electrically connected to the third data line 113 or the fourth data line 114 in the second display area AA2, and the first auxiliary wire 121 is electrically connected to the second auxiliary wire 122 in the first display area AA1.

[0089] With continued reference to Figure 19, optionally, the display area can further include: an array of sub-pixels (not shown in Figure 19); the plurality of columns of pixel driving circuits 31 include first pixel driving circuit columns 32 and second pixel driving circuit columns 33 arranged alternately; the first pixel driving circuit columns 32 include first pixel driving circuits 311 and second pixel driving circuits 312 arranged alternately along the second direction Y; the second pixel driving circuit columns 33 include third pixel driving circuits 313; the first pixel driving circuits 311 are electrically connected to first color sub-pixels; the second pixel driving circuits 312 are electrically connected to second color sub-pixels; the third pixel driving circuits 313 are electrically connected to third color sub-pixels; along the first direction X, the hth second auxiliary wire 122 is electrically connected to the first pixel driving circuits 311 of the first pixel driving circuit columns 32; the h+1th second auxiliary wire 122 is electrically connected to the second pixel driving circuits 312 of the first pixel driving circuit columns 32; the h+2th second auxiliary wire 122 is electrically connected to the odd-numbered rows of third pixel driving circuits 313 of the second pixel driving circuit columns 33; the h+3th second auxiliary wire 122 is electrically connected to the even-numbered rows of third pixel driving circuits 313 of the second pixel driving circuit columns 33; 1≤h≤N-3; h is a positive integer.

[0090] As shown in FIG. 19, the display panel includes a plurality of pixel driving circuits 31 arranged in an array, and different pixel driving circuits 31 drive different color sub-pixels (light emitting elements). Optionally, the sub-pixels in the embodiment can include first color sub-pixels, second color sub-pixels and third color sub-pixels. For example, the first color sub-pixels can be red sub-pixels, the second color sub-pixels can be blue sub-pixels, and the third color sub-pixels can be green sub-pixels. In the embodiment, the pixel driving circuit driving the first color sub-pixel to emit light can be referred to as a first pixel driving circuit 311, the pixel driving circuit driving the second color sub-pixel to emit light can be referred to as a second pixel driving circuit 312, and the pixel driving circuit driving the third color sub-pixel to emit light can be referred to as a third pixel driving circuit 313. Along the first direction X, the first pixel driving circuit column 32 and the second pixel driving circuit column 33 are arranged alternately, wherein the first pixel driving circuit column 32 includes the first pixel driving circuit 311 and the second pixel driving circuit 312 arranged alternately along the second direction Y, for example, the first pixel driving circuit 311 can be arranged in the odd rows, the second pixel driving circuit 312 can be arranged in the even rows, and the second pixel driving circuit column 33 is provided with only the third pixel driving circuit 313. In order to facilitate understanding of the specific positions of different pixel driving circuits, different filling patterns are used to represent the first pixel driving circuit 311, the second pixel driving circuit 312 and the third pixel driving circuit 313 in the embodiment. As shown in FIG. 19, in the first display area AA1, along the first direction X, in the adjacent N second auxiliary wires 122, the hth second auxiliary wire 122 is electrically connected with the first pixel driving circuit 311 of the first pixel driving circuit column 32, the h+1th second auxiliary wire 122 is electrically connected with the second pixel driving circuit 312 of the first pixel driving circuit column 32, the h+2th second auxiliary wire 122 is electrically connected with the odd row third pixel driving circuit 313 of the second pixel driving circuit column 33, and the h+3th second auxiliary wire 122 is electrically connected with the even row third pixel driving circuit 313 of the second pixel driving circuit column 33. That is, there is one first pixel driving circuit 311, one second pixel driving circuit 312 and two third pixel driving circuits 313 connected with every four adjacent second auxiliary wires 122. Then, along the first direction X, the arrangement sequence of the second data line 112 is the same as the arrangement sequence of the second auxiliary wire 122 connected therewith, which facilitates the wiring of the second auxiliary wire 122, avoids the interlacing of the auxiliary wires 12, and reduces the complexity of the auxiliary wires 12. In the embodiment, two data lines are used to charge a column of pixel driving circuits, and thus one data line only needs to charge half of the pixel driving circuits in a column of pixel driving circuits, which improves the charging effect of the pixel driving circuits and improves the display effect of the entire display panel.Optionally, referring to FIG. 19, in the display area, the third data line 113 and the second auxiliary wire 122, to which the outputs of the switches controlled by mux4 in the first multiplexer 131 and the second multiplexer 132 are connected, can be arranged adjacent to each other, so that the switches corresponding to the adjacent signal lines are opened at the same time, and the coupling jump between the adjacent signal lines is reduced. Optionally, the colors of the light emitting elements corresponding to the pixel driving circuits connected to the third data line 113 and the colors of the light emitting elements corresponding to the pixel driving circuits connected to the second auxiliary wire 122 can be the same, so that the signal crosstalk between the adjacent wires is reduced.

[0091] In addition, in the embodiment, the connection relationship between the multiplexer and the control signal line is controlled to implement the effective frequency conversion technology. FIG. 21 is a timing diagram of the control signal line provided in the embodiment. The control signal line includes a first control signal line MUX1, a second control signal line MUX2, a third control signal line MUX3, and a fourth control signal line MUX4. When the switch elements of the multiplexer are driven, the first control signal line MUX1, the second control signal line MUX2, the third control signal line MUX3, and the fourth control signal line MUX4 output effective pulses in sequence. For example, as shown in FIG. 19, the first control signal line MUX1 can control the fan-out wire 16 to transmit a signal to the first pixel driving circuit 311, the third control signal line MUX3 can control the fan-out wire 16 to transmit a signal to the second pixel driving circuit 312, and the second control signal line MUX2 and the fourth control signal line MUX4 both transmit a signal to the third pixel driving circuit 313. In the embodiment, the driving sequence of different types of pixel driving circuits is adjusted to implement effective frequency conversion.

[0092] In a specific example, as shown in FIG. 22, the first control signal line MUX1 can control the fan-out wire 16 to transmit a signal to the first pixel driving circuit 311, the fourth control signal line MUX4 can control the fan-out wire 16 to transmit a signal to the second pixel driving circuit 312, and the second control signal line MUX2 and the third control signal line MUX3 both transmit a signal to the third pixel driving circuit 313. If the display panel currently displays the third color, during the control of the second control signal line MUX2 and the third control signal line MUX3, the frequency of the voltage level flip on the output of the driving chip is reduced by half, effectively reducing the power consumption of the driving chip and prolonging the endurance time of the display panel.

[0093] Continuing to refer to FIG. 18, optionally, in the direction from the second display area AA2 to the first display area AA1 along the first direction X, the tth first data line 111 is electrically connected with the jth second auxiliary wire 122; the (t+1)th first data line 111 is electrically connected with the (j+1)th second auxiliary wire 122; wherein 1≤tM; 1≤j≤M; M is the number of the second data lines 112 of the second display area AA2 on one side of the first display area AA1; t, j and M are all positive integers. In the direction from the second display area AA2 to the first display area AA1 along the first direction X, the second data lines 112 on the second display area AA2 are sequentially connected with the proximal second auxiliary wires 122, then the setting length of the first auxiliary wire 121 required for each second data line 112 to connect the second auxiliary wire 122 tends to be the same. Then the resistance difference of the signal transmission path of each data line is small, and the situation that the signal transmission path loss of a certain data line is large to cause the display picture to be uneven does not easily exist, and the display effect of the display panel is improved.

[0094] Continuing to refer to FIG. 22, optionally, the second display area AA2 can include a plurality of data line groups 115; the data line group 115 includes W second data lines 112 arranged adjacently along the first direction X; W is an integer greater than 1; in the direction from the second display area AA2 to the first display area AA1 along the first direction X, the fth second data line 112 in the same data line group 115 is electrically connected with the kth second auxiliary wire 122; the (f+1)th second data line 112 is electrically connected with the (k+1)th second auxiliary wire 122; wherein 1≤fW; 1≤k≤M; f, k and M are all positive integers; M is the number of the second data lines 112 of the second display area AA2 on one side of the first display area AA1. In this embodiment, the second data lines 112 can be divided into a plurality of data line groups 115 in the direction from the second display area AA2 to the first display area AA1 along the first direction X, each data line group 115 includes the same number of second data lines 112. And in the direction from the second display area AA2 to the first display area AA1, the fth second data line 112 is connected with the kth second auxiliary wire 122 in the first display area AA1, and the (f+1)th second data line 112 is connected with the (k+1)th second auxiliary wire 122. Then, compared with FIG. 18, the first auxiliary wire 121 is irregularly set in this embodiment. The design of the irregular auxiliary wire can reduce the situation that the display panel displays unevenly, reduce the generation of mura, and improve the picture display effect of the display panel.

[0095] Continuing to refer to FIG. 22, optionally, the non-display area can include a first fan-out area S4; the first fan-out area S4 is arranged at a side of the demultiplexer 13 close to the display area; the first fan-out area S4 includes a plurality of first connection leads 161 and a plurality of second connection leads 162; the second auxiliary wire 122 is connected to the second connection lead 162; the first connection lead 161 is arranged to connect the first data line 111 and the first demultiplexer 131; the second connection lead 162 is arranged to connect the second auxiliary wire 122 and the second demultiplexer 132. As known from the above, the fan-out area includes connection leads, demultiplexers, and fan-out wires, etc. In this embodiment, it can be configured that the non-display area can include the first fan-out area S4. The first fan-out area S4 is located between the display area and the demultiplexer 13. The first fan-out area S4 includes the first connection lead 161 and the second connection lead 162, the first connection lead 161 transmits the output signal of the first demultiplexer 131 to the first data line 111, and the second connection lead 162 transmits the output signal of the second demultiplexer 132 to the second auxiliary wire 122. In this embodiment, the demultiplexer 13 is electrically connected to the corresponding first data line 111 or second auxiliary wire 122 in accordance with the principle of nearest connection, effectively reducing the width of the first fan-out area S4 in the second direction Y, and realizing the narrow frame design of the display panel.

[0096] FIG. 23 is a schematic diagram of a film layer structure of a display panel according to an embodiment of the present application. Referring to FIGS. 22 and 23, optionally, the non-display area can include a demultiplexer area 14; the demultiplexer area 14 is arranged with the demultiplexer 13; the second demultiplexer 132 is arranged at a side of the first demultiplexer 131 close to the display area; along the first direction X, a side of the demultiplexer area 14 is arranged with a second power bus BUS2; the length L2 of the second power bus BUS2 along the second direction Y is greater than the length L1 of the demultiplexer area 14 along the second direction Y; a side of the demultiplexer area 14 away from the display area includes a first power bus BUS1.

[0097] As shown in FIG. 23, the non-display area close to the first display area is provided with the demultiplexer area 14. In the first direction X, one side or both sides of the demultiplexer area 14 can be provided with the second power bus BUS2, which can be configured to provide the second power signal PVEE for the pixel driving circuit. As shown in FIG. 23, the longitudinal length L2 of the second power bus BUS2 along the second direction Y is greater than the longitudinal length L1 of the demultiplexer area 14 along the second direction Y. The present embodiment reduces the occupied space of the non-display area by the configuration of the demultiplexer 13, and also reduces the space of the R-angle area. Then, the space left by the non-display area is provided with the second power bus BUS2 with a larger size, which reduces the loss of the second power signal PVEE in the transmission process, and the first power bus BUS1 is provided on the side of the demultiplexer area 14 away from the display area to provide accurate driving current for the pixel driving circuit, thereby improving the display effect of the display panel.

[0098] Referring to FIGS. 9 and 23, optionally, the display panel can include a substrate 41 and a driving circuit layer on the substrate 41; the driving circuit layer is provided with a plurality of pixel driving circuits; the driving circuit layer includes a first active layer 43, a first gate layer 44, a source-drain layer 46, a third metal layer 49 and a fourth metal layer 50 in sequence away from the substrate 41; the auxiliary wire 12 and the data line 11 are arranged on different metal layers; the first power bus BUS1 includes a first bus portion 51 of the fourth metal layer 50; the first bus portion 51 extends to the demultiplexer area 14; the second power bus BUS2 includes a first branch portion 52 of the source-drain layer 46, a second branch portion 53 of the third metal layer 49 and a third branch portion 54 of the fourth metal layer 50.

[0099] The display panel in the embodiment can be an LTPO panel or an LTPS panel. FIG. 9 illustrates an LTPS panel as an example. The driving circuit layer of the display panel includes a first active layer 43, a first gate layer 44, a source-drain layer 46, a third metal layer 49, and a fourth metal layer 50 arranged away from the substrate 11 in sequence. Optionally, an intermediate metal layer 45 can be arranged between the first gate layer 44 and the source-drain layer 46. Optionally, when the display panel is an LTPO panel, the intermediate metal layer 45 and the source-drain layer 46 are further provided with a second active layer and a second gate layer. The auxiliary wire 12 and the data line 11 can be arranged on different metal layers. For example, as shown in FIG. 9, the data line 11 can be arranged on the third metal layer 49; the second auxiliary wire 122 is arranged on the fourth metal layer 50; and the first auxiliary wire 121 is arranged on the source-drain layer 46. As shown in FIG. 9 and FIG. 23, the first power bus BUS1 includes a first bus portion 51 of the fourth metal layer 50, and the first bus portion 51 extends to the multiplexer area 14. In this way, the width of the first power bus BUS1 is increased, the loss of the first power signal is reduced, the space of the multiplexer area 14 is reused, and the narrow frame design of the display panel is not affected. It should be noted that the first gate layer and the first active layer are not shown in FIG. 23 to show the structure of the first bus portion 51, but the actual panel structure includes the first gate layer and the first active layer. The second power bus BUS2 includes a multi-layer stacked structure to further reduce the resistance of the second power bus BUS2. As shown in FIG. 9, the second power bus BUS2 includes a first branch portion 52 of the source-drain layer 46, a second branch portion 53 of the third metal layer 49, and a third branch portion 54 of the fourth metal layer 50, and the adjacent two of the first branch portion 52, the second branch portion 53, and the third branch portion 54 are electrically connected through punching.

[0100] FIG. 24 is a schematic diagram of a film layer structure of another display panel provided in the embodiment. With reference to FIG. 10 and FIG. 24, the multiplexer area can include a first multiplexer area 141 and a second multiplexer area 142; the first multiplexer area 141 is arranged to arrange the first multiplexer 131; the second multiplexer area 142 is arranged to arrange the second multiplexer 132; the display panel includes a substrate 11 and a driving circuit layer on the substrate 11; the driving circuit layer is provided with a plurality of pixel driving circuits; the driving circuit layer includes a first active layer 43, a first gate layer 44, a source-drain layer 46, and a third metal layer 49 arranged away from the substrate 11 in sequence; a second auxiliary wire 122 and a data line 11 are arranged on the third metal layer 49; a first power bus BUS1 includes a second bus portion 55 of the third metal layer 49; the second bus portion 55 extends to the first multiplexer area 141; and a second power bus BUS2 includes a first branch portion 52 of the source-drain layer 46 and a second branch portion 53 of the third metal layer 49.

[0101] The display panel in the embodiment can be an LTPO panel or an LTPS panel. FIG. 10 illustrates an LTPS panel as an example. The driving circuit layer of the display panel includes a first active layer 43, a first gate layer 44, a source-drain layer 46, and a third metal layer 49 arranged in sequence away from the substrate 11. Optionally, an intermediate metal layer 45 can be further arranged between the first gate layer 44 and the source-drain layer 46. Optionally, when the display panel is an LTPO panel, the intermediate metal layer 45 and the source-drain layer 46 are further provided with a second active layer 47 and a second gate layer 48. As shown in FIG. 10, the fourth metal layer is not arranged in the embodiment, and the second auxiliary wire 122 and the data line 11 can be arranged in the same layer and arranged in the third metal layer 49. The first auxiliary wire can be arranged in the source-drain layer, the second gate layer, or other metal layers. The specific arrangement of the first auxiliary wire is not specially limited in the embodiment. In addition, the first power bus BUS1 does not arrange the first bus part 51, but arranges the second bus part 55 in the third metal layer 49. The second bus part 55 covers part of the multiplexer area, which increases the width of the first power bus BUS1, reduces the loss of the first power signal, multiplexes the space of the multiplexer area 14, and does not affect the narrow frame design of the display panel.

[0102] It should be noted that because the first data line also needs to be connected to the first multiplexer 131 through the first connecting lead 161 of the third metal layer 49, the first connecting lead 161 needs to cross the second multiplexer area 142 where the second multiplexer 132 is located. Therefore, in the plane parallel to the substrate, the second bus part 55 only covers the first multiplexer area 141 where the second multiplexer 132 is located, and does not cover the second multiplexer area 142. In addition, as shown in FIG. 10, the second power bus BUS2 includes a multi-layer stacked structure, and the stacked structure only includes the first branch part 52 of the source-drain layer 46 and the second branch part 53 of the third metal layer 49, so as to increase the width of the second power bus BUS2 and reduce the loss of the second power signal.

[0103] Continuing to refer to FIG. 24, optionally, the non-display area can include a multiplexer area 14, the multiplexer area 14 is provided with a multiplexer, a distance d1 between an edge of the multiplexer area 14 and a starting position of the first data line 111 in the first direction X is less than a preset distance D, or an edge of the multiplexer area 14 is aligned with a starting position of the second auxiliary wire 122 in the first direction X.

[0104] In the embodiment, the edge of the demultiplexer region 14 and the starting position of the second auxiliary wire 122 can be aligned along the first direction X, that is, the demultiplexer region 14 is only arranged in the frame region below the first display area AA1, and the frame region below the second display area AA2 is saved for the layout of other signal lines or further reducing the width of the frame region below the second display area AA2 to realize the narrow frame design of the display panel. Alternatively, as shown in FIG. 24, the distance d1 between the edge of the demultiplexer region 14 and the starting position of the first data line 111 along the first direction X is less than the preset distance D. Optionally, the value of the preset distance D can be 1-2 times the size of the pixel driving circuit along the first direction X. In the embodiment, the edge of the demultiplexer region 14 and the starting position of the first data line 111 tend to be the same position, and the R corner region of the display panel and the frame region below the second display area AA2 are not provided with the demultiplexer 13 and the fan-out wire, further reducing the frame width and improving the user experience. In addition, because the second auxiliary wire 122 connected to the demultiplexer 13 and the first data line 111 are arranged in the first display area AA1, the demultiplexer region 14 is arranged close to the first display area AA1 in the embodiment, which can further reduce the setting length of the first connection lead 161, the second connection lead and the fan-out wire, reduce the resistance value of each transmission path and reduce the signal transmission loss. Moreover, the setting length of the first connection lead 161, the second connection lead and the fan-out wire can be as short as possible to further reduce the overall occupied space of the fan-out region and reduce the width of the lower frame of the entire display panel. It should be noted that the lower frame in the embodiment is the non-display area provided with the fan-out region.

[0105] The embodiment of the present application also provides a display device. FIG. 25 is a structural schematic diagram of a display device provided by the embodiment of the present application. As shown in FIG. 25, the display device provided by the embodiment of the present application comprises the display panel 200 provided by any embodiment of the present application. The display device can be a display device of a mobile phone as shown in FIG. 25, or a display device of a computer, a television, a smart wearable device or the like, which is not specially limited in the embodiment.

[0106] The display device in the embodiment comprises the technical features of the display panel provided by any embodiment of the present application, and has the effects of the corresponding technical features, which are not described herein again.

Claims

1. A display panel, comprising: The display area and a non-display area at least partially surrounding the display area; The display area comprises a first display area and a second display area; the second display area is located at least one side of the first display area along a first direction; the display area further comprises a plurality of data lines arranged along the first direction and extending along a second direction; the first direction and the second direction intersect; the data lines comprise a first data line and a second data line; the first data line is arranged in the first display area; the second data line is arranged in the second display area; the display area further comprises a plurality of auxiliary wires; The non-display area comprises a plurality of demultipulators; the auxiliary wires transmit signals output by the demultipulators to the second data lines; Each of the demultipulators comprises N switch elements; the first ends of the switch elements of the same demultipulator are electrically connected to the input end of the demultipulator; The demultipulators comprise a first demultipulator and a second demultipulator; N first data lines are electrically connected to the second ends of N switch elements in the same first demultipulator one by one; N auxiliary wires are electrically connected to the second ends of N switch elements in the same second demultipulator one by one; N is an integer greater than 1; wherein the ratio of the number of the first demultipulators to the number of the second demultipulators ranges from 0.8 to 1.

5.

2. The display panel of claim 1, wherein, Along the first direction, adjacent N first data lines are electrically connected to the second ends of N switch elements in the same first demultipulator one by one; Along the first direction, adjacent N auxiliary wires are electrically connected to the second ends of N switch elements in the same second demultipulator one by one.

3. The display panel of claim 1, wherein, The ratio of the number of the first demultipulators to the number of the second demultipulators ranges from 1 to 1.

25.

4. The display panel of claim 1, wherein, The auxiliary wires comprise first auxiliary wires extending along the first direction and second auxiliary wires extending along the second direction; the first auxiliary wires are arranged to connect corresponding second data lines and second auxiliary wires; the second auxiliary wires are electrically connected to the second ends of the switch elements in the second demultipulators.

5. The display panel of claim 4, wherein, The non-display area further comprises a demultipulator area; the demultipulator area is provided with the demultipulators; Along the first direction, the distance between the edge of the demultipulator area and the starting position of the first data line is less than a preset distance; or, Along the first direction, the edge of the demultipulator area is aligned with the starting position of the second auxiliary wire. In the first display area, the virtual extension line of the second auxiliary wire along the second direction and the second demultipulator connected therewith have an overlapping area.

6. The display panel of claim 4, wherein, The non-display area further comprises a demultipulator area; the demultipulator area is provided with the demultipulators; 7. The display panel of claim 1, wherein, The virtual extension line of the second data line along the second direction does not overlap with the demultipulator area. ​ 8. The display panel of claim 1, wherein, The first multiplexer comprises N first switch elements arranged in sequence along the first direction; the second multiplexer comprises N second switch elements arranged in sequence along the first direction; the switch element comprises an active layer; The active layer of the switch element of the first multiplexer is located on the side of the active layer of the switch element of the second multiplexer away from the display area; In the first direction, the i-th first switch element of the first multiplexer and the i-th second switch element of the second multiplexer share a gate; 1≤i≤N; i is a positive integer.

9. The display panel of claim 1, wherein, The multiplexer further comprises a first element group and a second element group; the first element group and the second element group each comprise a plurality of switch elements arranged in sequence along the first direction; the switch element comprises an active layer; The active layer of the switch element of the second element group is located on the side of the active layer of the switch element of the first element group away from the display area; In the first direction, the p-th switch element of the first element group and the e-th switch element of the second element group share the first terminal; 1≤p≤N; 1≤e≤N; p and e are positive integers.

10. The display panel of claim 9, wherein, In the first direction, the first multiplexer and the second multiplexer are arranged alternately.

11. The display panel of claim 1, wherein, The switch element comprises a double-gate structure; The double-gate structure comprises a first gate structure and a second gate structure; the first gate structure and the second gate structure are arranged on different film layers.

12. The display panel of claim 11, comprising: A substrate; A shielding metal layer is located on the substrate; the shielding metal layer comprises the first gate structure of the switch element; A first active layer is located on the side of the shielding metal layer away from the substrate; the first active layer comprises the active layer of the switch element; A first gate layer is arranged on the side of the first active layer away from the substrate; the first gate layer comprises the second gate structure of the switch element; An intermediate metal layer is arranged on the side of the first gate layer away from the substrate; A source-drain layer is arranged on the side of the intermediate metal layer away from the substrate; the source-drain layer comprises the first terminal and the second terminal of the switch element.

13. The display panel of claim 12, wherein, The shielding metal layer further comprises a shielding portion of the display area; The shielding portion at least partially overlaps with the driving transistor of the display area; the shielding portion is connected to a preset potential; the preset potential is a first power signal, a second power signal, or a reference voltage signal.

14. The display panel of claim 11, comprising: A substrate; and a first active layer, a first gate layer, an intermediate metal layer, a second active layer, a second gate layer, and a source-drain layer arranged in sequence on the substrate; The active layer of the switch element is located in at least one of the first active layer or the second active layer; The first gate structure of the switch element is located in the first gate layer; the second gate structure of the switch element is located in the second gate layer; or The first gate structure of the switch element is located in the intermediate metal layer; the second gate structure of the switch element is located in the second gate layer.

15. The display panel of claim 1, wherein, The non-display area further comprises a binding area; the binding area is located on the side of the multiplexer away from the display area; An input terminal of the multiplexer is electrically connected with a corresponding binding terminal of the binding area; The non-display area further comprises N switch control lines; control terminals of N switch elements of the same multiplexer are electrically connected with the switch control lines one by one.

16. The display panel of claim 4, wherein, The display area further comprises a plurality of columns of pixel driving circuits extending along the second direction and arranged along the first direction; each column of pixel driving circuits is electrically connected with a data line.

17. The display panel of claim 16, wherein, In the first display area, a second auxiliary trace is included between adjacent first data lines.

18. The display panel of claim 16, wherein, In the first display area, two first data lines are included between adjacent second auxiliary traces.

19. The display panel of claim 16, wherein, The display area further comprises: a plurality of sub-pixels arranged in an array, wherein the sub-pixels comprise first color sub-pixels, second color sub-pixels, and third color sub-pixels; The plurality of columns of pixel driving circuits comprise first pixel driving circuit columns and second pixel driving circuit columns arranged alternately; the first pixel driving circuit columns comprise first pixel driving circuits and second pixel driving circuits arranged alternately along the second direction; the second pixel driving circuit columns comprise third pixel driving circuits; the first pixel driving circuits are electrically connected with the first color sub-pixels; the second pixel driving circuits are electrically connected with the second color sub-pixels; and the third pixel driving circuits are electrically connected with the third color sub-pixels. Along the first direction, a qth second auxiliary trace is electrically connected with the first pixel driving circuit columns; a q+1th second auxiliary trace is electrically connected with the second pixel driving circuit columns; 1≤q 20. The display panel of claim 16, wherein, The display area further comprises a plurality of first power signal lines extending along the second direction and arranged along the first direction; A first gap region is included between adjacent first data lines; the first gap region is provided with a second auxiliary trace and a first power signal line; and the second auxiliary trace and the first power signal line are symmetrically arranged about the first gap region.

21. The display panel of claim 4, wherein, The data lines further comprise third data lines and fourth data lines; The display area further comprises a plurality of columns of pixel driving circuits extending along the second direction and arranged along the first direction; pixel driving circuits of odd rows of each column of pixel driving circuits are electrically connected with the third data lines; pixel driving circuits of even rows of each column of pixel driving circuits are electrically connected with the fourth data lines; and the third data lines and the fourth data lines are respectively arranged on opposite sides of a column of pixel driving circuits.

22. The display panel of claim 21, wherein, In the first display area, a second gap region is included between the third data lines and the fourth data lines; the second gap region is provided with a second auxiliary trace.

23. The display panel of claim 21, wherein, In the first display area, a second auxiliary trace is arranged between adjacent third data lines and fourth data lines; In a direction perpendicular to the display panel, the second auxiliary trace at least partially overlaps the third data line, or the second auxiliary trace at least partially overlaps the fourth data line.

24. The display panel of claim 21, wherein, In the first display area, a second gap region is arranged between the third data line and the fourth data line; the second gap region is provided with two second auxiliary traces.

25. The display panel of claim 21, wherein, In the first display area, two second auxiliary traces are arranged between the third data line and the fourth data line; In a direction perpendicular to the display panel, one second auxiliary trace at least partially overlaps the third data line; the other second auxiliary trace at least partially overlaps the fourth data line.

26. The display panel of claim 21, wherein, The display area further comprises: a plurality of sub-pixels arranged in an array, wherein the sub-pixels comprise first color sub-pixels, second color sub-pixels, and third color sub-pixels; The plurality of pixel driving circuit columns comprises first pixel driving circuit columns and second pixel driving circuit columns arranged alternately; the first pixel driving circuit columns comprise first pixel driving circuits and second pixel driving circuits arranged alternately along the second direction; the second pixel driving circuit columns comprise third pixel driving circuits; the first pixel driving circuits are electrically connected to the first color sub-pixels; the second pixel driving circuits are electrically connected to the second color sub-pixels; and the third pixel driving circuits are electrically connected to the third color sub-pixels. Along the first direction, an hth second auxiliary trace is electrically connected to a first pixel driving circuit of the first pixel driving circuit column; an (h+1)th second auxiliary trace is electrically connected to a second pixel driving circuit of the first pixel driving circuit column; an (h+2)th second auxiliary trace is electrically connected to an odd-numbered row third pixel driving circuit of the second pixel driving circuit column; an (h+3)th second auxiliary trace is electrically connected to an even-numbered row third pixel driving circuit of the second pixel driving circuit column; 1≤h≤N-3; h is a positive integer.

27. The display panel of claim 4, wherein, Along a direction from the second display area to the first display area along the first direction, an tth first data line is electrically connected to a jth second auxiliary trace; an (t+1)th first data line is electrically connected to a (j+1)th second auxiliary trace; wherein 1≤tM; 1≤jM; M is the number of second data lines of the second display area on one side of the first display area; t, j, and M are positive integers.

28. The display panel of claim 4, wherein, The second display area comprises a plurality of data line groups; each data line group comprises W second data lines arranged adjacently along the first direction; W is an integer greater than 1. Along a direction from the second display area to the first display area along the first direction, an fth second data line in a same data line group is electrically connected to a kth second auxiliary trace; an (f+1)th second data line is electrically connected to a (k+1)th second auxiliary trace; wherein 1≤fW; 1≤kM; f, k, and M are positive integers; M is the number of second data lines of the second display area on one side of the first display area. 29.The display panel of claim 4, wherein, the non-display area further comprises a first fan-out area; the first fan-out area is disposed on a side of the plurality of demultipulators close to the display area; the first fan-out area comprises a plurality of first connection leads and a plurality of second connection leads; the second auxiliary wires are connected to the second connection leads; the first connection leads are configured to connect the first data lines and the first plurality of demultipulators; the second connection leads are configured to connect the second auxiliary wires and the second plurality of demultipulators.

30. The display panel of claim 4, wherein, the non-display area further comprises a plurality of demultipulator areas; the plurality of demultipulator areas are provided with the plurality of demultipulators; the second plurality of demultipulators are disposed on a side of the first plurality of demultipulators close to the display area; on the first direction, a side of the plurality of demultipulator areas is provided with a second power bus; a length of the second power bus on the second direction is greater than a length of the plurality of demultipulator areas on the second direction; a side of the plurality of demultipulator areas away from the display area comprises a first power bus. 31.The display panel of claim 30, comprising a substrate and a driving circuit layer on the substrate; the driving circuit layer is configured to provide a plurality of pixel driving circuits; the driving circuit layer comprises a first active layer, a first gate layer, a source-drain layer, a third metal layer and a fourth metal layer in sequence away from the substrate; The auxiliary wire and the data line are arranged in different metal layers. the first power bus comprises a first bus portion of the fourth metal layer; the first bus portion extends to the plurality of demultipulator areas; the second power bus comprises a first branch portion of the source-drain layer, a second branch portion of the third metal layer and a third branch portion of the fourth metal layer. 32.The display panel of claim 31, wherein, the data lines are disposed on the third metal layer; the second auxiliary wires are disposed on the fourth metal layer; the first auxiliary wires are disposed on the source-drain layer.

33. The display panel of claim 30, wherein, the plurality of demultipulator areas comprises a first plurality of demultipulator areas and a second plurality of demultipulator areas; the first plurality of demultipulator areas are configured to provide the first plurality of demultipulators; the second plurality of demultipulator areas are configured to provide the second plurality of demultipulators; the display panel comprises a substrate and a driving circuit layer on the substrate; the driving circuit layer is configured to provide a plurality of pixel driving circuits; the driving circuit layer comprises a first active layer, a first gate layer, a source-drain layer and a third metal layer in sequence away from the substrate; the second auxiliary wires and the data lines are disposed on the third metal layer; the first power bus comprises a second bus portion of the third metal layer; the second bus portion extends to the first plurality of demultipulator areas; the second power bus comprises a first branch portion of the source-drain layer and a second branch portion of the third metal layer. 34.A display device comprising the display panel of any one of claims 1-33. ​

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