Semiconductor device, manufacturing method therefor, and electronic device

Abstract

Provided are a semiconductor device, a manufacturing method therefor, and an electronic device. The semiconductor device comprises a plurality of layers of memory cell arrays stacked in a direction perpendicular to a substrate, wherein the memory cell array comprises at least one column of memory cells; a plurality of vertically extending bit lines (30); a plurality of horizontally extending word lines (40); the word lines (40) surround semiconductor layers (23) of a column of transistors, the semiconductor layers (23) extending in a first direction; a dimension of an end face of the semiconductor layers (23) that faces the bit lines (30) in a second direction is less than a minimum dimension of a region of the semiconductor layers (23) that is surrounded by the word lines (40) in the second direction, and a dimension of an end face of the semiconductor layers (23) that faces away from the bit lines (30) in the second direction is less than the minimum dimension of the region of the semiconductor layers (23) that is surrounded by the word lines (40) in the second direction.

Description

A semiconductor device, a manufacturing method thereof, and an electronic device

[0001] The present application claims priority to the Chinese patent application No. 2024112376688, filed on September 4, 2024, and entitled "A semiconductor device, a manufacturing method thereof, and an electronic device", the content of which is to be understood as incorporated herein by reference. TECHNICAL FIELD

[0002] Embodiments of the present disclosure relate to, but are not limited to, device design and manufacturing thereof in the technical field of semiconductor technology, and in particular to a semiconductor device, a manufacturing method thereof, and an electronic device. BACKGROUND

[0003] With the development of integrated circuit technology, the critical dimension of the device is increasingly reduced, and the types and quantities of devices contained in a single chip are also increasing, so that any slight difference in process production can affect the performance of the device.

[0004] In order to reduce the cost of products as much as possible, people want to make as many device units as possible on a limited substrate. Since the advent of Moore's Law, various semiconductor structure designs and process optimizations have been proposed in the industry to meet people's current product needs.

[0005] SUMMARY

[0006] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0007] The present application provides a semiconductor device, comprising:

[0008] A plurality of memory cell arrays stacked along a direction perpendicular to a substrate, the memory cell arrays comprising at least one column of a plurality of memory cells distributed along a second direction parallel to the substrate;

[0009] A plurality of bit lines extending along a direction perpendicular to the substrate through the memory cells of the plurality of layers;

[0010] A plurality of word lines distributed in different layers, the word lines and the bit lines being distributed along a first direction parallel to the substrate, the word lines extending along the second direction, the first direction and the second direction intersecting;

[0011] The memory cell includes a transistor including a semiconductor layer extending in the first direction; the word line encircles a part of a side surface of a plurality of the semiconductor layers of a column of the memory cells; a dimension of the semiconductor layer toward an end surface of the bit line in the second direction is smaller than a minimum dimension of an area of the semiconductor layer encircled by the word line in the second direction, and a dimension of the semiconductor layer away from the end surface of the bit line in the second direction is smaller than the minimum dimension of the area of the semiconductor layer encircled by the word line in the second direction.

[0012] In some embodiments, of the two side surfaces of the semiconductor layer opposite in the second direction, each of the side surfaces includes a first surface, a second surface, and a third surface sequentially distributed in the first direction, a part of the first surface and the second surface are encircled by the word line, the third surface is located between the area of the semiconductor layer encircled by the word line and the end surface of the semiconductor layer toward the bit line, and a junction of the first surface and the second surface is convex to the semiconductor layer adjacent in the second direction.

[0013] In some embodiments, a junction of the second surface and the third surface is convex to the semiconductor layer adjacent in the second direction.

[0014] In some embodiments, two side surfaces of the word line located between the semiconductor layers adjacent in the second direction and opposite in the first direction form an arc-shaped recess.

[0015] In some embodiments, a dimension of a cross section of the bit line parallel to the substrate in the second direction is smaller than a dimension of the cross section in the first direction.

[0016] In some embodiments, a gate insulating layer is provided between the semiconductor layer and the word line, the gate insulating layer encircles the semiconductor layer, and on the two side surfaces of the semiconductor layer opposite in the second direction, the gate insulating layer is distributed on the first surface and the second surface and not distributed on the third surface.

[0017] In some embodiments, the gate insulating layer continuously extends on the surface of the semiconductor layer away from the substrate and the surface of the semiconductor layer toward the substrate.

[0018] In some embodiments, the semiconductor layer includes single crystal silicon, and the gate insulating layer is silicon oxide formed by oxidizing the single crystal silicon.

[0019] In some embodiments, the semiconductor device further includes a first connecting sub-layer connected to an end surface of the semiconductor layer toward the bit line, and a second connecting sub-layer connected to an end surface of the semiconductor layer away from the bit line, the first connecting sub-layer and the second connecting sub-layer are metal silicides formed by metal silicidation of single crystal silicon, and the first connecting sub-layer is connected to the bit line.

[0020] In some embodiments, the memory cell further comprises a capacitor comprising a first capacitor electrode and a second capacitor electrode, the second capacitor electrode comprising a first sub-electrode, the semiconductor device further comprising a capacitor hole penetrating through multiple layers of the memory cell, a plurality of first capacitor electrodes of multiple memory cells at the same position of different layers are disposed on sidewalls of the capacitor hole and are spaced apart in a direction perpendicular to the substrate, the first sub-electrode fills the capacitor hole, and the plurality of first capacitor electrodes surround the first sub-electrode through a first dielectric layer.

[0021] In some embodiments, the capacitor hole exposes a plurality of second connection sub-layers respectively connected to a plurality of semiconductor layers of multiple memory cells stacked in a direction perpendicular to the substrate, and the first capacitor electrode is connected to the exposed second connection sub-layers.

[0022] In some embodiments, the first capacitor electrode comprises a first portion extending in a direction perpendicular to the substrate and a second portion extending from both ends of the first portion towards the first sub-electrode, respectively; and the first portion is connected to the second connection sub-layers.

[0023] In some embodiments, the second capacitor electrode further comprises a second sub-electrode, and the second sub-electrode surrounds the first portion through a second dielectric layer portion.

[0024] In some embodiments, a distance between a surface away from the substrate and a surface towards the substrate of the word line is equal to a length of the first capacitor electrode extending in a direction perpendicular to the substrate.

[0025] In some embodiments, the semiconductor device further comprises a first isolation hole penetrating through multiple layers of the memory cell array and an insulating film layer filling the first isolation hole, which is disposed between semiconductor layers adjacent in a second direction, between a column of capacitors distributed in the second direction and the word line; and a second isolation hole penetrating through multiple layers of the memory cell array and an insulating film layer filling the second isolation hole, which is disposed between bit lines adjacent in the second direction, between the word lines adjacent in the first direction.

[0026] Embodiments of the present disclosure provide a semiconductor device manufacturing method, comprising:

[0027] forming a stack structure comprising a plurality of semiconductor structure layers and sacrificial layers arranged alternately on a substrate;

[0028] forming a plurality of first holes penetrating through the stack structure in a direction perpendicular to the substrate and spaced apart in a second direction;

[0029] forming second holes through the stack structure in a direction perpendicular to the substrate direction between adjacent first holes, the second holes having a larger aperture in the first direction than the first holes;

[0030] lateral etching the semiconductor structure layers based on the second holes such that the second holes intersect the first holes and semiconductor structure layers remain between adjacent second holes in the second direction;

[0031] forming first trenches through the stack structure in the second direction;

[0032] forming a plurality of third holes through the stack structure in a direction perpendicular to the substrate direction between the first trenches and the first holes, the third holes and the first holes defining a transistor region;

[0033] etching the semiconductor structure layers based on the first trenches in a direction parallel to the substrate direction to remove semiconductor structure layers outside the transistor region and portions of the semiconductor structure layers in the transistor region, and to form fifth lateral recesses with the remaining semiconductor structure layers in the transistor region connected to portions of sidewalls of the third holes facing the first holes;

[0034] forming, in the transistor region, a plurality of first word line holes through the stack structure in the second direction spaced apart from each other and a plurality of second word line holes through the stack structure in the second direction spaced apart from each other, sidewalls of the first word line holes and the second word line holes exposing each of the semiconductor structure layers, the first word line holes and the second word line holes being spaced apart from each other in the first direction, the second word line holes being located in the region of the second holes;

[0035] etching the semiconductor structure layers based on the first word line holes and the second word line holes in a direction parallel to the substrate direction to form channels connecting adjacent first word line holes and second word line holes in the first direction to divide the semiconductor structure layers into a plurality of semiconductor layers of a corresponding plurality of transistors extending in the first direction and spaced apart from each other in the second direction;

[0036] forming, in sequence, a gate insulating layer surrounding the semiconductor layers, and a word line surrounding portions of side surfaces of the plurality of semiconductor layers of a column of transistors extending in the second direction;

[0037] forming a bit line extending in a direction perpendicular to the substrate direction in the first holes.

[0038] In some embodiments, before forming the first word line holes and the second word line holes, the method further comprises:

[0039] depositing an isolation layer film filling the fifth lateral recess, etching the isolation layer film to a side of the third hole facing the first hole outside the transistor region to form an isolation layer extending along the second direction and distributed in a region of the third hole facing the first hole and not in contact with the semiconductor layer;

[0040] wherein a sidewall of the first word line hole exposes the isolation layer.

[0041] In some embodiments, before the lateral etching of the semiconductor structure layer based on the second hole, further comprising, etching and removing a preset length of the sacrificial layer along a direction parallel to the substrate based on the second hole, and sequentially forming a first barrier layer covering the inner wall of the region where the sacrificial layer is etched and removed, and an insulating layer filling the region where the sacrificial layer is etched and removed.

[0042] After forming a plurality of semiconductor layers corresponding to a plurality of transistors extending along the first direction and spaced apart along the second direction, before sequentially forming a gate insulating layer surrounding the semiconductor layer, further comprising:

[0043] Etching and removing the first barrier layer so that the semiconductor layer forms a suspended structure with an exposed side surface, and thinning the thickness of the semiconductor layer along a direction perpendicular to the substrate;

[0044] The sequentially formed gate insulating layer surrounding the semiconductor layer, and the word line surrounding part of the side surface of the plurality of semiconductor layers surrounding a column of transistors distributed along the second direction, comprise:

[0045] Oxidizing the exposed side surface of the semiconductor layer to form the gate insulating layer;

[0046] Forming a word line filling the channel and the void left after the semiconductor layer is thinned;

[0047] Etching the word line based on the first hole and the third hole to retain the word line surrounding the channel region of the semiconductor layer.

[0048] In some embodiments, after etching the word line based on the first hole and the third hole to retain the word line surrounding the channel region of the semiconductor layer, further comprising,

[0049] Performing a metal silicidation process on one end of the semiconductor layer close to the first hole and one end close to the third hole to form a first connection sub-layer disposed on the side of the semiconductor layer close to the first hole and a second connection sub-layer disposed on the side of the semiconductor layer close to the third hole.

[0050] In some embodiments, before forming the first trench extending along the second direction through the stack structure, further comprising:

[0051] forming a second blocking layer covering sidewalls of the first hole and a first dummy layer filling the first hole;

[0052] etching the second blocking layer towards two sidewalls of a second hole adjacent in a second direction, exposing sidewalls of the first dummy layer, and thinning the first dummy layer in the second direction;

[0053] The forming of the bit line in the first hole includes:

[0054] etching to remove the first dummy layer and the second blocking layer, forming a bit line hole, and forming a bit line filling the bit line hole.

[0055] In some embodiments, before the etching of the word line based on the first hole and the third hole, further comprising:

[0056] forming a fourth lateral recess based on the third hole etching the semiconductor structure layer in a direction parallel to the substrate direction;

[0057] forming a third blocking layer covering inner walls of the fourth lateral recess and the third hole, and a second dummy layer filling the third hole and the fourth lateral recess;

[0058] etching to remove the second dummy layer at the same time of etching to remove the first dummy layer, and etching to remove the third blocking layer at the same time of etching to remove the second blocking layer;

[0059] after forming the first connection sub-layer arranged on one side of the semiconductor layer close to the first hole and the second connection sub-layer arranged on one side of the semiconductor layer close to the third hole, further comprising:

[0060] depositing a first conductive film covering inner walls of the third hole and the fourth lateral recess, etching to remove the first conductive film on sidewalls of the third hole, and retaining the conductive film on the inner walls of the fourth lateral recess to form a first capacitor electrode;

[0061] The forming of the bit line filling the bit line hole includes: depositing a first conductive film covering inner walls of the bit line hole to form a first conductive sub-layer of the bit line at the same time of depositing the first conductive film covering inner walls of the third hole and the fourth lateral recess;

[0062] depositing a second conductive film filling the bit line hole to form a second conductive sub-layer of the bit line in the bit line hole formed with the first conductive film.

[0063] The electronic device includes any of the semiconductor devices, or the semiconductor device formed by any of the manufacturing methods of the semiconductor device.

[0064] Other features and advantages of the present application will be set forth in the description that follows, and in part will be apparent from the description, or can be learned by practice of the application. The advantages of the present application will be realized and attained by the structure particularly pointed out in the description and claims hereof as well as the appended drawings.

[0065] Other aspects can become apparent from the following description, which is given by way of example only.

[0066] BRIEF DESCRIPTION OF DRAWINGS

[0067] The accompanying drawings are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the principles of the application. The drawings are provided for merely the purposes of illustration and description and can not be used to impose the only limitations on the application.

[0068] FIGS. 1A-1D are cross-sectional views of a semiconductor device along AA', BB', DD', and FF' directions, respectively, according to some embodiments;

[0069] FIGS. 2A-2D are cross-sectional views of the semiconductor device along AA', BB', CC', and DD' directions, respectively, after forming first holes, according to some embodiments;

[0070] FIGS. 3A-3C are cross-sectional views of the semiconductor device along AA', B1B1', and CC' directions, respectively, after forming second holes, according to some embodiments;

[0071] FIGS. 4A-4C are cross-sectional views of the semiconductor device along AA', B1B1', and CC' directions, respectively, after thinning a bit line region, according to some embodiments;

[0072] FIGS. 5A-5D are cross-sectional views of the semiconductor device along AA', B1B1', CC', and DD' directions, respectively, after forming first trenches, according to some embodiments;

[0073] FIGS. 6A-6D are cross-sectional views of the semiconductor device along AA', BB', CC', and DD' directions, respectively, after forming third holes, according to some embodiments;

[0074] FIGS. 7A-7E are cross-sectional views of the semiconductor device along AA', BB', B1B1', CC', and DD' directions, respectively, after forming a second isolation layer, according to some embodiments;

[0075] FIGS. 8A-8D are cross-sectional views of the semiconductor device along AA', BB', DD', and EE' directions, respectively, after forming first and second word line holes, according to some embodiments;

[0076] FIGS. 9A-9D are cross-sectional views of the semiconductor device along AA', BB', DD', and EE' directions, respectively, after forming a semiconductor layer, according to some embodiments;

[0077] FIGS. 10A-10D are cross-sectional views of the word line along the AA’ direction, the BB’ direction, the DD’ direction, and the EE’ direction, respectively, according to some embodiments;

[0078] FIGS. 11A-11D are cross-sectional views of the word line along the AA’ direction, the BB’ direction, the DD’ direction, and the FF’ direction, respectively, according to some embodiments;

[0079] FIGS. 12A-12C are cross-sectional views of the word line along the AA’ direction, the BB’ direction, and the DD’ direction, respectively, according to some embodiments;

[0080] FIGS. 13A-13C are cross-sectional views of the word line along the AA’ direction, the BB’ direction, and the DD’ direction, respectively, according to some embodiments;

[0081] FIGS. 14A-14C are cross-sectional views of the word line along the AA’ direction, the BB’ direction, and the DD’ direction, respectively, according to some embodiments;

[0082] FIGS. 15A-15C are cross-sectional views of the word line along the AA’ direction, the BB’ direction, and the DD’ direction, respectively, according to some embodiments;

[0083] FIGS. 16A-16C are cross-sectional views of the word line along the AA’ direction, the BB’ direction, and the DD’ direction, respectively, according to some embodiments;

[0084] FIGS. 17A and 17B are cross-sectional views of the word line along the BB’ direction and the DD’ direction, respectively, according to some embodiments;

[0085] FIGS. 18A and 18B are cross-sectional views of the word line along the AA’ direction and the BB’ direction, respectively, according to some embodiments;

[0086] FIG. 19 is a cross-sectional view of the word line along the BB’ direction, according to some embodiments;

[0087] FIGS. 20A-20C are cross-sectional views of the word line along the AA’ direction, the BB’ direction, and the DD’ direction, respectively, according to some embodiments.

[0088] DETAILED DESCRIPTION

[0089] The embodiments of the present disclosure will be described in detail below with reference to the drawings. The features of the embodiments of the present disclosure and the embodiments can be combined with each other as long as there is no conflict.

[0090] Unless otherwise defined, technical terms or scientific terms used in the present disclosure shall have the same meaning as those commonly understood by a person of ordinary skill in the art to which the present disclosure belongs.

[0091] Embodiments of the present disclosure are not necessarily limited to the sizes of the components shown in the drawings, and the shapes and sizes of the components shown in the drawings do not reflect true proportions. Furthermore, the drawings schematically show ideal examples, and embodiments of the present disclosure are not limited to the shapes or values shown in the drawings.

[0092] In the present disclosure, ordinal numbers such as "first", "second", "third", and the like are set in order to avoid confusion of components, and do not represent any order, number, or importance.

[0093] In the present disclosure, in order to facilitate the description, words indicating the orientation or positional relationship such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like are used to describe the positional relationship of the components with reference to the drawings, and are only for the convenience of describing the present specification and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present disclosure. The positional relationship of the components is appropriately changed according to the direction in which each component is described. Therefore, it is not limited to the words described in the disclosure, and can be appropriately replaced according to the situation.

[0094] In the present disclosure, unless explicitly defined and limited otherwise, the terms "mount", "connected", "connection" should be interpreted broadly. For example, it can be a physical connection or a signal connection, it can be a contact connection or an integral connection; it can be directly connected, or indirectly connected through an intermediate, or the communication between two elements inside. For those skilled in the art, the specific meaning of the above terms in the present disclosure can be understood according to the specific circumstances.

[0095] In the present disclosure, a transistor refers to an element including at least a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In the present disclosure, the channel region refers to a region through which current mainly flows.

[0096] In the present disclosure, it can be that the first electrode is the drain electrode and the second electrode is the source electrode, or it can be that the first electrode is the source electrode and the second electrode is the drain electrode. In the case of using a transistor with opposite polarity or in the case of changing the direction of current in the circuit operation, the functions of "source electrode" and "drain electrode" are sometimes exchanged with each other. Therefore, in the present disclosure, "source electrode" and "drain electrode" can be exchanged with each other.

[0097] In the present disclosure, "connection" includes a case where components are connected together through an element having some electrical action. The element having some electrical action is not particularly limited as long as it can perform the transmission and reception of electrical signals between the connected components. Examples of the element having some electrical action include not only electrodes and wiring but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0098] In the present disclosure, "parallel" means approximately parallel or almost parallel, such as a state where two straight lines form an angle of -10° or more and 10° or less, and thus also includes a state where the angle is -5° or more and 5° or less. In addition, "perpendicular" means approximately perpendicular, such as a state where two straight lines form an angle of 80° or more and 100° or less, and thus also includes a state where the angle is 85° or more and 95° or less.

[0099] In the present disclosure, "A and B are of an integral structure" can mean that there is no obvious fault or gap as an obvious boundary interface in a microscopic structure. Generally, a film layer patterned on one film layer is of an integral structure. For example, A and B are of one film layer using the same material and are formed by the same patterning process to have a connection relationship.

[0100] FIGS. 1A to 1D are cross-sectional views of a semiconductor device along AA' direction, BB' direction, DD' direction, and FF' direction, respectively, according to some embodiments. The AA' direction is parallel to the substrate 1 and passes through a film layer where the semiconductor layer 23 is located, and the BB' direction, DD' direction, and FF' direction are perpendicular to the substrate 1. As shown in FIGS. 1A to 1D, the present disclosure provides a semiconductor device, which can include a multilayer memory cell array stacked in a direction perpendicular to the substrate 1 on the substrate 1.

[0101] The memory cell array can include a plurality of memory cells, a plurality of bit lines 30, and a plurality of word lines 40. Each layer of the memory cell array can include a plurality of memory cells arrayed in a first direction X parallel to the substrate 1 and a second direction Y parallel to the substrate 1. The first direction X and the second direction Y can intersect. In some embodiments, the first direction X and the second direction Y can be perpendicular.

[0102] The bit lines 30 can extend in a direction perpendicular to the substrate 1, and a plurality of memory cells stacked in the vertical direction at the same position of different layers are connected to the same bit line 30.

[0103] In some embodiments, memory cells adjacent in the first direction X are connected to the same bit line 30. Every two columns of memory cells can be a group, and memory cells within the same group are connected to the same bit line 30.

[0104] The word lines 40 can extend along the second direction Y, a plurality of word lines 40 of the same memory cell array can be spaced apart from each other, and the plurality of word lines 40 of the same memory cell array can be spaced apart along the first direction X. The word lines 40 of memory cell arrays of different layers can be arranged in a stacked manner perpendicular to the substrate 1.

[0105] The memory cell can be a 1T1C memory cell, or can be a memory cell of other structures.

[0106] Taking a 1T1C memory cell as an example, the memory cell can include a transistor and a capacitor connected to the transistor. The transistor and the capacitor of the same memory cell can be distributed along the first direction X. The capacitor, the word line 40, and the bit line 30 can be distributed along the first direction X.

[0107] The transistor can include a semiconductor layer 23 extending along the first direction X, the word line 40 surrounds a part of the side surface of a plurality of semiconductor layers 23 of a column of memory cells distributed along the second direction Y; the size of the end surface of the semiconductor layer 23 facing the bit line 30 along the second direction Y is smaller than the minimum size of the region of the semiconductor layer 23 surrounded by the word line 40 along the second direction Y, and the size of the end surface of the semiconductor layer 23 away from the bit line 30 along the second direction Y is smaller than the minimum size of the region of the semiconductor layer 23 surrounded by the word line 40 along the second direction Y. The region of the semiconductor layer 23 surrounded by the word line 40 is a channel region, and the semiconductor layer 23 further includes a first region and a second region (one of which is a source region and the other is a drain region) distributed at both ends of the channel region along the first direction X.

[0108] The scheme provided by the embodiment realizes a structure of vertical bit lines, horizontal word lines, and word lines surrounding semiconductor layers. Compared with the scheme of horizontal bit lines and vertical word lines, the thickness of the word lines can be smaller, thereby reducing the parasitic capacitance between the word lines and the bit lines. Moreover, the end surface of the semiconductor layer is small and the middle part is large, which is beneficial to reducing the device area and improving the device density.

[0109] In some embodiments, of the two opposite side surfaces of the semiconductor layer 23 along the second direction Y, each of the side surfaces includes a first surface, a second surface, and a third surface distributed along the first direction X in sequence, a part of the first surface and the second surface are surrounded by the word line 40, the third surface is located between the region of the semiconductor layer 23 surrounded by the word line 40 and the end surface of the semiconductor layer 23 facing the bit line 30, and the connection between the first surface and the second surface is protruded to the semiconductor layer 23 of the memory cell adjacent along the second direction Y.

[0110] In some embodiments, the semiconductor layer 23 can be a solid structure.

[0111] In some embodiments, the distance between the first surfaces of the semiconductor layer 23 opposite in the second direction Y decreases in a direction away from the bit line 30.

[0112] In some embodiments, the distance between the third surfaces of the semiconductor layer 23 opposite in the second direction Y decreases in a direction toward the bit line 30.

[0113] In some embodiments, the distance at the junction of the first and second surfaces of the semiconductor layer 23 opposite in the second direction Y is the maximum distance of the semiconductor layer 23 in the second direction Y.

[0114] In some embodiments, the junction of the second and third surfaces protrudes toward the semiconductor layer 23 of the storage unit adjacent in the second direction Y.

[0115] In some embodiments, the two side surfaces of the word line 40 opposite in the first direction X and located between the semiconductor layers 23 adjacent in the second direction Y can form an arc-shaped recess. That is, a cavity can be generated by etching from both sides to the region where the word line 40 is to be formed, so as to form the word line 40.

[0116] In some embodiments, the dimension of the cross section of the bit line 30 parallel to the substrate 1 in the second direction Y can be smaller than the dimension of the cross section in the first direction X. That is, in the embodiments of the present disclosure, the dimension of the bit line 30 in the second direction Y can be thinned as much as possible, so that the distance between the bit lines 30 adjacent in the second direction Y is increased, and the coupling capacitance between the adjacent bit lines 30 is reduced.

[0117] In some embodiments, a gate insulating layer 24 is provided between the semiconductor layer 23 and the word line 40, the gate insulating layer 24 surrounds the semiconductor layer 23, and on the two side surfaces of the semiconductor layer 23 opposite in the second direction Y, the gate insulating layer 24 can be distributed on the first surface, the second surface and not distributed on the third surface.

[0118] In some embodiments, the gate insulating layer 24 can continuously extend on the surface of the semiconductor layer 23 away from the substrate 1 and the surface of the semiconductor layer 23 toward the substrate 1. That is, the gate insulating layer 24 covers the surface of the semiconductor layer 23 away from the substrate 1 and the surface of the semiconductor layer 23 toward the substrate 1.

[0119] In some embodiments, the semiconductor layer 23 can include single crystal silicon, and the gate insulating layer 24 can be silicon oxide formed by oxidizing the single crystal silicon. That is, the semiconductor layer 23 is formed using single crystal silicon, and the gate insulating layer 24 is formed by oxidizing the surface of the semiconductor layer 23.

[0120] In some embodiments, the semiconductor device can further include a first connecting sub-layer 251 connected to an end surface of the semiconductor layer 23 on a side facing the bit line 30, and a second connecting sub-layer 252 connected to an end surface of the semiconductor layer 23 on a side facing away from the bit line 30, the first connecting sub-layer 251 and the second connecting sub-layer 252 can be metal silicides formed by metal silicidation of single crystal silicon, the first connecting sub-layer 251 is connected to the bit line 30, and the second connecting sub-layer 252 is connected to the first capacitor electrode 41 of the capacitor.

[0121] In some embodiments, the gate insulating layer 24 can further extend to the surface of the first connecting sub-layer 251 facing away from the substrate 1 and the surface of the first connecting sub-layer 251 facing the substrate 1, and extend to the surface of the second connecting sub-layer 252 facing away from the substrate 1 and the surface of the second connecting sub-layer 252 facing the substrate 1.

[0122] In some embodiments, the capacitor can include a first capacitor electrode 41 and a second capacitor electrode, the second capacitor electrode can include a first sub-electrode 421, and the semiconductor device can further include a capacitor hole penetrating through multiple layers of the capacitor of the memory cell, and multiple first capacitor electrodes 41 of multiple memory cells at the same position of different layers are arranged on the sidewall of the capacitor hole and are spaced apart in a direction perpendicular to the substrate 1, and the first sub-electrode 421 fills the capacitor hole, and the multiple first capacitor electrodes 41 surround the first sub-electrode 421 through a first dielectric layer 431.

[0123] In some embodiments, the capacitor hole exposes multiple second connecting sub-layers 252 connected to multiple semiconductor layers 23 of multiple memory cells stacked in a direction perpendicular to the substrate 1, respectively, and the first capacitor electrode 41 is connected to the exposed second connecting sub-layers 252.

[0124] In some embodiments, the first capacitor electrode 41 includes a first portion extending in a direction perpendicular to the substrate 1 and a second portion extending from both ends of the first portion toward the first sub-electrode 421, respectively; and the first portion is connected to the second connecting sub-layer 252. That is, the first capacitor electrode 41 can form a ring-shaped recess, the ring-shaped recess can include a bottom wall perpendicular to the substrate 1 and two sidewalls parallel to the substrate 1, the bottom wall includes an inner bottom wall located inside the ring-shaped recess and an outer bottom wall located outside the ring-shaped recess, and the second connecting sub-layer 252 is connected to a partial area of the outer bottom wall. The projection of the ring-shaped recess on the substrate 1 can be a closed ring.

[0125] In some embodiments, the first sub-electrodes 421 of the memory cells at the same position of different layers can be connected to form an integrated structure extending in a direction perpendicular to the substrate 1.

[0126] In some embodiments, the first dielectric layers 431 of the capacitors in the same position of different layers can be connected to form an integrated structure.

[0127] In some embodiments, the sidewall of the annular groove includes an inner sidewall inside the annular groove and an outer sidewall outside the annular groove, and the first sub-electrode 421 is also distributed on the outer sidewall of the annular groove. That is, the first sub-electrode 421 can be distributed on the inner wall (including the inner bottom wall and the inner sidewall) of the annular groove, and can also be distributed on the outer sidewall of the annular groove, so as to increase the facing area with the first capacitor electrode 41 as much as possible and increase the capacitance of the capacitor. However, the embodiments of the present disclosure are not limited thereto, and the first sub-electrode 421 can not be distributed on the outer sidewall of the annular groove.

[0128] In some embodiments, the second capacitor electrode can further include a second sub-electrode 422, which partially surrounds the first part of the first capacitor electrode 41 through the second dielectric layer 432. The scheme provided in the present embodiment can further increase the capacitance of the capacitor by arranging the electrode outside the first capacitor electrode 41.

[0129] In some embodiments, the second sub-electrodes 422 of the capacitors in the same column and distributed along the second direction Y in the same layer can be connected to form an integrated structure.

[0130] In some embodiments, the second dielectric layers 432 of the capacitors in the same column and distributed along the second direction Y in the same layer can be connected to form an integrated structure.

[0131] In some embodiments, the second dielectric layers 432 of the capacitors in the same position of different layers can be connected to form an integrated structure.

[0132] In some embodiments, the distance between the surface away from the substrate 1 and the surface towards the substrate 1 of the word line 40 can be equal to the length of the first capacitor electrode 41 extending in the vertical direction of the substrate 1, that is, equal to the distance between the surface away from the substrate 1 and the surface towards the substrate 1 of the first capacitor electrode 41. That is, the film layer positions of the word line 40 and the first capacitor electrode 41 in the vertical direction are basically the same.

[0133] In some embodiments, the semiconductor device can further include a first isolation hole (see the first word line hole K41 described in subsequent embodiments) penetrating through the memory cell array in multiple layers between the capacitors arranged along the second direction Y and the word lines 40 arranged along the second direction Y, and an insulating film layer filling the first isolation hole; and a second isolation hole (see the second hole K2 described in subsequent embodiments) penetrating through the memory cell array in multiple layers between the bit lines 30 arranged along the second direction Y and the word lines 40 arranged along the first direction X, and an insulating film layer filling the second isolation hole.

[0134] The technical solution of the present embodiment is further illustrated below through the manufacturing process of the semiconductor device of the present embodiment. In the present embodiment, the film layer pattern is formed through a "patterning process" or a "photolithography process". The "patterning process" described in the present embodiment includes deposition of a film layer, coating of a photoresist, mask exposure, development, etching, stripping of the photoresist, etc., which are mature manufacturing processes in the related art. The "photolithography process" described in the present embodiment includes coating of a film layer, mask exposure, and development, which are mature manufacturing processes in the related art. Deposition can use known processes such as sputtering, evaporation, chemical vapor deposition, etc., coating can use known coating processes, and etching can use known methods, which are not specifically limited herein. In the description of the present embodiment, it should be understood that "thin film" refers to a thin film of a certain material manufactured on a substrate using a deposition or coating process. If the "thin film" does not need a patterning process or a photolithography process during the entire manufacturing process, the "thin film" can also be referred to as a "layer". If the "thin film" still needs a patterning process or a photolithography process during the entire manufacturing process, it is referred to as a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process or the photolithography process contains at least one "pattern".

[0135] In an exemplary embodiment, the manufacturing process of the semiconductor device can include:

[0136] 1) forming a first hole K1;

[0137] alternately growing single-crystal silicon and sacrificial layer thin films on the substrate 1 to form a stacked structure including a plurality of alternately arranged semiconductor structure layers 23' and sacrificial layers 10;

[0138] depositing a first insulating thin film to form a first insulating layer 11 covering the stacked structure;

[0139] etching the stacked structure from the top layer to the bottom layer in a direction perpendicular to the substrate 1 (the etching stops on the substrate 1) to form a plurality of first holes K1 spaced along the second direction Y; when manufacturing a memory array, the first holes K1 spaced along the second direction Y are referred to as a column of first holes K1, and a plurality of columns of first holes K1 spaced along the first direction X can be formed;

[0140] depositing a second insulating film to form a second insulating layer 12 (i.e., a second barrier layer) covering the bottom wall and the sidewall of the first hole K1;

[0141] depositing a first dummy layer film to form a first dummy layer 91 filling the first hole K1; as shown in FIG. 2A, FIG. 2B, FIG. 2C, FIG. 2D. FIG. 2A to FIG. 2D are cross-sectional views of the substrate 1 along the AA' direction, the BB' direction, the CC' direction, and the DD' direction, respectively, after forming the first hole K1 according to some embodiments. The CC' direction is perpendicular to the substrate 1.

[0142] In some embodiments, the substrate 1 can be a conventional silicon substrate or other bulk substrate including a semiconductor material layer.

[0143] In some embodiments, the sacrificial layer film can be silicon germanium (SiGe).

[0144] In some embodiments, the first insulating film and the second insulating film can be a low-K dielectric layer, including but not limited to silicon oxide, such as silicon dioxide (SiO2), etc. The materials of the subsequent fourth insulating film to the fourteenth insulating film are similar, and are not described again.

[0145] In some embodiments, the first dummy layer film can be a material with etching selectivity to the first insulating film and the sacrificial layer film, such as polysilicon, etc. The materials of the subsequent second dummy layer film to the fourth dummy layer film are similar to the first dummy layer film, and are not described again.

[0146] 2) forming a second hole K2;

[0147] etching the stack structure from the top layer to the bottom layer in a direction perpendicular to the substrate 1 (the etching stops on the substrate 1) to form a plurality of second holes K2 spaced along the second direction Y, the second holes K2 being arranged between the first holes K1 adjacent along the second direction Y, the second holes K2 having a size along the first direction X greater than the size of the first holes K1 along the first direction X, and the second holes K2 exposing part of the outer sidewall of the second insulating layer 12 in the two first holes K1 adjacent to the second hole K2;

[0148] Based on the second hole K2, laterally etching (etching in a direction parallel to the substrate 1) the sacrificial layer 10, etching to remove the sacrificial layer 10 in the transistor region, and retaining the sacrificial layer 10 in the capacitor region; forming a first lateral recess A1;

[0149] Low-temperature atomic layer deposition of a third insulating film to form a third insulating layer 13 (i.e., a first barrier layer), which can be silicon dioxide or silicon nitride (SiN), etc. The third insulating layer 13 covers the bottom wall and sidewall of the first lateral recess A1, and the sidewall of the second hole K2; the temperature of the low-temperature atomic layer deposition can be, for example, 50-60°C.

[0150] Deposition of a fourth insulating film to form a fourth insulating layer 14 filling the first lateral recess A1 and the second hole K2; there is a certain etching selectivity between the fourth insulating layer 14 and the third insulating layer 13, which facilitates subsequent etching of the third insulating layer 13 without affecting the fourth insulating layer 14. When the fourth insulating layer is SiO2, high-temperature atomic layer deposition can be used, for example, at a temperature of 700-800°C, etc., so that there is a large etching selectivity between the SiO2 formed by low-temperature atomic layer deposition.

[0151] Etching to remove the fourth insulating layer 14 and the third insulating layer 13 in the second hole K2, exposing the semiconductor structure layer 23' on the sidewall of the second hole K2;

[0152] Based on the second hole K2, the semiconductor structure layer 23' is etched laterally to form a second lateral recess A2; the length of the semiconductor structure layer 23' etched is less than the length of the sacrificial layer 10 etched, and after the semiconductor structure layer 23' is etched laterally, there is still a semiconductor structure layer 23' between the second holes K2 adjacent in the second direction Y, i.e., the semiconductor structure layer 23' is etched laterally by a small length, and the semiconductor structure layer 23' retained here is subsequently connected to the bit line 30; as shown in FIGS. 3A, 3B, and 3C. FIGS. 3A-3C are cross-sectional views along the AA' direction, the B1B1' direction, and the CC' direction, respectively, after the second hole K2 is formed according to some embodiments. The B1B1' direction is perpendicular to the substrate 1.

[0153] 3) Thinning the bit line region;

[0154] Deposition of a fifth insulating film to form a fifth insulating layer 15 covering the inner wall of the second lateral recess A2 and the second hole K2;

[0155] Based on the second hole K2, the second insulating layer 12 and the fifth insulating layer 15 are etched by wet etching to expose the sidewall of the first dummy layer 91;

[0156] The first dummy layer 91 is etched based on the second holes K2 by a wet etching method, and the length of the first dummy layer 91 along the second direction Y is thinned; the first dummy layer 91 is etched from two second holes K2 adjacent to the first hole K1, as shown in FIGS. 4A, 4B and 4C. FIGS. 4A to 4C are cross-sectional views of the bit line region along the AA' direction, the B1B1' direction and the CC' direction, respectively, provided by some embodiments. The region where the first dummy layer 91 is located is the bit line region, and the bit line will be formed in the region where the first dummy layer 91 is located and the region around the first dummy layer 91. The first dummy layer 91 is thinned, and the subsequently formed bit line 30 is correspondingly thinned. The scheme provided by the embodiment can increase the distance of the subsequently formed bit line 30 along the second direction Y by thinning the first dummy layer 91, thereby reducing the coupling between the bit lines and enhancing the device performance. When the first dummy layer 91 is thinned, the first dummy layer 91 can be thinned to a size along the second direction Y that is smaller than the size of the end surface of the semiconductor layer structure layer 23' in contact with the second insulating layer 12 along the second direction Y, so as to increase the distance of the subsequently formed bit line 30 along the second direction Y as much as possible.

[0157] 4) Forming a first trench T1;

[0158] Depositing a sixth insulating thin film and planarizing to form a sixth insulating layer 16, the sixth insulating layer 16 filling the second holes K2, the second lateral recesses A2 and the etched regions in the first holes K1 (i.e., the etched regions of the second insulating layer 12 and the first dummy layer 91);

[0159] Etching the stack structure in a direction perpendicular to the substrate 1 (the etching stops on the substrate 1) to form a first trench T1 penetrating through the stack structure, the first trench T1 extending along the second direction Y; a group of storage units is defined between two first trenches T1 spaced apart along the first direction X, and the group of storage units includes two columns of storage units;

[0160] Based on the first trench T1, the sacrificial layer 10 is removed by lateral etching to form a third lateral recess A3;

[0161] depositing a seventh insulating film, etching to remove the seventh insulating film in the first trench T1, to form a seventh insulating layer 17 filling the third lateral recess A3; at this time, the semiconductor structure layer 23' is exposed in the first trench T1, as shown in FIGS. 5A, 5B, 5C and 5D. FIGS. 5A-5C are cross-sectional views along the AA', B1B1', CC' and DD' directions of some embodiments after forming the first trench T1, respectively. Before depositing the seventh insulating film, the third insulating layer 13 exposed in the third lateral recess A3 can be etched to remove, i.e., the third insulating layer 13 of the bottom wall of the first lateral recess A1 is etched to remove. However, the embodiments of the present disclosure are not limited thereto, and the third insulating layer 13 can not be etched.

[0162] 5) forming a third hole K3;

[0163] depositing a first isolation layer film and planarizing, to form a first isolation layer 81 filling the first trench T1; the first isolation layer film can be, for example, SiN.

[0164] In the capacitor region, etching the stack structure from the top layer to the bottom layer in a direction perpendicular to the substrate 1 (stopping on the substrate 1), to form a plurality of third holes K3 spaced along the second direction Y; the third holes K3 and the first holes K1 can be spaced along the first direction X; wherein the aperture of the third hole K3 is larger than the aperture of the first hole K1;

[0165] Based on the third hole K3, laterally etching the semiconductor structure layer 23' to form a fourth lateral recess A4, which provides space for manufacturing a capacitor, i.e., provides space for the first capacitor electrode 41; and when laterally etching the semiconductor structure layer 23', the semiconductor structure layer 23' between the first trench T1 and the third hole K3 is not etched through, i.e., after laterally etching the semiconductor structure layer 23', the first trench T1 and the third hole K3 are not connected;

[0166] sequentially depositing an eighth insulating film and a second dummy layer film and then planarizing, to form an eighth insulating layer 18 (i.e., a third barrier layer) covering the inner walls of the fourth lateral recess A4 and the third hole K3, and a second dummy layer 92 filling the fourth lateral recess A4 and the third hole K3; at this time, the second dummy layer 92 and the first isolation layer 81 are flush;

[0167] Etching the first dummy layer 91 and the second dummy layer 92 such that the distance between the surface of the substrate 1 and the first dummy layer 91 and the second dummy layer 92 is less than the distance between the surface of the substrate 1 and the first isolation layer 81. That is, a portion of the top of the first dummy layer 91 and the second dummy layer 92 is etched to form a recess relative to the first isolation layer 81; as shown in FIGS. 6A, 6B, 6C, and 6D. FIGS. 6A-6D are cross-sectional views along the AA' direction, the BB' direction, the CC' direction, and the DD' direction, respectively, after forming the third hole K3 according to some embodiments.

[0168] 6) Forming the second isolation layer 82;

[0169] Depositing a ninth insulating film and planarizing to form a ninth insulating layer 19, the ninth insulating layer 19 covering the top of the first dummy layer 91 and the second dummy layer 92 and serving as a protective structure, the ninth insulating layer 19 being flush with the first isolation layer 81.

[0170] Etching to remove the first isolation layer 81 in the first trench T1;

[0171] Based on the first trench T1, etching the semiconductor structure layer 23' laterally to form a fifth lateral recess A5 in the region between the third hole K3 and the second hole K2 and closer to the third hole K3; etching to remove the third insulating layer 13 exposed in the fifth lateral recess A5; avoiding the formation of a hollow in the fifth lateral recess A5 when etching the third insulating layer 13 in subsequent step 8).

[0172] Depositing a second isolation layer film, the second isolation layer film filling the fifth lateral recess A5 and the region where the third insulating layer 13 is etched away, and etching the second isolation layer film laterally to the side of the third hole K3 facing the first hole K1 to form a second isolation layer 82, the second isolation layer 82 being distributed on a portion of the outer sidewall of the eighth insulating layer 18 on the side facing the first hole K1 in the third hole K3 (i.e., the region not in contact with the semiconductor structure layer 23'), wherein the portion of the outer sidewall of the eighth insulating layer 18 on the side facing the first hole K1 is in contact with the semiconductor structure layer 23', and the second isolation layer 82 is distributed on both sides of the region where the eighth insulating layer 18 is in contact with the semiconductor structure layer 23' along the second direction Y, as shown in FIGS. 7A, 7B, 7C, 7D, and 7E. FIGS. 7A-7E are cross-sectional views along the AA' direction, the BB' direction, the B1B1' direction, the CC' direction, and the DD' direction, respectively, after forming the second isolation layer 82 according to some embodiments.

[0173] In some embodiments, the second isolation layer film can be SiN.

[0174] 7) Forming the first word line hole K41 and the second word line hole K42;

[0175] depositing a third dummy layer film, which fills the first trench T1 and a fifth lateral recess A5 formed with the second isolation layer 82, to form a third dummy layer 93;

[0176] etching the third dummy layer 93 so that the distance between the surface of the third dummy layer 93 facing away from the substrate 1 and the substrate 1 is less than the distance between the surface of the second dummy layer 92 facing away from the substrate 1 and the substrate 1;

[0177] depositing a tenth insulating film to form a tenth insulating layer 70; the tenth insulating layer 70 covers the structure formed as described above;

[0178] In the transistor region, the stack structure is etched from top to bottom along a direction perpendicular to the substrate 1 (the etching stops on the substrate 1) to form a plurality of first word line holes K41 spaced apart along the second direction Y and a plurality of second word line holes K42 spaced apart along the second direction Y, the first word line holes K41 and the second word line holes K42 being spaced apart along the first direction X; a first word line hole K41 is arranged between adjacent third holes K3, and the region where each second hole K2 is located is provided with two second word line holes K42 spaced apart along the first direction X; part of the sidewall of the first word line hole K41 exposes the second isolation layer 82, and part of the sidewall exposes the semiconductor structure layer 23'; part of the sidewall of the second word line hole K42 exposes the sixth insulating layer 16 filled in the second hole K2, and part of the sidewall exposes the semiconductor structure layer 23', as shown in FIGS. 8A, 8B, 8C and 8D. FIGS. 8A to 8D are cross-sectional views along the AA' direction, the BB' direction, the DD' direction and the EE' direction, respectively, after the formation of the first word line hole K41 and the second word line hole K42 according to some embodiments. The EE' direction is perpendicular to the substrate 1.

[0179] The scheme provided in this embodiment forms the first word line hole K41 in the transistor region, rather than between the third holes K3 adjacent along the second direction Y, which can shorten the distance between the capacitors adjacent along the second direction Y and reduce the device area.

[0180] 8) forming a semiconductor layer 23;

[0181] Based on the lateral etching of the semiconductor structure layer 23' by the first word line hole K41 and the second word line hole K42, a channel is formed to connect the first word line hole K41 and the second word line hole K42 adjacent along the first direction X, so as to segment the semiconductor structure layer 23' to disconnect the semiconductor structure layer 23' into a plurality of independent parts distributed along the second direction Y, i.e., a plurality of semiconductor layers 23 of a plurality of transistors are formed;

[0182] Wet etching the third insulating layer 13, so that the semiconductor layer 23 presents a suspended structure; that is, etching to remove the third insulating layer 13 on the side of the semiconductor layer 23 facing the substrate 1 and the side of the semiconductor layer 23 facing away from the substrate 1; at this time, the side surfaces of the semiconductor layer 23 (including the surface on the side facing the substrate 1, the surface on the side facing away from the substrate 1, and the surface arranged opposite in the second direction Y) are all exposed;

[0183] Thinning the thickness of the semiconductor layer 23 in the direction perpendicular to the substrate 1; and the thinning can be performed simultaneously from the side of the semiconductor layer 23 facing the substrate 1 and the side of the semiconductor layer 23 facing away from the substrate 1; the semiconductor layer 23 can be thinned by wet etching to meet the channel layer thickness requirement of the transistor; since the capacitor structure is formed in the layer where the semiconductor structure layer 23' is initially formed, when the semiconductor structure layer 23' is initially grown, the thickness cannot be too small, and the thickness is greater than the channel layer thickness requirement of the transistor, so the semiconductor layer 23 is thinned here to meet the channel layer thickness requirement of the transistor, and in addition, the semiconductor layer 23 is thinned to leave space for the subsequent formation of the word line 40.

[0184] Etching to remove the second isolation layer 82, as shown in FIGS. 9A, 9B, 9C, and 9D. FIGS. 9A-9D are cross-sectional views along the AA' direction, the BB' direction, the DD' direction, and the EE' direction, respectively, after forming the semiconductor layer 23 according to some embodiments.

[0185] 9) Forming the word line 40;

[0186] Performing high-temperature thermal oxidation treatment on the semiconductor layer 23, so that the exposed surface of the semiconductor layer 23 forms a semiconductor oxide, which serves as the gate insulating layer 24; for example, the semiconductor oxide is SiO2; before performing the high-temperature thermal oxidation treatment, the channel region of the semiconductor layer 23 can be doped according to the doping requirement of the channel region of the transistor.

[0187] Depositing a first conductive thin film to form a word line 40 extending in the second direction Y around a plurality of semiconductor layers 23 of a column of transistors; as shown in FIGS. 10A, 10B, 10C, and 10D. FIGS. 10A-10D are cross-sectional views along the AA' direction, the BB' direction, the DD' direction, and the EE' direction, respectively, after forming the word line 40 according to some embodiments. The first conductive thin film is distributed on the sidewalls of the first word line hole K41 and the second word line hole K42 in addition to surrounding the semiconductor layer 23.

[0188] In some embodiments, the depositing the first conductive thin film can include sequentially depositing a first sub-conductive thin film and a second sub-conductive thin film, and the word line 40 can include a first sub-layer 31 and a second sub-layer 32, the first sub-layer 31 can be a conductive thin film with good adhesion, such as TiN, and the second sub-layer 32 can be a conductive material with low resistivity, such as tungsten.

[0189] In some embodiments, the first conductive thin film can be one or more of the following different types of materials:

[0190] For example, containing tungsten, aluminum, titanium, copper, nickel, platinum, ruthenium, molybdenum, gold, iridium, rhodium, tantalum, cobalt, etc. metal; can be a metal alloy containing the aforementioned metals;

[0191] Or, it can be a metal oxide, a metal nitride, a metal silicide, a metal carbide, etc., such as indium tin oxide (ITO), indium zinc oxide (IZO), indium oxide (InO), aluminum-doped zinc oxide (AZO), etc. metal oxide material with high conductivity; for example, titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN), etc. metal nitride material;

[0192] Or, it can be a polysilicon material, a conductive doped semiconductor material, etc., such as conductively doped silicon, conductively doped germanium, conductively doped silicon germanium, etc.; other materials that exhibit conductivity, etc.

[0193] The materials of the subsequent second conductive thin film to the fifth conductive thin film are similar to the first conductive thin film, and will not be repeated here.

[0194] 10) disconnect the word lines 40 of different layers;

[0195] Etching to remove the first conductive thin film on the sidewalls of the first word line hole K41 and the second word line hole K42, and retaining the first conductive thin film in the channel; at this time, the word lines 40 of different layers are disconnected;

[0196] Depositing an eleventh insulating thin film and polishing to form an eleventh insulating layer 71, the eleventh insulating layer 71 fills the first word line hole K41 and the second word line hole K42, and the surface of the side away from the substrate 1 of the eleventh insulating layer 71 is flush with the second dummy layer 92; as shown in FIGS. 11A, 11B, 11C, and 11D. FIGS. 11A-11D are cross-sectional views of the rear AA' direction, BB' direction, DD' direction, and FF' direction of the word lines 40 of different layers after being disconnected according to some embodiments. The subsequent FF' cross-sectional transistor structure is basically unchanged, and is omitted.

[0197] 11) expose the first hole K1 and the third hole K3;

[0198] etching to remove the first dummy layer 91 and the second dummy layer 92; that is, etching to remove the dummy layers (including the first dummy layer 91 and the second dummy layer 92) in the first hole K1 and the third hole K3;

[0199] etching to remove the eighth insulating layer 18 of the inner wall of the fourth lateral recess A4 and the third hole K3, so as to expose the semiconductor layer 23 and the word line 40 on the sidewall of the third hole K3, and etching to remove the second insulating layer 12 of the inner wall of the first hole K1, so as to expose the semiconductor layer 23 and the word line 40 on the sidewall of the first hole K1; facilitating the connection between the first capacitor electrode 41 and the bit line 30 and the semiconductor layer 23 formed subsequently, as shown in FIGS. 12A, 12B and 12C. FIGS. 12A to 12C are cross-sectional views of the back direction AA', BB' and DD' of the exposed first hole K1 and third hole K3 provided by some embodiments, respectively. At this time, the sixth insulating layer 16 in contact with the first dummy layer 91 is etched away in part. The currently exposed first hole K1 is only a part of the initial first hole K1, referred to as a bit line hole K1'. When etching the second insulating layer 12, the region of the sixth insulating layer 16 in contact with the first dummy layer 91 is etched away, so that the end surface of the semiconductor layer 23 on the side of the first hole K1 is exposed in the first hole K1, and the contact area between the semiconductor layer 23 and the subsequently formed bit line 30 is increased as much as possible.

[0200] 12) etching to remove the word line 40 in the non-channel region;

[0201] based on the bit line hole K1' and the third hole K3, etching the word line 40 laterally, retaining the word line 40 around the channel region of the semiconductor layer 23, and removing the word line 40 outside the channel region of the semiconductor layer 23, which can be located between the first word line hole K41 and the second word line hole K42 adjacent to each other in the same transistor region, that is, in the middle of the transistor region;

[0202] depositing a twelfth insulating thin film, etching to remove the twelfth insulating thin film in the bit line hole K1' sidewall, the third hole K3 sidewall and the fourth lateral recess A4, forming a twelfth insulating layer 72 filling the region where the word line 40 is etched away, at this time, the semiconductor layer 23 is exposed in the fourth lateral recess A4, and the semiconductor layer 23 is exposed in the bit line hole K1', as shown in FIGS. 13A, 13B and 13C. FIGS. 13A to 13C are cross-sectional views of the back direction AA', BB' and DD' of the etched non-channel region of the word line 40 provided by some embodiments, respectively.

[0203] 13) forming a connection layer 25;

[0204] The surface of the semiconductor layer 23 exposed in the first hole K1 and the fourth lateral recess A4 is subjected to a metal silicide treatment to form a connection layer 25, as shown in FIG. 14A, FIG. 14B, and FIG. 14C. FIG. 14A to FIG. 14C are cross-sectional views of the connection layer 25 along the AA' direction, the BB' direction, and the DD' direction, respectively, after the connection layer 25 is formed in some embodiments. In addition, when the third dummy layer 93 exposed in the fourth lateral recess A4 is polysilicon, a metal silicide is also formed on the surface of the third dummy layer 93 exposed in the fourth lateral recess A4. The connection layer 25 includes three parts, a first connection sub-layer 251 and a second connection sub-layer 252 formed by the semiconductor layer 23, and a third connection sub-layer 253 formed by the third dummy layer 93. The semiconductor layer 23 includes a channel region surrounded by the word line 40 and a source region and a drain region located at the two ends of the channel region, respectively. Before the metal silicide treatment, the source region and the drain region of the semiconductor layer 23 can be doped according to the doping requirements of the source region and the drain region of the semiconductor layer 23. The scheme provided in this embodiment can simultaneously realize the doping of the source region and the drain region, simplifying the process. The connection layer 25 can be a metal silicide, such as titanium (Ti), cobalt (Co), nickel (Ni), or nickel-platinum (NiPt) silicide, i.e., titanium silicide (TiSix), cobalt silicide (CoSix), and nickel-platinum silicide (NiPtSix), etc. The connection layer 25 can reduce the contact resistance between the subsequently formed electrode and the semiconductor layer 23. The first connection sub-layer 251 is connected to the subsequently formed bit line 30, and the second connection sub-layer 252 is connected to the first capacitor electrode 41. x x The connection layer 25 can reduce the contact resistance between the subsequently formed electrode and the semiconductor layer 23. The first connection sub-layer 251 is connected to the subsequently formed bit line 30, and the second connection sub-layer 252 is connected to the first capacitor electrode 41.

[0205] In some embodiments, the semiconductor layer 23 can be silicon, the connection layer 25 can be TiSix x , and the metal silicide treatment can include:

[0206] depositing a titanium thin film;

[0207] performing high-temperature heat treatment to cause the titanium thin film to react with the semiconductor layer 23 to form TiSix x ;

[0208] etching to remove the titanium thin film.

[0209] The scheme provided in this embodiment can simultaneously form the connection layer 25 at the two ends of the semiconductor layer 23, which simplifies the process and reduces the cost compared to the scheme of forming the connection layer 25 at the two ends of the semiconductor layer 23, respectively.

[0210] 14) forming a first conductive sub-layer 301 of the first capacitor electrode 41 and the bit line 30;

[0211] ​depositing a second conductive film covering the inner wall of the first hole K1, the inner wall of the third hole K3 and the inner wall of the fourth lateral recess A4, the second conductive film covering the inner wall of the first hole K1 is a first conductive sub-layer 301 forming a bit line 30;

[0212] depositing a fourth dummy layer film to form a fourth dummy layer 94, since the aperture of the third hole K3 is larger than the aperture of the first hole K1, the fourth dummy layer 94 can fill the bit line hole K1’ and not completely fill the third hole K3, i.e. the third hole K3 is hollow;

[0213] etching to remove the fourth dummy layer 94 on the sidewall of the third hole K3 to expose the second conductive film on the sidewall of the third hole K3; at this time, the fourth dummy layer 94 on the top of the bit line hole K1’ is etched away.

[0214] etching to remove the second conductive film on the sidewall of the third hole K3, leaving the second conductive film in the fourth lateral recess A4, at this time, the second conductive films of different layers are disconnected, and the second conductive film in the fourth lateral recess A4 is a first capacitor electrode 41; as shown in FIGS. 15A, 15B and 15C. FIGS. 15A to 15C are respectively cross-sectional views of the back along the AA’ direction, the BB’ direction and the DD’ direction after forming the first capacitor electrode 41 and the first conductive sub-layer 301 according to some embodiments.

[0215] 15) forming a first dielectric layer 431 and a first sub-electrode 421;

[0216] etching to remove the fourth dummy layer 94 in the third hole K3;

[0217] etching the seventh insulating layer 17 to expose the first capacitor electrode 41 towards the substrate 1 side and away from the substrate 1 side, forming a sixth lateral recess A6,

[0218] depositing a first dielectric film and a third conductive film in sequence to form a first dielectric layer 431 and a first sub-electrode 421; the first dielectric layer 431 covers the inner wall of the first capacitor electrode 41, and the inner wall of the sixth lateral recess A6(including the outer sidewall of the first capacitor electrode 41 towards the substrate 1 side, and the outer sidewall of the first capacitor electrode 41 away from the substrate 1 side); the first sub-electrode 421 fills the third hole K3, the fourth lateral recess A4 and the sixth lateral recess A6; as shown in FIGS. 16A, 16B and 16C. FIGS. 16A to 16C are respectively cross-sectional views of the back along the AA’ direction, the BB’ direction and the DD’ direction after forming the first dielectric layer 431 and the first sub-electrode 421 according to some embodiments.

[0219] In some embodiments, the first sub-electrode 421 can include a third sub-layer 33 and a fourth sub-layer 34. The third sub-layer 33 can be a conductive thin film with good adhesion, such as TiN, and the fourth sub-layer 34 can be a conductive material with low resistivity, such as tungsten. The third sub-layer 33 is distributed on the bottom wall and the inner side wall of the first capacitor electrode 41, as well as the outer side wall facing the substrate 1 and the outer side wall facing away from the substrate 1. The fourth sub-layer 34 fills the third hole K3, the fourth lateral groove A4, and the sixth lateral groove A6.

[0220] In some embodiments, the first dielectric thin film can be a High-K dielectric material. In some embodiments, it can include one or more oxides of hafnium, aluminum, lanthanum, zirconium, etc. Exemplary High-K materials can include, but are not limited to, at least one of hafnium oxide (HfO2), aluminum oxide (Al2O3), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), zirconium oxide (ZrO2), etc. The subsequent second dielectric thin film is similar to the first dielectric thin film and will not be described again.

[0221] 16) Forming a thirteenth insulating layer 73;

[0222] Etching the first sub-electrode 421 so that the first sub-electrode 421 at the top of the third hole K3 is etched away;

[0223] Depositing a thirteenth insulating thin film to form a thirteenth insulating layer 73, which is arranged in and fills the third hole K3. The thirteenth insulating layer 73 serves as a protective structure for the first sub-electrode 421. As shown in FIGS. 17A and 17B, which are cross-sectional views along the BB' direction and the DD' direction, respectively, after forming the thirteenth insulating layer 73 in some embodiments.

[0224] 17) Forming a second conductive sub-layer 302 of the bit line 30;

[0225] Etching to remove the fourth dummy layer 94 in the first hole K1;

[0226] Depositing a fourth conductive thin film to fill the first hole K1 and planarizing to form a second conductive sub-layer 302 of the bit line 30. As shown in FIGS. 18A and 18B, which are cross-sectional views along the AA' direction and the BB' direction, respectively, after forming the second conductive sub-layer 302 in some embodiments. The first conductive sub-layer 301 and the second conductive sub-layer 302 constitute the bit line 30.

[0227] The scheme provided in this embodiment simplifies the process and saves costs without the need for re-photolithography when forming the bit line 30.

[0228] 18) Forming a fourteenth insulating layer 74;

[0229] Etching the bit line 30 so that the bit line 30 on top of the bit line hole K1' is etched off;

[0230] Depositing a fourteenth insulating thin film and planarizing to form a fourteenth insulating layer 74, the fourteenth insulating layer 74 is arranged in the bit line hole K1' to fill the bit line hole K1'; the fourteenth insulating layer 74 serves as a protective structure on top of the bit line 30, and the fourteenth insulating layer 74 is flush with the third dummy layer 93 in the first trench T1. As shown in FIG. 19, which is a cross-sectional view along the direction of BB' after forming the fourteenth insulating layer 74 according to some embodiments. During planarization, a portion of the thirteenth insulating layer 73 is etched off to be flush with the third dummy layer 93.

[0231] 19) forming a second dielectric layer 432;

[0232] Etching to remove the third dummy layer 93;

[0233] Etching to remove the connection layer 25 (i.e. the third connection sub-layer 253) distributed on the outer bottom wall of the first capacitor electrode 41 exposed in the fifth lateral recess A5 to expose the first capacitor electrode 41;

[0234] Depositing a second dielectric thin film to form a second dielectric layer 432; the second dielectric layer 432 covers the inner walls of the first trench T1 and the fifth lateral recess A5; as shown in FIGS. 20A, 20B, and 20C, which are cross-sectional views along the directions of AA', BB', and DD' respectively after forming the second dielectric layer 432 according to some embodiments.

[0235] 20) forming a second sub-electrode 422;

[0236] Depositing a fifth conductive thin film to fill the first trench T1 and the fifth lateral recess A5 and planarizing to form a second sub-electrode 422; the second sub-electrode 422, the bit line 30, and the first sub-electrode 421 are exposed on the side away from the substrate 1, as shown in FIGS. 1A, 1B, 1C, and 1D.

[0237] In some embodiments, the second sub-electrode 422 can include a fifth sub-layer 35 and a sixth sub-layer 36; the fifth sub-layer 35 can be a conductive thin film with good adhesion, such as TiN, and the sixth sub-layer 36 can be a conductive material with low resistivity, such as tungsten. The fifth sub-layer 35 is distributed on the inner walls of the first trench T1 and the fifth lateral recess A5, and the sixth sub-layer 36 fills the first trench T1 and the fifth lateral recess A5.

[0238] The embodiments of the present disclosure further provide an electronic device including the semiconductor device of any of the preceding embodiments or the semiconductor device formed by the manufacturing method of any of the preceding embodiments. The electronic device can be a storage device, a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device, a mobile power supply, or the like. The storage device can include a memory in a computer, and the like, which is not limited herein.

[0239] Although the embodiments of the present disclosure are disclosed as above, the content described is only the embodiments adopted for the purpose of facilitating the understanding of the present disclosure, and is not intended to limit the present disclosure. Any person skilled in the art of the present disclosure can make any modification and change in the implementation form and details without departing from the spirit and scope of the present disclosure. The patent protection scope of the present disclosure shall be subject to the scope defined by the appended claims.

Claims

1. A semiconductor device comprising: a plurality of memory cell arrays stacked in a direction perpendicular to a substrate, the memory cell arrays including at least one column of a plurality of memory cells distributed in a second direction parallel to the substrate; a plurality of bit lines extending in the direction perpendicular to the substrate through the memory cells of the plurality of layers; a plurality of word lines distributed in different layers, the word lines and the bit lines being distributed in a first direction parallel to the substrate, the word lines extending in the second direction, the first and second directions intersecting; the memory cells including transistors including semiconductor layers extending in the first direction; the word lines surrounding a portion of side surfaces of a plurality of the semiconductor layers of the column of the memory cells; a dimension of the semiconductor layer in the second direction toward an end surface of the bit line being smaller than a smallest dimension of an area of the semiconductor layer surrounded by the word line, and a dimension of the semiconductor layer in the second direction away from the end surface of the bit line being smaller than the smallest dimension of the area of the semiconductor layer surrounded by the word line.

2. The semiconductor device of claim 1, wherein, of the semiconductor layer, each of the side surfaces includes a first surface, a second surface, and a third surface distributed in the first direction in order, a portion of the first surface and the second surface being surrounded by the word line, the third surface being located between the area of the semiconductor layer surrounded by the word line and the end surface of the semiconductor layer toward the bit line, and a junction of the first surface and the second surface being convex toward an adjacent semiconductor layer in the second direction.

3. The semiconductor device of claim 2, wherein, a junction of the second surface and the third surface being convex toward an adjacent semiconductor layer in the second direction.

4. The semiconductor device of claim 1, wherein, two side surfaces of the word line located between adjacent semiconductor layers in the second direction and opposite in the first direction form an arc-shaped recess.

5. The semiconductor device of claim 1, wherein, a cross section of the bit line parallel to the substrate has a dimension in the second direction smaller than a dimension in the first direction.

6. The semiconductor device of claim 2, wherein, a gate insulating layer is provided between the semiconductor layer and the word line, the gate insulating layer surrounding the semiconductor layer, and on two side surfaces of the semiconductor layer opposite in the second direction, the gate insulating layer being distributed on the first surface, the second surface, and not being distributed on the third surface.

7. The semiconductor device of claim 6, wherein, the gate insulating layer continuously extends on a surface of the semiconductor layer away from the substrate and a surface of the semiconductor layer toward the substrate.

8. The semiconductor device of claim 6, wherein, the semiconductor layer includes single crystal silicon, and the gate insulating layer is silicon oxide formed by oxidizing the single crystal silicon.

9. The semiconductor device of claim 8, wherein, the semiconductor device further includes a first connection sublayer connected to an end surface of the semiconductor layer toward the bit line, and a second connection sublayer connected to an end surface of the semiconductor layer away from the bit line, the first connection sublayer and the second connection sublayer being metal silicide formed by metal silicidizing the single crystal silicon, and the first connection sublayer being connected to the bit line.

10. The semiconductor device of claim 9, wherein, The memory cell further comprises a capacitor comprising a first capacitor electrode and a second capacitor electrode, the second capacitor electrode comprising a first sub-electrode, the semiconductor device further comprises a capacitor hole penetrating through the plurality of layers of the memory cell, a plurality of first capacitor electrodes of a plurality of memory cells at the same position of different layers are disposed on the sidewall of the capacitor hole and are spaced apart in a direction perpendicular to the substrate, the first sub-electrode fills the capacitor hole, and a plurality of the first capacitor electrodes surround the first sub-electrode through a first dielectric layer.

11. The semiconductor device of claim 10, wherein, The capacitor hole exposes a plurality of second connection sub-layers respectively connected to a plurality of semiconductor layers of a plurality of memory cells stacked in a direction perpendicular to the substrate, and the first capacitor electrode is connected to the exposed second connection sub-layers.

12. The semiconductor device of claim 10, wherein, The first capacitor electrode comprises a first part extending in a direction perpendicular to the substrate and a second part extending from both ends of the first part towards the first sub-electrode, respectively; the first part is connected to the second connection sub-layers.

13. The semiconductor device of claim 12, wherein, The second capacitor electrode further comprises a second sub-electrode, and the second sub-electrode surrounds the first part through a second dielectric layer.

14. The semiconductor device of claim 10, wherein, The distance between the surface away from the substrate and the surface towards the substrate of the word line is equal to the length of the first capacitor electrode extending in a direction perpendicular to the substrate.

15. The semiconductor device according to any one of claims 10 to 14, wherein The semiconductor device further comprises a first isolation hole penetrating through the plurality of layers of the memory cell array and an insulating film layer filling the first isolation hole, which are disposed between semiconductor layers adjacent in a second direction, between a column of capacitors distributed in the second direction and the word line; and a second isolation hole penetrating through the plurality of layers of the memory cell array and an insulating film layer filling the second isolation hole, which are disposed between bit lines adjacent in the second direction, between the word lines adjacent in the first direction.

16. A semiconductor device manufacturing method, comprising: forming a stack structure comprising a plurality of alternating semiconductor structure layers and sacrificial layers on a substrate; forming a plurality of first holes spaced apart in a second direction penetrating through the stack structure in a direction perpendicular to the substrate; forming a second hole penetrating through the stack structure in a direction perpendicular to the substrate between adjacent first holes, and the aperture of the second hole in a first direction is larger than the aperture of the first hole in the first direction; the first direction and the second direction are parallel to the substrate and intersect; laterally etching the semiconductor structure layers based on the second hole, so that the second hole intersects the first hole, and the semiconductor structure layers are retained between second holes adjacent in the second direction; forming a first trench penetrating through the stack structure and extending in the second direction; forming a plurality of third holes penetrating through the stack structure in a direction perpendicular to the substrate and spaced apart in the second direction between the first trench and the first hole, and a plurality of transistor regions are defined between a plurality of the third holes and a plurality of the first holes; etching the semiconductor structure layer along a direction parallel to the substrate based on the first trench to remove the semiconductor structure layer outside the transistor region and part of the semiconductor structure layer of the transistor region, and the remaining semiconductor structure layer in the transistor region is connected to part of the sidewall of the third hole on the side of the first hole, forming a fifth lateral groove; forming, in the transistor region, a plurality of first word line holes spaced along a second direction and penetrating the stack structure along a direction perpendicular to the substrate, and a plurality of second word line holes spaced along the second direction and penetrating the stack structure along the direction perpendicular to the substrate, the sidewalls of the first word line holes and the second word line holes exposing each layer of the semiconductor structure layer; the first word line holes and the second word line holes are spaced along a first direction, and the second word line holes are located in the region where the second hole is located; etching the semiconductor structure layer along a direction parallel to the substrate based on the first word line hole and the second word line hole to form a channel that connects the first word line hole and the second word line hole adjacent along the first direction, so as to divide the semiconductor structure layer to form a plurality of semiconductor layers of a corresponding plurality of transistors extending along the first direction and spaced along the second direction; forming, in sequence, a gate insulating layer surrounding the semiconductor layer, and a word line surrounding part of the side surface of the plurality of semiconductor layers of a column of transistors distributed along the second direction; forming a bit line extending along a direction perpendicular to the substrate in the first hole. Before forming the first word line hole and the second word line hole, further comprising:

17. The method of manufacturing a semiconductor device according to claim 16, wherein depositing an isolation layer film filling the fifth lateral groove, and etching the isolation layer film to the side of the third hole on the side of the first hole outside the transistor region to form an isolation layer extending along the second direction and distributed in the region of the third hole on the side of the first hole which does not contact the semiconductor layer; wherein the sidewall of the first word line hole exposes the isolation layer.

18. The semiconductor device manufacturing method of claim 17, wherein, Before laterally etching the semiconductor structure layer based on the second hole, further comprising: etching the sacrificial layer of a preset length along a direction parallel to the substrate based on the second hole, and sequentially forming a first barrier layer covering the inner wall of the region where the etched sacrificial layer is located and an insulating layer filling the region where the etched sacrificial layer is located in the region where the etched sacrificial layer is located; After forming the plurality of semiconductor layers of the corresponding plurality of transistors extending along the first direction and spaced along the second direction, and before sequentially forming the gate insulating layer surrounding the semiconductor layer, further comprising: etching to remove the first barrier layer so that the semiconductor layer forms a suspended structure with an exposed side surface, and thinning the thickness of the semiconductor layer along a direction perpendicular to the substrate; the sequentially forming the gate insulating layer surrounding the semiconductor layer, and the word line surrounding part of the side surface of the plurality of semiconductor layers of a column of transistors distributed along the second direction comprises: performing oxidation treatment on the exposed side surface of the semiconductor layer to form the gate insulating layer; forming a word line filling the channel and the gap left after the semiconductor layer is thinned; ​ etching the word line based on the first hole and the third hole, and retaining the word line around the channel region of the semiconductor layer.

19. The method of manufacturing a semiconductor device according to Claim 18, wherein after etching the word line based on the first hole and the third hole, and retaining the word line around the channel region of the semiconductor layer, further comprising, forming a first connection sub-layer disposed on the semiconductor layer near the first hole and a second connection sub-layer disposed on the semiconductor layer near the third hole by performing a metal silicidation process on the semiconductor layer near the first hole and the semiconductor layer near the third hole.

20. The method of manufacturing a semiconductor device according to Claim 19, wherein before forming the first trench extending through the stack structure and along the second direction, further comprising: forming a second blocking layer covering sidewalls of the first hole and a first dummy layer filling the first hole; etching the second blocking layer towards two sidewalls of a second hole adjacent along the second direction to expose sidewalls of the first dummy layer and thinning the first dummy layer along the second direction; the forming the bit line extending along a direction perpendicular to the substrate direction in the first hole comprises: etching to remove the first dummy layer and the second blocking layer to form a bit line hole and forming a bit line filling the bit line hole.

21. The method of manufacturing a semiconductor device according to Claim 20, wherein before etching the word line based on the first hole and the third hole, further comprising: forming a fourth lateral recess by etching the semiconductor structure layer along a direction parallel to the substrate direction based on the third hole; forming a third blocking layer covering inner walls of the fourth lateral recess and the third hole and a second dummy layer filling the third hole and the fourth lateral recess; etching to remove the second dummy layer simultaneously with etching to remove the first dummy layer and etching to remove the third blocking layer simultaneously with etching to remove the second blocking layer; after forming the first connection sub-layer disposed on the semiconductor layer near the first hole and the second connection sub-layer disposed on the semiconductor layer near the third hole, further comprising: depositing a first conductive film covering the third hole and inner walls of the fourth lateral recess, etching to remove the first conductive film on sidewalls of the third hole, and retaining the conductive film on the inner walls of the fourth lateral recess to form a first capacitor electrode; the forming the bit line filling the bit line hole comprises depositing a first conductive film covering inner walls of the bit line hole simultaneously with depositing the first conductive film covering the third hole and the inner walls of the fourth lateral recess to form a first conductive sub-layer of the bit line; depositing a second conductive film filling the bit line hole to form a second conductive sub-layer of the bit line in the bit line hole formed with the first conductive film.

22. An electronic device comprising the semiconductor device of any one of claims 1 to 15 or the semiconductor device formed according to the manufacturing method of any one of claims 16 to 21.

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