Semiconductor device and manufacturing method therefor, and electronic device

Abstract

A semiconductor device and a manufacturing method therefor, and an electronic device. The semiconductor device comprises: a plurality of memory cell arrays stacked in a direction perpendicular to a substrate, each memory cell array comprising at least one column of a plurality of memory cells distributed in a second direction parallel to the substrate (1); a plurality of bit lines (30), the bit lines (30) passing through the memory cells in different layers and extending in the direction perpendicular to the substrate (1), and the plurality of memory cells in the same layer and in the same column being respectively connected to the plurality of bit lines (30) distributed at intervals in the second direction; and a plurality of word lines (40) extending in the second direction, the word lines (40) and the bit lines (30) being distributed in the first direction, the first direction and the second direction being both parallel to the substrate and intersecting, but not being perpendicular to each other, wherein semiconductor layers (23) of transistors of the memory cells surround the word lines (40), and the semiconductor layers (23) of the memory cells in the same column are distributed at intervals in the second direction and surround the same word line (40).

Description

A semiconductor device, a manufacturing method thereof, and an electronic device

[0001] The present application claims priority to the Chinese patent application No. 2024112485238, filed on September 5, 2024, and entitled "A semiconductor device, a manufacturing method thereof, and an electronic device", the content of which is to be understood as incorporated herein by reference. TECHNICAL FIELD

[0002] Embodiments of the present disclosure relate to, but are not limited to, device design and manufacturing thereof in the technical field of semiconductor technology, and in particular to a semiconductor device, a manufacturing method thereof, and an electronic device. BACKGROUND

[0003] With the development of integrated circuit technology, the critical dimension of devices is increasingly shrinking, and the types and number of devices contained in a single chip are increasing, so that any slight difference in process production can affect the performance of the device.

[0004] In order to reduce the cost of products as much as possible, people want to make as many device units as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet people's current product needs.

[0005] SUMMARY

[0006] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0007] The present application provides a semiconductor device, comprising:

[0008] a plurality of memory cell arrays stacked along a direction perpendicular to a substrate, the memory cell arrays comprising at least one column of a plurality of memory cells distributed along a second direction parallel to the substrate;

[0009] a plurality of bit lines extending along a direction perpendicular to the substrate through the memory cells of different layers; a plurality of memory cells in the same layer and column are respectively connected to a plurality of bit lines distributed along the second direction;

[0010] a plurality of word lines distributed in different layers, the word lines and the bit lines being distributed along a first direction, the word lines extending along the second direction; the first direction and the second direction are both parallel to the substrate, intersecting each other and not perpendicular;

[0011] the memory cells comprise transistors, the transistors comprising a semiconductor layer connected to the bit lines, the semiconductor layer surrounding the word lines, the semiconductor layers of memory cells in the same column being distributed along the second direction and surrounding the same word line.

[0012] In some embodiments, every two storage units adjacent along the first direction are connected to the same bit line;

[0013] A first isolation hole penetrating through the multi-layer storage units is arranged between the bit lines adjacent along the second direction and between the word lines adjacent along the first direction, the first isolation hole is filled with a first isolation layer of an integral structure, the first isolation hole exposes the side surface of the adjacent word lines, and the side surface of the adjacent bit lines.

[0014] In some embodiments, the storage unit further comprises a capacitor connected to the semiconductor layer, the capacitor is arranged on the side of the semiconductor layer away from the bit line, the capacitor is distributed along the first direction with the word line, and the plurality of capacitors connected to the plurality of storage units in the same column are distributed along the second direction.

[0015] In some embodiments, the capacitor comprises a first capacitor electrode and a second capacitor electrode, the second capacitor electrode comprises a first sub-electrode, and the semiconductor device further comprises a capacitor hole penetrating through the multi-layer storage units, a plurality of first capacitor electrodes of the plurality of storage units at the same position of different layers are arranged on the sidewall of the capacitor hole and are spaced apart along the direction perpendicular to the substrate, the first sub-electrode fills the capacitor hole, and the plurality of first capacitor electrodes surround the first sub-electrode through a first dielectric layer.

[0016] A second isolation hole penetrating through the multi-layer storage units is arranged between the capacitor holes adjacent along the second direction, the second isolation hole is filled with a second isolation layer of an integral structure, the second isolation hole exposes the first capacitor electrode in the adjacent capacitor hole and the side surface of the word line adjacent to the capacitor hole.

[0017] In some embodiments, the first isolation hole extends along the second direction, and the plurality of first isolation holes distributed between the bit lines in a column are sequentially staggered along the first direction.

[0018] In some embodiments, the second isolation hole extends along the second direction, and the plurality of second isolation holes distributed between the capacitor holes in a column are sequentially staggered along the first direction.

[0019] In some embodiments, the first capacitor electrode comprises a first part extending along the direction perpendicular to the substrate and a second part extending from both ends of the first part towards the first sub-electrode, respectively; the first part is connected to the semiconductor layer and the two second isolation layers adjacent to the capacitor hole.

[0020] In some embodiments, the second capacitor electrode further comprises a second sub-electrode, and the second sub-electrode surrounds the first part of the first capacitor electrode through a second dielectric layer.

[0021] In some embodiments, the transistor further comprises a gate insulating layer disposed between the semiconductor layer and the word line and surrounding the word line; the gate insulating layers of the plurality of transistors in the same layer and the same column are disconnected at the contact area of the first isolation layer and the word line surrounded by the plurality of gate insulating layers, and disconnected at the contact area of the second isolation layer and the word line surrounded by the plurality of gate insulating layers.

[0022] In some embodiments, the first isolation hole further exposes the side surface of the adjacent gate insulating layer, and exposes the end surface of the adjacent semiconductor layer.

[0023] In some embodiments, the second isolation hole further exposes the side surface of the adjacent gate insulating layer, and exposes the end surface of the adjacent semiconductor layer.

[0024] In some embodiments, the contact surface of the semiconductor layer and the first capacitor electrode, and the contact surface of the semiconductor layer and the bit line are misaligned in the first direction.

[0025] Embodiments of the present disclosure provide a semiconductor device manufacturing method, comprising:

[0026] forming a stack structure comprising a plurality of first insulating layers and a plurality of sacrificial layers alternately arranged on a substrate;

[0027] forming a plurality of bit line holes penetrating through the stack structure along a direction perpendicular to the substrate and spaced apart along a second direction;

[0028] forming a bit line extending along a direction perpendicular to the substrate within the bit line hole and filling the bit line hole;

[0029] forming a plurality of capacitor holes penetrating through the stack structure along a direction perpendicular to the substrate and spaced apart along a second direction, and the bit line hole and the capacitor hole are spaced apart along a first direction, based on etching the sacrificial layer along a direction parallel to the substrate, a first lateral recess is formed; a first capacitor electrode is formed distributed on the inner wall of the first lateral recess; the first direction and the second direction intersect and are not perpendicular;

[0030] forming a first isolation hole penetrating through the stack structure between the bit line holes adjacent along the second direction, the first isolation hole exposing the side surface of the adjacent bit line; and forming a second isolation hole penetrating through the stack structure between the capacitor holes adjacent along the second direction, the second isolation hole exposing the adjacent first capacitor electrode; the first isolation hole and the second isolation hole are spaced apart along the first direction;

[0031] etching to remove the sacrificial layer distributed between the first isolation hole and the second isolation hole, forming a channel extending along the second direction between the first isolation hole distributed between the adjacent insulating layers and the second isolation hole distributed along the second direction;

[0032] forming a word line extending along the second direction in the channel, and a plurality of semiconductor layers distributed along the second direction surrounding the word line.

[0033] In some embodiments, the forming a word line extending along the second direction in the channel, and a plurality of semiconductor layers distributed along the second direction surrounding the word line comprises:

[0034] sequentially depositing a semiconductor thin film, a gate insulating thin film, and a conductive thin film, the semiconductor thin film and the gate insulating thin film sequentially covering the inner wall of the first isolation hole, the second isolation hole, and the channel, and the conductive thin film filling the channel and not completely filling the first isolation hole and the second isolation hole;

[0035] etching to remove the semiconductor thin film, the gate insulating thin film, and the conductive thin film in the first isolation hole and the second isolation hole, and etching the semiconductor thin film along the direction parallel to the substrate based on the first isolation hole and the second isolation hole, so that the semiconductor thin film forms a plurality of semiconductor layers distributed along the second direction, the conductive thin film forms a word line extending along the second direction, and the gate insulating thin film forms a gate insulating layer.

[0036] In some embodiments, the method further comprises sequentially forming a first dielectric layer covering the inner wall of a capacitor hole in which the first capacitor electrode is formed, and a first sub-electrode filling the capacitor hole.

[0037] In some embodiments, the method further comprises,

[0038] forming a trench penetrating through the stack structure between two adjacent rows of capacitor holes on the side of the second isolation hole away from the bit line, the trench exposing the sacrificial layer of each layer;

[0039] etching to remove the sacrificial layer between the trench and the second isolation hole based on the trench, forming a second lateral groove, the trench and the second lateral groove exposing the surface of the first capacitor electrode on the side of the second isolation hole away from the bit line;

[0040] sequentially forming a second dielectric layer covering the inner wall of the trench and the second lateral groove, and a second sub-electrode filling the trench and the second lateral groove in the trench and the second lateral groove.

[0041] The electronic device includes the semiconductor device of any of the above embodiments, or is formed according to the manufacturing method of the semiconductor device of any of the above embodiments.

[0042] Other features and advantages of the present application will be set forth in the following specification, and in part will be apparent from the description, or can be learned by practice of the application. Other advantages of the application will be realized and attained by the methods and solutions particularly pointed out in the written description and claims hereof.

[0043] Other aspects can become apparent to those of ordinary skill in the art upon reading and understanding the detailed description and the accompanying drawings.

[0044] SUMMARY

[0045] The accompanying drawings are included to provide a further understanding of the application, and constitute a part of this specification, illustrate embodiments of the application, and are included to provide a further understanding of the application, and together with the description serve to explain the principles of the application.

[0046] FIG. 1A, FIG. 1B, FIG. 1C, FIG. 1D are cross-sectional views of the semiconductor device along AA', BB', CC', and DD' directions, respectively, according to some embodiments;

[0047] FIG. 2A, FIG. 2B, FIG. 2C, FIG. 2D are cross-sectional views of the semiconductor device along AA', BB', CC', and EE' directions, respectively, after forming a bit line, according to some embodiments;

[0048] FIG. 3A, FIG. 3B, FIG. 3C, FIG. 3D are cross-sectional views of the semiconductor device along AA', BB', CC', and EE' directions, respectively, after forming a first capacitor electrode, according to some embodiments;

[0049] FIG. 4A, FIG. 4B, FIG. 4C, FIG. 4D are cross-sectional views of the semiconductor device along AA', BB', CC', and DD' directions, respectively, after forming a second dummy layer, according to some embodiments;

[0050] FIG. 5A, FIG. 5B, FIG. 5C, FIG. 5D are cross-sectional views of the semiconductor device along AA', BB', CC', and DD' directions, respectively, after forming a third hole and a fourth hole, according to some embodiments;

[0051] FIG. 6A, FIG. 6B, FIG. 6C, FIG. 6D are cross-sectional views of the semiconductor device along AA', BB', CC', and DD' directions, respectively, after forming a first trench, according to some embodiments;

[0052] FIG. 7A, FIG. 7B, FIG. 7C, FIG. 7D are cross-sectional views of the semiconductor device along AA', BB', CC', and DD' directions, respectively, after forming a second dielectric layer and a second sub-electrode, according to some embodiments;

[0053] FIG. 8 is a cross-sectional view along the direction of CC' of a back side of a protective structure forming a second sub-electrode according to some embodiments;

[0054] FIGS. 9A, 9B, 9C, and 9D are cross-sectional views along the directions of AA', BB', CC', and DD', respectively, of etching away a sacrificial layer according to some embodiments;

[0055] FIGS. 10A, 10B, 10C, and 10D are cross-sectional views along the directions of AA', BB', CC', and DD', respectively, of forming a semiconductor layer, a gate insulating layer, and a word line according to some embodiments;

[0056] FIGS. 11A, 11B, 11C, and 11D are cross-sectional views along the directions of AA', BB', CC', and DD', respectively, of disconnecting a plurality of semiconductor layers and a plurality of word lines according to some embodiments;

[0057] FIGS. 12A, 12B, 12C, and 12D are cross-sectional views along the directions of AA', BB', CC', and DD', respectively, of exposing a second initial hole according to some embodiments.

[0058] DETAILED DESCRIPTION

[0059] The embodiments of the present disclosure will be described in detail hereinafter with reference to the drawings. The features of the embodiments of the present disclosure and the embodiments can be combined with each other as long as they do not conflict with each other.

[0060] Unless otherwise defined, technical terms or scientific terms used in the present disclosure shall have the ordinary meaning understood by a person of ordinary skill in the art to which the present disclosure pertains.

[0061] The embodiments of the present disclosure are not necessarily limited to the shapes or values shown in the drawings, and the shapes and sizes of the components in the drawings do not reflect true proportions. Furthermore, the drawings schematically show ideal examples, and the embodiments of the present disclosure are not limited to the shapes or values shown in the drawings.

[0062] The ordinal numbers "first", "second", "third", and so on in the present disclosure are used to distinguish the components from each other, and do not mean any order, quantity, or importance.

[0063] In the present disclosure, the words of "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like indicating the positional or locational relationship are used to refer to the positional relationship of the components with reference to the drawings for the purpose of convenience and simplicity of the description and the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present disclosure. The positional relationship of the components is appropriately changed according to the direction in which each component is described. Therefore, it is not limited to the words described in the disclosure, and can be appropriately replaced according to the situation.

[0064] In the present disclosure, unless explicitly specified and limited otherwise, the terms "mount", "connect", and "connect" should be broadly understood. For example, it can be a physical connection or a signal connection, it can be a contact connection or an integral connection; it can be directly connected, or indirectly connected through an intermediate, or communication within two elements. For those skilled in the art, the specific meaning of the above terms in the present disclosure can be understood according to the specific circumstances.

[0065] In the present disclosure, a transistor refers to an element including at least a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In the present disclosure, the channel region refers to the region through which current mainly flows.

[0066] In the present disclosure, it can be that the first electrode is the drain electrode and the second electrode is the source electrode, or it can be that the first electrode is the source electrode and the second electrode is the drain electrode. In the case of using a transistor with opposite polarity or in the case of changing the current direction in the circuit operation, the functions of "source electrode" and "drain electrode" are sometimes exchanged with each other. Therefore, in the present disclosure, "source electrode" and "drain electrode" can be exchanged with each other.

[0067] In the present disclosure, "connection" includes the case where the components are connected together through an element having a certain electrical effect. The "element having a certain electrical effect" is not particularly limited as long as it can perform the transmission of electrical signals between the connected components. Examples of the "element having a certain electrical effect" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, other elements having various functions, and the like.

[0068] In the present disclosure, "parallel" means approximately parallel or almost parallel, for example, a state in which the angle formed by two straight lines is -10° or more and 10° or less, and thus, a state in which the angle is -5° or more and 5° or less is also included. In addition, "perpendicular" means approximately perpendicular, for example, a state in which the angle formed by two straight lines is 80° or more and 100° or less, and thus, a state in which the angle is 85° or more and 95° or less is also included.

[0069] In the present disclosure, "A and B are in an integral structure" can mean that there is no obvious fault or gap, or an obvious boundary interface in a microstructure. Generally, a film layer patterned to form a connected film layer is integral. For example, A and B use the same material to form a film layer and are simultaneously formed into a structure having a connection relationship by the same patterning process.

[0070] In the present disclosure, "the orthographic projection of B is located within the range of the orthographic projection of A" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps the boundary of the orthographic projection of B.

[0071] FIG. 1A is a cross-sectional view of a semiconductor device along the AA' direction parallel to the substrate 1 according to some embodiments, FIG. 1B is a cross-sectional view of a semiconductor device along the BB' direction parallel to the substrate 1 according to some embodiments, FIG. 1C is a cross-sectional view along the CC' direction perpendicular to the substrate 1 in FIG. 1A, and FIG. 1D is a cross-sectional view along the DD' direction perpendicular to the substrate 1 in FIG. 1A. As shown in FIGS. 1A to 1D, the present disclosure provides a semiconductor device including a multilayer memory cell array and a plurality of bit lines 30 vertically stacked on a substrate 1. The memory cell array can include at least one column of a plurality of memory cells distributed along a second direction Y parallel to the substrate 1, and a plurality of word lines 40. The plurality of word lines 40 can be distributed in different layers.

[0072] In some embodiments, each layer of the memory cell array can include a plurality of memory cells arrayed along a first direction X and a second direction Y parallel to the substrate 1. The first direction X and the second direction Y can intersect and not be perpendicular.

[0073] In some embodiments, the included angle of the first direction X and the second direction Y is, for example, 30° to 60°.

[0074] The bit lines 30 can extend through the memory cells of different layers in a direction perpendicular to the substrate 1. The memory cells of different layers at the same position stacked in a direction perpendicular to the substrate 1 are connected to the same bit line 30. The memory cells of the same column distributed along the second direction Y are connected to the bit lines 30 distributed along the second direction Y at intervals. In the embodiment, the bit lines 30 are arranged along the second direction Y which is not perpendicular to the first direction X, so that the bit lines 30 are staggered in a direction perpendicular to the first direction X. Compared with the arrangement in which the bit lines 30 are arranged along a direction parallel to the substrate and perpendicular to the first direction X, the distance between adjacent bit lines 30 is increased, and the parasitic capacitance between the bit lines 30 is reduced.

[0075] In some embodiments, two memory cells adjacent along the first direction X can be connected to the same bit line 30. Two columns of memory cells can form a group, and the memory cells adjacent along the first direction X in the same group are connected to the same bit line 30.

[0076] The word lines 40 can extend along the second direction Y. The word line 40 can include two end surfaces arranged opposite along the second direction Y and a side surface (i.e., a surface extending along the direction of the word line 40) between the two end surfaces. The word lines 40 of the same memory cell array can be distributed at intervals along the first direction X. The word lines 40 of the memory cell arrays of different layers can be arranged stacked in a direction perpendicular to the substrate 1.

[0077] The memory cell can be a 1T1C memory cell, or can be a memory cell of other structures.

[0078] Taking the 1T1C memory cell as an example, the memory cell can include a transistor and a capacitor connected to the transistor. The transistor and the capacitor of the same memory cell can be distributed along the first direction X. The capacitor, the word line 40, and the bit line 30 can be distributed along the first direction X. The plurality of capacitors connected to the plurality of memory cells of the same column can be distributed along the second direction Y.

[0079] The transistor can include a semiconductor layer 23 surrounding the side surface of the word line 40, and the semiconductor layer 23 is connected to the bit line 30. The semiconductor layers 23 of the memory cells of the same column are distributed at intervals along the second direction Y and surround the same word line 40. The semiconductor layer 23 can include two side surfaces (i.e., a surface facing the word line 40 and a surface away from the word line 40) and two end surfaces connecting the two side surfaces.

[0080] A gate insulating layer 24 is arranged between the semiconductor layer 23 and the word line 40. The gate insulating layer 24 surrounds the side surface of the word line 40. The gate insulating layer 24 can include a side surface facing the word line 40 and a side surface away from the word line 40.

[0081] In some embodiments, the gate insulating layers 24 of the memory cells in the same column can be spaced apart along the second direction Y and surround the same word line 40.

[0082] The bit line 30 can be disposed in a bit line hole (i.e., the first hole K1 in the subsequent embodiments) that penetrates the multi-layer memory cells in a direction perpendicular to the substrate 1. The bit line hole can be spaced apart along the second direction Y.

[0083] In some embodiments, the capacitor can include a first capacitor electrode 41 and a second capacitor electrode. The first capacitor electrode 41 is connected to the side of the semiconductor layer 23 that faces away from the bit line 30.

[0084] In some embodiments, the contact surface of the semiconductor layer 23 with the first capacitor electrode 41 and the contact surface of the semiconductor layer 23 with the bit line 30 are misaligned in the first direction X. Taking any memory cell as an example, referred to as a target memory cell, two memory cells adjacent to the target memory cell in the second direction Y are referred to as a first memory cell and a second memory cell, respectively. One of the contact surface of the semiconductor layer 23 of the target memory cell with the first capacitor electrode 41 and the contact surface of the semiconductor layer 23 with the bit line 30 is close to the first memory cell, and the other is close to the second memory cell. That is, compared with the scheme in which the bit line 30 is distributed in a direction perpendicular to the first direction X, in the present embodiment, the semiconductor layer 23 is inclined to surround the word line 40, and the surrounding direction of the semiconductor layer 23 and the extension direction of the word line 40 are not perpendicular.

[0085] The second capacitor electrode can include a first sub-electrode 421 and a second sub-electrode 422. The first capacitor electrode 41 can surround the first sub-electrode 421 through a first dielectric layer 431, and the second capacitor electrode can partially surround the first capacitor electrode 41 through a second dielectric layer 432.

[0086] In some embodiments, the first capacitor electrode 41 can include a first portion extending in a direction perpendicular to the substrate 1 and a second portion extending from both ends of the first portion toward the first sub-electrode 421, respectively; the first portion is connected to the semiconductor layer 23.

[0087] In some embodiments, the semiconductor device can further include a capacitor hole (i.e., a second hole in subsequent embodiments) penetrating through multiple layers of the memory cell, the first capacitor electrode 41 can be disposed on the sidewall of the capacitor hole, and multiple first capacitor electrodes 41 of multiple memory cells at the same position of different layers are disposed on the sidewall of the capacitor hole and are spaced apart in a direction perpendicular to the substrate 1. The first sub-electrode 421 and the first dielectric layer 431 are distributed within the capacitor hole, the first dielectric layer 431 covers the inner wall of the capacitor hole where the first capacitor electrode 41 is formed, and the first sub-electrode 421 fills the capacitor hole. The second sub-electrode 422 and the second dielectric layer 432 are distributed outside the capacitor hole.

[0088] In some embodiments, a first isolation hole penetrating through multiple layers of the memory cell is disposed between adjacent bit lines 30 in the second direction Y and between adjacent word lines 40 in the first direction X, the first isolation hole is filled with a first isolation layer 151 of an integral structure, the first isolation hole exposes the side surface of the adjacent word line 40, and the side surface of the adjacent bit line 30 (i.e., the surface of the bit line 30 extending in a direction perpendicular to the substrate 1).

[0089] In some embodiments, the first isolation hole further exposes the side surface of the gate insulating layer 24 (which can include the gate insulating layers 24 of four memory cells here, i.e., four memory cells adjacent in the first direction X and adjacent in the second direction Y) adjacent to the first isolation hole towards the side of the word line 40, and exposes the end surface of the semiconductor layer 23 (which can include the semiconductor layers 23 of four memory cells here) adjacent to the first isolation hole. The first isolation layer 151 is in contact with the exposed side surface of the gate insulating layer 24 and the exposed end surface of the semiconductor layer 23.

[0090] In some embodiments, a second isolation hole penetrating through multiple layers of the memory cell is disposed between adjacent capacitor holes in the second direction Y, the second isolation hole is filled with a second isolation layer 152 of an integral structure, the second isolation hole can expose the first capacitor electrode 41 in the adjacent capacitor holes (including two capacitor holes adjacent in the second direction Y) and the side surface of the word line 40 adjacent to the capacitor hole. The second isolation layer 152 can be in contact with the first part of the exposed first capacitor electrode 41 (which can be in contact with the first part of the two first capacitor electrodes 41 adjacent in the second direction Y) and the side surface of the exposed word line 40. The second isolation hole further exposes the second dielectric layer 432, i.e., the second isolation layer 152 is in contact with the second dielectric layer 432.

[0091] In some embodiments, the second isolation hole can also expose a side surface of the adjacent gate insulating layer 24 (may include the gate insulating layers 24 of two adjacent memory cells along the second direction Y) and expose an end surface of the adjacent semiconductor layer 23 (may include the semiconductor layers 23 of two adjacent memory cells along the second direction Y). The second isolation layer 152 is in contact with the exposed side surface of the gate insulating layer 24 and the exposed end surface of the semiconductor layer 23.

[0092] In some embodiments, the contact surface of the word line 40 and the first isolation layer 151 can form a recess away from the first isolation layer 151, and the contact surface of the word line 40 and the second isolation layer 152 can form a recess away from the second isolation layer 152. The scheme provided by the present embodiment can maximize the distance between the word line 40 and other adjacent word lines or electrodes of the capacitor, thereby reducing the coupling capacitance.

[0093] In some embodiments, the first isolation hole can extend along the second direction Y, and a plurality of first isolation holes distributed between a column of bit lines 30 are sequentially staggered along the first direction X. Referring to the first isolation hole K3' in FIGS. 11A and 11B, a plurality of first isolation holes K3' distributed between a column of bit lines 30 are sequentially staggered along the first direction X and in the same direction as the bit line hole.

[0094] In some embodiments, the second isolation hole can extend along the second direction Y, and a plurality of second isolation holes distributed between a column of capacitor holes are sequentially staggered along the first direction X. Referring to the second isolation hole K4' in FIGS. 11A and 11B, a plurality of second isolation holes K4' distributed between a column of capacitor holes are sequentially staggered along the first direction X and in the same direction as the capacitor hole.

[0095] In some embodiments, the first isolation layer 151 and the second isolation layer 152 can be formed simultaneously, for example, the first isolation layer 151 and the second isolation layer 152 can be the fifth insulating layer 15 described in the subsequent embodiments.

[0096] In some embodiments, a plurality of second sub-electrodes 422 of a plurality of memory cells in the same column distributed along the second direction Y can be connected to form an integrated structure. The second sub-electrode 422 can include a first sub-portion extending along a direction perpendicular to the substrate 1 direction through a plurality of layers of memory cells and a plurality of second sub-portions extending from the first sub-portion along a direction parallel to the substrate 1 direction, the first sub-portion filling the area between the first capacitor electrodes 41 adjacent along the first direction X; the second sub-portion extends to the side of the second isolation hole away from the word line 40, partially surrounds the first capacitor electrode 41, and fills the area between the first capacitor electrodes 41 adjacent along the second direction Y.

[0097] In some embodiments, the first sub-portion can include: a plurality of body portions 4221 extending along the second direction Y, a plurality of connection portions 4222 connecting adjacent body portions 4221, the connection portions 4222 being located between adjacent capacitor holes along the first direction X. The plurality of body portions 4221 of the first sub-portion can exist with a misalignment along the first direction X, and the misalignment direction is the same as that of the column of capacitor holes.

[0098] In some embodiments, the second sub-electrode 422 of the plurality of memory cells of each two adjacent columns distributed along the second direction Y can be connected to form an integrated structure.

[0099] In some embodiments, the second dielectric layer 432 of the plurality of memory cells of each two adjacent columns distributed along the second direction Y can be connected to form an integrated structure.

[0100] In some embodiments, the second dielectric layer 432 of the plurality of memory cells of each two adjacent columns distributed along the second direction Y can be connected to form an integrated structure.

[0101] The technical solutions of the present embodiment are further described below through the manufacturing process of the semiconductor device of the present embodiment. In the present embodiment, the film layer pattern is formed through a "patterning process" or a "photolithography process". The "patterning process" mentioned in the present embodiment includes deposition of a film layer, coating of a photoresist, mask exposure, development, etching, stripping of the photoresist, etc., which are mature manufacturing processes in the related art. The "photolithography process" mentioned in the present embodiment includes coating of a film layer, mask exposure, and development, which are mature manufacturing processes in the related art. Deposition can use known processes such as sputtering, evaporation, chemical vapor deposition, etc., coating can use known coating processes, and etching can use known methods, which are not specifically limited herein. In the description of the present embodiment, it should be understood that "thin film" refers to a thin film of a certain material manufactured on a substrate using a deposition or coating process. If the "thin film" does not need a patterning process or a photolithography process during the entire manufacturing process, the "thin film" can also be referred to as a "layer". If the "thin film" still needs a patterning process or a photolithography process during the entire manufacturing process, it is referred to as a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process or the photolithography process contains at least one "pattern".

[0102] In an exemplary embodiment, the manufacturing process of the semiconductor device can include:

[0103] 1) forming a bit line 30;

[0104] providing a substrate 1, depositing a first insulating thin film and a sacrificial layer thin film alternately on the substrate 1 to form a stack structure including a plurality of first insulating layers 11 and sacrificial layers 10 arranged alternately;

[0105] Etching the stack structure along a direction perpendicular to the substrate 1 from the top layer to the bottom layer (stopping on the substrate 1), a plurality of first holes K1 are formed, each column including a plurality of first holes K1 spaced along a second direction Y intersecting the first direction X and not perpendicular to the first direction X;

[0106] After depositing the first conductive thin film, the first holes K1 are filled with a bit line 30. As shown in FIGS. 2A, 2B, 2C and 2D, which are cross-sectional views along the AA', BB', CC' and EE' directions, respectively, after forming the bit line 30. Only one column of first holes K1 is shown in FIGS. 2A-2D. The EE' direction is perpendicular to the substrate 1 and perpendicular to the first direction X.

[0107] In some embodiments, the first conductive thin film can be one or more of the following different types of materials:

[0108] For example, containing tungsten, aluminum, titanium, copper, nickel, platinum, ruthenium, molybdenum, gold, iridium, rhodium, tantalum, cobalt, etc. It can be a metal alloy containing one of the aforementioned metals.

[0109] Alternatively, it can be a metal oxide, a metal nitride, a metal silicide, a metal carbide, etc. For example, indium tin oxide (ITO), indium zinc oxide (IZO), indium oxide (InO), aluminum-doped zinc oxide (AZO), etc. high-conductivity metal oxide materials; for example, titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN), etc. metal nitride materials.

[0110] Alternatively, it can be a polysilicon material, a conductive doped semiconductor material, etc. For example, conductively doped silicon, conductively doped germanium, conductively doped silicon germanium, etc. Other materials that exhibit conductivity, etc.

[0111] The materials of the subsequent second to fifth conductive thin films are similar to the first conductive thin film, and will not be described again.

[0112] In some embodiments, the bit line 30 can include a first sub-layer 31 and a second sub-layer 32. The first sub-layer 31 can be a conductive material such as TiN, etc. with good adhesion to other film layers, and the second sub-layer 32 can be a conductive material with low resistivity such as tungsten, etc. The first sub-layer 31 covers the bottom and side walls of the first holes K1, and the second sub-layer 32 fills the first holes K1. However, embodiments of the present disclosure are not limited thereto, and the bit line 30 can be other single-layer or multi-layer structures.

[0113] In some embodiments, the substrate 1 can be a conventional silicon substrate or other bulk substrate including a layer of semiconductor material.

[0114] In some embodiments, the first insulating film can be a low-K dielectric layer including but not limited to silicon oxide such as silicon dioxide (SiO2) and the like, and the subsequent second to fifth insulating film materials are similar and will not be repeated here.

[0115] In some embodiments, the sacrificial layer film can be a film layer having etching selectivity with the first insulating film, such as silicon nitride (SiN) and the like.

[0116] In some embodiments, the first hole K1 can be circular, square, or the like along a cross-section parallel to the substrate 1.

[0117] 2) Forming a first capacitor electrode 41;

[0118] Depositing a second insulating film to form a second insulating layer 12 covering the bit line 30 and the topmost sacrificial layer 10;

[0119] Etching the stack structure from top to bottom along a direction perpendicular to the substrate 1 (the etching stops on the substrate 1) to form a plurality of second initial holes K2 spaced along the second direction Y; the second initial holes K2 are spaced along the first direction X from the first holes K1;

[0120] Based on the second initial holes K2, etching the sacrificial layer 10 laterally (i.e., etching parallel to the substrate 1 direction) to form a first lateral recess V1, the second initial hole K2 and the first lateral recess V1 constitute a second hole, and the second hole is located in the first insulating layer 11 The projection of the sub-hole on the substrate 1 falls within the projection of the sub-hole of the second hole on the substrate 1;

[0121] In sequence, depositing a second conductive film and a first dummy layer film to form a first capacitor electrode 41 and a first dummy layer 91, the second conductive film covering the inner wall of the second initial hole K2 and the inner wall of the first lateral recess V1, and the first dummy layer film filling the second initial hole K2 and the first lateral recess V1;

[0122] Etching to remove the first dummy layer 91 in the second initial hole K2, and retaining the first dummy layer 91 in the first lateral recess V1, as shown in FIGS. 3A, 3B, 3C and 3D. FIGS. 3A, 3B, 3C, 3D are cross-sectional views along the AA', BB', CC', and EE' directions, respectively, after forming the first capacitor electrode 41 according to some embodiments.

[0123] In some embodiments, the first dummy layer film can be polysilicon or the like and the first insulating film, the sacrificial layer film has etching selectivity. The second dummy layer film and the third dummy layer film are similar in material and will not be described again.

[0124] In some embodiments, the second initial hole K2 can be circular, square, oval or the like along the cross section parallel to the substrate 1.

[0125] 3) Forming the second dummy layer 92;

[0126] Etching to remove the first capacitor electrode 41 in the second initial hole K2, leaving the first capacitor electrode 41 in the first lateral groove V1, at which time the first capacitor electrode 41 of different layers is disconnected;

[0127] Depositing a second dummy layer film and polishing to form a second dummy layer 92 filling the second initial hole K2; the second dummy layer 92 is flush with the second insulating layer 12, as shown in FIGS. 4A, 4B, 4C and 4D. FIGS. 4A, 4B, 4C, 4D are cross-sectional views along the AA', BB', CC', and DD' directions, respectively, after forming the second dummy layer 92 in some embodiments.

[0128] 4) Forming the third hole K3 and the fourth hole K4;

[0129] Depositing a first hard mask film to form a first hard mask layer 71 covering the previously formed structure; the first hard mask film can be a low-K dielectric layer, including but not limited to silicon oxide, such as SiO2 or the like.

[0130] The first hard mask layer 71 forms a first isolation groove extending along the second direction Y that completely exposes one side of the column of bit lines 30 away from the substrate 1, and the first hard mask layer 71 forms a second isolation groove extending along the second direction Y that exposes the area of the column of second initial holes K2 close to the bit lines 30;

[0131] Based on the first isolation groove, a third hole K3 extending along the second direction Y is formed between the first holes K1 adjacent along the second direction Y, and based on the second isolation groove, a fourth hole K4 extending along the second direction Y is formed between the second initial holes K2 adjacent along the second direction Y, and the fourth hole K4 is close to the second initial hole K2 towards the end of the bit line 30; adjacent third holes K3 and fourth holes K4 are spaced apart along the first direction X; the sidewall of the third hole K3 exposes two bit lines 30 adjacent along the second direction Y; the sidewall of the fourth hole K4 exposes two first capacitor electrodes 41 adjacent along the second direction Y;

[0132] Depositing a third insulating film and a third dummy layer film in sequence and planarizing, forming a third insulating layer 13 covering the inner walls of the first isolation groove, the second isolation groove, the third hole K3 and the fourth hole K4, and a third dummy layer 93 filling the first isolation groove, the second isolation groove, the third hole K3 and the fourth hole K4; as shown in FIGS. 5A, 5B, 5C and 5D. Among them, FIGS. 5A, 5B, 5C, 5D are respectively the cross-sectional views of some embodiments provided after forming the third hole K3 and the fourth hole K4 along the AA' direction, the BB' direction, the CC' direction and the DD' direction. The distance between the surface of the third dummy layer 93 away from the substrate 1 and the substrate 1 is greater than the distance between the surface of the second dummy layer 92 away from the substrate 1 and the substrate 1.

[0133] 5) Forming a first trench T1;

[0134] Depositing a second hard mask film to form a second hard mask layer 72 covering the previously formed structure; the second hard mask film can be a low-K dielectric layer, including but not limited to silicon oxide, such as SiO2, etc.

[0135] Eroding the stack structure along a direction perpendicular to the substrate 1 on the side of the second initial hole K2 away from the bit line 30 to form a plurality of first trenches T1 penetrating through the stack structure; the first trench T1 extends along the second direction Y, and adjacent first trenches T1 define a group of memory cells, each group of memory cells including two columns of memory cells; the first trench T1 is located between two columns of second initial holes K2 adjacent along the first direction X, and the first trench T1 extends substantially along the second direction Y and can include a plurality of first sub-trenches T11 located between two second initial holes K2 adjacent along the first direction X and a plurality of second sub-trenches T12 connected by the plurality of first sub-trenches T11, the second sub-trenches T12 extending along the second direction Y, and different second sub-trenches T12 are staggered along the first direction X, and the staggered direction is the same as that of the second initial hole K2.

[0136] Based on the lateral etching of the first trench T1 to the fourth hole K4 (i.e., etching to expose the third insulating layer 13 in the fourth hole K4 away from the bit line 30 side), a second lateral groove V2 is formed, as shown in FIGS. 6A, 6B, 6C and 6D. Among them, FIGS. 6A, 6B, 6C, 6D are respectively the cross-sectional views of some embodiments provided after forming the first trench T1 along the AA' direction, the BB' direction, the CC' direction and the DD' direction.

[0137] 6) Forming a second dielectric layer 432 and a second sub-electrode 422;

[0138] Depositing a second dielectric thin film and a third conductive thin film in sequence to form a second dielectric layer 432 and a second sub-electrode 422, the second dielectric layer 432 covers the inner walls of the first trench T1 and the second lateral groove V2, and the second sub-electrode 422 fills the first trench T1 and the second lateral groove V2.

[0139] In some embodiments, the second sub-electrode 422 can include a third sub-layer 33 and a fourth sub-layer 34, the third sub-layer 33 can be a conductive material such as TiN or the like with good adhesion to other film layers, and the fourth sub-layer 34 can be a conductive material with low resistivity such as tungsten or the like. As shown in FIGS. 7A, 7B, 7C and 7D, which are cross-sectional views along the AA' direction, the BB' direction, the CC' direction and the DD' direction respectively after forming the second dielectric layer 432 and the second sub-electrode 422 in some embodiments.

[0140] In some embodiments, the second dielectric thin film can be a High-K dielectric material. In some embodiments, it can include one or more oxides of hafnium, aluminum, lanthanum, zirconium or the like. Exemplary, it can include but is not limited to at least one of the following: hafnium oxide (HfO2), aluminum oxide (Al2O3), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), zirconium oxide (ZrO2) and other high-K materials. The subsequent first dielectric thin film is similar to the second dielectric thin film and will not be described again.

[0141] 7) forming a protective structure of the second sub-electrode 422;

[0142] Wet etching to remove the second sub-electrode 422 at the top of the first trench T1; etching to a distance between the surface of the second sub-electrode 422 away from the substrate 1 and the substrate 1 is less than the distance between the surface of the second dummy layer 92 away from the substrate 1 and the substrate 1.

[0143] Depositing a fourth insulating thin film and planarizing to form a fourth insulating layer 14 covering the second sub-electrode 422 away from the substrate 1, the fourth insulating layer 14 is flush with the third dummy layer 93, and the fourth insulating layer 14 serves as a protective structure at the top of the second sub-electrode 422. As shown in FIG. 8, which is a cross-sectional view along the CC' direction after forming a protective structure of the second sub-electrode 422 in some embodiments.

[0144] 8) etching to remove the sacrificial layer 10;

[0145] Wet etching to remove the third dummy layer 93;

[0146] Wet etching the third insulating layer 13 to expose the sacrificial layer 10;

[0147] The third hole K3 and the fourth hole K4 are used to remove the sacrificial layer 10 by wet etching, to form a channel B1, to provide space for manufacturing the semiconductor layer 23 and the word line 40; as shown in FIGS. 9A, 9B, 9C and 9D. FIGS. 9A, 9B, 9C and 9D are cross-sectional views along the AA' direction, the BB' direction, the CC' direction and the DD' direction, respectively, after the sacrificial layer 10 is removed by etching, according to some embodiments.

[0148] 9) forming the semiconductor layer 23, the gate insulating layer 24 and the word line 40;

[0149] The semiconductor thin film, the gate insulating thin film and the fourth conductive thin film are sequentially deposited to form the semiconductor layer 23, the gate insulating layer 24 and the word line 40; the fourth conductive thin film fills the space between the two adjacent first insulating layers 11, and does not completely fill the third hole K3 and the fourth hole K4, to facilitate subsequent etching of the semiconductor layer 23 and the word line 40 through the third hole K3 and the fourth hole K4; as shown in FIGS. 10A, 10B, 10C and 10D. FIGS. 10A, 10B, 10C and 10D are cross-sectional views along the AA' direction, the BB' direction, the CC' direction and the DD' direction, respectively, after the semiconductor layer 23, the gate insulating layer 24 and the word line 40 are formed, according to some embodiments.

[0150] In some embodiments, the material of the semiconductor thin film can be silicon or polycrystalline silicon, etc. with a band gap less than 1.65 eV, or can be a wide band gap material, such as a metal oxide material with a band gap greater than 1.65 eV.

[0151] For example, the material of the metal oxide semiconductor layer or the channel can include a metal oxide of at least one of the following metals: indium, gallium, zinc, tin, tungsten, magnesium, zirconium, aluminum, hafnium, etc. Of course, the metal oxide can also include compounds containing other elements, such as N, Si, etc.; and can also include other small amounts of doped elements.

[0152] In some embodiments, the material of the metal-oxide semiconductor layer or channel can include one or more of indium gallium zinc oxide (InGaZnO), indium zinc oxide (InZnO), indium gallium oxide (InGaO), indium tin oxide (InSnO), indium gallium tin oxide (InGaSnO), indium gallium zinc tin oxide (InGaZnSnO), indium oxide (InO), tin oxide (SnO), zinc tin oxide (ZnSnO, ZTO), indium aluminum zinc oxide (InAlZnO), zinc oxide (ZnO), indium gallium silicon oxide (InGaSiO), indium tungsten oxide (InWO, IWO), titanium oxide (TiO), zinc oxynitride (ZnON), magnesium zinc oxide (MgZnO), zirconium indium zinc oxide (ZrInZnO), hafnium indium zinc oxide (HfInZnO), tin indium zinc oxide (SnInZnO), aluminum tin indium zinc oxide (AlSnInZnO), silicon indium zinc oxide (SiInZnO), aluminum zinc tin oxide (AlZnSnO), gallium zinc tin oxide (GaZnSnO), zirconium zinc tin oxide (ZrZnSnO), and the like, as long as the leakage current of the transistor can meet the requirements, which can be adjusted according to the actual situation.

[0153] The band gap of these materials is wide, and the leakage current is low, for example, when the metal oxide material is IGZO, the leakage current of the transistor is less than or equal to 10 -15 A, thereby improving the working performance of the dynamic memory.

[0154] The material of the metal-oxide semiconductor layer or channel described above only emphasizes the element type of the material, and does not emphasize the atomic percentage in the material and the film quality of the material.

[0155] In some embodiments, the material of the gate insulating layer 24 can include one or more layers of High-K dielectric material. In some embodiments, one or more oxides of hafnium, aluminum, lanthanum, zirconium, etc. can be included. For example, at least one of the following high-K materials can be included, such as but not limited to: hafnium oxide (HfO2), aluminum oxide (Al2O3), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), zirconium oxide (ZrO2), and the like.

[0156] 10) disconnecting the plurality of semiconductor layers 23 in the same layer, and disconnecting the plurality of word lines 40;

[0157] etching the semiconductor thin film, the gate insulating thin film and the fourth conductive thin film in the third hole K3 and the fourth hole K4, and based on the third hole K3 and the fourth hole K4, etching the gate insulating thin film and the semiconductor thin film in a direction parallel to the substrate 1, so that the different word lines 40 are disconnected, and so that the multiple semiconductor layers 23 in the same layer and the same column are disconnected, and so that the multiple gate insulating layers 24 in the same layer and the same column are disconnected. At this time, the region of the semiconductor thin film and the gate insulating thin film around the third hole K3 and the third hole K3 which are etched form a first isolation hole K3', and the region of the semiconductor thin film and the gate insulating thin film around the fourth hole K4 and the fourth hole K4 which are etched form a second isolation hole K4'; as shown in FIG. 11A, FIG. 11B, FIG. 11C and FIG. 11D. Wherein, FIG. 11A, FIG. 11B, FIG. 11C, FIG. 11D are respectively cross-sectional views along the AA' direction, the BB' direction, the CC' direction, the DD' direction after disconnecting the multiple semiconductor layers 23 and the multiple word lines 40 provided by some embodiments.

[0158] 11) exposing the second initial hole K2;

[0159] 11) exposing the second initial hole K2;

[0160] polishing the fifth insulating layer 15, so that the surface of the second dummy layer 92 away from the substrate 1 side is exposed;

[0161] etching and removing the second dummy layer 92 and the first dummy layer 91, and exposing the second initial hole K2;

[0162] based on the second initial hole K2, etching the first insulating layer 11 in the lateral direction to form a third lateral groove V3, so as to expose the surface of the first capacitor electrode 41 towards the substrate 1 side and the surface of the first capacitor electrode 41 away from the substrate 1 side, i.e. the surface of the first capacitor electrode 41 parallel to the substrate 1 is exposed, so as to increase the area directly opposite between the electrodes of the capacitor. As shown in FIG. 12A, FIG. 12B, FIG. 12C and FIG. 12D. Wherein, FIG. 12A, FIG. 12B, FIG. 12C, FIG. 12D are respectively cross-sectional views along the AA' direction, the BB' direction, the CC' direction, the DD' direction after exposing the second initial hole K2 provided by some embodiments.

[0163] 12) forming a first dielectric layer 431 and a first sub-electrode 421;

[0164] The first dielectric thin film and the fifth conductive thin film are sequentially deposited to form a first dielectric layer 431 and a first sub-electrode 421; the first dielectric layer 431 covers the inner wall of the second initial hole K2, the inner wall of the first capacitor electrode 41, and the inner wall of the third transverse groove V3; the first sub-electrode 421 fills the second initial hole K2, the first transverse groove V1, and the third transverse groove V3; as shown in FIGS. 1A, 1B, 1C, and 1D.

[0165] In some embodiments, the first sub-electrode 421 can include a fifth sub-layer 35 and a sixth sub-layer 36; the fifth sub-layer 35 can be a conductive material such as TiN or the like with good adhesion to other film layers, and the sixth sub-layer 36 can be a conductive material such as tungsten or the like with low resistivity. The fifth sub-layer 35 is distributed on the bottom wall and the inner side wall of the first capacitor electrode 41, and the outer side wall on the side of the first capacitor electrode 41 facing the substrate 1 and the outer side wall on the side of the first capacitor electrode 41 facing away from the substrate 1; and the sixth sub-layer 36 fills the second initial hole K2, the first transverse groove V1, and the third transverse groove V3.

[0166] The embodiments of the present disclosure further provide an electronic device including the semiconductor device of any of the preceding embodiments or the semiconductor device formed by the manufacturing method of any of the preceding embodiments. The electronic device can be a storage device, a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device, a mobile power supply, or the like. The storage device can include a memory in a computer, and the like, which is not limited herein.

[0167] Although the embodiments of the present disclosure are disclosed as above, the content described is only the embodiments adopted for the purpose of facilitating the understanding of the present disclosure, and is not intended to limit the present disclosure. Any person skilled in the art of the present disclosure can make any modification and change in the form and details without departing from the spirit and scope of the present disclosure, but the patent protection scope of the present disclosure shall be subject to the scope defined by the appended claims.

Claims

1. A semiconductor device, comprising: a plurality of memory cell arrays stacked in a direction perpendicular to a substrate, the memory cell arrays including at least one column of a plurality of memory cells distributed in a second direction parallel to the substrate; a plurality of bit lines extending in the direction perpendicular to the substrate through the memory cells of different layers; and a plurality of memory cells in the same column and layer connected to a plurality of bit lines spaced apart in the second direction; a plurality of word lines distributed in different layers, the word lines and the bit lines being distributed in a first direction, the word lines extending in the second direction; the first direction and the second direction being parallel to the substrate, intersecting each other and not perpendicular; the memory cells including transistors including a semiconductor layer connected to the bit lines, the semiconductor layer surrounding the word lines, the semiconductor layers of memory cells in the same column being spaced apart in the second direction and surrounding the same word line.

2. The semiconductor device of claim 1, wherein, every two memory cells adjacent in the first direction are connected to the same bit line; a first isolation hole penetrating the memory cells of different layers is provided between adjacent bit lines in the second direction and between adjacent word lines in the first direction, the first isolation hole being filled with a first isolation layer of an integral structure, the first isolation hole exposing a side surface of the adjacent word line and a side surface of the adjacent bit line.

3. The semiconductor device of claim 2, wherein, the memory cells further include a capacitor connected to the semiconductor layer, the capacitor being provided on a side of the semiconductor layer away from the bit line, the capacitor being distributed in the first direction with the word line, a plurality of capacitors connected to a plurality of memory cells in the same column being distributed in the second direction.

4. The semiconductor device of claim 3, wherein, the capacitor includes a first capacitor electrode connected to the semiconductor layer and a second capacitor electrode including a first sub-electrode, the semiconductor device further includes a capacitor hole penetrating the memory cells of different layers, a plurality of first capacitor electrodes of a plurality of memory cells in the same position of different layers being provided on a sidewall of the capacitor hole and spaced apart in the direction perpendicular to the substrate, the first sub-electrode filling the capacitor hole, the plurality of first capacitor electrodes surrounding the first sub-electrode through a first dielectric layer; a second isolation hole penetrating the memory cells of different layers is provided between adjacent capacitor holes in the second direction, the second isolation hole being filled with a second isolation layer of an integral structure, the second isolation hole exposing the first capacitor electrode in the adjacent capacitor hole and a side surface of the word line adjacent to the capacitor hole.

5. The semiconductor device of claim 4, wherein, a contact surface of the semiconductor layer and the first capacitor electrode and a contact surface of the semiconductor layer and the bit line are misaligned in the first direction.

6. The semiconductor device of claim 2, wherein, the first isolation hole extends in the second direction, and a plurality of first isolation holes distributed between a column of bit lines are sequentially misaligned in the first direction.

7. The semiconductor device of claim 4, wherein, the second isolation hole extends in the second direction, and a plurality of second isolation holes distributed between a column of capacitor holes are sequentially misaligned in the first direction.

8. The semiconductor device of claim 4, wherein, The first capacitor electrode includes a first portion extending along a direction perpendicular to the substrate and second portions extending from both ends of the first portion toward the first sub-electrode, respectively; the first portion is connected to the semiconductor layer and two second isolation layers adjacent to the capacitor hole.

9. The semiconductor device of claim 8, wherein, The second capacitor electrode further includes a second sub-electrode, which surrounds the first portion of the first capacitor electrode through a second dielectric layer.

10. The semiconductor device of claim 4, wherein, The transistor further includes a gate insulating layer arranged between the semiconductor layer and the word line and surrounding the word line; the gate insulating layers of the plurality of transistors in the same layer and column are disconnected from the contact area of the word line surrounded by the plurality of gate insulating layers at the first isolation layer, and disconnected from the contact area of the word line surrounded by the plurality of gate insulating layers at the second isolation layer.

11. The semiconductor device of claim 10, wherein, The first isolation hole also exposes the side surface of the adjacent gate insulating layer, and exposes the end surface of the adjacent semiconductor layer.

12. The semiconductor device of claim 10, wherein, The second isolation hole also exposes the side surface of the adjacent gate insulating layer, and exposes the end surface of the adjacent semiconductor layer.

13. A semiconductor device manufacturing method, comprising: forming a stack structure including a plurality of first insulating layers and a plurality of sacrificial layers alternately arranged on a substrate; forming a plurality of bit line holes penetrating through the stack structure along a direction perpendicular to the substrate and spaced apart along a second direction; forming a bit line extending along a direction perpendicular to the substrate in the bit line hole to fill the bit line hole; forming a plurality of capacitor holes penetrating through the stack structure along a direction perpendicular to the substrate and spaced apart along a second direction, and the bit line hole and the capacitor hole are spaced apart along a first direction, based on etching the sacrificial layer along a direction parallel to the substrate, a first lateral recess is formed; forming a first capacitor electrode distributed on the inner wall of the first lateral recess; the first direction and the second direction intersect and are not perpendicular; forming a first isolation hole penetrating through the stack structure between the bit line holes adjacent along the second direction, the first isolation hole exposes the side surface of the adjacent bit line; and forming a second isolation hole penetrating through the stack structure between the capacitor holes adjacent along the second direction, the second isolation hole exposes the first capacitor electrode adjacent along the second direction; the first isolation hole and the second isolation hole are spaced apart along the first direction; etching and removing the sacrificial layer distributed between the first isolation hole and the second isolation hole, forming a channel extending along the second direction between the first isolation hole and the second isolation hole distributed along the second direction between the adjacent insulating layers; forming a word line extending along the second direction in the channel, and a plurality of semiconductor layers surrounding the word line and spaced apart along the second direction.

14. The method of manufacturing a semiconductor device according to Claim 13, wherein The forming a word line extending along the second direction in the channel, and a plurality of semiconductor layers surrounding the word line and spaced apart along the second direction includes: sequentially depositing a semiconductor thin film, a gate insulating thin film and a conductive thin film, the semiconductor thin film and the gate insulating thin film sequentially covering the first isolation hole, the second isolation hole and the inner wall of the channel, and the conductive thin film filling the channel and not completely filling the first isolation hole and the second isolation hole; etching to remove the semiconductor thin film, the gate insulating thin film and the conductive thin film in the first isolation hole and the second isolation hole, and etching the semiconductor thin film based on the first isolation hole and the second isolation hole in a direction parallel to the substrate, so that the semiconductor thin film forms a plurality of semiconductor layers spaced apart in the second direction, the conductive thin film forms a word line extending in the second direction, and the gate insulating thin film forms a gate insulating layer.

15. The semiconductor device manufacturing method of claim 13, further comprising sequentially forming a first dielectric layer covering the inner wall of a capacitor hole in which the first capacitor electrode is formed and a first sub-electrode filling the capacitor hole.

16. The semiconductor device manufacturing method of claim 13, further comprising, forming a trench through the stack structure between two adjacent rows of capacitor holes on a side of the capacitor hole facing away from the second isolation hole, the trench exposing the sacrificial layer of each layer; etching to remove the sacrificial layer between the trench and the second isolation hole based on the trench, forming a second lateral recess, the trench and the second lateral recess exposing a surface of the first capacitor electrode on a side of the second isolation hole facing away from the bit line; sequentially forming a second dielectric layer covering the inner wall of the trench and the second lateral recess and a second sub-electrode filling the trench and the second lateral recess in the trench and the second lateral recess.

17. An electronic device comprising the semiconductor device of any one of claims 1 to 12, or a semiconductor device formed according to the semiconductor device manufacturing method of any one of claims 13 to 16.

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