Solar cell and preparation method

Abstract

The present application relates to the technical field of semiconductor devices, and provides a solar cell and a preparation method. The solar cell of the present application comprises: a semiconductor substrate, comprising a first surface having a plurality of first texture structures, wherein in the direction moving away from the first surface, each first texture structure comprises a side surface and a top surface, and the top surface is connected to one end of the side surface; a tunneling layer, located on the first surface of the semiconductor substrate; a doped semiconductor layer, located on the surface of the tunneling layer distant from the semiconductor substrate; an electrode, located on the surface of the doped semiconductor layer distant from the semiconductor substrate and in contact with the doped semiconductor layer; and metal crystals, distributed at positions in the doped semiconductor layer in contact with the electrode, wherein the distribution density of the metal crystals in the doped semiconductor layer located on the top surface is greater than the distribution density in the doped semiconductor layer located on the side surface.

Description

Solar cell and method of manufacturing

[0001] Cross-reference to Related Applications

[0002] The present application claims priority to the Chinese patent application No. 202411238855.8, filed on September 5, 2024, and entitled "Solar cell and method of manufacturing", the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0003] The present application relates to the technical field of photovoltaic cells, in particular, the present application relates to a solar cell and a method of manufacturing. BACKGROUND

[0004] Different passivation contact schemes are increasingly applied in solar cells to improve efficiency. The back surface of a TOPCon (Tunnel Oxide Passivated Contact) cell usually has a polished structure. In order to increase the light trapping capability of the back surface of the TOPCon cell, the polished structure of the back surface of the cell usually has a concave-convex microstructure.

[0005] The conventional microstructure is thin and unevenly distributed on the sidewall of the concave-convex structure when depositing the tunnel layer and the doped polysilicon layer. When sintering is subsequently performed, the sidewall of the concave-convex structure has a risk of burning through. SUMMARY

[0006] In view of the above, in order to at least partially solve at least one of the above-mentioned technical problems, the present application provides a solar cell and a method of manufacturing.

[0007] In order to achieve the above-mentioned purpose, the technical solutions of the present application are as follows:

[0008] According to an aspect of the present application, a solar cell is provided, comprising: a semiconductor substrate comprising a first surface having a plurality of first texture structures; along a direction away from the first surface, the first texture structure comprises a side surface and a top surface, the top surface being connected to one end of the side surface; a tunnel layer located on the first surface of the semiconductor substrate; a doped semiconductor layer located on a surface of the tunnel layer away from the semiconductor substrate; an electrode located on a surface of the doped semiconductor layer away from the semiconductor substrate and in contact with the doped semiconductor layer; and a metal crystal distributed at a position of the doped semiconductor layer in contact with the electrode, the distribution density of the metal crystal in the doped semiconductor located on the top surface being greater than the distribution density of the metal crystal in the doped semiconductor located on the side surface.

[0009] According to another aspect of the present application, a method for manufacturing the above solar cell is provided, comprising: texturing and polishing a first surface of an initial substrate to form a plurality of first texture structures on the first surface to obtain a semiconductor substrate; sequentially forming a tunneling layer, a doped semiconductor layer, a first passivation and anti-reflection layer and an electrode material on the first surface of the semiconductor substrate; and sintering the electrode material to form an electrode, so that the electrode penetrates through the first passivation and anti-reflection layer to contact the doped semiconductor layer, and a metal crystal is formed in the doped semiconductor layer at a position contacting the electrode.

[0010] The first texture structure of the solar cell provided by the present application helps to increase the scattering and absorption of sunlight and improve the light trapping effect. Since a top surface is formed in the first texture structure, the proportion of side surfaces is small, so that the probability of the side surfaces contacting the metal paste is reduced, and the possibility of forming a metal crystal on the side surfaces is reduced, which helps to reduce the risk of burn-through. For the electrode paste, it is relatively easy to sinter to form a porous morphology, which further reduces the probability of the side surfaces contacting the metal paste, thereby reducing the burn-through at the side walls and inhibiting the formation of a metal crystal. Thus, a special distribution morphology is formed, in which the distribution density of the metal crystal on the top surface is greater than that on the side surface, which helps to optimize the current collection path and is beneficial to the extraction of carriers in the direction perpendicular to the top surface, thereby improving the photoelectric conversion performance of the solar cell.

[0011] The present application is based on texturing the first surface of the initial substrate, which helps to form a small texture or roughness on the first surface of the initial substrate to increase the scattering and absorption of light. Based on the polishing of the first surface, the first texture structure with a top surface is formed, and the proportion of side surfaces is reduced. Then, a tunneling layer, a doped semiconductor layer, a first passivation and anti-reflection layer and an electrode are sequentially formed on the first surface. It is found that the microstructure based on the small proportion of side surfaces reduces the possibility of the doped semiconductor layer on the side surface contacting the electrode, and reduces the possibility of forming a metal crystal on the side surface, thereby reducing the risk of burn-through, and a distribution morphology is formed in which the distribution density of the metal crystal on the top surface is greater than that on the side surface. BRIEF DESCRIPTION OF DRAWINGS

[0012] The above and other objects, features and advantages of the present application will become more apparent from the following description of embodiments of the present application, taken in conjunction with the accompanying drawings, in which:

[0013] FIG. 1 is a schematic structural diagram of a solar cell according to an embodiment of the present application;

[0014] FIG. 2 is a schematic side view of a first texture structure according to an embodiment of the present application, wherein a is a schematic side view of a first texture structure in a convex structure, and b is a schematic side view of a first texture structure in a groove structure;

[0015] FIG. 3 is a scanning electron microscope image of a cross section of a solar cell according to an embodiment of the present application;

[0016] FIG. 4 is a scanning electron microscope image of a cross section of a first texture structure according to an embodiment of the present application;

[0017] FIG. 5 is a scanning electron microscope image of a top view of the first texture structure according to an embodiment of the present application;

[0018] FIG. 6 is a side view schematic diagram of a protruding structure of the first texture structure according to an embodiment of the present application;

[0019] FIGS. 7A to 7C are partial enlarged views of metal crystal distribution at different positions of a cross section of a solar cell, respectively;

[0020] FIG. 8 is a flowchart of a method for manufacturing a solar cell according to another embodiment of the present application;

[0021] FIG. 9 is a flowchart of a method for manufacturing a TOPCon solar cell according to still another embodiment of the present application;

[0022] FIG. 10 is a schematic diagram of a manufacturing process of a TOPCon solar cell according to still another embodiment of the present application;

[0023] FIG. 11 is a schematic diagram of a structure of a back contact solar cell according to yet another embodiment of the present application. DETAILED DESCRIPTION

[0024] In order to make the objects, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the embodiments and the accompanying drawings.

[0025] The terms used herein are merely used to describe specific embodiments, and are not intended to limit the present application. The terms "comprise", "include" and the like used herein indicate the presence of the features, steps, operations and / or components, but do not exclude the presence or addition of one or more other features, steps, operations or components. All terms used herein (including technical and scientific terms) have meanings commonly understood by those skilled in the art, unless otherwise defined. It should be noted that the terms used herein should be interpreted to have meanings consistent with the context of the present specification, and should not be interpreted in an idealized or overly formal manner.

[0026] As used herein, relative terms such as "on", "above", or "upper" in reference to the relative position of two components (e.g., film layers or regions) can refer to the two components being in direct contact or can refer to the two components being non-directly in contact. Similarly, as used herein, relative terms such as "under", "below", or "lower" in reference to the relative position of two components can refer to the two components being in direct contact or can refer to the two components being non-directly in contact. For example, when one component (e.g., a film layer or region) is referred to as "on" another component, it can be directly on the other component or there can be intervening components between the two. On the other hand, when a component is referred to as "directly on" another component, there are no intervening components between the two. In addition, when one component is referred to as "on" another component, the two are in a top-to-bottom relationship in a plan view, and the component can be above or below the other component, so the top-to-bottom relationship depends on the orientation of the device.

[0027] For a solar cell with a tunneling passivation contact structure, to improve the light trapping capability of the surface, a concave-convex structure is usually made on the surface of the semiconductor substrate. However, when the tunneling layer and the doped polysilicon layer are subsequently deposited, the tunneling layer and the doped polysilicon layer on the side wall of the concave-convex structure are usually thin, and the layered structure formed is not uniform. When the metallization process is performed, for example, when the electrode is sintered, the side wall part of the concave-convex structure has a relatively high risk of burning through, especially when a laser-induced sintering process is used. Since this process has a large instantaneous current density, the risk of burning through caused by the non-uniformity of the tunneling layer and the doped polysilicon layer on the side wall is further amplified.

[0028] It is found in the implementation of the concept of the present application that by texturing and polishing the first surface of the initial substrate to form a first textured structure with a top surface on the first surface of the semiconductor substrate, the proportion of the side surface is reduced, the probability of the side surface contacting the metal paste is reduced, and the possibility of forming metal crystals on the side surface is reduced, thereby reducing the risk of burning through the side surface. Furthermore, when an electrode is made using an electrode paste containing appropriate paste ingredients, a porous morphology is formed, further reducing the probability of the side surface contacting the electrode paste, and more favorably reducing the risk of burning through the side surface and inhibiting the formation of metal crystals on the side surface. More metal crystals are distributed on the top surface, which helps to optimize the current collection path. The initial substrate is an initial state, untreated semiconductor type substrate, such as a silicon wafer in a raw state.

[0029] Specifically, according to an embodiment of the present application, a solar cell is provided, and FIG. 1 is a structural schematic diagram of the solar cell of the embodiment of the present application. FIG. 2 is a side view schematic diagram of a first texture structure of the embodiment of the present application, wherein (a) is a side view schematic diagram of the first texture structure being a convex structure, and (b) is a side view schematic diagram of the first texture structure being a groove structure. As shown in FIG. 1 and (a)-(b) of FIG. 2, the solar cell provided by the embodiment of the present application comprises a semiconductor substrate 101, a tunneling layer 102, a doped semiconductor layer 103, an electrode 104 and a metal crystal 105. The semiconductor substrate 101 comprises a first surface 101a having a plurality of first texture structures 1011; along a direction away from the first surface 101a, the first texture structure 1011 comprises a side surface 1011b and a top surface 1011a, and the top surface 1011a is connected to one end of the side surface 1011b. The tunneling layer 102 is located on the first surface 101a of the semiconductor substrate 101. The doped semiconductor layer 103 is located on a surface of the tunneling layer 102 away from the semiconductor substrate 101. The electrode 104 is located on a surface of the doped semiconductor layer 103 away from the semiconductor substrate 101 and is in contact with the doped semiconductor layer 103. The metal crystal 105 is distributed at a position of the doped semiconductor layer 103 in contact with the electrode 104, at least part of elements of the metal crystal 105 come from elements in the electrode 104, and a distribution density of the metal crystal 105 in the doped semiconductor layer located on the top surface 1011a is greater than a distribution density of the metal crystal 105 in the doped semiconductor layer located on the side surface 1011b. The above-mentioned relationship of the distribution densities can be understood as that the distribution density of the doped semiconductor layer on the top surface 1011a is greater than the distribution density of the doped semiconductor layer on the side surface 1011b adjacent to the top surface 1011a; or, it can also be understood as that, in a range of the first texture structure covered by the entire doped semiconductor layer 103, the overall distribution density of the doped semiconductor layer on the top surface 1011a is greater than the overall distribution density of the doped semiconductor layer on the side surface 1011b adjacent to the top surface 1011a; or, it can also be understood as that, in a range of the first texture structure of a local area covered by the entire doped semiconductor layer 103, the overall distribution density of the doped semiconductor layer on the top surface 1011a is greater than the overall distribution density of the doped semiconductor layer on the side surface 1011b adjacent to the top surface 1011a.

[0030] According to the embodiment of the present application, please continue to refer to (a)-(b) of FIG. 2, along a direction S away from the first surface, the first texture structure can be a convex structure or a groove structure, and the top surface 1011a of the first texture structure is a plane protruding along a direction away from the semiconductor substrate 101.

[0031] Further optionally, the "first texture structure" on the semiconductor substrate 101 can be a microstructure formed by texturing the first surface of the initial substrate and then polishing. It can be understood that the top surface 1011a is a polished surface formed by polishing.

[0032] According to embodiments of the present application, the "distribution density" of the metal crystal 105 refers to the number of metal crystals in a unit volume or a unit planar area or a unit cross-sectional area of the doped semiconductor on the top surface 1011a and the side surface 1011b.

[0033] According to embodiments of the present application, the semiconductor substrate 101 can be an N-type or P-type silicon substrate, for example, one of a single crystal silicon, a polycrystalline silicon, a microcrystalline silicon, and preferably an N-type or P-type single crystal silicon substrate. The conversion efficiency of a cell based on a single crystal silicon substrate is higher than that of other types such as a polycrystalline silicon cell. An N-type silicon substrate is obtained by introducing a donor impurity such as phosphorus (P), arsenic (As), or antimony (Sb) into the semiconductor material, or a P-type silicon substrate is obtained by introducing an acceptor impurity such as boron (B), aluminum (Al), or gallium (Ga) into the semiconductor material.

[0034] More preferably, the semiconductor substrate 101 can be an N-type single crystal silicon substrate with a (100) crystal orientation. The top surface 1011a is a (100) crystal plane, and the electron mobility on the top surface 1011a is higher than that on the side surface 1011b with other crystal planes. In this way, the distribution density of the metal crystal on the top surface 1011a and the side surface 1011b is more conducive to efficient transmission of electrons, easier extraction of photo-generated carriers, and thus better device performance.

[0035] According to embodiments of the present application, the tunneling layer 102 and the doped semiconductor layer 103 cooperate to form a tunneling passivation contact structure, wherein the tunneling layer 102 is used to transport multiple carriers and achieve a passivation effect, and can be but is not limited to silicon oxide, gallium oxide, aluminum oxide, titanium oxide, etc. The thickness of the tunneling layer 102 can be preferably 1-2 nm, for example, 1 nm, 1.2 nm, 1.5 nm, 1.8 nm, 2 nm, etc.

[0036] The doped semiconductor layer 103 can be at least one semiconductor material in a polysilicon layer or a microcrystalline silicon layer, etc., and the doping type thereof can be the same as or different from the doping type of the semiconductor substrate 101, which can be determined according to the battery type and the semiconductor substrate 101. For example, in the case of a TOPcon battery, in the case of an N-type silicon substrate for the semiconductor substrate 101, the doped semiconductor layer 103 can be N-type doping or P-type doping, or in the case of a P-type silicon substrate for the semiconductor substrate 101, the doped semiconductor layer 103 can be N-type doping or P-type doping. The thickness of the doped semiconductor layer 103 can be, for example, 80-200 nm, for example, 80 nm, 100 nm, 120 nm, 150 nm, 180 nm, 200 nm, etc.

[0037] According to the embodiments of the present application, the formation of the first texture structure 1011 makes the surface of the semiconductor substrate 101 have a concave-convex texture structure, which helps to increase the light trapping effect and improve the photoelectric conversion efficiency of the solar cell. The first texture structure 1011 with the top surface 1011a has a smaller side surface ratio, which reduces the contact probability of the doped semiconductor and the metal paste on the side surface, thereby reducing the possibility of forming metal crystals on the side surface 1011b during subsequent sintering, and also reducing the probability of burning through the side surface 1011b.

[0038] Further, for the electrode paste, by selecting appropriate paste ingredients, a porous morphology is formed after sintering, and the porous structure is more likely to form on the side surface 1011b of the first texture structure 1011. The presence of the porous structure further reduces the probability of the side surface contacting the metal paste, further reduces the probability of burning through the side surface 1011b, and inhibits the formation of metal crystals on the side surface 1011b. Therefore, the metal crystal distribution density of the top surface 1011a is greater than that of the side surface 1011b, which is beneficial to the extraction of photo-generated carriers along the direction perpendicular to the top surface 1011a, thereby improving the photoelectric conversion efficiency and current collection efficiency of the solar cell, and helping to obtain better device performance.

[0039] FIG. 3 is a scanning electron microscope (SEM) image of a partial cross-section of a solar cell according to an embodiment of the present application. FIG. 4 is a SEM image of a cross-section of a first texture structure according to an embodiment of the present application. FIG. 5 is a top view SEM image of a first texture structure according to an embodiment of the present application. The first texture structure 1011 is a protruding structure, which can be a truncated pyramid shape as shown in FIG. 3 or FIG. 4, but is not limited thereto, and can also be a truncated circular pyramid shape, etc. Here, "truncated pyramid shape" means a shape that is generally a truncated pyramid, and "truncated circular pyramid shape" is the same. The truncated pyramid shape can further be, for example, a staggered stack of pyramid base structures, such as the base structure 501 shown in FIG. 5. A suitable protruding structure not only facilitates uniform deposition of subsequent tunnel oxide and doped polysilicon layers, but also allows for a low proportion of side surfaces 1011b at the same side surface inclination angle.

[0040] According to an embodiment of the present application, FIG. 6 is a side view schematic diagram of a protruding structure of a first texture structure according to an embodiment of the present application. As shown in FIG. 6, along a direction S away from the first surface, the first texture structure 1011 includes a side surface 1011b and a top surface 1011a. The lateral dimension W2 of the side surface 1011b projected on the direction of the top surface 1011a refers to the lateral dimension W2 of the side surface 1011b orthogonally projected on the plane of the top surface 1011a. The ratio of the lateral dimension W2 of the side surface 1011b orthogonally projected on the plane of the top surface 1011a to the lateral dimension W1 of the top surface 1011a is 0.1-0.3, such as 0.1, 0.13, 0.15, 0.18, 0.2, 0.23, 0.25, 0.27, or 0.3, etc. As the ratio increases, the irregular topography formed by the plurality of base structures becomes more apparent, but if the ratio is too high, the proportion of the side surface 1011b is high, which is not conducive to uniform deposition of subsequent functional layers such as tunnel oxide and doped polysilicon layers fabricated on the first surface 101a. More importantly, it increases the risk of burn-through of the side surface 1011b. If the ratio is too low, it is difficult to maintain the micro-topography defined by the plurality of protruding structures for subsequent functional layers, and it is difficult to effectively improve the light incidence rate and light utilization rate. It can be understood that the "lateral dimension" of the top surface 1011a can be the dimension along the plane of the top surface 1011a, such as the side length or the diagonal length for a rectangular top surface 1011a, or the diameter length for a circular top surface 1011a.

[0041] Further, the lateral dimension W2 of the normal projection of the side surface 1011b on the plane of the top surface 1011a is 0.3-3 μm, for example, 0.3 μm, 0.5 μm, 0.8 μm, 1 μm, 1.5 μm, 2 μm, 2.5 μm or 3 μm, etc. The lateral dimension W1 of the top surface 1011a is 5-25 μm, for example, 5 μm, 7 μm, 9 μm, 11 μm, 13 μm, 15 μm, 17 μm, 19 μm, 21 μm or 23 μm, etc. The suitable size of the convex structure helps to reduce the probability of the side surface 1011b contacting the metal paste while ensuring that the first texture structure 1011 has good light trapping effect.

[0042] According to the embodiments of the present application, please continue to refer to FIG. 2 and FIG. 5, the first texture structure 1011 further includes a bottom surface 1011c connected to the other end of the side surface 1011b away from the top surface 1011a and located between the side surfaces 1011b of two adjacent first texture structures 1011. The distribution density of the metal crystals 105 in the doped semiconductor layer on the bottom surface 1011c is greater than that in the doped semiconductor layer on the side surface. Since the top surface 1011a and the bottom surface 1011c are formed in the first texture structure 1011, the proportion of the side surface 1011b is further reduced, the probability of the side surface 1011b contacting the metal paste is further reduced, the possibility of the side surface 1011b forming metal crystals is reduced, thereby reducing the risk of the side surface 1011b being burned through. In addition, more metal crystals can be formed in the doped semiconductor layer on the bottom surface 1011c, which further optimizes the current collection path and helps to reduce the contact resistance.

[0043] In the case of a (100) crystal direction N-type monocrystalline silicon substrate, the bottom surface 1011c is also a (100) crystal plane, similar to the top surface 1011a, the distribution of the metal crystals 105 on the bottom surface 1011c is more conducive to the efficient transmission of electrons and the extraction of photo-generated carriers, thereby achieving better device performance.

[0044] According to embodiments of the present application, the distance between two adjacent first texture structures 1011 is less than or equal to 9 μm, for example, it can be 0 μm, 1 μm, 2 μm, 3 μm, 4 μm, 5 μm, 6 μm, 7 μm, 8 μm or 9 μm, etc. When the two adjacent first texture structures are both protruding structures, the distance between the two adjacent first texture structures 1011 is the shortest distance between the two adjacent side surfaces 1011b of the two adjacent protruding structures; when the two adjacent first texture structures are both groove structures, the distance between the two adjacent first texture structures 1011 is the shortest distance between the two adjacent side surfaces 1011b of the two adjacent groove structures. Continue to refer to FIG. 5, when the distance between the two adjacent first texture structures 101 is 0, for example, as shown in FIG. 5, the staggered stacked pyramid base structure 501, at this time, the distance between the two adjacent first texture structures 1011 is 0 μm. As the distance increases, the number of first texture structures 1011 per unit area decreases. Keeping the distance within the above suitable range helps to maintain the micro-topography defined by the plurality of first texture structures 1011, improve the scattering and reflection ability of the incident light, improve the light utilization rate, and at the same time, the proportion of the side surface 1011b can be reduced, and the contact probability of the side surface 1011b with the metal paste can be reduced.

[0045] According to embodiments of the present application, the height from the bottom surface 1011c to the top surface 1011a is 0.1-0.8 μm, for example, it can be 0.1 μm, 0.2 μm, 0.3 μm, 0.4 μm, 0.5 μm, 0.6 μm, 0.7 μm or 0.8 μm. A suitable height helps to uniformly deposit the subsequent functional layers such as the tunneling oxide layer and the doped polysilicon layer on the first surface 101a. In this article, the "height from the bottom surface 1011c to the top surface 1011a" is the dimension in the direction S away from the first surface between the plane where the bottom surface 1011c is located and the plane where the top surface 1011a is located.

[0046] According to embodiments of the present application, please continue to refer to FIGS. 3-4, the side surface 1011b of the first texture structure 1011 has an arc that is recessed towards the inside of the semiconductor substrate 101. In this way, the bottom of the recessed first texture structure 1011 presents a concave surface. The topography of the concave surface helps to reduce the probability of the side surface 1011b contacting the metal paste, thereby helping to prevent the doped semiconductor layer 103 located on the side surface 1011b from being burned through.

[0047] According to embodiments of the present application, FIGS. 7A-7C are partial enlarged views of the distribution of metal crystals at different locations of the cross section of the solar cell; as shown in FIGS. 7A-7C, the metal crystals are mainly dispersed within the doped semiconductor layer 103. Further, the metal crystals 105 are nanoparticles in the form of dendritic, dentate or flower-like, and agglomerates of metal particles. The average particle size of the metal crystals 105 is 20-200 nm, for example, it can be 20 nm, 40 nm, 60 nm, 100 nm, 140 nm, 180 nm, 200 nm. The formation of the metal crystals 105 is conducive to the collection and transport of the photo-generated carriers generated by light excitation, and the size and morphology thereof can be regulated by the sintering process of the electrode 104, for example, by heating sintering and / or laser enhanced contact optimization process, and the appropriate particle size and morphology of the metal crystals 105 help to regulate the transport of the photo-generated carriers.

[0048] According to embodiments of the present application, the metal crystals 105 can be an alloy containing the metal elements of the electrode 104 and silicon elements. The alloy can establish a good ohmic contact between the electrode and the silicon substrate, which helps to improve the transport efficiency of the photo-generated carriers and reduce the contact resistance.

[0049] According to embodiments of the present application, as further shown in FIG. 1, the semiconductor substrate 101 further includes a second surface 101b having a plurality of second texture structures 1012, which are groove structures or protrusion structures. The second texture structures help to improve the light trapping effect, increase light absorption, and thus improve the photoelectric conversion efficiency. The solar cell further includes an emitter 107 formed in the second surface of the semiconductor substrate 101.

[0050] Herein, the "second texture structure" on the semiconductor substrate 101 can be a microstructure obtained by texturing the second surface, or the first surface and the second surface of the original substrate.

[0051] According to embodiments of the present application, further optionally, the emitter 107 generally has a high doping concentration to form a good ohmic contact, reduce the contact resistance, and improve the injection efficiency of the current. The emitter 107 can be N-type doped or P-type doped, and the doping type thereof can be the same as or different from that of the semiconductor substrate. Further optionally, the N-type doping can be achieved by doping the second surface 101b of the semiconductor substrate 101 with a high concentration of donor elements such as phosphorus (P), arsenic (As) or antimony (Sb), or by introducing acceptor elements such as boron (B), aluminum (Al) or gallium (Ga) into the second surface 101b of the semiconductor substrate 101.

[0052] According to an embodiment of the present application, as shown in FIG. 1, the solar cell further comprises a first passivation anti-reflection layer 106 on the surface of the doped semiconductor layer 103 away from the semiconductor substrate 101; and the electrode 104 is in contact with the doped semiconductor layer 103 through the first passivation anti-reflection layer 106.

[0053] According to an embodiment of the present application, as shown in FIG. 1, the solar cell further comprises a second passivation anti-reflection layer 108 on the surface of the emitter 107. The second passivation anti-reflection layer 108 helps to achieve good passivation anti-reflection effect, and improve the dark saturation current density and the hidden open circuit voltage of the solar cell. The second passivation anti-reflection layer 108 can be, for example, a silicon dioxide layer, a silicon nitride layer, or a laminated film of the combination of the two.

[0054] For example, the first passivation anti-reflection layer 106 and the second passivation anti-reflection layer 108 can respectively comprise an aluminum oxide layer and a silicon nitride layer arranged in sequence in the direction away from the semiconductor substrate 101. Further optionally, the thickness of the aluminum oxide layer can be 3-5 nm, for example, 3 nm, 3.5 nm, 4 nm, 4.5 nm, 5 nm, etc., and the thickness of the silicon nitride layer can be 80-120 nm, for example, 80 nm, 90 nm, 100 nm, 110 nm, 120 nm, etc.

[0055] According to an embodiment of another aspect of the present application, a preparation method of a solar cell is further provided. FIG. 8 is a flowchart of the preparation method of the solar cell according to another embodiment of the present application. As shown in FIG. 8 in combination with FIG. 1, the preparation method of the solar cell according to the embodiment of the present application comprises operation S801 to operation S803.

[0056] In operation S801, the first surface of the initial substrate is etched and polished to form a plurality of first texture structures 1011 on the first surface 101a, thereby obtaining the semiconductor substrate 101.

[0057] In operation S802, the tunneling layer 102, the doped semiconductor layer 103, the first passivation anti-reflection layer 106, and the electrode material are sequentially prepared on the first surface 101a of the semiconductor substrate 101.

[0058] In operation S803, the electrode material is sintered to form the electrode 104, so that the electrode 104 is in contact with the doped semiconductor layer 103 through the first passivation anti-reflection layer 106, and the metal crystal 105 is formed in the doped semiconductor layer 103 at the position in contact with the electrode 104.

[0059] According to the embodiments of the present application, based on the texturing and polishing of the first surface of the initial substrate, a plurality of first texture structures 1011 with top surfaces 1011a are formed, wherein the top surfaces 1011a are arranged to have a small proportion of side surfaces, thereby reducing the probability of the doped semiconductor layer 103 on the side surfaces 1011b contacting the metal paste or metal components during subsequent sintering, reducing the possibility of forming metal crystals in the doped semiconductor layer 103 on the side surfaces 1011b, and thereby reducing the probability of the doped semiconductor layer 103 on the side surfaces 1011b being burned through. Thus, the distribution density of the metal crystals 105 formed on the top surfaces 1011a of the first texture structures 1011 is greater than that on the side surfaces 1011b, which is conducive to the extraction of photo-generated carriers in the direction perpendicular to the top surfaces 1011a, and after being made into a solar cell, the photoelectric conversion efficiency and current collection efficiency can be improved.

[0060] According to the embodiments of the present application, in operation S801, specifically comprising: wet texturing the first surface of the initial substrate to form a plurality of second texture structures on the first surface; and polishing the first surface subjected to the wet texturing using a polishing reagent containing nitric acid and hydrofluoric acid to form a plurality of first texture structures on the first surface, thereby obtaining the semiconductor substrate 101.

[0061] According to the embodiments of the present application, further optionally, the wet texturing may, for example, be etching the surface of the initial substrate, such as a raw silicon wafer, using an alkaline solution (for example, containing 2wt%-6wt% potassium hydroxide or sodium hydroxide solution and 0.1wt%-1.0% texturing additive) at 70-80°C. This wet texturing process is more suitable for texturing single crystal silicon wafers to form pyramid structures. For another example, the wet texturing may also be etching the surface of the initial substrate using an acid solution (for example, HF / HNO3 solution with a volume ratio of 5:1-1:6) at 5-45°C. This wet texturing process is more suitable for texturing polycrystalline silicon wafers to form pit structures. Of course, it is not limited to wet texturing, and in addition, a dry texturing process such as laser etching can be combined to form a uniform array of micropores on the surface of the initial substrate. The dry texturing process is suitable for texturing single crystal silicon wafers or polycrystalline silicon wafers.

[0062] According to an embodiment of the present application, further optionally, the concentration of HNO3 in the polishing reagent is 68 wt%, and the concentration of HF is 0.2 wt%. The above suitable chemical polishing reagent is selected so that in the first texture structure 1011, the concentration of HF is lower at the other end of the side surface 1011b away from the top surface, and the product of etching is more difficult to diffuse out from the other end, so that the etching rate of the side surface 1011b near the other end has a tendency to decrease in gradient. Therefore, the side surface 1011b near the other end has a tendency to be rounded, forming a curved surface and even a concave curved surface, reducing the contact of the side surface 1011b with the metal slurry, and reducing the risk of burning through the side surface 1011b.

[0063] According to an embodiment of the present application, in operation S802, the tunneling layer 102 can be deposited on the surface of the semiconductor substrate 101 by chemical vapor deposition or atomic layer deposition as needed. For example, taking a silicon substrate as an example, a low-pressure chemical vapor deposition method can be used to thermally oxidize the silicon substrate to obtain a 1-2 nm thick tunneling layer 102. The tunneling layer 102 can also be referred to as a tunneling oxide layer.

[0064] Further optionally, an undoped semiconductor layer can be deposited on the surface of the tunneling layer 102 by a chemical vapor deposition method, and a doped semiconductor layer 103 can be formed by diffusion or ion implantation as needed. Taking a doped polysilicon layer as an example, a polysilicon or amorphous silicon layer can be deposited on the surface of the tunneling layer 102 by a low-pressure chemical vapor deposition method, and the polysilicon or amorphous silicon layer is converted into a doped polysilicon layer by a diffusion process.

[0065] Further optionally, a first passivation and anti-reflection layer 106 is deposited on the doped semiconductor layer 103, and the first passivation and anti-reflection layer 106 can be at least one of silicon nitride and silicon dioxide, for example.

[0066] Further optionally, an electrode material is printed on the first passivation and anti-reflection layer 106, and the printing method can be screen printing, inkjet printing, etc., which is used as needed. Since the electrode slurry used for printing contains organic components, it is easy to volatilize in the subsequent sintering process to form a porous morphology as shown in FIG. 3.

[0067] According to the embodiments of the present application, in operation S803, the sintering can be performed by means of thermal sintering or laser-assisted sintering, and the laser-assisted sintering is more preferred, which specifically includes: under-sintering the electrode material by means of heat treatment; and irradiating the edge region of the electrode material in contact with the doped semiconductor layer 103 after under-sintering by means of laser. It can be understood that the "under-sintering" of the present application refers to a state that the electrode is not completely sintered in the sintering process, for example, by reducing the sintering temperature and / or shortening the sintering time, so as to avoid the case that the mutual diffusion is excessive due to over-sintering. After under-sintering, the edge of the electrode material in contact with the doped semiconductor layer 103 is irradiated by means of laser to induce the formation of mutual diffusion between the metal component of the electrode 104 and the silicon component of the doped semiconductor layer 103, which is helpful to form the metal crystal 105. The laser induction is helpful to form a better ohmic contact between the electrode 104 and the doped semiconductor layer 103, which is helpful to improve the transport of carriers.

[0068] Specifically, taking the TOPCon cell as an example, FIG. 9 is a flowchart of a preparation method of a TOPCon cell according to another embodiment of the present application, and FIG. 10 is a schematic diagram of a preparation process of a TOPCon cell according to another embodiment of the present application. As shown in FIGS. 9 and 10, the preparation method of the TOPCon cell according to the embodiments of the present application includes operation S901 to operation S905.

[0069] In operation S901, the N-type single crystal silicon wafer is subjected to double-side texturing to obtain a silicon substrate 901 with a second texture structure 9012. For example, alkali texturing can be performed by using a 3% sodium hydroxide solution, so that the second texture structure 9012 is a pyramid structure and is respectively distributed on the opposite first surface 901a and second surface 901b of the silicon substrate 901.

[0070] In operation S902, the second surface 901b of the silicon substrate 901 with the second texture structure 9012 is doped by means of a diffusion process to form an emitter 907, as shown in FIG. 10(b). For example, the emitter 907 can be formed in the second surface 901b of the silicon substrate by means of boron diffusion.

[0071] In operation S903, the first surface 901a of the silicon substrate 901 opposite to the second surface 901b is subjected to single-side polishing to obtain a first surface 901a with a plurality of first texture structures 9011, as shown in FIG. 10(c). Along the direction away from the first surface 901a, the first texture structure 9011 includes a bottom surface 9011c, a side surface 9011b and a top surface 9011a, the top surface 9011a is connected to one end of the side surface 9011b, and the bottom surface 9011c is connected to the other end of the side surface 9011b.

[0072] At operation S904, the tunneling layer 902, the doped semiconductor layer 903, the first passivation anti-reflection layer 906 and the electrode material are sequentially fabricated on the first surface 901a of the silicon substrate 901, and the second passivation anti-reflection layer 908 and the electrode material are sequentially fabricated on the surface of the emitter 907. Exemplarily, the doped semiconductor layer 903 is an N-type doped polysilicon layer formed by a phosphorus diffusion process.

[0073] At operation S905, the electrode material is sintered to form the electrode 904, so that the electrode 904 on the first surface 901a is in contact with the doped semiconductor layer 903 through the first passivation anti-reflection layer 906, and a metal crystal 905 is formed in the doped semiconductor layer 903 at a position in contact with the electrode 904; and the electrode 904 on the second surface 901b is in contact with the emitter through the second passivation anti-reflection layer 908, as shown in (d) of FIG. 10. The sintering operation of the electrode 904 on the first surface 901a specifically includes: under-sintering the electrode material by means of heat treatment, and then irradiating the edge region of the under-sintered electrode material in contact with the doped semiconductor layer 903 by laser.

[0074] In the above exemplary embodiments of the present application, in the single-side polishing of operation S903, a chain device is used, and a polishing reagent containing 68wt% HNO3 and 0.2wt% HF is used for single-side polishing. The finally manufactured TOPCon cell cross-section has a morphology as shown in FIGS. 3 and 7A-7C, and the distribution density of the metal crystal in the doped polysilicon layer on the top surface and the bottom surface is greater than the distribution density of the metal crystal in the doped polysilicon layer on the side surface.

[0075] According to another aspect of the embodiments of the present application, a back contact type solar cell including the above metal crystal distribution structure is also provided. FIG. 11 is a structural schematic diagram of a back contact type solar cell according to another embodiment of the present application. The difference between the solar cell structure shown in FIG. 11 and the solar cell structure shown in FIG. 1 mainly lies in that the first surface is the back surface of the back contact type solar cell, and the first surface 101a includes the first region A and the second region B which are alternately and spacedly distributed, and the above tunneling passivation contact structure formed by the tunneling layer 102 and the doped semiconductor layer 103 is located on the first region A or respectively located on the first region A and the second region B. At this time, the distribution structure of the metal crystal in the doped semiconductor layer 103 is the same as described above, and will not be described herein again.

[0076] Exemplarily, as shown in FIG. 11, in an embodiment, the tunneling passivation contact structure can be located on the first region A and the second region B respectively, at this time, the tunneling layer 102 and the doped semiconductor layer 103 can be understood as a patterned layer structure, and the corresponding back contact solar cell is a TBC (TopCon-Back Contact) cell. And the doping type of the doped semiconductor layer 103 located on the first region A and the doped semiconductor layer 103 located on the second region B is different, for example, the doped semiconductor layer 103 located on the first region A is N-type doped, and the doped semiconductor layer 103 located on the second region B is P-type doped, or the doped semiconductor layer 103 located on the first region A is P-type doped, and the doped semiconductor layer 103 located on the second region B is N-type doped.

[0077] Exemplarily, in another embodiment, the tunneling passivation contact structure located on the second region B can be replaced by other passivation contact structures, for example, the tunneling layer 102 and the doped semiconductor layer 103 located on the second region B are replaced by an aluminum back field as a whole, so as to form an aluminum back field passivation structure on the second region B, and the corresponding back contact solar cell can be an HPBC (Hybrid Passivated Back Contact) cell, or, for example, the tunneling layer 102 and the doped semiconductor layer 103 located on the second region B are replaced by intrinsic amorphous silicon and doped amorphous silicon arranged in sequence along the direction away from the second region, so as to form a heterojunction passivation contact structure on the second region B, and the corresponding back contact solar cell can be a hybrid BC (Back Contact) cell.

[0078] According to the embodiments of the present application, the metal crystal distribution structure of the present application can be more widely applicable to various battery types containing a tunneling passivation contact structure, thereby reducing the risk of burn-through at the side surface of the first texture structure, optimizing the current collection path, and thereby improving the battery efficiency.

[0079] The above-described specific embodiments further illustrate the purpose, technical solutions and beneficial effects of the present application, and it should be understood that the above-described specific embodiments are only specific embodiments of the present application and are not used to limit the present application, and any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. A solar cell, wherein, The solar cell comprises: a semiconductor substrate comprising a first surface having a plurality of first texture structures; the first texture structure comprises a side surface and a top surface connected to one end of the side surface along a direction away from the first surface; a tunneling layer on the first surface of the semiconductor substrate; a doped semiconductor layer on a surface of the tunneling layer away from the semiconductor substrate; an electrode on a surface of the doped semiconductor layer away from the semiconductor substrate and in contact with the doped semiconductor layer; and a metal crystal, a distribution density of the metal crystal in the doped semiconductor layer on the top surface is greater than a distribution density of the metal crystal in the doped semiconductor layer on the side surface. The first texture structure is a convex structure, and a ratio of a lateral dimension of a projection of the side surface on a plane where the top surface is located to a lateral dimension of the top surface is 0.1-0.

3.

2. The solar cell of claim 1, wherein, The lateral dimension of the projection of the side surface on the plane where the top surface is located is 0.3-3 μm, and the lateral dimension of the top surface is 5-25 μm.

3. The solar cell of claim 2, wherein, The first texture structure further comprises a bottom surface connected to another end of the side surface away from the top surface and located between side surfaces of two adjacent first texture structures; 4. The solar cell according to claim 1 or 2, wherein a distribution density of the metal crystal in the doped semiconductor layer on the bottom surface is greater than a distribution density of the metal crystal in the doped semiconductor layer on the side surface. A distance between the two adjacent first texture structures is less than or equal to 9 μm, and a height from the bottom surface to the top surface is 0.1-0.8 μm.

5. The solar cell of claim 3, wherein, The side surface has a concave curvature towards an inside of the semiconductor substrate.

6. The solar cell according to any one of claims 1 to 3, 5, wherein The metal crystal is a nanoparticle in a dendritic, dentate or flower-like shape; 7. The solar cell of claim 1, wherein, a particle size of the metal crystal is 20-200 nm. The metal crystal is an alloy containing a metal element of the electrode and a silicon element.

8. The solar cell according to claim 1 or 7, wherein The semiconductor substrate further comprises a second surface having a plurality of second texture structures, the second texture structure being a groove structure or a convex structure; 9. The solar cell of claim 1, wherein, The solar cell further comprises an emitter formed in the second surface of the semiconductor substrate. The solar cell comprises:

10. A method of producing a solar cell as claimed in any one of claims 1 to 9, wherein, texturing and polishing a first surface of an initial substrate to form a plurality of first texture structures on the first surface, thereby obtaining a semiconductor substrate; sequentially forming a tunneling layer, a doped semiconductor layer, a first passivation and anti-reflection layer and an electrode material on the first surface of the semiconductor substrate; sintering the electrode material to form an electrode, so that the electrode is in contact with the doped semiconductor layer through the first passivation and anti-reflection layer, and a metal crystal is formed in the doped semiconductor layer at a position in contact with the electrode. ​

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