Solar cell, cell assembly, and photovoltaic system

Abstract

The present disclosure is applicable to the technical field of solar cells, and provides a solar cell, a cell assembly, and a photovoltaic system. The solar cell comprises: a silicon substrate, wherein a P region and an N region are provided on the surface of the silicon substrate; a P-type doped polysilicon layer arranged in the P region; and an N-type doped polysilicon layer arranged in the N region, wherein the average grain size of the N-type doped polysilicon layer measured by X-ray diffraction analysis is greater than the average grain size of the P-type doped polysilicon layer measured by X-ray diffraction analysis. The solar cell provided by the present disclosure can reduce the difference between the diffusion temperatures of the P-type doped polysilicon layer and the N-type doped polysilicon layer, thereby being conducive to improving the production efficiency and increasing the production capacity. Moreover, the conductive effect of the P-type doped polysilicon layer can be improved, and the metallization damage to the P-type doped polysilicon layer in a cell metallization process can be reduced, thereby improving the efficiency of the cell.

Description

Solar cell, cell assembly and photovoltaic system

[0001] Priority information

[0002] The present disclosure claims priority to and the benefit of the patent application with the patent application number 202411252332.9 filed on September 6, 2024 with the China National Intellectual Property Office, and incorporates it herein by reference in its entirety. TECHNICAL FIELD

[0003] The present disclosure relates to the technical field of solar cells, in particular to a solar cell, a cell assembly and a photovoltaic system. BACKGROUND

[0004] With the increasing depletion of fossil fuels, solar energy has become the most common and clean renewable energy. Among them, a solar cell is a device that directly converts light energy into electrical energy by using the photovoltaic effect, and the solar cell mainly includes a bifacial solar cell and a back contact solar cell.

[0005] In the prior art, the P region of the solar cell is usually provided with a P-type doped polysilicon layer, the N region of the solar cell is usually provided with an N-type doped polysilicon layer, the electrode of the P region is in contact with the P-type doped polysilicon layer, and the electrode of the N region is in contact with the N-type doped polysilicon layer; in order to improve the boron diffusion effect, the diffusion temperature of the P-type doped polysilicon layer usually needs to be much higher than the diffusion temperature of the N-type doped polysilicon layer, which will cause the average grain size of the P-type doped polysilicon layer to be larger than the average grain size of the N-type doped polysilicon layer, so that the P region has a relatively poor conduction effect, especially in a weak light environment, thereby affecting the cell efficiency; moreover, it will cause the P-type doped polysilicon layer structure to be more loose, so that the metallization damage of the P-type doped polysilicon layer in the cell metallization process is serious, which will also affect the cell efficiency. SUMMARY

[0006] The present disclosure provides a solar cell, which aims to solve the problem that the P region of the solar cell in the prior art has a poor conduction effect, the metallization damage of the P-type doped polysilicon layer in the cell metallization process is serious, and thus the cell efficiency is affected.

[0007] The present disclosure is achieved in this way, which provides a solar cell, comprising:

[0008] a silicon substrate, a surface of the silicon substrate being provided with a P region and an N region;

[0009] a P-type doped polysilicon layer arranged in the P region;

[0010] an N-type doped polysilicon layer arranged in the N region;

[0011] The average grain size of the N-type doped polysilicon layer measured by X-ray diffraction analysis is greater than the average grain size of the P-type doped polysilicon layer measured by X-ray diffraction analysis.

[0012] Optionally, the grain size of the N-type doped polysilicon layer measured by X-ray diffraction analysis in the (220) orientation is greater than the grain size of the P-type doped polysilicon layer measured by X-ray diffraction analysis in the (220) orientation.

[0013] Optionally, the grain size of the N-type doped polysilicon layer measured by X-ray diffraction analysis in the (311) orientation is greater than the grain size of the P-type doped polysilicon layer measured by X-ray diffraction analysis in the (311) orientation.

[0014] Optionally, the grain size of the N-type doped polysilicon layer measured by X-ray diffraction analysis in the (111) orientation is less than the grain size of the P-type doped polysilicon layer measured by X-ray diffraction analysis in the (111) orientation.

[0015] Optionally, the number of grains of the N-type doped polysilicon layer and the P-type doped polysilicon layer in the (111), (220), and (311) orientations satisfies at least one of the following:

[0016] The proportion of the number of grains of the N-type doped polysilicon layer in the (111) orientation is greater than the proportion of the number of grains of the N-type doped polysilicon layer in the (220) or (311) orientation;

[0017] The proportion of the number of grains of the P-type doped polysilicon layer in the (111) orientation is greater than the proportion of the number of grains of the P-type doped polysilicon layer in the (220) or (311) orientation.

[0018] Optionally, the proportion of grains of the N-type doped polysilicon layer in the (111) orientation is greater than the proportion of grains of the P-type doped polysilicon layer in the (111) orientation.

[0019] Optionally, the grain spacing of the N-type doped polysilicon layer is greater than the grain spacing of the P-type doped polysilicon layer.

[0020] Optionally, the deposition temperature of the P-type doped polysilicon layer is greater than the deposition temperature of the N-type doped polysilicon layer, and the difference between the deposition temperature of the P-type doped polysilicon layer and the deposition temperature of the N-type doped polysilicon layer is less than 50°C.

[0021] Optionally, the deposition temperature of the P-type doped polysilicon layer is less than or equal to the deposition temperature of the N-type doped polysilicon layer.

[0022] Optionally, the diffusion temperature of the P-type doped polysilicon layer is greater than the diffusion temperature of the N-type doped polysilicon layer, and the difference between the diffusion temperature of the P-type doped polysilicon layer and the diffusion temperature of the N-type doped polysilicon layer is less than 30°C.

[0023] Optionally, the solar cell is a back contact solar cell, and the P region and the N region are located on the same side of the silicon substrate.

[0024] Optionally, the solar cell is a bifacial solar cell, and the P region and the N region are located on opposite sides of the silicon substrate, respectively.

[0025] The present disclosure also provides a battery assembly comprising the above-mentioned solar cell.

[0026] The present disclosure also provides a photovoltaic system comprising the above-mentioned battery assembly.

[0027] The average grain size of the N-type doped polysilicon layer of the solar cell provided by the present disclosure is larger than the average grain size of the P-type doped polysilicon layer measured by X-ray diffraction analysis. Since the average grain size of the P-type doped polysilicon layer is smaller than the average grain size of the N-type doped polysilicon layer, the difference in diffusion temperature between the P-type doped polysilicon layer and the N-type doped polysilicon layer can be reduced compared to conventional solar cells, which helps to improve production efficiency and increase production capacity. Moreover, the average grain size of the P-type doped polysilicon layer is smaller than the average grain size of the N-type doped polysilicon layer, making the structure of the P-type doped polysilicon layer more dense. On the one hand, this can improve the conductivity of the P-type doped polysilicon layer, especially the conductivity of the P region in a weak light environment, thereby significantly improving the battery efficiency of the solar cell in a weak light environment. On the other hand, since the structure of the P-type doped polysilicon layer is more dense, it can to some extent block the metallization damage to the P-type doped polysilicon layer during the battery metallization process, thereby improving the battery efficiency. BRIEF DESCRIPTION OF DRAWINGS

[0028] FIG. 1 is a schematic diagram of a solar cell according to an embodiment of the present disclosure;

[0029] FIG. 2 is a schematic diagram of another solar cell according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0030] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the present disclosure will be further described in detail below in combination with the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present disclosure and do not limit the present disclosure.

[0031] The average grain size of the N-type doped polysilicon layer of the solar cell provided by the embodiment of the present disclosure is larger than the average grain size of the P-type doped polysilicon layer measured by X-ray diffraction analysis. Since the average grain size of the P-type doped polysilicon layer is smaller than the average grain size of the N-type doped polysilicon layer, compared with the traditional solar cell, the difference between the deposition and diffusion temperature of the P-type doped polysilicon layer and the diffusion temperature of the N-type doped polysilicon layer can be reduced, which is conducive to improving the production efficiency and increasing the production capacity. Moreover, the average grain size of the P-type doped polysilicon layer is smaller than the average grain size of the N-type doped polysilicon layer, so that the structure of the P-type doped polysilicon layer is more compact. On the one hand, the conductivity of the P-type doped polysilicon layer can be improved, especially the conductivity of the P-type doped polysilicon layer in a weak light environment, so that the cell efficiency of the solar cell in a weak light environment can be significantly improved. On the other hand, since the structure of the P-type doped polysilicon layer is more compact, the metallization damage of the P-type doped polysilicon layer in the cell metallization process can be blocked to a certain extent, so that the cell efficiency can be improved.

[0032] Please refer to FIG. 1-FIG. 2, the solar cell provided by the embodiment of the present disclosure comprises:

[0033] The silicon substrate 1 is provided with a P-type region 11 and an N-type region 12 on the surface thereof.

[0034] The P-type doped polysilicon layer 2 is arranged on the P-type region 11.

[0035] The N-type doped polysilicon layer 3 is arranged on the N-type region 12.

[0036] The average grain size of the N-type doped polysilicon layer 3 measured by X-ray diffraction analysis is larger than the average grain size of the P-type doped polysilicon layer 2 measured by X-ray diffraction analysis.

[0037] In the embodiment of the present disclosure, the average grain size of the N-type doped polysilicon layer 3 measured by X-ray diffraction analysis is the average value of the grain size of the orientation (111) measured by X-ray diffraction analysis, the grain size of the orientation (220) measured by X-ray diffraction analysis and the grain size of the orientation (311) measured by X-ray diffraction analysis of the N-type doped polysilicon layer 3. The average grain size of the P-type doped polysilicon layer 2 measured by X-ray diffraction analysis is the average value of the grain size of the orientation (111) measured by X-ray diffraction analysis, the grain size of the orientation (220) measured by X-ray diffraction analysis and the grain size of the orientation (311) measured by X-ray diffraction analysis of the P-type doped polysilicon layer 2.

[0038] In the embodiments of the present disclosure, when the average grain size of the N-type doped polysilicon layer 3 and the P-type doped polysilicon layer 2 is measured by X-ray diffraction analysis, the signal intensity peaks are reached in three diffraction directions, that is, the signal intensity peaks are detected in the orientation (111), the orientation (220), and the orientation (311) by X-ray diffraction analysis, and then the grain sizes of the N-type doped polysilicon layer 3 and the P-type doped polysilicon layer 2 in the orientation (111), the orientation (220), and the orientation (311) are calculated respectively according to the signal intensity peaks, and then the weighted average value of the grain sizes of the N-type doped polysilicon layer 3 and the P-type doped polysilicon layer 2 in the orientation (111), the orientation (220), and the orientation (311) is calculated, so as to obtain the average grain sizes of the N-type doped polysilicon layer 3 and the P-type doped polysilicon layer 2. The principle of measuring the grain size by X-ray diffraction analysis belongs to the existing conventional technology, and will not be described here.

[0039] The average grain size of the N-type doped polysilicon layer 3 of the solar cell provided in the embodiments of the present disclosure is greater than the average grain size of the P-type doped polysilicon layer 2 measured by X-ray diffraction analysis. Since the average grain size of the P-type doped polysilicon layer 2 is smaller than the average grain size of the N-type doped polysilicon layer 3, compared with the conventional solar cell, the diffusion temperature of the P-type doped polysilicon layer 2 can be reduced, so as to reduce the difference between the diffusion temperature of the P-type doped polysilicon layer 2 and the diffusion temperature of the N-type doped polysilicon layer 3, which can help to improve the production efficiency and increase the production capacity. Moreover, the average grain size of the P-type doped polysilicon layer 2 is smaller than the average grain size of the N-type doped polysilicon layer 3, so that the structure of the P-type doped polysilicon layer 2 is more compact. On the one hand, the conductivity of the P-type doped polysilicon layer 2, especially the conductivity of the P region 11 in the weak light environment, can be improved, so that the cell efficiency of the solar cell in the weak light environment can be obviously improved. On the other hand, since the structure of the P-type doped polysilicon layer 2 is more compact, the metallization damage of the P-type doped polysilicon layer 2 in the cell metallization process can be blocked to a certain extent, so as to improve the cell efficiency.

[0040] In the embodiments of the present disclosure, the silicon substrate 1 can be a P-type silicon substrate or an N-type silicon substrate. The surface of the silicon substrate 1 can be the back light surface or the light surface of the solar cell.

[0041] Referring to FIG. 1, as an embodiment of the present disclosure, the solar cell is a back contact solar cell, and the P region 11 and the N region 12 are located on the same surface of the silicon substrate 1. The silicon substrate 1 includes a front surface 101 and a back surface 102 opposite to the front surface 101. The front surface 101 of the silicon substrate 1 is the light surface of the back contact solar cell, the back surface 102 of the silicon substrate 1 is the back light surface of the back contact solar cell, and the P region 11 and the N region 12 are both located on the back surface 102 of the silicon substrate 1.

[0042] The P region 11 and the N region 12 are both multiple, the multiple P regions 11 and the multiple N regions 12 are alternately and spacedly arranged, and the adjacent P region 11 and the N region 12 are provided with the isolation region 13. The isolation region 13 can be a groove or a gap.

[0043] Referring to FIG. 2, as another embodiment of the present disclosure, the solar cell is a bifacial solar cell, and the P region 11 and the N region 12 are respectively located on opposite sides of the silicon substrate 1. The silicon substrate 1 includes a front surface 101 and a back surface 102 opposite to the front surface 101, the front surface 101 of the silicon substrate 1 is a light-receiving surface of the bifacial solar cell, the back surface 102 of the silicon substrate 1 is a back surface of the bifacial solar cell, and one of the P region 11 and the N region 12 is located on the front surface 101 of the silicon substrate 1, and the other is located on the back surface 102 of the silicon substrate 1.

[0044] The P region 11 and the N region 12 are both multiple, the multiple P regions 11 and the multiple N regions 12 are alternately and spacedly arranged, and the adjacent P region 11 and the N region 12 are provided with the isolation region 13. The isolation region 13 can be a groove or a gap.

[0045] In the embodiment of the present disclosure, the P-type doped polysilicon layer 2 is a P-type doped polysilicon containing a P-type dopant, and the N-type doped polysilicon layer 3 is an N-type doped polysilicon containing an N-type dopant. The P-type dopant is a Group IIIA element dopant, and the N-type dopant is a Group VA element dopant. For example, the P-type dopant can be a boron dopant, and the N-type dopant can be a phosphorus dopant.

[0046] As an embodiment of the present disclosure, the grain size of the orientation (220) of the N-type doped polysilicon layer 3 measured by X-ray diffraction analysis is greater than the grain size of the orientation (220) of the P-type doped polysilicon layer 2 measured by X-ray diffraction analysis.

[0047] In the embodiment, the grain size of the orientation (220) of the N-type doped polysilicon layer 3 measured by X-ray diffraction analysis is greater than the grain size of the orientation (220) of the P-type doped polysilicon layer 2 measured by X-ray diffraction analysis, which is conducive to realizing that the average grain size of the N-type doped polysilicon layer 3 is greater than the average grain size of the P-type doped polysilicon layer 2.

[0048] As one embodiment of the present disclosure, the grain size of the N-type doped polysilicon layer 3 measured by X-ray diffraction analysis in the (311) orientation is greater than the grain size of the P-type doped polysilicon layer 2 measured by X-ray diffraction analysis in the (311) orientation, which is conducive to further realizing that the average grain size of the N-type doped polysilicon layer 3 is greater than the average grain size of the P-type doped polysilicon layer 2.

[0049] As one embodiment of the present disclosure, the grain size of the N-type doped polysilicon layer 3 measured by X-ray diffraction analysis in the (111) orientation is less than the grain size of the P-type doped polysilicon layer 2 measured by X-ray diffraction analysis in the (111) orientation.

[0050] As one embodiment of the present disclosure, the number of grains of the N-type doped polysilicon layer 3 and the P-type doped polysilicon layer 2 in the (111) orientation, the (220) orientation, and the (311) orientation satisfies at least one of the following:

[0051] The proportion of the number of grains of the N-type doped polysilicon layer 3 in the (111) orientation is greater than the proportion of the number of grains of the N-type doped polysilicon layer 3 in the (220) orientation or the (311) orientation;

[0052] The proportion of the number of grains of the P-type doped polysilicon layer 2 in the (111) orientation is greater than the proportion of the number of grains of the P-type doped polysilicon layer 2 in the (220) orientation or the (311) orientation.

[0053] In the present embodiment, the proportion of the number of grains of the N-type doped polysilicon layer 3 in the (111) orientation is greater than the proportion of the number of grains of the N-type doped polysilicon layer 3 in the (220) orientation or the (311) orientation, that is, the number of grains of the N-type doped polysilicon layer 3 grown in the (111) orientation is the most, so that the grains of the N-type doped polysilicon layer 3 grow more concentrated in the (111) orientation, so that the structure of the N-type doped polysilicon layer 3 is more uniform and dense. The proportion of the number of grains of the P-type doped polysilicon layer 2 in the (111) orientation is greater than the proportion of the number of grains of the P-type doped polysilicon layer 2 in the (220) orientation or the (311) orientation, that is, the number of grains of the P-type doped polysilicon layer 2 grown in the (111) orientation is the most, so that the grains of the P-type doped polysilicon layer 2 grow more concentrated in the (111) orientation, so that the structure of the P-type doped polysilicon layer 2 is more uniform and dense.

[0054] As one embodiment of the present disclosure, the proportion of the number of grains of the N-type doped polysilicon layer 3 in the (111) orientation is greater than the proportion of the number of grains of the P-type doped polysilicon layer 2 in the (111) orientation.

[0055] In the embodiment, the proportion of grains in the N-type doped polysilicon layer 3 in the (111) orientation is greater than the proportion of grains in the P-type doped polysilicon layer 2 in the (111) orientation. The proportion of grains in the N-type doped polysilicon layer 3 in the (111) orientation can be understood as the percentage of the number of grains in the N-type doped polysilicon layer 3 growing in the (111) orientation to the total number of grains in the N-type doped polysilicon layer 3. The proportion of grains in the P-type doped polysilicon layer 2 in the (111) orientation can be understood as the percentage of the number of grains in the P-type doped polysilicon layer 2 growing in the (111) orientation to the total number of grains in the P-type doped polysilicon layer 2.

[0056] In the embodiment, the proportion of grains in the N-type doped polysilicon layer 3 in the (111) orientation is greater than the proportion of grains in the P-type doped polysilicon layer 2 in the (111) orientation. More grains in the N-type doped polysilicon layer 3 grow in the (111) orientation, that is, the grains in the N-type doped polysilicon layer 3 are more concentrated in the (111) orientation, so that the structure of the N-type doped polysilicon layer 3 is more uniform and dense.

[0057] As an embodiment of the present disclosure, the grain spacing of the N-type doped polysilicon layer 3 is greater than the grain spacing of the P-type doped polysilicon layer 2.

[0058] In the embodiment, the grain spacing of the N-type doped polysilicon layer 3 and the grain spacing of the P-type doped polysilicon layer 2 can be measured by X-ray diffraction analysis. The grain spacing of the N-type doped polysilicon layer 3 is greater than the grain spacing of the P-type doped polysilicon layer 2, that is, the grain spacing of the P-type doped polysilicon layer 2 is smaller, and the structure of the P-type doped polysilicon layer 2 is more dense. This can reduce the metallization damage of the structure of the P-type doped polysilicon layer 2, and at the same time improve the conductivity of the P-type doped polysilicon layer 2 and the battery efficiency.

[0059] In the embodiment, the grain spacing of the N-type doped polysilicon layer 3 is greater than the grain spacing of the P-type doped polysilicon layer 2. The grain spacing of the N-type doped polysilicon layer 3 is the average grain spacing of the N-type doped polysilicon layer 3. The grain spacing of the P-type doped polysilicon layer 2 is the average grain spacing of the P-type doped polysilicon layer 2. Alternatively, the grain spacing of the N-type doped polysilicon layer 3 can also be less than or equal to the grain spacing of the P-type doped polysilicon layer 2.

[0060] As an embodiment of the present disclosure, the deposition temperature of the P-type doped polysilicon layer 2 is greater than the deposition temperature of the N-type doped polysilicon layer 3, and the difference between the deposition temperature of the P-type doped polysilicon layer 2 and the deposition temperature of the N-type doped polysilicon layer 3 is less than 50°C.

[0061] In this embodiment, the deposition temperature of the P-type doped polysilicon layer 2 is the temperature of depositing intrinsic amorphous silicon of the P-type doped polysilicon layer 2; and the deposition temperature of the N-type doped polysilicon layer 3 is the temperature of depositing intrinsic amorphous silicon of the N-type doped polysilicon layer 3. The deposition temperature of the P-type doped polysilicon layer 2 is greater than the deposition temperature of the N-type doped polysilicon layer 3, and the difference between the deposition temperature of the P-type doped polysilicon layer 2 and the deposition temperature of the N-type doped polysilicon layer 3 is less than 50℃, so that the average grain size of the P-type doped polysilicon layer 2 is smaller than the average grain size of the N-type doped polysilicon layer 3, and the difference between the deposition temperature of the P-type doped polysilicon layer 2 and the deposition temperature of the N-type doped polysilicon layer 3 can be reduced, which is beneficial to improving production efficiency and increasing production capacity.

[0062] As an embodiment of the present disclosure, the deposition temperature of the P-type doped polysilicon layer 2 is 300-600℃, and the deposition temperature of the N-type doped polysilicon layer 3 is 250-550℃.

[0063] In this embodiment, the deposition temperature of the P-type doped polysilicon layer 2 and the specific deposition temperature of the N-type doped polysilicon layer 3 can be flexibly set according to actual conditions.

[0064] As another embodiment of the present disclosure, the deposition temperature of the P-type doped polysilicon layer 2 is less than or equal to the deposition temperature of the N-type doped polysilicon layer 3.

[0065] In this embodiment, the deposition temperature of the P-type doped polysilicon layer 2 is less than or equal to the deposition temperature of the N-type doped polysilicon layer 3, and at the same time, the average grain size of the P-type doped polysilicon layer 2 is smaller than the average grain size of the N-type doped polysilicon layer 3, which is beneficial to improving production efficiency and increasing production capacity.

[0066] As an embodiment of the present disclosure, the diffusion temperature of the P-type doped polysilicon layer 2 is greater than the diffusion temperature of the N-type doped polysilicon layer 3, and the difference between the diffusion temperature of the P-type doped polysilicon layer 2 and the diffusion temperature of the N-type doped polysilicon layer 3 is less than 30℃.

[0067] In this embodiment, the diffusion temperature of the P-type doped polysilicon layer 2 is the temperature of diffusing intrinsic amorphous silicon of the P-type doped polysilicon layer 2 to form the P-type doped polysilicon layer 2; and the diffusion temperature of the N-type doped polysilicon layer 3 is the temperature of diffusing intrinsic amorphous silicon of the N-type doped polysilicon layer 3 to form the N-type doped polysilicon layer 3.

[0068] In the embodiment, the diffusion temperature of the P-type doped polysilicon layer 2 is greater than the diffusion temperature of the N-type doped polysilicon layer 3, and the difference between the diffusion temperature of the P-type doped polysilicon layer 2 and the diffusion temperature of the N-type doped polysilicon layer 3 is less than 30℃. In this way, the average grain size of the P-type doped polysilicon layer 2 is smaller than the average grain size of the N-type doped polysilicon layer 3, and the difference between the diffusion temperature of the P-type doped polysilicon layer 2 and the diffusion temperature of the N-type doped polysilicon layer 3 can be reduced, which is beneficial to improving production efficiency and increasing production capacity.

[0069] As an embodiment of the present disclosure, the diffusion temperature of the P-type doped polysilicon layer 2 is 850-950℃, and the diffusion temperature of the N-type doped polysilicon layer 3 is 820-920℃.

[0070] In the embodiment, the diffusion temperature of the P-type doped polysilicon layer 2 and the diffusion temperature of the N-type doped polysilicon layer 3 can be flexibly set according to actual conditions.

[0071] As an embodiment of the present disclosure, the solar cell further comprises:

[0072] The first passivation layer 4 is located in the P region 11 and arranged on the surface of the silicon substrate 1, and the P-type doped polysilicon layer 2 is arranged on the side of the first passivation layer 4 away from the silicon substrate 1.

[0073] The second passivation layer 5 is located in the N region 12 and arranged on the surface of the silicon substrate 1, and the N-type doped polysilicon layer 3 is arranged on the side of the second passivation layer 5 away from the silicon substrate 1.

[0074] In the embodiment, the first passivation layer 4 and the second passivation layer 5 realize tunnel passivation, which can improve the efficiency of the cell.

[0075] As an embodiment of the present disclosure, the solar cell further comprises:

[0076] The first electrode 6 is arranged in the P region 11 and in contact with the P-type doped polysilicon layer 2.

[0077] The second electrode 7 is arranged in the N region 12 and in contact with the N-type doped polysilicon layer 3.

[0078] In the embodiment, the first electrode 6 forms ohmic contact with the P-type doped polysilicon layer 2, and the second electrode 7 forms ohmic contact with the N-type doped polysilicon layer 3. Optionally, the depth of the first electrode 6 into the P-type doped polysilicon layer 2 is greater than the depth of the second electrode 7 into the N-type doped polysilicon layer 3, which can increase the contact area of the first electrode 6 with the P-type doped polysilicon layer 2, further improve the conductivity of the P region 11, and improve the efficiency of the cell.

[0079] As an embodiment of the present disclosure, the solar cell further comprises:

[0080] A first back passivation layer 8 is arranged on the side of the P-type doped polysilicon layer 2 away from the silicon substrate 1.

[0081] A second back passivation layer 9 is arranged on the side of the N-type doped polysilicon layer 3 away from the silicon substrate 1.

[0082] In some embodiments, the first back passivation layer 8 and the second back passivation layer 9 can include an aluminum oxide film layer and a silicon nitride film layer stacked in sequence, without limitation.

[0083] In this embodiment, the first back passivation layer 8 and the second back passivation layer 9 can further improve the passivation effect of the battery and improve the battery efficiency.

[0084] The present disclosure also provides a battery assembly including the solar cell of the above embodiment. It should be noted that the battery assembly and the solar cell have the same or similar beneficial effects, and the related parts between the two can be referred to each other, and to avoid repetition, this will not be repeated here.

[0085] The present disclosure also provides a photovoltaic system including the battery assembly of the above embodiment. It should be noted that the battery assembly and the solar cell have the same or similar beneficial effects, and the related parts between the two can be referred to each other, and to avoid repetition, this will not be repeated here.

[0086] The average grain size of the N-type doped polysilicon layer of the solar cell provided by the present disclosure is larger than the average grain size of the P-type doped polysilicon layer measured by X-ray diffraction analysis. Since the average grain size of the P-type doped polysilicon layer is smaller than that of the N-type doped polysilicon layer, compared with the traditional solar cell, the difference between the diffusion temperature of the P-type doped polysilicon layer and the diffusion temperature of the N-type doped polysilicon layer can be reduced, which is beneficial to improve the production efficiency and increase the production capacity. Moreover, the average grain size of the P-type doped polysilicon layer is smaller than that of the N-type doped polysilicon layer, which makes the structure of the P-type doped polysilicon layer more dense. On the one hand, it can improve the conductivity of the P-type doped polysilicon layer, especially the conductivity of the P-type doped polysilicon layer in a weak light environment, thereby significantly improving the battery efficiency of the solar cell in a weak light environment. On the other hand, since the structure of the P-type doped polysilicon layer is more dense, it can block the metalization damage of the P-type doped polysilicon layer to a certain extent during the battery metallization process, thereby improving the battery efficiency.

[0087] The above merely preferred embodiments of the present disclosure and are not intended to limit the present disclosure. Therefore, any modification, equivalent replacement and improvement made without departing from the spirit and principle of the present disclosure shall fall within the protection scope of the present disclosure.

Claims

1. A solar cell, wherein, The solar cell comprises: a silicon substrate, a surface of the silicon substrate being provided with a P region and an N region; a P-type doped polysilicon layer provided on the P region; an N-type doped polysilicon layer provided on the N region; wherein the average grain size of the N-type doped polysilicon layer measured by X-ray diffraction analysis is greater than the average grain size of the P-type doped polysilicon layer measured by X-ray diffraction analysis.

2. The solar cell of claim 1, wherein, The grain size of the N-type doped polysilicon layer measured by X-ray diffraction analysis in the orientation (220) is greater than the grain size of the P-type doped polysilicon layer measured by X-ray diffraction analysis in the orientation (220).

3. The solar cell of claim 1, wherein, The grain size of the N-type doped polysilicon layer measured by X-ray diffraction analysis in the orientation (311) is greater than the grain size of the P-type doped polysilicon layer measured by X-ray diffraction analysis in the orientation (311).

4. The solar cell of claim 1, wherein, The grain size of the N-type doped polysilicon layer measured by X-ray diffraction analysis in the orientation (111) is less than the grain size of the P-type doped polysilicon layer measured by X-ray diffraction analysis in the orientation (111).

5. The solar cell of claim 1, wherein, The number of grains of the N-type doped polysilicon layer and the P-type doped polysilicon layer in the orientation (111), the orientation (220) and the orientation (311) satisfies at least one of the following conditions: The proportion of the number of grains of the N-type doped polysilicon layer in the orientation (111) is greater than the proportion of the number of grains of the N-type doped polysilicon layer in the orientation (220) or the orientation (311). The proportion of the number of grains of the P-type doped polysilicon layer in the orientation (111) is greater than the proportion of the number of grains of the P-type doped polysilicon layer in the orientation (220) or the orientation (311).

6. The solar cell of claim 1, wherein, The proportion of the number of grains of the N-type doped polysilicon layer in the orientation (111) is greater than the proportion of the number of grains of the P-type doped polysilicon layer in the orientation (111).

7. The solar cell of claim 1, wherein, The grain spacing of the N-type doped polysilicon layer is greater than the grain spacing of the P-type doped polysilicon layer.

8. The solar cell of claim 1, wherein, The deposition temperature of the P-type doped polysilicon layer is greater than the deposition temperature of the N-type doped polysilicon layer, and the difference between the deposition temperature of the P-type doped polysilicon layer and the deposition temperature of the N-type doped polysilicon layer is less than 50°C.

9. The solar cell of claim 1, wherein, The deposition temperature of the P-type doped polysilicon layer is less than or equal to the deposition temperature of the N-type doped polysilicon layer.

10. The solar cell of claim 1, wherein, The diffusion temperature of the P-type doped polysilicon layer is greater than the diffusion temperature of the N-type doped polysilicon layer, and the difference between the diffusion temperature of the P-type doped polysilicon layer and the diffusion temperature of the N-type doped polysilicon layer is less than 30°C.

11. The solar cell of claim 1, wherein, The solar cell is a back contact solar cell, and the P region and the N region are located on the same surface of the silicon substrate.

12. The solar cell of claim 1, wherein, The solar cell is a bifacial solar cell, and the P region and the N region are located on opposite surfaces of the silicon substrate, respectively.

13. A battery assembly, wherein, The battery assembly comprises the solar cell according to any one of claims 1-12.

14. A photovoltaic system, wherein, The battery assembly comprises the solar cell according to claim 13.

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