Reconfigurable power amplifier, control method, communication device, and storage medium

Abstract

Embodiments of the present application relate to, but are not limited to, the technical field of communications, and provide a reconfigurable power amplifier, a control method, a communication device, and a storage medium. The reconfigurable power amplifier comprises a main power amplifier, an auxiliary power amplifier, and a combiner unit; the main power amplifier and the auxiliary power amplifier each comprise an input matching unit, a power amplification unit, and an output matching unit which are connected in sequence, and the output matching unit has a bias voltage end; and the output ends of the main power amplifier and the auxiliary power amplifier each are connected to the combiner unit.

Description

Reconfigurable power amplifier, control method, communication device and storage medium

[0001] Cross-reference to Related Applications

[0002] The present application is based on and claims priority to Chinese Patent Application No. 2024112378429, filed on September 4, 2024, the entire contents of which are incorporated herein by reference. TECHNICAL FIELD

[0003] Embodiments of the present application relate to the field of communication technology, and in particular to a reconfigurable power amplifier, a control method, a communication device and a storage medium. BACKGROUND

[0004] With the rapid development of modern communication technology, the performance requirements for communication circuits are also becoming higher and higher. As a core component of a communication base station, the performance of a power amplifier is directly related to the core competitiveness of the communication base station. A reconfigurable power amplifier flexibly realizes the reconfigurable characteristics of power and efficiency, and has better system performance.

[0005] For a reconfigurable power amplifier of a traditional scheme, a fixed drain bias voltage is adopted, and the reconfigurable power amplifier is mainly implemented based on a reconfigurable matching circuit. Switching elements are added in the reconfigurable matching circuit, and different capacitances are connected by using the on and off states of the switching elements, so as to change the impedance characteristics and phase characteristics of the reconfigurable matching circuit, and realize the reconfigurable characteristics of power and efficiency. The switching elements of the adjustable matching circuit introduce parasitic parameters, increase the insertion loss of the circuit, and cause the performance of power and efficiency to decrease. If a large range of reconfigurable characteristics needs to be realized, a large number of switching elements need to be added, which not only causes the performance to decrease, but also greatly increases the cost, and affects the competitiveness of the product. SUMMARY

[0006] Embodiments of the present application provide a reconfigurable power amplifier, a control method, a communication device and a storage medium.

[0007] In a first aspect, embodiments of the present application provide a reconfigurable power amplifier, comprising a main-path power amplifier, an auxiliary-path power amplifier and a combining unit.

[0008] The main-path power amplifier and the auxiliary-path power amplifier each comprise an input matching unit, a power amplification unit and an output matching unit connected in sequence, and the output matching unit has a bias voltage terminal.

[0009] The output end of the main-path power amplifier and the output end of the auxiliary-path power amplifier are connected to the combining unit, respectively.

[0010] In a second aspect, an embodiment of the present application provides a control method applied to a reconfigurable power amplifier, the reconfigurable power amplifier comprising a main-path power amplifier, an auxiliary-path power amplifier, and a combining unit, an output end of the main-path power amplifier and an output end of the auxiliary-path power amplifier being connected to the combining unit respectively, the method comprising:

[0011] controlling a size of a bias voltage of the main-path power amplifier and the auxiliary-path power amplifier to adjust an output efficiency.

[0012] In a third aspect, an embodiment of the present application provides an electronic device comprising a processor and a memory, the memory storing a program or instructions executable on the processor, the program or instructions being executed by the processor to implement the control method according to the second aspect.

[0013] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium having a computer program stored thereon, the program being executed by a processor to implement the control method according to the second aspect. BRIEF DESCRIPTION OF DRAWINGS

[0014] The accompanying drawings are used to provide a further understanding of the technical scheme of the present application, and constitute a part of the specification, and are used to explain the technical scheme of the present application together with the embodiments of the present application, and do not constitute a limitation on the technical scheme of the present application.

[0015] FIG. 1 is a reconfigurable power amplifier provided by the related art;

[0016] FIG. 2 is a reconfigurable matching circuit provided by the related art;

[0017] FIG. 3a is a structural schematic diagram of a reconfigurable power amplifier provided by an embodiment of the present application;

[0018] FIG. 3b is a structural schematic diagram of a reconfigurable power amplifier provided by another embodiment of the present application;

[0019] FIG. 4 is a structural schematic diagram of a reconfigurable power amplifier provided by another embodiment of the present application;

[0020] FIG. 5 is a structural schematic diagram of a reconfigurable power amplifier provided by another embodiment of the present application;

[0021] FIG. 6 is a circuit schematic diagram of a combining unit provided by an embodiment of the present application;

[0022] FIG. 7 is a circuit schematic diagram of a reconfigurable power amplifier provided by another embodiment of the present application;

[0023] FIG. 8 is a structural schematic diagram of a reconfigurable power amplifier provided by another embodiment of the present application;

[0024] Fig. 9 is a structural schematic diagram of a reconfigurable power amplifier according to another embodiment of the present application;

[0025] Fig. 10 is a circuit schematic diagram of a reconfigurable power amplifier according to another embodiment of the present application;

[0026] Fig. 11 is a schematic diagram of efficiency curves under voltage configuration according to an embodiment of the present application;

[0027] Fig. 12 is a schematic diagram of efficiency curves under voltage configuration according to another embodiment of the present application;

[0028] Fig. 13 is a structural schematic diagram of a controller according to an embodiment of the present application. DETAILED DESCRIPTION

[0029] In order to make the objects, technical solutions and advantages of the present application clearer, further detailed description will be given to the present application in combination with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application, and are not used to limit the present application.

[0030] It should be understood that, in the description of the embodiments of the present application, if there is description to "first", "second", etc., it is only for the purpose of distinguishing technical features, and it cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features or the sequence of indicated technical features. "At least one" means one or more, and "multiple" means two or more. "And / or" describes the association relationship of the associated objects, which means that there can be three kinds of relationships, for example, A and / or B can represent the cases of A alone, A and B together, and B alone. Wherein A and B can be singular or plural. The character " / " generally represents an "or" relationship between the front and rear associated objects. "At least one of the following" and the like means any group of these items, including any group of single items or multiple items. For example, at least one of a, b and c can represent: a, b, c, a and b, a and c, b and c, or a and b and c, wherein a, b, c can be single or multiple.

[0031] In addition, the technical features involved in each embodiment of the present application described below can be combined with each other as long as there is no conflict.

[0032] In order to facilitate the understanding of the scheme of the embodiments of the present application and the clear, concise description of each of the following embodiments, first give a brief introduction of related art:

[0033] With the rapid development of modern communication technology, the performance requirements of communication circuits are also increasing. As the core component of a communication base station, the performance of a power amplifier is directly related to the core competitiveness of the communication base station. A reconfigurable power amplifier flexibly realizes the reconfigurable characteristics of power and efficiency, and has better system performance.

[0034] As shown in FIG. 1, for a reconfigurable power amplifier of a traditional scheme, a fixed drain bias voltage is adopted, and the reconfigurable power amplifier is mainly implemented based on a reconfigurable matching circuit. As shown in FIG. 2, a switch element (S1, S2) is added to the reconfigurable matching circuit, different capacitances (C2, C3) are connected by using the on and off states of the switch element, the impedance characteristics and phase characteristics of the reconfigurable matching circuit are changed, and the reconfigurable characteristics of power and efficiency are realized. The switch element of the adjustable matching circuit introduces parasitic parameters, increases the insertion loss of the circuit, and causes the performance of power and efficiency to decrease. If a large range of reconfigurable characteristics need to be realized, a large number of switch elements need to be added, which not only causes the performance to decrease, but also causes the cost to greatly increase, and affects the competitiveness of the product.

[0035] Based on this, the embodiments of the present application provide a reconfigurable power amplifier, a control method, a communication device and a storage medium, aiming to reduce the insertion loss of the reconfigurable power amplifier and improve the performance of the reconfigurable power amplifier.

[0036] As shown in FIG. 3a and FIG. 3b, FIG. 3a is a structural schematic diagram of a reconfigurable power amplifier provided by the embodiments of the present application; and FIG. 3b is a structural schematic diagram of a reconfigurable power amplifier provided by another embodiment of the present application.

[0037] In one possible embodiment, the reconfigurable power amplifier includes a main-path power amplifier, an auxiliary-path power amplifier and a combining unit; the main-path power amplifier and the auxiliary-path power amplifier each include an input matching unit, a power amplification unit and an output matching unit connected in sequence, and the output matching unit has a bias voltage terminal; and the output terminal of the main-path power amplifier and the output terminal of the auxiliary-path power amplifier are connected to the combining unit respectively.

[0038] It should be noted that the main-path power amplifier and the auxiliary-path power amplifier of the embodiments of the present application each have a bias voltage terminal, and by controlling the size of the bias voltage on the bias voltage terminal of the main-path power amplifier and the auxiliary-path power amplifier, the output power configuration and the output efficiency configuration of the main-path power amplifier and the auxiliary-path power amplifier can be reconfigured. Compared with the current method of adding a switch element to a reconfigurable power amplifier, the embodiments of the present application can realize the purpose of reducing the insertion loss of the reconfigurable power amplifier as much as possible and improving the performance of the reconfigurable power amplifier.

[0039] It can be understood that the combining unit is used to combine the output signals of the main-path power amplifier and the auxiliary-path power amplifier, and complete the preset impedance conversion function.

[0040] Exemplarily, the reconfigurable power amplifier has a main path input end, an auxiliary path input end and an output end, the main path input end is connected to the main path power amplifier, the auxiliary path input end is connected to the auxiliary path power amplifier, and the output end is connected to the combining unit.

[0041] Exemplarily, the bias voltage of the auxiliary path power amplifier is greater than or equal to the bias voltage of the main path power amplifier.

[0042] Exemplarily, the power amplifying unit is used to complete the power amplifying function of the input signal.

[0043] Specifically, in a possible embodiment, the input matching unit includes a first input matching unit and a second input matching unit, wherein the first input matching unit is used to transform the input impedance of the power amplifying unit to a first preset impedance, and the second input matching unit is used to transform the first preset impedance to a first target impedance.

[0044] It can be understood that the input impedance can be 0.2 ohms, can be 2 ohms, can be 5 ohms, or can be between 0.2 ohms and 5 ohms, and the size of the input impedance is not specifically limited in the embodiment of the application.

[0045] It can be understood that the first preset impedance can be 2 ohms, can be 20 ohms, can be 40 ohms, or can be between 2 ohms and 40 ohms, and the size of the first preset impedance is not specifically limited in the embodiment of the application.

[0046] It can be understood that the first target impedance value can be 50 ohms, and can be set according to actual needs, and the size of the first target impedance value is not specifically limited in the embodiment of the application.

[0047] Exemplarily, the first input matching unit transforms the input impedance of 0.2 ohms of the power amplifying unit to the first preset impedance of 2 ohms, and the second input matching unit transforms the first preset impedance to the first target impedance value of 50 ohms.

[0048] Exemplarily, the first input matching unit transforms the input impedance of 5 ohms of the power amplifying unit to the first preset impedance of 40 ohms, and the second input matching unit transforms the first preset impedance to the first target impedance value of 50 ohms.

[0049] Exemplarily, the second input matching unit also has a phase shift function and completes a specific phase shift amount according to actual needs.

[0050] It can be understood that the first input matching unit can be an input inner matching unit, and the second input matching unit can be an input outer matching unit.

[0051] Specifically, in one possible embodiment, the output matching unit comprises a first output matching unit and a second output matching unit, wherein the first output matching unit is configured to transform the output impedance of the power amplification unit to a second preset impedance value; the second output matching unit is configured to transform the second preset impedance value to a second target impedance value, and access a bias voltage.

[0052] For example, the first output matching unit also has a second harmonic control function and a video bandwidth expansion function; the second output matching unit also has a drain bias voltage supply function.

[0053] For example, the second output matching unit of the auxiliary path power amplifier also has a phase shift function, and completes a specific phase shift amount according to actual needs.

[0054] It can be understood that the first output matching unit can be an output inner matching unit, and the second output matching unit can be an output outer matching unit.

[0055] For example, the main path input signal passes through the first input matching unit of the main path power amplifier, enters the second input matching unit, and then enters the power amplification unit for signal amplification. The amplified signal passes through the first output matching unit and then enters the second output matching unit.

[0056] For example, the auxiliary path input signal passes through the first input matching unit of the auxiliary path power amplifier, enters the second input matching unit, and then enters the power amplification unit for signal amplification. The amplified signal passes through the first output matching unit and then enters the second output matching unit.

[0057] For example, the bias voltage of the main path power amplifier is connected to the power amplification unit through the second output matching unit and the first output matching unit of the main path power amplifier; the bias voltage of the auxiliary path power amplifier is connected to the power amplification unit through the second output matching unit and the first output matching unit of the auxiliary path power amplifier.

[0058] For example, the first input matching unit, the power amplification unit and the first output matching unit form a packaged device.

[0059] For example, the bias voltage of the reconfigurable power amplifier is V DM , V DA . The reconfigurable power amplifier has two maximum efficiency points. By configuring V DM , V DA , the positions of the two maximum efficiency points can be reconfigured.

[0060] When the input signal is small, only the power amplification unit of the main path power amplifier works, and the power amplification units of the auxiliary path power amplifiers are in an off state. The main path input signal passes through the second input matching unit and the first input matching unit, enters the power amplification unit of the main path power amplifier for power amplification, and the amplified signal passes through the first output matching unit and the second output matching unit, and then is output through the combining unit.

[0061] When the output signal reaches the average output power, the output efficiency reaches the first maximum efficiency point. At this time, the auxiliary path power amplifier starts to work, and when the auxiliary path power amplifier reaches the preset output power, the output efficiency reaches the second maximum efficiency point, and the power amplification units of the main path power amplifier and the auxiliary path power amplifier both reach the saturation power state.

[0062] The saturation power of the main path power amplifier is reduced by reducing the bias voltage of the main path power amplifier, and the saturation power of the auxiliary path power amplifier is increased by increasing the bias voltage of the auxiliary path power amplifier. The reduced saturation power of the main path power amplifier and the increased saturation power of the auxiliary path power amplifier compensate for each other, so that the total saturation output power remains unchanged. At this time, the ratio of the saturation output power of the auxiliary path to the saturation output power of the main path becomes larger, and the positions of the first maximum efficiency point and the second maximum efficiency point are reconstructed.

[0063] As shown in FIG. 4, FIG. 4 is a structural schematic diagram of a reconfigurable power amplifier provided by another embodiment of the present application.

[0064] In a possible embodiment, the number of auxiliary path power amplifiers is multiple, and the output ends of the multiple auxiliary path power amplifiers are respectively connected to the combining unit.

[0065] For example, the reconfigurable power amplifier mainly consists of a main path power amplifier and two auxiliary path power amplifiers, which are a first auxiliary path power amplifier and a second auxiliary path power amplifier, wherein the bias voltages of the reconfigurable power amplifier are V DM1 , V DA1 , and V DA2 . The reconfigurable power amplifier has three maximum efficiency points. By configuring V DM1 , V DA1 , and V DA2 , the positions of the three maximum efficiency points can be reconfigured.

[0066] When the input signal is small, only the power amplification unit of the main path power amplifier works, and the power amplification units of the auxiliary path power amplifiers are in an off state. The main path input signal passes through the second input matching unit and the first input matching unit, enters the power amplification unit of the main path power amplifier for power amplification, and the amplified signal passes through the first output matching unit and the second output matching unit, and then is output through the combining unit.

[0067] When the output signal reaches the average output power, the output efficiency reaches the first maximum efficiency point. At this time, the first auxiliary power amplifier starts to work, and when the first auxiliary power amplifier reaches the preset output power, the output efficiency reaches the second maximum efficiency point. At this time, the second auxiliary power amplifier starts to work, and as the output signal continues to increase to the maximum value, the output efficiency reaches the third maximum efficiency point, and the power amplification units of the main power amplifier, the first auxiliary power amplifier and the second auxiliary power amplifier all reach the saturation power state.

[0068] The bias voltage of the main power amplifier is reduced, which reduces the saturation power of the main power amplifier; the bias voltage of the second auxiliary power amplifier is increased, which increases the saturation power of the second auxiliary power amplifier. The saturation power of the first auxiliary power amplifier is related to the preset output power, which needs to be determined in combination with specific applications. Here, the bias voltage variation trend of the first auxiliary power amplifier is set to be the same as that of the second auxiliary power amplifier. The saturation power of the main power amplifier is reduced and the saturation power of the first auxiliary power amplifier and the second auxiliary power amplifier is increased, which are mutually compensated, so that the total saturation output power is unchanged, and the position of the third maximum efficiency point is unchanged. The ratio of the auxiliary saturation output power to the main saturation output power is increased, which reconstructs the positions of the first maximum efficiency point and the second maximum efficiency point.

[0069] As shown in FIG. 5, FIG. 5 is a structural schematic diagram of a reconfigurable power amplifier provided by another embodiment of the present application.

[0070] In a possible embodiment, the reconfigurable power amplifier includes a plurality of reconfigurable sub-power amplifiers and a total combining unit; the reconfigurable sub-power amplifier includes a main power amplifier, an auxiliary power amplifier and a combining unit; the combining units of the respective reconfigurable sub-power amplifiers are respectively connected to the total combining unit.

[0071] It can be understood that the combining units of the respective reconfigurable sub-power amplifiers are combined through the total combining unit to obtain the output signal.

[0072] For example, the reconfigurable sub-power amplifier further includes a power dividing unit, and the input end of the main power amplifier and the input end of the auxiliary power amplifier are respectively connected to the power dividing unit.

[0073] It can be understood that each combining unit can be implemented by two transmission lines, the main power amplifier is connected to one transmission line and connected to the auxiliary power amplifier, and the total combining unit outputs the signal after passing through one transmission line.

[0074] As shown in FIG. 5, the reconfigurable power amplifier includes two reconfigurable sub-power amplifiers and a total combining unit, and the combining units of the two reconfigurable sub-power amplifiers are combined through the total combining unit to obtain the output signal.

[0075] It can be understood that the two reconfigurable sub-power amplifiers can be the same or different in structure, and the embodiments of the present application do not make specific limitation thereto.

[0076] As shown in FIG. 6, FIG. 6 is a circuit schematic diagram of the combining unit according to an embodiment of the present application.

[0077] In one possible embodiment, the circuit of the combining unit is composed of four transmission lines and a capacitor. The electrical length of the transmission line TL1, the transmission line TL2 and the transmission line TL4 is one quarter of a wavelength. One end of the transmission line TL3 is grounded to form a short circuit, and the electrical length is less than one quarter of a wavelength, showing an inductor characteristic. The first reconfigurable sub-power amplifier is connected to input 1, and the second reconfigurable sub-power amplifier is connected to input 2.

[0078] Generally, the reconfigurable power amplifier is applied in digital power amplifier technology. The digital system processes the amplitude and phase of the input signal, and the processed signal is converted into a radio frequency input signal, which is divided into two paths to be input 1 and input 2. However, the reconfiguration ability of the output power and the output efficiency is not flexible enough under the traditional scheme. By configuring the drain bias voltage, the present application adjusts the bias voltage ratio of the main path power amplifier and the auxiliary path power amplifier, and the position of the output power and the maximum output efficiency point is reconfigured.

[0079] As shown in FIG. 7, FIG. 7 is a circuit schematic diagram of the reconfigurable power amplifier according to another embodiment of the present application.

[0080] In one embodiment, the reconfigurable power amplifier is composed of a control path power amplifier (CPA), two balanced path power amplifiers (BPA) BPA1 and BPA2 and a 90° coupler. The control path power amplifier is connected to the isolation end of the 90° coupler.

[0081] In the working state, the input signal enters the CPA for amplification, and when the output power reaches the preset value, the efficiency reaches the first maximum efficiency point, at which time the BPA1 and the BPA2 start to work, and with the output power of the BPA1 and the BPA2 reaching the maximum, the efficiency reaches the second maximum efficiency point. Usually, the BPA1 and the BPA2 adopt the same power amplifier and the same drain bias voltage to form a symmetrical LMBA (Load Modulated Balanced Amplifier). In actual application, the BPA1 and the BPA2 can also adopt different power amplifiers and different drain bias voltages to form an asymmetrical LMBA.

[0082] Another case is that the input signal first enters the balanced path power amplifiers BPA1 and BPA2, and after reaching the preset output power value, the CPA starts to output power to load modulate the BPA1 and BPA2, and improve the output efficiency.

[0083] By configuring the bias voltages V CA , V BA1 and V BA2 , the output powers of the CPA, the BPA1 and the BPA2 are adjusted to reconstruct the maximum efficiency point at the average output power.

[0084] As shown in FIG. 8, FIG. 8 is a structural schematic diagram of a reconfigurable power amplifier provided by another embodiment of the present application.

[0085] The reconfigurable power amplifier mainly comprises a main path power amplifier, a first auxiliary path power amplifier, a second auxiliary path power amplifier and an N-1th auxiliary path power amplifier, and the bias voltages are V DM1 , V DA1 , V DA2 to V DA(N-1) . The reconfigurable power amplifier has N maximum efficiency points. By configuring V DM1 , V DA1 , V DA2 to V DA(N-1) , the positions of the N maximum efficiency points can be reconstructed.

[0086] When the input signal is small, only the power amplification unit of the main path power amplifier works, and the power amplification units of the auxiliary path power amplifiers are in an off state. As the input signal increases, the power amplification units of the auxiliary path power amplifiers work in turn. When the first auxiliary path power amplifier starts to work, the output efficiency reaches the first maximum efficiency point; when the second auxiliary path power amplifier starts to work, the output efficiency reaches the second maximum efficiency point; when the N-1th auxiliary path power amplifier starts to work, the output efficiency reaches the N-1th maximum efficiency point; and when the main path and the auxiliary paths all reach the saturated output power, the output efficiency reaches the Nth maximum efficiency point.

[0087] By configuring V DM1 , V DA1 , V DA2 to V DA(N-1) , the positions of the N maximum efficiency points can be reconstructed.

[0088] As shown in FIG. 9, FIG. 9 is a structural schematic diagram of a reconfigurable power amplifier provided by another embodiment of the present application.

[0089] In a possible embodiment, the reconfigurable power amplifier further comprises a power supply module and a voltage control module, wherein the power supply module is configured to provide bias voltages for the main path power amplifier and the auxiliary path power amplifiers; and the voltage control module is configured to control the magnitude of the bias voltages of the main path power amplifier and the auxiliary path power amplifiers.

[0090] It can be understood that the voltage control module configures the bias voltages according to system applications, and transmits the data to the power supply module, so that the power supply module provides the bias voltages for the main path power amplifier and the auxiliary path power amplifiers.

[0091] It can be understood that, in the case that the reconfigurable power amplifier is composed of N path power amplifiers (1 main path power amplifier and N-1 auxiliary path power amplifiers) and a combining unit, the power supply module provides at least N bias voltages. For example, in the case that the reconfigurable power amplifier is composed of 6 path power amplifiers and a combining unit, the power supply module provides at least 6 bias voltages.

[0092] As shown in FIG. 10, FIG. 10 is a circuit schematic diagram of a reconfigurable power amplifier provided by another embodiment of the present application.

[0093] In a possible embodiment, the second input matching unit of the main path power amplifier is implemented by a capacitor C1 and a transmission line TL1. This network is simple and easy to implement, and has very small insertion loss. The capacitor C1 can be implemented by a patch capacitor.

[0094] The first input matching unit of the main path power amplifier is implemented by a bonding wire BW1, a capacitor C2 and a bonding wire BW2, which form a "T" type network. The first input matching unit improves the input impedance of the power amplification unit of the power amplifier, so that the second input matching unit is easier to implement. The bonding wire BW1 and the bonding wire BW2 can implement the function of an inductor, and have the characteristics of small insertion loss and flexible implementation. The capacitor C2 can be implemented by a plate capacitor, and has the characteristic of high quality factor.

[0095] The first input matching unit of the auxiliary path power amplifier is implemented by a bonding wire BW4, a capacitor C7 and a bonding wire BW5, which form a "T" type network. The first input matching unit improves the input impedance of the power amplification unit of the power amplifier, so that the second input matching unit is easier to implement. The bonding wire BW4 and the bonding wire BW5 can implement the function of an inductor, and have the characteristics of small insertion loss and flexible implementation. The capacitor C7 can be implemented by a plate capacitor, and has the characteristic of high quality factor.

[0096] The power amplification unit M of the main path power amplifier and the power amplification unit A of the auxiliary path power amplifier can realize the function of power amplification; in addition, the embodiment of the application can realize the function of power amplification by adopting a gallium nitride (GaN) technology, can realize the function of power amplification by adopting a laterally diffused metal oxide semiconductor (LDMOS) technology, and can realize the function of power amplification by adopting a gallium arsenide (GaAs) technology, and the embodiment of the application does not make specific limitation on the technology for realizing power amplification.

[0097] The first output matching unit of the main path power amplifier is implemented by a bonding wire BW3, and the bonding wire BW3 can realize the function of an inductor and complete the preset impedance conversion function.

[0098] The second output matching unit is composed of a transmission line TL2, a transmission line TL3, a capacitor C3, a capacitor C4 and a capacitor C5. The transmission line TL3 and the capacitor C3 constitute a drain bias network for biasing the voltage V DM . The capacitor C3 is generally composed of multiple capacitors with different capacitances, provides decoupling, and reduces the drain bias voltage ripple. In an ideal state, the drain bias network generally presents an open circuit state (infinite impedance) and does not participate in the second output matching unit. In an actual working frequency band, the drain bias network is not an ideal open circuit state and generally participates in the second output matching unit. The transmission line TL2, the transmission line TL3, the capacitor C3, the capacitor C4 and the capacitor C5 of the second output matching unit cooperatively complete the impedance conversion function and match to a specific impedance value.

[0099] The first output matching unit of the auxiliary path power amplifier is implemented by a bonding wire BW6, and the bonding wire BW6 can realize the function of an inductor and complete the preset impedance conversion function.

[0100] In addition to completing the specific impedance conversion function, the second output matching unit of the auxiliary path power amplifier is a phase shift network for compensating the phase, the transmission line TL8 and the capacitor C8 constitute a drain bias network for biasing the voltage V DA .

[0101] The combining unit is implemented by a transmission line TL4 and a transmission line TL5.

[0102] It can be understood that the transmission lines described above can be implemented by microstrip lines or strip lines, and the embodiment of the application does not make specific limitation thereon.

[0103] Based on the reconfigurable power amplifier of each of the above embodiments, the following respectively proposes each embodiment of the control method of the present application.

[0104] In an embodiment, the control method can include but is not limited to the following step S110:

[0105] Step S110, control the size of the bias voltage of the main path power amplifier and the auxiliary path power amplifier to adjust the output efficiency.

[0106] It is worth noting that the embodiments of the present application can achieve the reconfiguration of the output power configuration and the output efficiency configuration of the main path power amplifier and the auxiliary path power amplifier by controlling the size of the bias voltage of the main path power amplifier and the auxiliary path power amplifier, thereby the embodiments of the present application can improve the output efficiency of the reconfigurable power amplifier and reduce the overall power consumption compared with the current way of adding a switching element to the reconfigurable power amplifier.

[0107] Specifically, in one possible embodiment, regarding the above step S110, the control method further includes step S120:

[0108] Step S120, determine the target bias voltage ratio according to the average back-off parameter, control the size of the bias voltage of the main path power amplifier and the auxiliary path power amplifier, so that the bias voltage ratio of the main path power amplifier and the auxiliary path power amplifier is the target bias voltage ratio.

[0109] For example, the embodiments of the present application determine the target bias voltage ratio through the average back-off parameter, so as to adjust the output power ratio of the main path and the auxiliary path according to the target bias voltage ratio, and further adjust the average power back-off amount of the reconfigurable power amplifier of the present application.

[0110] It can be understood that the relationship between the size of the bias voltage of the main path power amplifier and the auxiliary path power amplifier and the target bias voltage ratio can be obtained by the formula V DA =(1 / k)*V DM , where k is the target bias voltage ratio, V DM is the bias voltage of the main path power amplifier, and V DA is the bias voltage of the auxiliary path power amplifier.

[0111] It can be understood that the average power back-off amount can be obtained by the formula α = 10 APBO / 20 , where APBO (Average Power Back-Off) is the average power back-off amount, and α is the average back-off parameter.

[0112] Specifically, in one possible implementation, regarding the determination of the target bias voltage ratio according to the average back-off parameter in step S120, the control method further includes steps S130-S140:

[0113] Step S130, determining a target load impedance ratio of the main path power amplifier and the auxiliary path power amplifier;

[0114] It can be understood that the target load impedance ratio is a fixed value, which can be set according to actual needs, and can be 1 or 0.8. The present embodiment does not specifically limit the size of the target load impedance ratio.

[0115] Step S140, determining the target bias voltage ratio according to the average back-off parameter and the target load impedance ratio.

[0116] For example, the target bias voltage ratio can be obtained according to the formula wherein k is the target bias voltage ratio, a is the average back-off parameter, and x is the target load impedance ratio.

[0117] It can be understood that after the target bias voltage ratio is determined, the present application can determine the size of the bias voltage of the main path power amplifier and the auxiliary path power amplifier according to the target bias voltage ratio, so as to reconstruct the output power configuration and the output efficiency configuration of the main path power amplifier and the auxiliary path power amplifier.

[0118] For example, Table 1 is a sample of the size of the bias voltage provided by the present embodiment.

[0119] Table 1

[0120] Specifically, in one possible implementation, regarding the control of the size of the bias voltage of the main path power amplifier and the auxiliary path power amplifier in step S110, the control method further includes step S150 or step S160:

[0121] Step S150, in the case of reducing the output power, the bias voltage ratio between the main path power amplifier and the auxiliary path power amplifier remains unchanged, and the bias voltage of the main path power amplifier and the auxiliary path power amplifier is reduced respectively;

[0122] For example, in the case of reducing the bias voltage of the main path power amplifier and the auxiliary path power amplifier while the bias voltage ratio between the main path power amplifier and the auxiliary path power amplifier remains unchanged, the output power will be reduced, so as to reconstruct the output power configuration and the output efficiency configuration of the main path power amplifier and the auxiliary path power amplifier. Therefore, compared with the current method of adding a switching element to the reconfigurable power amplifier, the present embodiment can improve the output efficiency of the reconfigurable power amplifier and reduce the overall power consumption.

[0123] Step S160, in the case of increasing the output power, the bias voltage ratio between the main path power amplifier and the auxiliary path power amplifier is unchanged, and the bias voltages of the main path power amplifier and the auxiliary path power amplifier are respectively increased.

[0124] For example, in the case of increasing the bias voltages of the main path power amplifier and the auxiliary path power amplifier while the bias voltage ratio between the main path power amplifier and the auxiliary path power amplifier is unchanged, the output power is increased, so as to reconstruct the output power configuration and the output efficiency configuration of the main path power amplifier and the auxiliary path power amplifier, thereby reducing the insertion loss of the reconfigurable power amplifier, improving the output power and the output efficiency of the reconfigurable power amplifier, and reducing the power consumption of the whole machine, as compared with the current method of adding a switching element to the reconfigurable power amplifier.

[0125] In order to better understand the scheme of the embodiments of the present application, the reconfigurable power amplifier provided by the embodiments of the present application is described below through several specific application examples.

[0126] Example one:

[0127] As shown in FIG. 3, the reconfigurable power amplifier of the embodiments of the present application works at a specific output power, which is the average output power. The reconfigurable power amplifier also has a saturation output power.

[0128] The average power backoff amount APBO can be obtained by the formula APBO=P avg -P sat , where P avg is the average output power, and P sat is the saturation output power.

[0129] The reconfigurable power amplifier has at least two maximum efficiency points, a first maximum efficiency point and a second maximum efficiency point. The first maximum efficiency point appears at the average output power of the reconfigurable power amplifier, and the second maximum efficiency point appears at the saturation output power of the reconfigurable power amplifier.

[0130] α is the average backoff parameter, and the value range is (0<α≦1). The average power backoff amount APBO=20lg(α)dB. For example, when α is 0.5, the average power backoff amount is -6dB. When α is 0.333, the average power backoff amount is -9.5dB. When α is 0.25, the average power backoff amount is -12dB.

[0131] In combination with the power backoff amount, the first maximum efficiency point and the second maximum efficiency point are respectively located at the average power backoff amount APBO and the power backoff amount of 0dB.

[0132] The output power can be obtained by the formula wherein P Out is the output power, R L is the load impedance, and V DD is the bias voltage. According to the formula, when the load impedance is fixed, increasing the bias voltage of the power amplifier can increase the output power, and decreasing the bias voltage of the power amplifier can decrease the output power.

[0133] Example Two:

[0134] As shown in FIG. 11, FIG. 11 is an efficiency curve diagram under voltage configuration according to an embodiment of the present application.

[0135] By configuring the ratio of the bias voltage of the main path power amplifier to the bias voltage of the auxiliary path power amplifier, the output power ratio of the main path to the auxiliary path is adjusted, and thus the average power backoff of the reconfigurable power amplifier of the present application is adjusted. That is, the position of the second maximum efficiency point is kept unchanged, and the position of the first maximum efficiency point is reconfigured.

[0136] By configuring the bias voltage, the ratio of the bias voltage of the main path power amplifier to the bias voltage of the auxiliary path power amplifier is reduced, and thus the average power backoff can be reduced. Reducing the bias voltage of the main path power amplifier can reduce the saturation power of the main path power amplifier, and increasing the bias voltage of the auxiliary path power amplifier can increase the saturation power of the auxiliary path power amplifier. The reduced saturation power of the main path power amplifier and the increased saturation power of the auxiliary path power amplifier compensate for each other, and the total saturation power is kept unchanged, and thus the position of the second maximum efficiency point is kept unchanged. The power ratio of the saturation power of the auxiliary path power amplifier to the saturation power of the main path power amplifier is increased, and thus the position of the first maximum efficiency point is reconfigured.

[0137] The bias voltage ratio of voltage configuration 1 is k1, the bias voltage ratio of voltage configuration 2 is k2, and the bias voltage ratio of voltage configuration 3 is k3, and k1 < k2 < k3 ≦ 1. When the bias voltage ratio is k1, the APBO is -12 dB, and the corresponding output efficiency is greater than the output efficiency when the bias voltage ratio is k2 or k3. Therefore, under the same average power backoff, selecting voltage configuration 1 can reduce the system power consumption and improve the performance of the system.

[0138] Thus, different signals need to select different average power backoffs to obtain the maximum output efficiency and reduce the power consumption of the whole machine. Advantageously, the reconfigurable power amplifier of the present application can reconfigure different APBOs to meet the output efficiency requirement under different signal modes. In addition, the present application can also meet the requirement of improving the output efficiency under low output power.

[0139] For example, the average power backoff amount of the embodiment of the present application is related to the signal type, for example, the average power backoff amount of 5G signal is greater than that of 4G signal, and the optimal voltage configuration is selected according to the average power backoff amount of the current signal; for example, in the case of the average power backoff amount of -6dB, the voltage configuration 3 can obtain a higher efficiency.

[0140] It can be understood that each signal has a fixed average power backoff amount, and by selecting the voltage configuration that is more matched to the average power backoff amount corresponding to the current signal type, a more optimal efficiency can be obtained.

[0141] Example three:

[0142] As shown in FIG. 12, FIG. 12 is a schematic diagram of efficiency curves under voltage configurations according to another embodiment of the present application.

[0143] The ratio of the bias voltage of the main path power amplifier to the bias voltage of the auxiliary path power amplifier is unchanged, and the average power backoff amount APBO is fixed. By reducing the bias voltages of the two paths, the average output power decreases, the saturation powers of the main path and the auxiliary path decrease at the same time, the total saturation power decreases, and the first maximum efficiency point position and the second maximum efficiency point position are reconstructed.

[0144] For example, the embodiment of the present application is aimed at a specific type of signal, when the output power is high, the voltage configuration 6 needs to be selected to obtain a higher efficiency; when the output power is low, the power backoff amount is small, and the voltage configuration 4 needs to be selected to obtain a higher efficiency. Under the same voltage configuration, the smaller the power backoff amount, the smaller the output power.

[0145] For example, under the voltage configuration 4, the output efficiency under the power backoff amount of -14dB is much greater than that under the voltage configurations 5 and 6.

[0146] It can be understood that the embodiment of the present application can select the voltage configuration according to the corresponding output power when the average power backoff amount APBO is unchanged.

[0147] It can be understood that after the signal type is fixed, the average output power of the signal is large or small, and the voltage configuration is selected according to the power backoff amount corresponding to the average output power.

[0148] For example, when the drain voltage is not reduced, the saturation power is Psat(=46dBm), and the output power is the average output power Pavg(=40dBm); if there is an application requirement that the output power is reduced, and the output power is reduced to Pavg'(=37dBm), there are two cases:

[0149] Case one is to maintain Psat saturation without reducing the drain voltage, and the power backoff amount is Pavg'-Psat=-9dB;

[0150] Case two is to reduce the drain voltage, and the saturation power after reducing the drain voltage is Psat'(=43dBm), and the power backoff amount is Pavg'-Psat'=-6dB.

[0151] The average power backoff amount APBO is Pavg-Psat=-6dB, which is equal to the average power backoff amount Pavg'-Psat'=-6dB after reducing the drain voltage. Because the average power backoff amount is unchanged.

[0152] Therefore, according to the reduced output power, the power backoff amount is calculated, and when the power backoff amount is less than APBO (i.e., -9dB<-6dB), the drain bias voltage is reduced, and the drain voltage ratio is maintained unchanged.

[0153] Example four:

[0154] As shown in FIG. 10, when the input signal is small, only the power amplification unit of the main path power amplifier works, and the power amplification unit of the auxiliary path power amplifier is in an off state. The main path input signal passes through the second input matching unit and the first input matching unit, and then enters the power amplification unit of the main path power amplifier for power amplification. The amplified signal passes through the first output matching unit and the second output matching unit, and then outputs the signal through the combining unit.

[0155] When the output signal reaches the average output power, the output efficiency reaches the first maximum efficiency point. At this time, the auxiliary path starts to work, and when the saturation output power is reached, the output efficiency reaches the second maximum efficiency point. The bias voltage of the main path is reduced, which reduces the saturation power of the main path; the bias voltage of the auxiliary path is increased, which increases the saturation power of the auxiliary path. The reduced saturation power of the main path and the increased saturation power of the auxiliary path compensate each other, so that the total saturation output power remains unchanged, and at this time the position of the second maximum efficiency point remains unchanged. The ratio of the saturation output power of the auxiliary path to the saturation output power of the main path becomes larger, and the position of the first maximum efficiency point is reconstructed.

[0156] The optimal load impedance of the power amplification unit of the main path power amplifier and the power amplification unit of the auxiliary path power amplifier is R L1 and R L2 , respectively, and R L1 =x*R L2 . x is the ratio of the optimal load impedance of the power amplification unit of the main path power amplifier to the power amplification unit of the auxiliary path power amplifier. The main path works at a bias voltage of 48V, i.e., V DM =48V, and the actual voltage can be set as needed.

[0157] In the initial state of the reconfigurable power amplifier, the average power back-off amount APBO1, the ratio of the drain bias voltage of the main path and the auxiliary path is k1, and for the average power back-off amount of -6dB, α1=10 APBO / 20 α1=10

[0158] When x=1, k1=1 is obtained from the equation When x=1, k1=1 is obtained from the equation

[0159] When x=0.8, k1=0.894 is obtained from the equation When x=0.8, k1=0.894 is obtained from the equation

[0160] In the reconfigurable state, according to the average power back-off amount, α2=10 APBO / 20 α2=10 The ratio of the bias voltage of the main path and the auxiliary path is k2, which is obtained from the equation The bias voltage of the main path power amplifier is obtained from the equation DA2 The bias voltage of the auxiliary path power amplifier is obtained from the equation DM2 .

[0161] The reconfiguration steps of the reconfigurable power amplifier are as follows:

[0162] Given V DM1 =48V, the optimal load impedance ratio x, which can be set according to requirements.

[0163] (1) According to the average power back-off amount APBO1 in the initial state, α1=10 APBO1 / 20 is obtained.

[0164] (2) According to α1 and x, k1 is obtained from the equation

[0165] (3) According to V DA1 , V DM1 is obtained. DA1

[0166] (4) In the reconfigurable state, according to the average power back-off amount APBO2, α2=10 APBO2 / 20 is obtained.

[0167] (5) According to α2 and x, k2 is obtained from the equation

[0168] ​​​(6) bring a1 and a2 into Equation, V DM2 .

[0169] According to V DA2 = (1 / k) * V DM2 Equation, V DA2 .

[0170] It can be understood that the parameters such as x, APBO, V DM1 , etc. mentioned above can be set according to actual needs, and the embodiments of the present application do not make specific limitations thereto.

[0171] It can be understood that, due to the existence of non-ideal conditions such as start-up resistance and thermal effect of the power amplifier in the working process, the setting of the voltage ratio is not strictly in accordance with V DA = (1 / k) * V DM , and needs to be adjusted according to experience.

[0172] Example five:

[0173] In the initial state, the bias voltages of the main path and the auxiliary path are V DM1 and V DA1 , respectively, and when the output power is reduced by N dB, the bias voltage of the main path in the reconstruction state is obtained by the formula V DM2 = 10 -N / 20 * V DM1 , and the bias voltage of the auxiliary path is obtained by the formula V DA2 = (1 / k) * V DM2 .

[0174] Taking APBO = -6 dB, x = 0.8, V DM1 = 48 V, and V DA1 = 53.67 V, when the output power is reduced by 4 dB, i.e. N = 4, V DM1 = 30.3 V and VDA1 = 33.86 V are calculated. See voltage configuration 5 shown in FIG. 12. Similarly, the case when N = 8 can be calculated, see voltage configuration 4 shown in FIG. 12. When the voltage configuration 4, the output efficiency under the average power backoff of -14 dB is much greater than that when the voltage configuration 5 and 6.

[0175] It can be understood that the reconfigurable power amplifier of the embodiments of the present application can adopt a double-end input form of main path input and auxiliary path input. The form is mainly applied in digital technology power amplifiers such as reconfigurable load modulation balance type (power) amplifiers LMBA and reconfigurable Doherty-outphasing power amplifiers (DOPA), and the output efficiency of the reconfigurable power amplifier is greatly improved by adjusting the input amplitude and phase through digital technology and combining the reconfigurable power amplifier technology of the present application.

[0176] Example six:

[0177] As shown in FIG. 4, in the case of APBO fixation, the power amplifier can also provide reconfiguration at low output power.

[0178] When the output power decreases, the bias voltage (V DM1 , V DA1 , V DA2 ) of the main path power amplifier, the first auxiliary path power amplifier and the second auxiliary path power amplifier decreases at the same time, and the ratio (k) of the bias voltage of the main path power amplifier, the first auxiliary path power amplifier and the second auxiliary path power amplifier remains unchanged, the saturation power of the main path and the auxiliary path decreases at the same time, the total saturation output power decreases, and the first maximum efficiency point position and the second maximum efficiency point position are reconfigured.

[0179] The embodiments of the present application also provide a communication device, as shown in FIG. 13, the communication device 1400 comprises:

[0180] one or more processors 1410;

[0181] a memory 1420, one or more programs are stored on the memory 1420, when the one or more programs are executed by the one or more processors 1410, the one or more processors 1410 realize:

[0182] a control method applied to a reconfigurable power amplifier.

[0183] The memory 1420 is a kind of non-transient network system, and can be used to store non-transient software programs and non-transient computer executable programs.In addition, the memory 1420 can include high-speed random access memory, and can also include non-transient memory, such as at least one magnetic disk storage device, flash memory device or other non-transient solid-state memory device.In some embodiments, the memory 1420 can include memory 1420 remotely arranged relative to the processor 1410, and these remote memories 1420 can be connected to the processor 1410 through a network.The above-mentioned network includes but is not limited to the Internet, enterprise intranet, local area network, mobile communication network and combination thereof.

[0184] The memory 1420 can be implemented in the form of a read-only memory (ROM), a static storage device, a dynamic storage device, or a random access memory (RAM), etc. The memory 1420 can store an operating system and other application programs. When the technical solutions provided by the embodiments of the present specification are implemented by software or firmware, the related program codes are stored in the memory 1420 and are called and executed by the processor 1410 to implement the method of the embodiments of the present application.

[0185] The processor 1410 can be implemented in the form of a general-purpose CPU (Central Processing Unit), a microprocessor, an application specific integrated circuit (ASIC), or one or more integrated circuits, etc., for executing related programs to implement the technical solutions provided by the embodiments of the present application.

[0186] In some embodiments, the communication device further comprises:

[0187] An input / output interface for realizing information input and output;

[0188] A communication interface for realizing communication interaction between the device and other devices. The communication can be realized by wired means (such as USB, network cable, etc.) or by wireless means (such as mobile network, WIFI, Bluetooth, etc.).

[0189] A bus for transmitting information between various components (such as the processor 1410, the memory 1420, the input / output interface, and the communication interface) of the device.

[0190] The processor 1410, the memory 1420, the input / output interface, and the communication interface can realize communication connection between each other within the device through the bus.

[0191] An embodiment of the present application further provides a computer readable storage medium storing computer executable instructions for implementing:

[0192] A control method applied to a reconfigurable power amplifier.

[0193] The reconfigurable power amplifier, the control method, the communication device and the storage medium provided in the embodiments of the present application, wherein the reconfigurable power amplifier comprises a main path power amplifier, an auxiliary path power amplifier and a combining unit; the main path power amplifier and the auxiliary path power amplifier respectively comprise an input matching unit, a power amplification unit and an output matching unit connected in sequence, and the output matching unit is connected with a bias unit; the output end of the main path power amplifier and the output end of the auxiliary path power amplifier are respectively connected with the combining unit. Therefore, the embodiments of the present application can control the size of the bias voltage of the main path power amplifier and the auxiliary path power amplifier, so as to reconfigure the output power configuration and the output efficiency configuration of the main path power amplifier and the auxiliary path power amplifier, thereby reducing the insertion loss of the reconfigurable power amplifier and improving the performance of the reconfigurable power amplifier relative to the conventional method of adding a switching element to the reconfigurable power amplifier.

[0194] The system architecture and application scenarios described in the embodiments of the present application are used to more clearly illustrate the technical solutions of the embodiments of the present application, and do not constitute a limitation on the technical solutions provided by the embodiments of the present application. It can be known by those skilled in the art that, with the evolution of system architecture and the appearance of new application scenarios, the technical solutions provided by the embodiments of the present application are also applicable to similar technical problems.

[0195] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer readable storage medium, and when the computer program is executed, the processes of the above-mentioned embodiments can be included. In the embodiments of the present application, any reference to memory, storage, database or other medium can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. As an illustration but not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM) and memory bus dynamic RAM (RDRAM) and the like.

[0196] As will be appreciated by one of ordinary skill in the art, all or some of the steps, systems, and techniques disclosed herein can be embodied in software, firmware, hardware, and / or suitable combination thereof. Some or all of the physical components can be implemented in software executed by a processor, such as a central processing unit, a digital signal processor, or a microprocessor, or in hardware, or in an integrated circuit, such as an application- specific integrated circuit. Such software can be distributed on computer readable media, which can comprise computer storage media (or non-transitory media), and communication media (or transitory media). As will be appreciated by one of ordinary skill in the art, the term computer storage media includes all physical and tangible computer storage media, such as a volatile and non-volatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can be accessed by a computer. Further, as will be appreciated by one skilled in the art, communication media typically embodies computer readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism and includes any information delivery media.

[0197] The above description is not intended to limit the scope of the application. Modifications, equivalent replacements, and improvements made by those skilled in the art without departing from the scope and spirit of the application shall fall within the scope of the application.

Claims

1. A reconfigurable power amplifier, comprising a main path power amplifier, an auxiliary path power amplifier and a combining unit; the main path power amplifier and the auxiliary path power amplifier each comprise an input matching unit, a power amplifying unit and an output matching unit connected in sequence, and the output matching unit has a bias voltage terminal; the output terminal of the main path power amplifier and the output terminal of the auxiliary path power amplifier are connected to the combining unit respectively.

2. The reconfigurable power amplifier of claim 1, wherein, the input matching unit comprises a first input matching unit and a second input matching unit, wherein the first input matching unit is configured to transform the input impedance of the power amplifying unit to a first preset impedance; the second input matching unit is configured to transform the value of the first preset impedance to a first target impedance value.

3. The reconfigurable power amplifier of claim 2, wherein, the output matching unit comprises a first output matching unit and a second output matching unit, wherein the first output matching unit is configured to transform the output impedance of the power amplifying unit to a second preset impedance value; the second output matching unit is configured to transform the second preset impedance value to a second target impedance value and access the bias voltage.

4. The reconfigurable power amplifier of claim 1, wherein, The number of auxiliary path power amplifiers is multiple, and the output terminals of the multiple auxiliary path power amplifiers are connected to the combining unit respectively.

5. The reconfigurable power amplifier of claim 1, wherein, comprising a plurality of reconfigurable sub-power amplifiers and a total combining unit; the reconfigurable sub-power amplifier comprises the main path power amplifier, the auxiliary path power amplifier and the combining unit; the combining unit of each reconfigurable sub-power amplifier is connected to the total combining unit.

6. The reconfigurable power amplifier of claim 1, further comprising a power dividing unit, and the input terminal of the main path power amplifier and the input terminal of the auxiliary path power amplifier are connected to the power dividing unit respectively.

7. The reconfigurable power amplifier of claim 1, further comprising a power supply module and a voltage control module, wherein: the power supply module is configured to provide the bias voltage for the main path power amplifier and the auxiliary path power amplifier; the voltage control module is configured to control the size of the bias voltage of the main path power amplifier and the auxiliary path power amplifier.

8. A control method applied to a reconfigurable power amplifier, the reconfigurable power amplifier comprising a main path power amplifier, an auxiliary path power amplifier and a combining unit, the output terminal of the main path power amplifier and the output terminal of the auxiliary path power amplifier being connected to the combining unit respectively, the method comprising: controlling the size of the bias voltage of the main path power amplifier and the auxiliary path power amplifier to adjust the output efficiency.

9. The control method according to claim 8, wherein the control of the size of the bias voltage of the main path power amplifier and the auxiliary path power amplifier comprises: determining a target bias voltage ratio according to an average backoff parameter, and controlling the size of the bias voltage of the main path power amplifier and the auxiliary path power amplifier so that the bias voltage ratio of the main path power amplifier and the auxiliary path power amplifier is the target bias voltage ratio.

10. The control method according to claim 9, wherein the determination of the target bias voltage ratio according to the average backoff parameter comprises: determining a target load impedance ratio of the main path power amplifier and the auxiliary path power amplifier. A target bias voltage ratio is determined according to the average back-off parameter and the target load impedance ratio.

11. The control method according to claim 9, wherein The control of the magnitude of the bias voltage of the main path power amplifier and the auxiliary path power amplifier comprises: In case of output power reduction, the bias voltage ratio between the main path power amplifier and the auxiliary path power amplifier is kept unchanged, and the bias voltage of the main path power amplifier and the auxiliary path power amplifier is reduced respectively; Or, In case of output power increase, the bias voltage ratio between the main path power amplifier and the auxiliary path power amplifier is kept unchanged, and the bias voltage of the main path power amplifier and the auxiliary path power amplifier is increased respectively. 12.A communication device comprising a processor and a memory, the memory storing programs or instructions executable on the processor, the programs or instructions, when executed by the processor, implement the control method according to any one of claims 8-11. 13.A computer readable storage medium comprising instructions, which, when executed on a processor, cause the processor to perform the control method according to any one of claims 8-11.

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