Information acquisition method and analysis system

Abstract

The present application can be applied to the technical field of computers. Provided are an information acquisition method and analysis system. The information acquisition method is applied to an analysis system, which is used for analyzing a plurality of operation units, wherein the plurality of operation units are used for implementing a first instruction set, the first instruction set is compiled by a computer program, which is used for implementing operators, there is a first execution order for a plurality of instructions in the first instruction set, and each instruction is executed by one of the plurality of operation units according to the first execution order. The information acquisition method comprises: an analysis system monitoring whether each operation unit from among a plurality of operation units is executing an instruction; and on the basis of whether each operation unit is executing an instruction, outputting a time period within which each operation unit is in an idle state and a time period within which each operation unit is in a non-idle state, wherein the idle state is used for indicating that an operation unit is not executing an instruction, and the non-idle state is used for indicating that an operation unit is executing an instruction. A user can learn, by means of an output result, the actual usage situation of hardware resources during the execution of operators.

Description

Information acquisition method and analysis system

[0001] The present application claims priority to the Chinese patent application No. 202411239704.4, filed on September 5, 2024, with the State Intellectual Property Office of China, and entitled "Information acquisition method and analysis system", the whole content of which is incorporated herein by reference. TECHNICAL FIELD

[0002] The present application relates to the technical field of computer, and in particular, to an information acquisition method and analysis system. BACKGROUND

[0003] A neural network is composed of multiple operators, and the performance of neural network training or inference mainly depends on the performance of these operators. Here, the performance of neural network training or inference represents the time required for neural network training or inference, and the performance of operators represents the execution time of operators. In the process of running a neural network by a computing device, the computing device will reasonably allocate its hardware resources (such as computing resources, storage resources, etc.) to multiple operators that make up the neural network, so as to fully utilize the allocated hardware resources to accelerate the execution process of operators.

[0004] Generally speaking, the higher the hardware resource utilization rate of an operator is, the better the performance of the operator is. Therefore, for an operator developer, the performance of the operator developed by him can be measured by the hardware resource utilization rate of the operator. Moreover, the operator developer can also optimize the operator according to the hardware resource utilization rate of the operator. However, the hardware resource utilization rate of the operator is a statistical index, which can only reflect the overall execution of the operator, and the information provided to the operator developer is very limited, so the optimization of the operator according to the hardware resource utilization rate of the operator is inefficient. SUMMARY

[0005] To solve the above technical problems, the present application provides an information acquisition method and analysis system, which can feedback the actual use of hardware resources when the operator is executed to the user.

[0006] In a first aspect, an information acquisition method is provided, which is applied to an analysis system. The analysis system is configured to analyze a plurality of operation units. The plurality of operation units are configured to implement a first instruction set. The first instruction set is compiled from a computer program configured to implement an operator, and the first instruction set includes a plurality of instructions. The plurality of instructions have a first execution order, and each instruction is executed by one of the plurality of operation units according to the first execution order. The method includes: monitoring, by the analysis system, whether each operation unit of the plurality of operation units executes an instruction; and outputting, according to whether each operation unit executes an instruction, a period during which each operation unit is in an idle state and a period during which each operation unit is in a non-idle state. The idle state indicates that no instruction is executed, and the non-idle state indicates that an instruction is executed.

[0007] In the above solution, during implementation of the operator, i.e., during execution of the instructions in the first instruction set, the execution of the instructions by the operation units is monitored, and the periods during which the operation units are in the idle state and the periods during which the operation units are in the non-idle state are obtained according to the execution of the instructions by the operation units and are fed back to the user. The user can obtain the switching time points of the operation units from busy to idle and from idle to busy during implementation of the operator from the output results, and thus clearly knows the actual use of the hardware resources when the operator is executed. In addition, the actual use of the hardware resources when the operator is executed can be obtained without repeatedly running the computer program, but only by running the computer program once (i.e., executing the first instruction set once).

[0008] In some possible implementation manners, the method further includes: obtaining, by the analysis system, a start time and an end time of a first period during which the first operation unit is in the idle state; and outputting positions of instructions corresponding to the start time and the end time in a second instruction set. The second instruction set is compiled from the computer program configured to implement the operator. The first instruction set is a subset of the second instruction set.

[0009] In the above solution, after the period during which the first operation unit is in the idle state is determined, the user is provided with the instructions related to the idle state of the first operation unit. It can be understood that the instructions related to the idle state of the first operation unit are equivalent to the instructions for reducing the utilization of the first operation unit, i.e., the problem instructions. Therefore, the positions of the problem instructions are fed back to the user, so that the user can find the part of the entire computer program that needs to be optimized.

[0010] In some possible implementation manners, the first instruction is an instruction corresponding to the start time point or an instruction corresponding to the end time point, and a position of the first instruction in the second instruction set is indicated by the computer program corresponding to the first instruction or is indicated by a position of the computer program corresponding to the first instruction in the computer program used to implement the operator.

[0011] In the scheme, the position of the problem instruction is indicated by specific content or a specific position of the computer program corresponding to the problem instruction, so that familiar information can be provided for the user, thereby improving the user experience.

[0012] In some possible implementation manners, the method further includes: outputting, by the analysis system, a time period in which the second operation unit is in an idle state and a time period in which the second operation unit is in a non-idle state within the first time period. The second operation unit belongs to the plurality of operation units. The second operation unit is configured to execute a second instruction. The second instruction is an instruction between an instruction corresponding to the start time point and an instruction corresponding to the end time point in the first execution order.

[0013] In the scheme, not only can the position of the problem instruction be provided for the user, but also a problem scenario in which other operation units execute instructions when the first operation unit is in an idle state can be provided. The problem scenario can reflect which operation units are working when the first operation unit is in an idle state, specific conditions in which the operation units execute instructions, and the relevance between the operation units in executing instructions, and the like. The problem scenario can reflect information such as which operation units the first operation unit is waiting for to process results and the like. The information reflected by the problem scenario can guide the user to optimize the computer program in a direction, thereby improving the optimization efficiency of the user. In addition, the technical scheme can only analyze, record, and feed back the problem instruction and the problem scenario corresponding to the problem instruction, without recording and feeding back the execution conditions and scenarios of each instruction. Therefore, the amount of information recorded and fed back by the technical scheme is small, and the quality of the information is high. This reduces the storage requirement of the analysis system and facilitates the user to directly obtain useful information to optimize the computer program being developed by the user, thereby improving the optimization efficiency of the user.

[0014] In some possible implementation manners, the instructions executed by the first operation unit are all computing instructions.

[0015] Because the time consumed for executing a computing instruction is long, the use time of an operation unit that executes a computing instruction determines the execution time of an operator to a great extent, that is, the performance of the operator. Therefore, the technical scheme can focus on analyzing the actual use conditions of the operation unit that executes the computing instruction, and guide the user to optimize the computer program being developed by the user in a direction of improving the utilization rate of the operation unit that executes the computing instruction.

[0016] In some possible implementation manners, the plurality of operation units belong to a same processor.

[0017] In some possible implementation manners, the plurality of operation units are used to implement a third instruction set. The third instruction set is obtained by compiling different computer programs for implementing the same operator, respectively. The method further includes: monitoring, by the analysis system, whether each operation unit executes instructions in the process of implementing the third instruction set; and outputting, by the analysis system, a period in which each operation unit is in an idle state and a period in which each operation unit is in a non-idle state in the process of implementing the third instruction set, and a period in which each operation unit is in the idle state and a period in which each operation unit is in the non-idle state in the process of implementing the first instruction set, according to whether each operation unit executes instructions in the process of implementing the third instruction set.

[0018] In the scheme, in a scenario of running a computer program optimized by a user, the user is provided with execution conditions of each operation unit before and after optimization, so that the user can compare overall optimization effects of the computer program.

[0019] In a second aspect, an analysis system is provided, which is used to analyze a plurality of operation units. The plurality of operation units are used to implement a first instruction set. The first instruction set is obtained by compiling a computer program used to implement an operator, and the first instruction set includes a plurality of instructions. The plurality of instructions have a first execution order, and each instruction is executed by one of the plurality of operation units according to the first execution order. The analysis system includes a monitoring unit and an output unit. The monitoring unit is used to monitor whether each operation unit of the plurality of operation units executes instructions. The output unit is used to output a period in which each operation unit is in an idle state and a period in which each operation unit is in a non-idle state according to whether each operation unit executes instructions. The idle state is used to indicate that no instruction is executed, and the non-idle state is used to indicate that an instruction is executed.

[0020] In some possible implementation manners, the analysis system includes a determination unit. The determination unit is used to obtain a start time and an end time of a first period. The first period is a period in which a first operation unit is in an idle state. The first operation unit belongs to the plurality of operation units. The output unit is further used to output positions of instructions corresponding to the start time and the end time in a second instruction set. The second instruction set is obtained by compiling a computer program used to implement the operator. The first instruction set is a subset of the second instruction set.

[0021] In some possible implementation manners, the first instruction is a instruction corresponding to the start time point or a instruction corresponding to the end time point, a position of the first instruction in the second instruction set is indicated by a computer program corresponding to the first instruction, or is indicated by a position of the computer program corresponding to the first instruction in a computer program used to implement the operator.

[0022] In some possible implementation manners, the output unit is further configured to output a time period during which the second operation unit is in an idle state and a time period during which the second operation unit is in a non-idle state in the first time period. The second operation unit belongs to the plurality of operation units. The second operation unit is configured to execute a second instruction. The second instruction is a instruction between a instruction corresponding to the start time point and a instruction corresponding to the end time point in the first execution order.

[0023] In some possible implementation manners, the instructions executed by the first operation unit are all calculation instructions.

[0024] In some possible implementation manners, the plurality of operation units belong to a same processor.

[0025] In some possible implementation manners, the plurality of operation units are configured to implement a third instruction set. The third instruction set and the first instruction set are obtained by compiling different computer programs used to implement a same operator.

[0026] The monitoring unit is further configured to monitor whether each operation unit executes a instruction in a process of implementing the third instruction set.

[0027] The output unit is further configured to output a time period during which each operation unit is in an idle state and a time period during which each operation unit is in a non-idle state in a process of implementing the third instruction set, and output a time period during which each operation unit is in an idle state and a time period during which each operation unit is in a non-idle state in a process of implementing the first instruction set, according to whether each operation unit executes a instruction in the process of implementing the third instruction set.

[0028] In a third aspect, an analysis device cluster is provided, including at least one analysis device, each analysis device including a processor and a memory.

[0029] The processor of the at least one analysis device is configured to execute instructions stored in the memory of the at least one analysis device, so that the analysis device cluster executes the method of any one of the first aspect.

[0030] In a fourth aspect, a computer program product including instructions is provided, which, when executed by an analysis device, causes the analysis device to execute the method of any one of the first aspect.

[0031] In a fifth aspect, a computer-readable storage medium is provided, and the computer-readable storage medium comprises computer program instructions, when the computer program instructions are executed by an analysis device, the analysis device performs the method according to any one of the first aspect. BRIEF DESCRIPTION OF DRAWINGS

[0032] FIG. 1A is an architecture diagram of an analysis system according to an embodiment of the present application;

[0033] FIG. 1B is an architecture diagram of another analysis system according to an embodiment of the present application;

[0034] FIG. 2 is a flow diagram of an information acquisition method according to an embodiment of the present application;

[0035] FIG. 3A is a schematic diagram of a flow graph according to an embodiment of the present application;

[0036] FIG. 3B is a schematic diagram of another flow graph according to an embodiment of the present application;

[0037] FIG. 3C is a schematic diagram of another flow graph according to an embodiment of the present application;

[0038] FIG. 3D is a schematic diagram of another flow graph according to an embodiment of the present application;

[0039] FIG. 3E is a schematic diagram of another flow graph according to an embodiment of the present application;

[0040] FIG. 4 is a structural diagram of an analysis device according to an embodiment of the present application;

[0041] FIG. 5 is a structural diagram of an analysis device cluster according to an embodiment of the present application;

[0042] FIG. 6 is a structural diagram of another analysis device cluster according to an embodiment of the present application. DETAILED DESCRIPTION

[0043] The embodiments of the present application will be described below with reference to the accompanying drawings.

[0044] Before introducing the embodiments of the present application, the application scenarios involved in the present application are explained.

[0045] An artificial intelligence (AI) model refers to a mathematical model or a computational model used to simulate human intelligent behavior, including neural network models, deep learning models, genetic algorithm models, etc.

[0046] Operators are used to represent basic operations or functions in an AI model. An AI model is usually composed of multiple operators. Operators define the computation process and learning rules of an AI model, thus determining how an AI model learns from input data and how an AI model makes predictions or inferences. For example, a neural network model includes convolution operators, pooling operators, fully connected operators, etc. These operators define the structure and computation process of a neural network, such as convolution operations and pooling operations in a convolutional neural network. A deep learning model includes activation function operators (such as ReLU, Sigmoid), batch normalization operators, Dropout operators, etc. These operators are used to implement various functions and characteristics of a deep learning model. A genetic algorithm model includes selection operators, crossover operators, mutation operators, etc. These operators are used to simulate the biological evolution process to achieve the evolution and optimization of a population.

[0047] An operator developer (hereinafter referred to as a user) implements the operator developed by him or her by writing a computer program. Therefore, when a computing device runs the computer program, it is considered that the operator is implemented. Specifically, the computing device implements the running of the computer program by executing the instruction set compiled from the computer program. Taking a computing device containing an AI accelerator as an example, the specific process of the computing device containing the AI accelerator running the computer program for implementing the operator is as follows: the processor in the computing device controls the compiler in the computing device to compile the computer program into an instruction set containing multiple instructions, the processor sends the instruction set to the AI accelerator, and the control unit in the AI accelerator distributes the instructions in the instruction set to multiple AI processors in the AI accelerator, which execute these instructions in parallel to achieve high-performance processing and computation of the computer program.

[0048] The computing device is an electronic device for computing, processing and storing data, including servers, supercomputers, personal computers, workstations, mobile devices, etc. The AI accelerator is a hardware device specially designed to accelerate the calculation of AI models, which can usually run independently and work with the processors (such as central processing units (CPUs), data processing units (DPUs), graphics processing units (GPUs), etc.) in the computing device. The AI processor, also known as the minimum execution unit, is the basic computing unit in the AI accelerator. The AI processor (such as neural-network processing unit (NPU), tensor processing unit (TPU), machine learning unit (MLU), etc.) is usually designed to be able to execute instructions independently, and multiple AI processors can work in parallel to accelerate the execution efficiency of multiple instructions.

[0049] It should be understood that the above computer program for implementing the operator running on the computing device containing the AI accelerator is only an example and is not limited herein. In actual applications, the computer program for implementing the operator can also run on a computing device containing an AI chip, and the computer program for implementing the operator can also run on a computing device without installing an AI accelerator and an AI chip. The AI chip is a chip integrating a special AI processor (such as an NPU), which is usually integrated in a mobile device, an Internet of Things device or an embedded system, and is used for real-time artificial intelligence inference and processing at the device end.

[0050] Through the above specific process of running the computer program for implementing the operator on the computing device containing the AI accelerator, it can be seen that the instruction set for implementing the operator can be implemented by one AI processor or multiple AI processors. When the instruction set is implemented by multiple AI processors, one of the AI processors only executes part of the instructions in the instruction set.

[0051] Since the AI model is composed of multiple operators, the performance of the AI model training or inference mainly depends on the performance of these operators. Here, the performance of the AI model training or inference represents the time required for the AI model training or inference, and the performance of the operator represents the execution time of the operator. In the process of running the AI model on the computing device, the computing device will reasonably allocate its hardware resources (such as computing resources, storage resources, etc.) to the multiple operators that make up the AI model, so as to fully utilize the allocated hardware resources to accelerate the execution process of the operators.

[0052] Generally, the higher the hardware resource utilization of an operator is, the better the performance of the operator is. Therefore, for a user, the performance of an operator developed by the user can be measured by the hardware resource utilization of the operator. Moreover, the user can also tune the operator according to the hardware resource utilization of the operator. However, the hardware resource utilization of the operator is a statistical index, which can only reflect the overall execution of the operator, and the information provided to the user is very limited, and therefore, the tuning of the operator according to the hardware resource utilization of the operator is inefficient.

[0053] To solve the problem of inefficient tuning of an operator according to the hardware resource utilization of the operator, the present application provides an analysis system, which can be applied to a computing device for implementing an operator. Specifically, during the implementation of the operator, the system monitors whether an operation unit in the computing device executes instructions, and according to the execution of the instructions by the operation unit, outputs to the user the period of time when the operation unit is in an idle state and the period of time when the operation unit is in a non-idle state. Through the output result, the user can obtain the switching time points of the operation unit from busy to idle and from idle to busy during the implementation of the operator, and thus clearly knows the actual use of hardware resources when the operator is executed.

[0054] Referring to FIG. 1A, FIG. 1A is an architecture diagram of an analysis system provided by an embodiment of the present application. As shown in FIG. 1A, the architecture includes a client 100, a computing system 200, and an analysis system 300. The client 100 and the computing system 200, the computing system 200 and the analysis system 300, and the client 100 and the analysis system 300 can communicate through wired or wireless means.

[0055] The client 100 is configured to obtain a computer program input by a user for implementing an operator, and send the computer program to the computing system 200 for processing.

[0056] The computing system 200 is configured to run the computer program, thereby implementing the operator. Specifically, a plurality of instructions obtained by compiling the computer program are executed by a plurality of operation units in the computing system 200.

[0057] The analysis system 300 is configured to obtain the execution of the instructions by the operation units in the computing system 200, analyze the execution of the instructions by the operation units to obtain an analysis result, and send the analysis result to the client 100. Specifically, the analysis system 300 is configured to monitor whether the operation units execute instructions, and according to the execution of the instructions by the operation units, send to the client 100 the period of time when the operation units are in an idle state and the period of time when the operation units are in a non-idle state. The idle state is used to indicate that no instructions are executed, and the non-idle state is used to indicate that instructions are being executed.

[0058] In some possible implementation manners, the client 100, the computing system 200, and the analysis system 300 can be deployed on a computing device. The client 100, the computing system 200, and the analysis system 300 can be deployed on different computing devices, or deployed on the same computing device. When the client 100, the computing system 200, and the analysis system 300 are deployed on different computing devices, at least two of the client 100, the computing system 200, and the analysis system 300 are deployed on different computing devices in the same computing device cluster, or deployed on different computing devices in different computing clusters. The computing device cluster can include a plurality of computing devices as described above. The specific deployment can be determined according to the actual application scenario, and the present application does not make specific limitations.

[0059] In a specific implementation manner, the client 100 can also be deployed on a terminal device. The terminal device is an electronic device for accessing a computing device, including a personal computer, a smart phone, a palm processing device, a tablet computer, a mobile notebook, an integrated palm computer, a smart conference device, a smart advertising device, and the like.

[0060] In some possible implementation manners, the computing unit in the computing system 200 is configured to implement training or inference of an AI model.

[0061] The computing unit in the computing system 200 is a hardware unit in the computing device where the computing system 200 is located, including an arithmetic and logic unit (ALU), a floating point unit (FPU), a vector processing unit (VPU), a storage unit, and the like. The ALU is configured to perform arithmetic and logic operations, including addition, subtraction, multiplication, division, logical and, logical or, and the like. The FPU is configured to perform floating point number operations, including floating point addition, subtraction, multiplication, division, square root, and the like. The VPU is configured to perform vectorization calculation, including matrix multiplication, convolution operation, and the like. The storage unit is configured to store data and intermediate results, including a register file, a cache, and the like.

[0062] Optionally, the computing system 200 is installed with a hardware device or a chip (such as an AI acceleration card, an AI chip, and the like) for accelerating AI model calculation. In this case, the computing unit in the computing system 200 not only includes the hardware unit in the computing device, but also includes the hardware unit in the hardware device or the chip for accelerating AI model calculation.

[0063] Taking an AI acceleration card as an example of a hardware device for accelerating AI model calculation, the operation unit includes an operation unit of an AI processor in the AI acceleration card. The operation unit of the AI processor includes not only an ALU, an FPU, etc., but also a memory transfer engine (MTE) unit, a Cube unit, a Vector unit, etc. Among them, the MTE unit is used for data transmission and management between the global memory of the computing device and the on-chip cache of the AI processor, including data loading, storage, movement, etc. Optionally, the MTE unit includes a first MTE unit and a second MTE unit. The first MTE unit is used for transmitting data in the global memory to the on-chip cache. The second MTE unit is used for transmitting data in the on-chip cache to the global memory. The Cube unit is used for performing a calculation operation on data, such as matrix multiplication, convolution operation, etc. The Vector unit is used for performing a vector operation on data, such as performing a ReLU, Sigmoid, Tanh, etc. activation function on the output data of the AI model.

[0064] For ease of illustration, the following uniformly takes an AI acceleration card as an example of a hardware device or chip for accelerating AI model calculation.

[0065] In some possible implementations, the analysis system 300 includes a plurality of units. For example, referring to FIG. 1B, FIG. 1B is an architecture diagram of another analysis system provided by an embodiment of the present application.

[0066] In FIG. 1B, the analysis system 300 includes a monitoring unit 310, a determination unit 320, and an output unit 330.

[0067] The monitoring unit 310, the determination unit 320, and the output unit 330 can be implemented by software or by hardware. For example, the implementation of the monitoring unit 310 is described below. Similarly, the implementation of the determination unit 320 and the output unit 330 can refer to the implementation of the monitoring unit 310.

[0068] As an example of a software functional unit, the monitoring unit 310 can include code running on a compute instance. The compute instance can include at least one of a physical host (computing device), a virtual machine, a container. Further, the compute instance can be one or more. For example, the monitoring unit 310 can include code running on multiple hosts / virtual machines / containers. It is noted that the multiple hosts / virtual machines / containers running the code can be distributed in the same region, or in different regions. Further, the multiple hosts / virtual machines / containers running the code can be distributed in the same availability zone (AZ), or in different AZs, each of which includes one data center or multiple data centers in close geographical proximity. Typically, a region can include multiple AZs.

[0069] Similarly, the multiple hosts / virtual machines / containers running the code can be distributed in the same virtual private cloud (VPC), or in multiple VPCs. Typically, a VPC is set up within a region, and communication between two VPCs in the same region, or between VPCs in different regions, requires a communication gateway in each VPC to enable interconnection between the VPCs.

[0070] As an example of a hardware functional unit, the monitoring unit 310 can include at least one computing device, such as a server, etc. Alternatively, the monitoring unit 310 can be a device implemented using an application-specific integrated circuit (ASIC), or a programmable logic device (PLD), etc. The PLD can be implemented as a complex programmable logical device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL), a data processing unit (DPU), a neural network processing unit (NPU), a system on chip (SoC), an offload card, an acceleration card, or any combination thereof.

[0071] The multiple computing devices included in the monitoring unit 310 can be distributed in the same region or in different regions. The multiple computing devices included in the monitoring unit 310 can be distributed in the same AZ or in different AZs. Similarly, the multiple computing devices included in the monitoring unit 310 can be distributed in the same VPC or in multiple VPCs. The multiple computing devices can be any combination of servers, ASICs, PLDs, CPLDs, FPGAs GALs, DPUs, NPUs, SoCs, offload cards, acceleration cards, and the like.

[0072] The functions of the various units in the analysis system 300 will be described below.

[0073] The monitoring unit 310 is configured to monitor whether each operation unit in the multiple operation units in the computing system 200 executes instructions. The process can refer to the execution process of step S101 in FIG. 2 described below.

[0074] The determination unit 320 is configured to determine the period of time when each operation unit is in an idle state and the period of time when each operation unit is in a non-idle state according to whether each operation unit executes instructions, wherein the idle state is used to indicate that no instructions are executed, and the non-idle state is used to indicate that instructions are being executed. The process can refer to the execution process of step S102 in FIG. 2 described below.

[0075] The output unit 330 is configured to send the period of time when each operation unit is in an idle state and the period of time when each operation unit is in a non-idle state to the client 100. The process can refer to the execution process of step S103 in FIG. 2 described below.

[0076] It should be understood that the units in the analysis system 300 described above are exemplarily described by taking the monitoring unit 310 to the output unit 330 of the analysis system 300 in FIG. 1B as an example. In actual applications, the analysis system 300 can further include more or fewer units, which are not specifically limited in the present application.

[0077] It should be understood that the architecture of the analysis system in FIG. 1A or FIG. 1B described above is exemplarily described by taking the client 100 and the computing system 200 in communication with the analysis system 300 as an example. In actual applications, the number of the client 100 and the computing system 200 can be one or more, which are not specifically limited in the present application.

[0078] In summary, the analysis system 300 provided by the present application can feed back to the user the switching time points of each operation unit from busy to idle and from idle to busy in the process of running the computer program for implementing the operator, so that the user can clearly know the actual use of hardware resources when the operator is executed.

[0079] The analysis system 300 provided by the embodiments of the present application is introduced above in combination with FIG. 1A and FIG. 1B. Next, a flowchart of an information acquisition method provided by the embodiments of the present application is introduced.

[0080] Referring to FIG. 2, FIG. 2 is a flowchart of an information acquisition method provided by the embodiments of the present application. The information acquisition method provided by the present application is applied to the analysis system 300 in the architecture of the analysis system in FIG. 1A or FIG. 1B. As shown in FIG. 2, the information acquisition method provided by the embodiments of the present application includes the following steps.

[0081] S101: A monitoring unit in the analysis system monitors whether each operation unit in a plurality of operation units executes an instruction.

[0082] The analysis system can be the analysis system 300 in FIG. 1B, and the monitoring unit can be the monitoring unit 310 in the analysis system 300 in FIG. 1B. The range of the operation units monitored by the monitoring unit can be configured as needed, and specific reference can be made to the following application scenario 1 and application scenario 2:

[0083] Application scenario 1: The plurality of operation units monitored by the monitoring unit are used to implement a first instruction set.

[0084] The plurality of operation units belong to a computing system. The computing system can be the computing system 200 in FIG. 1B.

[0085] The first instruction set is compiled from a computer program used to implement an operator. The first instruction set includes a plurality of instructions. The instructions in the first instruction set have a first execution order, and each instruction is executed by one of the plurality of operation units according to the first execution order. In a possible application scenario, the computer program used to compile the first instruction set is part of the entire computer program used to implement the operator, and therefore, for the sake of distinction, the instruction set compiled from the entire computer program used to implement the operator is referred to as a second instruction set. Therefore, the first instruction set is a subset of the second instruction set.

[0086] In application scenario 1, if the AI acceleration card is not installed in the computing system, the plurality of operation units used to implement the first instruction set are all operation units in the same processor in the computing device, such as ALU, FPU, VPU, etc. If the AI acceleration card is installed in the computing system, the plurality of operation units are all operation units in the same AI processor in the AI acceleration card, such as the first MTE unit, the second MTE unit, the Cube unit, etc. The computing system can be the computing system 200 in FIG. 1B. For the sake of convenience, the related content about application scenario 1 is uniformly described below by taking the plurality of operation units belonging to the same AI processor as an example.

[0087] In some possible implementations, the instructions in the first instruction set are of different types, such as a data load instruction, a store instruction, a compute instruction, and the like. Among them, the data load instruction is used to instruct to load data from the global memory of the computing device to the on-chip cache of the AI processor. The store instruction is used to instruct to store data from the on-chip cache of the AI processor to the global memory of the computing device. The compute instruction is used to instruct to perform a compute operation, such as a matrix multiplication, a convolution operation, an activation function, and the like.

[0088] Generally, the instructions executed by one operation unit are all instructions of the same type. Continuing to take the first MTE unit, the second MTE unit, and the Cube unit in the same AI processor as an example of the plurality of operation units, the instructions executed by the first MTE unit are all data load instructions, the instructions executed by the second MTE unit are all store instructions, and the instructions executed by the Cube unit are all compute instructions.

[0089] In application scenario 1, the plurality of operation units executes the instructions in the first instruction set according to a first execution order. Among them, each instruction is executed by one of the plurality of operation units. Continuing to take the first MTE unit, the second MTE unit, and the Cube unit in the same AI processor as an example of the plurality of operation units, since the compute operation involves data, the execution of one compute instruction by the Cube unit often needs the cooperation of the first MTE unit and the second MTE unit. First, the data load instruction is executed by the first MTE unit to load the data to be computed from the global memory of the computing device to the on-chip cache of the AI processor. After the first MTE unit completes the data load instruction, the compute instruction is executed by the Cube unit, specifically, the Cube unit reads the data to be computed from the on-chip cache, performs computation on the data to be computed, obtains the computation result, and writes the computation result to the on-chip cache of the AI processor. After the Cube unit completes the compute instruction, the store instruction is executed by the second MTE unit to store the computation result from the on-chip cache of the AI processor to the global memory of the computing device.

[0090] It can be considered that the data load instruction, the compute instruction, and the store instruction generally exist in a matched manner and have a relatively fixed execution order. When the first instruction set includes a plurality of compute instructions that need to be executed by the Cube unit, the Cube unit can only execute these compute instructions one by one. When the execution order of these compute instructions on the Cube unit is determined, since the data load instruction and the store instruction matched with each compute instruction already have a relatively fixed execution order with the compute instruction, the execution order of all instructions in the first instruction set can be obtained, that is, the first execution order.

[0091] Application scenario 2: The plurality of operation units monitored by the monitoring unit are used to implement a second instruction set.

[0092] The second instruction set is compiled from the entire computer program for implementing the operator.

[0093] In application scenario 2, if no AI acceleration card is installed in the computing system, the plurality of operation units belong to different processors in the computing device. If an AI acceleration card is installed in the computing system, the plurality of operation units belong to different AI processors in the AI acceleration card. Specifically, the controller in the AI acceleration card distributes the instructions in the second instruction set to the plurality of AI processors in the AI acceleration card, and the plurality of AI processors execute the instructions in the second instruction set in parallel, thereby implementing the operator. Therefore, each AI processor obtains part of the instructions in the second instruction set. It can be considered that each of the AI processors obtains the first instruction set, and each AI processor is used to implement the first instruction set. The plurality of operation units for implementing the second instruction set in application scenario 2 are collectively composed of all the operation units in the AI processors. Moreover, the plurality of operation units in application scenario 2 include the plurality of operation units in application scenario 1.

[0094] In some possible implementation manners, the instructions in the second instruction set have different types, such as data loading instructions, storage instructions, computing instructions, and the like.

[0095] In application scenario 2, different AI processors independently execute the first instruction set assigned to them. The process in which the first AI processor implements the first instruction set assigned to the first AI processor does not interfere with the process in which the second AI processor implements the first instruction set assigned to the second AI processor. This means that the time period in which the first AI processor implements the first instruction set may or may not overlap with the time period in which the second AI processor implements the first instruction set.

[0096] In some possible implementation manners, the monitoring period of the monitoring unit is related to the application scenario.

[0097] In application scenario 1 corresponding to step S101, since the plurality of operation units are used to implement the first instruction set, the monitoring unit can monitor whether each operation unit executes instructions in real time in the process of implementing the first instruction set, in the process of implementing the second instruction set, or at the start time of the operation of each operation unit. The process of implementing the first instruction set specifically refers to the process from the execution of the first instruction in the first instruction set to the execution of the last instruction in the first instruction set. The process of implementing the second instruction set specifically refers to the process from the execution of the first instruction in the second instruction set to the execution of the last instruction in the second instruction set.

[0098] Corresponding to the application scenario 2 of step S101, since multiple operation units are used to implement the second instruction set, the monitoring unit can either monitor in real time whether each operation unit executes instructions in the process of implementing the second instruction set, or monitor whether each operation unit executes instructions all the time from the start time of the operation of the operation unit.

[0099] In some possible implementation manners, the monitoring unit communicates with each operation unit through a debugging interface or a driver, and acquires the execution state of each operation unit in real time, so as to realize real-time monitoring of whether each operation unit executes instructions. Real-time monitoring generally refers to continuous monitoring of the change of a certain index or state at a very short time interval. Generally, real-time monitoring can be performed at a time interval of microseconds or shorter. Real-time monitoring of whether an operation unit executes instructions means continuous monitoring of the execution state of the operation unit at a very short time interval. The execution state refers to whether the operation unit is executing instructions. If the operation unit does not execute instructions, the execution state is an idle state; if the operation unit is executing instructions, the execution state is a non-idle state.

[0100] Specifically, the operation unit generally provides a debugging interface or a communication interface.

[0101] When the monitoring unit connects the debugging interface of the operation unit, the monitoring unit can acquire the execution state of the operation unit in real time through the debugging interface. The process can refer to the process of acquiring the execution state of a CPU by using a software performance analysis tool (such as AMD CodeXL), a hardware performance analyzer (such as a JTAG Debugger), and the like, and will not be described in detail here for the sake of brevity of the description.

[0102] When the monitoring unit connects the communication interface of the operation unit, the monitoring unit can send a command to the operation unit through a driver, and receive the execution state returned by the operation unit according to the command. In this scenario, the monitoring unit sends a command to the operation unit in real time, and thus the monitoring unit can obtain the real-time execution state of the operation unit.

[0103] In a specific implementation manner, the monitoring unit can also acquire instruction execution information of the operation unit in real time through the debugging interface or the communication interface. The instruction execution information refers to specific information of the instruction being executed by the operation unit, including information such as the type, execution phase, and execution cycle of the instruction.

[0104] S102: The determining unit in the analysis system determines the period in which each operation unit is in an idle state and the period in which each operation unit is in a non-idle state according to whether each operation unit executes instructions.

[0105] The determining unit can be the determining unit 320 in the analysis system 300 in FIG. 1B.

[0106] The monitoring unit of the analysis system monitors each operation unit in real time to determine whether the operation unit executes instructions, and obtains a monitoring result of each operation unit in a monitoring period. The determining unit determines a period in which the operation unit executes instructions and a period in which the operation unit does not execute instructions according to the monitoring result of the operation unit. Since the execution state corresponding to the period in which the operation unit executes instructions is a non-idle state and the execution state corresponding to the period in which the operation unit does not execute instructions is an idle state, the determining unit can obtain a period in which the operation unit is in the non-idle state and a period in which the operation unit is in the idle state.

[0107] In the application scenario 1 of the step S101, if the monitoring period is a process of implementing the first instruction set and the plurality of operation units are the first MTE unit, the second MTE unit, and the Cube unit in the same AI processor, the determining unit can obtain the periods in which the first MTE unit, the second MTE unit, and the Cube unit are in the non-idle state and the periods in which the first MTE unit, the second MTE unit, and the Cube unit are in the idle state according to the monitoring results of the first MTE unit, the second MTE unit, and the Cube unit, respectively.

[0108] For example, the monitoring period is 0-10 (unit: microsecond / μs), and the monitoring results of the first MTE unit, the second MTE unit, and the Cube unit are shown in Table 1 below. In order to simplify the description, Table 1 indicates that no instruction is executed by “0” and that an instruction is executed by “1”.

[0109] Table 1

[0110] From Table 1, it can be seen that:

[0111] The period in which the first MTE unit is in the non-idle state is 0-2 and 5-6.5, and the remaining periods are in the idle state.

[0112] The period in which the second MTE unit is in the non-idle state is 4-5 and 8.5-10, and the remaining periods are in the idle state.

[0113] The period in which the Cube unit is in the non-idle state is 2-4 and 6.5-8.5, and the remaining periods are in the idle state.

[0114] It should be understood that the monitoring period and the monitoring result in the example of the application scenario 1 described above are only examples, and the present application is not limited in this regard.

[0115] In the application scenario 2 of the step S101, if the monitoring period is a process of implementing the second instruction set and the plurality of operation units include operation units in a plurality of AI processors, the determining unit can also obtain the periods in which each operation unit is in the non-idle state and the periods in which each operation unit is in the idle state according to the monitoring result of each operation unit.

[0116] Exemplarily, the monitoring period is 0-30 (unit: microsecond / μs), the plurality of operation units include operation units in the first AI processor and the second AI processor, and specifically include a first MTE unit, a second MTE unit and a Cube unit in the first AI processor, and a first MTE unit, a second MTE unit and a Cube unit in the second AI processor.

[0117] In the above example, the first MTE unit, the second MTE unit and the Cube unit in the first AI processor can correspond to the first MTE unit, the second MTE unit and the Cube unit in the same AI processor in the above example of the application scenario 1 respectively. The monitoring results of the first MTE unit, the second MTE unit and the Cube unit in the first AI processor are shown in Table 2 below; the monitoring results of the first MTE unit, the second MTE unit and the Cube unit in the second AI processor are shown in Table 3 below. For the sake of simplicity of the description, “0” in Tables 2 and 3 indicates that no instruction is executed; and “1” indicates that an instruction is being executed.

[0118] Table 2

[0119] Table 3

[0120] From Table 2, it can be seen that in the first AI processor,

[0121] The period in which the first MTE unit is in a non-idle state is 0-2, 5-6.5;

[0122] The period in which the second MTE unit is in a non-idle state is 4-5, 6.5-10;

[0123] The period in which the Cube unit is in a non-idle state is 2-4, 6.5-8.5;

[0124] From Table 3, it can be seen that in the second AI processor,

[0125] The period in which the first MTE unit is in a non-idle state is 5-8, 14-18;

[0126] The period in which the second MTE unit is in a non-idle state is 12-14, 28-30;

[0127] The period in which the Cube unit is in a non-idle state is 8-12, 18-28;

[0128] In the monitoring period, the period in which each operation unit is not in a non-idle state is the period in which each operation unit is in an idle state.

[0129] It should be understood that the monitoring period and the monitoring results in the above example are only an example, and the present application is not limited in this regard.

[0130] S103: The output unit in the analysis system sends to the client the time period in which each operation unit is in an idle state and the time period in which each operation unit is in a non-idle state.

[0131] The output unit can be the output unit 330 in the analysis system 300 in FIG. IB.

[0132] In some possible implementation manners, the output unit outputs the time period in which each operation unit is in different states in multiple ways, which can be specifically referred to as the following output manner 1-output manner 3:

[0133] Output manner 1: The output unit summarizes the time period in which each operation unit is in an idle state and the time period in which each operation unit is in a non-idle state, and sends the time period to the client in the form of a table. Accordingly, the client receives an execution situation table. Each entry in the execution situation table is the time period in which an operation unit is in an idle state and the time period in which the operation unit is in a non-idle state within a monitoring time period.

[0134] Corresponding to the example of application scenario 1 of the above step S102, the execution situation table can be Table 1 in the above step S102.

[0135] Corresponding to the example of application scenario 2 of the above step S102, the execution situation table includes Table 2 and Table 3 in the above step S102, and can be a combined table of Table 2 and Table 3, for example.

[0136] Output manner 2: The output unit records the time period in which each operation unit is in an idle state and the time period in which each operation unit is in a non-idle state, and sends the time period to the client in the form of a document. Accordingly, the client receives an execution situation document.

[0137] Corresponding to the example of application scenario 1 of the above step S102, the specific content of the execution situation document is:

[0138] “The time period in which the first MTE unit is in a non-idle state is: 0-2, 5-6.5, and the time period in which the first MTE unit is in an idle state is: 2-5, 6.5-10;

[0139] The time period in which the second MTE unit is in a non-idle state is: 4-5, 8.5-10, and the time period in which the second MTE unit is in an idle state is: 0-4, 6.5-8.5;

[0140] The time period in which the Cube unit is in a non-idle state is: 2-4, 6.5-8.5, and the time period in which the Cube unit is in an idle state is: 0-2, 4-6.5, 8.5-10.”

[0141] Corresponding to the example of application scenario 2 of step S102 described above, the specific content of the execution case document includes the first MTE unit, the second MTE unit, the Cube unit in the first AI processor, the period in which the first MTE unit, the second MTE unit, the Cube unit in the second AI processor are in the idle state within 0-30 μs, and the period in which they are in the non-idle state.

[0142] Output mode 3: the output unit draws the period in which each operation unit is in the idle state and the period in which it is in the non-idle state, and sends it to the client in the form of a picture. Correspondingly, the client receives the flow chart.

[0143] Corresponding to the example of application scenario 1 of step S102 described above, the flow chart is shown in FIG. 3A. Referring to FIG. 3A, FIG. 3A is a schematic diagram of a flow chart provided by an embodiment of the present application.

[0144] Corresponding to the example of application scenario 2 of step S102 described above, the flow chart is shown in FIG. 3B. Referring to FIG. 3B, FIG. 3B is a schematic diagram of another flow chart provided by an embodiment of the present application.

[0145] As can be seen from FIGS. 3A and 3B, the flow chart can intuitively show the switching time points of the operation unit from busy to idle and from idle to busy.

[0146] It should be understood that the output modes 1-3 of the periods in which the operation unit is in different states described above are only examples, and in actual application, other ways of outputting the periods in which the operation unit is in different states can also be used, which are not limited in the present application.

[0147] In summary, in the process of implementing the operator, i.e., in the process of executing the instructions in the first instruction set, by monitoring the execution of the instructions by the operation unit, the periods in which the operation unit is in the idle state and the periods in which it is in the non-idle state are obtained according to the execution of the instructions by the operation unit and fed back to the user, so that the user can obtain the switching time points of the operation unit from busy to idle and from idle to busy in the process of implementing the operator through the output result, and thus clearly know the actual use of the hardware resources when the operator is executed. In addition, the present technical solution does not need to repeatedly run the computer program, and only needs to run the computer program once (i.e., execute the first instruction set once), to obtain the actual use of the hardware resources when the operator is executed.

[0148] In some possible implementation manners, the starting time and the ending time of the first period are obtained by the determination unit in step S102 described above, and the positions of the instructions corresponding to the starting time and the ending time in the second instruction set are determined; then the positions of the instructions corresponding to the starting time and the ending time in the second instruction set are sent to the client by the output unit in step S103 described above.

[0149] The first time period is a time period in which the first operation unit is in an idle state. The first operation unit belongs to a plurality of operation units.

[0150] Continuing with the above-mentioned application scenario 1 of step S101, the first operation unit can be a first MTE unit, a second MTE unit, or a Cube unit in the same AI processor. Taking the Cube unit as the first operation unit as an example, in the above-mentioned example of application scenario 1 of step S102, the first time period can be 0-2, 4-6.5, or 8.5-10. Taking 4-6.5 as the first time period as an example, the start time of the first time period is 4, and the end time is 6.5.

[0151] Optionally, the instructions executed by the first operation unit are all calculation instructions.

[0152] Optionally, among all time periods in which the first operation unit is in an idle state, a time period with a duration greater than or equal to a specified duration is taken as the first time period. The specified duration is determined by a user.

[0153] The above-mentioned manner of determining the positions of the start time and the end time of the first time period in the second instruction set can be automatically determined by the analysis system, or can be determined by the analysis system in combination with a user-provided dotting command. The dotting command is used to indicate the output of preset information (such as a specific string, a value of a variable, a path of a computer program execution, etc.).

[0154] The automatic determination manner by the analysis system is as follows:

[0155] The instruction corresponding to the start time or the instruction corresponding to the end time is taken as the first instruction, and the computer program corresponding to the first instruction is determined. The position of the first instruction in the second instruction set can be represented by the specific content of the computer program corresponding to the first instruction, or by the position of the computer program corresponding to the first instruction in the entire computer program for implementing the operator (such as the code line number of the computer program).

[0156] When the position of the first instruction in the second instruction set is represented by the specific content of the computer program corresponding to the first instruction, the output unit sends the specific content of the computer program corresponding to the instruction corresponding to the start time and the specific content of the computer program corresponding to the instruction corresponding to the end time to the client. The user can then find the computer program corresponding to the instruction corresponding to the start time and the computer program corresponding to the instruction corresponding to the end time in the entire computer program developed by the user for implementing the operator, and optimize the computer program between the two computer programs as the computer program to be optimized to improve the performance of the operator.

[0157] When the position of the first instruction in the second instruction set is represented by the position (e.g., the line number of the computer program) of the computer program corresponding to the first instruction in the entire computer program for implementing the operator, the output unit sends the line number (e.g., line 10) of the computer program corresponding to the instruction at the start time and the line number (e.g., line 22) of the computer program corresponding to the instruction at the end time to the client. The user can then find the computer program between line 10 and line 22 in the entire computer program for implementing the operator developed by the user as the computer program to be optimized for optimization to improve the performance of the operator.

[0158] The implementation manner determined by the analysis system in combination with the provided dotting command is as follows:

[0159] After the user obtains the start time and the end time of the first time period through the client, the user finds the computer program to be confirmed from the entire computer program for implementing the operator according to the start time and the end time. Then, the user inserts the dotting command before and after the computer program to be confirmed, that is, inserts two dotting commands.

[0160] The user sends the entire computer program containing the two dotting commands to the computing system through the client. The computing system then compiles the computer program containing the two dotting commands to obtain a new second instruction set. The plurality of operation units in the computing system that implement the original second instruction set continue to implement the new second instruction set.

[0161] In the process of implementing the new second instruction set, the analysis system monitors whether the instruction compiled by the dotting command is executed. When the analysis system monitors that the execution of the instruction compiled by one of the dotting commands starts, the analysis system records the time when the execution starts as the first time. When the analysis system monitors that the execution of the instruction compiled by the other dotting command starts, the analysis system records the time when the execution starts as the second time. Then, the analysis system sends the first time and the second time to the client.

[0162] Optionally, to facilitate the user to observe, the analysis system can send the first time, the second time, and the flowchart as the output result to the user. Specifically, on the flowchart of the period in the idle state and the period in the non-idle state during the process of recording the implementation of the original second instruction set or the new second instruction set by each operation unit, the first time and the second time are marked, and the start time and the end time of the first time period are marked. In the case where the first operation unit is a Cube unit, the start time of the first time period is 4, and the end time of the first time period is 6.5, the marking result is shown in FIG. 3C. Referring to FIG. 3C, FIG. 3C is a schematic diagram of another flowchart provided by an embodiment of the present application.

[0163] After the user obtains the first time and the second time through the client, the first time, the second time, and the start time and the end time of the first time period are compared, so as to determine whether the computer program to be confirmed is the computer program to be optimized.

[0164] If the first time is close to the start time of the first time period and the second time is close to the end time of the first time period, it indicates that the computer program to be confirmed is the computer program to be optimized, and the position of the computer program to be confirmed in the entire computer program for implementing the operator is the position of the instructions corresponding to the start time and the end time of the first time period in the second instruction set.

[0165] If the first time is not close to the start time of the first time period or the second time is not close to the end time of the first time period, it indicates that the computer program to be confirmed is not the computer program to be optimized, and then the user needs to find a new computer program to be confirmed from the entire computer program again, and use the analysis system to determine whether the new computer program to be confirmed is the computer program to be optimized until the user finds the computer program to be optimized.

[0166] In summary, after the time period in which the first operation unit is in the idle state is determined, the user is provided with the related instructions for making the first operation unit in the idle state. It can be understood that the related instructions for making the first operation unit in the idle state are equivalent to the instructions for reducing the utilization rate of the first operation unit, that is, the problem instructions, and therefore, the position of the problem instructions is fed back to the user, so as to facilitate the user to find the part to be optimized in the entire computer program being developed by the user.

[0167] In addition, the specific content or specific position of the computer program corresponding to the problem instructions is used to represent the position of the problem instructions, so that the user can be provided with information familiar to the user, thereby improving the user experience.

[0168] In the scenario in which the instructions executed by the first operation unit are all computing instructions, since the execution time of the computing instructions is long, the use time of the operation unit executing the computing instructions determines the execution time of the operator to a great extent, that is, the performance of the operator, and therefore, the technical solution can focus on analyzing the actual use of the operation unit executing the computing instructions, and guiding the user to optimize the computer program being developed by the user in the direction of improving the utilization rate of the operation unit executing the computing instructions.

[0169] In the scenario in which the length of the first time period is greater than or equal to the specified length, the technical solution can focus on analyzing the time period with a large length in all time periods in which the first operation unit is in the idle state, so as to guide the user to optimize the computer program being developed by the user in the direction of greatly improving the utilization rate of the operation unit.

[0170] In some possible implementation manners, the output unit sends, to the client, a time period during which the second operation unit is in an idle state and a time period during which the second operation unit is in a non-idle state in the first time period.

[0171] The second operation unit is an operation unit of the plurality of operation units for executing the second instruction. The second instruction is an instruction between the instruction corresponding to the start time and the instruction corresponding to the end time. When the plurality of operation units to which the second operation unit belongs are used to implement the first instruction set, the second instruction is an instruction between the instruction corresponding to the start time and the instruction corresponding to the end time in the first execution order.

[0172] The following is an example in combination with FIG. 3D. Referring to FIG. 3D, FIG. 3D is a schematic diagram of another pipeline diagram provided by an embodiment of the present application.

[0173] In FIG. 3D, the first operation unit is a Cube unit, the start time of the first time period is 4, and the end time is 6.5.

[0174] Because between the completion of a calculation instruction (that is, the instruction corresponding to the start time of the first time period) by the Cube unit 4 and the start of another calculation instruction (that is, the instruction corresponding to the end time of the first time period) at 6.5, a storage instruction is executed by the second MTE unit first, and then a data loading instruction is executed by the first MTE unit, the storage instruction and the data loading instruction are both second instructions, and the first MTE unit and the second MTE unit are both second operation units.

[0175] Therefore, the output unit needs to send, to the client, a time period during which the first MTE unit is in an idle state and a time period during which the first MTE unit is in a non-idle state between 4 and 6.5, and a time period during which the second MTE unit is in an idle state and a time period during which the second MTE unit is in a non-idle state between 4 and 6.5. If the pipeline diagram is sent to the client in the form of a pipeline diagram, the sending result is shown in the pipeline diagram in the dashed box in FIG. 3D.

[0176] It should be understood that the pipeline diagram in the dashed box in FIG. 3D that needs to be sent to the client is determined when the first operation unit is a Cube unit, the start time of the first time period is 4, and the end time is 6.5. If the first operation unit is another operation unit, or the first time period is another time period, the specific content of the pipeline diagram in the dashed box in FIG. 3D that needs to be sent to the client will change. In actual applications, the pipeline diagram in the dashed box in FIG. 3D that needs to be sent to the client can be determined according to user needs or actual application scenarios, and the present application does not make specific limitations.

[0177] To sum up, the technical solution can not only provide the user with the location of the problem instruction, but also provide the user with the problem scene: the case where other operation units execute instructions when the first operation unit is in an idle state. The problem scene can reflect which operation units are working when the first operation unit is in an idle state, the specific case where these operation units execute instructions, the correlation between the execution of instructions by these operation units, and the information that the first operation unit is not working because it is waiting for the processing result of which operation unit. The information reflected by the problem scene can guide the user to optimize the computer program in the right direction and improve the user's optimization efficiency. In addition, the technical solution can only analyze, record, and feedback the problem instruction and the corresponding problem scene, without recording and feeding back the execution case and scene of each instruction. Therefore, the technical solution records and feeds back a small amount of information with high information quality, which reduces the storage requirement of the analysis system and facilitates the user to directly obtain useful information to optimize the computer program being developed by the user and improve the user's optimization efficiency.

[0178] In the embodiments of the present application, in order to distinguish the operation units in different application scenarios (including application scenario 1 and application scenario 2) in the above step S101, each operation unit in the plurality of operation units for implementing the second instruction set in the application scenario 2 can be referred to as a third operation unit. In the application scenario 2, the analysis system implements monitoring whether the third operation unit executes instructions, determining and outputting the period in which the third operation unit is in an idle state and the period in which the third operation unit is in a non-idle state according to whether the third operation unit executes instructions. The specific execution process can be referred to the related description of the application scenario 2 in the above steps S101, S102, and S103, which will not be described here again.

[0179] In some possible application scenarios, the user optimizes the computer program for implementing the operator according to the feedback result of the analysis system, obtains an optimized computer program, and records the optimized computer program on the client. Then, the client sends the optimized computer program to the computing system. The computing system compiles the optimized computer program to obtain a third instruction set. The plurality of operation units for implementing the first instruction set in the computing system continue to implement the third instruction set. Since the first instruction set is obtained by compiling the computer program before optimization, and the third instruction set is obtained by compiling the computer program after optimization, the first instruction set and the third instruction set are different instruction sets. The process of implementing the third instruction set by the plurality of operation units is similar to the process of implementing the first instruction set by the plurality of operation units in the application scenario 1 of the above step S101, which will not be described here again.

[0180] In the process of implementing the third instruction set, the analysis system monitors whether each operation unit executes instructions, and according to whether each operation unit executes instructions, outputs a period in which each operation unit is in an idle state and a period in which each operation unit is in a non-idle state in the process of implementing the third instruction set, and outputs a period in which each operation unit is in an idle state and a period in which each operation unit is in a non-idle state in the process of implementing the first instruction set. The process can refer to the above-mentioned descriptions about the application scenario 1 in steps S101, S102 and S103, and will not be described here again.

[0181] In this application scenario, if the results are output in the form of a flowchart, the output results are as shown in FIG. 3E. Referring to FIG. 3E, which is a schematic diagram of another flowchart provided by an embodiment of the present application, a user can understand whether the utilization rate of each operation unit is significantly improved by observing FIG. 3E, compared with the computer program before optimization.

[0182] It should be noted that in the application scenario 2 of step S101, the analysis system can also output a period in which each operation unit is in an idle state and a period in which each operation unit is in a non-idle state in the process of implementing the instruction set compiled by the optimized entire computer program, and output a period in which each operation unit is in an idle state and a period in which each operation unit is in a non-idle state in the process of implementing the instruction set (i.e., the second instruction set) compiled by the entire computer program before optimization.

[0183] In summary, in the scenario of running the computer program optimized by the user, the execution of instructions of each operation unit before and after optimization is provided to the user, so that the user can compare the overall optimization effect of the computer program.

[0184] Referring to FIG. 4, which is a structural schematic diagram of an analysis device provided by an embodiment of the present application, as shown in FIG. 4, the analysis device 400 provided by the present application includes a bus 401, a processor 402, a memory 403 and a communication interface 404. The processor 402, the memory 403 and the communication interface 404 communicate through the bus 401. The analysis device 400 can be a server or a terminal device. It should be understood that the number of processors and memories in the analysis device 400 is not limited by the present application.

[0185] The bus 401 can be a peripheral component interconnect Express (PCIe) bus or an extended industry standard architecture (EISA) bus, a unified bus (Ubus or UB), a compute express link (CXL), a cache coherent interconnect for accelerators (CCIX), or the like. Among them, the unified bus is also referred to as a coherent bus. The bus can be divided into an address bus, a data bus, a control bus, and the like. For ease of representation, only one line is represented in FIG. 4, but it does not mean that there is only one bus or only one type of bus. The bus 401 can include a path for transmitting information between various components (for example, the memory 403, the processor 402, the communication interface 404) of the analysis device 400.

[0186] The processor 402 can include any one or more of a central processing unit (CPU), a graphics processing unit (GPU), a microprocessor (MP), or a digital signal processor (DSP), an ASIC, a FPGA, a CPLD, an NPU, a SoC, an offload card, an acceleration card, or the like.

[0187] The memory 403 can include a volatile memory, such as a random access memory (RAM). The processor 402 can also include a non-volatile memory, such as a read-only memory (ROM), a flash memory, a hard disk drive (HDD), or a solid state drive (SSD). In addition, the memory 403 can also be implemented through a storage class memory (SCM), a phase change memory (PCM), or other types of storage media.

[0188] It is worth mentioning that the same type of storage medium can be configured in the same analysis device to realize the function of the storage 403, or two or more types of storage media can be configured to realize the function of the storage 403, and the present application does not limit this.

[0189] The storage 403 stores executable program codes, and the processor 402 executes the executable program codes to realize the functions of the monitoring unit 310 and the output unit 330 in the analysis system 300 of FIG. 1B respectively, so as to execute the steps executed by the monitoring unit and the output unit in the analysis system in the information acquisition method of FIG. 2 respectively.

[0190] Optionally, the program codes for realizing the functions of the monitoring unit 310 and the output unit 330 in the storage 403 can also be dynamically adjusted according to business needs, so that the program codes stored in the storage 403 can also realize the functions of one or more of the monitoring unit 310, the determination unit 320 and the output unit 330 in the analysis system 300 of FIG. 1B. For example, the program codes for realizing the function of the output unit 330 in the storage 403 can not only realize the function of the output unit 330 in the analysis system 300 of FIG. 1B, but also realize the function of the determination unit 320 in the analysis system 300 of FIG. 1B.

[0191] In summary, the storage 403 stores instructions for executing the information acquisition method of FIG. 2. For brevity, this will not be repeated here.

[0192] The communication interface 404 uses a transceiver module such as but not limited to a network interface card and a transceiver to realize the communication between the analysis device 400 and other analysis devices or communication networks.

[0193] As a possible implementation manner, the analysis device 400 can also include a chip system including a processor and a power supply circuit for supplying power to the processor, and the processor is used to execute the operation steps executed by the analysis system in the information acquisition method of FIG. 2. Optionally, the processor can realize the functions of one or more of the monitoring unit 310, the determination unit 320 and the output unit 330 in the analysis system 300 of FIG. 1B by executing the program codes stored in the storage 403 in the analysis device 400, so as to realize the operation steps executed by the analysis system in the information acquisition method of FIG. 2. The processor can be realized by a CPU, or by a GPU, a DPU, a NPU, an XPU, a SoC, an offload card, an acceleration card or an AI chip.

[0194] As a possible implementation, a plurality of types of processors 402 can be included in the analysis device 400, i.e., the analysis device 400 is a heterogeneous device, for example, the analysis device 400 includes a CPU and a GPU, and the operations performed by the analysis system in the information acquisition method of FIG. 2 can be performed by at least one of the processors 402.

[0195] Referring to FIG. 5, FIG. 5 is a structural diagram of an analysis device cluster according to an embodiment of the present application. The analysis device cluster according to the present application includes at least one analysis device. The analysis device can be a server, for example, a central server, an edge server, or a local server in a local data center. In some embodiments, the analysis device can also be a terminal device such as a desktop computer, a notebook computer, or a smart phone.

[0196] As shown in FIG. 5, the analysis device cluster includes at least one analysis device 400. The memory 403 in one or more analysis devices 400 in the analysis device cluster can store the same instructions for performing the steps performed by the analysis system in the information acquisition method of FIG. 2.

[0197] In some possible implementations, the memory 403 in one or more analysis devices 400 in the analysis device cluster can also respectively store partial instructions for performing the steps performed by the analysis system in the information acquisition method of FIG. 2. In other words, the combination of one or more analysis devices 400 can collectively execute the instructions for performing the steps performed by the analysis system in the information acquisition method of FIG. 2.

[0198] It should be noted that the memories 403 in different analysis devices 400 in the analysis device cluster can store different instructions for respectively performing part of the functions of the analysis system 300 in FIG. 1B. That is, the instructions stored in the memories 403 in different analysis devices 400 can implement the functions of one or more of the monitoring unit 310 and the output unit 330.

[0199] Optionally, the program codes in the memory 403 for implementing the functions of the monitoring unit 310 and the output unit 330 can also be dynamically adjusted according to business needs, so that the program codes stored in the memory 403 can also implement the functions of one or more of the monitoring unit 310, the determination unit 320, and the output unit 330 in the analysis system 300 of FIG. 1B.

[0200] Referring to FIG. 6, FIG. 6 is a structural schematic diagram of another analysis device cluster provided by an embodiment of the present application. In some possible implementation manners, one or more analysis devices in the analysis device cluster can be connected through a network. The network can be a wide area network or a local area network, etc. As shown in FIG. 6, two analysis devices 400A and 400B are connected through a network. Specifically, the communication interfaces in the analysis devices are connected to the network. In this kind of possible implementation manner, the memory 403 in the analysis device 400A stores instructions for executing the function of the monitoring unit 310. The memory 403 in the analysis device 400B stores instructions for executing the function of the output unit 330.

[0201] The connection manner between the analysis devices in FIG. 6 can be that, considering that the information acquisition method provided by the present application needs to output a large amount of analysis results, the function implemented by the output unit 330 is executed by the analysis device 400B.

[0202] It should be understood that the function of the analysis device 400A shown in FIG. 6 can also be completed by multiple analysis devices 400. Similarly, the function of the analysis device 400B can also be completed by multiple analysis devices 400.

[0203] The present application also provides another analysis device cluster. The connection relationship between the analysis devices in the analysis device cluster can be similar to the connection manners of the analysis device clusters described with reference to FIG. 5 and FIG. 6. The difference is that the memory 403 in one or more analysis devices 400 in the analysis device cluster can store the same instructions for executing the steps executed by the analysis system in the information acquisition method of FIG. 2.

[0204] In some possible implementation manners, the memory 403 of one or more analysis devices 400 in the analysis device cluster can also respectively store part of the instructions for executing the steps executed by the analysis system in the information acquisition method of FIG. 2. In other words, the combination of one or more analysis devices 400 can collectively execute the instructions for executing the steps executed by the analysis system in the information acquisition method of FIG. 2.

[0205] It should be noted that the memory 403 in different analysis devices 400 in the analysis device cluster can store different instructions for respectively executing part of the functions of the analysis system 300 in FIG. 1B. That is, the instructions stored in the memory 403 in different analysis devices 400 can implement the function of one or more of the monitoring unit 310 and the output unit 330.

[0206] Optionally, the program codes stored in the memory 403 for implementing the functions of the monitoring unit 310 and the output unit 330 can also be dynamically adjusted according to the business requirements, so that the program codes stored in the memory 403 can also implement the functions of one or more of the monitoring unit 310, the determining unit 320 and the output unit 330 of the analysis system 300 in FIG. 1B.

[0207] The embodiments of the present application further provide a computer program product containing instructions. The computer program product can be a software or program product containing instructions, which can run on an analysis device or be stored in any available medium. When the computer program product runs on at least one analysis device, the at least one analysis device is caused to perform the steps performed by the analysis system in the information acquisition method in FIG. 2.

[0208] The embodiments of the present application further provide a computer readable storage medium. The computer readable storage medium can be any available medium that can be stored by an analysis device or a data storage device such as a data center containing one or more available media. The available medium can be a magnetic medium (for example, a floppy disk, a hard disk, a magnetic tape), an optical medium (for example, a DVD), or a semiconductor medium (for example, a solid state disk) and the like. The computer readable storage medium contains instructions, which instruct the analysis device to perform the steps performed by the analysis system in the information acquisition method in FIG. 2.

[0209] It should be understood that, in the embodiments of the present application, “when”, “if” and “when” all refer to the device making corresponding processing under certain objective conditions, and are not limited to time, and do not require the device to have a judgment action when implementing, nor does it mean that there are other limitations.

[0210] It should be understood that, in the embodiments of the present application, “at the same time” does not necessarily require strict simultaneity, sameness, second and even the same time. When there is a slight difference in the time of occurrence, it can also be understood as “at the same time”.

[0211] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: it can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement for part of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the protection scope of the technical solutions of the embodiments of the present application.

Claims

1. An information acquisition method characterized by comprising: The method is applied to an analysis system for analyzing a plurality of operation units for implementing a first instruction set compiled from a computer program for implementing an operator, the first instruction set comprising a plurality of instructions having a first execution order, each instruction being executed by one of the plurality of operation units according to the first execution order, the method comprising: The analysis system monitors whether each operation unit of the plurality of operation units executes an instruction; The analysis system outputs a period of time when each operation unit is in an idle state and a period of time when each operation unit is in a non-idle state according to whether each operation unit executes an instruction, wherein the idle state indicates that no instruction is executed, and the non-idle state indicates that an instruction is executed.

2. The method of claim 1, wherein, The method further comprises: The analysis system obtains a start time and an end time of a first period of time, wherein the first period of time is a period of time when a first operation unit is in the idle state, and the first operation unit belongs to the plurality of operation units; The analysis system outputs positions of instructions corresponding to the start time and the end time in a second instruction set, wherein the second instruction set is compiled from the computer program for implementing the operator, and the first instruction set is a subset of the second instruction set.

3. The method of claim 2, wherein, A first instruction is the instruction corresponding to the start time or the instruction corresponding to the end time, and the position of the first instruction in the second instruction set is indicated by the computer program corresponding to the first instruction or by the position of the computer program corresponding to the first instruction in the computer program for implementing the operator.

4. The method according to claim 2 or 3, characterized in that, The method further comprises: The analysis system outputs a period of time when a second operation unit is in the idle state and a period of time when the second operation unit is in the non-idle state within the first period of time, wherein the second operation unit belongs to the plurality of operation units, and the second operation unit is used to execute a second instruction between the instruction corresponding to the start time and the instruction corresponding to the end time according to the first execution order.

5. The method according to any of claims 2-4, characterized by, The instructions executed by the first operation unit are all computing instructions.

6. The method according to any one of claims 1 to 5, characterized in that, The plurality of operation units belong to the same processor.

7. The method according to any of claims 1 to 6, characterized in that The plurality of operation units are used to implement a third instruction set, and the third instruction set and the first instruction set are obtained by compiling different computer programs for implementing the same operator, and the method further comprises: The analysis system monitors whether each operation unit executes an instruction in the process of implementing the third instruction set; The analysis system outputs a period of time when each operation unit is in the idle state and a period of time when each operation unit is in the non-idle state in the process of implementing the third instruction set according to whether each operation unit executes an instruction in the process of implementing the third instruction set, and outputs a period of time when each operation unit is in the idle state and a period of time when each operation unit is in the non-idle state in the process of implementing the first instruction set.

8. An analytical system, characterized by The analysis system is used for analyzing a plurality of operation units, the plurality of operation units are used for implementing a first instruction set, the first instruction set is compiled from a computer program used for implementing an operator, the first instruction set comprises a plurality of instructions, the plurality of instructions have a first execution order, each instruction is executed by one of the plurality of operation units according to the first execution order, the analysis system comprises an acquisition unit and an output unit, The acquisition unit is used for monitoring whether each operation unit of the plurality of operation units executes an instruction; The output unit is used for outputting a period in which each operation unit is in an idle state and a period in which each operation unit is in a non-idle state according to whether each operation unit executes an instruction, wherein the idle state is used for indicating that no instruction is executed, and the non-idle state is used for indicating that an instruction is executed.

9. The system of claim 8, wherein, The analysis system comprises a determination unit, The determination unit is used for acquiring a start time and an end time of a first period, wherein the first period is a period in which a first operation unit is in the idle state, and the first operation unit belongs to the plurality of operation units; The output unit is further used for outputting positions of instructions corresponding to the start time and the end time in a second instruction set, wherein the second instruction set is compiled from the computer program used for implementing the operator, and the first instruction set is a subset of the second instruction set.

10. The system of claim 9, wherein, A first instruction is the instruction corresponding to the start time or the instruction corresponding to the end time, and the position of the first instruction in the second instruction set is indicated by the computer program corresponding to the first instruction or by the position of the computer program corresponding to the first instruction in the computer program used for implementing the operator.

11. The system of claim 9 or 10, wherein, The output unit is further used for outputting a period in which a second operation unit is in the idle state and a period in which the second operation unit is in the non-idle state in the first period, wherein the second operation unit belongs to the plurality of operation units, and the second operation unit is used for executing a second instruction, and the second instruction is an instruction between the instruction corresponding to the start time and the instruction corresponding to the end time according to the first execution order.

12. The system of any of claims 9-11, wherein, The instructions executed by the first operation unit are all computing instructions.

13. The system of any of claims 8-12, wherein, The plurality of operation units belong to a same processor.

14. The system of any of claims 8-13, wherein, The plurality of operation units are used for implementing a third instruction set, and the third instruction set and the first instruction set are obtained by compiling different computer programs used for implementing a same operator, The acquisition unit is further used for monitoring whether each operation unit executes an instruction in a process of implementing the third instruction set; The output unit is further used for outputting a period in which each operation unit is in the idle state and a period in which each operation unit is in the non-idle state in the process of implementing the third instruction set according to whether each operation unit executes an instruction in the process of implementing the third instruction set, and outputting a period in which each operation unit is in the idle state and a period in which each operation unit is in the non-idle state in the process of implementing the first instruction set.

15. A cluster of analysis devices, characterized in that comprising at least one analysis device, each analysis device comprising a processor and a memory; the processor of the at least one analysis device is configured to execute instructions stored in the memory of the at least one analysis device to cause the cluster of analysis devices to perform the method of any one of claims 1 to 7.

16. A computer program product comprising instructions, characterized in that, the instructions, when executed by an analysis device, cause the analysis device to perform the method of any one of claims 1 to 7.

17. A computer-readable storage medium, characterized in that, computer program instructions, which, when executed by an analysis device, cause the analysis device to perform the method of any one of claims 1 to 7.

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