Computing unit and processor

Abstract

The present invention provides a computing unit and a processor. The computing unit comprises: a Josephson junction and a chiplet, wherein the chiplet comprises a carrier, a deep trench capacitor and a filling dielectric layer, the deep trench capacitor being embedded in the carrier, the filling dielectric layer covering the carrier and the deep trench capacitor, and the deep trench capacitor being electrically connected to the Josephson junction. According to the computing unit and the processor provided in embodiments of the present application, the plane size of the computing unit can be reduced, and the integration density of the processor can be improved.

Description

A computing unit and a processor TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, in particular to a computing unit and a processor. BACKGROUND

[0002] In the field of superconducting quantum computing, superconducting qubits and corresponding on-chip control elements usually have a large physical size, which poses a great challenge to the large-scale integration of quantum processors.

[0003] In a superconducting qubit, a bypass capacitor is usually added to suppress noise caused by charge fluctuations, thereby helping to greatly extend the decoherence time of the qubit. In the widely used Transmon / Xmon structure design, the bypass capacitor in the qubit is generally a coplanar capacitor, i.e., the two plates of the capacitor are in the same plane. The coplanar capacitor requires a large planar area, which is not conducive to the integration of superconducting qubits. SUMMARY

[0004] To solve the problems in the prior art, the embodiments of the present application provide a computing unit and a processor, which can at least partially solve the problems in the prior art.

[0005] In one aspect, the embodiments of the present application provide a computing unit, which comprises a superconducting qubit, the superconducting qubit comprising a Josephson junction and a core particle, wherein:

[0006] The core particle comprises a carrier sheet, a deep trench capacitor and a filling dielectric layer, the deep trench capacitor being embedded in the carrier sheet, the filling dielectric layer covering the carrier sheet and the deep trench capacitor, and the deep trench capacitor being electrically connected to the Josephson junction.

[0007] Further, the superconducting qubit provided by the embodiments of the present application further comprises an adapter plate, the Josephson junction being arranged on the adapter plate, the adapter plate being bonded to the filling dielectric layer, a first plate of the Josephson junction being electrically connected to a first conductive layer of the deep trench capacitor through a first bump and a first conductive part, and a second plate of the Josephson junction being electrically connected to a second conductive layer of the deep trench capacitor through a second bump and a second conductive part; the first conductive part is arranged in the filling dielectric layer and connects the first bump and the first conductive layer; and the second conductive part is arranged in the filling dielectric layer and connects the second bump and the second conductive layer.

[0008] Further, the superconducting quantum bit provided by the embodiment of the present application further comprises a transition plate, the core particles are multiple, the filling medium layer of each core particle is bonded on the transition plate, the deep trench capacitor of each core particle corresponds to at least one Josephson junction, and each Josephson junction is arranged on the transition plate.

[0009] Further, the Josephson junction is arranged on the filling medium layer, the first pole plate of the Josephson junction is electrically connected with the first conductive layer of the deep trench capacitor through a third conductive part, the second pole plate of the Josephson junction is electrically connected with the second conductive layer of the deep trench capacitor through a fourth conductive part, and the third conductive part and the fourth conductive part are arranged in the filling medium layer respectively.

[0010] Further, the Josephson junction is arranged on the filling medium layer, the first pole plate of the Josephson junction is electrically connected with the second conductive layer of the deep trench capacitor through a fifth conductive part, the second pole plate of the Josephson junction is electrically connected with the first conductive layer of the deep trench capacitor through a sixth conductive part, the fifth conductive part and the sixth conductive part are arranged in the filling medium layer, and the deep trench capacitor is located below the second pole plate.

[0011] Further, the deep trench capacitor corresponds to multiple Josephson junctions.

[0012] Further, the core particle comprises multiple deep trench capacitors, and each deep trench capacitor corresponds to at least one Josephson junction.

[0013] Further, there are deep trench capacitors with different structures in the multiple deep trench capacitors.

[0014] Further, the deep trench capacitor comprises 2n conductive layers, and the deep trench capacitor corresponds to n Josephson junctions.

[0015] Further, the Josephson junctions are multiple, and each Josephson junction is communicatively connected with another Josephson junction through a corresponding coupling structure.

[0016] In another aspect, the embodiment of the present application provides a processor, which comprises a superconducting quantum chip, the superconducting quantum chip comprises the superconducting quantum bit, the packaging substrate and the PCB plate of any one of the above-mentioned embodiments, and wherein:

[0017] The superconducting quantum bit is arranged on the packaging substrate through a spacing column, a resonant cavity is arranged on the side surface of the packaging substrate close to the superconducting quantum bit, and the resonant cavity corresponds to one Josephson junction;

[0018] The PCB plate is arranged at the bottom of the packaging substrate.

[0019] The Josephson junction of the superconducting quantum bit receives a control signal through a first data transmission link and outputs data through a second data transmission link, and the second data transmission link passes through a resonant cavity corresponding to the Josephson junction of the superconducting quantum bit.

[0020] Further, the superconducting quantum bit has a plurality.

[0021] Further, there are superconducting quantum bits with different structures in the plurality of superconducting quantum bits.

[0022] Further, the first data transmission link includes a first transmission line, a first superconducting conductive part, a first superconducting coaxial bump, a second superconducting conductive part, a second transmission line and a control coaxial line connected in sequence; the first transmission line is coupled to a first plate of the Josephson junction, the control coaxial line is arranged on the PCB board, the second superconducting conductive part penetrates the packaging substrate, and the first superconducting conductive part penetrates the adapter plate or penetrates the carrier sheet and the filling medium layer.

[0023] Further, the second data transmission link includes a third transmission line, a third superconducting conductive part, a fourth superconducting conductive part, a fourth transmission line and a reading coaxial line, wherein:

[0024] The first end of the third transmission line is coupled to the second plate of the Josephson junction, the second end of the third transmission line is connected to the first end of the third superconducting conductive part, the second end of the third superconducting conductive part is coupled to the resonant cavity corresponding to the Josephson junction, the resonant cavity corresponding to the Josephson junction is coupled to the first end of the fourth superconducting conductive part, the second end of the fourth superconducting conductive part is connected to the first end of the fourth transmission line, and the second end of the fourth transmission line is connected to the reading coaxial line.

[0025] The reading coaxial line is arranged on the PCB board, the fourth superconducting conductive part penetrates the packaging substrate, and the third superconducting conductive part penetrates the adapter plate or penetrates the carrier sheet and the medium layer.

[0026] Further, the resonant cavity adopts a coplanar spiral line structure.

[0027] The superconducting quantum bit and the superconducting quantum chip provided by the embodiments of the present application include a Josephson junction and a core particle, the core particle includes a carrier sheet, a deep trench capacitor and a medium layer, the deep trench capacitor is embedded in the carrier sheet, the filling medium layer covers the carrier sheet and the deep trench capacitor, and the deep trench capacitor is electrically connected with the Josephson junction. By taking the deep trench capacitor as a bypass capacitor, the planar size of the superconducting quantum bit can be reduced, and the integration degree of the superconducting quantum bit can be improved. BRIEF DESCRIPTION OF DRAWINGS

[0028] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the accompanying drawings needed to be used in the embodiments or prior art description will be briefly introduced as follows. Obviously, the accompanying drawings in the following description only only some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained without creative labor based on these drawings.

[0029] Fig. 1 is a schematic diagram of a cross-sectional structure of a superconducting quantum bit according to a first embodiment of the present application.

[0030] Fig. 2 is a schematic diagram of a cross-sectional structure of a superconducting quantum bit according to a second embodiment of the present application.

[0031] Fig. 3 is a schematic diagram of a cross-sectional structure of a superconducting quantum bit according to a third embodiment of the present application.

[0032] Fig. 4 is a schematic diagram of a cross-sectional structure of a superconducting quantum bit according to a fourth embodiment of the present application.

[0033] Fig. 5 is a schematic diagram of a cross-sectional structure of a superconducting quantum bit according to a fifth embodiment of the present application.

[0034] Fig. 6A is a schematic diagram of a top view structure of a superconducting quantum bit according to a sixth embodiment of the present application.

[0035] Fig. 6B is a schematic diagram of a cross-sectional structure of a superconducting quantum bit according to the sixth embodiment of the present application.

[0036] Fig. 6C is a schematic diagram of another cross-sectional structure of a superconducting quantum bit according to the sixth embodiment of the present application.

[0037] Fig. 7 is a schematic diagram of a cross-sectional structure of a superconducting quantum bit according to a seventh embodiment of the present application.

[0038] Fig. 8 is a schematic diagram of a cross-sectional structure of a superconducting quantum chip according to an eighth embodiment of the present application.

[0039] Fig. 9 is a schematic diagram of a cross-sectional structure of a superconducting quantum chip according to a ninth embodiment of the present application.

[0040] Fig. 10 is a flowchart of a preparation method of a computing unit according to a tenth embodiment of the present application.

[0041] Fig. 11 is a flowchart of a preparation method of a deep trench capacitor according to an eleventh embodiment of the present application.

[0042] Fig. 12 is a flowchart of a preparation method of a Josephson junction according to a twelfth embodiment of the present application.

[0043] Fig. 13 is a flowchart of a preparation method of a deep trench capacitor according to a thirteenth embodiment of the present application.

[0044] Figure 14A is a schematic diagram of the structure of a processor according to a fourteenth embodiment of the application.

[0045] Figure 14B is a schematic diagram of a partial enlarged structure of the processor according to the fourteenth embodiment of the application.

[0046] Figure 15 is a schematic diagram of the structure of a processor according to a fifteenth embodiment of the application.

[0047] Figure 16A is a schematic diagram of the structure of a processor according to a sixteenth embodiment of the application.

[0048] Figure 16B is a schematic diagram of a partial enlarged structure of the processor according to the sixteenth embodiment of the application.

[0049] Figure 17A is a schematic diagram of the structure after blind via formation according to a seventeenth embodiment of the application.

[0050] Figure 17B is a schematic diagram of the structure after insulating layer deposition according to the seventeenth embodiment of the application.

[0051] Figure 17C is a schematic diagram of the structure after first electrode plate layer formation according to the seventeenth embodiment of the application.

[0052] Figure 17D is a schematic diagram of the structure after first electrode plate layer patterning according to the seventeenth embodiment of the application.

[0053] Figure 17E is a schematic diagram of the structure after double layer glue coating according to the seventeenth embodiment of the application.

[0054] Figure 17F is a schematic diagram of the structure after double layer glue forming double opening structure according to the seventeenth embodiment of the application.

[0055] Figure 17G is a schematic diagram of the structure after first metallization layer formation according to the seventeenth embodiment of the application.

[0056] Figure 17H is a schematic diagram of the structure after in-situ oxidation according to the seventeenth embodiment of the application.

[0057] Figure 17I is a schematic diagram of the structure after second metallization layer formation according to the seventeenth embodiment of the application.

[0058] Figure 17J is a schematic diagram of the structure after double layer glue removal according to the seventeenth embodiment of the application.

[0059] Figure 17K is a schematic diagram of the structure after second electrode plate layer formation according to the seventeenth embodiment of the application.

[0060] Figure 17L is a schematic diagram of the structure after medium filling according to the seventeenth embodiment of the application.

[0061] FIG. 17M is a schematic view of a structure after photoetching according to the seventeenth embodiment of the present application.

[0062] FIG. 17N is a schematic view of a structure after growing a computing unit pad according to the seventeenth embodiment of the present application.

[0063] FIG. 17O is a schematic view of a structure after removing photoresist according to the seventeenth embodiment of the present application. DETAILED DESCRIPTION

[0064] To make the objects, technical solutions, and advantages of the embodiments of the present application clearer, the embodiments of the present application are described in further detail below with reference to the drawings. Here, the schematic embodiments of the present application and the descriptions thereof are used to explain the present application but are not used as limitations of the present application. It should be noted that the embodiments in the present application and the features in the embodiments can be combined with each other in any manner without conflict. The acquisition, storage, use, processing, etc. of data in the technical solutions in the present application all comply with relevant provisions of laws and regulations. The user information in the embodiments of the present application is obtained through a legal and compliant manner, and the acquisition, storage, use, processing, etc. of the user information is authorized and agreed by the client.

[0065] To facilitate understanding of the technical solutions provided by the present application, the related content of the technical solutions of the present application is described first below.

[0066] In a typical superconducting quantum bit structure, a superconducting resonant cavity is composed of a meandering part of a coplanar waveguide transmission line. In order to realize readout multiplexing, multiple resonant cavities are coupled to a shared feed line, one end of each resonant cavity is close to the shared feed line, and the other end is close to the readout end of the quantum bit. In the case of weak external coupling and high internal quality factor, the frequency of the resonant cavity is determined by the inductance, capacitance per unit length, and total length of the resonant cavity. Although it is very simple to use a coplanar waveguide resonant cavity from the perspective of design and manufacturing, these resonant cavities occupy a large area from the perspective of space utilization.

[0067] In the currently widely used Transmon / Xmon structure design, the bypass capacitance in the quantum bit is generally a coplanar capacitance, that is, the two plates of the capacitor are in the same plane. In this case, the distribution of the electric field is uneven, and the planar area occupancy is too large, which limits the integration density of the quantum bit to some extent. In the prior art, a parallel-plate capacitor with a real space gap is also used as a bypass capacitance for a quantum bit. Although this technology initially transforms the capacitor into a vertical structure, the planar size of the parallel-plate capacitor is still too large, and the size advantage is limited.

[0068] Therefore, the application proposes a new three-dimensional quantum bit, a three-dimensional resonant cavity and a core granulation structure based on advanced packaging technology. The deep trench capacitor (DTC) is used to replace the capacitor structure in the planar design, thereby realizing the three-dimensionalization and core granulation transformation of the superconducting quantum bit. The area limitation in the planar design is broken, and a new three-dimensional quantum bit architecture is proposed, which makes the superconducting quantum bit itself more compatible with the demand of core granulation integration. It is also conducive to realizing the scalability and large-scale superconducting quantum chip based on the core granulation design methodology.

[0069] Taking the commonly used Transmon quantum bit as an example, the shunt capacitor with a high quality factor is generally realized by a large-size coplanar capacitor, and the superconducting microwave resonant cavity for quantum bit state reading out is composed of a millimeter-level coplanar waveguide, both of which occupy a large planar area. The DTC in the present application has a high aspect ratio vertical structure and can be used to construct a large self-capacitor, so it can replace the coplanar capacitor required by the quantum bit, and it is more conducive to the vertical interconnection structure of the FC, TSV, etc. as the vertical coupling node for the three-dimensional transformation of the quantum bit and the resonant cavity. Under the guidance of this idea, the planar size of the superconducting quantum bit is expected to be reduced by tens of times. When the DTC diameter is very small and reaches the order of hundreds of nanometers, the integrated density will be limited by the Josephson junction itself rather than the bypass capacitor. The pitch between quantum bits can be further reduced, which helps to realize a larger integrated scale of quantum processors.

[0070] Further, the new superconducting quantum bit based on the DTC proposed in the embodiments of the application can provide a very high capacitance value at a very small planar size, greatly improving the design efficiency.

[0071] FIG. 1 is a schematic diagram of the cross-sectional structure of the superconducting quantum bit provided by the first embodiment of the application. As shown in FIG. 1, the superconducting quantum bit provided by the embodiments of the application includes a Josephson junction 1 and a core granule 2, wherein:

[0072] The core granule 2 includes a carrier sheet 2-1, a deep trench capacitor 2-2 and a filling dielectric layer 2-3. The deep trench capacitor 2-2 is embedded in the carrier sheet 2-1, and the filling dielectric layer 2-3 covers the carrier sheet 2-1 and the deep trench capacitor 2-2. The deep trench capacitor 2-2 is electrically connected with the Josephson junction 1.

[0073] Specifically, the Josephson junction 1 can be selected for preparation of Al-based, Nb-based, Ta-based, etc. materials, and the Josephson junction 1 and other necessary functional auxiliary structures are used to construct various types of quantum bits. The constructed quantum bits can be flux, charge, phase, Transmon, etc. quantum bit types. The carrier sheet 2-1 can be selected from intrinsic silicon, epitaxially grown silicon, sapphire, silicon on insulator (SOI), quartz, germanium, silicon germanium, silicon carbide, indium phosphide, gallium arsenide, gallium nitride, crystalline quartz, sapphire, diamond, and one or more ceramics, etc. The deep trench capacitor 2-2 is a vertical capacitor structure with multiple parallel conductive layer-dielectric layer-conductive layer formed in a high aspect ratio blind hole, and the deep trench capacitor 2-2 is used as a bypass capacitor of a superconducting quantum bit, which can help to greatly extend the quantum bit decoherence time while reducing the occupied area, thereby reducing the planar size of the superconducting quantum bit. When the size of the deep trench capacitor 2-2 is very small to reach the order of hundreds of nanometers, the integrated density will be limited by the Josephson junction itself rather than the bypass capacitor. The deep trench capacitor 2-2 can provide very high capacitance at a smaller planar size, thereby saving silicon area.

[0074] The deep trench capacitor 2-2 is electrically connected with the Josephson junction 1. For example, as shown in FIG. 1, the first conductive layer 2-2-1 of the deep trench capacitor 2-2 is electrically connected with the first plate 1-1 of the Josephson junction 1, and the second conductive layer 2-2-2 of the deep trench capacitor 2-2 is electrically connected with the second plate 1-2 of the Josephson junction 1.

[0075] The superconducting quantum bit provided by the embodiment of the present application comprises a Josephson junction and a core particle, the core particle comprises a carrier sheet, a deep trench capacitor and a dielectric layer, the deep trench capacitor is embedded in the carrier sheet, the filling dielectric layer covers the carrier sheet and the deep trench capacitor, and the deep trench capacitor is electrically connected with the Josephson junction. By taking the deep trench capacitor as a bypass capacitor, the planar size of the superconducting quantum bit can be reduced, and the integration degree of the superconducting quantum bit can be improved.

[0076] Figure 2 is a schematic diagram of a cross-sectional structure of a superconducting quantum bit according to a second embodiment of the present application. As shown in Figure 2, the superconducting quantum bit according to the second embodiment of the present application further comprises an adapter plate 3, the Josephson junction 1 is disposed on the adapter plate 3, the adapter plate 3 is bonded to the filling medium layer 2-3, the first electrode plate 1-1 of the Josephson junction 1 is electrically connected to the first conductive layer 2-2-1 of the deep trench capacitor 2-2 through the first bump 4 and the first conductive part 5, and the second electrode plate 1-2 of the Josephson junction 1 is electrically connected to the second conductive layer 2-2-2 of the deep trench capacitor 2-2 through the second bump 6 and the second conductive part 7; the first conductive part 5 is disposed in the filling medium layer 2-3 and connects the first bump 4 and the first conductive layer 2-2-1; and the second conductive part 7 is disposed in the filling medium layer 2-3 and connects the second bump 6 and the second conductive layer 2-2-2.

[0077] Specifically, the adapter plate 3 can be made of intrinsic silicon, epitaxially grown silicon, sapphire, silicon-on-insulator (SOI), quartz, germanium, silicon germanium, silicon carbide, indium phosphide, gallium arsenide, gallium nitride, crystalline quartz, sapphire, diamond, etc. The Josephson junction 1 is disposed on the adapter plate 3. The adapter plate 3 is bonded to the filling medium layer 2-3, so that the core particle 2 can be flip-chip bonded to the adapter plate 3. The adapter plate 3 can be bonded to the filling medium layer 2-3 through the first bump 4 and the second bump 6.

[0078] The Josephson junction 1 comprises the first electrode plate 1-1 and the second electrode plate 1-2. The deep trench capacitor 2-2 comprises the first conductive layer 2-2-1 and the second conductive layer 2-2-2. The first electrode plate 1-1 is connected to the first bump 4, the first bump 4 is connected to the first conductive part 5, and the first conductive part 5 is connected to the first conductive layer 2-2-1. The second electrode plate 1-2 is connected to the second bump 6, the second bump 6 is connected to the second conductive part 7, and the second conductive part 7 is connected to the second conductive layer 2-2-2. The first conductive part 5 can be obtained by punching a hole in the filling medium layer 2-3 and filling a conductive material, and the conductive material includes but is not limited to tungsten, copper, etc., which can be selected according to actual needs. The second conductive part 7 has a structure similar to that of the first conductive part 5, which will not be described here.

[0079] For example, as shown in FIG. 2, the wafer 2-1 is provided with two "W" type grooves containing the deep trench capacitors 2-2, and each "W" type groove contains one deep trench capacitor 2-2. The deep trench capacitor 2-2 includes a first dielectric layer 2-2-4, a first conductive layer 2-2-1 and a second dielectric layer 2-2-3 and a second conductive layer 2-2-2 stacked in sequence along the "W" type groove, the first dielectric layer 2-2-4 separates the wafer 2-1 and the first conductive layer 2-2-1, and the second dielectric layer 2-2-3 is located between the second conductive layer 2-2-2 and the first conductive layer 2-2-1. A filling dielectric layer 2-3 can be deposited on the wafer 2-1 and the deep trench capacitors 2-2, so that the filling dielectric layer 2-3 covers the wafer 2-1 and the deep trench capacitors 2-2.

[0080] FIG. 3 is a schematic diagram of a cross-sectional structure of a superconducting quantum bit according to a third embodiment of the present application. As shown in FIG. 3, on the basis of the above embodiments, the superconducting quantum bit further includes a switch plate 3, and the plurality of core particles 2, the filling dielectric layer 2-3 of each core particle 2 is bonded to the switch plate 3, and the deep trench capacitor 2-2 of each core particle 2 corresponds to at least one Josephson junction 1, and each Josephson junction 1 is arranged on the switch plate 3.

[0081] Specifically, the switch plate 3 can carry a plurality of core particles 2, and the filling dielectric layer 2-3 of each core particle 2 is bonded to the switch plate 3. The filling dielectric layer 2-3 can be bonded to the switch plate 3 through the corresponding first bump 4 and second bump 6. The deep trench capacitor 2-2 of each core particle 2 corresponds to at least one Josephson junction 1, and the first conductive layer 2-2-1 of the deep trench capacitor 2-2 can be electrically connected to the first plate 1-1 of the Josephson junction 1 through the corresponding first conductive part 5 and first bump 4; and the second conductive layer 2-2-2 of the deep trench capacitor 2-2 can be electrically connected to the second plate 1-2 of the Josephson junction 1 through the corresponding second conductive part 7 and second bump 6. The specific number of core particles 2 is set according to actual needs, and the present application does not make any limitation.

[0082] When the deep trench capacitor 2-2 corresponds to n Josephson junctions 1, the deep trench capacitor 2-2 can include 2n conductive layers, and each two conductive layers correspond to one Josephson junction. n is a natural number.

[0083] Figure 4 is a schematic diagram of a cross-sectional structure of a superconducting quantum bit according to a fourth embodiment of the present application. As shown in Figure 4, on the basis of the above embodiments, further, the Josephson junction 1 is arranged on the filling medium layer 2-3, the first electrode plate 1-1 of the Josephson junction 1 is electrically connected with the first conductive layer 2-2-1 of the deep trench capacitor 2-2 through the third conductive part 8, and the second electrode plate 1-2 of the Josephson junction 1 is electrically connected with the second conductive layer 2-2-2 of the deep trench capacitor 2-2 through the fourth conductive part 9; the third conductive part 8 is arranged in the filling medium layer 2-3, and the fourth conductive part 9 is arranged in the filling medium layer 2-3.

[0084] Specifically, in order to reduce the size of the superconducting quantum bit, the Josephson junction 1 can be arranged on the filling medium layer 2-3. The Josephson junction 1 includes the first electrode plate 1-1 and the second electrode plate 1-2. The deep trench capacitor 2-2 includes the first conductive layer 2-2-1 and the second conductive layer 2-2-2. The third conductive part 8 connects the first electrode plate 1-1 and the first conductive layer 2-2-1, and the fourth conductive part 9 connects the second conductive layer 2-2-2 and the second electrode plate 1-2. The third conductive part 8 can be obtained by etching a hole on the filling medium layer 2-3 and filling a conductive material, and the conductive material includes but is not limited to tungsten, copper, etc., which can be selected according to actual needs. The fourth conductive part 9 has a similar structure to the third conductive part 8, which will not be described here.

[0085] Figure 5 is a schematic diagram of a cross-sectional structure of a superconducting quantum bit according to a fifth embodiment of the present application. As shown in Figure 5, on the basis of the above embodiments, further, the Josephson junction 1 is arranged on the filling medium layer 2-3, the first electrode plate 1-1 of the Josephson junction 1 is electrically connected with the first conductive layer 2-2-1 of the deep trench capacitor 2-2 through the fifth conductive part 10, and the second electrode plate 1-2 of the Josephson junction 1 is electrically connected with the second conductive layer 2-2-2 of the deep trench capacitor 2-2 through the sixth conductive part 11; the fifth conductive part 10 is arranged in the filling medium layer 2-3, and the sixth conductive part 11 is arranged in the filling medium layer 2-3; and the deep trench capacitor 2-2 is located below the second electrode plate 1-2.

[0086] Specifically, in order to further reduce the size of the superconducting quantum bit, while the Josephson junction 1 is arranged on the filling medium layer 2-3, the deep trench capacitor 2-2 is arranged below the second plate 1-2 of the Josephson junction 1. The Josephson junction 1 includes a first plate 1-1 and a second plate 1-2. The deep trench capacitor 2-2 includes a first conductive layer 2-2-1 and a second conductive layer 2-2-2. The fifth conductive part 10 connects the first plate 1-1 and the first conductive layer 2-2-1, and the sixth conductive part 11 connects the second conductive layer 2-2-2 and the second plate 1-2. Among them, the sixth conductive part 11 can be obtained by punching on the filling medium layer 2-3 and filling the conductive material, and the conductive material includes but is not limited to tungsten, copper and the like, which is selected according to actual needs. The fifth conductive part 10 can be realized gradually through multi-step photoetching and multi-step medium deposition process.

[0087] For example, as shown in FIG. 5, two grooves containing the deep trench capacitor 2-2 are arranged in the slide 2-1, and each groove contains one deep trench capacitor 2-2. The deep trench capacitor 2-2 includes a first medium layer 2-2-4, a second conductive layer 2-2-2, a first conductive layer 2-2-1 and a second medium layer 2-2-3 stacked in sequence along one groove, the first medium layer 2-2-4 separates the slide 2-1 and the first conductive layer 2-2-1, and the second medium layer 2-2-3 is located between the second conductive layer 2-2-2 and the first conductive layer 2-2-1. The filling medium layer 2-3 can be deposited on the slide 2-1 and the deep trench capacitor 2-2, so that the filling medium layer 2-3 covers the slide 2-1 and the deep trench capacitor 2-2.

[0088] FIG. 6A is a top view of a superconducting quantum bit according to a sixth embodiment of the present application, FIG. 6B is a cross-sectional view of the superconducting quantum bit according to the sixth embodiment of the present application, and FIG. 6C is another cross-sectional view of the superconducting quantum bit according to the sixth embodiment of the present application. FIG. 6B is a cross-sectional view of A-A in FIG. 6A, and FIG. 6C is a cross-sectional view of B-B in FIG. 6A. As shown in FIGS. 6A, 6B and 6C, on the basis of the above-mentioned embodiments, further, the deep trench capacitor 602-2 corresponds to a plurality of Josephson junctions. The deep trench capacitor 602-2 is electrically connected to each Josephson junction.

[0089] For example, as shown in FIGS. 6A, 6B and 6C, the superconducting quantum bit includes two Josephson junctions and a core particle 602, the core particle 602 includes a slide 602-1, a deep trench capacitor 602-2 and a filling medium layer 602-3, the deep trench capacitor 602-2 is embedded in the slide 602-1, and the filling medium layer 602-3 covers the slide 602-1 and the deep trench capacitor 602-2. The deep trench capacitor 602-2 corresponds to two Josephson junctions 601-1 and 601-2, and the Josephson junctions 601-1 and 601-2 are electrically connected through the coupling structure 12.

[0090] The deep trench capacitor 602-2 includes a first conductive layer 602-2-1, a second conductive layer 602-2-2, a third conductive layer 602-2-3, and a fourth conductive layer 602-2-4, and a dielectric layer is arranged between the connected conductive layers. The Josephson junction 601-1 includes a first plate 601-1-1 and a second plate 601-1-2. The Josephson junction 601-2 includes a first plate 601-2-1 and a second plate 601-2-2. The seventh conductive part 603 connects the first plate 601-1-1 and the third conductive layer 602-2-3, and the eighth conductive part 604 connects the fourth conductive layer 602-2-4 and the second plate 601-1-2. The ninth conductive part 605 connects the first plate 601-2-1 and the second conductive layer 602-2-2, and the tenth conductive part 606 connects the first conductive layer 602-2-1 and the second plate 601-2-2.

[0091] The seventh conductive part 603, the eighth conductive part 604, the ninth conductive part 605, and the tenth conductive part 606 are all arranged in the filling dielectric layer 602-3. The seventh conductive part 603 can be obtained by punching a hole in the filling dielectric layer 602-3 and filling a conductive material. The eighth conductive part 604, the ninth conductive part 605, and the tenth conductive part 606 are similar in structure to the seventh conductive part 603, and will not be described here.

[0092] As shown in FIG. 1, the core particle 2 includes a plurality of deep trench capacitors 2-2, and each deep trench capacitor 2-2 corresponds to at least one Josephson junction 1. The number of deep trench capacitors 2-2 and the number of Josephson junctions 1 are set according to actual needs, and embodiments of the present application are not limited.

[0093] FIG. 7 is a schematic diagram of the cross-sectional structure of a superconducting quantum bit according to a seventh embodiment of the present application. As shown in FIG. 7, on the basis of the above-mentioned embodiments, further, there are deep trench capacitors with different structures in the plurality of deep trench capacitors 2-2.

[0094] The difference in the structure of the deep trench capacitor 2-2 can be the difference in the number of corresponding trenches, or the difference in the number of included conductive layers, which is set according to actual needs, and embodiments of the present application are not limited.

[0095] For example, as shown in FIG. 7, one deep trench capacitor 2-2 corresponds to one trench, and another deep trench capacitor 2-2 corresponds to two trenches.

[0096] As shown in FIG. 2 and FIG. 4, there are multiple Josephson junctions 1, and each Josephson junction 1 is connected in communication through a corresponding coupling structure 12. The coupling structure 12 includes but is not limited to a capacitive coupling structure, a resonant cavity coupling structure, etc., which is selected according to actual needs, and the embodiments of the present application are not limited. The specific position of the coupling structure 12 is set according to actual needs, and the embodiments of the present application are not limited.

[0097] For example, as shown in FIG. 4, the coupling structure 12 is bonded on two Josephson junctions 1 through corresponding electrical bumps.

[0098] For example, as shown in FIG. 2, the coupling structure 12 is prepared on the side surface of the filling medium layer 2-3 facing the Josephson junction 1, and can connect the corresponding first bump 4 of one Josephson junction 1 and the corresponding second bump 6 of another Josephson junction 1.

[0099] FIG. 8 is a schematic diagram of the cross-sectional structure of a superconducting quantum chip according to an eighth embodiment of the present application, and FIG. 9 is a schematic diagram of the cross-sectional structure of a superconducting quantum chip according to a ninth embodiment of the present application. As shown in FIG. 8 and FIG. 9, the superconducting quantum chip provided by the embodiments of the present application includes the superconducting quantum bit 801, the packaging substrate 802 and the PCB board 803 described in any of the above embodiments, wherein:

[0100] The superconducting quantum bit 801 is arranged on the packaging substrate 802 through the spacer column 804; the resonant cavity 805 is arranged on the side surface of the packaging substrate 802 close to the superconducting quantum bit 801, and the resonant cavity 805 corresponds to the Josephson junction 801-1 one by one;

[0101] The PCB board 803 is arranged at the bottom of the packaging substrate 802;

[0102] The Josephson junction 801-1 of the superconducting quantum bit 801 receives a control signal through the first data transmission link 806 and outputs data through the second data transmission link 807, and the second data transmission link 807 passes through the resonant cavity 805 corresponding to the Josephson junction 801-1 of the superconducting quantum bit 801.

[0103] Specifically, the superconducting quantum bit 801 includes the Josephson junction 801-1 and the core particle 801-2, and the core particle 801-2 includes the carrier sheet 801-2-1, the deep trench capacitor 801-2-2 and the filling medium layer 801-2-3. When the Josephson junction 801-1 is arranged on the filling medium layer 801-2-3, the filling medium layer 801-2-3 is arranged on the packaging substrate 802 through the spacer column 804, and the introduction of the spacer column 804 helps to accurately define the wafer spacing and improve the wafer uniformity.

[0104] The superconducting quantum bit 801 can further include a transition plate 801-3, the transition plate 801-3 is arranged on the packaging substrate 802 through a spacing column 804, and the Josephson junction 801-1 is arranged on the transition plate 801-3. The packaging substrate 802 can be made of intrinsic silicon, epitaxially grown silicon, sapphire, silicon-on-insulator, quartz, lithium niobate, or the like.

[0105] The packaging substrate 802 is provided with a resonant cavity 805 on one side surface close to the superconducting quantum bit 801, and the resonant cavity 805 corresponds to the Josephson junction 801-1 in one-to-one correspondence; the resonant cavity 805 is used to realize data reading of the Josephson junction 801-1.

[0106] The PCB board 803 is arranged at the bottom of the packaging substrate 802, and a coaxial line can be arranged between the PCB board 803 and the packaging substrate 802, which can transmit external control signals and finally provide the superconducting quantum bit 801, and can also output data from the superconducting quantum bit 801 to the outside.

[0107] The Josephson junction 801-1 of the superconducting quantum bit 801 can receive a control signal through a first data transmission link 806 and output data through a second data transmission link 807, and the second data transmission link 807 passes through the resonant cavity 805 corresponding to the Josephson junction 801-1 of the superconducting quantum bit 801. The specific structure of the first data transmission link 806 and the second data transmission link 807 is described below, and will not be described here.

[0108] The superconducting quantum chip provided by the embodiment of the application comprises a superconducting quantum bit, a packaging substrate, and a PCB board, the superconducting quantum bit is arranged on the packaging substrate through a spacing column; the packaging substrate is provided with a resonant cavity on one side surface close to the superconducting quantum bit, and the resonant cavity corresponds to a Josephson junction in one-to-one correspondence; the PCB board is arranged at the bottom of the packaging substrate; the Josephson junction of the superconducting quantum bit receives a control signal through a first data transmission link and outputs data through a second data transmission link, and the second data transmission link passes through the resonant cavity corresponding to the Josephson junction of the superconducting quantum bit, which can reduce the planar size of the superconducting quantum chip and improve the integration of the superconducting quantum chip.

[0109] On the basis of the above-mentioned embodiments, further, the superconducting quantum bit 801 has a plurality of superconducting quantum bits 801. Each superconducting quantum bit 801 is fixed on the packaging substrate 802 through a corresponding spacing column 804.

[0110] On the basis of the above-mentioned embodiments, further, there are superconducting quantum bits with different structures in the plurality of superconducting quantum bits 801.

[0111] For example, the plurality of superconducting qubits 801 exist superconducting qubits including a transmon and superconducting qubits not including a transmon. The plurality of superconducting qubits 801 exist qubit implementation ways including different physical structures such as a transmon, an Xmon, a charge, a flux, a phase, and the like.

[0112] For example, the plurality of superconducting qubits 801 exist superconducting qubits 801 with different deep trench capacitor structures.

[0113] As shown in FIGS. 8 and 9, the first data transmission link 806 includes a first transmission line 806-1, a first superconducting conductive part 806-2, a first superconducting coaxial bump 806-3, a second superconducting conductive part 806-4, a second transmission line 806-5, and a control coaxial line 806-6 connected in sequence; the first transmission line 806-1 is coupled to the first electrode plate 801-1-1 of the Josephson junction 801-1, the control coaxial line 806-6 is arranged on the PCB board 803, the second superconducting conductive part 806-4 penetrates the packaging substrate 802, and the first superconducting conductive part 806-2 penetrates the adapter board 801-3 or penetrates the carrier sheet 801-2-1 and the filling medium layer 801-2-3.

[0114] Specifically, the external control signal is transmitted to the first electrode plate 801-1-1 of the Josephson junction 801-1 in sequence through the control coaxial line 806-6, the second transmission line 806-5, the second superconducting conductive part 806-4, the first superconducting coaxial bump 806-3, the first superconducting conductive part 806-2, and the first transmission line 806-1. The first transmission line 806-1 is coupled to the first electrode plate 801-1-1 of the Josephson junction 801-1. The second superconducting conductive part 806-4 can be obtained by punching a hole on the packaging substrate 802 and filling superconducting metal. When the Josephson junction 1 is arranged on the adapter board 801-3, the first superconducting conductive part 806-2 can be obtained by punching a hole on the adapter board 801-3 and filling superconducting metal-dielectric layer-superconducting metal-dielectric layer through a superconducting coaxial TSV filling technology. When the Josephson junction 1 is arranged on the filling medium layer 801-2-3, the first superconducting conductive part 806-2 can be obtained by filling superconducting metal-dielectric layer-superconducting metal-dielectric layer in the through hole penetrating the carrier sheet 801-2-1 and the filling medium layer 801-2-3 through a superconducting coaxial TSV preparation technology. The superconducting metal includes but is not limited to aluminum, niobium, titanium nitride, and the like, which is selected according to actual needs, and the embodiments of the present application are not limited.

[0115] As shown in FIGS. 8 and 9, the second data transmission link 807 includes a third transmission line 807-1, a third superconducting conductive part 807-2, a fourth superconducting conductive part 807-3, a fourth transmission line 807-4, and a reading coaxial line 807-5, wherein:

[0116] The first end of the third transmission line 807-1 is coupled to the second plate 801-1-2 of the Josephson junction 801-1, the second end of the third transmission line 807-1 is connected to the first end of the third superconducting conductive part 807-2, the second end of the third superconducting conductive part 807-2 is coupled to the resonant cavity 805 corresponding to the Josephson junction 801-1, the resonant cavity 805 corresponding to the Josephson junction 801-1 is coupled to the first end of the fourth superconducting conductive part 807-3, the second end of the fourth superconducting conductive part 807-3 is connected to the first end of the fourth transmission line 807-4, and the second end of the fourth transmission line 807-4 is connected to the read coaxial line 807-5.

[0117] The read coaxial line 807-5 is arranged on the PCB board 803, the fourth superconducting conductive part 807-4 and the fourth transmission line 807-4 pass through the packaging substrate 802, and the third superconducting conductive part 807-2 passes through the adapter plate 801-3 or passes through the carrier 801-2-1 and the filling dielectric layer 801-2-3.

[0118] If the packaging substrate 802 is made of a semiconductor material such as silicon, a dielectric region needs to be arranged between the resonant cavity 805 corresponding to the Josephson junction 801-1 and the first end of the fourth superconducting conductive part 807-3 to achieve the coupling connection between the resonant cavity 805 and the first end of the fourth superconducting conductive part 807-3. The resonant cavity 805 and the first end of the fourth superconducting conductive part 807-3 can be capacitively coupled. The second end of the third superconducting conductive part 807-2 and the resonant cavity 805 can be capacitively coupled. When the Josephson junction 1 is arranged on the adapter plate 801-3, the third superconducting conductive part 807-2 can be obtained by punching a hole in the adapter plate 801-3 and filling superconducting metal-dielectric layer-superconducting metal-dielectric layer. When the Josephson junction 1 is arranged on the filling dielectric layer 801-2-3, the third superconducting conductive part 807-2 can be obtained by filling superconducting metal-dielectric layer-superconducting metal-dielectric layer in the through hole passing through the carrier 801-2-1 and the filling dielectric layer 801-2-3.

[0119] On the basis of the above-mentioned embodiments, further, the resonant cavity 805 adopts a coplanar spiral line structure.

[0120] Specifically, the coplanar resonant cavity based on the meander transmission line in the prior art can be modified to the resonant cavity 805 based on the coplanar spiral line, and the performance of the resonant cavity 805 is determined by the inner diameter, the outer diameter, and the spiral line distance p of the spiral. Compared with the coplanar resonant cavity based on the meander transmission line in the prior art, the resonant cavity 805 in the embodiments of the present application can significantly reduce the size of the resonant cavity, which is conducive to improving the integration of the superconducting quantum chip.

[0121] It should be noted that all the interconnections between the chips allow the use of solder bumps, stud bumps, etc., the adapter board can be silicon-based, glass-based, etc., and each conductive part can be made by through-silicon via technology (TSV), through-glass via technology (TGV), and molded via technology (TMV).

[0122] In the process of three-dimensional modification of the superconducting quantum bits, the three-dimensional structure based on the DTC is directly introduced into the core quantum component inside, which has a significant advantage in three-dimensional integration process compatibility and modular assembly, and is more helpful for the physical realization of the chiplet architecture. Through the screening of the known good chiplet (KGC), the high yield of the chiplets used in the system integration stage can be ensured, thereby solving the problem that the overall yield of the superconducting quantum bits and the superconducting quantum chip decreases rapidly with the increase of the integration scale.

[0123] The chiplet bonding and the chiplet-adapter board packaging body bonding steps can be completed integrally after placement by one bonding process, thereby shortening the process steps and reducing the adverse effects of repeated temperature rising and falling processes on the Josephson junction. The packaging substrate allows multiple adapter boards to be carried, and different types of quantum bit chiplets can be carried between different adapter boards, thereby greatly improving the large-scale scalability of the system under the premise of ensuring the yield, and helping to provide a more convenient test platform for the lateral comparison of the performance of different types of quantum bits.

[0124] The superconducting quantum bit and the superconducting quantum chip provided by the embodiment of the application have the following advantages:

[0125] (1) The physical size of the component is significantly reduced, and the integration density is significantly increased. The vertical structure with high aspect ratio can be used to construct a DTC structure with very small footprint and large capacitance, so that the large-size coplanar capacitor required by the quantum bit can be replaced, and the vertical interconnection structure such as the FC and the TSV can be used as the vertical coupling node after the three-dimensional modification of the quantum bit and the resonant cavity.

[0126] (2) For the new type of bit based on the DTC, the DTC can provide very high capacitance value under very small planar size, greatly improving the design efficiency and flexibility.

[0127] (3) The three-dimensional modification process directly introduces a three-dimensional interconnection structure into the core quantum component inside, which has a significant advantage in three-dimensional integration process compatibility and modular assembly, and is more helpful for the physical realization of the chiplet architecture.

[0128] (4) A complete multi-chiplet integration packaging architecture is designed, which takes into account the comprehensive needs of superconducting quantum chip cost control, decoherence suppression, and electrical signal transmission link.

[0129] (5)Through the screening of known good die, the high yield of the die used in the system integration stage can be ensured, thereby solving the problem that the overall yield of the superconducting quantum processor rapidly decreases as the integration scale increases.

[0130] (6)In the manufacture of superconducting quantum bits, the die bonding and the die-adapter plate package bonding steps can be completed integrally after placement through one bonding process, thereby shortening the process steps and reducing the adverse effects of repeated temperature rising and falling processes on Josephson junctions.

[0131] (7)The packaging substrate allows multiple adapter plates to be carried, and different types of quantum bit dies can be carried between different adapter plates, thereby greatly improving the large-scale scalability of the system under the premise of ensuring the yield, and facilitating the provision of a convenient test platform for the lateral comparison of the performance of different types of quantum bits.

[0132] Superconducting quantum bits are core components in quantum computing, and their size directly affects the integration of quantum processors.

[0133] In the structure of a superconducting quantum bit, a bypass capacitor is usually added to suppress noise caused by charge fluctuations, which helps to prolong the decoherence time of the quantum bit. In the currently widely used Transmon / Xmon bit structure design, the quantum bit generally uses a coplanar capacitor, i.e., both plates of the capacitor are on the same horizontal plane. In this case, the capacitor occupies a large planar area, which is not conducive to the large-scale expansion and high-density integration of superconducting quantum bits. Therefore, the present application proposes a new quantum bit preparation process, which significantly reduces the size of a single quantum bit by introducing a deep trench capacitor. By realizing a superconducting quantum bit structure with a parallel Josephson junction and deep trench capacitor (similar to a traditional Transmon quantum bit), a large parallel capacitor is added, which helps to reduce the sensitivity to charge noise, is easier to control, and has a longer lifespan. The deep trench capacitor can achieve a much higher capacitance density than the planar capacitor in the same area, so the noise suppression effect is more significant.

[0134] Three-dimensional integration technology is an important technology in the "post-Moore era" that can significantly improve the integration density and computing power of a single processor at the same process node. Therefore, the present application also proposes an adaptive three-dimensional integration technology to realize a scalable superconducting quantum processor architecture for the new quantum bit preparation process.

[0135] In the currently widely used Transmon / Xmon structure design, the bypass capacitor in the superconducting quantum bit is generally a coplanar capacitor, i.e., both plates of the capacitor are in the same plane. In this case, the planar area occupies too much space, which limits the integration density of the quantum bit to some extent. In terms of scale, the integration density of the current processor is mainly limited by the bypass capacitor and the resonant cavity, rather than the Josephson junction itself.

[0136] The application replaces the capacitor structure in the planar design with a deep trench capacitor structure, so that the superconducting quantum bit itself is more compatible with the demand of core granulation three-dimensional integration, reduces the size of the superconducting quantum bit, and is expected to realize an expandable, large-scale and high-integration-density superconducting quantum processor based on core granulation design.

[0137] The application provides a preparation method of a computing unit, which prepares a deep trench capacitor while preparing a Josephson junction, can simplify the preparation process flow of the whole computing unit, and avoids the interface deterioration problem caused by the thin film interface leaving the high vacuum cavity and being transported in the atmosphere.

[0138] In the currently widely used Transmon / Xmon structure design, the bypass capacitor in the superconducting quantum bit is generally a coplanar capacitor, that is, the two plates of the capacitor are in the same plane. In this case, the planar area occupies too much space, which limits the integration density of the quantum bit to some extent. From the scale, the integration density of the processor at the present stage is mainly limited by the bypass capacitor and the resonant cavity, rather than the Josephson junction itself.

[0139] The application replaces the capacitor structure in the planar design with a deep trench capacitor structure, so that the superconducting quantum bit itself is more compatible with the demand of core granulation three-dimensional integration, reduces the size of the superconducting quantum bit, and is expected to realize an expandable, large-scale and high-integration-density superconducting quantum processor based on core granulation design.

[0140] The application provides a preparation method of a computing unit, which prepares a deep trench capacitor while preparing a Josephson junction, can simplify the preparation process flow of the whole computing unit, and avoids the interface deterioration problem caused by the thin film interface leaving the high vacuum cavity and being transported in the atmosphere.

[0141] FIG. 10 is a flowchart of the preparation method of the computing unit provided by the tenth embodiment of the application. As shown in FIG. 10, the preparation method of the computing unit provided by the embodiment of the application comprises the following steps.

[0142] S1001, forming a blind hole in a wafer, and forming a first electrode plate layer of a deep trench capacitor based on the blind hole;

[0143] Specifically, a blind hole is prepared in the wafer, which extends from a first surface of the wafer to a second surface of the wafer. A conductive layer is prepared based on the blind hole to obtain a first electrode plate layer of a deep trench capacitor (DTC). The wafer material is not limited, but the material layer close to the quantum bit needs to have a low enough two-level system (TLS) loss to not affect the function of the quantum bit. The conductive material of the first electrode plate layer is selected according to actual needs, and the embodiments of the present application are not limited.

[0144] For example, the blind hole can be prepared on the first surface of the silicon-based wafer through photolithography and deep reactive ion etching (DRIE).

[0145] S1002, a first metallization layer of the Josephson junction is prepared, and the first metallization layer is electrically connected with the first electrode plate layer;

[0146] Specifically, a first metallization layer of the Josephson junction is prepared on the wafer, and the first metallization layer is electrically connected with the first electrode plate layer. The first metallization layer can be made of superconducting metal materials such as Al and Nb, and is selected according to actual needs, and the embodiments of the present application are not limited.

[0147] S1003, the first metallization layer and the first electrode plate layer are in-situ oxidized, a first dielectric layer is formed on the first metallization layer, and a second dielectric layer is formed on the first electrode plate layer;

[0148] Specifically, the first metallization layer and the first electrode plate layer are in-situ oxidized, so that an oxide layer is formed on the first metallization layer as a first dielectric layer and an oxide layer is formed on the first electrode plate layer as a second dielectric layer.

[0149] The first metallization layer and the first electrode plate layer are synchronously oxidized in a vacuum chamber, which not only simplifies the overall process steps, but also avoids the interface deterioration problem caused by the transport of the thin film interface in the atmosphere after leaving the high vacuum chamber, provides an as ideal as possible interface state, and helps to improve the coherence performance of the Josephson junction and the high capacitance ability of the deep trench capacitor.

[0150] S1004, a second metallization layer of the Josephson junction is prepared on the first dielectric layer;

[0151] Specifically, a second metallization layer of the Josephson junction is prepared on the first dielectric layer. The first dielectric layer serves as a barrier layer of the Josephson junction. The second metallization layer can be made of superconducting metal materials such as Al and Nb, which are selected according to actual needs, and the embodiments of the present application are not limited.

[0152] For example, after the first metallization layer is prepared and in-situ oxidation is performed, a superconducting metal material is grown through the double-layer resist of the double-opening structure at a second angle to form the second metallization layer. The second angle is selected so that the second metallization layer can be formed on the first dielectric layer. Because the double-layer resist is of a double-opening structure, in addition to the second metallization layer, an excess metallization layer is also formed on the surface of the wafer, but it does not substantially affect the structure of the deep trench capacitor and does not affect the electrical properties of the finally obtained computing unit, so that the excess metallization layer does not need to be additionally processed, thereby simplifying the complexity of the process. The second angle is set according to actual experience, and the embodiments of the present application are not limited.

[0153] S1005, forming a second electrode plate layer of the deep trench capacitor on the second dielectric layer, so that the second electrode plate layer is electrically connected with the second metallization layer;

[0154] Specifically, the second electrode plate layer of the deep trench capacitor is formed on the second dielectric layer, and the second electrode plate layer is electrically connected with the second metallization layer. The conductive material of the second electrode plate layer is selected according to actual needs, and the embodiments of the present application are not limited.

[0155] For example, the current structure is subjected to photolithography, the structure on the surface of the wafer is blocked, the surface of the second dielectric layer in the blind hole is exposed, and the second electrode plate layer is grown on the surface of the second dielectric layer in the blind hole by using a growth method that can fill deep holes.

[0156] S1006, filling the blind hole wrapped by the second electrode plate layer with a dielectric to form a filling dielectric layer of the deep trench capacitor;

[0157] Specifically, the blind hole wrapped by the second electrode plate layer is filled with a dielectric to form a filling dielectric layer of the deep trench capacitor. The filling dielectric layer is made of an insulating material, which is selected according to actual needs, and the embodiments of the present application are not limited.

[0158] For example, the current structure is subjected to photolithography, the structure on the surface of the wafer is blocked, the structure except the blind hole wrapped by the second electrode plate layer is protected by the photoresist, and the dielectric layer is grown or spin-coated in the blind hole to obtain the filling dielectric layer of the deep trench capacitor.

[0159] S1007, growing a conductive material connected with the first metallization layer and the second metallization layer respectively to form a first pad and a second pad of the computing unit.

[0160] Specifically, the conductive material is grown to be connected with the first metallization layer and the second metallization layer respectively, forming the first pad and the second pad of the computing unit. The first metallization layer of the Josephson junction is connected with the first electrode plate layer of the deep trench capacitor, and the second metallization layer of the Josephson junction is connected with the second electrode plate layer of the deep trench capacitor, so that the first pad and the second pad of the computing unit also serve as the two electrode plates of the deep trench capacitor, forming a superconducting quantum bit structure in which the Josephson junction and the deep trench capacitor are connected in parallel. This structure is similar to the traditional Transmon quantum bit, and the parallel large capacitor helps to reduce the sensitivity to charge noise, is easier to operate, and has a longer service life. The deep trench capacitor can achieve a much higher capacitance density than the planar capacitor under the same area, so the effect is more significant.

[0161] In the present application, the computing unit includes a superconducting quantum bit, a wafer, a deep trench capacitor, and a filling medium layer to form a core particle. The superconducting quantum bit includes a Josephson junction and the core particle.

[0162] The preparation method of the computing unit provided by the embodiment of the present application includes the following steps: forming a blind hole in a wafer, and forming a first electrode plate layer of a deep trench capacitor based on the blind hole; preparing a first metallization layer of a Josephson junction, and electrically connecting the first metallization layer with the first electrode plate layer; in-situ oxidizing the first metallization layer and the first electrode plate layer to form a first dielectric layer on the first metallization layer and a second dielectric layer on the first electrode plate layer; preparing a second metallization layer of the Josephson junction on the first dielectric layer; forming a second electrode plate layer of the deep trench capacitor on the second dielectric layer, and electrically connecting the second electrode plate layer with the second metallization layer; filling a medium in the blind hole wrapped by the second electrode plate layer to form a filling medium layer of the deep trench capacitor; and growing a conductive material to be connected with the first metallization layer and the second metallization layer respectively, forming a first pad and a second pad of the computing unit. Since the preparation processes of the deep trench capacitor and the Josephson junction are combined, the preparation process of the computing unit is simplified, the preparation efficiency of the computing unit is improved, and the cost is reduced.

[0163] FIG. 11 is a flowchart of a preparation method of a deep trench capacitor according to an eleventh embodiment of the present application. As shown in FIG. 11, based on the above-mentioned embodiments, further, the first electrode plate layer of the deep trench capacitor obtained based on the blind hole includes the following steps:

[0164] S1101, depositing an insulating layer on the surface of the wafer and the surface of the blind hole;

[0165] Specifically, an insulating layer is deposited on the surface of the wafer and the surface of the blind hole, and the insulating layer can cover the sidewall and the bottom of the wafer and the blind hole.

[0166] For example, a SiO2 thin film is deposited on the surface of the wafer and the sidewall and bottom of the blind hole by using a thin film growth technology capable of filling high aspect ratio, to obtain an insulating layer.

[0167] S1102, growing a conductive layer on the insulating layer;

[0168] Specifically, a conductive layer is grown on the insulating layer, and the conductive metal material used in the conductive layer is selected according to actual needs, which is not limited by the embodiments of the present application.

[0169] For example, a metal conductive material is grown on the insulating layer by using a thin film growth technology capable of filling high aspect ratio, to form a conductive layer.

[0170] S1103, patterning the conductive layer to form the first electrode plate layer.

[0171] Specifically, the conductive layer can be patterned by using photolithography and dry etching to form the first electrode plate layer. The first electrode plate layer can appropriately extend to outside the blind hole, so as to be electrically connected with the first metallization layer in the subsequent process. Wherein, the first electrode plate layer can extend to outside the blind hole.

[0172] Figure 12 is a flowchart of the preparation method of the Josephson junction provided by the twelfth embodiment of the present application. As shown in Figure 12, on the basis of the above-mentioned embodiments, further, the first metallization layer of the Josephson junction prepared on the wafer is electrically connected with the first electrode plate layer, which includes:

[0173] S1201, coating a double-layer glue on the wafer; wherein the selection of the double-layer glue needs to make the opening space formed by the lower layer glue after development larger than the upper layer glue;

[0174] S1202, exposing and developing the double-layer glue to form a double-layer glue with a double-opening structure on the wafer;

[0175] Specifically, the double-layer glue is exposed and developed to form a double-layer glue with a double-opening structure on the wafer, and the lower part of the double-opening structure forms a cavity, so as to facilitate the preparation of the first metallization layer and the second metallization layer.

[0176] S1203, based on the double-layer glue with a double-opening structure, a first metallization layer of the Josephson junction is prepared on the wafer at a first angle, so as to electrically connect the first metallization layer with the first electrode plate layer.

[0177] Specifically, the superconducting metal material is grown through the double-layer glue of the double-opening structure at a first angle to form a first metallization layer. The first angle is selected so that the first metallization layer can be electrically connected with the first electrode plate layer. The first angle is set according to actual experience, and the embodiments of the present application are not limited.

[0178] The first metallization layer and the first electrode plate layer are in-situ oxidized to form a first dielectric layer on the first metallization layer and a second dielectric layer on the first electrode plate layer.

[0179] FIG. 13 is a flowchart of a preparation method of a deep trench capacitor according to a thirteenth embodiment of the present application. As shown in FIG. 13, on the basis of the above-mentioned embodiments, after the second dielectric layer is completed, the method further includes:

[0180] S1301, if the conductive material of the first electrode plate layer is a preset material, the surface of the current structure is subjected to photolithography to obtain a second dielectric layer surface pattern;

[0181] Specifically, the first dielectric layer serves as a barrier layer of the Josephson junction, and the second dielectric layer serves as an insulating layer between the first electrode plate layer and the second electrode plate layer of the deep trench capacitor. The first dielectric layer cannot be too thick to avoid the failure of quantum tunneling; and the second dielectric layer cannot be too thin to avoid the failure of good insulation. Due to the functional differences between the barrier layer of the Josephson junction and the insulating layer of the deep trench capacitor, the first dielectric layer may meet the requirements while the second dielectric layer may not meet the requirements according to the different materials used. In the case where the conductive material of the first electrode plate layer is a certain preset material, the second dielectric layer obtained by in-situ oxidation of the first electrode plate layer cannot meet the insulation requirements, and the thickness of the second dielectric layer needs to be increased separately so that the second dielectric layer can meet the insulation requirements. The preset material is set according to actual conditions, and the embodiments of the present application are not limited.

[0182] S1302, based on the second dielectric layer surface pattern, an insulating material is deposited on the surface of the second dielectric layer to make the thickness of the second dielectric layer meet the insulation requirements.

[0183] Specifically, based on the second dielectric layer surface pattern, an insulating material is deposited on the surface of the second dielectric layer to increase the thickness of the second dielectric layer, so that the thickness of the second dielectric layer meets the insulation requirements. The thickness of the second dielectric layer is set according to actual needs, and the embodiments of the present application are not limited. The insulating material is selected according to actual needs, and the embodiments of the present application are not limited.

[0184] On the basis of the above-mentioned embodiments, further, a plurality of computing units are formed on the wafer.

[0185] Specifically, a plurality of Josephson junctions and deep trench capacitors corresponding to the respective Josephson junctions can be synchronously prepared on the wafer.

[0186] The computing module provided by the embodiment of the present application is prepared by using the preparation method of the computing unit of any of the above-mentioned embodiments, and the computing unit prepared thereby comprises a Josephson junction and a deep trench capacitor.

[0187] The Josephson junction can be prepared by using Al-based, Nb-based, Ta-based and the like, and the Josephson junction and other necessary functional auxiliary structures are used to construct various types of superconducting quantum bits. The superconducting quantum bits can be quantum bit types such as magnetic flux, charge, phase, and Transmon. The deep trench capacitor as a bypass capacitor of the superconducting quantum bit can help to greatly extend the quantum bit decoherence time, while reducing the occupied area, thereby reducing the planar size of the superconducting quantum bit. When the size of the deep trench capacitor is very small to reach the order of hundreds of nanometers, the possible limitation of integrated density may be the Josephson junction itself, rather than the bypass capacitor which is the main limiting factor at the present stage, thereby significantly improving the integrated density of active devices compared to the present stage process. The deep trench capacitor can provide a very high capacitance value under a smaller planar size, thereby significantly improving the area utilization rate.

[0188] FIG. 14A is a structural schematic diagram of a processor provided by a fourteenth embodiment of the present application, and FIG. 14B is a partial enlarged structural schematic diagram of the processor provided by the fourteenth embodiment of the present application, and FIG. 14B is an enlarged view of A in FIG. 14A, as shown in FIGS. 14A and 14B, the processor provided by the embodiment of the present application comprises the first adapter plate 1401, the resonant cavity core particle 1402 and the packaging substrate 1403 described in the above-mentioned embodiments, wherein:

[0189] The resonant cavity core particle 1402 is bonded on the first adapter plate 1401, and the first adapter plate 1401 is arranged on the packaging substrate 1403 through the spacer column 1404; the first adapter plate 1401 comprises a plurality of Josephson junctions 1405, and a part of the resonant cavity 1406 can also be arranged on the back surface of the first adapter plate 1401.

[0190] Specifically, the resonant cavity 1406 adopts a traditional planar resonant cavity structure. Due to the large size of the traditional planar resonant cavity, if arranged on the same plane, the spacing between adjacent quantum bits will be completely limited by the resonant cavity, thereby reducing the integration density of the device. Therefore, the embodiment of the present application proposes that part of the resonant cavity 1406 is provided in the form of a core particle, which is arranged on the resonant cavity core particle 1402 and connected to the superconducting quantum bit below by means of flip-chip bonding. Another part of the resonant cavity 1406 is arranged on the back of the first adapter plate 1401. In this way, the problem of loose quantum bit density caused by the coplanar arrangement of resonant cavities can be effectively alleviated.

[0191] The first adapter plate 1401 includes a plurality of Josephson junctions 1405, each Josephson junction 1405 having a corresponding resonant cavity 1406 and a deep trench capacitor 1407. The first adapter plate 1401 further includes a first carrier (a superconducting quantum bit containing adapter plate) 1408 for carrying each Josephson junction 1405 and the corresponding deep trench capacitor 1407, and the first carrier 1408 is arranged with the resonant cavity 1406 on the side surface close to the packaging substrate 1403. The resonant cavity core particle 1402 includes the resonant cavity 1406 and a second carrier 1409, and the second carrier 1409 is arranged with the resonant cavity 1406 on the side surface close to the first adapter plate 1401. The plurality of Josephson junctions 1405 are alternately coupled to the resonant cavities 1406 included in the first adapter plate 1401 and the resonant cavities 1406 included in the resonant cavity core particle 1402. The resonant cavity 1406 is used to realize the measurement and control of the Josephson junction 1405. The first adapter plate 1401 is arranged on the packaging substrate 1403 by means of the spacer column 1404.

[0192] Each Josephson junction 1405 can receive a control signal through a third data transmission link 1410 and output calculation data through a fourth data transmission link 1411. The fourth data transmission link 1411 passes through the resonant cavity 1406 included in the first adapter plate 1401.

[0193] As shown in FIG. 14A, on the basis of the above-mentioned embodiments, further, the third data transmission link 1410 includes a fifth transmission line 1410-1, an eleventh conductive part 1410-2, a third bump bonding pair 1410-3, a twelfth conductive part 1410-4 and a coaxial line 1410-5 connected in sequence; the fifth transmission line 1410-1 is coupled to the first pad 1405-1 of the Josephson junction 1405, the eleventh conductive part 1410-2 penetrates the first carrier 1408, and the twelfth conductive part 1410-4 penetrates the packaging substrate 1403.

[0194] The eleventh conductive part 1410-2 can be a coaxial via obtained by punching, filling a dielectric layer and a superconducting metal, and chemical mechanical polishing on the first carrier 1408. The twelfth conductive part 1410-4 can also be a coaxial via obtained by punching, filling a dielectric layer and a superconducting metal, and chemical mechanical polishing on the packaging substrate 1403. The superconducting metal includes but is not limited to aluminum, niobium, titanium nitride, etc., and the dielectric layer can be silicon dioxide, benzocyclobutene (BCB), polyimide (PI), etc., which are selected according to actual needs, and the embodiments of the present application are not limited.

[0195] As shown in FIG. 14A, on the basis of the above-mentioned embodiments, further, if the resonant cavity 1406 corresponding to the Josephson junction 1405 is on the resonant cavity core particle 1402, the fourth data transmission link 1411 includes a third bump bonding pair 1411-1, the resonant cavity 1406, a sixth transmission line 1411-2, a twelfth conductive part 1411-3, and a coaxial line 1411-4; the first end of the third bump bonding pair 1411-1 is coupled to the second pad 1405-2 of the Josephson junction 1405, the second end of the third bump bonding pair 1411-1 is coupled to the first end of the resonant cavity 1406 corresponding to the Josephson junction 1405, the second end of the resonant cavity 1406 is coupled to the first end of the sixth transmission line 1411-2, and the second end of the sixth transmission line 1411-2 is connected to the coaxial line 1411-4.

[0196] The second pad 1405-2 of the Josephson junction 1405 and the first end of the third bump bonding pair 1411-1 can be capacitively coupled. The second end of the third bump bonding pair 1411-1 and the first end of the resonant cavity 1406 can be capacitively coupled. The twelfth conductive part 1411-3 can be a coaxial via obtained by punching, filling a dielectric layer and a superconducting metal, and chemical mechanical polishing on the resonant cavity core particle 1402.

[0197] As shown in FIG. 14A, on the basis of the above-mentioned embodiments, further, if the resonant cavity 1406 corresponding to the Josephson junction 1405 is at the bottom of the first adapter plate 1401, the fourth data transmission link 1411 includes the seventh transmission line 1411-5, the fourth conductive part 1411-6, the resonant cavity 1406, the eighth transmission line 1411-7, the fourth bump bonding pair 1411-8, the fifth conductive part 1411-9 and the coaxial line 1411-10; the first end of the seventh transmission line 1411-5 is coupled to the second pad 1405-2 of the Josephson junction 1405, the second end of the seventh transmission line 1411-5 is connected to the first end of the fourth conductive part 1411-6, the second end of the fourth conductive part 1411-6 is coupled to the first end of the resonant cavity 1406 corresponding to the Josephson junction 1405, the second end of the resonant cavity 1406 is coupled to the first end of the eighth transmission line 1411-7, the second end of the eighth transmission line 1411-7 is connected to the first end of the fourth bump bonding pair 1411-8, the second end of the fourth bump bonding pair 1411-8 is connected to the first end of the fifth conductive part 1411-9, the second end of the fifth conductive part 1411-9 is connected to the coaxial line 1411-10, the fourth conductive part 1411-6 penetrates the first carrier 1408, and the fifth conductive part 1411-9 penetrates the packaging substrate 1403.

[0198] The second pad 1405-2 of the Josephson junction 1405 and the first end of the seventh transmission line 1411-5 can be capacitively coupled. The second end of the fourth conductive part 1411-6 and the first end of the resonant cavity 1406 can be capacitively coupled. The fourth conductive part 1411-6 can be a coaxial via obtained by punching, filling a dielectric layer and a superconducting metal, and chemical mechanical polishing on the first carrier 1408. The fifth conductive part 1411-9 can be a coaxial via obtained by punching, filling a dielectric layer and a superconducting metal, and chemical mechanical polishing on the packaging substrate 1403.

[0199] FIG. 15 is a structural schematic diagram of a processor provided by a fifteenth embodiment of the present application. As shown in FIG. 15, the processor provided by the embodiment of the present application includes the computing module 1501, the second adapter plate 1502 and the packaging substrate 1503 described in the above-mentioned embodiments, wherein:

[0200] The computing module 1501 is flip-chip bonded on the second adapter plate 1502, and the second adapter plate 1502 is arranged on the packaging substrate 1503 through the spacer column 1504; the computing module 1501 includes at least one Josephson junction 1505, and the first surface and the second surface of the second adapter plate 1502 are respectively provided with the resonant cavity 1506.

[0201] Specifically, the computing module 1501 is provided in the form of a core particle, and the integration density is improved by arranging the resonant cavities 1506 on the two surfaces of the second adapter plate 1502 respectively. Since the second adapter plate 1502 mainly contains a mature resonant cavity 1506 structure, the process yield is high, and the yield of the second adapter plate 1502 is less sensitive to the area than the low-yield computing module 1501, so that the second adapter plate 1502 is allowed to be fully dispersed to the area corresponding to the computing module 1501 in a similar "fan-out" manner. In the case of reasonable arrangement of the resonant cavities 1506 of the second adapter plate 1502, the integration density of the processor will mainly be related to the area of the computing module 1501 and the size of the Josephson junction, thereby fully exerting the small size advantage of the new quantum bit proposed in the present patent.

[0202] The computing module 1501 includes a plurality of Josephson junctions 1505, and each Josephson junction 1505 is provided with a corresponding deep trench capacitor 1507. The substrate of the computing module 1501 is a third carrier wafer 1508, which is used to carry each Josephson junction 1505 and the corresponding deep trench capacitor 1507. The computing module 1501 is flip-chip bonded on the second adapter plate 1502, and the first surface and the second surface of the second adapter plate 1502 are respectively provided with resonant cavities 1506. The second adapter plate 1502 is fixed on the packaging substrate 1503 by the spacer column 1504.

[0203] Each Josephson junction 1505 can receive a control signal through a fifth data transmission link 1509 and transmit output data through a sixth data transmission link 1510. The sixth data transmission link 1510 passes through the resonant cavity 1506 corresponding to the Josephson junction 1505.

[0204] FIG. 16A is a structural schematic diagram of a processor provided by a sixteenth embodiment of the present application, and FIG. 16B is a partially enlarged structural schematic diagram of the processor provided by the sixteenth embodiment of the present application, which is an enlarged view of C in FIG. 16A. As shown in FIGS. 16A and 16B, the processor provided by the embodiment of the present application includes the computing module 1601, the second adapter plate 1602 and the packaging substrate 1603 described in the above embodiments, wherein:

[0205] The computing module 1601 is flip-chip bonded on the second adapter plate 1602, and the second adapter plate 1602 is arranged on the packaging substrate 1603 by the spacer column 1604; the computing module 1601 includes at least one Josephson junction 1605, and the resonant cavity 1606 is arranged on the side surface of the packaging substrate 1603 close to the second adapter plate 1602.

[0206] Specifically, the computing module 1601 is provided in the form of a core particle, and the resonant cavity 1606 can be configured in a spiral line configuration, a coaxial configuration, etc., which can greatly reduce the planar area of the resonant cavity 1606. In this case, the integration density of the processor will be completely limited by the quantum bits themselves, and meanwhile, the effective arrangement of the input / output ports can be achieved without requiring the second adapter plate 1602 to be larger than the computing module 1601, the second adapter plate 1602 and the computing module 1601 can occupy the same planar area, and the occupied area is smaller and the integration density is higher relative to the structure of the processor as shown in FIGS. 14A and 15.

[0207] The computing module 1601 includes at least one Josephson junction 1605, and each Josephson junction 1605 corresponds to a deep trench capacitor 1607. The computing module 1601 further includes a fourth carrier wafer 1608 for carrying each Josephson junction 1605 and the corresponding deep trench capacitor 1607. The computing module 1601 is flip-chip bonded on the second adapter plate 1602, and the second adapter plate 1602 is fixed on the packaging substrate 1603 by the spacer column 1604. The resonant cavity 1606 is arranged on the side surface of the packaging substrate 1603 close to the second adapter plate 1602, and each Josephson junction 1605 corresponds to a resonant cavity 1606.

[0208] Each Josephson junction 1605 can receive a control signal through the fourteenth data transmission link 1609 and transmit output data through the eighth data transmission link 1610. The eighth data transmission link 1610 passes through the resonant cavity 1606 corresponding to the Josephson junction 1605.

[0209] As shown in FIG. 16A, on the basis of the above-mentioned embodiments, further, the seventh data transmission link 1609 includes a fifth bump bonding pair 1609-1, a ninth transmission line 1609-2, an eighth conductive part 1609-3, a sixth bump 1609-4, a ninth conductive part 1609-5 and a coaxial line 1609-6 connected in sequence; the fifth bump bonding pair 1609-1 is coupled to the first pad 1605-1 of the Josephson junction 1605, the eighth conductive part 1609-3 penetrates through the second adapter plate 1602, and the ninth conductive part 1609-5 penetrates through the packaging substrate 1603.

[0210] The external control signal is transmitted to the first pad 1605-1 of the Josephson junction 1605 through the coaxial line 1609-6, the ninth conductive part 1609-5, the sixth bump 1609-4, the eighth conductive part 1609-3, the ninth transmission line 1609-2 and the fifth bump bonding pair 1609-1 in turn. The eighth conductive part 1609-3 can be a coaxial via obtained by punching, filling a dielectric layer and a superconducting metal, and chemical mechanical polishing on the second adapter plate 1602. The ninth conductive part 1609-5 can be a coaxial via obtained by punching, filling a dielectric layer and a superconducting metal, and chemical mechanical polishing on the packaging substrate 1603. The superconducting metal includes but is not limited to aluminum, niobium, titanium nitride, etc., which is selected according to actual needs, and the embodiments of the present application are not limited.

[0211] As shown in FIG. 16A, on the basis of the above-mentioned embodiments, further, the eighth data transmission link 1610 includes the sixth bump 1610-1, the tenth transmission line 1610-2, the tenth conductive part 1610-3, the eleventh conductive part 1610-4, the eleventh transmission line 1610-5, the coaxial line 1610-6 and the coaxial line 1610-7; the first end of the sixth bump 1610-1 is coupled to the second pad 1605-2 of the Josephson junction 1605, the second end of the sixth bump 1610-1 is connected to the first end of the tenth transmission line 1610-2, the second end of the tenth transmission line 1610-2 is connected to the first end of the tenth conductive part 1610-3, the second end of the tenth conductive part 1610-3 is coupled and connected to the first end of the resonant cavity 1606 corresponding to the Josephson junction 1605, the second end of the resonant cavity 1606 is coupled and connected to the first end of the eleventh conductive part 1610-4, the second end of the eleventh conductive part 1610-4 is connected to the first end of the eleventh transmission line 1610-5, the second end of the eleventh transmission line 1610-5 is connected to the coaxial line 1610-6, and the third end of the eleventh transmission line 1610-5 is connected to the coaxial line 1610-7; the tenth conductive part 1610-3 penetrates the second adapter plate 1602, and the eleventh conductive part 1610-4 penetrates the packaging substrate 1603.

[0212] If the packaging substrate 1603 is made of semiconductor materials such as silicon, a separate dielectric region needs to be arranged between the resonant cavity 1606 corresponding to the Josephson junction 1605 and the first end of the eleventh conductive part 1610-4 to achieve the coupling connection between the resonant cavity 1606 and the first end of the eleventh conductive part 1610-4. The coupling connection between the resonant cavity 1606 and the first end of the eleventh conductive part 1610-4 can be capacitive coupling. The coupling connection between the second end of the tenth conductive part 1610-3 and the resonant cavity 1606 can be capacitive coupling. The tenth conductive part 1610-3 can be a coaxial through hole obtained by punching, filling a dielectric layer and a superconducting metal, and chemical mechanical polishing on the second adapter plate 1602. The eleventh conductive part 1610-4 can be a coaxial through hole obtained by punching, filling a dielectric layer and a superconducting metal, and chemical mechanical polishing on the packaging substrate 1603. The superconducting metal includes but is not limited to aluminum, niobium, titanium nitride, etc., which can be selected according to actual needs, and the embodiments of the present application are not limited.

[0213] On the basis of the above-mentioned embodiments, further, the resonant cavity 1606 can adopt a coplanar spiral line or a coaxial configuration.

[0214] It should be noted that all inter-chip interconnections in the present application can use solder bumps, stud bumps, etc., the adapter plate can be silicon-based, glass-based, etc., each conductive part can be made of through-silicon via technology (TSV), through-glass via technology (TGV), molded via technology (TMV), etc.; various film layers can be prepared by compatible sputtering, CVD, PVD, ALD, electroplating, chemical plating, etc. Common material growth techniques are replaced; various grooves, holes, and protruding structures can be replaced by compatible additive and subtractive processes, such as mechanical processing, dry etching, wet etching, material growth processes, 3D printing, etc. Commonly used technologies in the industry are replaced; and various material layers with electrical functions can be replaced by other materials with superconducting properties, such as TiN, Al, Ti, W, Ru, AlCu, In, Nb, Ta, NbN, and NbTiN-based materials.

[0215] The following describes a specific implementation process of the preparation method of the computing unit provided by the embodiments of the present application with a specific embodiment.

[0216] First step, preparing a blind hole. A blind hole 1702 is prepared on the surface of a wafer 1701 by photolithography and DRIE, as shown in FIG. 17A.

[0217] Second step, depositing an insulating layer. A SiO2 thin film is deposited on the surface of the wafer 1701 and the sidewall and bottom of the blind hole by using a thin film growth technology that can fill a high aspect ratio, as an insulating layer 1703, as shown in FIG. 17B.

[0218] Third step, forming conductive layer. A thin film growth technology with high aspect ratio filling capability is used to grow a metal conductive material on the insulating layer 1703, forming a conductive layer 1704, as shown in FIG. 17C.

[0219] Fourth step, forming first electrode plate layer. The conductive layer is patterned by using photolithography and dry etching, forming a first electrode plate layer 1705, as shown in FIG. 17D.

[0220] Fifth step, coating double-layer glue. Double-layer glue 1706 is coated on the slide 1701, so that the double-layer glue covers the insulating layer 1703 and the first electrode plate layer 1705, as shown in FIG. 17E. The developing removal rate of the lower layer glue 1706-1 in the double-layer glue 1706 is higher than that of the upper layer glue 1706-2, so as to form a subsequent double-opening structure.

[0221] Sixth step, forming double-layer glue of double-opening structure. The double-layer glue 1706 is subjected to electron beam direct writing and developing, forming a double-layer glue of double-opening structure 1706, as shown in FIG. 17F.

[0222] Seventh step, preparing first metallization layer. A superconducting metal material is grown on the insulating layer 1703 through the double-layer glue of double-opening structure 1706 at a first angle, forming a first metallization layer 1707 and a redundant electrode 1708, the first metallization layer 1707 being connected with the first electrode plate layer 1705, as shown in FIG. 17G. Further, in the process of preparing the first metallization layer 1707, it is possible to also grow a superconducting metal material on the first electrode plate layer 1705 in the blind hole at the same time. Since this part of the superconducting metal material is directly grown on the first electrode plate layer 1705, it has little effect on the electrical performance of the deep trench capacitor, and there is no need to separately process the superconducting metal material grown on the first electrode plate layer 1705, thereby improving the process flexibility. The superconducting metal material can be selected from Al, Nb and other superconducting metals commonly used in Josephson junctions.

[0223] Eighth step, in-situ oxidation. In the process of preparing the first metallization layer 1707, in-situ oxidation is directly performed in the vacuum environment, forming an oxide layer on the first metallization layer 1707, the redundant electrode 1708 and the first electrode plate layer 1705. The oxide layer on the first metallization layer 1707 constitutes a first dielectric layer 1709, and the oxide layer on the first electrode plate layer constitutes a second dielectric layer 1710, as shown in FIG. 17H.

[0224] In the ninth step, a second metallization layer is prepared. A superconducting metal material is grown on the first dielectric layer 1709 and the second dielectric layer 1710 on the slide 1701 through the double-layer glue 1706 at a second angle to form the second metallization layer 1711, and extra electrode 1712 and superconducting metal material on the insulating layer 1703, as shown in FIG. 17I. Further, during the preparation of the second metallization layer 1711, extra superconducting metal material can also be grown on the second dielectric layer 1710 of the blind hole. As described above, no additional treatment is required for the extra superconducting metal material, which improves the flexibility of the process. The second angle is set according to actual experience, and the embodiments of the present application are not limited.

[0225] In the tenth step, the double-layer glue is removed. The double-layer glue 1706 is removed by an organic solvent such as acetone to expose the structure on the slide 1701, as shown in FIG. 17J.

[0226] Further, after the double-layer glue is removed, if the conductive material of the first electrode plate layer 1705 is a preset material, and the thickness of the second dielectric layer formed after in-situ oxidation is insufficient to provide high dielectric properties required by the deep trench capacitor, photolithography is required to block all structures outside the blind hole to form a second dielectric layer surface pattern, and based on the second dielectric layer surface pattern, insulating material is further deposited on the second dielectric layer of the sidewall and bottom of the blind hole to make the thickness of the second dielectric layer of the sidewall and bottom of the blind hole meet the high dielectric properties required by the deep trench capacitor.

[0227] It should be noted that the conductive material of the first electrode plate layer 1705 should preferably be able to form a second dielectric layer that meets the high dielectric properties required by the deep trench capacitor after oxidation, so as to avoid the implementation of the above process step of increasing the thickness of the second dielectric layer, thereby reducing the complexity of the process.

[0228] In the eleventh step, a second electrode plate layer is formed. Photolithography is performed on the current structure to form a photoresist that blocks all structures outside the blind hole to form a second electrode plate layer surface pattern, and based on the second electrode plate layer surface pattern, a second electrode plate layer 1713 is grown in a growth mode that can fill deep holes, as shown in FIG. 17K.

[0229] In the twelfth step, dielectric filling is performed. Photolithography is performed on the current structure to form a photoresist 1715 that blocks all structures on the slide 1701 except the blind hole wrapped by the second electrode plate layer 1713 to form a filling dielectric layer surface pattern, and based on the filling dielectric layer surface pattern, a dielectric is grown in the blind hole wrapped by the second electrode plate layer 1713 to perform dielectric filling and form a filling dielectric layer 1714, as shown in FIG. 17L. The filling dielectric layer 1714 is made of insulating material.

[0230] Thirteenth step, removing the oxide layer. Before growing the conductive material, the photoresist 1715 is removed by acetone and ultrasonic, and then the oxide layer on the surface of the exposed first metallization layer 1707 and the excess electrode 1708 is removed. The removing of the oxide layer on the surface of the exposed first pad and the excess electrode 1708 specifically includes: covering the second metallization layer 1711, part of the first dielectric layer 1709 and the deep trench capacitor by the photoresist 1716, removing the oxide layer on the surface of the exposed first metallization layer 1707 (i.e. the part of the first dielectric layer 1709 exposed outside) and the oxide layer on the surface of the excess electrode 1708, 1712 by dry etching, as shown in FIG. 17M.

[0231] Fourteenth step, growing the conductive material. The conductive material is grown on the insulating layer 1703 to form the first pad 1717 and the second pad 1718 of the Josephson junction, as shown in FIG. 17N. The first pad 1717 is in communication with the first electrode plate layer 1705 of the deep trench capacitor, and the second pad 1718 is in communication with the second electrode plate layer 1713. The first pad 1717 and the second pad 1718 are also the first pad and the second pad of the deep trench capacitor, that is, the Josephson junction and the deep trench capacitor form a parallel structure.

[0232] Fifteenth step, removing the photoresist. The photoresist 1716 is removed by acetone, as shown in FIG. 17O.

[0233] The preparation method of the computing unit, the computing module and the processor provided by the embodiment of the present application have the following advantages:

[0234] (1) The physical size of the component is significantly reduced, and the integration density is significantly increased. The vertical structure with high aspect ratio can be used to construct a deep trench capacitor structure with small planar area and large capacitance value, so as to replace the coplanar capacitor required by the quantum bit, and is more conducive to the vertical coupling node of the three-dimensional interconnection structure such as the FC and the TSV as the quantum bit and the resonant cavity.

[0235] (2) The oxide layer of the Josephson junction and the oxide layer of the deep trench capacitor are prepared synchronously in the present application, and the new process of in-situ oxidation not only simplifies the overall process steps, but also avoids the interface deterioration problem caused by the transfer of the metal and metal oxide interface in the atmosphere after leaving the high vacuum cavity, provides an as ideal interface state as possible, and helps to improve the coherence performance of the Josephson junction and the high capacitance capability of the deep trench capacitor. The Josephson junction and the deep trench capacitor share the first pad and the second pad, realize the direct parallel electrical connection, and avoid other additional parasitic effects.

[0236] (3) The deep trench capacitor and other three-dimensional interconnection structures are directly introduced into the core quantum component, which has a significant advantage in three-dimensional integration process compatibility and modular assembly, and is more conducive to the physical implementation of the chip architecture.

[0237] (4) The steps of core particle bonding, core particle-adaptor plate package bonding, etc. can be completed integrally after placement through a one-time bonding process, which shortens the process complexity and reduces the adverse effects of repeated temperature rising and falling processes on Josephson junctions.

[0238] (5) The packaging substrate allows multiple adaptors to be carried, and different types of quantum bit cores can be carried between different adaptors, which significantly improves the large-scale scalability of the system under the premise of ensuring yield, and helps to provide a convenient test platform for lateral comparison of different types of quantum bit performance.

[0239] In an embodiment, the application provides a preparation method of a computing unit, comprising:

[0240] forming a blind hole in the wafer, and forming a first electrode plate layer of a deep trench capacitor based on the blind hole;

[0241] preparing a first metallization layer of a Josephson junction, and electrically connecting the first metallization layer with the first electrode plate layer;

[0242] in-situ oxidizing the first metallization layer and the first electrode plate layer, forming a first dielectric layer on the first metallization layer, and forming a second dielectric layer on the first electrode plate layer;

[0243] preparing a second metallization layer on the first dielectric layer to form a Josephson junction;

[0244] forming a second electrode plate layer of a deep trench capacitor on the second dielectric layer, and electrically connecting the second electrode plate layer with the second metallization layer;

[0245] filling the blind hole wrapped by the second electrode plate layer with a dielectric to form a filled dielectric layer of the deep trench capacitor;

[0246] growing a conductive material connected with the first metallization layer and the second metallization layer respectively to form a first pad and a second pad of the computing unit.

[0247] In an embodiment, the first electrode plate layer of the deep trench capacitor based on the blind hole comprises:

[0248] depositing an insulating layer on the surface of the wafer and the blind hole;

[0249] growing a conductive layer on the insulating layer;

[0250] patterning the conductive layer to form the first electrode plate layer.

[0251] In an embodiment, the method for preparing the Josephson junction further comprises:

[0252] coating a double-layer resist on the wafer; wherein the double-layer resist is selected to form an opening space in the lower-layer resist larger than that in the upper-layer resist after development;

[0253] exposing and developing the double-layer resist to form a double-layer resist with a double-opening structure on the wafer;

[0254] preparing a first metalization layer of the Josephson junction on the wafer at a first angle based on the double-layer resist with the double-opening structure, and electrically connecting the first metalization layer with the first electrode plate layer.

[0255] In an embodiment, after the second metalization layer of the Josephson junction is prepared on the first dielectric layer, the method further comprises:

[0256] if the conductive material of the first electrode plate layer is a preset material, performing photolithography on the surface of the current structure to obtain a second dielectric layer surface pattern;

[0257] depositing an insulating material on the surface of the second dielectric layer based on the second dielectric layer surface pattern to make the thickness of the second dielectric layer meet the requirement of insulation.

[0258] In an embodiment, a plurality of computing units are formed on a wafer.

[0259] In an embodiment, the application provides a computing module comprising at least one computing unit prepared by the preparation method described in any of the above embodiments.

[0260] In an embodiment, the application provides a processor comprising a first adapter plate, a resonant cavity chip, and a packaging substrate, wherein:

[0261] the resonant cavity chip comprises at least one resonant cavity bonded on the first adapter plate; the first adapter plate has at least one computing unit on its top surface and at least one resonant cavity on its bottom surface, and is arranged on the packaging substrate through a spacer column.

[0262] In an embodiment, the application provides a processor comprising a computing module, a second adapter plate, and a packaging substrate, wherein:

[0263] the computing module is flip-chip bonded on the second adapter plate, and the second adapter plate is arranged on the packaging substrate through a spacer column; the computing module comprises at least one Josephson junction, and the first surface and the second surface of the second adapter plate are respectively provided with at least one resonant cavity.

[0264] In an embodiment, the application provides a processor comprising a computing module, a second adapter plate and a package substrate, wherein:

[0265] The computing module is flip-chip bonded on the second adapter plate, and the second adapter plate is disposed on the package substrate by a spacer column; the computing module comprises at least one Josephson junction, and a resonant cavity is disposed on a side surface of the package substrate close to the second adapter plate.

[0266] In the description of the present specification, the description of the terms "one embodiment", "one specific embodiment", "some embodiments", "for example", "exemplary", "specific example", or "some examples" and the like means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In the present specification, the illustrative description of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0267] The specific embodiments described above further illustrate the objects, technical solutions and advantages of the present application. It should be understood that the above description is only for specific embodiments of the present application and is not intended to limit the protection scope of the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A computing unit comprising superconducting qubits, characterized in that, The superconducting quantum bit comprises a Josephson junction and a core particle, wherein: The core particle comprises a carrier sheet, a deep trench capacitor embedded in the carrier sheet, and a filling medium layer covering the carrier sheet and the deep trench capacitor, and the deep trench capacitor is electrically connected with the Josephson junction.

2. The computing unit according to claim 1, characterized in that, Further comprising an adapter plate, the Josephson junction is arranged on the adapter plate, the adapter plate is bonded to the filling medium layer, the first electrode plate of the Josephson junction is electrically connected with the first conductive layer of the deep trench capacitor through a first bump and a first conductive part, and the second electrode plate of the Josephson junction is electrically connected with the second conductive layer of the deep trench capacitor through a second bump and a second conductive part; the first conductive part is arranged in the filling medium layer and connects the first bump and the first conductive layer; the second conductive part is arranged in the filling medium layer and connects the second bump and the second conductive layer.

3. The computing unit according to claim 1, c h a r a c t e r i z e d i n that, Further comprising an adapter plate, the core particle has a plurality of core particles, the filling medium layer of each core particle is bonded to the adapter plate, the deep trench capacitor of each core particle corresponds to at least one Josephson junction, and each Josephson junction is arranged on the adapter plate.

4. The computing unit according to claim 1, characterized in that, The Josephson junction is arranged on the filling medium layer, the first electrode plate of the Josephson junction is electrically connected with the first conductive layer of the deep trench capacitor through a third conductive part, and the second electrode plate of the Josephson junction is electrically connected with the second conductive layer of the deep trench capacitor through a fourth conductive part; the third conductive part and the fourth conductive part are arranged in the filling medium layer respectively.

5. The computing unit according to claim 1, characterized in that, The Josephson junction is arranged on the filling medium layer, the first electrode plate of the Josephson junction is electrically connected with the second conductive layer of the deep trench capacitor through a fifth conductive part, and the second electrode plate of the Josephson junction is electrically connected with the first conductive layer of the deep trench capacitor through a sixth conductive part; the fifth conductive part and the sixth conductive part are arranged in the filling medium layer; and the deep trench capacitor is located below the second electrode plate.

6. The computing unit according to claim 1, characterized in that, The deep trench capacitor corresponds to a plurality of Josephson junctions.

7. The computing unit according to claim 1, characterized in that, The core particle comprises a plurality of deep trench capacitors, and each deep trench capacitor corresponds to at least one Josephson junction.

8. The computing unit according to claim 7, characterized in that, There are deep trench capacitors with different structures in the plurality of deep trench capacitors.

9. The computing unit according to claim 1, characterized in that, The deep trench capacitor comprises 2n conductive layers, and the deep trench capacitor corresponds to n Josephson junctions.

10. The computing unit according to any one of claims 1 to 9, characterized in that, The Josephson junction has a plurality of Josephson junctions, and each Josephson junction is communicatively connected through a corresponding coupling structure.

11. A processor comprising a superconducting quantum chip, characterized in that, The superconducting quantum chip comprises the superconducting quantum bit of any one of claims 1 to 10, a packaging substrate, and a PCB board, wherein: The superconducting quantum bit is arranged on the packaging substrate through a spacer column; a resonant cavity is arranged on the surface of the side of the packaging substrate close to the superconducting quantum bit, and the resonant cavity corresponds to one Josephson junction; The PCB board is arranged at the bottom of the packaging substrate; The Josephson junction of the superconducting quantum bit receives a control signal through a first data transmission link and outputs data through a second data transmission link, and the second data transmission link passes through a resonant cavity corresponding to the Josephson junction of the superconducting quantum bit.

12. The processor of claim 11, wherein, The superconducting quantum bit has a plurality of superconducting quantum bits.

13. The processor of claim 12, wherein, The plurality of superconducting quantum bits includes superconducting quantum bits with different structures.

14. The processor of claim 11, wherein, The first data transmission link includes a first transmission line, a first superconducting conductive part, a first superconducting coaxial bump, a second superconducting conductive part, a second transmission line and a control coaxial line connected in sequence; the first transmission line is coupled to a first plate of the Josephson junction, the control coaxial line is arranged on the PCB board, the second superconducting conductive part penetrates the packaging substrate, and the first superconducting conductive part penetrates the adapter plate or penetrates the carrier sheet and the filling dielectric layer.

15. The processor of claim 11, wherein, The second data transmission link includes a third transmission line, a third superconducting conductive part, a fourth superconducting conductive part, a fourth transmission line and a reading coaxial line, wherein: The first end of the third transmission line is coupled to a second plate of the Josephson junction, the second end of the third transmission line is connected to the first end of the third superconducting conductive part, the second end of the third superconducting conductive part is coupled to the resonant cavity corresponding to the Josephson junction, the resonant cavity corresponding to the Josephson junction is coupled to the first end of the fourth superconducting conductive part, the second end of the fourth superconducting conductive part is connected to the first end of the fourth transmission line, and the second end of the fourth transmission line is connected to the reading coaxial line; The reading coaxial line is arranged on the PCB board, the fourth superconducting conductive part penetrates the packaging substrate, and the third superconducting conductive part penetrates the adapter plate or penetrates the carrier sheet and the dielectric layer.

16. The processor of any one of claims 11 to 15, wherein, The resonant cavity adopts a coplanar spiral line structure.

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