Optoelectronic device, pixel array and method for processing an optoelectronic device

Abstract

The invention concerns an optoelectronic device, comprising a layer stack with structured sidewalls (16) extending substantially perpendicular to an emission surface (110) from a second doped semiconductor layer (12), an active region (13) onto a first portion of a first doped semiconductor layer (ID with a second portion extending laterally from the sidewalls. A dielectric material layer (20) is arranged partially on the contact layer (14), the sidewalls (16) and on the second portion of the first doped semiconductor opposite the emission surface (110) and comprises a central opening (22) and beveled sidewalls (200). A conductive and reflective layer (21) is arranged on the beveled sidewalls (200) contacting the contact layer (14) through the opening (22). The device further comprises a buried contact structure (40) arranged in the second portion of the first doped semiconductor layer (11) extending adjacent to the dielectric material layer (20) towards the emission surface (110) and an out coupling structure (50) located above the emission surface (110).

Description

[0001] 2024PF00497

[0002] OPTOELECTRONIC DEVICE , PIXEL ARRAY AND METHOD FOR PROCESSING AN

[0003] OPTOELECTRONIC DEVICE

[0004] The present application claims priority form German patent application DE 10 2024 125 197 . 2 dated September 03 , 2024 , the disclosure of which is incorporated herein by reference in its entirety . The present invention concerns an optoelectronic device , in particular a pLED, a pixel array and a method for processing an optoelectronic device .

[0005] BACKGROUND

[0006] Optoelectronic devices with an edge sized of less than 50pm down to approximately 1 pm to 2pm are references as pLEDs . Those devices are implemented in a variety of different application requiring high resolution, and brightness on very small size .

[0007] For example , in certain augmented reality and virtual reality applications as well as small proj ectors , the overalls size of such devices should not exceed 2 cm x 2 cm at Full-HD resolution ( 1980 x 1080 pixels ) or even 4K resolution . Like in certain automotive applications , the emitted light should be collimated and provide a high brightness . Several challenges are associated with such requirements .

[0008] For a high light extraction efficiency ( LEE ) or certain far-field characteristics , a certain structure of the optoelectronic devices is advisable . It has been found that certain angles the pixel sidewall are desired, as those improve the light extraction, based on the internal quantum efficiency and the material systems used for the optoelectronic devices . At the same time , it has been found that sidewalls should be treated to reduce etching effects and thus improve the internal quantum efficiency or IQE .

[0009] For this purpose , a KOH etching process is often conducted as this process provides a self-aligned and self-terminating treatment of the sidewalls , reducing the above-mentioned defects . However, the angle for the device' s sidewall suitable for good light extraction is not compatible with KOH etching treatment . Thus , one must either accept a loss of the internal quantum efficiency by omitting the KOH defect etch 2024PF00497 or find a way to process inclined sidewalls otherwise for the reflective mirror to be deposited .

[0010] At the same time , one wants to reduce optical crosstalk between several optical devices arranged next to each other and monolithically implemented . Any light out coupling structures with as much space as possible .

[0011] It is an obj ect of the present application to provide an optoelectronic device that provides an improved internal quantum efficiency, while ensuing a good light extraction efficiency . It is also an obj ect to provide a pixel array with reduced crosstalk and a method of providing an optoelectronic device with an improved internal quantum efficiency .

[0012] SUMMARY OF THE INVENTION

[0013] This and other obj ects are addressed by the subj ect matter of the independent claims . Features and further aspects of the proposed principles are outlined in the dependent claims .

[0014] The inventor has realized that an important aspect is the size of the out coupling structure in relation to the size of the optoelectronic device , and particularly the size of the emission surface . This is particularly challenged as the emission surface of pLEDS comprises a size of about 1 pm2to about 50 pm2, for example . Consequently, the inventor proposes a buried contact structure , thus enabling a planar light emission surface which can be used to structure out coupling structures as large as the pixel pitch . The buried contact structure also separates adj acent monolithically integrated optoelectronic devices , reducing the crosstalk in between them.

[0015] This aspect can be combined with sidewalls optimized for reflecting light towards the out coupling structure , while maintaining a low defect density at edges of the active region . The proposed optoelectronic device is suitable for monolithically integration to form pixel arrays of various color . In this regard, the expression "various color" or certain color" refers to one or more optoelectronic devices that are configured to emit a certain light in operation of the device . For example , a blue pLED or a blue optoelectronic device 2024PF00497 is an optoelectronic device configured to emit blue light . A corresponding RGB pixel array is an array with a plurality of optoelectronic devices , each of them configured to emit one of red, green and blue colors .

[0016] In some aspects , the inventor proposes an optoelectronic device , comprising a layer stack . The layer stack comprises a first doped semiconductor layer having an emission surface . An active region is arranged on a side of the first doped semiconductor layer opposite the emission surface . A second doped semiconductor layer is arranged on the active region . Finally, a contact layer is deposited on the second doped semiconductor layer opposite the active region .

[0017] Different deposition techniques and material systems are applicable for processing the layer stack . Material systems for generating optoelectronic devices are based on GaN and AlGaN . Those material systems can be amended by replacing pats of Ga by In to shift the emission wavelength . The layer stack is deposited on certain crystallographic planes , which are known in the art . In case of red optoelectronic devices and pLEDs , phosphide material system like GaP , and AlGaP are suitable .

[0018] The active region may comprise a quantum well or a multi-quantum well including a plurality of thin quantum well and barrier layers with an optional cladding layer sandwiching the previously mentioned layers . The doped layer may comprise constant or varying dopant concentration implementing different functionalities , like for example current spreading and current distribution as well as charge carrier blocking layers .

[0019] The layer stack of the proposed optoelectronic device further comprises a sidewall extending substantially perpendicular to the emission surface from the second doped semiconductor layer onto a first portion of the first doped semiconductor layer , wherein a second portion of the first doped semiconductor layer extends laterally from the sidewalls . A dielectric material layer is arranged partially on the contact layer , the sidewalls and on the second portion of the first 2024PF00497 doped semiconductor opposite the emission surface . The dielectric layer material is transparent to light generated in the active region in operation of the device and comprises a central opening giving access to the second contact layer and beveled sidewalls with an increasing diameter towards the emission surface .

[0020] The separation of the beveled sidewalls and the sidewalls of the structured layer stack enables optimization of internal quantum efficiency and light extraction efficiency independent of each other . A reflective layer is arranged on the beveled sidewalls , contacting the contact layer through the opening . The reflective layer can also be conductive . In any case , a conductive material is filled in the opening, providing electrical contact to the second doped layer . In addition, a buried contact structure is arranged in the second portion of the first doped semiconductor layer and extends adj acent to the dielectric material layer towards the emission surface .

[0021] Finally, the optoelectronic device according to the proposed principle comprises an out coupling structure located above the emission surface and may extend at least up to the buried contact structure .

[0022] In some aspects , the proposed optoelectronic device according further comprises a dielectric layer that is deposited on the sidewalls and the second portion of the first doped semiconductor layer between the sidewalls and the second portion of the first doped semiconductor layer and the dielectric material layer . The dielectric layer may be deposited using ALD or other similar deposition techniques and may be used to treat and passivate the surface of the KOH etched sidewalls of the layer stack . The material of the dielectric layer is usually different from the material of the dielectric material layer and may comprise for example A12O2 or AIN . In some cases , the material of the dielectric layer is the same as of the dielectric material layer , for example when Si02 is used . The dielectric layer may comprise various different sublayers . The dielectric material layer may comprise Si02 and Nb2O5 for example . 2024PF00497

[0023] In some further aspects , the optoelectronic device comprises a dielectric reflective structure , particularly a DBR arranged between the dielectric material layer and the conductive layer , such DBR structure reflects the emitted light such that a non-ref lective material like ITO and the like can be sued as conductive layer . In some other aspects , the DBR structure is additionally provided to improve the reflection .

[0024] Some other aspects concern the geometry of the first layer stack . In some aspects , a thickness of the first portion of the first doped semiconductor layer is larger than a combined thickness of the second doped semiconductor layer and the active region . However, it may be desirable for certain design to reduce the first doped semiconductor layer to the extent possible . In some other aspects , a thickness of the second doped semiconductor layer, the active region and the first portion of the first doped semiconductor layer is smaller than a diameter of the layer stack bounded by the sidewalls . For example , the diameter may range from 1pm to less than 10pm, resulting in a thickness of the layer stack to be less than 10pm and down to less than 1pm . In this regard, it should be noted that a thickness of the second portion may be larger than a thickness of the layer stack as defined above .

[0025] In some aspects , the contact layer, in particular comprising a transparent conductive oxide is arranged on a central portion of the second doped semiconductor layer opposite the active region . The contact layer may be smaller than an area or size of the second doped semiconductor layer such that the material of the contact layer is not flush with the edge of the second doped semiconductor layer but is set back .

[0026] In some other aspects , the buried contact structure extends from a recess in the dielectric material layer, through the optional dielectric layer into the second portion of the first doped semiconductor layer . Its height may be a large as a thickness of the second portion of the first doped semiconductor . In some aspects , the buried contact structure comprises beveled sidewalls with a decreasing diameter towards the emission surface . In case the buried contact 2024PF00497 structure comprises a reflective material , light emitted towards the buried contact structure is reflected towards the out coupling structure further supporting the efficiency of the optoelectronic device .

[0027] Ins some aspects , the buried contact structure may act a suppressor against optical crosstalk, particularly if several proposed optoelectronic devices are adj acently arranged on a common backplane or monolithically integrated . Therefore , the contact structure may laterally surround the layer stack, in particular at a position that is outside a proj ection of the beveled sidewalls of the buried dielectric material layer onto the emission surface .

[0028] In some aspects , the conductive and in particular reflective layer overlaps over the buried contact structure but is vertically separated by a portion of the dielectric material layer .

[0029] Likewise , in some aspects , a proj ection of the beveled sidewalls of the conductive and in particular reflective layer onto the emission surface is laterally distanced from a proj ection of the sidewalls extending substantially perpendicular to the emission surface onto the emission surface and particularly comprises a larger diameter . In other words , the sidewalls of the reflective layer are beveled at an area sufficiently laterally distanced from the sidewalls of the layer stack . Different angles of the beveled sidewalls in the range of 30 ° to 65 ° are possible . Those angles may also change . For instance , the inventor proposes in some aspects that the beveled sidewalls comprises at least two different angles in a portion laterally distanced from a proj ection of the sidewalls extending substantially perpendicular to the emission surface onto the emission surface and particularly comprises a larger diameter . In other words , the angle of the beveled sidewalls changes , particular to higher values in the direction towards the emission surface .

[0030] Different shapes of a proj ection of the beveled and perpendicular sidewalls onto the emission surface are possible . In addition, the shapes of a proj ection of the beveled sidewalls of the dielectric 2024PF00497 material layer or the reflective layer and a proj ection of the perpendicular sidewall can be different . Possible shapes include a square , a rectangle , a hexagon and a circle .

[0031] Some aspects relate to the out coupling structure . In some aspects , the out coupling structure comprises the same material as the first doped semiconductor layer . It is possible in some aspects to structure the first doped semiconductor layer to form at least a part of the out coupling structure . In some other aspects , the out coupling structure extends laterally on the emission surface to a position above the buried contact structure surrounding the layer stack . The out coupling structure therefore covers the emission surface completely and partially the buried contact structure . This will ensure , that light emitted from the device will be collimated and formed in the out coupling structure , particularly if the buried contact structure acts as a further reflector . In some further aspects , the out coupling structure terminates at an edge of the buried contact structure , such that the buried contact structure optionally acts as a light reflecting element .

[0032] The out coupling structure comprises at least one of a micro lens , a DBR layer structure , a periodic structure with a periodicity smaller than a lateral dimension of a diameter of a proj ection of the layer stack onto the emission surface , a conversion material , or a photonic crystal . Several elements can be combined to achieve a desired optical function .

[0033] The buried contact structure provides an electric contact to the first semiconductor layer . For an external contact , the optoelectronic device according to the proposed principle further comprises a metallic contact plug that contacts the buried contact structure through the first doped semiconductor layer , wherein optionally the metallic contact plug is separated from conductive reflective layer by the dielectric material layer . This is referred as top contact . In an alternative approach, a metallic contact plug contacts the buried contact structure through a dielectric material layer , that is from 2024PF00497 the back side . The latter may be suitable as backplane can contact both sides of the layer stack from contact plugs on the same side .

[0034] In some aspects , the proposed optoelectronic further comprises a backplane with a circuit layer, in particular including one or more CMOS circuit elements having at least two contact areas . The contact areas are connected to the contact layer via the conductive reflective layer and to the buried contact structure via respective contact plugs .

[0035] The proposed optoelectronic device is suitable for light generation of different colors . This is achieved either by proper material selection or by a conversion material . In some instances , the proposed optoelectronic device further comprises a conversion material . The conversion material may be arranged on the emission surface , with optionally the out coupling structure arranged on the conversion material . The conversion material can also be embedded in the out coupling structure . As a further alternative , the conversion material may be arranged in a recess in the first doped semiconductor layer , a surface of the conversion material opposite a bottom of the recess forming the emission surface . A wavelength dependent reflective layer can be arranged above the recess to reflect non-converted light back to the conversion material .

[0036] Some further aspects concern a pixel array . The pixel array may comprise at least three optoelectronic devices according to the proposed principle . The three optoelectronic devices are configured to emit light of different wavelength . For this purpose , the least three optoelectronic devices may comprise different base material systems . For example nitride material system, optionally with In content are sued to provide blue and green light , while phosphide material system are suitable for generating red light . In some aspects , a conversion material as proposed further above can be sued to provide light conversion and emission of light with different colors . In accordance with the proposed principle , an emission area of the optoelectronic devices configured to emit light in the green portion of the visible spectrum is larger than an emission area of the two other optoelectronic devices . 2024PF00497

[0037] Some other aspects concern a method for processing an optoelectronic device . The method comprises providing a layer stack on a carrier growth substrate as a first step . On the growth substrate , a plurality of different layer is deposited using various epitaxial deposition techniques . These include , but are not limited to gas phase deposition, chemical vapor deposition CVD and MOCVD with its respective derivates . Particularly, a first doped semiconductor layer is deposited on the growth substrate , whereas the growth substrate may also comprise a buffer layer to provide a smooth and effect reduced surface . An active region is then deposited on a side of the first doped semiconductor layer opposite the growth substrate . The active region may comprise one o more quantum well and quantum barrier layers , that can be doped or slightly doped . In some aspects , the barrier layers are distinguished from the quantum well layer by a different Al content . Two undoped cladding layers may embed the quantum well and quantum barrier layers to prevent undesired dopant diffusion into the quantum well layers and aging thereof .

[0038] A second doped semiconductor layer is deposited on the active region . Depending on the base material system, for example particularly for nitride-based material systems , an optional contact layer , particularly made of ITO can be deposited on the second doped semiconductor layer opposite the active region .

[0039] The layer stack is then structured to provide sidewalls extending substantially perpendicular to the growth substrate from the second doped semiconductor layer onto a first portion of the first doped semiconductor layer . This is achievable for example by depositing a structured mas k on the surface and then providing a plasma etching process to remove material of the layer stack, thereby exposing sidewalls thereof . The sidewalls are then treated using a KOH etching process . This step is , depending on the growth direction and crystallographic plane , a self-aligned and self-terminating process and results in a sidewall substantially perpendicular to the growth substate . The various etching and treatment steps also cause a second portion of the first doped semiconductor layer to remain on the growth 2024PF00497 substrate , whereas the second portion extends laterally from the sidewalls .

[0040] A conductive contact structure is formed partially into an area of the second portion of the first doped semiconductor layer laterally displaced to the sidewalls of the layer stack . In some aspects , the conductive contact structure completely surrounds the structured layer stacks and its sidewalls . The conductive contact structure reduces cross talk in an operation of the device . A dielectric material layer is deposited in a subsequent step , burying the layer stack, the second portion of the first doped semiconductor layer and the conductive contact structure . The dielectric material layer is transparent to light generated in the active region in operation of the device on a surface of the layer stack . In some instances , the dielectric material layer may comprise Si02 or Nb2O5 .

[0041] The dielectric material layer is structured, and an etching process is conducted to form beveled sidewalls of the dielectric material layer and an opening through the dielectric material layer, thereby exposing a portion of the second doped semiconductor layer . Form and shape and its position in regard to the layer stack are already presented above .

[0042] In a subsequent step, a reflective and in particular conductive layer is deposited on the beveled sidewalls contacting the contact layer through the opening . The conductive layer can comprise silver, a gold alloy or another highly reflective material . The processed structured layer stack is then rebonded to the structured layer stack to a substrate and removing the growth substate to expose a surface of the first doped semiconductor layer . An out coupling structure is finally arranged above the surface of the first doped semiconductor layer located above the structured layer stack .

[0043] The proposed method enables to optimize the sidewalls of the layer stack generated after the plasma etching process and hen subsequently provide an optimized beveled sidewall . Both sidewalls can be optimized separately and independent for each other for its respective functionality . In some further aspects , the step of structuring the 2024PF00497 layer stack comprises the step of depositing, particularly by ALD, a dielectric layer on the sidewalls and the second portion of the first doped semiconductor layer . The dielectric layer on the sidewalls and the second portion of the first doped semiconductor layer comprises for example A12O3 or AIN may thus be different from the material used for the dielectric material layer . The layer of A12O3 or AIN reduced defect density on the KOH etched sidewalls of the layer stack .

[0044] The of depositing conductive and in particular reflective layer may comprise the step of structuring the deposition of the conductive and in particular reflective layer such that an area above the contact structure is free of material of the conductive and in particular reflective layer . This will provide an opening to the contact structure and can serve to subsequently deposit a contact material upon . In addition, it is used to separate adj acent optoelectronic devices from each such that they can be addressed separately later in operation of a device containing a plurality of such devices . For this purpose , material of conductive and in particular reflective layer above the second portion of the first doped semiconductor layer may be removed .

[0045] In some further optional steps , a conductive contact plug is deposited in said area through an opening in the dielectric material layer . The conductive contact plug is electrically isolated from the conductive and in particular reflective layer, for example by material of the dielectric material layer . In some aspects , a proj ection of the beveled sidewalls of the conductive and in particular reflective layer onto the emission surface is laterally distanced from a proj ection of the sidewalls extending substantially perpendicular to the emission surface onto the emission surface and particularly comprises a larger diameter . In some further aspects , the beveled sidewall comprises at least two different angles in a portion laterally distanced from a proj ection of the sidewalls extending substantially perpendicular to the emission surface onto the emission surface and particularly comprises a larger diameter . For example , the beveled sidewalls can be curved and form a parabolic or other curved lens . 2024PF00497

[0046] Some further aspects relate to the step of providing an out coupling structure located above the structured layer stack . In some aspects , a conversion material may first be deposited on the surface of the first doped semiconductor layer . The out coupling structure is then arranged on the conversion material . In an alternative approach, a conversion material is deposited in the out coupling structure . A collimating element may be arranged above the conversion material to collimate the converted light . In some further alternative aspects , a recess is formed into the first doped semiconductor layer . The conversion material is the arranged in a recess in semiconductor layer ( 11 ) and providing a conversion material in said recess .

[0047] To prevent unconverted light from being emitted, a wavelength dependent reflective layer can be arranged as part of the out coupling structure above the conversion material .

[0048] SHORT DESCRIPTION OF THE DRAWINGS

[0049] Further aspects and embodiments in accordance with the proposed principle will become apparent in relation to the various embodiments and examples described in detail in connection with the accompanying drawings in which

[0050] Figure 1 shows a first embodiment of an optoelectronic device in accordance with some aspects of the proposed principle ;

[0051] Figure 2 illustrates a top and side view of two optoelectronic devices in accordance with some aspects of the proposed principle ;

[0052] Figures 3 and 4 show side and top views of various cuts through an embodiment of an optoelectronic device in accordance with some aspects of the proposed principle ;

[0053] Figure 5 illustrates a top and side view of a pixel array in accordance with some aspects of the proposed principle ;

[0054] Figures 6 and 7 show two side views of an optoelectronic device in accordance with some aspects of the proposed principle ; 2024PF00497

[0055] Figure 8 shows two embodiments of a pixel array with a plurality of optoelectronic devices including contact elements for contacting them in accordance with some aspects of the proposed principle ;

[0056] Figure 9 illustrates an embodiment of an optoelectronic device with a different out coupling structure in accordance with some aspects of the proposed principle ;

[0057] Figure 10 shows an embodiment of an optoelectronic device in accordance with some aspects of the proposed principle ;

[0058] Figure 11 illustrates an embodiment of an optoelectronic device with differently angled sidewalls in accordance with some aspects of the proposed principle ;

[0059] Figure 12 shows another embodiment of an optoelectronic device in accordance with some aspects of the proposed principle ;

[0060] Figures 13 and 14 illustrate two embodiments of an optoelectronic device with different out coupling structures in accordance with some aspects of the proposed principle ;

[0061] Figure 15 shows another embodiment of an optoelectronic device with a conversion material applied thereto in accordance with some aspects of the proposed principle ;

[0062] Figures 16A and 16B illustrate a pixel array configured to emit light of different colors ;

[0063] Figures 17A to 17H illustrate several method steps for processing an optoelectronic device in accordance with some aspects of the proposed principle ;

[0064] Figure 18 shows an optoelectronic device processed by the proposed method . 2024PF00497

[0065] DETAILED DESCRIPTION

[0066] The following embodiments and examples disclose various aspects and their combinations according to the proposed principle . The embodiments and examples are not always to scale . Likewise , different elements can be displayed enlarged or reduced in size to emphasize individual aspects . It goes without saying that the individual aspects of the embodiments and examples shown in the figures can be combined with each other without further ado , without this contradicting the principle according to the invention . Some aspects show a regular structure or form . It should be noted that in practice slight differences and deviations from the ideal form may occur without , however , contradicting the inventive idea .

[0067] In addition, the individual figures and aspects are not necessarily shown in the correct size , nor do the proportions between individual elements have to be essentially correct . Some aspects are highlighted by showing them enlarged . However , terms such as "above" , "over" , "below" , "under" "larger" , "smaller" and the like are correctly represented with regard to the elements in the figures . So it is possible to deduce such relations between the elements based on the figures .

[0068] Figure 1 illustrates an embodiment of an optoelectronic device in accordance with the proposed principle .

[0069] The optoelectronic device comprises a layer stack 10 with a plurality of different layers partially buried in a transparent dielectric material 20 . The layer stack 10 in particular comprises a first doped layer 11 , a second doped layer 12 and an active region 13 arranged in between . First doped layer 11 is at least partially n-doped and second doped layer is p-doped . The active region 13 comprises one or more quantum well layers , whereas in the latter case , the various quantum well layers are separated by respective quantum barrier layers . Quantum well and quantum barrier layers differentiate by their respective Al content in the present example . Active region 13 may also comprise two cladding layers , not illustrated herein, to prevent an undesired dopant 2024PF00497 diffusion from the first or the second doped semiconductor layer into the active region .

[0070] The layer stack 10 further comprises a contact portion 14 centrally arranged on the surface of the second doped layer 12 opposite the active region 13 . Material of first doped layer 11 also extends laterally the perpendicular sidewall 16 of layer stack 10 and forms a second portion of first doped semiconductor layer 11 , while the layer stack includes the first portion of first doped semiconductor layer 11 . Sidewall 16 extends from the contact portion 14 towards the main emission surface 110 of the layer stack .

[0071] The sidewall as well as the surface of the first doped semiconductor material 11 is covered by a dielectric layer 15 . The dielectric layer 15 comprises aluminum oxide , A12O3 or aluminum nitride , AIN and is only a few nm in thickness for example up to 40 nm. It is used for surface passivation of the perpendicular exposed sidewalls of the layer stack 10 And reduce non-radiative sidewall recombinations .

[0072] A transparent dielectric layer material 20 is arranged filling the space between the lateral second portions of first semiconductor layer 11 parallel to the emission surface 10 and the side walls 16 . The dielectric material layer 20 extends onto the top of the central contact layer 14 and the dielectric layer 15 deposited thereupon . An opening in the dielectric material layer 20 is filled with a reflective conductive material 21 to provide a contact to the contact layer 14 . As illustrated in figure 1 , the dielectric material layer 20 comprises beveled sidewalls with an increasing diameter towards the main emission surface 110 . As further illustrated, a proj ection of the beveled sidewalls 200 onto the emission surface 110 is laterally displaced and separated from a respective proj ection of the perpendicular sidewall 16 onto the emission surface . In other words , a virtual extension of the perpendicular sidewalls 16 through the conductive reflective layer 21 does not cut through the beveled area 200 , but the beveled region of conductive reflective layer 21 lies outside and surrounds the layer stack . 2024PF00497 16

[0073] A buried contact structure 40 is laterally displaced and separated from layer stack 10 . The buried contact structure 40 is located within the dielectric material layer 20 and reaches through the dielectric layer 15 into the material of the first doped semiconductor layer 11 . In the present embodiment , the buried contract structure 40 comprises beveled sidewalls with a slightly decreasing diameter towards the main emission surface 110 . Although, not illustrated herein, the buried contact structure 40 can reach deep into the second portion of first doped semiconductor layer 11 , almost up to the actual mission surface . In the present case , the buried contact structure 40 completely surrounds the layer stack 10 .

[0074] Further illustrated in Figure 1 , a virtual extension of the beveled sidewalls of conductive reflective layer 21 towards the emission surface and contact structure 40 does intersect the contact buried structure 40 . Rather, contact buried structure 40 is arranged slightly displaced and separated from that virtual extension, such that the virtual extension intersects the dielectric layer 15 at a location between contact structure 40 and the perpendicular sidewalls 16 of layer stack 10 .

[0075] A further bonding and filling material 30 is arranged on the beveled sidewalls as well as on any other surface of dielectric reflective layer 21 to provide an even and smooth surface of the device . An optical element 50 in form of a plens is further arranged on the emission surface 110 . As illustrated, the optical element 50 is located between the virtual center of the buried contact structures 40 surrounding the layer stack 10 .

[0076] The different beveled sidewalls 16 and 21 of the optoelectronic device enable optimizing the internal quantum efficiency as well as the light extraction efficiency independent of each other . This is further supported by the structure and shape of the optical element 50 . Buried contact structure 40 may further support and act as a reflective and crosstalk reduction / prevention element between adj acent optoelectronic devices . At the same time , buried contact structure 40 surrounding the layer stack provides an electrical contact to the first semiconductor 2024PF00497 layer 11 , while the conductive reflective layer 12 , electrically isolated from the buried contact structure 40 , provides an electrical contact through the opening 22 to the second doped semiconductor layer 12 .

[0077] The perpendicular sidewalls 16 are treated during processing of the device to reduce the crystallographic defects and dangling bonds on the etched sidewalls . The etching process is performed with a KOH etching step, which is a self-aligned and self-terminating procedure to provide the illustrated perpendicular sidewalls . The angle a of the conductive reflective layer 21 onto a normal of the emission surface 110 can be adj usted based on the growth parameters of the dielectric material layer 20 . Dielectric material layer 20 may comprise SiO2 or Nb2O5 or any similar non-ref lective , transparent and dielectric material .

[0078] Light being emitted from active region 13 is either reflected at the conductive reflective layer 21 or directly emitted towards the optical structure 50 . Optical structure 50 comprises a lens and the like . It is used to collimate and out couple light from the semiconductor material of the first doped layer 11 .

[0079] Figure 2 illustrates a pixel array in a top and side view, respectively . The pixel array comprises a 2x2 matrix of in total 4 optoelectronic devices in accordance with the proposed principle . As illustrated herein, the shapes of the layer stack 10 with the perpendicular sidewalls 16 can be different in relation to the optical out coupling structure 50 . In the present case , the shape of the layer stack 10 and the vertical sidewalls 16 is rectangular, while the shape of the out coupling structure 50 is virtually circular . The out coupling structures of two adj acent optoelectronic devices are touching each other in a small area . As illustrated in the side view below the top view, the buried contact structure 40 is beneath the area of the two out coupling structures , 50in which the two structure 50 collide . The buried contact structure 40 therefore does not only provide an electrical contact to the material of the first doped semiconductor 2024PF00497

[0080] 11 , but also prevents a crosstalk between two adj acent optoelectronic devices .

[0081] As further illustrated, the material of the first doped semiconductor layer 11 is the same as the material of the out coupling structure 50 . This is suitable in some designs , as the out coupling structure 50 can be processed and shaped directly afterward on the material of the first doped semiconductor layer 11 using proper alignment mechanisms without depositing further layers of different material thereupon .

[0082] Some further embodiments are illustrated in Figures 3 and 4 , respectively . Elements with similar or the same functionality comprises the same reference signs . Figure 3 illustrates a top view of a pixel array illustrated in its side view in Figure 4 . The second drawing of Figure 4 further illustrates also a top view with a different cut through the optoelectronic device , namely though the dielectric layer 15 . As shown in this embodiment , the shape of the out coupling structure 50 is rectangular , with two out coupling structures of adj acent optoelectronic devices arranged directly adj acent to each other above the buried contact structure 40 . Contract structure 40 surrounds each of the optoelectronic devices and provides a common electrode and contact for each of the optoelectronic devices . As illustrated in the second drawing of Figure 4 , contact structure 40 is directly beneath the individual out coupling structures 50 indicated by the dashed line .

[0083] Apart from a circular and rectangular shapes as illustrated in the respective top views of the previous figure , other shapes as shown in figure 5 are usable for implementing a display with optoelectronic devices in accordance with the proposed principle .

[0084] Figure 5 illustrates a top view, in which a pixel array of optoelectronic devices in hexagonal shape are formed . In this regard, each of out coupling structures 50 comprises a hexagonal shape . Each of the hexagonal out coupling structures are arranged directly adj acent to one another . The hexagonal shapes allow to place a plurality of optoelectronic devices and out coupling structures directly adj acent to each other without some space in between . The buried contact 2024PF00497 19 structure 40 also comprises a rectangular shape that lies between the borders of two adj acent out coupling structures as shown in the second drawing of Figure 5 .

[0085] In the present example , the out coupling structures are arranged on the emission surface , stretching between the surrounding buried contact structure . The buried contact structure 40 can be used as a marker and indicator for implementing and processing the respective out coupling structure . Furthermore , in case of self-aligned processing , the buried contact structure 40 can be used as a border or edge for the out coupling structure itself . Figure 6 illustrates the respective embodiment . While the layer stack 10 and the respective semiconductor layers are implemented in the same way, the buried contact structure 40 reaches from the dielectric material layer 20 through the dielectric layer 15 far into and beyond the main emission surface 11 . More particularly, dielectric material layer 20 comprises a recess with a depth h, into which material of the buried contact structure 40 is deposited . The contact structure 40 extend through dielectric layer 15 to the height H . The top surface of buried contact structure 40 is above the main emission surface 110 of the first doped layer 11 .

[0086] As a result thereof , the action of contact structure 40 acts as a limiter and edge for the material of out coupling structure 50 . Consequently, out coupling structure 50 substantially extends within the inner edges of buried contact structure 40 . The top surface of buried contact structure 40 can either be free of material of the deposited out coupling structure 50 or j ust comprise a small portion of such material . The adj acent out coupling structure 50 illustrated in Figure 6 lies adj acent to the other etch of contact buried structure 40 .

[0087] In the present example of Figure 6 , the processing of out coupling structure 50 is perfeclty aligned . However, due to misalignment of the respective mas king procedure , the resulting optoelectronic structure 50 may also be slightly misaligned . Due to the lateral size and diameter of the contact buried structure 40 , small tolerances are available when processing a plurality of the optoelectronic devices in accordance with the proposed principle . As such, a small misalignment in the out 2024PF00497 20 coupling structures 50 as shown in Figure 7 does not result m a larger deterioration of the overall light extraction efficiency of the device . Rather , a small misalignment in the same range as the lateral distance is affordable without tempering the functionality of the device .

[0088] Another aspect is illustrated in the two drawings of Figure 8 . The respective drawings illustrate a side view of a plurality of optoelectronic devices in accordance with the proposed principle . In the respective embodiments , the plurality of optoelectronic devices are monolithically integrated, having the respective buried contact structure 40 surrounding each of the optoelectronic devices . The optoelectronic devices are arranged and soldered onto a backplane 60 having a plurality of circuits 62 implemented therein with contact pads on its surface . Backplane 60 may comprise silicon Si as based material or any other suitable material , whereas the circuitry 62 can be implemented using bipolar or CMOS technology .

[0089] A plurality of contact areas is located on the surface of backplane 60 , the distances and lateral space between the contact areas corresponding to the contact areas on the bottom surface of the conductive reflective layer 21 . In the present embodiment , the conductive reflective layers 21 are separated in the area beneath the contact buried structure 40 by removing the material of layer 21 therein and filling the opening gap 31 with the dielectric filling material 30 . Consequently, each of the contacts of conductive reflective layers 21 are separated from each other , while the buried contact structure 40 provides a common contact area for each of the first doped semiconductor layer 11 .

[0090] A common contact plug 61 is now arranged in the dielectric filling material 30 reaching through the dielectric material layer 20 and contacting a buried contact structure 41 . The buried contract structure 41 is in turn connected to the buried contact structures 40 separating each of the optoelectronic devices from each other . As a result illustrated in the upper drawing of figure 8 , all contact pads of the pixel array to an external contact , i . e . of the backplane to the plurality of optoelectronic devices are arranged on the same side . The 2024PF00497 21 backplane 60 comprise corresponding pads on its upper surface , enabling a quick connection without the need of a redistribution layer .

[0091] The second drawing illustrates a slightly different solution, in which the common contact pad 41 is contacted through the top surface and an opening in the material providing the out coupling structure 50 . The contact plot 63 may still be a connected to the backplane 60 in an area outside the subpixel array . The surface size of contact structure 41 is larger than the size of plug 63 compensating for a possible misalignment during contacting procedure . Both solutions offer a common contact to the buried contact structure 40 of the plurality of optoelectronic devices and the pixel array without interfering with the external quantum efficiency or the light extraction efficiency, respectively .

[0092] The out coupling structures 50 can have different shapes and forms depending on the needs and requirements . Figure 9 illustrate another embodiment of such out coupling structure 51 . In contrast to previous embodiments , out coupling structure 51 provides a different shape . However, as illustrated, each of the out coupling structures extends between a location above the contact barrier structure 40 and therefore directly above the respective layer stack 10 and the beveled sidewalls 21 . In other words , the present embodiments illustrate that the out coupling structure may have a maximum size larger than the size of the layer stack and the beveled sidewalls and thus covering the whole emission surface .

[0093] Figure 10 illustrates an embodiment , in which a contact plug 63 made of metal or similar reflective material is filled into the gap and whole provided through the offered coupling structure 50 and the first doped semiconductor layer 11 . In the present example , contact black 63 comprises slightly beveled sidewalls with a decreasing diameter towards the buried contact area 40 . However , this inclination is not required . Rather , contact plug 63 can comprise perpendicular sidewalls or sidewalls with a decreasing diameter towards the upper surface of the optical out coupling structure , thereby reflecting the light back towards the out coupling structure 50 itself . 2024PF00497

[0094] In the previous embodiments , the beveled sidewalls 200 of the dielectric material layer 20 and the reflective layer 21 comprise a constant angle from a position slightly laterally displaced from a proj ection of the perpendicular sidewall 16 towards the emission surface to a position slightly laterally displaced with regard to the buried contact structure . Nevertheless , the dielectric layer material fills the space between the buried contact structure 40 and the reflective conductive layer 21 .

[0095] However, Figure 11 illustrates an embodiment , in which at least a portion of the sidewalls comprises curved or different angles . In the embodiment , the beveled sidewalls 210 have two different angles a and o' compared to a normal onto the main emission surface as shown . The first angle a extends from the bottom of the conductive reflective layer 21 , that is closest to the layer stack 10 towards the barrier contact structure 40 . A second angle a ' then extends from a position laterally distanced from the layer stack 10 and perpendicular sidewalls 16 , further towards the buried contact structure 40 . However , as shown, angle o ' is slightly smaller in regard to a normal onto the emission surface 100 than the first angle o . As a result , the change of the diameter increases of the bevel sidewall of conductive reflective layer 21 decreases towards the emission surface , when the inclination changes from angle a to angle o' . The beveled sidewalls with a varying angles can be used to implement a parabolic reflective surface or any other shaped beveled surfaces , thereby improving the light emission and light extraction efficiency .

[0096] In some aspects , the reflection coefficient of the conductive material 21 may not be sufficient to provide a optimal reflection . For example , it might be necessary to use a transparent conductive oxide for the conductive layer 21 of the opening 22 to contact the contacting portion 14 also made for instance of a transparent conductive oxide , TCO ( ITO for example ) or a p-doped semiconductor material . In cases , the reflection coefficient is not sufficient for layer 21 , one may use a DBR structure applied directly on the beveled sidewalls of the dielectric material layer 20 . Figure 12 illustrates a respective embodiment , which comprises a dielectric DBR structure 203 deposited 2024PF00497 on the beveled sidewalls . The DBR structure 203 comprises a plurality of different layers to 201 and 202 having different refractive indices . The thickness of the respective layers resembles 1 / 4 of the wavelengths of the emitted light and is usually in the range of a few l OOnm . Light being emitted towards the DBR structure 203 is reflected by constructive interference towards the main emission surface 110 . While the DBR structure 203 in this particular embodiment is used to provide the reflection, it may be advisable in some aspects to utilize the DBR structure 203 in addition to a conductive and reflective material of layer 21 .

[0097] Figures 13 to 14 illustrate different out coupling structures in accordance with the proposed principle . Out coupling structure 52 of Figure 13 comprises a periodic structure generating a virtual bandgap , thus suppressing light from being emitted in certain directions , also referred as a photonic crystal . In the present example , the photonic crystal structure 52 does not extend only over one optoelectronic device with a boundary given by the buried contact structures 40 , but over a plurality of adj acent optoelectronic devices . The periodicity of the out coupling structure 52 and the photonic crystal is higher than the lateral a diameter of the optoelectronic device itself .

[0098] Another out coupling structure provided by an anti-reflective coating is given by element 53 illustrated in Figure 14 . The out coupling structure may also extend above the plurality of optoelectronic devices as illustrated herein . The anti-reflective coating or any other coating adapting the refractive indices towards the adj acent material can be combined with the different other out coupling structures disclosed herein .

[0099] Some further aspects are illustrated in Figure 15 . In some instances , it is advisable to convert the light emitted and generated by the active region 30 into different wavelengths using a converter material . For example , nitride-based material systems usually emit with a wavelength in the blue to green portion of the visible spectrum, while red light emission is often provided by phosphide material systems . In cases , in which nitride-based material systems are selected to emit 2024PF00497 24 red light as well , one can use a conversion material which converts blue or green light into a longer wavelength in the red spectrum ( the same applies for conversion of blue into green light ) .

[0100] For this purpose , a conversion material can be applied directly on the main emission surface 110 of the optoelectronic device in accordance with the proposed principle . In such embodiments , the out coupling structure or any other optical element is usually arranged above the conversion material , such that the converted light is emitted through the optical element . In this regard, the optical element may comprise a wavelength sensitive reflecting material to reflect non-converted light back into the conversion material for an additional conversion . DBR structures are suitable for such wave-length sensitive reflective layers .

[0101] In some other aspects , illustrated in Figure 15 , a recess is formed in the first doped semiconductor layer 11 , usually in the first and second portion thereof . The recess preferably extends laterally throughout the layer stack 10 close to or to the buried contact structure 40 . The recess may then be filled with the conversion material 111 , said material including quantum dots , for example . The recess may be completely filled with the quantum dots , which can extend above the emission surface to provide a full conversion of the emitted light . The proposed approach offers a small and compact design, with the conversion material 111 being as close as possible to the light generation structure in active region 13 .

[0102] Light reflected from the conductive reflective material layer 21 will eventually be absorbed in the conversion material 111 and converted into a light with a larger wavelength . The buried contact structure 40 can act as border and etch for the recess to provide a self alignment when implementing the recess and filling the conversion material therein . Top surface of the conversion material 111 can then be covered by optical out coupling structure , plenses and the like . The use of conversion material to provide light of different wavelengths is suitable in a pixel arrays and pixel arrangements with optoelectronic devices in accordance with the proposed principle . The optoelectronic 2024PF00497 devices are optimized m their internal quantum efficiency and the external light extraction efficiency, independent of each other . A proper conversion material is placed above the light emission surface of the first doped semiconductor layer or in the recess thereof . One can implement a pixel array of providing different colors for emission . Each of those optoelectronic devices in the pixel array is individually addressable . As a result , an RGB pixel can be implemented using the proposed optoelectronic devices without changing the base material system .

[0103] Figures 16A and 16B illustrate a top view of two pixel arrays implemented and configured to emit light of various wavelengths . The respective embodiments emphasize the fact that the human eye is more sensitive to green light than to blue or red light , respectively . As a result thereof , the overall emission areas for green light provided by a respective converting material 111 is increased in comparison to the emission areas of the other colors . The conversion material can be applied on top of the main emission surface or within the recess of the surface in accordance to the embodiment of Figure 15 shown herein .

[0104] Two optoelectronic devices are covered by a converting material configured to emit green light in Figure 16A, while one optoelectronic device of a pixel is covered by a converting material 112 configured to emit red light . The remaining optoelectronic devices for each pixel only comprise the out coupling structure 50 , thus configured to emit light in the blue portion of the spectrum.

[0105] Each of the optoelectronic devices are surrounded by the common buried contact structure 40 . As shown in the top view, each of the emission areas are equal in size , but there are two green emission areas in each pixel , while only one pixel for red and blue light . The resulting ratio R : G : B is 1 : 2 : 1 . On the embodiment illustrated in Figure 16B, the emission area for green in each pixel is also doubled . However , this is achieved by simply enlarging the emission area of the optoelectronic device ( in the present case even slightly larger than a factor of 2 , as the buried contact 40 between two adj acent optoelectronic devices is missing ) . Hence , the area configured to emit green light is 2024PF00497 26 significantly larger approximately twice the size of the emission areas for red and blue light , respectively . This embodiment also illustrates the possibility of different shapes for optoelectronic devices in accordance with the proposed principle .

[0106] Figures 17A to 17H as well as Figure 18 illustrate a method for processing a plurality of optoelectronic devices in accordance with the proposed principle . As illustrated in Figure 17A to Figure 17H , only one of the plurality of optoelectronic devices is presented . However, the proposed method can be applied on wafer level processing a plurality of optoelectronic devices at once , those devices suitable for the proposed pixel arrays and arrangements as well as for separate individual pixels and optoelectronic devices , respectively .

[0107] A growth substrate 100 for example , comprising GaN, AlGaN or sapphire is provided in a first step . The growth substrate may comprise a plurality of undoped buffer layers to ensure a substantial defect free or at least defect-reduced flat surface . A first doped semiconductor layer 11 is deposited on said surface , using chemical vapor deposition techniques , for example . Those are known for the skilled person and no not deviate from conventional techniques . The first doped semiconductor layer 11 may comprise a plurality of different layers to further reduce the defect density and achieve different functionalities like current inj ection and current transportation into adj acent layers . Furthermore , in some aspects , the material of this first doped layer and also a part of the buffer layers may be later used for implementing and processing the optical out coupling structures .

[0108] An active region 13 is then deposited on top of the first doped semiconductor layer 11 . Active region 13 may comprise an undoped cladding layer to prevent in undesired dopant diffusion from the first doped semiconductor layer 11 into the quantum well and barrier layers of active region 13 . Active region 13 comprises a multi-quantum well structure with a plurality of barrier and quantum well layers . The barrier layer includes a slightly larger bandgap for instance implemented by a different aluminum content in the respective base material during deposition of the layers . Another cladding layer ( not shown) is deposited on the multi-quantum well structure , on which a p- 2024PF00497 doped second semiconductor layer 12 is deposited upon . Then, a mas k layer is arranged structured and a structured transparent contact layer 14 applied thereupon . The transparent contact is made of ITO for example to ensure a good electrical contact with a low transition resistance to the p-doped semiconductor layer 12 .

[0109] Then, a hard mas k may be applied on the top surface of contact layer 14 structured followed by a mesa etching process . The etching process exposes sidewalls of the contact layer 14 , the p-doped semiconductor layer 13 , the active region 13 as well as a first portion of the first doped semiconductor layer 11 . However, the etching process is stopped with material of the first semiconductor layer still being present on the growth substrate 100 as illustrated in Figure 17A. Then, another etching process with KOH is conducted . The KOH etching process is a self-alignment and self-terminating process in gallium nitride material system based on the growth direction . In the present case , it results in perpendicular sidewalls with a flat lateral surface . As a result , layer stack 10 is generated using a KOH process with a first portion having perpendicular sidewalls 16 and a second portion of the first doped semiconductor layer 11 , extending laterally thereto . The resulting structure after the KOH and any other optional surface treatment is illustrated in Figure 17H .

[0110] After the treatment using a KOH etching process is completed, a thin dielectric layer made of aluminum dioxide , A12O3 or aluminum nitride , AIN is deposited using an atomic layer deposition process , ALD . The thickness of dielectric layer 15 may comprise a few nanometers . The dielectric layer covers the whole surface as shown in Figure 17B .

[0111] The results of the next steps are shown in Figure 17C . First , another mask layer is deposited, structured and a recess is formed through a portion of dielectric layer 15 in the second portion of first doped semiconductor 11 . The recess is laterally displaced from the perpendicular sidewalls and reaches into the material of first doped semiconductor layer 11 . The recess is subsequently filled with a conductive material , forming a contact structure 40 . Although not presented herein, contact structure 40 surrounds the layer stack 2024PF00497 28 completely . The depth of the contact structure 40 into the second portion of first doped semiconductor layer 11 as well as the height and the producing of the barrier structure 40 above the dielectric layer 15 is adj ustable by the respective process . The height and protrusion above the dielectric layer 15 may depend on the height of the mas k layer ( not shown herein ) , while the depth of contact barrier structure into the second portion of layer 11 depends on the previously performed selective etching process .

[0112] In a subsequent step , the surface of dielectric layer 15 is covered and overgrown by a dielectric material layer 20 . Dielectric material layer 20 may comprise a transparent material like as SiO2 . It covers the surface of dielectric layer 15 and completely buries the contact structure 40 . Furthermore , due to the layer stack 10 , the dielectric material layer 20 forms a bulge over the layer stack 10 . The result is illustrated in figure 17D . The bulged is used as an initial staring point to generate the beveled sidewalls in a subsequent etching step .

[0113] An etching process is performed, shown in Figure 1E7 , which removes parts of the dielectric material layer 20 , resulting in beveled sidewalls 200 . The etching process is self-aligned in the present case due to the bulge of the deposited dielectric material layer . As an alternative , one or more mask layers can be applied and subsequently structured to remove the material of dielectric material layer 20 to generate the beveled sidewalls 200 . Furthermore , the sidewalls 200 are beveled at a location that is laterally displaced between the perpendicular sidewalls 16 of the buried contact structure 40 . In the present embodiment , the buried contact structure remains buried and covered by material of dielectric material layer 20 even after the etching process is completed .

[0114] Then, an opening 22 is generated through a top portion of dielectric material layer 20 and dielectric layer 15 , exposing a part of the surface of contact layer 14 as presented in Figure 17 F .

[0115] Then, a conductive and reflective layer 21 is deposited on the top surface of dielectric layer 20 and the beveled sidewalls 200 . The 2024PF00497 29 material of conductive reflective layer 21 fills the opening 22 , thereby contacting layer 14 .

[0116] In some aspects , another mask layer is deposited and structured and subsequently openings 31 are etched over the buried contract structure 42 to separate adj acent optoelectronic devices from each other . In this regard, it should be noted that , buried contract structure 40 completely surrounds layer stack and beveled sidewalls 16 . The result of such separation is presented in Figure 17G .

[0117] The opening 31 is then filled with another dielectric layer material 30 to provide a flat , levelled surface with an opening therein centrally arranged over layer 21 on the layer stack . The opening is filled with a contact material to provide a contact to reflective layer 21 . Alternatively, the dielectric layer material polished and grinned back to provide access to the conductive portion of reflective layer 21 .

[0118] The plurality of optoelectronic devices is then ready to be transferred to a secondary substrate , which in the present case is a backplane 60 with a plurality of contacts and circuit elements 62 therein . Each contact and circuit element provides a contact to the conductive electric layer 21 of each device . This process illustrated in Figure 17H, also referred to as a re-bonding process , provides access to the bottom side of the first semiconductor layer 11 .

[0119] The growth substrate 100 is removed and the top surface of layer 11 exposed in a subsequent step . Then, one or more optical out coupling elements 50 as illustrated in figure 18 can be applied upon .

[0120] 2024PF00497

[0121] LIST OF REFERENCES

[0122] 1 optoelectronic device

[0123] 10 layer stack

[0124] 11 first doped semiconductor layer

[0125] 12 second doped semiconductor layer

[0126] 13 active region

[0127] 14 contact layer

[0128] 16 sidewalls

[0129] 20 dielectric material layer

[0130] 21 reflective layer

[0131] 22 opening

[0132] 30 dielectric layer

[0133] 31 opening

[0134] 40 buried contact structure

[0135] 50 out coupling structure

[0136] 52 photonic crystal

[0137] 53 AR Coating

[0138] 60 backplane

[0139] 61 contact plug

[0140] 62 circuit

[0141] 63 contact plug

[0142] 110 emission surface

[0143] 111 conversion material

[0144] 112 conversion material

[0145] 200 beveled sidewall

[0146] 201 DBR structure

[0147] 210 curved sidewall

[0148] H, h heights

Claims

2024PF00497CLAIMS1. Optoelectronic device (1) , in particular a pLED comprising- a layer stack comprising a first doped semiconductor layer (11) having an emission surface ( 110 ) ; an active region (13) arranged on a side of the first doped semiconductor layer (11) opposite the emission surface (110) ; a second doped semiconductor layer (12) arranged on the active region ( 13 ) ; a contact layer (14) arranged on the second doped semiconductor layer (12) opposite the active region; sidewalls (16) extending substantially perpendicular to the emission surface (110) from the second doped semiconductor layer (12) onto a first portion of the first doped semiconductor layer (11) , wherein a second portion of the first doped semiconductor layer (11) extends laterally from the sidewalls; a dielectric material layer (20) that is transparent to light generated in the active region in operation of the device, said dielectric material layer (20) arranged partially on the contact layer (14) , the sidewalls (16) and on the second portion of the first doped semiconductor opposite the emission surface (110) ; wherein said dielectric material layer (20) comprises a central opening (22) and beveled sidewalls (200) with an increasing diameter towards the emission surface (110) ; a conductive and in particular reflective layer (21) arranged on the beveled sidewalls (200) contacting the contact layer (14) through the opening (22) ; a buried contact structure (40) , particularly at least partially encapsulated by a dielectric layer arranged in the second portion of the first doped semiconductor layer (11) an out coupling structure (50) located above the emission surface (110) .

2. Optoelectronic device according to claim 1, further comprising a dielectric layer (15) deposited on the sidewalls (16) and the second2024PF00497 portion of the first doped semiconductor layer (11) between the sidewalls and the second portion of the first doped semiconductor layer (11) and the dielectric material layer (20) , material of the dielectric layer (15) being different from material of the dielectric material layer (20) .

3. Optoelectronic device according to any of the preceding claims, further comprising a dielectric reflective structure, particularly a DBR arranged between the dielectric material layer (20) and the conductive and in particular reflective layer (21) .

4. Optoelectronic device according to any of the preceding claims, wherein a thickness of the first portion of the first doped semiconductor layer (12) is larger than a combined thickness of the second doped semiconductor layer (12) and the active region (13) ; and / or a thickness of the second doped semiconductor layer (12) , the active region and the first portion of the first doped semiconductor layer is smaller than a diameter of the layer stack bounded by the sidewalls; the contact layer (14) , in particular comprising a transparent conductive oxide is arranged on a central portion of the second doped semiconductor layer (12) opposite the active region (13) .

5. Optoelectronic device according to any of the preceding claims, wherein the buried contact structure (40) extends from a recess in the dielectric material layer (20) , through the optional dielectric layer (15) into the second portion of the first doped semiconductor layer (11) ; optionally the buried contact structure (40) comprises beveled sidewalls with a decreasing diameter towards the emission surface (110) .2024PF004976. Optoelectronic device according to any of the preceding claims, wherein the contact structure (40) laterally surrounds the layer stack at a position that is outside of a projection of the beveled sidewalls (200) of the buried dielectric material layer (20) onto the emission surface (110) ; and / or the contact structure (40) is laterally placed at positions between neighbouring pixels in a periodic manner outside of a projection of the beveled sidewalls (200) of the buried dielectric material layer (20) onto the emission surface (110) .

7. Optoelectronic device according to any of the preceding claims, wherein a projection of the beveled sidewalls (200) of the conductive and in particular reflective layer (21) onto the emission surface (110) is laterally distanced from a projection of the sidewalls (16) extending substantially perpendicular to the emission surface (110) onto the emission surface (110) and particularly comprises a larger diameter.

8. Optoelectronic device according to any of the preceding claims, wherein the conductive and in particular reflective layer (21) overlaps with the buried contact structure (40) vertically separated by a portion of the dielectric material layer (20) .

9. Optoelectronic device according to any of the preceding claims, wherein the beveled sidewalls (200) comprises at least two different angles in a portion laterally distanced from a projection of the sidewalls (16) extending substantially perpendicular to the emission surface (110) onto the emission surface (110) and particularly comprises a larger diameter.

10. Optoelectronic device according to any of the preceding claims, wherein a shape of a projection of the beveled sidewalls (200) onto the emission surface (110) and / or a projection of the sidewalls (16) onto the emission surface (110) comprises one of: a square;2024PF00497 a rectangle; a hexagon; a circle; and a square with rounded corners .

11. Optoelectronic device according to any of the preceding claims, wherein the out coupling structure (50) comprises the same material as the first doped semiconductor layer (11) ; the out coupling structure (50) extends on the emission surface (110) to a position above the buried contact structure (40) surrounding the layer stack; and / or the out coupling structure terminates at an edge of the buried contact structure (40) , such that the buried contact structure (40) optionally acts as a light reflecting element.

12. Optoelectronic device according to any of the preceding claims, wherein the out coupling structure (50) comprises at least one of: a micro lens; a DBR layer structure; a periodic structure with a periodicity smaller than a lateral dimension of a diameter of a projection of the layer stack onto the emission surface (110) ; a photonic crystal.

13. Optoelectronic device according to any of the preceding claims, further comprising a metallic contact plug (63) that contacts the buried contact structure (40) through the first doped semiconductor layer (11) , wherein optionally the metallic contact plug (63) is separated from conductive reflective layer (21) by the dielectric material layer (20) .

14. Optoelectronic device according to any of the preceding claims, further comprising a metallic contact plug (61) that contact the buried contact structure (40) through dielectric material layer (20) .2024PF0049715. Optoelectronic device according to any of claims 13 to 14, further comprising a circuit layer, particular including one or more CMOS circuit elements having at least two contact areas, said contact areas (62) connected to contact layer (14) via the conductive reflective layer (21) and to the buried contact structure (40) via the contact plug (61, 63) .

16. Optoelectronic device according to any of the preceding claims, further comprising a conversion material, wherein the conversion material is arranged on the emission surface, with optionally the out coupling structure (50) arranged on the conversion material; and / or the conversion material is arranged in the out coupling structure (50) ; and / or the conversion material is arranged in a recess in the first doped semiconductor layer (11) , a surface of the conversion material opposite a bottom of the recess forming the emission surface ( 110 ) .

17. Pixel array comprising: at least three optoelectronic devices according to any of the preceding claims, wherein at least two of the three optoelectronic devices comprise a conversion material; wherein an emission area of the optoelectronic devices configured to emit light in the green portion of the visible spectrum is larger than an emission area of the two other optoelectronic devices.

18. Method for processing an optoelectronic device, comprising the steps of :Providing a layer stack on a carrier growth substrate (100) , the layer stack comprising o A first doped semiconductor layer (11) arranged on the growth substrate (100) ; o an active region (13) arranged on a side of the first doped semiconductor layer (11) opposite the growth substrate (100) ;2024PF00497 o a second doped semiconductor layer (12) arranged on the active region (13) ; o an optional contact layer (14) arranged on the second doped semiconductor layer (12) opposite the active region ( 13 ) ; structuring the layer stack to provide sidewalls (16) extending substantially perpendicular to the growth substrate (100) from the second doped semiconductor layer (12) onto a first portion of the first doped semiconductor layer (11) , wherein a second portion of the first doped semiconductor layer (11) extends laterally from the sidewalls (16) ; forming a contact structure (40) partially into an area of the second portion of the first doped semiconductor layer (11) laterally displaced to the sidewalls (16) of the layer stack; depositing a dielectric material layer (20) that is transparent to light generated in the active region in operation of the device on a surface of the layer stack, the second portion of the first doped semiconductor layer (11) and the contact structure; forming beveled sidewalls (200) of the dielectric material layer (20) and an opening (22) through the dielectric material layer (20) thereby exposing a portion of the second doped semiconductor layer (12) ; depositing conductive and in particular reflective layer (21) on the beveled sidewalls (200) contacting the contact layer (14) through the opening (22) ; rebonding the structured layer stack to a substrate and removing the growth substate (100) to expose a surface of the first doped semiconductor layer (11) ; providing an out coupling structure (50) located above the structured layer stack.

19. Method according to claim 18, wherein the step of structuring the layer stack comprises the step of depositing, particularly by ALD, a dielectric layer on the sidewalls and the second portion of the first doped semiconductor layer (11) .2024PF0049720. Method according to any of claims 18 to 19, wherein the step of depositing conductive and in particular reflective layer (21) comprises the step of :Structuring the deposition of the conductive and in particular reflective layer (21) such that an area above the contact structure (40) is free of material of the conductive and in particular reflective layer (21) ; and optionally further comprising: o depositing a conductive contact plug (61) in said area through an opening in the dielectric material layer (20) .

21. Method according to any of claims 18 to 19, wherein a projection of the beveled sidewalls (200) of the conductive and in particular reflective layer (21) onto the emission surface (110) is laterally distanced from a projection of the sidewalls (16) extending substantially perpendicular to the emission surface (110) onto the emission surface (110) and particularly comprises a larger diameter; and / or wherein the beveled sidewalls (200) comprises at least two different angles in a portion laterally distanced from a projection of the sidewalls (16) extending substantially perpendicular to the emission surface (110) onto the emission surface (110) and particularly comprises a larger diameter.

22. Method according to any of claims 18 to 19, wherein the step of providing an out coupling structure (50) located above the structured layer stack comprises the step of:Depositing a conversion material on the surface of the first doped semiconductor layer (11) and providing the out coupling structure (50) on the conversion material; and / or Depositing a conversion material in the out coupling structure ( 50 ) ; and / orForming a recess into the first doped semiconductor layer, and arranging the conversion material in the recess.

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