Memory block structure and semiconductor device

Abstract

A memory block structure comprising: a plurality of memory blocks configured to store data of at least part of a graph or other non-linear data model as one or more linear data structures; a plurality of local controllers, each local controller associated with a corresponding memory block and configured to search and / or retrieve data of the graph or other non-linear data model by navigating the one or more linear data structures, wherein the linear data structure comprises a head node and a plurality of nodes each represented by at least a reference to a head node of the linear data and a reference to a further node of the plurality of nodes.

Description

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[0003] Memory Block Structure and Semiconductor Device Field

[0004] The present invention relates to a memory block structure and semiconductor device comprising the memory block structure and related methods.

[0005] Background

[0006] Conventional relational databases store data in tables. Each row has a unique ID, and each column a unique attribute. A model is used to represent data and their relationships. An issue with conventional relational databases is that they may not be optimized for storing certain types of data.

[0007] A graph database is a database that is based on graph theory. It stores data in terms of their connections. The standard way of performing computation on graph database workloads is to use standard memories and resolve any graph-related issues in software. This may lead to slow processing speeds and high energy costs, encapsulated in inflexible commercial packages, such as large GPUs.

[0008] Summary

[0009] According to a first aspect, there is provided a memory block structure comprising: a plurality of memory blocks configured to store data of at least part of a graph or other non-linear data model as one or more linear data structures; a plurality of local controllers, each local controller associated with a corresponding memory block and configured to search and / or retrieve and / or store and / or perform a data operation for data of the graph or other non-linear data model by navigating the one or more linear data structures.

[0010] The one or more linear data structures may comprise a linked list data structure. The graph or other non-linear data may comprise an infinitely-labellable graph structure. The one or more linear data structures store information to reconstruct said graph structure. The properties of the linear data structure and / or linked list may determine its configuration in physical memory.

[0011] The linear data structure may further comprise or represent property information for nodes and / or edges. The linear data structure may comprise further properties, for example, edge weights, confidence and / or a measure of attention focus.

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[0014] The data of at least part of a graph or other non-linear data model may be mapped to the linear data structure.

[0015] The memory block may comprise of form part of a supercluster. A supercluster may comprise a memory block of the plurality of memory blocks together with the associated circuitry.

[0016] The memory block structure of any preceding claim, wherein the one or more linear data structures may comprise at least a first and second linked data structure, wherein the first and second linear data structures are linked and / or have a common head node and / or a further common node.

[0017] The linear data structure is formed by a plurality of data objects, wherein each data object is configured to equally represent a vertex or an edge or a label of the underlying nonlinear data structure.

[0018] The one or more linear data structure may comprise a first linear data structure and one or more subordinate linear data structures. The first linear data structure may refer to a head of a subordinate linear data structure.

[0019] Each linear data structure may be navigable in a single direction.

[0020] The linear data structures may comprise a plurality of nodes each represented by at least a reference, for example, a memory pointer, to a head node of the linear data structure and a reference to a further node of the plurality of nodes.

[0021] The linear data structures may comprise a plurality of nodes each represented by at least a reference, for example, a memory pointer, to a head node of the linear data structure and a reference to a subsequent or previous node of the plurality of nodes.

[0022] The one or more linear data structures may represent edge and vertex information, optionally associated label information, of at least part of the graph or other non-linear data model.

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[0025] Each of the local controllers may be configured to perform graph or other non-linear data operations, for example, graph traversal, by navigating the one or more linear data structures, optionally in a single direction.

[0026] The plurality of local controllers may be configured to perform data operations independently of other controllers and / or perform parallelised searching of the plurality of memory blocks.

[0027] The graph or other non-linear data model may represent data as a plurality of vertices connected by edges, optionally directed edges, optionally with associated label information, wherein each vertex and graph and optionally each label is represented as a node in the linear data structure

[0028] The graph or other non-linear data model may be mapped to the linear data structures and / or wherein each vertex, directed edge and associated label of the graph or other non-linear data model is mapped to a respective node of the linear data structure.

[0029] The graph or other data structure may comprise a source vertex and a destination vertex joined by a labelled directed edge, wherein each of the source vertex, destination vertex and labelled directed edge are represented by respective nodes in the linear data structure.

[0030] The graph or other non-linear data model may comprise an infinitely label-able graph.

[0031] At least one of the linear data structures comprises a first node representing a label, for example, for an edge or vertex, and a second, linked node, representing a second label for the first label.

[0032] Each edge, vertex and label of the graph and / or non-linear data model may be represented by and / or is mapped onto a common node data structure.

[0033] The common node data structure may comprise a plurality, optionally at least six, optionally eight, variables representing a memory address of another node or data.

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[0036] The node may form part of a chain having a head, and each node of the chain incudes head information for the head of the chain.

[0037] The node data structure may comprise at least two navigation pointers. The controller may be configured to use said navigation pointers to navigate from one end of the linear data structure to the other. The controller may be configured to use said navigation pointers to navigate from a head of the linear data structure to the end. The navigation pointers may comprise a pair. The navigation pointers may comprise a first pointer to a head of the linear data structure and a second pointer to a next node of the data structure.

[0038] The node data structure may comprise at least two content pointers. The content pointers may point to content or items. The content pointers may include label and destination vertex identification pointers. The content pointers include a pointer to identify the destination vertex of the node and to identify the edge of the node. The content pointers for a single node may comprise both edge and vertex information.

[0039] The node data structure may comprise at least two subordinate pointers. Each pointer may point to part of a secondary or subordinate linear data structure. The subordinate pointers may point to further nodes associated with properties of the content pointed to by the content pointers.

[0040] The nodes of each linear data representation may be stored in a pre-determined order. One or more of the pointers may be represented as binary numbers, optionally binary natural coded numbers. One or more pointers, for example the content pointers, may be concatenated into a single number, in size order. The nodes may be stored using the concatenated number.

[0041] Each node may represent an edge and associated vertex, for example, a destination vertex, of the non-linear graph model.

[0042] Each local controller may be configured to perform at least one of: direct memory read, associative read, write, counterpart search.

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[0045] Each memory block comprises a plurality of nodes of the linear data structure. The plurality of nodes may comprise any suitable number of nodes. The plurality of nodes may comprise, for example, 64, 128, 256 or 512 nodes.

[0046] The linear data structure may be formed from a plurality of nodes, wherein at least one of the linked nodes is a first node representing part of a primary graph, wherein the first node is linked to a copy of the first node that represents part of a secondary graph.

[0047] The linear data structure may be formed from a plurality of nodes, wherein at least one of the linked nodes represents part of a primary graph, wherein the first node is linked to a copy of the first node forming part of a secondary graph, wherein the first node is part of a first linear data representation and the second node is part of a second linear data representation.

[0048] Properties associated with a part of, for example, a node of a first linear data structure may be represented in one or more further linear data structures.

[0049] The graph structure or other non-linear data model represents a plurality of linked graph layers, wherein each layer of the plurality of linked graph layers is mapped on to a plurality of linear data representations.

[0050] Each memory block may comprise a plurality of memory cell devices configured to store binary information, wherein the plurality of memory cell devices together store pointers or memory addresses to form the linear data structure.

[0051] Each memory block structure may comprise a plurality of contiguous memory cell devices. The binary information for each node may be stored in a plurality of contiguous memory cell devices.

[0052] Each memory block may be arranged to store pointers of the same type together. Each memory block may comprise a plurality of arrays for storing pointers, where each array is configured to store pointers of the same type.

[0053] One or more nodes of the linear data structures may represent and / or reference to one or more executable instructions and / or part of instructions, wherein the controller is

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[0056] configure to navigate the one or more linear data structures to obtain one or more instructions and execute said one or more instructions.

[0057] The memory block structure may be implemented as associative memory. The memory block structure may comprise one or more associative memory chips or modules.

[0058] The one or more linear data structures may store semantic information. One or more nodes may represent a semantic object and / or associated information and / or a reference to a semantic object and / or associated information.

[0059] The structure may comprise a first linear data structure and a second linear data structure, the first and second linear data structures comprising one or more linked nodes, wherein the first linear data structure represents first semantic information and the second linear data structure represents second semantic information independent of a context of the first semantic information. The linked nodes may comprise a node of the first linear data structure that comprises a reference and / or pointer to a node of the second linear data structure.

[0060] Information for a first object may be stored as data and / or as a memory reference in a first linear data structure, and information associated with said object or a property of said object may be stored as data and / or a memory reference in a second linear data structure, wherein the second linear data structure is linked with and / or navigable from the first data structure and / or wherein the first linear data structure is linked with and / or navigable from the second linear data structure.

[0061] Data may be stored in said model in accordance with a semantic data model, optionally wherein the sematic data model comprises one or more of: a cognitive data model, a hierarchy-based taxonomy model, an attention based cognitive model.

[0062] The memory block structure of any preceding claim, wherein data is retrieved from said semantic data model using one or more pre-determined queries, wherein the queries comprise one or more of: content addressable read operations, address addressable read operations, comparison operations, buffer control, programming, buffer clear and counterpart operations.

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[0065] The graph structure or other non-linear data model may represent a plurality of linked graph layers, wherein each layer of the plurality of linked graph layers is mapped on to a plurality of linear data representations.

[0066] The cognitive model may be an attention-based model. The linear data structures may represent a plurality of concepts as corresponding head nodes and relationship information between said concepts may be represented by further nodes in the one or more chains. The one or more nodes may represent activation information.

[0067] A node, optionally all nodes, of the at least one linear data structure may comprise one or more pointers to one or more data objects or structures, optionally stored on a further memory resource provided externally to the memory block structure, further optionally provided on a further memory resource, for example, a networked resource.

[0068] The memory block structure may be provided on one or more first memory devices and may store memory references to data objects stored on one or more further memory resources.

[0069] A node, optionally all nodes, may comprise a pair of content pointers each represented as a corresponding pair of binary natural-coded numbers or other binary-coded decimal, wherein each node is assigned a number formed by concatenation of said pair of binary natural-coded numbers.

[0070] The nodes may be sorted and / or stored based on the assigned concatenation number. The nodes may be stored on a memory resource in a pre-determined order based on the concatenation number, for example, size order.

[0071] At least one node, optionally each node may comprise a pair of memory references to a respective pair of associated data items, wherein the structure comprises at least one of:

[0072] a) one or more nodes comprises a pointer to a node of further linear data structure having a node representing further properties of at least one of the respective pair of associated data items;

[0073] b) the pair of pointers point to a node of a further linear data structure corresponding to at least one of the pair of associated data items.

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[0076] Each linear data structure may represent semantic information related to a semantic object. The associated pair may represent a data item and a corresponding property of the data item. The further linear data structure of option a) may represents context dependent properties of the data item and / or its property. The further linear data structure of option b) may represents context independent properties of the data item and / or its property.

[0077] According to a second aspect, there is provided a semiconductor device comprising a non-transitory memory resource comprising and / or formed by the memory block structure of the first aspect.

[0078] In accordance with a third aspect, there is provided a memory block structure comprising: a plurality of memory blocks configured to store data of at least part of a graph or other non-linear data model as a plurality of nodes, wherein the graph or other non-linear data model comprises edges connecting vertices, wherein each edge has an associated vertex, for example, a destination vertex, wherein each node represents the edge and the associated vertex.

[0079] According to a further aspect, there is provided a data structure for storing data of at least part of a graph or other non-linear data model, wherein the data structure comprises a plurality of nodes, each node representing edge-vertex pairs of the graph or other nonlinear data model as a linear data representation or a linked list.

[0080] According to a further aspect, there is provided a method of obtaining or storing data from a memory block structure, wherein the memory block structure comprises a plurality of memory blocks configured to store data of at least part of a graph or other non-linear data model, the method comprising: searching and / or retrieving data of the graph or other non-linear data model or storing data of the graph or other non-linear data model by navigating the one or more linear data structures of the memory block structure.

[0081] The method may comprise performing, by the plurality of controllers, a first search or other data operation on the plurality of memory blocks and performing a second search or other data operation by one or more of the controllers on one or more of the memory blocks based on the results of the first search. The second search or data operation may be performed on fewer of the memory blocks that the first search. The second search or

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[0084] data operation may be performed on memory blocks identified during the first search or data operation.

[0085] The first search or other data operation on the respective memory blocks may comprise navigating the plurality of linear data representations. The second search or other data operation may comprise navigating one or more, optionally a subset of the plurality of linear data representations. The subset may be selected based on the first search or data operation.

[0086] According to a further aspect, there is provided an apparatus that comprises one or more memory devices in accordance with the first aspect, together with a further external memory resource, wherein the memory device comprises one or more memory references to the further memory resource.

[0087] Features of one aspect may be provided as features of any other aspects. For example, features of the devices of the first, second, third and fifth aspect may be provided as features of the method and vice versa.

[0088] Brief Description

[0089] Figure 1(a) depicts a graph structure and Figure 1(b) depicts a data representation of a graph structure;

[0090] Figure 2(a) is an illustration of part of a linear data representation, in accordance with an embodiment, Figure 2(b) depicts part of a graph structure; Figure 2(c) depicts a head node of the linear data representation; Figure 2(d) depicts a further illustration of the linear data representation; Figure 2(e), 2(f) and 2(g) depict further illustrations of the linear data representation;

[0091] Figure 3 is a schematic diagram of a memory block structure, in accordance with an embodiment;

[0092] Figure 4(a) is an illustration of a first representation of example data as a graph structure; Figure 4(b) is an illustration of a second representation of the example data in accordance with an embodiment, and Figure 2(c) is an illustration of a further representation of the example data;

[0093] Figure 5 is a further illustration of the linear data representation, in accordance with an embodiment;

[0094] Figure 6(a) is an illustration of a first representation of further example data as a graph structure; Figure 6(b) is an illustration of a second representation of the further example

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[0097] data in accordance with an embodiment; Figure 6(c) is an illustration of a further representation of the further example data in accordance with an embodiment and Figure 6(d) is an illustration of a further representation of the further example data in accordance with an embodiment;

[0098] Figure 7 is an illustration of a linear data representation of yet further example data in accordance with an embodiment;

[0099] Figure 8 is a circuit diagram of a memory block structure, in accordance with an embodiment;

[0100] Figure 9 is a table of data operations, in accordance with an embodiment.

[0101] Figure 10 is an illustration of an example data operation;

[0102] Figure 11 depicts a further graph structure;

[0103] Figure 12 depicts an example of a content addressable read;

[0104] Figure 13(a) depicts a memory block structure, in accordance with an embodiment and Figure 13(b) depicts a memory block structure, in accordance with a further embodiment; Figure 14(a) depicts an example of a representation of data using a number of linear data representation and Figure 14(b) depicts a further example;

[0105] Figure 15 depicts a further example of data represented using the linear data representation.

[0106] Detailed Description

[0107] The following described embodiments relate to a memory block structure forming part of a computer architecture. The memory block structure allows for infinitely labellable graph support. The following embodiments relate to a computer architecture for arranging data on physical hardware.

[0108] Specifically, the memory block structure allows for the mapping of an infinitely labellable graph on to a hardware substrate which may be substantially homogeneous. The embodiments described herein may offer faster processing times, for example, for information retrieval and searching of databases. In addition, further advantages relating to improved power dissipation may be achieved.

[0109] Graphs are mathematical structures used to model pairwise relations between objects. A graph in this context is made up of vertices which are connected by edges. Terminology for graphs can vary. Vertices may alternatively be referred to as nodes or points. Edges may alternatively be referred to as arcs, links or lines. A distinction can be made between undirected graphs, where edges link two vertices symmetrically, and

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[0112] directed graphs, where edges link two vertices asymmetrically. The direction of an edge can be indicated graphically by an arrow.

[0113] Figure 1(a) illustrates a standard graph relation between two vertices. The graph relation is directed from a source vertex 102 to a destination vertex 104 by an edge 106. The edge is represented graphically by a directed arrow. The edge may be a directed edge. In Figure 1(a) the edge 106 is labelled by label 108. The graph data model therefore represents a plurality of data and the relationships between said data using vertices and edges. For brevity, Figure 1(a) may be referred to as “graph view”.

[0114] Figure 1(b) corresponds to a data representation of the graph relationship of Figure 1(a). In Figure 1(b), the source vertex 110, the destination vertex 112 and the label 114 are represented inside boxes. The boxes in Figure 1(b) represent that each of these objects can be stored in a memory and in a data representation is a reference to a data address. The source vertex is connected to information on the edge label and the destination vertex by two arrows 116, 118.

[0115] Without being bound by theory, an infinitely labellable graph is a graph that can be described using the following information: source vertices, edges, destination vertices, any labels for each edge and destination (and source) vertex and then labels for those labels. To describe a single vertex in a graph structure, the following information for that vertex is required: vertex information about the vertex itself, edge information for every edge the vertex is connected to, vertex information for every destination vertex of every edge, and label information for labels of any edges and vertices.

[0116] Figure 2 represents an alternative data structure for a memory block structure, in accordance with an embodiment. The data structure may be referred to as node structure for representing a more general concept of what is referred to as a node. A node in this context is to be understood as a separate concept to that of a node of a graph. “Node” in the context of a graph may be used as an alternative term for a vertex. In the current context, node is used to refer to a constituent part of a larger linear data structure that represents the abstract concept of a graph. In the present embodiment, the node may represent an edge-destination vertex pair. The node may alternative be described as a constituent data structure. The node may also include pointers to further nodes that represent labels or label information associated with the edge and destination vertex. In

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[0119] some embodiments, a node may represent, a vertex of a graph, an edge of a graph or even a label or property of either the vertex or graph. The labels may be represented as ‘edge-destination vertex’ pairs that emanate from the item that they label. For example, the label may treat the edge of the vertex that they describe as a head node. For brevity, Figure 2 may be referred to as chain view. Nodes may alternatively be referred to as a linknode.

[0120] In accordance with embodiments, a node (of the linear data structure) is a group of at least six pointers or other references to a memory address. A pointer will be understood as an object that stores a memory address. The pointer is represented by memory words of a fixed length, each word being represented by underlying binary information stored in memory cells. As such, the node can be considered to be part of a data representation that is stored in memory cells. A pointer can be understood as simply a number or other suitable string format.

[0121] Figure 2(a) represents a node data structure that has at least six pointers, each represented in a number format, in accordance with embodiment. The node may also be referred to as a linknode, or simply as a link.

[0122] As described in the following, the node data structure is a constituent part of a linear data representation for a graph model or other non-linear data model. In the present embodiment, the linear data representation is a linked list representation in which at least some of the pointers of the nodes allow for the nodes to form a linked list. The linear data representation comprises a representation in which data elements or objects is ordered by each data element or object of the list pointing to the next object or element in the list. In the following embodiments, the linear data representation is also referred to as a chain made up of nodes. In the present embodiment, the linear data representation has a linked list structure, as described below.

[0123] The pointers are indicated by their name inside a bevelled rectangles. Each pointer is capable of being stored in memory. The six pointers are associated to a common address, referred to as the link or node address 202. The link address is not physically represented in memory, hence the different shape (oval).

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[0126] In some embodiments, a pointer to a node may mean that the pointer represents a record of the address (either physical, hashing or other forms of rapid lookup tables) of a node, so that hardware, for example, the controller described below, may quickly find the corresponding node.

[0127] In the present embodiment, the node structure has the following memory pointers: head ID, next node, primIDI, primlD2, sub1 and sub2. Each of these pointers is described in the following and may be referred to as navigation pointers, content pointers and subordinate pointers. In the present embodiment, the node structure allows for storage of a pair of navigation pointers, content pointer and subordinate pointers. In some embodiments, the node structure has further pointers, for example, a pair of miscellaneous pointers.

[0128] Each node has at least two navigation pointers. These pointers allow navigation from one end of the chain to the other end of the chain. In the present embodiment, each node has a pair of navigation pointers.

[0129] The first navigation pointer is “head ID” 204. Head ID is a pointer to the memory address of the head node of the chain to which the node belongs. Rather than point to a previous node in the chain, each node in the chain has a pointer to the head of the chain.

[0130] By including head information in each node (i.e. via the headID) the system can find the start of the chain in a single step no matter where in the chain the node is located. For example, the system can find the start of the chain independently of the origin of an earlier search. As an example, if we search for “fur” and it is the 75thitem in the chain “cat”. To determine “What has fur?” the head node of the chain “cat” must be returned. That operation can be completed in a single step.

[0131] In other embodiments, the headID may point to the "previous node" of the chain. In embodiments, the headID points to a previous or next node of the chain

[0132] The second navigation pointer is “next node” 205. Next node is a pointer to the memory address of the next node of the chain.

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[0135] The navigation pointers allow the system to traverse the linked list. Queries such as what are all the edges connected to a vertex can be answered efficiently.

[0136] In other embodiments, the next node pointer may instead point to a preceding node in the chain.

[0137] Each node also has a pair of content pointers. The content pointers include label and destination vertex identification pointers. The content pointers include a pointer to identify the destination vertex of the node and to identify the edge of the node (i.e. the edge connected the source vertex to the destination vertex). In the present embodiment, the edge ID pointer is stored as “primIDI” 206 and points to the edge and “primlD2” 208 points to the destination vertex ID. As such the node data structure provides a symmetric representation in that the node does not distinguish between an edge and a destination vertex and instead includes information on both.

[0138] In embodiments, the content pointers can be considered to form a pair of associated data items. For example, the content pointers may point to or represent a first data item and a second associated data item. The specific type of data stored will be dependent on the implementation. However, without limitation, the second data item may represent an identifier or qualifier or property of the first data item. It will be understood that any semantic data or information that can be stored using vertices and nodes can be stored or referenced by the content pointers.

[0139] The node also includes two further pointers “sub1” 210 and “sub2” 212. These are examples of subordinate pointers. The subordinate pointers point to part of subordinate chains. These can be considered as properties of the items that the content pointers (prim I Ds) point to. Those items may be referred as labels but it will be understood that the actual label is one of their properties. For example, “English graphical representation - ‘cat’” corresponds to a chain representing cats is represented in English by writing the word ‘cat’.

[0140] Figure 2(b) illustrates a simple example of part of a graph structure to illustrate the content pointers. The vertex (in this example, labelled head ID) has an edge (labelled primIDI) pointing to destination vertex (primlD2). In this example, fora node representing

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[0143] the vertex, the number for the edge is stored as “primIDI” and the number of the destination vertex “i” is stored as primlD2.

[0144] If a vertex (referred to as A) points to two vertices i and j, then 2 nodes are included in the chain of A. The node for vertex i points to the head of the chain of i via primID. The node for vertex j points to the head of the chain forj via primID. These will be understood as two independent chains with separate heads. In such a way, the non-linear graph representation is represented by more than one linear representation.

[0145] To provide context-specific information, for example, information regarding how i and j behave “within the context of A”, subordinate pointers can be used to point to new nodes that describe these properties. These new nodes are not directly connected to or owned by the independent chains of i and j. Instead, these nodes exist only within the context of A’s independent chain.

[0146] In embodiment, in which a head node has more than one destination vertex (in the graph view), each vertex has a corresponding chain in the chain view. As such, the find specific content, (for example, “colour” of “fur” of a “cat”), the processes under such data structures use short steps of queries, instead of storing variable lengths of paths, thus simplifying storage and operator representations.

[0147] Figure 2(c) represents a data structure of a head node, in accordance with an embodiment. This represents a “head node”, leading a chain within the said graph database. It shares the same hardware and graphical structure with Figure 2(a). In this embodiment, primIDI, primlD2 and sub2 are set to null (and therefore omitted here). Within head nodes, the head IDs point to its own link address, as denoted in the figured with a dashed arrow. This self-referential feature distinguishes head nodes from link nodes. The "head ID" number 230 is set to NULL, showing that this is a chain head. The head node has a "next node" 236 as described with reference to Figure 2(a). Head properties 234 refer to other properties of the head node. With reference to Figure 2(a), a head node may be constructed as: "head ID"=NULL, "primIDI" simply stores its own link address, so it points to itself, "primlD2"=NULL, "sub1"="sub2"=NULL, in the present embodiment. " Next node" points to the next node in the chain.

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[0150] Other options may be possible, such as both primIDs = NULL and head=<self>, but because the accelerator is highly optimised to search primIDs, the most efficient way of encoding the head node is as given here. To find the head node of a chain, a CAR2 operation for [<cue>, NULL], can be used where <cue> is the item whose head we are looking for. <cue> may be a primID obtained from a previous operation.

[0151] A summary of the pointers / identifiers in accordance with an embodiment is provided in Table 1.

[0152] Type Identifier Usage

[0153] Content C1. C2 Label node and to node ID

[0154] Navigator NLN2 Head node ID and next node address Subordinate SI. S2 Premises and suboperations

[0155]

[0156] Miscellaneous Ml. M2 Node properties

[0157] Table I. GDB entry usage allocation.

[0158] As a non-limiting example, "headJD" might point to the concept (represented as a node) of "chicken soup", primIDI may point to the concept of "has" and primlD2 may point to the concept of "chicken". Sub2 may point to the fact that "chicken" in the context of chicken soup may have further properties such as "is - fried" etc. The "is -fried" relation would be represented by the node that sub2 points to. Thus in this example we have a chain head that establishes that "this chain is about 'chicken soup'" and the node being examined says: "[chicken soup] has - chicken" and "the aforementioned chicken has further properties, please consult the node that 'sub2' points to for further details".

[0159] Figure 2(d) represents an example of a node representation including subordinate properties. The “graph-view” of Figure 2(d) is a vertex representing the name “Bob” having an edge called “know” and a destination vertex called “Alice”. Together the graph representation of vertex, edge and destination vertex represent the concept “Bob knows Alice”.

[0160] In the chain representation (chain view) the vertex called “Bob” is represented by a first node (at link address 77), the edge called “know” is represented by a second node (at link address 27) and the destination vertex called “Alice” is represented by a third node (at link address 99).

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[0163] With regard to the Bob node, this node has pointers as described with reference to Figure 2(a). The node has the following pointers: headID 252, primIDI 254, primlD2256, sub1 258, sub2260, next node 262. The node has a link address 264.

[0164] As can be seen each pointer of the node points to an address (represented by an integer). In further detail, headID is a pointer to the concept “Bob”. PrimIDI is a pointer pointing to address 27. PrimID of the Bob node provides information that the vertex Bob has an edge called “know” with link address 27.

[0165] Similarly, primlD2 of the node points is address “99” and provides us the information that vertex " Bob" has a destination vertex called “Alice” with address e.g. 99. Together primIDI and primlD2 are linked as a pair, allowing the retrieval of information that vertex " Bob" has an edge called "know" with address 27 that points to destination vertex called " Alice" with address 99, i.e., " Bob knows Alice".

[0166] In the present embodiment, “sub1” is a pointer to the next item in the chain that contains subordinate or local properties of the edge label. Sub2 is a pointer to the destination vertex label. In the present embodiment, “sub1” is a pointer to the next item in the chain that contains subordinate or local properties of the destination vertex. In the present embodiment, “sub2” is a pointer to the next item in the chain that contains subordinate or local properties of the edge label.

[0167] In this example, sub1 points to a further node and sub2 points a second further node. In this example, sub 1 points to a node representing the edge label and sub2 points to a node representing the “head-primlD1” connection label.

[0168] The Bob node has two subordinate pointers. Sub1 (which is associated with primIDI ("know")) points to a node at address 37 with the contents (represented in the same node language) "3 years of time". Sub 2 (associated with primlD2) (" Alice") points to address 38 "connection weight 60". Altogether, this reconstructs a preposition that Bob knows Alice for 3 years, with their relationship weight equals to 60. Note that in other embodiments the connection weight may be a universal property and stored in M2 instead. Note that in this example an explicit mapping using subordinates is used. The set-up allows " Bob" to "know" other people with different connection weights.

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[0171] In some embodiments, further pointers may be included. These include a further pointer “sub3” (omitted in the figure) which is similar to sub1 and sub2, but rather than being associated with primIDI or primlD2 this pointer relates to information that belongs or is otherwise associated with the entire node. J. e. it is associated collectively with the whole node stored at location 77, as opposed to just the primIDs (27 and 99) individually. An example would be a node at location 101 with contents "confidence that this relation is correct" and "70%" as contents (not pictured).

[0172] In addition, the node may include a "bin" of properties. The format inside this is free and can store properties such as weight-of-primlD1 -connection etc. It is also in principle expandable. In the present embodiment, approach all fields have equal sizes (in fact we have 2x distinct "g" fields, 1x for primIDI and 1x for primlD2), but this need not necessarily be the case. The bin properties may also be referred to as M1, M2.

[0173] Figure 2(e) illustrates a first node representing a vertex. Figure 2(f) represents a second node representing a head node of a chain. Each node has the following memory pointers: head ID, next node, primIDI, primlD2. Not shown in Figure 2 are the subordinate pointers.

[0174] The node of Figure 2(e) is associated with a common address, referred to as the link or node address 2202a. The node has a pair of navigation pointers: first navigation pointer 2204a (headID) pointing to the memory address of the head node of the chain to which the node belongs. The vertex node has a second navigation pointer 2205a (next) which is a pointer to the memory address of the next node of the chain. The vertex node of Figure 2(e) has a pair of content pointers: first content pointer 2208a (primIDI) and second content pointer 2206a (primlD2). In the present embodiment, the edge ID pointer is stored as “primIDI” and points to the edge and “primlD2” points to the destination vertex ID.

[0175] The node of Figure 2(f) is associated with a common address, referred to as the link or node address 2202b. The node has a pair of navigation pointers: first navigation pointer 2204b (headID) pointing to the memory address of the head node of the chain to which the node belongs. The node has a second navigation pointer 2205b (next) which is a pointer to the memory address of the next node of the chain. In contrast to the node of Figure 2(e), the content pointers 2206a and 2206b are NULL.

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[0178] Figure 2(f) depicts a head node in its primitive version. No order is imposed on the other nodes. The head node can be considered as “the object at [link address] exists as an entity”. Practically, it acts as the origin of a chain. The headnode has the exact same structure as any other linknode; the difference is in its contents. Within headnodes exclusively: head ID points to its own address (link address) and both primIDs are empty (NULL). The headnode’s self-reference distinguishes it from linknodes as a discrete source vertex. Finally, we note that to end a chain, the final node’s next pointer to a specially chosen value that represents the end of chain (EOC). EOC defines the end point of a chain to effectively terminate traversal operations. Therefore, all chains are finite by the EOC and can be traversed in a linear fashion.

[0179] Without limitations, the structure of the node in the absence of sub-ordinate pointer may be referred to as a proto-linknode. Internally, a proto-linknode may be formatted as follows: [“source vertex”, “edge”, “destination vertex”, “next linknode”], abbreviated to:

[0180] [head ID, primIDI, primlD2, next], where primID stands for “primary ID”. As set out above, head ID corresponds to the “source vertex” whilst primIDI and primlD2 correspond to the “edge” and “destination vertex” respectively.

[0181] It will be understood that Figure 2(a) represents the node of Figure 2(e) with two additional sub-ordinate pointers, referred to as sub1 (or propl) and sub2 (or prop2). In the present embodiment, “sub1” is a pointer to the next item in the chain that contains subordinate or local properties of the edge label. Sub2 is a pointer to the destination vertex label. In the present embodiment, “sub1” is a pointer to the next item in the chain that contains subordinate or local properties of the destination vertex. The node structure may be formatted as follows: [“source vertex”, “edge”, “edge properties”, “destination vertex”, “destination vertex properties”, “next linknode”], abbreviated to: [head ID, primIDI, propl, primlD2, prop2, next], where primID stands for “primary ID” and “prop” for “properties”.

[0182] The subordinate pointers may be additional or auxiliary content pointers that enable recursive labellability. In embodiments, the pointers are numbers stored in a physical memory and each number corresponds to an address in memory. They point to further nodes that elaborate on the properties of primIDI and primlD2 within the context of the

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[0185] nodes triplet. This “context-dependent” versus “context-free” allows distinction between “a property of object X” and “a property of object X when it relates to Y via Z”.

[0186] Figure 2(g) represents the head node of Figure 2(f) with sub-ordinate pointers. In Figure 2(f), one of the sub-ordinate pointers 2212b is null, while the other pointer 2210b points to properties of the head node.

[0187] In the above described embodiments, primID can be considered to be an identifier number corresponding to a pointer. The pointer may point to an independent object (e.g., “that chestnut brown bird on this green tree”) or a concept (or class, “sparrow” and “camphor tree”). The primID may refer to a specific entity that’s described by its own linknodes, while the sub-ordinate pointers represent context-specific information. That context specific information may have no meaning outside the specific context of the relation being specified by the linknode. Thus objects may have the same processing level as classes, so as to avoid the scalability problem of recursive inheritances in GDB expressions. Uniform data structures may then be used to build up a knowledge graph with contextual descriptions. In further embodiments, the head node may be reserved for classes and all instance may be represented as sub-chains.

[0188] Figure 3 depicts a memory block structure in accordance with an embodiment, in which each memory block is configured to represent data of a graph or other non-linear data model as one or more linear data structures.

[0189] Figure 3 depicts a memory block structure having a number of memory blocks.. In the present embodiment, each memory block is configured to store data in a linear data structure. The linear data structure has a number of linked nodes having a node data structure described with reference to Figure 2. In Figure 3, each memory block is configured to store N nodes (in this embodiment, 2048 nodes). As described above, each node comprises 8 entries of 64 bit each. Each memory block has a local controller. The memory block 302 and local controller 306 may be collectively referred to as a leaf node.

[0190] Figure 3 depicts a first memory block 302. The first memory block 302 is configured to store data in N node data structures (represented by 304a,..., 304n). The first memory block 302 has a local controller 306. A second memory block 310 is also depicted together with its local controller 312. Each memory block may be referred to as a

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[0193] supercluster. In some embodiments, a supercluster refers to a functional until that includes one of the memory blocks and its local controller.

[0194] In total there are N memory blocks. The Nth node 314 is depicted together with its local controller 316. In the present embodiment, each memory block has N nodes as described for the first memory block. The memory block structure has a central controller 318 for coordinating signals between the nodes. The central controller is configured to send and receive signals to each local controller for each memory block. The central controller is coupled to an associated communication interface 320 to receive and send signals, for example, to a further processing resource (not shown).

[0195] In embodiments, the number of memory blocks (superclusters) can be varied and dependent on the hardware used. A physical chip may be made of more than one supercluster. In addition, while Figure 3 refers to a physical chip structure, it will be understood that a memory block structure may be shared over more than one physical chip, for example, a first plurality of memory blocks on a first chip and a second plurality of memory blocks on second chip.

[0196] Each local controller is configured to perform data operations by navigating the linear data structures stored in the nodes of their associated memory block. In some embodiments, the linear data structures are serially navigable in a single direction (i.e. from a head node of the list to an end of chain or tail node). In the other direction, from tail to head, the linear data structure may jump more than one node. The linear data structures represent or are a mapping of the graph structure and graph operations, such as traversal of the graph, can be performed by navigating the linear data structure.

[0197] Each local controller is configured to perform local data operations on their associated memory block independently of the other local controllers. For example, each local controller can navigate the nodes of the linear representations stored on the memory block independently of the controllers of the other memory blocks. Parallelised searching of the memory block is possible. As an example, a search instruction signal is transmitted from central signal controller 318 to each local controller and each local controller is configured to carry out the search on the associated memory block independently.

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[0200] The local controllers are configured to perform a number of data operations. The data operations include a direct memory read, an associative memory read, a data write or a counterpart search.

[0201] In this context, a direct memory read operation include retrieving content stored at an address of interest. An associative memory read operation includes retrieving a pointer. The associated memory read operation includes presenting a cue (query) to memory and the memory returns pointers to all locations in which the cue is found. These may be typically primID. A counterpart search data operation includes retrieving an address for a counterpart of an object. As an example, the counterpart search may include answering the query “where does the counterpart of the object pointing to address Y point to”). Other data operations include writing new values to memory.

[0202] In some embodiments, each memory block is formed using a number of memory devices grouped together. In general, the memory block is formed of a plurality of memory cells configured to store binary data. The memory cells are grouped together to store words of fixed length. In the present embodiment, the words are entries for the nodes.

[0203] Other configurations are possible. In some embodiments, the memory blocks may be arranged into groups with shared resources. In some embodiments, a plurality of associative memory devices or chips are arranged to store nodes. Pointers of nodes may be distributed across different memory cores of a memory chip.

[0204] In some embodiments, a known memory chip uses 8x memory cores of size 64x64 to store a total of 64 nodes. Each pointer is 64 bits long, each of the 8x memory cores stores 1 of the pointers in the node (so that an 8 pointer node is distributed across 8x memory cores taking a 64x1 slice of each). Together the memory chip stores 64 nodes. In such an embodiment, each memory block (of a super cluster) of Figure 3 corresponds to the memory chip and has associated processing circuitry. The memory cores may be alternatively referred to as a cluster and the memory block formed of a plurality of memory cores referred to as a supercluster.

[0205] In another embodiment, the memory block is formed from 8 cores, each having size 64x 2048, in which 20488-pointer nodes with 64 bits per pointer. In such an embodiment,

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[0208] each memory block of Figure 3 corresponds to or forms part of a super cluster and has associated processing circuitry in the form of the local controller.

[0209] In other embodiments, different numbers of cores may be combined in different combinations. As a further non-limiting example, a chip may include 8 cores, each having 512 nodes each having 8 pointers of 36 bits.

[0210] In some embodiments, each memory block is configured to store pointers of the same type together in arrays (for example, as shown in Figure 13(a)). Each memory block thus may comprise a plurality of memory arrays for storing pointers and each memory array is configured to store pointers of the same type. In such embodiments, the local controller communicates with each array.

[0211] In embodiments, the memory block structure is provided as part of a semiconductor device. The memory block structure can form part of a larger memory device. In embodiments, the semiconductor device comprises a non-transitory memory resource comprising and / or formed by the memory block structure described herein. The memory block structure may be formed a suitable hardware substrate, for example, a suitable semiconductor substrate.

[0212] The following comments relate to three non-limiting example searches of the memory block structure of Figure 3. In this example, the search is a search for a property (i.e. a related property) that is related to a primary concept. It will be understood that more complex search operations may be constructed.

[0213] At a first step, a global search is performed. This includes sending a first search query from the central controller 318 to the controller of each memory block. Each controller then independently performs a search for a match to the search query. In the present embodiment, the search for a match includes querying each node to find one or more matching nodes. One or more memory blocks then return a set of results in response to the first query. In the present embodiment, only a single memory block returns a match. For illustrative purposes this is memory block 302. The controllers respond to the central controller with a success or fail signal.

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[0216] At a next step, the chain to which matching node is identified. The identified chain is then traversed to find the related property. Information about the matching related property is then returned to the signal controller 318.

[0217] A second example of a search is now described. The second search is an example of a search for the related property of “production year” related to the primary concept of Tom Hanks.

[0218] As a first step, a first search for “Tom Hanks” is performed in the plurality of memory blocks. In this example, the specific association is not relevant. It may be that the search query returns results for [Tom Hanks: acted in] or [Tom Hanks: directed]. In a film database of suitable format finding this and then requesting the head node will return a list of films associated with Tom Hanks. The search returns an entry at address 777 in one of the plurality of memory blocks. The chain to which that node belongs is identified. In this example, the identified chain relates to the film “Bridge of spies” and that film happens to have 23 entries (i.e. is a chain of 23 entries) The chain of nodes may be distributed across more than one memory block. In this example, 22 of the nodes are in a first memory block (supercluster) 777 and the last node of that chain is in a different memory block (supercluster) 778.

[0219] A register, also referred to as a location of interest (LOI) register may record the identified chain so that the next query for the related concept “production year” is performed on the identified chain (i.e. on the 23 entries of the film).

[0220] The LOI register is a location of interest register and stored locally within a supercluster whether a CAR operation returned a valid result or not. The LOI is intermediate data stored within the supercluster, directly interpreted as priority-encoded search hits within a memory core, by a single query operation.

[0221] A further non-limiting example of a related search is provided. In this example, data for movies are stored in the memory block structure. A desired search is to find all films which an actor, in this example, Tom Hanks has acted in between 1990 and 2000. In this example, the search involves a global search across all memory block for " Tom Hanks", then a further local search to find the property "acted-in" and then navigate to each film. To obtain the data range, a counterpart operation can be found to check the

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[0224] year associated with each film result (specifically the counterpart of the "production-year" node can be used). By being able to perform simple operations at the edge, this means that each small chunk of memory, can perform simple operations independently of the rest of the system, as described above. The memory may massively parallelise the process of searching.

[0225] An example query is described. As a first step, a query is sent to every memory block. The instruction is sent to every memory block. This is clearly massively parallel.

[0226] Within each " Tom Hanks" node, all counterparts for edges called "acted-in" are found. This instruction is sent only to the memory block that contains the " Tom Hanks" head vertex. The memory block starts to independently traverse the graph searching (specifically the linear data structure representing the graph) for "acted-in" without further interference from the controller. The controller is then available to perform other tasks. This process then returns a set of films.

[0227] At the next step, the controller then searches for each film similar to the results from the first search. In further detail, each film is the head of a new chain, and its respective chain is searched. At the next step, the hit returns and the controller then asks for all counterparts of "production-year" edges. When the hits return the controller or the signal controller can locally make the comparison with the 1990-2000 range and stores those films that match.

[0228] The above process is to be contrasted with a regular database search, in which a database has a table column for "acted-in", almost removing the flexibility of working with inhomogeneous data (everybody needs an "acted-in" column or special arrangements must be otherwise made). The query for such columns is multiplied across the columns (acted-in-1, acted-in-2, acted-in-3,.. ) because the relational database paradigm generally forbids multiple entries with the same label and attempts to force uniformity.

[0229] As a result, the system should achieve both massive parallelism, speeding up the process and support flexible and irregular data, which should save memory space.

[0230] In summary the search described above includes the following steps:

[0231] 1) Search “Tom Hanks”. Finds chain head for the actor.

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[0234] 2) Search “acted in” within “Tom Hanks”. Finds all films he’s acted in.

[0235] 3) Search for head nodes of each film found in (2). Now all the films’ heads are marked in the database.

[0236] 4) Traverse all film chains and mark them for associative search. Now all the films’ entire chains are highlighted in the database.

[0237] 5) Perform associative search for “production year” in all highlighted chains (leaving the rest of the memory alone). Now all the answers have been marked and can be returned to the controller.

[0238] Figure 4 depicts a non-limiting example, of information stored in a graph structure (shown in Figure 4(a) in the graph view) and chain representation described above (Figure 4(b)). The information of the graph structure corresponds to the statement “This (object 0x00a) is a black naughty cat”.

[0239] As can be seen from Figure 4(a) the source vertex 402 has a memory address 0x00a and has three destination vertices: first destination vertex 404 - “black”; second destination vertex 406 - “naughty”; third destination vertex 408 - “cat”; There are three edges between the source vertex and the destination vertex each one is labelled with edge information: first edge label 410- “colour”; second edge label 412 - “temper”; third edge label 414 - “species”. The edge labels and corresponding destination vertex pairs specify properties of the object at address 0x00a. Specifically that the object has species=cat (first edge and vertex); colour=black (second edge and vertex) and temper=naughty (third edge and vertex). Figure 4(a) is to be understood as an example only of how graph structures can be used to represent information. Figure 4(a) and (b) represent "local properties". Local properties are to be understood as properties of entities within the context of a head node.

[0240] The chain representation of Figure 4(b) depicts the same information of Figure 4(a). The head node 416 corresponds to the source vertex and is a pointer to the memory address of the object at 0x00a. The first node 418 of the chain is “colour-black” corresponding to the first destination vertex and the label of the first edge. The second node 420 of the chain is “temper-naughty” corresponding to the second destination vertex and label of the second edge. The third node 422 of the chain is “species-cat” correspond to the third destination vertex and label of the third edge. The termination link of the chain is labelled “end of chain” or “EOC” and indicates that there are not further links.

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[0243] As a non-limiting example, in the chain representation of Figure 4(b), for the nodes within chain '0x00a' each node stores the following pointers:

[0244] 1st node @0x00a (head node): headID = 0x00a, primIDI = NULL, primlD2 = NULL, next node = 0x00b;

[0245] 2nd node @0x00b (1st link node, similarly hereafter): headID = 0x00a, primIDI = colour, primlD2 = black, next node = 0x00c;

[0246] 3rd node @0x00c: headID = 0x00a, primIDI = temper, primlD2 = naughty, next node = OxOOd;

[0247] 4th node @0x00d: headID = 0x00a, primIDI = species, primlD2 = cat, next node = OxOOe 5th node @0x00e: headID = 0x00a, all other IDs point to NULL.

[0248] In Figure 4(b), if a subordinate from "naughty" in 420 it means that "the chain emanating from this subordinate pointer will inform us about properties further specifying the meaning of 'naughty1within the context of the entity described by 0x00a. This extra information could be further nuances to the concept of "naughty" that apply to this particular cat.

[0249] The structure above is represented graphically in Figure 4(c), which depicts the chain having 5 nodes. Each node is represented by their associated node address: head node 452, second node 454, third node 456, fourth node 458 and fifth node 460. Each node is represented by their associated node address.

[0250] First node is a head node, and therefore its head pointer points to its node address 452. The first node has two NULL content pointers 454, 454. The next pointer of first node points to the node address of the second node 454.

[0251] The head pointer of the second node points to the node address of the first node 452. The next pointer of the second node points to the node address of the third node 456. The content pointers of the second node point to “colour” 464 and black 462.

[0252] The head pointer of the third node points to the node address of the second 454. The next pointer of the third node points to the node address of the fourth node 456. The content pointers of the second node point to “temper” 468 and “naughty” 466.

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[0255] The head pointer of the fourth node points to the node address of the third node 456. The next pointer of the fourth node points to the node address of the fifth node 460. The content pointers of the fourth node point to “cat” 458 and “species” 472.

[0256] The chain thus stores and represents semantic information. In this case the sentence “Object 0x00a is a naughty black cat” is represented and stored in the linear data structure. To make a query, the controller traverses the chain until a match is found. A complex graph reading operation is therefore converted into iterative chain node reading.

[0257] Figure 5 is an illustration of a linked node representation showing how a number of nodes link in a linked list form a linear node structure. Figure 5 illustrates how each item or object corresponding to a head ID has a number of properties and may be extended in an infinite fashion. It will be appreciated that shorthand version of the nodes is shown in Figure 5 for clarity. The chain is defined between a head node 502 and tail (or end of chain EOC node) 506. Between the head node and tail node are a number of intermediate nodes (504a, 504b,..., 504n). Figure 5 depicts how each node of a main (or first) linked list can form a head of a subordinate chain.

[0258] The head node is represented by “head ID”. The head node 502 may have one or more properties 508. Each intermediate node has a link address, as described with reference to Figure 2(a).

[0259] Each intermediate node has a number of secondary properties. The "label / dest ID" properties (514a, 514b,... 514n) each represent two head nodes, and these head nodes are pointed to by “primIDI" and "primlD2" of the node. The “label / dest properties” (512a, 512b,..., 512n) each represent nodes in sub-ordinate chains and are pointed to “sub1” and “sub2”.

[0260] Concretely, primIDI of node 504 points to a first head node and primlD2 points to a second head node where the first and second head nodes are represented by “label / destID”. “Sub1” points to a node in a sub-ordinate chain and “sub2” points to a node in another sub-ordinate chain, as described above.

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[0263] The arrows linking from a node to the next “link address” represent the “next node” variable of Figure 2(a). The backward connections from each link address to head ID are omitted to avoid clutter but it will be understood that each node include the next node address and head ID address. The arrow themselves can be considered to belong to the node that they originate from. The arrows represent pointers that are stored inside the node.

[0264] In the present embodiment, the tail node (or " EOC" node is included). However, in some embodiments, the last item of chain 512n may have the “next node” set to a NULL value to terminate the chain.

[0265] Pointers may act as proxies for their corresponding nodes. As such the head node is represented by the leftmost rectangle (502). The node may have up to 2x subordinate properties. Those are collectively represented by the white rectangle above it (508). The next node (node 504a) is the 1st node in the chain of the head 502. That node has 2x primIDs that are collectively represented by the red rectangle below it (514a) and up to 2x subordinate chains that are collectively represented by the white rectangles above it (512a). Figure 5 thus allows us to visualise a chain representation of the main chain easily.

[0266] Figure 6 illustrates a graph structure (shown in Figure 6(a)) mapped to the linked data structure (shown in Figure 6(b)). In Figure 6(a) the source vertex 602 represents the concept of cat and has an edge pointing to the destination vertex 604 of “Felidae”. That edge is labelled by an edge label 606 “family”. Figure 6(a) shows only “global properties” of the concept “family” as opposed to local properties.

[0267] In Figure 6(a) the concept of “family” represented by first label 606 in the graph has further properties. In this example, the concept to “family” has properties of "domain -taxonomy". This means that within this context “family” means taxonomical family rather than genealogical family. In Figure 6(a) these properties of the label are represented by a second edge pointing from the first label “family” to a second destination vertex 608. The second vertex 604 edge has a label 610 “taxonomoy” which is labelled “domain”.

[0268] In general, an infinite graph may be represented using further edges pointing from labels (or vertices) of a graph, as shown in Figure 6(a). For example, a secondary graph

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[0271] structure can include an edge (607) and further vertex (608), as shown in Figure 6(a) pointing from an edge label (606) or vertex of a primary graph. The edge and further vertex of the secondary graph structure can be used to store properties of the objects of the primary graph. In this example, the secondary graph structure includes edge 607, further vertex 608 and the label information 610 for edge 607. In embodiments, the primary and secondary graph structures are mapped onto a plurality of chains. In some embodiments, the data representation of the primary and secondary graph structure may include a first node as part of a first linear data representation and a copy of the first node as part of a second linear data representation.

[0272] Figure 6(b) depicts a data representation of the data of the graph structure of Figure 6(a). The first part of Figure 6(b) is similar to that described in Figure 1 (b). In Figure 6(b), the source vertex 602, the destination vertex 616 and the label 614 are represented inside boxes. Likewise the source vertex 602, and the destination vertex 604 and the label 606 are represented inside boxes. The boxes in Figure 1(b) and Figure 6(b) represent that each of these objects can be stored in a memory and in a data representation as a reference to a data address. The source vertex is connected to information on the edge label and the destination vertex by two arrows 603, 605.

[0273] In Figure 6(b), the label “family” is a head node 612. In this example, the local properties originate from label 606. This concept of family has a related concept (local property) of “domain-taxonomy” represented by vertices 614, 616. In some embodiments, properties associated with a part of, for example, a node of a first linear data structure may be represented in one or more further linear data structures.

[0274] In the node representation, "family" within the context of "cat" (the first white rectangle 606) points to the basic concept of "family" (the red rectangle 612). This connection is made via the primID pointer. In this example, the node of “family” 606 points, via primID, to a head node 612 that represents family. As such, the node family 606 of the first chain of cat points to a node of family (a head node) of a second chain.

[0275] In this example, the concept of “family” represented by vertex 612 is the general concept of family having the properties ‘domain-taxonomy”. If the concept of “family” within the concept of “cat” has that property then the vertices 616 and 614 would be attached to

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[0278] node 606. Vertex 612 is to be distinguished from 606 which represents family within the concept of cat (i.e. in the cat chain).

[0279] In Figure 6, the local properties emanate from family 606 rather than family 612. To understand how this works, something inside 612’s chain that defines the idea of a family as a taxonomical concept and stores its global properties. However, in 606 it is needed to tell the chain ‘cat’ that “this is how we mean family here; in the taxonomical sense”. This allows traversal of the graph from the primID ‘family’ to the actual chain corresponding to ‘family’, and also provides enough information to extract global properties related only to the context of ‘taxonomical family’.

[0280] In some embodiments, a graph structure represents at least a primary and a secondary graph. For example, as depicted in Figure 6(a), a label of a first graph may be associated with a secondary (or subordinate) graph that corresponds to properties of that label. In some embodiments, the graph structure may represent a plurality of linked graph layers and these may be mapped on to a plurality of linear data representations.

[0281] The concept of Figure 6(b) are presented in Figure 6(c) and (d). Figure 6(c) graphically represent a graph structure having a primary linear structure and a secondary linear structure. The primary structure of Figure 6(c) has a head node 1602 and a first node 1604 is represented by a circle. Further nodes belonging to the chain are represented by rectangle 1606. The head node represents the concept of “cat”. The primary structure depicted corresponds to the first semantic information “cats belong to the family of Felidae”.

[0282] The secondary structure has a head node “family” 1612. The secondary structure has two further nodes: first node 1614 and second node 1616. Further nodes are represented by 1618. The secondary structure represents second semantic information that is independent of the context of the first semantic information represented by the first structure. In this example, the secondary structure represents semantic information that that this “family” chain refers to the taxonomical context and is itself a noun. The context free secondary may be pointed to by multiple family of Felidae, and in fact can be pointed to by multiple primIDs scattered throughout the database.

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[0285] In this example, the “family” primID pointer of the first structure points to the head node of the secondary chain. The secondary chain represents semantic information on what a “family” is, independent of context.. The secondary chain is independent on the semantic information and context of the first chain.

[0286] Figure 6(d) graphically represents a graph structure having a first linear data structure and a second linear data structure. The first structure has a head node 1620 and a first node 1622. Further nodes of the chain are represented by node 1624. As in Figure 6(c), the content pointer of the first node points to head node 1612 of the second structure. In contrast to Figure 6(c), where the second structure included information about taxonomic rank, the second structure of Figure 6(d) is a more generic concept of the term the content pointer of the first node primID “family” points to the head of a chain. In this example, this “family” chain informs us that it is a noun in a context-independent manner.

[0287] As such the content pointer may point to a further linear structure that represents semantic information that is context independent of the node and / or first linear structure to which the content pointer belongs.

[0288] In addition, the first node also includes a further pair of pointers, specifically propl and prop2 that point to properties of further properties associated with the edge label and destination vertex (i.e. associated with the propID1 and proplD2). In this example, the edge label 606 is family and the destination vertex 604 is Felidae. The properties associated is at node 1626 that represents the semantic information that family of the edge label refers to the taxonomical interpretation.

[0289] Propl of the node to indicate that in the context of the semantic information of the first structure (i.e. “cats belonging to the family of Felidae”) “family” refers to the taxonomical interpretation. Beyond that point, the chain for “family” may have further specifications as to what the different meanings of the term imply, and the information encoded in the node emitted from propl can be used to seek that information.

[0290] It is noted that in recursively labelled graphs, an edge label itself may be further linked to other vertices via labelled edges, and so forth. This can be enabled by the “prop” pointers and additionally destination vertices can also be labelled by in-context properties in the exact same manner as edges.

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[0293] Therefore, for a given linear structure, a node may represent first semantic information at that node may include one or more pointers to one or more nodes of a further linear structure, where the one or more nodes represent second semantic information, the second semantic information being context free or otherwise

[0294] Semantic meanings of words can therefore be treated either as a contextual property of a node, via the miscellaneous pointer, or may form a node on its own. In the described embodiments, primID is essentially an identifier number as a pointer, but it can point to either an independent object (e.g., “that chestnut brown bird on this green tree”) or a concept (or class, “sparrow” and “camphor tree”). A primID may refer to a specific entity that’s described by its own nodes and the associated prop pointers may handle contextspecific information, which has no meaning of its own outside the specific context of the relation being specified by the node. This grants objects the same processing level as classes, so it may be possible to avoid the scalability problem of recursive inheritances in such expressions. Without limitation, it may be possible to build a knowledge graph with uniform data structures, while maintaining powerful contextual descriptions.

[0295] Figure 7 depicts special nodes in which contents are stored in subordinate arrays. Figure 7 represents the information of the natural language statement “Some cats are Persian breed” and “All cats belong to the family of Felidae”. In this example, in addition to storing properties, a special property called a quantifier value can be stored in M arrays, ensuring a formal system of first-order logic. This may, for example, empowers ASOCA GDB to store quantified propositions, as shown in Fig. 7. The M arrays may hold "universal properties" such as e.g. weights showing how strong an edge or vertex is.

[0296] The chain has a head node 702, a first intermediate node 704, a second intermediate node 706 and an end of chain node 708.

[0297] The first intermediate node, the second intermediate node and the end of chain node points to the head node. The role of “next” pointer in data structure points to another address of the node data structure along the chain.

[0298] The first intermediate node 704 represents a first property belonging to the concept of “cat” (i.e. within the context of the head node). In this example, the concept some breeds

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[0301] are Persian. The second intermediate node 706 represents a second property belong to the concept of “cat”. The second property is that all cats belong to the family of Felidae.

[0302] In the above-described embodiment, a linear data representation for information represented by a non-linear model such as infinitely labellable graphs is described. By mapping the information of those non-linear data models to one or more linear data representations, retrieval and search operations can be much faster. In addition, such operations can be parallelised. Different parts of the block structure may also communicate with each other.

[0303] The above-described embodiments allows a representation of data on a substantially homogeneous hardware. These quantifiers may be stored via a subordinate node in the form of [quantifier: therejs] or using a small set of quantifiers in M 1, M2 arrays, described above. M1 and M2 are the "bin properties" described above.

[0304] Figure 8 depicts an example architecture in accordance with an embodiment. The actual storage of the architecture includes the MEM block(s) and everything in the fast clock domain. The 8x MEM blocks of Figure 8 represent the 8x pointers in a node. Those a memories that store information and can perform address- and content-addressable reading.

[0305] The other parts of the architecture operate on a slow clock domain to implement higher level functions, such as marking memory locations as “of interest” (LOI block), or allowing storage of the results from content-addressable searches within the fast clock domain, especially when there are multiple of them. It also includes a local controller that can choreograph the action of multiple MEM blocks.

[0306] Figure 9 is a table of data operations, in accordance with an embodiment. The data operations can be grouped as content addressable read operations, address addressable read operations, comparison operations, buffer control, programming, buffer clear and counterpart operations.

[0307] The following comments on the data operations are provided.

[0308] NOP” corresponds to no operation. This is an idle state.

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[0311] “CAR” corresponds to a single-ended content-addressable search. As an example, for a film database, such a search includes find me “Tom Hanks.” In embodiments, a pointer may be searched for in the database as a cue. The address(es) where it has been found are returned by the underlying associative memory. In embodiments, it can be specified within which array of a supercluster to search, which may depend on an applied implementation scheme. For example.within the CNSM mapping, the array could be C1, C2, N1 etc.

[0312] “CAR2” corresponds to a double-ended content-addressable search. As an example, the search may correspond to “Find me [has: chicken]”. This is a 2-flit operation: CAR2-1 sends “has” and CAR2-2 sends “chicken”. In embodiments, CAR2 is an instruction to retrieve specific combinations of 2x pointers. As an example, specific combinations of pointers at selected arrays can be performed (for example, arrays C1 and C2 may be selected).

[0313] “AAR” corresponds to an Address addressable read. As an example, this operation includes show me what’s at location 777. This instructions reads or retrieves the pointer stored at a specified address in the database. This can be understood as a standard memory read.

[0314] “COMP” corresponds to a standard comparison between 2x numbers.

[0315] “BLKTRA” is a Utility function. This operation shifts data between a set of buffers. A small set of buffers can locally store data such as incoming commands or results of operations.

[0316] “GETBUF2” return the contents of a buffer to the central controller / route.

[0317] “PROG” corresponds to a write operation and write something to a particular address. In embodiments, PROGS sets a pointer within a node. For example, with reference to embodiments described above, PROG may set the primIDI pointer of a link node N that is stored in a C1-type array within a supercluster.

[0318] CLR” corresponds to “Clear all buffers”.

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[0321] “CTPT” is a counterpart operation. This operation corresponds to finding a counterpart of a search. For example, Find [’’wings”:?] will return?.

[0322] Additional utility operations may be implemented. These include HEAD, CARNEXT & TAIL). These operations allow the controller to traverse the graph structure. Instruction HEAD reads N1 of a given linknode and finds the headnode of the chain that “owns” this linknode.

[0323] CARNEXT returns “the next match” in the event that a CAR / CAR2 operation identifies more than a single match / answer.

[0324] TAIL iteratively reads N2 until the EOC and returns the address of the last linknode of the chain that ‘owns’ a given linknode.

[0325] A non-limiting example of querying the database is provided. After programming a complete database into hardware using PROG requests, massively parallel CARs on N1-type arrays can be used to quickly find the addresses of all linknodes belonging to a specific headnode (i.e., they can “highlight” a complete chain). This may be used directly for queries of the sort: “Fetch all information directly associated with Tom Hanks.” - note the use of “directly” to denote that we are not looking for information about Tom Hanks available in other chains, i.e. cases where thinking of a film or some other concept would “make us think of’ Tom Hanks.

[0326] Afterwards, AARs may be used to retrieve further contents from the identified linknodes (e.g. the primIDs) and fuel further searches using CAR, AAR, HEAD, CARNEXT or TAIL. Another example would be using CAR2 to locate 2 out of the 3 components in a ternary relationship, using a follow-up AAR to retrieve the final component. This can answer queries like: “Who won 2 Oscars?”. A CAR2 operation can be sent using “won” and “2 Oscars” as the query and then trace the head of the chain that owns nodes that match that description.

[0327] The proposed model may offers hardware advantages in terms of storage and performance. The model may grant a high degree of storage efficiency and response speed. Furthermore, the structure of the nodes strongly prescribes implementations where each element of the linknode is stored in a separate memory array.

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[0330] In the above-described embodiments, a linked list structure is described. The linked list may be ordered or unordered. In some embodiments, the linear data structure is an ordered linear data structure. In such embodiments, the ordering of elements may improve search time.

[0331] In an embodiment, if the nodes in a chain follow a logical order then searching may be improved. As an example, the primIDs may be taken as binary natural-coded numbers and sorted in size order, for example, with the smallest first. The numbers are then concatenated. The result is a long number formed by [primlDX: PrimlDY]. This can be considered as a “Godel number” of the node. The concatenated number can be used to sort and / or store nodes. As an example, if PROG operations are performed with sorting in mind, database sorting can be guaranteed along all chains.

[0332] In some embodiments, a node can represent or point to, for example, instructions and / or operations. The controller is configured to retrieve said instructions and execute them. Figure 10 represents an embodiment in which node represent instructions and / or operations. A search query is constructed from two operands into a set of operations: the object (ID 0x00a) and the property to search for (Felidae).

[0333] As an initial step, a null detection operator decides whether both operands are valid, as premises at step 1004.

[0334] If successful, the controller then traverses (the TRAV operation) the chain of 0x00a node by node, at step 1006. At each node, a content-addressable read 1002 for the property Felidae is performed (CAR). Upon finding the property or the end of chain, the content search result is returned, at step 1006.

[0335] As a failure CAR example, the operation is performed on the chain of Figure 4(b). In the first loop the controller will CAR for the concept “Felidae” on each node of that chain. The processor finds nothing but EOC. It then turns back to traverse 0x00a chain, but the same will apply on several other nodes, for example, colour, temper, naughty.

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[0338] CAR operations will occur in parallel. To perform a CAR, the chain is traversed to highlight the locations to perform a CAR. The search is then performed in memory and parallel, without the need to shift data back and forth.

[0339] When the controller traverses the chain of Figure 7, however, things are different: Felidae is found in this chain. This hit then breaks the content search process, and returns the node address (of node 706). The controller returns the address to a register inside the central controller.

[0340] Figure 11 depicts a presentation of a data operation for the memory block structure. Special nodes may be represented using the data representations that correspond to the contents stored in subordinate arrays to distinguish them from others. With processors under ASOCA architecture, the system enables functional mechanisms with IF-THEN statements. The special nodes may represent instructions, or functional statements or conditional statements. The special nodes may include an identifier to identify itself.

[0341] A method is described as follows. As a first step, a special "premise" node is searched for. When found, examine its downstream chain, i.e. if it is a subordinate chain like in Fig. 11, fetch the subordinate chain ascending from "premise" to the central controller, ignore everything else. The controller then checks if the conditions encoded in the fetched chain are met (this is done by checking its local memory and the details here are not important). If the conditions are met, the controller requests that the corresponding "operation" subordinate chain is fetched, as seen in Fig. 11. When fetched, the controller executes the instructions encoded in it.

[0342] In some embodiments, the configuration in physical memory of the linked list structure will be dependent on the linked list being represented. For example, a long chain without subordinates may be stored using a different configuration to a chain that branches a lot having many levels of subordinates.

[0343] In some embodiments, each memory block comprises a plurality of memory cell devices configured to store binary information and each memory cell device are configured to operate together to store pointers or memory addresses to form the linear data structure. In some embodiments, each individual node is stored at a single location across the 8

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[0346] arrays. In some embodiments, consecutive nodes along a chain may be stored in consecutive locations.

[0347] In the Figures, a bevelled rectangle means a node address. The colour red means "source vertex address". Red rectangles correspond to 102, 110, 204, 230, 252, 502, 602, 612, 702, 1002. White means any other address, which can be a destination vertex address, but it may also be other types of addresses as in Fig. 2. Blue means "next in the chain" node address. Blue corresponds to: 205, 236, 262, 504a, 504b, 504b, 704, 706, 708 and 1004. A node address may be used as a proxy for the node itself. An oval shape, refers to the address of the node under discussion. This is not physically represented in memory, hence the different shape. Note that head nodes "points to themselves" and so "head ID" will in fact be equal to "link address".

[0348] The memory block structure may form part of a microarchitecture module which is designed to store infinitely labellable graphs (with universal properties). The module is configured to manipulate them and traverse them in an extremely efficient fashion. It will be understood that the memory block structure described above, may be part of a microarchitecture which is an arrangement of registers, ALUs, finite state machines (FSMs), memories, and other logic building blocks needed to implement an architecture. The memory block structure answers the growing demand for graph databases, which contrary to the paradigm of relational, table-based databases, store data in terms of their connections. An infinitely labellable graph can be considered as graph where the following must be stored: source vertices, [edges, destination vertices], labels for each edge and destination vertex and then labels for those labels. In other words, to describe a single vertex in a graph we need following information: 1. The vertex itself, 2. Every edge that connects to it, 3. Every destination vertex, 4. Labels that manifest themselves as edges and vertices that connect to each edge and each destination vertex.

[0349] Since the above information is not different from what memory block would naturally store, storing the above details provides a way to save a graph of potentially infinite depth. Using simple instructions on the memory, it should be possible to traverse such a graph efficiently. Each memory block implements a linked list structure and spread the data stored in each linked list “node” into eight numbers, namely:

[0350] 1. The edge ID.

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[0353] 2. The destination vertex ID.

[0354] 3. The "head" pointer.

[0355] 4. The "next" pointer.

[0356] 5. The "edge label" pointer.

[0357] 6. The "destination vertex" pointer.

[0358] 7. Block A of extra, universal properties (e.g. node weight).

[0359] 8. Block B of extra, universal properties (e.g. node weight).

[0360] In embodiments, the memory block structure may be implemented as associative memory. In some embodiments, the memory block structure may comprise one or more associative memory modules or chips.

[0361] The following non-limiting comments are provided for completeness.

[0362] The complexity and interconnected nature of graph-structured data demand specialised accelerators to efficiently manage and process large-scale datasets, overcoming the limitations of traditional computing architectures. A modular graph database accelerator is described, a novel hardware solution designed to address the unique demands of graph-structured data. This modular design may facilitate high-throughput and low-latency operations, significantly improving scalability and performance in graph database applications.

[0363] Figure 9 depicts instruction set architecture. The instruction set architecture (ISA) defines 8 groups of instructions that the memory block structure or associated device (referred to as ASOCA2) can execute and 7 available registers. It may be via graph manipulation-oriented and hardware operations. Starting from MSB, an instruction uses 4 bits for opcodes, 12 bits for instruction arguments, and 64 bits for data values. The ASOCA ISA define the interactions with data inside the system.

[0364] In an example, 8 memory arrays of 64×64 make up a supercluster (SC), the fundamental unit for instruction execution. To address data in hardware, both arrays and SCs are assigned with identifiers. A structure called “linknode” (also referred to as a node or link structure). The linknode is addressed by its physical memory address, which takes the format: [“primIDI”, “primlD2”, “head”, “next”, “propl”, “prop2”]. A graph database entry is

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[0367] then represented by 8 numbers stored across 8 arrays in corresponding locations. In this example, for a plurality of nodes, pointers of the same type are stored together.

[0368] Type Array identifier Linknode component. Usage

[0369] Cl prirnlDl Edge label node ID Content

[0370] 02 prind'D2 Destination node ID

[0371] N1 head Source node ID Navigator

[0372] N2 next Next node address

[0373] S'l.fesereed

[0374] Subordinate Kesewed

[0375] S2 Eeserued fared!

[0376] Ml propl Edge label properties

[0377] Miscellaneous

[0378]

[0379] M2 prop2 Destination vertex label properties Memory array identifier aiiocation

[0380] Table 2

[0381] N1, C1 and C2 collectively define: a source vertex, an edge and a destination vertex respectively, thus representing a graph database entry as a structure with 8 fields across 8 physical memory arrays (as shown in Figure 13(a)) while N2 is used to connect all nodes that share the same source node for a linked list.

[0382] Ultimately, arbitrary graph structures can be represented via multiple linked lists, where each linked list represents all connections emanating from the source vertex that “owns” the chain. Working with chains may allow for maximum flexibility, completely decoupling the conceptual structure of the graph being stored from the physical memory location where each node is stored.

[0383] Eight functionally identical memory arrays are used in the CNSM allocation. Each memory array is allocated an identifier reflecting its functional meaning as shown in Table 1. “C” arrays.

[0384] Table 2 illustrates a memory array identified allocation in accordance with a first scheme, referred to as CNSM allocation. In such a scheme, eight functionally identical memory arrays may be used. “C” arrays store primIDs, the main “Content” of the GDB. “N” arrays store pointers that allow traversals, i.e., they are “Navigational” in nature. “S” arrays store pointers that branch towards “Subordinates”. Finally, “M” arrays were added to store extra properties (“Miscellaneous”).

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[0387] The M arrays allow storage of additional properties for graph edges and vertices, such as edge wrights, vertex degrees and quantifiers for first order logic. They may be referred to a universals. A further scheme, referred to as normalised allocation is outlined in Table 3.

[0388] Ty v M Uffer Linkrsnle mapping

[0389]

[0390] , l prisXPl dge wr to painter

[0391] Content I iatta. pointer

[0392] ., head TO Shores vertex painter avtoter.....xnext ^ext intoodn ptenter

[0393] Table 3

[0394] This alternative allocation is a minimal version for simpler database. The S and M arrays are removed, leaving just C and N. Sub-ordinate chains may be implemented as separate chains. Such an allocation is suite for graphs with less context dependent information.

[0395] These two scheme may be referred to as mappings of the structures onto hardware (the physical memory arrays).

[0396] Figure 8 (above) depicts a system implementation. A supercluster (SC) operates with a slow clock four times the period of the fast clock. This asynchronous design makes the system more commensurate to the actual processing rate, thus lowering power. Each SC contains 8 memory blocks (MEM) under the fast clock, derived from the previous iteration of ASOCA1, and digital peripherals functioning under the slow clock. These include: ONECON for storing matching addresses, LOI for marking locations of interest, CTRL for control logic, BUF for purpose-specific regfile, COMP for near-memory arithmetic.

[0397] Every functional block inside SC interfaces with others through DATASRC buses to record data from different sources for operations and outputs.

[0398] The modular graph database accelerator is described providing a specialised hardware solution designed to address the unique demands of graph-structured data. By grouping

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[0401] memory cores into superclusters with local processing units, this modular approach may enhance data locality and processing efficiency, facilitating high-throughput and low-latency operations. It may show high scalability and provide a flexible framework adaptable to various graph-based applications.

[0402] The convergence of deep learning with neuromorphic hardware highlights the potential of combining computational efficiency with innovative architectures. A scalable, modular graph database accelerator tailored to the unique demands of graph-structured data is described. This system may demonstrate performance improvements and applications in parallel graph database processing for high-performance, energy-efficient data solutions.

[0403] Figure 13(a) depicts a supercluster 1300 in accordance with an embodiment. As described with reference to Figure 13(a), the supercluster includes a memory block and a controller 1302. In this embodiment, the memory block is formed from eight physical memory arrays (1304a, 1304b, 1304c, 1304d, 1304e, 1304f, 1304g, 1304h). The memory block is configured to store a plurality of nodes, as described above. Each of these physical memory arrays is configured to store pointers of the same type for the plurality of nodes of the memory block. For example, as set out in Table 2, all pointers for the plurality of nodes stores on the memory block of the type “primIDI” are stored in array 1304g. For example, as set out in Table 2, all pointers for the plurality of nodes stores on the memory block of the type “head” (or head ID) are stored in array 1304c. The arrays of the Figure are labelled using the corresponding identifiers of Table 2. The arrays are paired to share resources, such as registers.

[0404] Figure 13(a) also depicts a number of buffers modules for servicing the supercluster. The controller is further configured to send signals to the arrays of the memory block. The controller also handles communications with the central controller (labelled routing network) and coordinates actions within the memory block. An input bus (1306) is also depicted for sending queries or other data into the memory arrays. An output bus (1308) is also depicted for sending responses and other data from the memory array.

[0405] The superclusters may be a near-memory processor (NMP) that store relations near the data itself with physical memory arrays and local processing units. This modular

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[0408] approach may enhances processing efficiency with a higher throughput and lower latency.

[0409] Figure 13(b) depicts an array of superclusters, in accordance with an embodiment. In this embodiment, there are eight superclusters. A first supercluster 1320 is labelled. Each supercluster may be provided as described with reference to Figure 13(a). As described with reference to Figure 13(a) 8 memory arrays of 64×64 (each referred to as an ASOCA array 1322 make up a supercluster (SC). These sub-arrays can be considered as the unit storage array.

[0410] In the larger array of superclusters, the graph structure described above is mapped onto groups of sub-arrays. The arrays in each group correspond to identifiers described above. Each group (in this embodiment, of eight sub-arrays) is referred to as a superclusters. Superclusters thus store 64x nodes under a CNSM allocation scheme for a total memory footprint of 32kb. As described above, processing resources are provided around these memory arrays to enable near-memory computation. The array of Figure 13(b) has eight such superclusters, and provided on available 180nm. In embodiments, the architecture is provided on a field programmable gate array platform.

[0411] Beyond-CMOS memory cells may be implemented as a basic bit-storage unit, it is a dually-addressable memory (DAM) array capable of storing any of the pointers in, for example, both the CNSM and Normalised schemes shown previously (i.e., any line in Table 2 and Table 3). The array ASOCA1 arrays are designed to hold 64* 64-bit pointer entries each and for the purposes of this paper, they can be considered the “unit storage array”.

[0412] A further chip (referred to as Associative Memory Chip II (ASOCA2) has a structure mapped onto groups of 8* ASOCA1 arrays (4* pairs). The arrays in each group correspond to the identifiers from Table 2 and each group as a whole is called a “supercluster”. Superclusters store 64* link nodes under CNSM allocation for a total memory footprint of 32Kb. A set of digital peripherals is built around these memory arrays for enabling near-memory computation. The ASOCA2 chip as a whole contains 8* such superclusters and its tape-out layout is shown in Figure 13(b). Without limitation, the technology may be built around a 180nm node. This architecture was also translated on

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[0415] a field-programmable gate array (FPGA) platform, where the custom-made DAM was replaced by a more conventional, but still relatively resource-efficient implementation Figure 14(a) and (b) illustrate further examples of linked list structures demonstrating how sematic information may be stored using said structures. Figure 14(a) depicts a first linear structure (also referred to as a chain) having head node 1402 and first node 1404 and end of chain node 1406. Figure 14(a) depicts a second chain having a head node 1410 and first node 1412 and the same end of chain node 1406.

[0416] A further third chain is depicted in Figure 14(a). The third chain has a first node 1414, second node 1416, third node 1418 and end of chain node 1406. The first, second and third linear chains have a common end of chain node 1406. It will be understood that the node labelled first node may not be the first node of the chain but rather an intermediate node in a longer chain.

[0417] A further node 1420 is depicted. The further node belongs to a further (fourth) chain.

[0418] The third and fourth chain may be referred to a sub-ordinate chains and are linked to nodes of a primary chain (in this example, the first chain) by the sub-ordinate pointers (propl and prop2). In other words, the first node 1404 of the first chain has a first content pointer (primIDI) 1422 and associated sub-ordinate pointer (propl) pointing to the node 1406 of the third chain. Likewise, the first node 1404 of the first chain has a second content pointer (primlD2) 1424 and associated sub-ordinate pointer pointing to node 1420 of the further chain.

[0419] As can be seen from Figure 14(a), the sub-ordinate chains include contextual information relating to the “concept” or “object” represented by the content pointer. In other words, the sub-ordinate chain represents semantic information for that concept or object within the context of the first chain.

[0420] In this example, the first chain represents “This soup contains chicken” and that the “chicken” in the context of the soup has contains chicken, about which we know that the part of interest is “breast”, and that it is chopped into cubes and marinated in soy sauce. That contextual information is thus encoded in a subordinate chain. In embodiments, using such sub-ordinate chains, local infinite labellability for priml Ds can be implemented and subtree search and graph mining can be performed.

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[0423] In contrast, the second chain is not a sub-ordinate chain, but rather a chain that is linked via the content pointer of the first chain. The primID of the first chain points 1422 to the head node of the second chain 1410. The second chain provides context independent information about the concept or object represented by the content pointer of the first chain. In this case, that information is represented in the content pointers of the second chain, that the species for name of chicken is Gallus Gallus.

[0424] Turning to Figure 14(b), it is depicted that a sub-ordinate chain can itself be linked to further sub-ordinate chains, emphasising the infinitely recursive labellability of the model, and in this way, the proposed GDB model is capable of representing complex contextual information. In this example, there is a primary chain having a head node 1430, a first node 1432 and an end of chain node 1434. The first sub-ordinate chain (represented by node 1436) is linked to the first node 1432, while a second sub-ordinate chain (represented by node 1438) is linked to node 1436 of the first sub-ordinate chain. Further a third sub-ordinate chain (represented by node 1440) is linked to node 1438 of the second sub-ordinate chain. Figure 14(b) also depicts that a node can be linked to more than one sub-ordinate chain (in this case, first node 1432 is linked to first sub-ordinate chain 1436 and a further sub-ordinate chain 1442).

[0425] As described above, chains can represent semantic information, and sub-ordinate chains may represent further semantic information within the context of their parent chain. In this example, multiple levels or in-context labelling is stored in the data structure, which reads as Films-is a-form{of-visual storytelling[through-a sequence(of-moving images)} or simply “Film is a form of visual storytelling through a sequence of moving images”. Each sub-ordinate node points to the end-of-chain node to indicate that the those nodes are not part of a single chain but belong to their own sub-ordinate chains.

[0426] Figure 15 depicts a non-linear graph structure represented as a plurality of linked lists.

[0427] In Figure 15, each node is depicted as a physical address, visible inside the circle that represents the node. In the following description, nodes are referred to as the physical address node (for example, node having physical address 0x1 is referred to as the 0x1 node.

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[0430] The structure of Figure 15 can be described as five chains that are interconnected. Each chain has a corresponding head node. The first chain has, in order, a first head node 1502, 0x1 node, 0x2 node, and terminates at end node 1508. The second chain has, in order, a head node 1504, 0x6 node, 0x7 node, 0x8 node and terminates at end node 1508. The third chain has, in order, head node 1506, 0x4 node and terminates at end node 1508. The fourth chain has, in order, head node 1510, Oxa node and terminates at end node 1508. The fifth chain has, in order, head node 1512, Oxc node, Oxd node and termination in end node 1508. All five chains have the same common end node 1508.

[0431] Each list, optionally each node of the list, can be considered to represent semantic information, for example, information about objects or concept and / or relationship information between said objects or concepts. Each chain can be considered to store or represent information about a semantic object or concept.. For example, the first chain stores information about the actor “Tom Hanks”, while the second chain stores information about the film “Sully”. The third chain stores information about the phrase “act in”. The fourth chain stores information about the object “Film”. The fifth chain stores information about the person “Sully Sullenberger”.

[0432] The information encoding the phrase “Tom Hanks - acts in - this film” is represented in the first chain, by the 0x1 node having head ID = “Tom Hanks”, primIDI = “this film” and primlD2 = “acts in”.

[0433] The phrase “this film” can be considered as a human-readable label used to denote the chain that contains information on the film “Sully”. It will be understood that other codephrase such as “linknode at 0x5” or “entity 83” could be used.

[0434] To retrieve information about the film in question, the pointer from primIDI (“this film”) is followed. This leads to the “This Film” chain having three linknodes (0x6, 0x7 and 0x8). These nodes, in turn, represent information that: (i) the entity is a film, (ii) the title is “Sully” and (iii) the protagonist is Sully.

[0435] To obtain information about the concept of “act in” independent on the context of the first list, primlD2 points towards 0x4 node.

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[0438] Contextual information is not obtained by following the primlD2 pointer to 0x4 node -that list returns only general and non-contextual information about what is meant by “act in” - it’s a cinematic term. An example of a contextual query, in the context of the first list is “Who in this film does Tom Hanks act as specifically (the answer is the character, captain Sully Sullenberger)”. In Figure 15, 0x1 node has a linked subordinate chain (represented by node Oxe). The subordinate chain represents local properties of primIDI (i.e. act in). In this example, the subordinate chain represents that the object of primIDI (“act in”) has the additional property of “as - Sully”. This is the same object “Sully” that 0x8 node from the “This Film” chain is pointing to.

[0439] It will understood that the node Oxe is not directly linked into the chain of “Tom Hanks”. This is because “as - Sully” is a property of “act(s) in” within the context of “This Film”, not of Tom Hanks in general. Again “Sully” is a human-readable codeword. The key feature here is that the corresponding primID from the linknode at Oxe points to the chain that is labelled “Sully Sullenberger”.

[0440] The 0x7 node represents information that this list represents a film titled “Sully”. This is denoted explicitly as “Sully” to show that the pointer does not point to a linknode of the person Sully Sullenberger, but rather to a generic string. This allows the graph structure to refer to objects outside its direct space of nodes. In this manner, other data objects or data structures such as strings, multimedia, and even ensemble activations of neural networks may be connected to the graph. That information may be stored on an external memory resource.

[0441] A further example query “Who is Sully?” is described. To answer this question, the chain with head node “Sully Sullenberger” is identified as the “Sully”. The list having nodes Oxc and Oxd represents the information that he is a public figure with a profession of pilot. That chain is context independent of, for example, the first list and does not provide information that “Sully” is a protagonist in the film titled “Sully”. This is equivalent to being prompted with “What do you know about Sully Sullenberger?” and replying with the contents of the corresponding chain. The query itself is therefore context independent.

[0442] A context dependent query such as “In what film is Sully Sullenberger a protagonist”? may also be answered using a content addressable search. In this example, the answer

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[0445] is found at an intersection of the concept of “Sully Sullenberger” and the concept of “protagonist”. The answer is Sully, the primlD2 of 0x8 node of the This Film list.

[0446] A cued concept refers to knowing headnode addressed. In this example,the first cue is “Sully Sullenberger” and the second cue is “protagonist”. A content-addressable search of the database for where these two cued concepts meet, can be used to recover the answer to this question.

[0447] A further example query Is described. “Where does Tom Hanks act?” and receive the answer “He acts in Sully.” Someone not knowing the film may ask: “What is Sully?” and receive the answer “It is a film.” This allows a user to start building the chain that we have denoted here as “This film” (in fact there is enough information to build the headnode and linknodes at 0x6 and 0x7). By someone not knowing what a film is, the follow-up question “What is a film?” may also be asked.

[0448] As a final example, to provide a distinction between the real Sully Sullenberger and his on-screen character. In this case we have two immediately obvious options: either (i) we will start a subordinate chain for the primID pointing to “Sully” in the 0x8 node, or (ii) we will create a new chain for the dramatized version of Sully Sullenberger and let the connection from the primID of the linknode at 0x8 to this new chain, and then somewhere in the new chain introduce a linknode making it clear that the chain refers to the dramatis personae of the real Sully Sullenberger. This illustrates both the importance of setting up a schema so as to be fit-for-purpose and the flexibility of the described structure. The is also naturally compatible with the property graph data model with “nodes” mapping to “head nodes”, “edges” mapping to primIDs and “properties” possible to attach a subordinate chains.

[0449] The following non-limiting examples and comments on further applications of the data structure are provided.

[0450] The following non-limiting comments on graph database model are provided. Embodiments relate to a graph database model that represent graphs with the following properties: (1) Directedness: vertex pairs are connected by directed edges (or “arcs”), (2) Labellability: edges and vertices can both be “labelled” i.e., further properties may be attached to them (3) Recursiveness of labelling: labels can themselves be labelled and

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[0453] so on ad infinitum. These graphs may be referred to as directed recursively labelled graphs (DRLGs). Notably, both arbitrarily connected directed graphs and directed acyclic graphs (DAGs) are subsets of this definition (the former does not feature infinitely deep labelling and the latter also does not feature graph cycles).

[0454] The graph relationship of Figure 1(a) may be referred to a “half-K2” digraph (to distinguish it from the full K2 digraph which includes the reciprocal edge). The graph of Figure 1(a) may be considered to represent a “unit of relational information” within a graph. As such, repeated instantiation of such ternary relationships can be used to create any DRLG graph. In the semantic web context, such a structure corresponds to a Resource Description Framework (RDF) triple, and repeated instantiation constructs an RDF graph. Within that framework of <subject-predicate-object>, subject corresponds to the “source” vertex, predicate to the labelled edge, and object to the “destination” vertex. Finally, note that the terms “source”, “edge” and “destination” are used in a “de re” fashion and refer to the objects in question directly: we have not yet made use of labellability so far.

[0455] Views represents the triplet relationship using a “source-centred”, numerical structure that we shall call the “conjugate triplet”, meaning that edges and destination vertices are treated as equivalent entities (i.e., we make no distinction between them), both of which relate to the source vertex in the same fashion. This is illustrated in Figure 1(b), where the source vertex “points to” both the edge and the destination vertex. Note that the arrows in this figure denote the concept of “owns” or possessive. In other words, the source vertex “owns” the marked destination vertex and edge. Thus, the pair of vertices and connecting edge have been mapped onto a set of 3 numbers that can be stored in a physical memory. So long as there is a way to track the association between the members of the conjugate triplet, a triplet in physical memory can be stored.

[0456] In further applications, the graph database structure may be used for semantic reasoning. In such applications, a first chain may be used to represent a class of an object while the object or a property of the class and / or object may be represented by a second chain. As such, to determine that an object has a property that belongs to a larger class, a first query to determine that the object is a member of that class may be performed followed by a second query to determine the property of the class.

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[0459] Different data representation schemes may change the logic of the solution very dramatically. Consider, for example, how the programme would change if instead of encoding the statement that “The species of ‘this’ is cat” as illustrated above we encoded it with the primID pairing (“is”, “cat”). In a further example, in a hierarchically structured taxonomical database(s), information about “family” may only be traced by its subordinate “genus”.

[0460] Further applications may be used. In particular, cognitive models may be represented using the linear data structures as a non-limiting example, activation based cognitive models, such as copycat models, may be implemented using the structure. In such models, each concept may be stored as a head node. Conceptual relationships can then be encoded using a regular (non-head) linknode format. In embodiments, a slipnet based model may be represented by the linear data structures.

[0461] In embodiments, cognitive models that use activation levels across a network may be modelled using the linear data structures. In such embodiments, miscellaneous pointers can be used to store activation information, such as activation value and activation decay rates for each node, and a conductance value or level of spread to encode how efficiently a conductance value can spread over a node.

[0462] In accordance with embodiments, the graph structure is implemented in hardware in one or more first memory devices described above, and the graph structure includes memory references that refer to one or more storage devices that are outside the graph structure. In embodiment, the graph structure may be implemented as a database on one or more memory devices (and / or superclusters) that communicates internally. In embodiments, the graph structure may be implemented as a database on one or more memory devices (superclusters) that include memory references to further, external storage resources outside the one or more memory devices.

[0463] In the above described embodiments, memory references may refer to a semantic object or concept represented by data or other data object. The references may be stored on hardware provided in the memory device while the data is stored either in the memory device or in a further memory resource. In embodiments, the memory device is self-contained in that all data referred to by the graph structure is contained within the

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[0466] memory device. In further embodiment, the graph structure is stored on the memory device that links to data objects found on a further memory.

[0467] Although description of particular embodiments has been provided above, it should be understood that these embodiments are illustrative only and that the claims are not limited to those embodiments. Those skilled in the art will be able to make modifications and alternatives to the described embodiments which are contemplated as falling within the scope of the appended claims. Each feature disclosed or illustrated in the present specification may be incorporated in any embodiment, whether alone or in any appropriate combination with any other feature disclosed or illustrated herein. In particular, one of ordinary skill in the art will understand that one or more of the features of the embodiments of the present disclosure described above with reference to the drawings may produce effects or provide advantages when used in isolation from one or more of the other features of the embodiments of the present disclosure and that different combinations of the features are possible other than the specific combinations of the features of the embodiments of the present disclosure described above.

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Claims

M& C PE963137GB53CLAIMS:

1. A memory block structure comprising:a plurality of memory blocks configured to store data of at least part of a graph or other non-linear data model as one or more linear data structures;a plurality of local controllers, each local controller associated with a corresponding memory block and configured to search and / or retrieve data of the graph or other non-linear data model by navigating the one or more linear data structures, wherein the linear data structure comprises a head node and a plurality of nodes each represented by at least a reference to a head node of the linear data and a reference to a further node of the plurality of nodes.

2. The memory block structure of any preceding claim, wherein the one or more linear data structures comprise a linked list data structure.

3. The memory block structure of any preceding claim, wherein the one or more linear data structures comprise at least a first and second linked data structure, wherein the first and second linear data structures are linked and / or have a common head node and / or a further common node.

4. The memory block structure of any preceding claim, wherein each linear data structure is navigable in a single direction.

5. The memory block structure of any preceding claim, wherein each of the local controllers are configured to perform graph or other non-linear data operations, for example, graph traversal, by navigating the one or more linear data structures, optionally in a single direction.

6. The memory block structure of any preceding claim, wherein the plurality of local controllers are configured to perform data operations independently of other controllers and / or perform parallelised searching of the plurality of memory blocks.

7. The memory block structure of any preceding claim, wherein the graph or other non-linear data model represents data as a plurality of vertices connected by edges, optionally directed edges, optionally with associated label information, wherein each55657216-1M& C PE963137GB54vertex and graph and optionally each label is represented as a node in the linear data structure8. The memory block structure of any preceding claim, wherein the graph or other non-linear data model is mapped to the linear data structures and / or wherein each vertex, directed edge and associated label of the graph or other non-linear data model is mapped to a respective node of the linear data structure.

9. The memory block structure of the any preceding claim, wherein the graph or other data structure comprises a source vertex and a destination vertex joined by a labelled directed edge, wherein each of the source vertex, destination vertex and labelled directed edge are represented by respective nodes in the linear data structure.

10. The memory block structure where at least one of the linear data structure comprises a first node representing a first label, for example, for an edge or vertex, and a second, linked node, representing a second label for the first label.

11. The memory block structure of any preceding claim, wherein each edge, vertex and label of the graph and / or non-linear data model is represented by and / or is mapped onto a common node data structure.

12. The memory block structure of claim 11, wherein the common node data structure comprises a plurality, optionally at least six, optionally eight, variables representing a memory address of another node or data.

13. The memory block structure of any preceding claim, wherein each local controller is configured to perform at least one of: direct memory read, associative read, write, counterpart search.

14. The memory block structure of any preceding claim, wherein each memory block comprises a plurality of nodes of the linear data structure, for example, 64, 128, 256 or 512 nodes.

15. The memory block structure of any preceding claim, wherein the linear data structure is formed from a plurality of nodes, wherein at least one of the linked nodes is55657216-1M& C PE963137GB55a first node representing part of a primary graph, wherein the primary node is linked to a copy of the first node that represents part of a secondary graph.

16. The memory block structure of any preceding claim, wherein the graph structure or other non-linear data model represents a plurality of linked graph layers, wherein each layer of the plurality of linked graph layers is mapped on to a plurality of linear data representations.

17. The memory block structure of any preceding claim, each memory block comprises a plurality of memory cell devices configured to store binary information, wherein the plurality of memory cell devices together store pointers or memory addresses to form the linear data structure.

18. The memory block structure of any preceding claim, wherein one or more nodes of the linear data structures represents and / or refers to one or more instructions, wherein the controller is configure to navigate the one or more linear data structures to obtain one or more instructions and execute said one or more instructions.

19. The memory block structure of any previous claim, wherein the at least one linear data structure is configured to store semantic information, optionally wherein each node represents a semantic object and / or associated information and / or a reference to a semantic object and / or associated information.

20. The memory block structure of any preceding claim, comprising a first linear data structure and a second linear data structure, the first and second linear data structures comprising one or more linked nodes, wherein the first linear data structure represents first semantic information and the second linear data structure represents second semantic information independent of a context of the first semantic information21. The memory block structure of any preceding claim wherein information for a first object is stored as data and / or a memory reference in a first linear data structure, and information associated with said object or a property of said object is stored as data and / or a memory reference in a second linear data structure, wherein the second linear data structure is linked with and / or navigable from the first data structure and vice versa.55657216-1M& C PE963137GB5622. The memory block structure of any preceding claim, wherein data is stored in said model in accordance with a semantic data model, optionally wherein the sematic data model comprises one or more of: a cognitive data model, a hierarchy based taxonomy model, an attention based cognitive model.

23. The memory block structure of any preceding claim, wherein the node comprises one or more pointers to one or more data objects or structures, optionally stored on a further memory resource provided externally to the memory block structure, further optionally provided on a further memory resource, for example, a networked resource.

24. The memory block structure of any preceding claim, wherein each node comprises a pair of content pointers each represented as a corresponding pair of binary natural-coded numbers or other binary-coded decimal, wherein each node is assigned a number formed by concatenation of said pair of binary natural-coded numbers.

25. The memory block structure of claim 24, wherein the nodes are sorted and / or stored based on the assigned concatenation number.

26. The memory block structure of any preceding claim, wherein each node comprises a pair of memory references to a respective pair of associated data items, wherein the structure comprises at least one of:a) one or more nodes comprises a pointer to a node of further linear data structure having a node representing further properties of at least one of the respective pair of associated data items;b) the pair of pointers point to a node of a further linear data structure corresponding to at least one of the pair of associated data items.

27. A semiconductor device comprises a non-transitory memory resource comprising and / or formed by the memory block structure of any preceding claim.

28. A method of obtaining data from a memory block structure, wherein the memory block structure comprises a plurality of memory blocks configured to store data of at least part of a graph or other non-linear data model, the method comprising:searching and / or retrieving data of the graph or other non-linear data model by navigating the one or more linear data structures of the memory block structure.55657216-1

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