Charge transfer element

Abstract

A charge transfer element (10) according to the present invention includes a substrate (101), a lower insulating film (102), a semiconductor channel (12), and an upper insulating film (103) in this order in the direction perpendicular to the surface of the substrate, and also includes a first gate (14) and a second gate (15), which are disposed in the lower insulating film or the upper insulating film, a source region (11) electrically connected to one end of the semiconductor channel, and a drain region (13) electrically connected to the other end of the semiconductor channel. The first gate and the second gate are disposed above the semiconductor channel to be in parallel in the direction in which the semiconductor channel extends, the source region includes a p-type semiconductor or a n-type semiconductor, and the drain region includes a semiconductor of a conductivity type opposite to the conductivity type of the source region.　Thus, the present invention can provide a charge transfer element enabling the selection between electrons and holes and capable of transferring a single charge by a single element.

Description

Charge Transfer Device

[0001] The present invention relates to a charge transfer device that transfers electrons or holes.

[0002] In charge-transfer devices, a single charge transfer device is a device that periodically and accurately transfers a single charge within the device by applying a clock signal with frequency f to the gate electrode of the device. The generated current is an accurate value obtained by multiplying the elementary charge e by the frequency f, so it is expected to be applied to a current standard corresponding to a current ruler.

[0003] To apply a single charge transfer device to a current standard, the accuracy of the generated current is important. －８ However, no device has been developed that can achieve this target value in all frequency bands, especially in the GHz region. Currently, single charge-coupled devices have a transfer error rate of 2×10 in the GHz region. －７ It has been demonstrated that it is possible to reach a level of 10 －８ It is expected that this will exceed the standard (Non-Patent Document 1).

[0004] However, at present, it is not possible to achieve the accuracy of this theoretical prediction for all devices.

[0005] In single charge transfer, the accuracy of single charge transfer differs between the transfer of a single electron and the transfer of a single hole. Electrons are expected to be more resistant to fluctuations and operate stably (Non-Patent Document 2). On the other hand, holes are expected to have higher physical accuracy (Non-Patent Document 3). Therefore, when fabricating a large number of single charge transfer devices, it is desirable to select whether to use electrons or holes and utilize the optimal charge.

[0006] P. Giblin, G. Yamahata, A. Fujiwara, and M. Kataoka, Metrologia 60, 055001 (2023).Y. Niida et al., Appl. Phys. Lett. 102, 191603 (2013).G. Yamahata and A. Fujiwara, J. Appl. Phys. 014502 (2024).

[0007] As mentioned above, it is difficult to achieve high-precision operation with a single charge transfer device. To achieve high-precision operation with a large number of devices, a device that can select between electrons and holes is required. However, until now, a device that can transfer a single charge for both electrons and holes with a single device has not been realized.

[0008] In order to solve the above-mentioned problems, the charge-coupled device according to the present invention comprises, in order, a substrate, a lower insulating film, a semiconductor channel, and an upper insulating film, and further comprises, disposed within the lower insulating film or the upper insulating film, a first gate, a second gate, a source region electrically connected to one end of the semiconductor channel, and a drain region electrically connected to the other end of the semiconductor channel, the first gate and the second gate being disposed above the semiconductor channel in parallel with each other in the direction in which the semiconductor channel extends, the source region being made of either a p-type semiconductor or an n-type semiconductor, and the drain region being made of a semiconductor of a conductivity type opposite to that of the source region.

[0009] Furthermore, a charge-coupled device according to the present invention comprises, in this order, a substrate, a lower insulating film, a semiconductor channel, and an upper insulating film; and, disposed within the lower insulating film or the upper insulating film, a first gate, a second gate, a source region electrically connected to one end of the semiconductor channel, and a drain region electrically connected to the other end of the semiconductor channel; the first gate and the second gate are disposed above the semiconductor channel and parallel to each other in the direction in which the semiconductor channel extends; the source region comprises a first source region made of a p-type semiconductor and a second source region made of an n-type semiconductor; and the drain region comprises a first drain region made of a p-type semiconductor and a second drain region made of an n-type semiconductor.

[0010] According to the present invention, it is possible to provide a charge transfer device that can transfer a single charge by selecting electrons and holes with a single device.

[0011] FIG. 1A is a schematic top view showing the configuration of a charge-coupled device according to a first embodiment of the present invention. FIG. 1B is a schematic cross-sectional view taken along line IB-IB' showing the configuration of a charge-coupled device according to the first embodiment of the present invention. FIG. 2A is a schematic top view showing the configuration of a charge-coupled device according to a second embodiment of the present invention. FIG. 2B is a schematic cross-sectional view taken along line IIB-IIB' showing the configuration of a charge-coupled device according to the second embodiment of the present invention. FIG. 3 is a schematic top view showing the configuration of a charge-coupled device according to a third embodiment of the present invention.

[0012] First Embodiment A charge-coupled device according to a first embodiment of the present invention will be described with reference to FIGS. 1A and 1B.

[0013] 1A and 1B, a charge-coupled device 10 according to this embodiment comprises, in the horizontal direction (the x-direction in the drawings), a source region 11, a semiconductor channel 12, and a drain region 13. The semiconductor channel 12 extends in the x-direction and is electrically connected to both the source region 11 and the drain region 13.

[0014] Charge-coupled device 10 comprises, in order in a direction perpendicular to the surface of substrate 101 (z direction in the drawing), substrate 101, lower insulating film 102, semiconductor channel 12, upper insulating film 103, and upper gate 16, and further comprises first gate 14 and second gate 15 within upper insulating film 103. In the following, to make the configuration of charge-coupled device 10 easier to understand, upper gate 16 is shown by a dashed line in top view schematic diagrams.

[0015] The first gate 14 and the second gate 15 are arranged in the upper insulating film 103 above the semiconductor channel 12 in parallel with the direction in which the semiconductor channel 12 extends.

[0016] The substrate 101 may be made of Si. The lower insulating film 102 and the upper insulating film 103 may be made of SiO. ２ The substrate 101 and the lower insulating film 102 may be formed of an SOI (Silicon on Insulator) substrate.

[0017] Si may be used for the semiconductor channel 12. The semiconductor channel 12 does not need to be doped with impurities.

[0018] The source region 11 is made of an n-type semiconductor, and the drain region 13 is made of a p-type semiconductor.

[0019] In the source region 11 and the drain region 13, portions other than the vicinity of the connection portion with the semiconductor channel 12 (for example, the hatched portion in FIG. 1A ) are heavily doped with impurities, for example, n-type or p-type doping (doped region). The vicinity of the connection portion with the semiconductor channel 12 is not doped with impurities (undoped region), but may have a low concentration of n-type or p-type.

[0020] In the source region 11 and the drain region 13, a source electrode and a drain electrode (not shown) are disposed on a part of the surface of the region doped with impurities.

[0021] The length (x direction) of the semiconductor channel 12 is preferably 100 nm or more and 1 μm or less, and preferably 100 to several hundreds of nm. The width (y direction) of the semiconductor channel 12 is preferably 10 nm or more and 100 nm or less, and preferably 10 to several tens of nm. The thickness (z direction) of the semiconductor channel 12 is preferably 10 nm or more and 100 nm or less, and preferably 10 to several tens of nm.

[0022] The length of each of the first gate 14 and the second gate 15 in the direction in which the semiconductor channel 12 extends (x direction) is preferably 10 nm to 200 nm, more preferably 10 to 100 plus several tens of nm.

[0023] The distance between the first gate 14 and the second gate 15 is preferably 10 nm or more and 200 nm or less, and more preferably 10 to 100 plus several tens of nm.

[0024] The top gate 16 is configured to cover the first gate 14 , the second gate 15 and the semiconductor channel 12 .

[0025] The upper gate 16, the first gate 14, and the second gate 15 are preferably made of a highly conductive material, such as a semiconductor doped with a high concentration of impurities or a metal such as aluminum.

[0026] In the charge-coupled device 10, a first gate electrode 14 and a second gate electrode 15 are formed on the semiconductor channel 12 to form a first field effect transistor (FET) 17 and a second FET 18 (shown by dotted lines in the figure).

[0027] <Operation of Charge-Coupled Device> The operation of the charge-coupled device 10 according to this embodiment will be described.

[0028] The value of the current flowing from the source region 11 to the drain region 13 is determined by the charge transfer current due to the high-frequency voltage (which may be a pulse voltage or a sine wave) applied to the first gate 14 or the second gate 15 and the recombination current in the PN junction region (near the boundary between the p-type doped region and the undoped region and near the boundary between the n-type doped region and the undoped region). Here, the charge transfer current is a current generated by the transfer of charges. Charge transfer refers to the movement of electrons from the n-type semiconductor region (source region 11) to the p-type semiconductor region (drain region 13), or the movement of holes from the p-type semiconductor region (drain region 13) to the n-type semiconductor region (source region 11).

[0029] In the charge-coupled device 10, recombination is fast in the PN junction region, and charge transfer is slow. As a result, the current flowing through the charge-coupled device 10 is determined by the current due to the slower charge transfer. To speed up recombination in the PN junction region, a forward bias voltage approximately equal to the band gap of the semiconductor material constituting the source region 11 or drain region 13 (e.g., band gap of approximately ±0.1 V) is applied to the source region 11 or drain region 13. For example, when silicon (band gap 1.1 eV) is used as the semiconductor material, a voltage of approximately 1 V is applied to the p-type drain region 13, or a voltage of approximately −1 V is applied to the n-type source region 11.

[0030] When transferring electrons, a voltage of about 1 V is applied to the upper gate 16 to induce electrons in the semiconductor thin-wire channel region, while when transferring holes, a voltage of about −1 V is applied to the upper gate 16 to induce holes in the semiconductor thin-wire channel region.

[0031] In this way, by applying a voltage to the drain region 13 or the source region 11, recombination of electrons and holes occurs near the p-type drain region 13 in the case of electrons, and near the n-type source region 11 in the case of holes, and the recombination current becomes sufficiently large.

[0032] In a state where this recombination current is increasing, i.e., where recombination is fast, a radio frequency voltage is applied to the first gate 14 or the second gate 15. When transferring electrons, the radio frequency voltage is applied to the gate electrode (first gate 14) close to the n-type source region 11. When transferring holes, the radio frequency voltage is applied to the gate electrode (second gate 15) close to the p-type drain region 13. The frequency to be applied is preferably about 10 MHz to 10 GHz.

[0033] For example, when recombination is slow in the charge-coupled device 10, electrons accumulate near the boundary between the doped and undoped regions in the p-type drain region 13. The accumulation of a large number of electrons makes charge transfer difficult. Alternatively, electrons may flow backward (from the drain region 13 toward the source region 11). Therefore, by increasing the recombination rate in the charge-coupled device 10, electron accumulation near the boundary between the p-type drain region 13 and the undoped region can be suppressed, making it easier to transfer charge.

[0034] In addition, a DC voltage is applied to the gate to which the radio frequency voltage is not applied. This makes it possible to suppress the flow of charges other than the transferred charges between the source and drain. When transferring electrons, a DC voltage of about -1 V is applied to the gate electrode (second gate 15) close to the p-type drain region 13. When transferring holes, a DC voltage of about 1 V is applied to the gate electrode (first gate 14) close to the n-type source region 11.

[0035] For example, when no DC voltage is applied to either the first gate 14 or the second gate 15, i.e., when the first FET 17 and the second FET 18 are ON, a current flows in a normal transistor operation. By applying a DC voltage to the gate electrodes to which no high-frequency voltage is applied, the current in such a normal transistor operation can be suppressed.

[0036] One electron or hole is trapped in the region between the first gate 14 and the second gate 15 per clock cycle and is subsequently released.

[0037] For example, in the case of electron transfer, a DC voltage is applied to the second gate 15 to turn the second FET OFF, and a high frequency voltage is applied to the first gate 14. The behavior of electrons during one cycle of the high frequency voltage will be described below.

[0038] First, when the voltage (high frequency voltage) of the first gate 14 is low (for example, 0 V), the first FET 17 is in the ON state, and electrons flow into the region between the first gate 14 and the second gate 15 .

[0039] Next, when the voltage applied to the first gate 14 increases and the first FET 17 is turned OFF, the electrons accumulated in the region between the first gate 14 and the second gate 15 repel each other, and one electron is accumulated.

[0040] Furthermore, as the voltage applied to the first gate 14 increases, the barrier in the first FET 17 becomes higher, and as a result, one electron is emitted to the drain region 13. In this manner, a single electron is transferred from the source region 11 to the drain region 13 in one cycle of the high-frequency voltage applied to the first gate 14.

[0041] The resulting current value is much smaller than the recombination current, so the current flowing between the source and drain is determined by the single charge transfer current.

[0042] In order to confine one single charge (electron or hole) between the first gate 14 and the second gate 15, the thermal energy must be sufficiently smaller than the Coulomb blockade energy, so an operating temperature of approximately 10 Kelvin or less is desirable.

[0043] According to this embodiment, in the charge transfer device, electrons and holes can be selected and a single charge can be transferred with high precision by a single device.

[0044] In the present embodiment, an example has been shown in which the source region is made of an n-type semiconductor and the drain region is made of a p-type semiconductor, but this is not limiting, and the source region may be made of a p-type semiconductor and the drain region may be made of an n-type semiconductor.

[0045] Second Embodiment A charge-coupled device according to a second embodiment of the present invention will be described with reference to FIGS. 2A and 2B.

[0046] 2A and 2B, the charge-coupled device 20 according to this embodiment includes, in the horizontal direction (x direction in the drawings), a source region 11, a semiconductor channel 12, and a drain region 13, in that order, as in the first embodiment. The semiconductor channel 12 extends in the x direction and is electrically connected to the source region 11 and the drain region 13.

[0047] Charge-coupled device 20 comprises, in order in a direction perpendicular to the surface of substrate 101 (z direction in the drawing), substrate 101, lower insulating film 102, semiconductor channel 12, and upper insulating film 103, and comprises first gate 14 and second gate 15 within upper insulating film 103. Charge-coupled device 20 differs from the first embodiment in that it does not comprise an upper gate.

[0048] In fabricating the charge-coupled device 20, the source region 11 and the drain region 13 must be formed with a mask such as resist on the semiconductor thin-wire channel so as to prevent impurities from being introduced into the semiconductor thin-wire channel.

[0049] In the operation of the charge-coupled device 20, the charge induced at the upper gate in the first embodiment is induced by a voltage applied to the substrate 101. Other operations are the same as those in the first embodiment.

[0050] According to this embodiment, in a charge-transfer device, a single charge can be transferred simultaneously with high precision by selecting electrons and holes with a simpler configuration than that of the first embodiment.

[0051] In this embodiment, similarly to the first embodiment, the source region may be made of an n-type semiconductor and the drain region may be made of a p-type semiconductor, or the source region may be made of a p-type semiconductor and the drain region may be made of an n-type semiconductor.

[0052] Third Embodiment A charge-coupled device according to a third embodiment of the present invention will be described with reference to FIG.

[0053] 3, the charge-coupled device 30 according to this embodiment includes, in the horizontal direction (the x-direction in the figure), a source region 31, a semiconductor channel 12, and a drain region 33. The semiconductor channel 12 extends in the x-direction and is electrically connected to both the source region 31 and the drain region 33.

[0054] In the source region 31, regions to be doped with impurities are separated, one of which is doped with n-type impurities (first source region 311) and the other of which is doped with p-type impurities (second source region 312).

[0055] In the drain region 33, the regions to be doped with impurities are separated, one of which is doped with n-type impurities (first drain region 331) and the other of which is doped with p-type impurities (second drain region 332).

[0056] The configuration other than the source region 31 and the drain region 33 is the same as that of the first embodiment.

[0057] In the charge-coupled device 30, the layer structure in the direction perpendicular to the surface of the substrate 101 (z direction in the drawing) is the same as that in the first embodiment.

[0058] <Operation of Charge-Coupled Device> The operation of the charge-coupled device 30 according to this embodiment will be described.

[0059] First, in the charge-coupled device 30, a voltage is applied to the upper gate 16 to induce electrons or holes, as in the first embodiment.

[0060] Next, when transferring electrons, similarly to the first embodiment, a high frequency voltage is applied to the first gate 14 and a DC voltage is applied to the second gate 15. This allows a single electron to be transferred to the second drain region 332.

[0061] Furthermore, a DC voltage is applied to the first gate 14, and a high frequency voltage is applied to the second gate 15. This allows a single electron to be transferred to the second source region 312.

[0062] In this manner, a single electron can be transferred in both directions between the second source region 312 and the second drain region 332 .

[0063] On the other hand, when transferring holes, a high frequency voltage is applied to the first gate 14 and a DC voltage is applied to the second gate 15. This allows a single hole to be transferred to the first drain region 331.

[0064] Furthermore, a DC voltage is applied to the first gate 14, and a high frequency voltage is applied to the second gate 15. This allows a single hole to be transferred to the first source region 311.

[0065] In this way, a single hole can be transferred in both directions between the first source region 311 and the first drain region 331 .

[0066] According to this embodiment, in a charge-transfer device, electrons and holes can be selected and a single charge can be transferred with high precision using a single device. Furthermore, while the first embodiment allows a single charge to be transferred only in one direction, this embodiment allows a single charge to be transferred in both directions.

[0067] In this embodiment, an example has been shown in which the configuration and layer configuration other than the source region and drain region are the same as those in the first embodiment, but this is not limiting and the same configuration as that in the second embodiment may also be used.

[0068] In this embodiment, an example in which Si is used for the substrate is shown, but the present invention is not limited to this. Other semiconductor substrates, dielectric substrates, glass substrates, etc. may also be used for the substrate.

[0069] In this embodiment, the insulator is SiO ２ However, the present invention is not limited to this example, and other insulating materials such as SiN may also be used.

[0070] In this embodiment, an example has been shown in which Si is used as the semiconductor, but this is not limiting, and other semiconductors such as GaAs may also be used.

[0071] In the embodiments of the present invention, examples of the structure, dimensions, materials, etc. of each component in the configuration and manufacturing method of the charge-coupled device are shown, but the present invention is not limited to these examples. Anything that can demonstrate the function and effect of the charge-coupled device can be used.

[0072] It should be noted that the present invention is not limited to the above-described embodiments, and it is clear that many modifications and combinations can be made by a person having ordinary knowledge in the art within the technical concept of the present invention.

[0073] A part or all of the above-described embodiment or an example thereof can be described as, but is not limited to, the following supplementary notes.

[0074] (Supplementary Note 1) A charge-transfer device comprising, in this order, a substrate, a lower insulating film, a semiconductor channel, and an upper insulating film; and, disposed within the lower insulating film or the upper insulating film, a first gate, a second gate, a source region electrically connected to one end of the semiconductor channel, and a drain region electrically connected to the other end of the semiconductor channel; the first gate and the second gate are disposed above the semiconductor channel in parallel with each other in a direction in which the semiconductor channel extends; the source region is made of either a p-type semiconductor or an n-type semiconductor; and the drain region is made of a semiconductor of a conductivity type opposite to that of the source region.

[0075] (Appendix 2) A charge-transfer device as described in Appendix 1, wherein a forward bias is applied between the source region and the drain region, a high-frequency voltage is applied to one of the first gate and the second gate that is closer to the n-type source region, and a DC voltage is applied to the other gate, and a single electron is transferred to the p-type drain region.

[0076] (Appendix 3) A charge transfer element as described in Appendix 1 or Appendix 2, wherein a forward bias is applied between the source region and the drain region, a high frequency voltage is applied to one of the first gate and the second gate that is closer to the p-type source region, and a DC voltage is applied to the other gate, and a single hole is transferred to the n-type drain region.

[0077] (Supplementary Note 4) A charge-transfer device comprising, in this order, a substrate, a lower insulating film, a semiconductor channel, and an upper insulating film; and, disposed within the lower insulating film or the upper insulating film, a first gate, a second gate, a source region electrically connected to one end of the semiconductor channel, and a drain region electrically connected to the other end of the semiconductor channel; the first gate and the second gate are disposed above the semiconductor channel in parallel with each other in a direction in which the semiconductor channel extends; the source region comprises a first source region made of a p-type semiconductor and a second source region made of an n-type semiconductor; and the drain region comprises a first drain region made of a p-type semiconductor and a second drain region made of an n-type semiconductor.

[0078] (Appendix 5) A charge transfer element as described in Appendix 4, wherein a high frequency voltage is applied to one of the first gate and the second gate that is farther from either the second source region or the second drain region, and a DC voltage is applied to the other gate, and a single electron is transferred to either the second source region or the second drain region.

[0079] (Appendix 6) A charge transfer element as described in Appendix 4 or Appendix 5, wherein a high-frequency voltage is applied to one of the first gate and the second gate that is farther from either the first source region or the first drain region, and a DC voltage is applied to the other gate, and a single hole is transferred to either the first source region or the first drain region.

[0080] (Supplementary Note 7) The charge-transfer device according to any one of Supplementary Notes 1 to 6, further comprising an upper gate on a surface of the upper insulating film opposite to the semiconductor channel.

[0081] (Appendix 8) A charge transfer element according to any one of Appendices 1 to 7, wherein the length of the semiconductor channel in the extension direction is 100 nm or more and 1 μm or less, the width of the semiconductor channel is 10 nm or more and 100 nm or less, and the thickness of the semiconductor channel is 10 nm or more and 100 nm or less.

[0082] (Supplementary Note 9) The charge-transfer device according to any one of Supplementary Notes 1 to 8, wherein the length of each of the first gate and the second gate in the direction in which the semiconductor channel extends is 10 nm or more and 200 nm or less.

[0083] (Appendix 10) The charge-transfer device according to any one of Appendices 1 to 9, wherein the distance between the first gate and the second gate is 10 nm or more and 200 nm or less.

[0084] The present invention can be applied to a high-precision current source (current standard).

[0085] 10 Charge-coupled device 101 Substrate 102 Lower insulating film 103 Upper insulating film 11 Source region 12 Semiconductor channel 13 Drain region 14 First gate 15 Second gate

Claims

1. A charge transfer device comprising, in order, a substrate, a lower insulating film, a semiconductor channel, and an upper insulating film; a first gate and a second gate, which are disposed within the lower insulating film or the upper insulating film, a source region electrically connected to one end of the semiconductor channel, and a drain region electrically connected to the other end of the semiconductor channel; the first gate and the second gate are disposed above the semiconductor channel in parallel with each other in the direction in which the semiconductor channel extends; the source region is made of either a p-type semiconductor or an n-type semiconductor; and the drain region is made of a semiconductor of a conductivity type opposite to that of the source region.

2. The charge transfer device of claim 1, wherein a forward bias is applied between the source region and the drain region, a high frequency voltage is applied to one of the first gate and the second gate that is closer to the n-type source region, and a DC voltage is applied to the other gate, and a single electron is transferred to the p-type drain region.

3. A charge transfer device according to claim 1 or claim 2, wherein a forward bias is applied between the source region and the drain region, a radio frequency voltage is applied to one of the first gate and the second gate that is closer to the p-type source region, and a DC voltage is applied to the other gate, and a single hole is transferred to the n-type drain region.

4. A charge transfer device comprising, in order: a substrate; a lower insulating film; a semiconductor channel; and an upper insulating film; and, arranged in the lower insulating film or the upper insulating film, a first gate and a second gate; a source region electrically connected to one end of the semiconductor channel; and a drain region electrically connected to the other end of the semiconductor channel; the first gate and the second gate are arranged above the semiconductor channel in parallel with each other in the direction in which the semiconductor channel extends; the source region comprises a first source region made of a p-type semiconductor and a second source region made of an n-type semiconductor; and the drain region comprises a first drain region made of a p-type semiconductor and a second drain region made of an n-type semiconductor.

5. The charge transfer device of claim 4, wherein a high frequency voltage is applied to one of the first gate and the second gate that is farther from either the second source region or the second drain region, and a DC voltage is applied to the other gate, and a single electron is transferred to either the second source region or the second drain region.

6. A charge transfer device as claimed in claim 4 or claim 5, wherein a radio frequency voltage is applied to one of the first gate and the second gate that is farther from either the first source region or the first drain region, and a DC voltage is applied to the other gate, and a single hole is transferred to either the first source region or the first drain region.

7. The charge-transfer device according to claim 1 or 4, further comprising an upper gate on a surface of said upper insulating film opposite to said semiconductor channel.

8. A charge-transfer device according to claim 1 or claim 4, wherein the length of the semiconductor channel in the direction of extension is 100 nm or more and 1 μm or less, the width of the semiconductor channel is 10 nm or more and 100 nm or less, and the thickness of the semiconductor channel is 10 nm or more and 100 nm or less.

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