Multilayer ceramic capacitor

Abstract

[Problem] To provide a multilayer ceramic capacitor that makes it possible to suppress wet spread of solder to a surface on the side opposite from a mounting surface at the time of mounting. [Solution] A multilayer ceramic capacitor 10 according to the present invention comprises: a multilayer body that has a first surface and a second surface that are on opposite sides from each other in a stacking direction, a third surface and a fourth surface that are on opposite sides from each other in a first direction orthogonal to the stacking direction, and a fifth surface and a sixth surface that are on opposite sides from each other in a second direction orthogonal to both the stacking direction and the first direction; a first external electrode that is disposed on the first surface and the third surface; a second external electrode that is disposed on the first surface and the fourth surface; a third external electrode that is disposed on the first surface and the third surface; and a fourth external electrode that is disposed on the first surface and the fourth surface. The multilayer body includes a first internal electrode and a second internal electrode. The first external electrode includes a first base layer that is connected to the first internal electrode, a first thin film layer that is disposed on the first surface, and a first surface plating layer. The first external electrode has a first recess that is positioned inside the multilayer body, the first recess being longer in the second direction than in the first direction.

Description

Multilayer ceramic capacitors

[0001] The present invention relates to a multilayer ceramic capacitor.

[0002] In recent years, electronic devices such as mobile phones and portable music players have become smaller and thinner. Accordingly, the multilayer ceramic capacitors mounted in these smaller and thinner electronic devices have also become smaller and thinner (see Patent Document 1). In particular, multilayer ceramic capacitors that have become thinner are now being used by being built into wiring boards, or even when mounted on the surface of a wiring board, they are being mounted in very narrow spaces.

[0003] Japanese Patent Application Laid-Open No. 2021-101449

[0004] The multilayer ceramic capacitor described in Patent Document 1 and the like has an external shape that is approximately tetragonal and has a thin thickness in the lamination direction. When the thickness in the lamination direction is thin, the solder used during mounting may excessively wet up in a direction perpendicular to the mounting surface, and may wet up to the surface opposite the mounting surface of the multilayer ceramic capacitor, which may increase the mounting height by the amount of solder wet up.

[0005] SUMMARY OF THE INVENTION Therefore, a primary object of the present invention is to provide a multilayer ceramic capacitor that can prevent solder from wetting onto the surface opposite the mounting surface during mounting.

[0006] A multilayer ceramic capacitor according to the present invention includes a laminate having a first surface and a second surface opposed to each other in a stacking direction, a third surface and a fourth surface opposed to each other in a first direction perpendicular to the stacking direction, and a fifth surface and a sixth surface opposed to each other in a second direction perpendicular to the stacking direction and the first direction; first external electrodes arranged on the first surface and the third surface; second external electrodes arranged on the first surface and the fourth surface; a third external electrode arranged on the first surface and the third surface; and a fourth external electrode disposed on the first surface and the fourth surface, wherein the laminate includes a first internal electrode and a second internal electrode, the first external electrode includes a first base layer connected to the first internal electrode, a first thin film layer disposed on the first surface, and a first surface plating layer, the first external electrode has a first recess located inside the laminate, and the first recess is longer in the second direction than in the first direction.

[0007] In the multilayer ceramic capacitor according to the present invention, the first external electrode includes a first base layer connected to the first internal electrode, a first thin film layer disposed on the first surface, and a first surface plating layer, and the first external electrode has a first recess located inside the laminate, and the first recess is longer in the second direction than in the first direction. Therefore, during mounting, this first recess can prevent solder from wetting up from the first surface to the external electrode disposed on the surface opposite in the second direction.

[0008] According to the present invention, a multilayer ceramic capacitor is provided that can prevent solder from wetting onto the surface opposite the mounting surface during mounting.

[0009] The above and other objects, features, and advantages of the present invention will become more apparent from the following detailed description of the preferred embodiments of the invention, which proceeds with reference to the accompanying drawings.

[0010] 6A is an external perspective view showing an example of a multilayer ceramic capacitor according to a first embodiment of the present invention; FIG. 6B is an external perspective view, seen from another side, of an example of a multilayer ceramic capacitor according to the first embodiment of the present invention; FIG. 6C is an external perspective view, seen from another side, of an example of a multilayer ceramic capacitor according to the first embodiment of the present invention; FIG. 6D is a front view showing an example of a multilayer ceramic capacitor according to the first embodiment of the present invention; FIG. 6E is a side view showing an example of a multilayer ceramic capacitor according to the first embodiment of the present invention; FIG. 6F is a cross-sectional view taken along line IV-IV in FIG. 1A; FIG. 6G is a cross-sectional view taken along line V-V in FIG. 1A; FIG. 6H is a cross-sectional view taken along line VI-VI in FIG. 1A; FIG. 6I is a cross-sectional view taken along line VII-VII in FIG. 1A; FIG. 6J is an enlarged view of part A in FIG. 6A, illustrating a schematic structure of an underlayer; and FIG. 6B is an enlarged view of part A in FIG. 6A, illustrating a schematic structure of an Sn plating. 11A ; 11B ; 11C ; 11D ; 11E ; 11F ; 11G ; 11H ; 11H ; 11I ... FIG. 19B is a cross-sectional view taken along line XXIII-XXIII in FIG. 19A.

[0011] A. First Embodiment 1. Multilayer Ceramic Capacitor Next, an example of a multilayer ceramic capacitor 10 according to an embodiment of the present invention will be described.

[0012] FIG. 1A is an external perspective view showing an example of a multilayer ceramic capacitor according to a first embodiment of the present invention. FIG. 1B is an external perspective view from another side showing an example of a multilayer ceramic capacitor according to the first embodiment of the present invention. FIG. 2 is a front view showing an example of a multilayer ceramic capacitor according to the first embodiment of the present invention. FIG. 3 is a side view showing an example of a multilayer ceramic capacitor according to the first embodiment of the present invention. FIG. 4 is a cross-sectional view taken along line IV-IV in FIG. 1A. FIG. 5 is a cross-sectional view taken along line V-V in FIG. 1A. FIG. 6 is a cross-sectional view taken along line VI-VI in FIG. 1A. FIG. 7 is a cross-sectional view taken along line VII-VII in FIG. 1A. FIG. 8(a) is an enlarged view of portion A in FIG. 6, illustrating a schematic structure of the underlayer. FIG. 8(b) is an enlarged view of portion A in FIG. 6, illustrating a schematic structure of the Sn plating. FIG. 9A is a cross-sectional view taken along line IXA-IXA in FIG. 2. Fig. 9B is a schematic cross-sectional view taken along line IXB-IXB in Fig. 2. Fig. 10 is an exploded perspective view of the laminate shown in Fig. 1A.

[0013] The multilayer ceramic capacitor 10 includes a laminate 12 and a plurality of external electrodes 30 .

[0014] (Laminate) The laminate 12 has a first surface 12a and a second surface 12b facing in a stacking direction x, a third surface 12c and a fourth surface 12d facing in a first direction y perpendicular to the stacking direction x, and a fifth surface 12e and a sixth surface 12f facing in a second direction z perpendicular to the stacking direction x and the first direction y. The direction connecting the first surface 12a and the second surface 12b of the laminate 12 is the stacking direction x.

[0015] Furthermore, it is preferable that the corners and ridges of the laminate 12 are rounded. Note that the corners refer to the portions where three adjacent faces of the laminate 12 intersect, and the ridges refer to the portions where two adjacent faces of the laminate 12 intersect. Furthermore, unevenness may be formed on part or all of the third face 12c, the fourth face 12d, and the fifth face 12e and the sixth face 12f.

[0016] In addition, either the first surface 12a or the second surface 12b may have a roughened surface.

[0017] The laminate 12 includes a plurality of dielectric layers 14 and a plurality of internal electrodes 16. The dielectric layers 14 include an inner dielectric layer 14a and an outer dielectric layer 14b. The internal electrodes 16 include a first internal electrode 16a and a second internal electrode 16b.

[0018] The laminate 12 also has an inner layer portion 18, a first outer layer portion 20a located on the first surface 12a side, and a second outer layer portion 20b located on the second surface 12b side.

[0019] The first outer layer portion 20a is located on the first surface 12a side of the laminate 12 and is an aggregate of multiple outer dielectric layers 14b located between the first surface 12a and the internal electrode 16 closest to the first surface 12a.

[0020] The second outer layer portion 20b is located on the second surface 12b side of the laminate 12 and is an aggregate of multiple outer dielectric layers 14b located between the second surface 12b and the internal electrode 16 closest to the second surface 12b.

[0021] The region sandwiched between the first outer layer portion 20a and the second outer layer portion 20b is the inner layer portion 18.

[0022] The inner layer portion 18 has a first inner electrode 16a having one end exposed to the third surface 12c and the fifth surface 12e and the other end exposed to the fourth surface 12d and the sixth surface 12f, a second inner electrode 16b having one end exposed to the third surface 12c and the sixth surface 12f and the other end exposed to the fourth surface 12d and the fifth surface 12e, and an inner layer dielectric layer 14a.

[0023] The dielectric layer 14 can be formed from, for example, a dielectric material. Examples of the dielectric material include dielectric ceramics primarily composed of BaTiO3, CaTiO3, SrTiO3, or CaZrO3. Substituents such as Mn compounds, Fe compounds, Cr compounds, Co compounds, and Ni compounds may also be added to these primary components. The inner dielectric layer 14a and the outer dielectric layer 14b may be made of the same dielectric material, or may be made of different dielectric materials to separate the functions of the inner layer 18 and the outer layer 20a, 20b. At least one of Si, Mg, Ba, and Mn may also be added as an additive.

[0024] For example, if the inner dielectric layer 14a contains a large amount of CaTiO3 or CaZrO3 as a dielectric component, it can make it less likely for dielectric breakdown to occur between the first inner electrode 16a and the second inner electrode 16b. Furthermore, without being limited thereto, the inner dielectric layer 14a can also be mainly composed of SrTiO3 or the like. Separately, in order to increase the capacitance of the multilayer ceramic capacitor 10, it is preferable for the layer 14a to be made of a material with a high dielectric constant, such as BaTiO3. It is preferable that the outer dielectric layer 14b be made of the same type of component as the inner dielectric layer 14a.

[0025] The dielectric layer 14 may have a plurality of crystal grains containing a perovskite-type compound having a basic structure of BaTiO3.

[0026] The thinner the dielectric layer 14, the greater the capacitance of the capacitor, so the crystal grain size is preferably 1 μm or less.

[0027] The number of dielectric layers 14 to be laminated is not particularly limited, but is preferably 3 to 300, including the first outer layer portion 20a and the second outer layer portion 20b. The thickness of the inner dielectric layer 14a is preferably 0.4 μm to 2.0 μm, and the thickness of the outer dielectric layer 14b is preferably 2.0 μm to 100.0 μm.

[0028] When the direction in which the third surface 12c and the fourth surface 12d face each other is defined as a first direction y and the direction in which the fifth surface 12e and the sixth surface 12f face each other is defined as a second direction z, the dimension L of the laminate 12 in the first direction y and the dimension W of the laminate 12 in the second direction z satisfy the condition 0.85≦L / W≦1.00. In other words, the laminate 12 has a substantially tetragonal shape.

[0029] (Internal Electrode) The internal electrode 16 includes a plurality of first internal electrodes 16a and a plurality of second internal electrodes 16b. The first internal electrodes 16a and the second internal electrodes 16b are alternately stacked with the dielectric layer 14 interposed therebetween.

[0030] The first internal electrode 16a is disposed on the surface of the inner dielectric layer 14a. The first internal electrode 16a faces the first surface 12a and the second surface 12b, has a first opposing electrode portion 22a facing the second internal electrode 16b, and is laminated in the direction connecting the first surface 12a and the second surface 12b.

[0031] The first internal electrode 16a is extended to the third surface 12c and the fifth surface 12e of the laminate 12 by a first extension electrode portion 24a, and is extended to the fourth surface 12d and the sixth surface 12f of the laminate 12 by a second extension electrode portion 24b. The width of the first extension electrode portion 24a extended to the third surface 12c may be approximately equal to the width of the first extension electrode portion 24a extended to the fifth surface 12e, and the width of the second extension electrode portion 24b extended to the fourth surface 12d may be approximately equal to the width of the second extension electrode portion 24b extended to the sixth surface 12f.

[0032] Furthermore, the first internal electrode 16a is continuously extended to the third surface 12c and the fifth surface 12e of the laminate 12 by the first extension electrode portion 24a, and is continuously extended to the fourth surface 12d and the sixth surface 12f of the laminate 12 by the second extension electrode portion 24b, but this is not limited to this and the electrode may be extended discontinuously.

[0033] The second internal electrode 16b is disposed on a surface of the inner dielectric layer 14a different from the surface of the inner dielectric layer 14a on which the first internal electrode 16a is disposed. The second internal electrode 16b faces the first surface 12a and the second surface 12b, has a second opposing electrode portion 22b facing the first internal electrode 16a, and is laminated in a direction connecting the first surface 12a and the second surface 12b.

[0034] The second internal electrode 16b is extended to the third surface 12c and the sixth surface 12f of the laminate 12 by the third extension electrode portion 24c, and is extended to the fourth surface 12d and the fifth surface 12e of the laminate 12 by the fourth extension electrode portion 24d. The width of the third extension electrode portion 24c extended to the third surface 12c may be approximately equal to the width of the third extension electrode portion 24c extended to the sixth surface 12f, and the width of the fourth extension electrode portion 24d extended to the fourth surface 12d may be approximately equal to the width of the fourth extension electrode portion 24d extended to the fifth surface 12e.

[0035] Furthermore, the second internal electrode 16b is continuously extended to the third surface 12c and the sixth surface 12f of the laminate 12 by the third extension electrode portion 24c, and is continuously extended to the fourth surface 12d and the fifth surface 12e of the laminate 12 by the fourth extension electrode portion 24d, but this is not limited to this and the second internal electrode 16b may be extended discontinuously.

[0036] Furthermore, when the multilayer ceramic capacitor 10 is viewed from the stacking direction x, it is preferable that a straight line connecting the first extraction electrode portion 24a and the second extraction electrode portion 24b of the first internal electrode 16a intersects with a straight line connecting the third extraction electrode portion 24c and the fourth extraction electrode portion 24d of the second internal electrode 16b.

[0037] As shown in FIG. 7 , the laminate 12 also includes a side portion (W gap) 26 a of the laminate 12 located between one end in the first direction y of the second opposing electrode portion 22 b of the second internal electrode 16 b and the third surface 12 c, and a side portion (W gap) 26 b of the laminate 12 located between the other end in the first direction y of the first opposing electrode portion 22 a of the first internal electrode 16 a and the fourth surface 12 d.

[0038] Furthermore, as shown in FIG. 6 , the laminate 12 includes an end portion (L gap) 27 a of the laminate 12 located between one end in the second direction z of the second opposing electrode portion 22 b of the second internal electrode 16 b and the fifth surface 12 e, and a side portion (L gap) 27 b of the laminate 12 located between the other end in the second direction z of the first opposing electrode portion 22 a of the first internal electrode 16 a and the sixth surface 12 f.

[0039] The first internal electrode 16a and the second internal electrode 16b can be made of an appropriate conductive material, such as, for example, metals such as Ni, Cu, Ag, Pd, and Au, or alloys containing at least one of these metals, such as Ni-Cu alloys and Ag-Pd alloys, but are not limited thereto. Furthermore, the first internal electrode 16a and the second internal electrode 16b may be made of the same conductive material or different conductive materials.

[0040] Furthermore, by including a Sn layer at the interface between the first internal electrode 16a and the second internal electrode 16b and the dielectric layer 14, electric field concentration at the interface between the internal electrode 16 and the dielectric layer 14 can be alleviated, leading to improved high-temperature load reliability.

[0041] The total number of the first internal electrodes 16a and the second internal electrodes 16b is preferably 3 to 300. The thickness of the first internal electrodes 16a and the second internal electrodes 16b is not particularly limited, but is preferably 0.2 μm to 2.0 μm, for example.

[0042] The laminate 12 of the multilayer ceramic capacitor 10 may have the following configuration.

[0043] In the multilayer ceramic capacitor 10, the third surface 12c to the sixth surface 12f of the laminate 12 may be curved so as to form a concave shape toward the center of the laminate 12 when viewed in the stacking direction x. In other words, the third surface 12c to the sixth surface 12f of the laminate 12 may have a warped shape. In this case, it is preferable that the center of the curvature or warpage is near the center of the third surface 12c to the sixth surface 12f. This allows the distance between adjacent external electrodes 30, which will be described later, to be increased, thereby reducing the risk of electrical conduction between the external electrodes 30.

[0044] Furthermore, when viewed in at least one of the first direction y and the second direction z, the regions where the internal electrodes 16 are drawn out onto the third surface 12c to the sixth surface 12f preferably have a curved shape from the first surface 12a to the second surface 12b, thereby increasing the exposed area of ​​the internal electrodes 16 and improving the contact area between the internal electrodes 16 and the external electrodes 30.

[0045] 1 to 7, external electrodes 30 are arranged on the laminate 12. The external electrodes 30 include a plurality of external electrodes 30 connected to the first internal electrodes 16a and the second internal electrodes 16b. The external electrodes 30 include a first external electrode 30a, a second external electrode 30b, a third external electrode 30c, and a fourth external electrode 30d.

[0046] The first external electrode 30a is disposed on the third surface 12c and the fifth surface 12e so as to cover the first lead electrode portion 24a of the first internal electrode 16a, and further so as to cover a part of the first surface 12a and a part of the second surface 12b. The first external electrode 30a is electrically connected to the first lead electrode portion 24a of the first internal electrode 16a.

[0047] The second external electrode 30b is disposed on the fourth surface 12d and the sixth surface 12f so as to cover the second lead electrode portion 24b of the first internal electrode 16a, and further so as to cover a part of the first surface 12a and a part of the second surface 12b. The second external electrode 30b is electrically connected to the second lead electrode portion 24b of the first internal electrode 16a.

[0048] The third external electrode 30c is disposed on the third surface 12c and the sixth surface 12f so as to cover the third lead electrode portion 24c of the second internal electrode 16b, and further so as to cover a part of the first surface 12a and a part of the second surface 12b. The third external electrode 30c is electrically connected to the third lead electrode portion 24c of the second internal electrode 16b.

[0049] The fourth external electrode 30d is disposed on the fourth surface 12d and the fifth surface 12e so as to cover the fourth lead electrode portion 24d of the second internal electrode 16b, and further so as to cover a part of the first surface 12a and a part of the second surface 12b. The fourth external electrode 30d is electrically connected to the fourth lead electrode portion 24d of the second internal electrode 16b.

[0050] When viewed from the stacking direction x, the external electrode 30 has a first recess 40 extending in the first direction y inside the laminate 12. The external electrode 30 may also have a second recess 42 extending in the second direction z inside the laminate 12.

[0051] More specifically, when the first external electrode 30a covers the first surface 12a, the second surface 12b, the third surface 12c, and the fifth surface 12e, when viewed in the stacking direction x from the first surface 12a side, the first external electrode 30a has a second recess 42a1 extending in the second direction z on the third surface 12c side, and a first recess 40a1 extending in the first direction y on the fifth surface 12e side. Furthermore, when the first external electrode 30a covers the first surface 12a, the second surface 12b, the third surface 12c, and the fifth surface 12e, when viewed in the stacking direction x from the second surface 12b side, the first external electrode 30a has a second recess 42a2 extending in the second direction z on the third surface 12c side, and a first recess 40a2 extending in the first direction y on the fifth surface 12e side.

[0052] When viewed in the stacking direction x from the first surface 12a, the dimension of the first recess 40a1 in the first direction y is 10% to 96.0% of the dimension in the first direction y of the first external electrode 30a in which the first recess 40a1 is formed, and more preferably 100% or less. Similarly, when viewed in the stacking direction x from the second surface 12b, the dimension of the first recess 40a2 in the first direction y is 10% to 96.0% of the dimension in the first direction y of the first external electrode 30a in which the first recess 40a2 is formed, and more preferably 100% or less. This makes it possible to prevent excessive wetting of the solder onto the fifth surface 12e. When the first recess 40a1 and the first recess 40a2 are arranged discontinuously, the dimensions of the first recess 40a1 and the first recess 40a2 in the first direction y are defined by their total lengths.

[0053] The first recess 40a1 is preferably located at a distance of 0.01 μm or more and 10.0 μm or less from the outermost surface of the fifth surface 12e of the laminate 12. Similarly, the first recess 40a2 is preferably located at a distance of 0.01 μm or more and 10.0 μm or less from the outermost surface of the fifth surface 12e of the laminate 12. In other words, the first recess 40a1 and the first recess 40a2 are located inside the laminate 12. This allows the first recess 40a1 to block or trap solder from wetting up from the first surface 12a to the external electrode 30 located on the surface opposite to the second direction z, thereby suppressing wetting up onto the fifth surface 12e.

[0054] The first recess 40a1 and the second recess 42a1 may be connected. Connecting the first recess 40a1 and the second recess 42a1 can also prevent solder from wetting up to the intersection of two adjacent surfaces. Similarly, the first recess 40a2 and the second recess 42a2 may be connected. Connecting the first recess 40a2 and the second recess 42a2 can also prevent solder from wetting up to the intersection of two adjacent surfaces. When viewed in the first direction y, the distance from the bottom surface of the first recess 40a1 to the apex of the surface plating layer 36 (described later) located outside the first recess 40a1 is preferably 1.0 μm or more.

[0055] When the second external electrode 30b covers the first surface 12a, the second surface 12b, the fourth surface 12d, and the sixth surface 12f, when viewed in the stacking direction x from the first surface 12a side, the second external electrode 30b has a second recess 42b1 extending in the second direction z on the fourth surface 12d side and a first recess 40b1 extending in the first direction y on the sixth surface 12f side. Furthermore, when the second external electrode 30b covers the first surface 12a, the second surface 12b, the fourth surface 12d, and the sixth surface 12f, as viewed in the stacking direction x from the second surface 12b side, the second external electrode 30b has a second recess 42b2 extending in the second direction z on the fourth surface 12d side and a first recess 40b2 extending in the first direction y on the sixth surface 12f side. The rest of the configuration of the second external electrode 30b is similar to that of the first external electrode 30a.

[0056] When the third external electrode 30c covers the first surface 12a, the second surface 12b, the third surface 12c, and the sixth surface 12f, when viewed in the stacking direction x from the first surface 12a side, the third external electrode 30c has a second recess 42c extending in the second direction z on the third surface 12c side and a first recess 40b extending in the first direction y on the sixth surface 12f side. Furthermore, when the third external electrode 30c covers the first surface 12a, the second surface 12b, the third surface 12c, and the sixth surface 12f, as viewed in the stacking direction x from the second surface 12b side, the third external electrode 30c has a second recess 42c2 extending in the second direction z on the third surface 12c side and a first recess 40c2 extending in the first direction y on the sixth surface 12f side. The rest of the configuration of the third external electrode 30c is similar to that of the first external electrode 30a.

[0057] When the fourth external electrode 30d covers the first surface 12a, the second surface 12b, the fourth surface 12d, and the fifth surface 12e, when viewed in the stacking direction x from the first surface 12a side, the fourth external electrode 30d has a second recess 42d extending in the second direction z on the fourth surface 12d side and a first recess 40d extending in the first direction y on the fifth surface 12e side. Furthermore, when the fourth external electrode 30d covers the first surface 12a, the second surface 12b, the fourth surface 12d, and the fifth surface 12e, as viewed in the stacking direction x from the second surface 12b side, the fourth external electrode 30d has a second recess 42d2 extending in the second direction z on the fourth surface 12d side and a first recess 40d2 extending in the first direction y on the fifth surface 12e side. The rest of the configuration of the fourth external electrode 30d is similar to that of the first external electrode 30a.

[0058] In the laminate 12, the first opposing electrode portion 22a of the first internal electrode 16a and the second opposing electrode portion 22b of the second internal electrode 16b face each other via the inner dielectric layer 14a, thereby forming a capacitance. Therefore, a capacitance can be obtained between the first external electrode 30a and the second external electrode 30b to which the first internal electrode 16a is connected and the third external electrode 30c and the fourth external electrode 30d to which the second internal electrode 16b is connected, thereby realizing the characteristics of a capacitor.

[0059] The first external electrode 30a, the second external electrode 30b, the third external electrode 30c, and the fourth external electrode 30d each have an underlayer 32, a thin film layer 34, and a surface plating layer 36.

[0060] In other words, the first external electrode 30a has a first base layer 32a, a first thin film layer 34a, and a first surface plating layer 36a. The second external electrode 30b has a second base layer 32b, a second thin film layer 34b, and a second surface plating layer 36b. The third external electrode 30c has a third base layer 32c, a third thin film layer 34c, and a third surface plating layer 36c. The fourth external electrode 30d has a fourth base layer 32d, a fourth thin film layer 34d, and a fourth surface plating layer 36d.

[0061] (Underlayer) The underlayer 32 is disposed on the third surface 12c to the sixth surface 12f. The specific configuration of the underlayer 32 will be described below.

[0062] The first underlayer 32a is arranged on the surfaces of the third surface 12c and the fifth surface 12e of the laminate 12 so as to cover the first extraction electrode portion 24a of the first internal electrode 16a exposed from the third surface 12c and the fifth surface 12e of the laminate 12.

[0063] The second underlayer 32b is arranged on the surfaces of the fourth surface 12d and the sixth surface 12f of the laminate 12 so as to cover the second extraction electrode portion 24b of the first internal electrode 16a exposed from the fourth surface 12d and the sixth surface 12f of the laminate 12.

[0064] The third underlayer 32c is arranged on the surfaces of the third surface 12c and the sixth surface 12f of the laminate 12 so as to cover the third extraction electrode portion 24c of the second internal electrode 16b exposed from the third surface 12c and the sixth surface 12f of the laminate 12.

[0065] The fourth base layer 32d is arranged on the surfaces of the fourth surface 12d and the fifth surface 12e of the laminate 12 so as to cover the fourth extraction electrode portion 24d of the second internal electrode 16b exposed from the fourth surface 12d and the fifth surface 12e of the laminate 12.

[0066] Preferably, the upper end of the first underlayer 32a of the first external electrode 30a is connected to the first thin film layer 34a on the ridge formed by the first surface 12a, the third surface 12c, and the fifth surface 12e of the laminate 12. Preferably, the lower end of the first underlayer 32a of the first external electrode 30a is connected to the first thin film layer 34a on the ridge formed by the second surface 12b, the third surface 12c, and the fifth surface 12e of the laminate 12. In this case, the first underlayer 32a may be disposed so as to cover the ridge formed by the third surface 12c and the fifth surface 12e.

[0067] Here, the structure of the first underlayer 32a of the first external electrode 30a will be described in detail with reference to FIG. 8(a). As shown in FIG. 8(a), the distance t1 in the stacking direction x between the end of the fifth surface 12e of the first underlayer 32a and the end of the internal electrode 16 closest to the first surface 12a that is exposed on the fifth surface 12e is preferably 3.0 μm or more and 8.1 μm or less. The first underlayer 32a is preferably disposed so as to extend toward the first surface 12a. In other words, the distance t2 in the stacking direction x between a point P on the outermost surface of the first surface 12a, located 1.0 μm inward from the fifth surface 12e, and the end of the first underlayer 32a in the stacking direction x is preferably 10.0 μm or less. It is preferable that the thickness t3 of the first underlayer 32a is 3.0 μm or more and 8.1 μm or less in the first direction y from the end exposed on the fifth surface 12e of the internal electrode 16 closest to the first surface 12a.

[0068] The upper end of the second underlayer 32b of the second external electrode 30b is preferably connected to the second thin film layer 34b on the ridge formed by the first surface 12a, the fourth surface 12d, and the sixth surface 12f of the laminate 12. The lower end of the second underlayer 32b of the second external electrode 30b is preferably connected to the second thin film layer 34b on the ridge formed by the second surface 12b, the fourth surface 12d, and the sixth surface 12f of the laminate 12. In this case, the second underlayer 32b may be disposed so as to cover the ridge formed by the fourth surface 12d and the sixth surface 12f. The rest of the configuration of the second external electrode 30b is similar to that of the first external electrode 30a.

[0069] The upper end of the third underlayer 32c of the third external electrode 30c is preferably connected to the third thin film layer 34c on the ridge formed by the first surface 12a, the third surface 12c, and the sixth surface 12f of the laminate 12. The lower end of the third underlayer 32c of the third external electrode 30c is preferably connected to the third thin film layer 34c on the ridge formed by the second surface 12b, the third surface 12c, and the sixth surface 12f of the laminate 12. In this case, the third underlayer 32c may be disposed so as to cover the ridge formed by the third surface 12c and the sixth surface 12f. The rest of the configuration of the third external electrode 30c is similar to that of the first external electrode 30a.

[0070] The upper end of the fourth underlayer 32d of the fourth external electrode 30d is preferably connected to the fourth thin film layer 34d on the ridge formed by the first surface 12a, the fourth surface 12d, and the fifth surface 12e of the laminate 12. The lower end of the fourth underlayer 32d of the fourth external electrode 30d is preferably connected to the fourth thin film layer 34d on the ridge formed by the second surface 12b, the fourth surface 12d, and the fifth surface 12e of the laminate 12. In this case, the fourth underlayer 32d may be disposed so as to cover the ridge formed by the fourth surface 12d and the fifth surface 12e. The rest of the configuration of the fourth external electrode 30d is similar to that of the first external electrode 30a.

[0071] The base layer 32 contains, for example, Cu as a main metal component. For example, when the first internal electrode 16 a and the second internal electrode 16 b are formed using Ni, it is preferable to adopt Cu plating as the base layer 32, which has good bonding properties with Ni.

[0072] The underlayer 32 is formed by plating growing from the internal electrode 16 .

[0073] The thickness of each of the underlayers 32 is preferably 0.5 μm or more and 10.0 μm or less.

[0074] (Thin Film Layers) The thin film layers 34 include a first thin film layer 34a, a second thin film layer 34b, a third thin film layer 34c, and a fourth thin film layer 34d.

[0075] The first thin film layer 34a covers a part of the first surface 12a and a part of the second surface 12b on the third surface 12c side and the fifth surface 12e side of the laminate 12. The first thin film layer 34a is preferably disposed in contact with the first base layer 32a.

[0076] The second thin film layer 34b covers a part of the first surface 12a and a part of the second surface 12b on the fourth surface 12d side and the sixth surface 12f side of the laminate 12. The second thin film layer 34b is preferably disposed in contact with the second base layer 32b.

[0077] The third thin film layer 34c covers a part of the first surface 12a and a part of the second surface 12b on the third surface 12c side and the sixth surface 12f side of the laminate 12. The third thin film layer 34c is preferably arranged in contact with the third base layer 32c.

[0078] The fourth thin film layer 34d covers the fourth surface 12d side and the fifth surface 12e side of the first surface 12a and the second surface 12b of the laminate 12. The fourth thin film layer 34d is preferably arranged in contact with the fourth base layer 32d.

[0079] Each of the first to fourth thin film layers 34 a to 34 d is preferably formed by depositing metal particles by sputtering, vapor deposition, etc. This allows the thickness of the first to fourth thin film layers 34 a to 34 d in the direction connecting the first surface 12 a and the second surface 12 b of the laminate 12 to be 1 μm or less, which allows the dimension of the multilayer ceramic capacitor 10 in the stacking direction x to be sufficiently small, thereby allowing the multilayer ceramic capacitor 10 to be made low-profile.

[0080] The dimensions of the first to fourth thin film layers 34a to 34d in the stacking direction x can be measured as follows. That is, when the thin film layers are formed by depositing metal particles, a fluorescent X-ray device can be used to convert the concentration of a predetermined element into a thickness using a calibration curve method for the corresponding metal species. Alternatively, a cross section of the component can be observed using an FIB with a scanning microscope, and the thickness can be measured from the actual observation image.

[0081] Furthermore, when the first to fourth thin film layers 34a to 34d are formed by a thin film forming method, these thin film layers are preferably made of a metal such as Cu or Ni.

[0082] The first to fourth thin film layers 34a to 34d can be configured taking into consideration their respective functions. For example, it is preferable that the main component be NiCr or NiCu in consideration of adhesion to the laminate 12. The first to fourth thin film layers 34a to 34d may be multiple layers or may have a two-layer structure of NiCr and NiCu.

[0083] The thin film layer 34 may be formed by screen printing or the like and contain a dielectric material and a metal component. This allows the thin film layer 34 to adhere to the ceramic of the laminate 12, further improving the adhesion between the laminate 12 and the external electrode 30. In this case, the thin film layer 34 may contain a ceramic component having the same main component as the inner dielectric layer 14a in addition to the metal component. The inclusion of a ceramic component in the thin film layer 34 reduces the difference in thermal expansion coefficient between the laminate 12 and the thin film layer 34, thereby alleviating stress on the thin film layer 34. However, the metal component may be other metal components besides Cu and Ni, or a glass component may be included in addition to the ceramic component. Examples of the glass component include oxides of Ba (barium), Sr (strontium), Si (silicon), Ca (calcium), Zn, Al, or B (boron). Other metal components may include Mg, Cr, Sr, Al, Na, Fe, etc. The thin film layer 34 may also have a discontinuous shape. The term "discontinuous" means that the film is formed discontinuously when viewed in a direction perpendicular to the longitudinal direction.

[0084] For example, when the thin film layer 34 is formed using a material containing ceramic, one method is to polish the cross section, then take a cross section photograph using a digital microscope (Keyence Corporation: VHX-5000), and use the cross section photograph to calculate the thickness, etc. Another method is to measure the thickness, etc. from the actual observation image of the cross section of the part taken by FIB using a scanning microscope.

[0085] (Surface Plated Layer) The surface plated layer 36 includes a first surface plated layer 36a, a second surface plated layer 36b, a third surface plated layer 36c, and a fourth surface plated layer 36d.

[0086] The first surface plating layer 36a is arranged to cover the first thin film layer 34a and the first underlayer 32a arranged on the third surface 12c and fifth surface 12e of the laminate 12. The second surface plating layer 36b is arranged to cover the second thin film layer 34b and the second underlayer 32b arranged on the fourth surface 12d and sixth surface 12f of the laminate 12. The third surface plating layer 36c is arranged to cover the third thin film layer 34c and the third underlayer 32c arranged on the third surface 12c and sixth surface 12f of the laminate 12. The fourth surface plating layer 36d is arranged to cover the fourth thin film layer 34d and the fourth underlayer 32d arranged on the fourth surface 12d and fifth surface 12e of the laminate 12.

[0087] The surface plating layer 36 preferably contains at least one metal selected from the group consisting of Cu, Ni, Sn, Pb, Au, Ag, Pd, Bi, and Zn, or an alloy containing such a metal. The plating layer preferably does not contain glass.

[0088] The surface plating layer 36 may be, for example, only Sn plating, or preferably has a two-layer structure of Ni plating, Sn plating, or Ni plating and Cu plating.

[0089] The Sn plating covers the Ni plating. Specifically, the Sn plating is formed by plating growth starting from the Ni plating. The thickness of the Sn plating is preferably 1.0 μm or more and 5.0 μm or less. Here, FIG. 8( b) illustrates the structure of the first surface plating layer 36a of the first external electrode 30a in detail. As shown in FIG. 8( b), the first surface plating layer 36a constituting the first external electrode 30a includes a Ni plating layer 36a1 and a Sn plating layer 36a2. In this case, the relationship between the thickness t4 of the Sn plating disposed in the first recess 40a (or the second recess 42a) and the thickness t5 of the Sn plating disposed at a center position (½) on the first surface 12a of the first external electrode 30a at a distance 1 in the second direction z on the first surface 12a side of the first external electrode 30a is preferably |t4-t5|≦t5 / 2. The relationship between the thickness of the Sn plating disposed in the first recess 40a (or the second recess 42a) and the thickness t6 of the Sn plating disposed on the first surface 12a in a region 10 μm from the tip thereof is preferably |t4−t6|≦t6 / 2. The above-described structure of the Sn plating constituting the first surface plating layer 36a included in the first external electrode 30a is also possessed by the Sn plating constituting the second surface plating layer 36b included in the second external electrode 30b, the Sn plating constituting the third surface plating layer 36c included in the third external electrode 30c, and the fourth surface plating layer 36d included in the fourth external electrode 30d.

[0090] The thickness of the surface plating layer 36 is preferably, for example, 0.5 μm or more and 10 μm or less.

[0091] The metal content per unit volume of the surface plating layer is preferably 99% by volume or more.

[0092] The thickness of each surface plating layer is preferably 0.5 μm or more and 10.0 μm or less.

[0093] The dimension of the multilayer ceramic capacitor 10 including the laminate 12 and the external electrodes 30 in the first direction y is defined as dimension L, the dimension of the multilayer ceramic capacitor 10 including the laminate 12 and the external electrodes 30 in the stacking direction x is defined as dimension T, and the dimension of the multilayer ceramic capacitor 10 including the laminate 12 and the external electrodes 30 in the second direction z is defined as dimension W. The dimensions of the multilayer ceramic capacitor 10 are preferably such that the L dimension in the first direction y is 0.2 mm or more and 3.2 mm or less, the T dimension in the stacking direction x is 0.04 mm or more and 0.22 mm or less, and the W dimension in the second direction z is 0.2 mm or more and 3.2 mm or less. The dimensions of the multilayer ceramic capacitor 10 preferably satisfy the relationship 0.85≦L / W≦1.00. This allows the laminate 12 to have a substantially tetragonal shape, thereby improving the flexibility of mounting.

[0094] The multilayer ceramic capacitor 10 shown in FIG. 1 has a first recess 40 located inside the laminate 12, and therefore, during mounting, this first recess 40 can prevent solder from wetting up from the first surface 12 a onto the external electrode disposed on the surface facing the second direction z.

[0095] 2. Method for Manufacturing a Multilayer Ceramic Capacitor A method for manufacturing a multilayer ceramic capacitor according to the first embodiment will now be described.

[0096] First, a conductive paste for the dielectric sheets and the internal electrodes is prepared. The conductive paste for the dielectric sheets and the internal electrodes contains a binder and a solvent. Known binders and solvents can be used.

[0097] Next, a conductive paste for the internal electrodes is printed in a predetermined pattern on the dielectric sheet by, for example, inkjet printing, screen printing, gravure printing, etc. This prepares a dielectric sheet on which the pattern of the first internal electrode is formed and a dielectric sheet on which the pattern of the second internal electrode is formed. Thereafter, the sheet on which the pattern of the first internal electrode is printed and the sheet on which the pattern of the second internal electrode is printed are laminated together to form the portion that becomes the inner layer portion 18.

[0098] Furthermore, for example, when forming a printing pattern of an internal electrode by gravure printing, the design of the gravure plate used in the gravure printing is set to the graphic pattern of the first internal electrode, and by changing the structure to correspond to the graphic pattern of the second internal electrode, it is possible to form each of the desired internal electrodes.

[0099] Furthermore, when forming a printing pattern of the internal electrode layer by screen printing, the desired internal electrode can be formed by designing the screen printing mask to the graphic pattern of the first internal electrode and changing the structure to correspond to the graphic pattern of the second internal electrode.

[0100] Next, a predetermined number of dielectric sheets not printed with an internal electrode pattern are stacked to form the portion that will become the first outer layer portion 20a on the first surface 12a. After that, the portion that will become the inner layer portion 18 prepared above is stacked, and a predetermined number of dielectric sheets not printed with an internal electrode pattern are stacked on top of this portion that will become the inner layer portion 18 to form the portion that will become the second outer layer portion 20b on the second surface 12b. In this way, a laminated sheet is produced.

[0101] Next, the laminated sheet is pressed in the lamination direction by means of a hydrostatic press or the like to produce a laminated block.

[0102] The laminated block is then cut to a predetermined size to cut out laminated chips, the corners and ridges of which may be rounded by barrel polishing or the like.

[0103] Next, the laminated chip is fired to produce the laminate 12. The firing temperature depends on the ceramic and internal electrode materials, but is preferably 900° C. or higher and 1400° C. or lower.

[0104] At this time, the first lead electrode portion 24a of the first internal electrode 16a and the third lead electrode portion 24c of the second internal electrode 16b are exposed from the third surface 12c of the laminate 12. Furthermore, the second lead electrode portion 24b of the first internal electrode 16a and the fourth lead electrode portion 24d of the second internal electrode 16b are exposed from the fourth surface 12d of the laminate 12.

[0105] Subsequently, the external electrodes 30 are formed on the laminate 12 .

[0106] First, an underlayer 32 is formed so as to cover the internal electrodes 16 exposed on the surface of the laminate 12. The underlayer 32 is Cu plated and is formed by electrolytic plating or electroless plating. At this time, the plated laminate 12 is subjected to a heat treatment to remove residual moisture remaining in the plating film and at the interface between the laminate 12 and the underlayer 32.

[0107] Here, after the base layer 32 is formed, predetermined locations on the first surface 12a and the second surface 12b on the third surface 12c side to the sixth surface 12f side are surface treated, for example, by plasma etching, to form regions for forming the first recess 40 and the second recess 42.

[0108] Next, the laminate 12 on which the underlayer 32 has been formed is aligned on a work table, and the thin film layer 34 is formed on the first surface 12a by, for example, sputtering.

[0109] Thereafter, a top plating layer 36 is formed on the underlayer 32 and the thin film layer 34 disposed on the surface of the laminate 12. More specifically, a Ni plating layer and a Sn plating layer are formed as the top plating layer 36 on the underlayer 32 and the thin film layer 34. Either electrolytic plating or electroless plating may be employed for the plating process. However, electroless plating has the disadvantage of requiring pretreatment using a catalyst or the like to improve the plating deposition rate, which complicates the process. Therefore, electrolytic plating is usually preferred. However, without being limited to this, after forming the top plating layer, for example, a Ni plating layer may be formed, followed by forming recesses, and then a Sn plating layer may be formed.

[0110] In this manner, the multilayer ceramic capacitor 10 according to the embodiment shown in FIG. 1 can be manufactured.

[0111] B. Second Embodiment 1. Multilayer Ceramic Capacitor An example of a multilayer ceramic capacitor 110 according to a second embodiment of the present invention will now be described.

[0112] FIG. 11A is an external perspective view from one side showing an example of a multilayer ceramic capacitor according to a second embodiment of the present invention. FIG. 11B is an external perspective view from the other side showing an example of a multilayer ceramic capacitor according to the second embodiment of the present invention. FIG. 12 is a front view showing an example of a multilayer ceramic capacitor according to the second embodiment of the present invention. FIG. 13 is a cross-sectional view taken along line XIII-XIII in FIG. 11A. FIG. 14 is a cross-sectional view taken along line XIV-XIV in FIG. 11A. FIG. 15 is a cross-sectional view taken along line XV-XV in FIG. 11A. FIG. 16 is a cross-sectional view taken along line XVI-XVI in FIG. 11A. FIG. 17A is a cross-sectional view taken along line XVIIA-XVIIA in FIG. 12. FIG. 17B is a cross-sectional view taken along line XVIIB-XVIIB in FIG. 12. FIG. 18 is an exploded perspective view of the laminate shown in FIG. 11A. 1 to 7 are given the same reference numerals and detailed description thereof will be omitted.

[0113] The multilayer ceramic capacitor 110 includes a laminate 112 and external electrodes 130 .

[0114] (Laminate) The laminate 12 includes a plurality of dielectric layers 114 and a plurality of internal electrodes 116. The dielectric layers 114 include an inner dielectric layer 114a and an outer dielectric layer 114b. The internal electrodes 116 include a first internal electrode 116a and a second internal electrode 116b.

[0115] The laminate 112 also has an inner layer portion 118, a first outer layer portion 120a located on the first surface 112a side, and a second outer layer portion 120b located on the second surface 112b side.

[0116] The first outer layer portion 120a is located on the first surface 112a side of the laminate 112 and is an aggregate of multiple outer layer dielectric layers 114b located between the first surface 112a and the internal electrode 116 closest to the first surface 112a.

[0117] The second outer layer portion 120b is located on the second surface 112b side of the laminate 12 and is an aggregate of multiple outer layer dielectric layers 114b located between the second surface 112b and the internal electrode 116 closest to the second surface 112b.

[0118] The region sandwiched between the first outer layer portion 120a and the second outer layer portion 120b is the inner layer portion 118.

[0119] The inner layer portion 118 has a first inner electrode 116a having one end exposed to the third surface 112c and the other end exposed to the fourth surface 112d, a second inner electrode 116b having one end exposed to the third surface 112c and the other end exposed to the fourth surface 112d, and an inner layer dielectric layer 114a.

[0120] The material of the dielectric layer 114 is the same as that of the dielectric layer 14, and therefore a description thereof will be omitted.

[0121] (Internal Electrode) The internal electrode 116 includes a plurality of first internal electrodes 116a and a plurality of second internal electrodes 116b. The first internal electrodes 116a and the second internal electrodes 116b are alternately stacked with the dielectric layer 114 interposed therebetween.

[0122] The first internal electrode 116a is disposed on the surface of the inner dielectric layer 114a. The first internal electrode 116a faces the first surface 112a and the second surface 112b, has a first opposing electrode portion 122a facing the second internal electrode 116b, and is laminated in the direction connecting the first surface 112a and the second surface 112b.

[0123] The first internal electrode 116a is extended to the third surface 112c of the laminate 112 by a first extension electrode portion 124a, and is extended to the fourth surface 112d of the laminate 112 by a second extension electrode portion 124b. The first extension electrode portion 124a is extended to the fifth surface 112e of the laminate 112, and the second extension electrode portion 124b is extended to the sixth surface 112f of the laminate 112.

[0124] The second internal electrode 116b is disposed on a surface of the inner dielectric layer 114a different from the surface of the inner dielectric layer 114a on which the first internal electrode 116a is disposed. The second internal electrode 116b faces the first surface 112a and the second surface 112b, has a second opposing electrode portion 122b facing the first internal electrode 116a, and is laminated in a direction connecting the first surface 112a and the second surface 112b.

[0125] The second internal electrode 116b is extended to the third surface 112c of the laminate 12 by a third extension electrode portion 124c, and is extended to the fourth surface 112d of the laminate 112 by a fourth extension electrode portion 124d. The third extension electrode portion 124c is extended to the sixth surface 112f of the laminate 112, and the fourth extension electrode portion 124d is extended to the fifth surface 112e of the laminate 112.

[0126] The first internal electrode 116 a and the second internal electrode 116 b are not exposed on the fifth surface 112 e and the sixth surface 112 f of the laminate 112 .

[0127] Furthermore, when the multilayer ceramic capacitor 110 is viewed from the stacking direction x, it is preferable that a straight line connecting the first extraction electrode portion 124a and the second extraction electrode portion 124b of the first internal electrode 116a intersects with a straight line connecting the third extraction electrode portion 124c and the fourth extraction electrode portion 124d of the second internal electrode 116b.

[0128] Furthermore, on the surfaces 112c, 112d, 112e, and 112f of the laminate 112, it is preferable that the first extraction electrode portion 124a of the first internal electrode 116a and the fourth extraction electrode portion 124d of the second internal electrode 116b are extracted to opposing positions, and that the second extraction electrode portion 124b of the first internal electrode 116a and the third extraction electrode portion 124c of the second internal electrode 116b are extracted to opposing positions.

[0129] As shown in FIG. 16 , the laminate 112 also includes a side portion (W gap) 126a of the laminate 112 located between one end in the first direction y of the second opposing electrode portion 122b of the second internal electrode 116b and the third surface 112c, and a side portion (W gap) 126b of the laminate 112 located between the other end in the first direction y of the first opposing electrode portion 122a of the first internal electrode 116a and the fourth surface 112d.

[0130] Furthermore, as shown in FIG. 15 , the laminate 112 includes an end portion (L gap) 127a of the laminate 112 located between one end in the second direction z of the second opposing electrode portion 122b of the second internal electrode 116b and the fifth surface 112e, and a side portion (L gap) 127b of the laminate 112 located between the other end in the second direction z of the first opposing electrode portion 122a of the first internal electrode 116a and the sixth surface 112f.

[0131] 11A to 16, external electrodes 130 are arranged on the laminate 12. The external electrodes 130 include a plurality of external electrodes 130 connected to the first internal electrodes 116a and the second internal electrodes 116b. The external electrodes 130 include a first external electrode 130a, a second external electrode 130b, a third external electrode 130c, and a fourth external electrode 130d.

[0132] The first external electrode 130a is disposed on the third surface 112c so as to cover the first lead electrode portion 124a of the first internal electrode 116a, and further so as to cover a portion of the first surface 112a and a portion of the second surface 112b. The first external electrode 130a is electrically connected to the first lead electrode portion 124a of the first internal electrode 116a.

[0133] The second external electrode 130b is disposed on the fourth surface 112d so as to cover the second lead electrode portion 124b of the first internal electrode 116a, and further so as to cover a portion of the first surface 112a and a portion of the second surface 112b. The second external electrode 130b is electrically connected to the second lead electrode portion 124b of the first internal electrode 116a.

[0134] The third external electrode 130c is disposed on the third surface 112c so as to cover the third lead electrode portion 124c of the second internal electrode 116b, and further so as to cover a part of the first surface 112a and a part of the second surface 112b. The third external electrode 130c is electrically connected to the third lead electrode portion 124c of the second internal electrode 116b.

[0135] The fourth external electrode 130d is disposed on the fourth surface 112d so as to cover the fourth lead electrode portion 124d of the second internal electrode 116b, and further so as to cover a part of the first surface 112a and a part of the second surface 112b. The fourth external electrode 130d is electrically connected to the fourth lead electrode portion 124d of the second internal electrode 116b.

[0136] Furthermore, as shown in Figure 12, it is preferable that the external electrode 130 arranged on the fifth surface 112e or the sixth surface 112f from which the internal electrode 116 is not pulled out covers in a U-shape one of the short sides of the side surface from which the internal electrode 116 is not pulled out and the portion from the end of that short side to the middle of both long sides.

[0137] When viewed from the stacking direction x, the external electrode 130 has a second recess 142 extending in the second direction z inside the laminate 112 .

[0138] More specifically, when the first external electrode 130a covers the first surface 112a, the second surface 112b, and the third surface 112c, the first external electrode 130a has a second recess 142a1 extending in the second direction z on the third surface 112c side when viewed in the stacking direction x from the first surface 112a side. Also, when the first external electrode 130a covers the first surface 112a, the second surface 112b, and the third surface 112c, the first external electrode 130a has a second recess 142a2 extending in the second direction z on the third surface 112c side when viewed in the stacking direction x from the second surface 112b side.

[0139] When viewed in the stacking direction x from the first surface 112a, the dimension of the second recess 142a1 in the second direction z is 10% to 96.0% of the dimension of the first external electrode 130a in which the second recess 140a1 is formed, in the second direction z, and more preferably 100% or less. Similarly, when viewed in the stacking direction x from the second surface 112b, the dimension of the second recess 142a2 in the second direction z is 10% to 96.0% of the dimension of the first external electrode 130a in which the second recess 140a2 is formed, in the second direction z, and more preferably 100% or less. This makes it possible to prevent excessive wetting of the solder onto the third surface 112c. When the second recesses 142a1 and 142a2 are arranged discontinuously, the dimensions of the second recesses 142a1 and 142a2 in the first direction y are defined by their total lengths.

[0140] The second recess 142a1 is preferably positioned at a distance of 0.01 μm or more and 10.0 μm or less from the outermost surface of the third surface 112c of the laminate 112. Similarly, the second recess 142a2 is preferably positioned at a distance of 0.01 μm or more and 10.0 μm or less from the outermost surface of the third surface 112c of the laminate 112. In other words, the second recess 142a1 and the second recess 142a2 are positioned inside the laminate 112. This allows the second recess 140a1 to block or trap the solder from wetting up from the first surface 112a to the external electrode 130 disposed on the surface opposite to the second direction z, thereby suppressing wetting up to the third surface 112c.

[0141] When viewed in the second direction z, the distance from the bottom surface of the second recess 142a1 to the apex of the surface plating layer 36, which is located outside the second recess 142a1 and will be described later, is preferably 1.0 μm or more.

[0142] When the second external electrode 130b covers the first surface 112a, the second surface 112b, and the fourth surface 112d, the second external electrode 130b has a second recess 142b1 extending in the second direction z on the fourth surface 112d side when viewed in the stacking direction x from the first surface 112a side. When the second external electrode 130b covers the first surface 112a, the second surface 112b, and the fourth surface 112d, the second external electrode 130b has a second recess 142b2 extending in the second direction z on the fourth surface 112d side when viewed in the stacking direction x from the second surface 112b side. The rest of the configuration of the second external electrode 130b is similar to that of the first external electrode 130a.

[0143] When the third external electrode 130c covers the first surface 112a, the second surface 112b, and the third surface 112c, the third external electrode 130c has a second recess 142c extending in the second direction z on the third surface 112c side when viewed in the stacking direction x from the first surface 112a side. When the third external electrode 130c covers the first surface 112a, the second surface 112b, and the third surface 112c, the third external electrode 130c has a second recess 142c2 extending in the second direction z on the third surface 112c side when viewed in the stacking direction x from the second surface 112b side. The rest of the configuration of the third external electrode 130c is similar to that of the first external electrode 130a.

[0144] When the fourth external electrode 130d covers the first surface 112a, the second surface 112b, and the fourth surface 112d, the fourth external electrode 130d has a second recess 142d extending in the second direction z on the fourth surface 112d side when viewed in the stacking direction x from the first surface 112a side. Also, when the fourth external electrode 130d covers the first surface 112a, the second surface 112b, and the fourth surface 112d, the fourth external electrode 130d has a second recess 142d2 extending in the second direction z on the fourth surface 112d side when viewed in the stacking direction x from the second surface 112b side. The rest of the configuration of the fourth external electrode 130d is similar to that of the first external electrode 130a.

[0145] In the laminate 112, the first opposing electrode portion 122a of the first internal electrode 116a and the second opposing electrode portion 122b of the second internal electrode 116b face each other via the inner dielectric layer 114a, thereby forming a capacitance. Therefore, a capacitance can be obtained between the first external electrode 130a and the second external electrode 130b to which the first internal electrode 116a is connected and the third external electrode 130c and the fourth external electrode 130d to which the second internal electrode 116b is connected, thereby realizing the characteristics of a capacitor.

[0146] Each of the first external electrode 130 a , the second external electrode 130 b , the third external electrode 130 c and the fourth external electrode 130 d preferably has an underlayer 132 , a thin film layer 134 and a surface plating layer 136 .

[0147] (Underlayer) The underlayer 132 is disposed on the third surface 112c and the fourth surface 112d. The specific configuration of the underlayer 132 will be described below.

[0148] The first underlayer 132a is disposed on the surface of the third surface 112c of the laminate 112 so as to cover the first extraction electrode portion 124a of the first internal electrode 116a exposed from the third surface 112c of the laminate 112.

[0149] The second underlayer 132b is disposed on the surface of the fourth surface 112d of the laminate 112 so as to cover the second extraction electrode portion 124b of the first internal electrode 116a exposed from the fourth surface 112d of the laminate 112.

[0150] The third underlayer 132c is disposed on the surface of the third surface 112c of the laminate 112 so as to cover the third extraction electrode portion 124c of the second internal electrode 116b exposed from the third surface 112c of the laminate 112.

[0151] The fourth underlayer 132d is disposed on the surface of the fourth surface 112d of the laminate 112 so as to cover the fourth extraction electrode portion 124d of the second internal electrode 116b exposed from the fourth surface 112d of the laminate 112.

[0152] The underlayer 132 is preferably made of Cu plating, although this depends on the connectivity with the internal electrodes 116 .

[0153] Preferably, the upper end of the first base layer 132a of the first external electrode 130a is connected to the first thin film layer 134a on the ridge formed by the first surface 112a and the third surface 112c of the laminate 112. Preferably, the lower end of the first base layer 132a of the first external electrode 130a is connected to the first thin film layer 134a on the ridge formed by the second surface 112b and the third surface 112c of the laminate 112.

[0154] As with the first underlayer 32a of the multilayer ceramic capacitor 10, the distance in the stacking direction x between the leading end of the third surface 112c of the first underlayer 132a and the end of the internal electrode 116 closest to the first surface 112a that is exposed on the third surface 112c is preferably 3.0 μm or more and 8.1 μm or less. The first underlayer 132a is preferably disposed so as to extend toward the first surface 112a. In other words, the distance in the stacking direction x between a point on the outermost surface of the first surface 112a located 1.0 μm inward from the third surface 112c and the leading end of the first underlayer 132a in the stacking direction x is preferably 10.0 μm or less. The thickness of the first underlayer 132a is preferably 3.0 μm or more and 8.1 μm or less in the first direction y from the end exposed on the third surface 112c of the internal electrode 116 closest to the first surface 112a.

[0155] The upper end of the second base layer 132b of the second external electrode 130b is preferably connected to the second thin film layer 134b on the ridge formed by the first surface 112a and the fourth surface 112d of the laminate 112. Furthermore, the lower end of the second base layer 132b of the second external electrode 130b is preferably connected to the second thin film layer 134b on the ridge formed by the second surface 112b and the fourth surface 112d of the laminate 112. The rest of the configuration of the second external electrode 130b is similar to that of the first external electrode 130a.

[0156] The upper end of the third base layer 132c of the third external electrode 130c is preferably connected to the third thin film layer 134c on the ridge formed by the first surface 112a and the third surface 112c of the laminate 112. Furthermore, the lower end of the third base layer 132c of the third external electrode 130c is preferably connected to the third thin film layer 134c on the ridge formed by the second surface 112b and the third surface 112c of the laminate 112. The rest of the configuration of the third external electrode 130c is similar to that of the first external electrode 130a.

[0157] The upper end of the fourth base layer 132d of the fourth external electrode 130d is preferably connected to the fourth thin film layer 134d on the ridge formed by the first surface 112a and the fourth surface 112d of the laminate 112. Furthermore, the lower end of the fourth base layer 132d of the fourth external electrode 130d is preferably connected to the fourth thin film layer 34d on the ridge formed by the second surface 112b and the fourth surface 112d of the laminate 112. The rest of the configuration of the fourth external electrode 130d is similar to that of the first external electrode 130a.

[0158] (Thin Film Layers) The thin film layers 134 include a first thin film layer 134a, a second thin film layer 134b, a third thin film layer 134c, and a fourth thin film layer 134d.

[0159] The first thin film layer 134a covers a part of the first surface 112a and a part of the second surface 112b on the third surface 112c side and the fifth surface 112e side of the laminate 112. The first thin film layer 134a is preferably disposed in contact with the first base layer 132a.

[0160] The second thin film layer 134b covers a part of the first surface 112a and a part of the second surface 112b on the fourth surface 112d side and the sixth surface 112f side of the laminate 112. The second thin film layer 134b is preferably arranged in contact with the second base layer 132b.

[0161] The third thin film layer 134c covers a part of the first surface 112a and a part of the second surface 112b on the third surface 112c side and the sixth surface 112f side of the laminate 112. The third thin film layer 134c is preferably arranged in contact with the third base layer 132c.

[0162] The fourth thin film layer 134d covers a part of the first surface 112a and a part of the second surface 112b on the fourth surface 112d side and the fifth surface 112e side of the laminate 112. The fourth thin film layer 134d is preferably arranged in contact with the fourth base layer 132d.

[0163] (Surface Plated Layer) The surface plated layer 136 includes a first surface plated layer 136a, a second surface plated layer 136b, a third surface plated layer 136c, and a fourth surface plated layer 136d.

[0164] The first surface plating layer 136a is arranged to cover the first thin film layer 134a and the first foundation layer 132a arranged on the third surface 112c of the laminate 112. The second surface plating layer 136b is arranged to cover the second thin film layer 134b and the second foundation layer 132b arranged on the fourth surface 112d of the laminate 112. The third surface plating layer 136c is arranged to cover the third thin film layer 134c and the third foundation layer 132c arranged on the third surface 112c of the laminate 112. The fourth surface plating layer 136d is arranged to cover the fourth thin film layer 134d and the fourth foundation layer 132d arranged on the fourth surface 112d of the laminate 112.

[0165] The surface plating layer 136 may be, for example, only Sn plating, or preferably has a two-layer structure of Ni plating, Sn plating, or Ni plating and Cu plating.

[0166] The Sn plating covers the Ni plating. Specifically, the Sn plating is formed by plating growth starting from the Ni plating. The thickness of the Sn plating is preferably 1.0 μm or more and 5.0 μm or less. Here, the structure of the first surface plating layer 136a of the first external electrode 130a will be described in detail using an example of the first surface plating layer 136a. As with the surface plating layer 36 of the multilayer ceramic capacitor 10, the first surface plating layer 136a constituting the first external electrode 130a includes a Ni plating layer and a Sn plating layer. In this case, the relationship between the thickness t4 of the Sn plating disposed in the second recess 142a and the thickness t5 of the Sn plating disposed at a center position (½) on the first surface 112a of the first external electrode 130a at a distance 1 in the second direction z on the first surface 112a side of the first external electrode 130a is preferably |t4-t5|≦t5 / 2. The relationship between the thickness of the Sn plating disposed in the second recess 142a and the thickness t6 of the Sn plating disposed on the first surface 112a in a region 10 μm from the tip thereof is preferably |t4−t6|≦t6 / 2. The above-described structure of the Sn plating constituting the first surface plating layer 136a included in the first external electrode 130a is also possessed by the Sn plating constituting the second surface plating layer 136b included in the second external electrode 130b, the Sn plating constituting the third surface plating layer 136c included in the third external electrode 130c, and the fourth surface plating layer 136d included in the fourth external electrode 130d.

[0167] The multilayer ceramic capacitor 110 shown in FIG. 11A has the same effects as the multilayer ceramic capacitor 10 according to the first embodiment.

[0168] 2. Method for Manufacturing a Multilayer Ceramic Capacitor A method for manufacturing a multilayer ceramic capacitor according to a second embodiment will now be described.

[0169] First, a dielectric sheet and a conductive paste for the internal electrodes are prepared. The conductive paste for the dielectric sheet and the internal electrodes contains a binder and a solvent. Known binders and solvents can be used.

[0170] Next, a conductive paste for the internal electrodes is printed in a predetermined pattern on the dielectric sheet by, for example, inkjet printing, screen printing, gravure printing, etc. This prepares a dielectric sheet on which the pattern of the first internal electrode is formed and a dielectric sheet on which the pattern of the second internal electrode is formed. Thereafter, the sheet on which the pattern of the first internal electrode is printed and the sheet on which the pattern of the second internal electrode is printed are laminated together to form the portion that becomes the inner layer portion 18.

[0171] Next, a predetermined number of dielectric sheets without printed internal electrode patterns are stacked to form the portion that will become the first outer layer portion 120a on the first surface 112a. After that, the portion that will become the inner layer portion 118 prepared above is stacked, and a predetermined number of dielectric sheets without printed internal electrode patterns are stacked on top of this portion that will become the inner layer portion 118 to form the portion that will become the second outer layer portion 120b on the second surface 112b. In this way, a laminated sheet is produced.

[0172] Next, the laminated sheet is pressed in the lamination direction by means of a hydrostatic press or the like to produce a laminated block.

[0173] Next, the laminated block is cut to a predetermined size to cut out laminated chips. At this time, the corners and ridges of the laminated chips may be rounded by barrel polishing or the like.

[0174] Next, the laminated chip is fired to produce the laminate 112. The firing temperature depends on the ceramic and internal electrode materials, but is preferably 900° C. or higher and 1400° C. or lower.

[0175] At this time, the first lead electrode portion 124a of the first internal electrode 116a and the third lead electrode portion 124c of the second internal electrode 116b are exposed from the third surface 112c of the laminate 112. Furthermore, the second lead electrode portion 124b of the first internal electrode 116a and the fourth lead electrode portion 124d of the second internal electrode 116b are exposed from the fourth surface 112d of the laminate 112.

[0176] Subsequently, the external electrodes 130 are formed on the laminate 112 .

[0177] First, an underlayer 132 is formed so as to cover the internal electrodes 116 exposed on the surface of the laminate 112. The underlayer 132 is Cu plated and is formed by electrolytic plating or electroless plating. At this time, the plated laminate 112 is subjected to a heat treatment to remove residual moisture remaining in the plating film and at the interface between the laminate 112 and the underlayer 132.

[0178] Here, after the base layer 132 is formed, predetermined locations on the first surface 112a and the second surface 112b on the third surface 112c side to the sixth surface 112f side are surface treated, for example, by plasma etching, to form regions for forming the second recess 142.

[0179] Next, the laminate 112 on which the underlayer 132 has been formed is aligned on a work table, and a thin film layer 134 is formed on the first surface 112a and the second surface 112b by, for example, sputtering.

[0180] Thereafter, a top plating layer 136 is formed on the thin film layer 134 and the surface of the laminate 112. More specifically, a Ni plating layer and a Sn plating layer are formed on the thin film layer 134 as the top plating layer 136. Either electrolytic plating or electroless plating may be used for the plating process. However, electroless plating has the disadvantage of requiring pretreatment using a catalyst or the like to improve the plating deposition rate, which complicates the process. Therefore, it is usually preferable to use electrolytic plating. However, without being limited to this, after forming the top plating layer, for example, a Ni plating layer may be formed, followed by forming recesses, and then a Sn plating layer may be formed.

[0181] At this time, the external electrode 130 placed on the side where the internal electrode 116 is not pulled out is formed in a U-shape by the surface plating layer 136 so as to cover both short sides of the side where the internal electrode 116 is not pulled out and the portions from the ends of both short sides to the middle parts of both long sides.

[0182] In this manner, a multilayer ceramic capacitor 110 as shown in FIG. 13 is manufactured.

[0183] C. Third Embodiment 1. Multilayer Ceramic Capacitor An example of a multilayer ceramic capacitor 210 according to a third embodiment of the present invention will now be described.

[0184] FIG. 19A is an external perspective view showing an example of a multilayer ceramic capacitor according to a third embodiment of the present invention. FIG. 19B is an external perspective view from the other side showing an example of a multilayer ceramic capacitor according to a second embodiment of the present invention. FIG. 20 is a cross-sectional view taken along line XX-XX in FIG. 19A. FIG. 21 is a cross-sectional view taken along line XXI-XXI in FIG. 19A. FIG. 22 is a cross-sectional view taken along line XXII-XXII in FIG. 19A. FIG. 23 is a cross-sectional view taken along line XXIII-XXIII in FIG. 19A. Note that the same or corresponding components as those in FIGS. 1 to 7 are designated by the same reference numerals, and detailed description thereof will be omitted.

[0185] The multilayer ceramic capacitor 210 includes a laminate 12 and a plurality of external electrodes 230 .

[0186] (Laminate) In the multilayer ceramic capacitor 210 according to the third embodiment, the laminate 12 has the same configuration as the laminate 12 according to the first embodiment of the present invention shown in FIG.

[0187] (Internal Electrode) The internal electrode 16 includes a plurality of first internal electrodes 16a and a plurality of second internal electrodes 16b. The first internal electrodes 16a and the second internal electrodes 16b are alternately stacked with the dielectric layer 14 interposed therebetween.

[0188] The first internal electrode 16a is disposed on the surface of the inner dielectric layer 14a. The first internal electrode 16a faces the first surface 12a and the second surface 12b, has a first opposing electrode portion 22a facing the second internal electrode 16b, and is laminated in the direction connecting the first surface 12a and the second surface 12b.

[0189] (Internal electrode) The first internal electrode 16a is extended to the third surface 12c and the fifth surface 12e of the laminate 12 by the first extension electrode portion 24a, and is extended to the fourth surface 12d and the sixth surface 12f of the laminate 12 by the second extension electrode portion 24b.

[0190] The second internal electrode 16b is disposed on a surface of the inner dielectric layer 14a different from the surface of the inner dielectric layer 14a on which the first internal electrode 16a is disposed. The second internal electrode 16b faces the first surface 12a and the second surface 12b, has a second opposing electrode portion 22b facing the first internal electrode 16a, and is laminated in a direction connecting the first surface 12a and the second surface 12b.

[0191] The second internal electrode 16b is extended to the third surface 12c and the sixth surface 12f of the laminate 12 by the third extension electrode portion 24c, and is extended to the fourth surface 12d and the fifth surface 12e of the laminate 12 by the fourth extension electrode portion 24d.

[0192] Furthermore, when the multilayer ceramic capacitor 210 is viewed from the stacking direction x, it is preferable that a straight line connecting the first extraction electrode portion 24a and the second extraction electrode portion 24b of the first internal electrode 16a intersects with a straight line connecting the third extraction electrode portion 24c and the fourth extraction electrode portion 24d of the second internal electrode 16b.

[0193] Furthermore, on the surfaces 12c, 12d, 12e, and 12f of the laminate 12, it is preferable that the first extraction electrode portion 24a of the first internal electrode 16a and the fourth extraction electrode portion 24d of the second internal electrode 16b are extracted to opposing positions, and that the second extraction electrode portion 24b of the first internal electrode 16a and the third extraction electrode portion 24c of the second internal electrode 16b are extracted to opposing positions.

[0194] As shown in FIG. 27 , the laminate 12 also includes a side portion (W gap) 26 a of the laminate 12 located between one end in the first direction y of the second opposing electrode portion 22 b of the second internal electrode 16 b and the third surface 12 c, and a side portion (W gap) 26 b of the laminate 12 located between the other end in the first direction y of the first opposing electrode portion 22 a of the first internal electrode 16 a and the fourth surface 12 d.

[0195] Furthermore, as shown in FIG. 26 , the laminate 12 includes an end portion (L gap) 27 a of the laminate 12 located between one end in the second direction z of the second opposing electrode portion 22 b of the second internal electrode 16 b and the fifth surface 12 e, and a side portion (L gap) 127 b of the laminate 12 located between the other end in the second direction z of the first opposing electrode portion 22 a of the first internal electrode 16 a and the sixth surface 12 f.

[0196] 19A to 23, external electrodes 230 are arranged on the laminate 12. The external electrodes 230 include a plurality of external electrodes 230 connected to the first internal electrodes 16a and the second internal electrodes 16b. The external electrodes 230 include a first external electrode 230a, a second external electrode 230b, a third external electrode 230c, and a fourth external electrode 230d.

[0197] The first external electrode 230a is disposed on the third surface 12c and the fifth surface 12e so as to cover the first lead electrode portion 24a of the first internal electrode 16a, and further so as to cover a portion of the first surface 12a. The first external electrode 230a is electrically connected to the first lead electrode portion 24a of the first internal electrode 16a.

[0198] The second external electrode 230b is disposed on the fourth surface 12d and the sixth surface 12f so as to cover the second lead electrode portion 24b of the first internal electrode 16a, and further so as to cover a portion of the first surface 12a. The second external electrode 230b is electrically connected to the second lead electrode portion 24b of the first internal electrode 16a.

[0199] The third external electrode 230c is disposed on the third surface 12c and the sixth surface 12f so as to cover the third lead electrode portion 24c of the second internal electrode 16b, and further so as to cover a part of the first surface 12a. The third external electrode 230c is electrically connected to the third lead electrode portion 24c of the second internal electrode 16b.

[0200] The fourth external electrode 230d is disposed on the fourth surface 12d and the fifth surface 12e so as to cover the fourth lead electrode portion 24d of the second internal electrode 16b, and further so as to cover a part of the first surface 12a. The fourth external electrode 230d is electrically connected to the fourth lead electrode portion 24d of the second internal electrode 16b.

[0201] When viewed from the stacking direction x, the external electrode 230 has a first recess 240 extending in the first direction y inside the laminate 12. The external electrode 230 may also have a second recess 242 extending in the second direction z inside the laminate 12.

[0202] More specifically, when the first external electrode 230a covers the first surface 12a, the third surface 12c, and the fifth surface 12e, when viewed in the stacking direction x from the first surface 12a side, the first external electrode 230a has a second recess 242a1 extending in the second direction z on the third surface 12c side, and a first recess 240a1 extending in the first direction y on the fifth surface 12e side.

[0203] When viewed from the first surface 12a in the stacking direction x, the dimension of the first recess 240a1 in the first direction y is 10% to 96.0% of the dimension of the first external electrode 230a on which the first recess 240a1 is formed in the first direction y. More preferably, it is 100% or less. This makes it possible to prevent excessive solder from wetting up onto the fifth surface 12e. Note that when the first recesses 240a1 are arranged discontinuously, the dimension of the first recesses 240a1 in the first direction y is defined by the total length of the first recesses 240a1.

[0204] The first recess 240a1 is preferably disposed within a distance of 0.01 μm to 10.0 μm from the outermost surface of the fifth surface 12e of the laminate 12. In other words, the first recess 240a1 is disposed inside the laminate 12. This allows the first recess 240a1 to block or trap the solder from wetting up from the first surface 12a onto the external electrode 230 disposed on the surface facing the second direction z, thereby suppressing the solder from wetting up onto the fifth surface 12e.

[0205] The first recess 240a1 and the second recess 242a1 may be connected. By connecting the first recess 240a1 and the second recess 242a1, it is possible to prevent solder from wetting up to the area where two adjacent surfaces intersect. When viewed in the first direction y, the distance from the bottom surface of the first recess 240a1 to the apex of the surface plating layer 36 (described later) that is located outside the first recess 240a1 is preferably 1.0 μm or more.

[0206] When the second external electrode 230b covers the first surface 12a, the fourth surface 12d, and the sixth surface 12f, as viewed in the stacking direction x from the first surface 12a side, the second external electrode 230b has a second recess 242b1 extending in the second direction z on the fourth surface 12d side and a first recess 240b1 extending in the first direction y on the sixth surface 12f side. The rest of the configuration of the second external electrode 230b is similar to that of the first external electrode 230a.

[0207] When the third external electrode 230c covers the first surface 12a, the third surface 12c, and the sixth surface 12f, as viewed in the stacking direction x from the first surface 12a side, the third external electrode 230c has a second recess 242c extending in the second direction z on the third surface 12c side and a first recess 240b extending in the first direction y on the sixth surface 12f side. The other configuration of the third external electrode 230c is similar to that of the first external electrode 230a.

[0208] When the fourth external electrode 230d covers the first surface 12a, the fourth surface 12d, and the fifth surface 12e, as viewed in the stacking direction x from the first surface 12a side, the fourth external electrode 230d has a second recess 242d extending in the second direction z on the fourth surface 12d side and a first recess 240d extending in the first direction y on the fifth surface 12e side. The rest of the configuration of the fourth external electrode 230d is similar to that of the first external electrode 230a.

[0209] Each of the first external electrode 230a, the second external electrode 230b, the third external electrode 230c, and the fourth external electrode 230d preferably has an underlayer 32, a thin film layer 34, and a surface plating layer 36.

[0210] (Underlayer) The underlayer 32 is disposed on the third surface 12c to the sixth surface 12f. The specific configuration of the underlayer 32 will be described below.

[0211] The first underlayer 32a is arranged on the surfaces of the third surface 12c and the fifth surface 12e of the laminate 12 so as to cover the first extraction electrode portion 24a of the first internal electrode 16a exposed from the third surface 12c and the fifth surface 12e of the laminate 12.

[0212] The second underlayer 32b is arranged on the surfaces of the fourth surface 12d and the sixth surface 12f of the laminate 12 so as to cover the second extraction electrode portion 24b of the first internal electrode 16a exposed from the fourth surface 12d and the sixth surface 12f of the laminate 12.

[0213] The third underlayer 32c is arranged on the surfaces of the third surface 12c and the sixth surface 12f of the laminate 12 so as to cover the third extraction electrode portion 24c of the second internal electrode 16b exposed from the third surface 12c and the sixth surface 12f of the laminate 12.

[0214] The fourth base layer 32d is arranged on the surfaces of the fourth surface 12d and the fifth surface 12e of the laminate 12 so as to cover the fourth extraction electrode portion 24d of the second internal electrode 16b exposed from the fourth surface 12d and the fifth surface 12e of the laminate 12.

[0215] The underlayer 32 is preferably made of Cu plating, although this depends on the connectivity with the internal electrodes 16 .

[0216] In addition, it is preferable that the upper end of the first base layer 32a of the first external electrode 230a is connected to the first thin film layer 34a on the ridge formed by the first surface 12a of the laminate 12 and the third surface 12c and the fifth surface 12e.

[0217] As with the first underlayer 32a of the multilayer ceramic capacitor 10, the distance in the stacking direction x between the leading end of the third surface 112c of the first underlayer 32a and the end of the internal electrode 16 closest to the first surface 12a that is exposed on the third surface 12c is preferably 3.0 μm or more and 8.1 μm or less. The first underlayer 32a is preferably disposed so as to extend toward the first surface 12a. In other words, the distance in the stacking direction x between a point on the outermost surface of the first surface 12a located 1.0 μm inward from the third surface 12c and the leading end of the first underlayer 32a in the stacking direction x is preferably 10.0 μm or less. The thickness of the first underlayer 32a is preferably 3.0 μm or more and 8.1 μm or less in the first direction y from the end exposed on the third surface 12c of the internal electrode 16 closest to the first surface 12a.

[0218] The upper end of the second base layer 32b of the second external electrode 230b is preferably connected to the second thin film layer 34b on the ridge formed by the first surface 12a, and the fourth surface 12d and the sixth surface 12f of the laminate 12. The rest of the configuration of the second external electrode 230b is similar to that of the first external electrode 230a.

[0219] The upper end of the third base layer 32c of the third external electrode 230c is preferably connected to the third thin film layer 34c on the ridge formed by the first surface 12a, the third surface 12c, and the sixth surface 12f of the laminate 12. The rest of the configuration of the third external electrode 230c is similar to that of the first external electrode 230a.

[0220] The upper end of the fourth base layer 32d of the fourth external electrode 230d is preferably connected to the fourth thin film layer 34d on the ridge formed by the first surface 12a, and the fourth and fifth surfaces 12d, 12e of the laminate 12. The rest of the configuration of the fourth external electrode 230d is similar to that of the first external electrode 230a.

[0221] (Thin Film Layers) The thin film layers 34 include a first thin film layer 34a, a second thin film layer 34b, a third thin film layer 34c, and a fourth thin film layer 34d.

[0222] The first thin film layer 34a covers a portion of the first surface 12a of the laminate 12 on the third surface 12c side and the fifth surface 12e side. The first thin film layer 34a is preferably disposed in contact with the first base layer 32a.

[0223] The second thin film layer 34b covers a portion of the first surface 12a of the laminate 12 on the fourth surface 12d side and the sixth surface 12f side. The second thin film layer 34b is preferably disposed in contact with the second base layer 32b.

[0224] The third thin film layer 34c covers a portion of the first surface 12a of the laminate 12 on the third surface 12c side and the sixth surface 12f side. The third thin film layer 34c is preferably arranged in contact with the third base layer 32c.

[0225] The fourth thin film layer 34d covers a portion of the first surface 12a of the laminate 12 on the fourth surface 12d side and the fifth surface 12e side. The fourth thin film layer 34d is preferably arranged in contact with the fourth base layer 32d.

[0226] (Surface Plated Layer) The surface plated layer 36 includes a first surface plated layer 36a, a second surface plated layer 36b, a third surface plated layer 36c, and a fourth surface plated layer 36d.

[0227] The first surface plating layer 36a is arranged to cover the first thin film layer 34a and the first underlayer 32a arranged on the third surface 12c and fifth surface 12e of the laminate 12. The second surface plating layer 36b is arranged to cover the second thin film layer 34b and the second underlayer 32b arranged on the fourth surface 12d and sixth surface 12f of the laminate 12. The third surface plating layer 36c is arranged to cover the third thin film layer 34c and the third underlayer 32c arranged on the third surface 12c and sixth surface 12f of the laminate 12. The fourth surface plating layer 36d is arranged to cover the fourth thin film layer 34d and the fourth underlayer 32d arranged on the fourth surface 12d and fifth surface 12e of the laminate 12.

[0228] The surface plating layer 36 may be, for example, only Sn plating, or preferably has a two-layer structure of Ni plating, Sn plating, or Ni plating and Cu plating.

[0229] The Sn plating covers the Ni plating. Specifically, the Sn plating is formed by plating growth starting from the Ni plating. The thickness of the Sn plating is preferably 1.0 μm or more and 5.0 μm or less. Here, the structure of the first surface plating layer 36a of the first external electrode 230a will be described in detail using the first surface plating layer 36a of the first external electrode 230a as an example. As with the surface plating layer 36 of the multilayer ceramic capacitor 10, the first surface plating layer 36a constituting the first external electrode 230a also includes a Ni plating layer and a Sn plating layer. In this case, the relationship between the thickness t4 of the Sn plating disposed in the first recess 240a (or the second recess 242a) and the thickness t5 of the Sn plating disposed at a center position (½) on the first surface 112a at a distance 1 in the second direction z on the first surface 12a side of the first external electrode 230a is preferably |t4-t5|≦t5 / 2. The relationship between the thickness of the Sn plating disposed in the first recess 240a (or the second recess 242a) and the thickness t6 of the Sn plating disposed on the first surface 12a in a region 10 μm from the tip thereof is preferably |t4−t6|≦t6 / 2. The above-described structure of the Sn plating constituting the first surface plating layer 36a included in the first external electrode 230a is also possessed by the Sn plating constituting the second surface plating layer 36b included in the second external electrode 230b, the Sn plating constituting the third surface plating layer 36c included in the third external electrode 230c, and the fourth surface plating layer 36d included in the fourth external electrode 230d.

[0230] The multilayer ceramic capacitor 210 according to the third embodiment shown in Fig. 19A has the same effects as the multilayer ceramic capacitor 10 described above, and also has the following effect: That is, according to the multilayer ceramic capacitor 210 according to the third embodiment shown in Fig. 19A, even in a multilayer ceramic capacitor in which the external electrodes 230 are disposed so as to cover only the first surface 12a of the laminate 12 and not cover the second surface 12b, it is possible to provide a multilayer ceramic capacitor with a reduced height without impairing mountability during mounting, similar to the multilayer ceramic capacitor 10 shown in Fig. 1.

[0231] The multilayer ceramic capacitor 210 according to the third embodiment may be configured such that the external electrodes 230 cover a portion of the second surface 12b and do not cover the first surface 12a.

[0232] 2. Method for Manufacturing a Multilayer Ceramic Capacitor A method for manufacturing a multilayer ceramic capacitor according to the third embodiment will now be described.

[0233] First, a dielectric sheet, a conductive paste for the internal electrodes, and a conductive paste for the peripheral electrodes are prepared. The dielectric sheet, the conductive paste for the internal electrodes, and the conductive paste for the peripheral electrodes contain a binder and a solvent. Known binders and solvents can be used.

[0234] Next, conductive paste for the internal electrodes and conductive paste for the peripheral electrodes are printed in predetermined patterns on the dielectric sheets by, for example, inkjet printing, screen printing, or gravure printing. This prepares a dielectric sheet on which the patterns of the first internal electrodes and the first peripheral electrodes are formed, and a dielectric sheet on which the patterns of the second internal electrodes and the second peripheral electrodes are formed. Thereafter, the sheet on which the patterns of the first internal electrodes and the first peripheral electrodes are printed and the sheet on which the patterns of the second internal electrodes and the second peripheral electrodes are printed are laminated to form the portion that becomes the inner layer portion 18.

[0235] In printing the patterns using each conductive paste, first, the patterns using the conductive paste for the internal electrodes are printed, and then the patterns using the conductive paste for the peripheral electrodes are printed.

[0236] Next, a predetermined number of dielectric sheets not printed with internal electrode patterns or peripheral electrode patterns are stacked to form the portion that will become the first outer layer portion 20a on the first surface 12a. After that, the portion that will become the inner layer portion 18 prepared above is stacked, and a predetermined number of dielectric sheets not printed with internal electrode patterns or peripheral electrode patterns are stacked on top of this portion that will become the inner layer portion 18 to form the portion that will become the second outer layer portion 20b on the second surface 12b. In this way, a laminated sheet is produced.

[0237] Next, the laminated sheet is pressed in the lamination direction by means of a hydrostatic press or the like to produce a laminated block.

[0238] The laminated block is then cut to a predetermined size to cut out laminated chips, the corners and ridges of which may be rounded by barrel polishing or the like.

[0239] Next, the laminated chip is fired to produce the laminate 12. The firing temperature depends on the ceramic and internal electrode materials, but is preferably 900° C. or higher and 1400° C. or lower.

[0240] At this time, the first lead electrode portion 24a of the first internal electrode 16a and the third lead electrode portion 24c of the second internal electrode 16b are exposed from the third surface 12c of the laminate 12. Furthermore, the second lead electrode portion 24b of the first internal electrode 16a and the fourth lead electrode portion 24d of the second internal electrode 16b are exposed from the fourth surface 12d of the laminate 12.

[0241] Subsequently, the external electrodes 230 are formed on the laminate 12 .

[0242] First, an underlayer 32 is formed so as to cover the internal electrodes 16 exposed on the surface of the laminate 12. The underlayer 32 is Cu plated and is formed by electrolytic plating or electroless plating. At this time, the plated laminate 12 is subjected to a heat treatment to remove residual moisture remaining in the plating film and at the interface between the laminate 12 and the underlayer 32.

[0243] Here, after the base layer 32 is formed, predetermined locations on the first surface 12a on the third surface 12c side to the sixth surface 12f side are surface treated, for example, by plasma etching, to form regions for forming the first recess 240 and the second recess 242.

[0244] Next, the laminate 12 on which the underlayer 32 has been formed is aligned on a work table, and the thin film layer 34 is formed on the first surface 12a and the second surface 12b by, for example, sputtering.

[0245] Thereafter, a top plating layer 36 is formed on the thin film layer 34 and the surface of the laminate 12. More specifically, a Ni plating layer and a Sn plating layer are formed on the thin film layer 34 as the top plating layer 36. Either electrolytic plating or electroless plating may be used for the plating process. However, electroless plating has the disadvantage of requiring pretreatment using a catalyst or the like to improve the plating deposition rate, which complicates the process. Therefore, it is usually preferable to use electrolytic plating. However, without being limited to this, after forming the top plating layer, for example, a Ni plating layer may be formed, followed by forming recesses, and then a Sn plating layer may be formed.

[0246] In this manner, the multilayer ceramic capacitor 210 according to the third embodiment shown in FIG. 22 can be manufactured.

[0247] D. Experimental Example Next, in order to confirm the effects of the multilayer ceramic capacitor according to the present invention, solder mounting evaluation was carried out on experimental samples according to the manufacturing method described above.

[0248] (1) Specifications of multilayer ceramic capacitors fabricated as samples for experimental examples Using the manufacturing method according to the above embodiment, multilayer ceramic capacitors, designated as samples No. 1 to No. 15, were fabricated. Note that multilayer ceramic capacitors without recesses were also fabricated as conventional structures. Multilayer ceramic capacitor structure: multilayer ceramic capacitor shown in FIG. 15 Multilayer ceramic capacitor dimensions (L): 480 μm Multilayer ceramic capacitor dimensions (W): 480 μm Multilayer ceramic capacitor dimensions (T): 60 μm Ceramic material: BaTiO3 Internal electrode material: Ni External electrode structure: Underlayer: Cu plating Thin film layer: sputtered film containing at least one of Ni, Cr, and Cu Surface plating layer: two-layer structure of Ni plating layer and Sn plating layer

[0249] (2) Solder Mounting Test Method: An appropriate amount of solder paste was applied to a specified position on the board, and each sample multilayer ceramic capacitor was mounted on top of it. The board with the multilayer ceramic capacitor mounted on it was then heated to complete the soldering. A similar method was used to solder mount the conventional structure without a recess on the board. Evaluation Method: After solder mounting, the height to the outermost surface of the multilayer ceramic capacitor was measured using a laser microscope or the like, relative to the board surface. Similar measurements were also performed on the conventional structure without a recess, and the difference in the amount of solder wetting up was evaluated. In Table 2, x represents the ratio of the length of each recess to the dimension of the external electrode in the first direction y or the dimension in the second direction z.

[0250] (3) Results The evaluation results are shown in Tables 1 and 2. Table 1 shows the change in the difference between the amount of wetting up of solder for each sample and the amount of wetting up of solder for a conventional structure with respect to the change in distance t1. Table 2 shows the change in the difference between the amount of wetting up of solder for each sample and the amount of wetting up of solder for a conventional structure with respect to the change in the ratio of the length of each recess to the dimension of the external electrode in the first direction or the dimension in the second direction.

[0251]

[0252]

[0253] According to Table 1, it was confirmed that the amount of solder wetting and rising was reduced in all samples within the range of 1.0≦t1≦9.0 for Samples 1 to 8. In particular, for Samples 3 to 7, a significant effect of suppressing the amount of solder wetting and rising was observed within the range of 3.0≦t1≦8.1.

[0254] Furthermore, according to Table 2, the amount of solder wetting was reduced for all samples with sample numbers, but it was confirmed that the amount of solder wetting was particularly reduced for sample numbers 12 to 15 within the range of 10.0≦x≦96.0 compared to samples with other sample numbers. It was also confirmed that the amount of solder wetting could be reduced even within the range of x≦100.

[0255] Although the embodiments of the present invention have been disclosed above, the present invention is not limited thereto. In other words, various modifications can be made to the above-described embodiments in terms of mechanism, shape, material, quantity, position, arrangement, etc., without departing from the scope of the technical idea and purpose of the present invention, and such modifications are included in the present invention.

[0256] 10, 110, 210 Multilayer ceramic capacitor 12 Laminate 12a, 112a First surface 12b, 112b Second surface 12c, 112c Third surface 12d, 112d Fourth surface 12e, 112e Fifth surface 12f, 112f Sixth surface 14, 114 Dielectric layer 14a, 114a Inner dielectric layer 14b, 114b Outer dielectric layer 16, 116 Internal electrode 16a, 116a First internal electrode 16b, 116b Second internal electrode 18, 118 Internal layer portion 20a, 120a First outer layer portion 20b, 120b Second outer layer portion 22a, 122a First opposing electrode portion 22b, 122b Second opposing electrode portion 24a, 124a First lead electrode portion 24b, 124b Second lead electrode portion 24c, 124c Third lead electrode portion 24d, 124d Fourth lead electrode portion 26a, 26b, 126a, 126b Side portion of laminate (W gap) 27a, 27b, 127a, 127b End portion of laminate (L gap) 30, 130, 230 External electrodes 30a, 130a, 230a First external electrode 30b, 130b, 230b Second external electrode 30c, 130c, 230c Third external electrode 30d, 130d, 230d Fourth external electrode 32, 132 Underlayer 32a, first underlayer 32b, second underlayer 32c, third underlayer 32d, fourth underlayer 34, 134 Thin film layer 34a, 134a First thin film layer 34b, 134b Second thin film layer 34c, 134c Third thin film layer 34d, 134d Fourth thin film layer 36, 136 Surface plating layer 36a, 136a First surface plating layer 36b, 136b Second surface plating layer 36c, 136c Third surface plating layer 36d, 136d Fourth surface plating layer 40, 140, 240 First recess 42, 142, 242 Second recess x Stacking direction y First direction z Second direction L Dimension of multilayer ceramic capacitor in first direction W Dimension of multilayer ceramic capacitor in second direction T Dimension of multilayer ceramic capacitor in stacking direction

Claims

1. A multilayer ceramic capacitor comprising: a laminate having first and second surfaces opposed to each other in the lamination direction, third and fourth surfaces opposed to each other in a first direction perpendicular to the lamination direction, and fifth and sixth surfaces opposed to each other in a second direction perpendicular to the lamination direction and the first direction; first external electrodes arranged on the first and third surfaces; second external electrodes arranged on the first and third surfaces; a third external electrode arranged on the first and third surfaces; and a fourth external electrode arranged on the first and fourth surfaces, wherein the laminate includes first internal electrodes and second internal electrodes; the first external electrodes include a first base layer connected to the first internal electrodes, a first thin film layer arranged on the first surface, and a first surface plating layer; and the first external electrodes have a first recess located inside the laminate, The first recess has a dimension longer in the second direction than in the first direction.

2. The multilayer ceramic capacitor according to claim 1, wherein the dimension of said first recess in said first direction is 10% or more and 100% or less of the dimension of said first external electrode in said first direction.

3. A multilayer ceramic capacitor according to claim 1 or 2, wherein the first recesses are arranged discontinuously in the first direction.

4. A multilayer ceramic capacitor according to claim 1 or 2, wherein the first recesses are arranged continuously in the first direction.

5. A multilayer ceramic capacitor as described in any one of claims 1 to 4, wherein the distance in the stacking direction from the innermost end of the first underlayer to the outermost surface of the first surface plating layer located outside the innermost end of the first underlayer is 3.0 μm or more and 8.1 μm or less.

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